stats: Update stats for CPU and cache changes

This patch updates the stats to reflect the fixes and changes to the
CPU (mainly the o3), and the caches.

104 files changed, 62695 insertions, 62099 deletions

diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt
index 401e8a630..9abb1e987 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt
@@ -1,123 +1,126 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  1.884209                       # Number of seconds simulated
-sim_ticks                                1884208734500                       # Number of ticks simulated
-final_tick                               1884208734500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  1.883224                       # Number of seconds simulated
+sim_ticks                                1883223940000                       # Number of ticks simulated
+final_tick                               1883223940000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 147223                       # Simulator instruction rate (inst/s)
-host_op_rate                                   147223                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             4942377286                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 320260                       # Number of bytes of host memory used
-host_seconds                                   381.24                       # Real time elapsed on the host
-sim_insts                                    56126572                       # Number of instructions simulated
-sim_ops                                      56126572                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 180615                       # Simulator instruction rate (inst/s)
+host_op_rate                                   180615                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             6060637883                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 316396                       # Number of bytes of host memory used
+host_seconds                                   310.73                       # Real time elapsed on the host
+sim_insts                                    56122642                       # Number of instructions simulated
+sim_ops                                      56122642                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst          25914048                       # Number of bytes read from this memory
-system.physmem.bytes_read::tsunami.ide        2652352                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             28566400                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst      1052800                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         1052800                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7560448                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7560448                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst             404907                       # Number of read requests responded to by this memory
-system.physmem.num_reads::tsunami.ide           41443                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                446350                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          118132                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               118132                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst             13753279                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::tsunami.ide           1407674                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                15160953                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          558749                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             558749                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           4012532                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                4012532                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           4012532                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst            13753279                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::tsunami.ide          1407674                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               19173485                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        446350                       # Number of read requests accepted
-system.physmem.writeReqs                       118132                       # Number of write requests accepted
-system.physmem.readBursts                      446350                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     118132                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 28559040                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      7360                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   7558400                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  28566400                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                7560448                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      115                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytes_read::cpu.inst          25930944                       # Number of bytes read from this memory
+system.physmem.bytes_read::tsunami.ide            960                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             25931904                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst      1052544                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1052544                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      4902720                       # Number of bytes written to this memory
+system.physmem.bytes_written::tsunami.ide      2659328                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7562048                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst             405171                       # Number of read requests responded to by this memory
+system.physmem.num_reads::tsunami.ide              15                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                405186                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           76605                       # Number of write requests responded to by this memory
+system.physmem.num_writes::tsunami.ide          41552                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               118157                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst             13769443                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::tsunami.ide               510                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                13769952                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          558905                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             558905                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           2603365                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::tsunami.ide          1412115                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                4015480                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           2603365                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst            13769443                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::tsunami.ide          1412624                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               17785432                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        405186                       # Number of read requests accepted
+system.physmem.writeReqs                       118157                       # Number of write requests accepted
+system.physmem.readBursts                      405186                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     118157                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 25919424                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     12480                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   7560064                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  25931904                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                7562048                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      195                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs            154                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               28089                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               28219                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               28571                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               28273                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               27775                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               27529                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               27274                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               26987                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               27827                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               27514                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              28065                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              27430                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              27510                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              28401                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              28311                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              28460                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                7814                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs            157                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               25480                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               25741                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               25855                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               25788                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               25233                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               24956                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               24811                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               24586                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               25127                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               25280                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              25532                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              24857                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              24547                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              25588                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              25870                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              25740                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                7812                       # Per bank write bursts
 system.physmem.perBankWrBursts::1                7677                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                8054                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                7732                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                7319                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                6955                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                8067                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                7744                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                7318                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                6954                       # Per bank write bursts
 system.physmem.perBankWrBursts::6                6788                       # Per bank write bursts
 system.physmem.perBankWrBursts::7                6406                       # Per bank write bursts
 system.physmem.perBankWrBursts::8                7235                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                6877                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               7390                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                6889                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               7393                       # Per bank write bursts
 system.physmem.perBankWrBursts::11               6865                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               7046                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               8008                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               7991                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               7943                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               7045                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               8007                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               7989                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               7937                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                           8                       # Number of times write queue was full causing retry
-system.physmem.totGap                    1884200137500                       # Total gap between requests
+system.physmem.numWrRetry                           5                       # Number of times write queue was full causing retry
+system.physmem.totGap                    1883215178500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  446350                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  405186                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 118132                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    402858                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      3909                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                      2828                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                      1301                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                      2032                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                      4354                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                      3935                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                      3963                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                      2519                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                      2152                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                     2122                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                     2100                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                     1643                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                     1621                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                     1890                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                     1850                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                     2123                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                     1201                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                      949                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                      877                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                        8                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 118157                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    402670                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      2243                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        66                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                         1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                         1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                         1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                         1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                         1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
@@ -144,283 +147,274 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     1024                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     1062                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     4664                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     4781                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     4804                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     4807                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     4824                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     4947                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     5088                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     5171                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     5379                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     5611                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     5560                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     5729                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     5781                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     5895                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     5861                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     5917                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      907                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      921                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      954                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      875                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      945                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      993                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                     1067                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      976                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                     1137                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                     1161                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                     1136                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                     1209                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                     1384                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                     1615                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                     1837                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                     2004                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                     1906                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                     1810                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                     1674                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                     1668                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                     1785                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                     1617                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                      827                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                      369                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                      193                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                      127                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       36                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       27                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       21                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       16                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       15                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        65499                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      551.419716                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     340.219574                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     417.619626                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          14326     21.87%     21.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        10638     16.24%     38.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         5049      7.71%     45.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3016      4.60%     50.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2484      3.79%     54.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         2116      3.23%     57.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1384      2.11%     59.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1595      2.44%     62.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        24891     38.00%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          65499                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          6964                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        64.074383                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::gmean       16.502018                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev     2530.928651                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-8191           6961     99.96%     99.96% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::40960-49151            1      0.01%     99.97% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::57344-65535            1      0.01%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::196608-204799            1      0.01%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            6964                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          6964                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        16.958644                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.733261                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        3.741198                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16               5665     81.35%     81.35% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17                 36      0.52%     81.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18                854     12.26%     94.13% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19                 55      0.79%     94.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                 10      0.14%     95.06% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21                 13      0.19%     95.25% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22                 23      0.33%     95.58% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23                 94      1.35%     96.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24                 12      0.17%     97.10% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::25                 41      0.59%     97.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26                 13      0.19%     97.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::27                 17      0.24%     98.12% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28                 13      0.19%     98.31% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::29                 12      0.17%     98.48% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::30                  3      0.04%     98.52% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::31                 21      0.30%     98.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32                  7      0.10%     98.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::33                  2      0.03%     98.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::34                  2      0.03%     98.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::35                  1      0.01%     98.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36                  2      0.03%     99.02% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::37                  3      0.04%     99.07% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::38                  3      0.04%     99.11% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::39                  2      0.03%     99.14% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40                  8      0.11%     99.25% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::41                  7      0.10%     99.35% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::43                  3      0.04%     99.40% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44                  1      0.01%     99.41% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::45                  1      0.01%     99.43% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::46                  1      0.01%     99.44% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::47                  7      0.10%     99.54% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48                  2      0.03%     99.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::49                  1      0.01%     99.58% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::50                  1      0.01%     99.60% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::51                  1      0.01%     99.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52                  4      0.06%     99.67% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::54                  1      0.01%     99.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56                  9      0.13%     99.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::57                  8      0.11%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::58                  4      0.06%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::59                  1      0.01%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            6964                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     7297586750                       # Total ticks spent queuing
-system.physmem.totMemAccLat               15664493000                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   2231175000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       16353.69                       # Average queueing delay per DRAM burst
+system.physmem.wrQLenPdf::15                     1541                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     2210                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     5693                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     5920                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     6144                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     6907                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     7208                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     8408                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     8700                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     8681                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     8384                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     8515                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     7009                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     6582                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     5776                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     5533                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     5557                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     5513                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      225                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      212                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      188                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      177                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      158                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      137                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      112                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      118                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      140                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      127                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      148                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      178                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      193                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      184                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      166                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      173                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      163                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                      137                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                      123                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                      131                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                      125                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                      108                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                      101                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                       82                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                       73                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                       59                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                       46                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                       34                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                       18                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       13                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                       12                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        62955                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      531.800302                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     324.503879                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     415.177975                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          14434     22.93%     22.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        10626     16.88%     39.81% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         4984      7.92%     47.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3035      4.82%     52.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2479      3.94%     56.48% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         2063      3.28%     59.76% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1365      2.17%     61.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1615      2.57%     64.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        22354     35.51%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          62955                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          5310                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        76.265725                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev     2898.384419                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-8191           5307     99.94%     99.94% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::40960-49151            1      0.02%     99.96% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::57344-65535            1      0.02%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::196608-204799            1      0.02%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total            5310                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          5310                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        22.245951                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.963647                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       20.434666                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            4660     87.76%     87.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23              16      0.30%     88.06% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27              15      0.28%     88.34% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31             227      4.27%     92.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35              38      0.72%     93.33% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39               5      0.09%     93.43% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43               8      0.15%     93.58% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47               6      0.11%     93.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51              26      0.49%     94.18% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55               4      0.08%     94.26% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59               5      0.09%     94.35% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67              14      0.26%     94.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71               2      0.04%     94.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75               5      0.09%     94.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83              26      0.49%     95.24% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87               9      0.17%     95.40% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91               5      0.09%     95.50% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95               6      0.11%     95.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99             182      3.43%     99.04% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             6      0.11%     99.15% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111             1      0.02%     99.17% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115             2      0.04%     99.21% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-123             3      0.06%     99.27% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127             2      0.04%     99.30% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131             6      0.11%     99.42% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135             5      0.09%     99.51% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-139             4      0.08%     99.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143             2      0.04%     99.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147             7      0.13%     99.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-155             1      0.02%     99.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159             1      0.02%     99.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-163             5      0.09%     99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179             2      0.04%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::180-183             1      0.02%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::224-227             3      0.06%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            5310                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     2131293750                       # Total ticks spent queuing
+system.physmem.totMemAccLat                9724875000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   2024955000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        5262.57                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  35103.69                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          15.16                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  24012.57                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          13.76                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           4.01                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       15.16                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        4.01                       # Average system write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       13.77                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        4.02                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           0.15                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       0.12                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                           0.14                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       0.11                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.01                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        22.97                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     402726                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     96110                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   90.25                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  81.36                       # Row buffer hit rate for writes
-system.physmem.avgGap                      3337927.76                       # Average gap between requests
-system.physmem.pageHitRate                      88.39                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE     1774702818500                       # Time in different power states
-system.physmem.memoryStateTime::REF       62917660000                       # Time in different power states
+system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        24.54                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     364467                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     95695                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   89.99                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  80.99                       # Row buffer hit rate for writes
+system.physmem.avgGap                      3598433.87                       # Average gap between requests
+system.physmem.pageHitRate                      87.96                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE     1774121817500                       # Time in different power states
+system.physmem.memoryStateTime::REF       62884900000                       # Time in different power states
 system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT       46582219000                       # Time in different power states
+system.physmem.memoryStateTime::ACT       46214912500                       # Time in different power states
 system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.membus.throughput                     19215856                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq              295757                       # Transaction distribution
-system.membus.trans_dist::ReadResp             295741                       # Transaction distribution
-system.membus.trans_dist::WriteReq               9619                       # Transaction distribution
-system.membus.trans_dist::WriteResp              9619                       # Transaction distribution
-system.membus.trans_dist::Writeback            118132                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq              156                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp             156                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            158094                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           158094                       # Transaction distribution
+system.membus.throughput                     17814330                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq              295751                       # Transaction distribution
+system.membus.trans_dist::ReadResp             295735                       # Transaction distribution
+system.membus.trans_dist::WriteReq               9618                       # Transaction distribution
+system.membus.trans_dist::WriteResp              9618                       # Transaction distribution
+system.membus.trans_dist::Writeback             76605                       # Transaction distribution
+system.membus.trans_dist::WriteInvalidateReq        41552                       # Transaction distribution
+system.membus.trans_dist::WriteInvalidateResp        41552                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq              157                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp             157                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            116539                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           116539                       # Transaction distribution
 system.membus.trans_dist::BadAddressError           16                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave        33098                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       887017                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave        33096                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       887261                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio           32                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total       920147                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       124680                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       124680                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1044827                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave        44316                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     30817728                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total     30862044                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port      5309120                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::total      5309120                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total            36171164                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus               36171164                       # Total data (bytes)
-system.membus.snoop_data_through_bus            35520                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy            29834000                       # Layer occupancy (ticks)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total       920389                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        83292                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total        83292                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                1003681                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave        44308                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     30833664                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total     30877972                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port      2660288                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.iocache.mem_side::total      2660288                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total            33538260                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus               33538260                       # Total data (bytes)
+system.membus.snoop_data_through_bus            10112                       # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy            29840000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy          1588295250                       # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy          1547069500                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.1                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy               22000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy               19500                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         3825084824                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         3825068843                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
-system.membus.respLayer2.occupancy          376625999                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy           43112000                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
 system.iocache.tags.replacements                41685                       # number of replacements
-system.iocache.tags.tagsinuse                1.295855                       # Cycle average of tags in use
+system.iocache.tags.tagsinuse                1.288165                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs                41701                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         1728026399000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::tsunami.ide     1.295855                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::tsunami.ide     0.080991                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.080991                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         1728026235000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::tsunami.ide     1.288165                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::tsunami.ide     0.080510                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.080510                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses               375525                       # Number of tag accesses
-system.iocache.tags.data_accesses              375525                       # Number of data accesses
+system.iocache.tags.tag_accesses               375533                       # Number of tag accesses
+system.iocache.tags.data_accesses              375533                       # Number of data accesses
+system.iocache.WriteInvalidateReq_hits::tsunami.ide        41552                       # number of WriteInvalidateReq hits
+system.iocache.WriteInvalidateReq_hits::total        41552                       # number of WriteInvalidateReq hits
 system.iocache.ReadReq_misses::tsunami.ide          173                       # number of ReadReq misses
 system.iocache.ReadReq_misses::total              173                       # number of ReadReq misses
-system.iocache.WriteReq_misses::tsunami.ide        41552                       # number of WriteReq misses
-system.iocache.WriteReq_misses::total           41552                       # number of WriteReq misses
-system.iocache.demand_misses::tsunami.ide        41725                       # number of demand (read+write) misses
-system.iocache.demand_misses::total             41725                       # number of demand (read+write) misses
-system.iocache.overall_misses::tsunami.ide        41725                       # number of overall misses
-system.iocache.overall_misses::total            41725                       # number of overall misses
-system.iocache.ReadReq_miss_latency::tsunami.ide     21134133                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     21134133                       # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency::tsunami.ide  12414876231                       # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_latency::total  12414876231                       # number of WriteReq miss cycles
-system.iocache.demand_miss_latency::tsunami.ide  12436010364                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total  12436010364                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::tsunami.ide  12436010364                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total  12436010364                       # number of overall miss cycles
+system.iocache.WriteInvalidateReq_misses::tsunami.ide            1                       # number of WriteInvalidateReq misses
+system.iocache.WriteInvalidateReq_misses::total            1                       # number of WriteInvalidateReq misses
+system.iocache.demand_misses::tsunami.ide          173                       # number of demand (read+write) misses
+system.iocache.demand_misses::total               173                       # number of demand (read+write) misses
+system.iocache.overall_misses::tsunami.ide          173                       # number of overall misses
+system.iocache.overall_misses::total              173                       # number of overall misses
+system.iocache.ReadReq_miss_latency::tsunami.ide     21132383                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     21132383                       # number of ReadReq miss cycles
+system.iocache.demand_miss_latency::tsunami.ide     21132383                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total     21132383                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::tsunami.ide     21132383                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total     21132383                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::tsunami.ide          173                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            173                       # number of ReadReq accesses(hits+misses)
-system.iocache.WriteReq_accesses::tsunami.ide        41552                       # number of WriteReq accesses(hits+misses)
-system.iocache.WriteReq_accesses::total         41552                       # number of WriteReq accesses(hits+misses)
-system.iocache.demand_accesses::tsunami.ide        41725                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total           41725                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::tsunami.ide        41725                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total          41725                       # number of overall (read+write) accesses
+system.iocache.WriteInvalidateReq_accesses::tsunami.ide        41553                       # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::total        41553                       # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.demand_accesses::tsunami.ide          173                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total             173                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::tsunami.ide          173                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total            173                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
-system.iocache.WriteReq_miss_rate::tsunami.ide            1                       # miss rate for WriteReq accesses
-system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide     0.000024                       # miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::total     0.000024                       # miss rate for WriteInvalidateReq accesses
 system.iocache.demand_miss_rate::tsunami.ide            1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122162.618497                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 122162.618497                       # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::tsunami.ide 298779.270095                       # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total 298779.270095                       # average WriteReq miss latency
-system.iocache.demand_avg_miss_latency::tsunami.ide 298046.982960                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 298046.982960                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::tsunami.ide 298046.982960                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 298046.982960                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs        364154                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122152.502890                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 122152.502890                       # average ReadReq miss latency
+system.iocache.demand_avg_miss_latency::tsunami.ide 122152.502890                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 122152.502890                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::tsunami.ide 122152.502890                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 122152.502890                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                28275                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs    12.879010                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.fast_writes                          0                       # number of fast writes performed
+system.iocache.fast_writes                      41552                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.writebacks::writebacks           41512                       # number of writebacks
-system.iocache.writebacks::total                41512                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::tsunami.ide          173                       # number of ReadReq MSHR misses
 system.iocache.ReadReq_mshr_misses::total          173                       # number of ReadReq MSHR misses
-system.iocache.WriteReq_mshr_misses::tsunami.ide        41552                       # number of WriteReq MSHR misses
-system.iocache.WriteReq_mshr_misses::total        41552                       # number of WriteReq MSHR misses
-system.iocache.demand_mshr_misses::tsunami.ide        41725                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total        41725                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::tsunami.ide        41725                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total        41725                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     12137133                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     12137133                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::tsunami.ide  10251971233                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::total  10251971233                       # number of WriteReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::tsunami.ide  10264108366                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total  10264108366                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::tsunami.ide  10264108366                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total  10264108366                       # number of overall MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide        41552                       # number of WriteInvalidateReq MSHR misses
+system.iocache.WriteInvalidateReq_mshr_misses::total        41552                       # number of WriteInvalidateReq MSHR misses
+system.iocache.demand_mshr_misses::tsunami.ide          173                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total          173                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::tsunami.ide          173                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total          173                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     12135383                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     12135383                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide   2514597305                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::total   2514597305                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::tsunami.ide     12135383                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total     12135383                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::tsunami.ide     12135383                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total     12135383                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
-system.iocache.WriteReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteReq accesses
-system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
+system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide     0.999976                       # mshr miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_mshr_miss_rate::total     0.999976                       # mshr miss rate for WriteInvalidateReq accesses
 system.iocache.demand_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for demand accesses
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70156.838150                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 70156.838150                       # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 246726.300371                       # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total 246726.300371                       # average WriteReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 245994.208892                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 245994.208892                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 245994.208892                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 245994.208892                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70146.722543                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 70146.722543                       # average ReadReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 60516.877768                       # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60516.877768                       # average WriteInvalidateReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70146.722543                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 70146.722543                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70146.722543                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 70146.722543                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
@@ -434,36 +428,36 @@ system.disk2.dma_read_txs                           0                       # Nu
 system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
 system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
 system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
-system.cpu.branchPred.lookups                14968340                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          12984271                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            377638                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             10101234                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                 5190890                       # Number of BTB hits
+system.cpu.branchPred.lookups                14964215                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          12981470                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            376025                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             10003487                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                 5188980                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             51.388672                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                  808188                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect              32062                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             51.871712                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                  807651                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect              32040                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                      9240282                       # DTB read hits
-system.cpu.dtb.read_misses                      17901                       # DTB read misses
+system.cpu.dtb.read_hits                      9238395                       # DTB read hits
+system.cpu.dtb.read_misses                      17814                       # DTB read misses
 system.cpu.dtb.read_acv                           211                       # DTB read access violations
-system.cpu.dtb.read_accesses                   766280                       # DTB read accesses
-system.cpu.dtb.write_hits                     6385567                       # DTB write hits
-system.cpu.dtb.write_misses                      2310                       # DTB write misses
+system.cpu.dtb.read_accesses                   766068                       # DTB read accesses
+system.cpu.dtb.write_hits                     6385066                       # DTB write hits
+system.cpu.dtb.write_misses                      2311                       # DTB write misses
 system.cpu.dtb.write_acv                          159                       # DTB write access violations
-system.cpu.dtb.write_accesses                  298488                       # DTB write accesses
-system.cpu.dtb.data_hits                     15625849                       # DTB hits
-system.cpu.dtb.data_misses                      20211                       # DTB misses
+system.cpu.dtb.write_accesses                  298441                       # DTB write accesses
+system.cpu.dtb.data_hits                     15623461                       # DTB hits
+system.cpu.dtb.data_misses                      20125                       # DTB misses
 system.cpu.dtb.data_acv                           370                       # DTB access violations
-system.cpu.dtb.data_accesses                  1064768                       # DTB accesses
-system.cpu.itb.fetch_hits                     4001359                       # ITB hits
-system.cpu.itb.fetch_misses                      6809                       # ITB misses
-system.cpu.itb.fetch_acv                          657                       # ITB acv
-system.cpu.itb.fetch_accesses                 4008168                       # ITB accesses
+system.cpu.dtb.data_accesses                  1064509                       # DTB accesses
+system.cpu.itb.fetch_hits                     4000795                       # ITB hits
+system.cpu.itb.fetch_misses                      6874                       # ITB misses
+system.cpu.itb.fetch_acv                          703                       # ITB acv
+system.cpu.itb.fetch_accesses                 4007669                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -476,39 +470,39 @@ system.cpu.itb.data_hits                            0                       # DT
 system.cpu.itb.data_misses                          0                       # DTB misses
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
-system.cpu.numCycles                        176815826                       # number of cpu cycles simulated
+system.cpu.numCycles                        176776474                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                    56126572                       # Number of instructions committed
-system.cpu.committedOps                      56126572                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                       2538059                       # Number of ops (including micro ops) which were discarded before commit
-system.cpu.numFetchSuspends                      5497                       # Number of times Execute suspended instruction fetching
-system.cpu.quiesceCycles                   3593513250                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.cpi                               3.150305                       # CPI: cycles per instruction
-system.cpu.ipc                               0.317430                       # IPC: instructions per cycle
+system.cpu.committedInsts                    56122642                       # Number of instructions committed
+system.cpu.committedOps                      56122642                       # Number of ops (including micro ops) committed
+system.cpu.discardedOps                       2532635                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.numFetchSuspends                      5494                       # Number of times Execute suspended instruction fetching
+system.cpu.quiesceCycles                   3591582755                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.cpi                               3.149825                       # CPI: cycles per instruction
+system.cpu.ipc                               0.317478                       # IPC: instructions per cycle
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.quiesce                     6380                       # number of quiesce instructions executed
-system.cpu.kern.inst.hwrei                     211465                       # number of hwrei instructions executed
-system.cpu.kern.ipl_count::0                    74787     40.94%     40.94% # number of times we switched to this ipl
+system.cpu.kern.inst.quiesce                     6375                       # number of quiesce instructions executed
+system.cpu.kern.inst.hwrei                     211451                       # number of hwrei instructions executed
+system.cpu.kern.ipl_count::0                    74783     40.94%     40.94% # number of times we switched to this ipl
 system.cpu.kern.ipl_count::21                     131      0.07%     41.01% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::22                    1901      1.04%     42.05% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::31                  105856     57.95%    100.00% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::total               182675                       # number of times we switched to this ipl
-system.cpu.kern.ipl_good::0                     73420     49.32%     49.32% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_count::22                    1900      1.04%     42.05% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::31                  105851     57.95%    100.00% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::total               182665                       # number of times we switched to this ipl
+system.cpu.kern.ipl_good::0                     73416     49.32%     49.32% # number of times we switched to this ipl from a different ipl
 system.cpu.kern.ipl_good::21                      131      0.09%     49.41% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::22                     1901      1.28%     50.68% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::31                    73420     49.32%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::total                148872                       # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_ticks::0             1833844528000     97.33%     97.33% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::21                80077500      0.00%     97.33% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::22               673181000      0.04%     97.37% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::31             49609971000      2.63%    100.00% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::total         1884207757500                       # number of cycles we spent at this ipl
-system.cpu.kern.ipl_used::0                  0.981721                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_good::22                     1900      1.28%     50.68% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::31                    73416     49.32%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::total                148863                       # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_ticks::0             1832860357500     97.33%     97.33% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::21                80169000      0.00%     97.33% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::22               672803000      0.04%     97.37% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::31             49609630000      2.63%    100.00% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::total         1883222959500                       # number of cycles we spent at this ipl
+system.cpu.kern.ipl_used::0                  0.981720                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.ipl_used::21                        1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.ipl_used::22                        1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::31                 0.693584                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::total              0.814956                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used::31                 0.693579                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used::total              0.814951                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.syscall::2                          8      2.45%      2.45% # number of syscalls executed
 system.cpu.kern.syscall::3                         30      9.20%     11.66% # number of syscalls executed
 system.cpu.kern.syscall::4                          4      1.23%     12.88% # number of syscalls executed
@@ -544,35 +538,35 @@ system.cpu.kern.callpal::cserve                     1      0.00%      0.00% # nu
 system.cpu.kern.callpal::wrmces                     1      0.00%      0.00% # number of callpals executed
 system.cpu.kern.callpal::wrfen                      1      0.00%      0.00% # number of callpals executed
 system.cpu.kern.callpal::wrvptptr                   1      0.00%      0.00% # number of callpals executed
-system.cpu.kern.callpal::swpctx                  4177      2.17%      2.17% # number of callpals executed
+system.cpu.kern.callpal::swpctx                  4174      2.17%      2.17% # number of callpals executed
 system.cpu.kern.callpal::tbi                       54      0.03%      2.20% # number of callpals executed
 system.cpu.kern.callpal::wrent                      7      0.00%      2.20% # number of callpals executed
-system.cpu.kern.callpal::swpipl                175516     91.22%     93.43% # number of callpals executed
-system.cpu.kern.callpal::rdps                    6804      3.54%     96.96% # number of callpals executed
-system.cpu.kern.callpal::wrkgp                      1      0.00%     96.96% # number of callpals executed
+system.cpu.kern.callpal::swpipl                175508     91.23%     93.43% # number of callpals executed
+system.cpu.kern.callpal::rdps                    6803      3.54%     96.96% # number of callpals executed
+system.cpu.kern.callpal::wrkgp                      1      0.00%     96.97% # number of callpals executed
 system.cpu.kern.callpal::wrusp                      7      0.00%     96.97% # number of callpals executed
 system.cpu.kern.callpal::rdusp                      9      0.00%     96.97% # number of callpals executed
 system.cpu.kern.callpal::whami                      2      0.00%     96.97% # number of callpals executed
-system.cpu.kern.callpal::rti                     5126      2.66%     99.64% # number of callpals executed
+system.cpu.kern.callpal::rti                     5125      2.66%     99.64% # number of callpals executed
 system.cpu.kern.callpal::callsys                  515      0.27%     99.91% # number of callpals executed
 system.cpu.kern.callpal::imb                      181      0.09%    100.00% # number of callpals executed
-system.cpu.kern.callpal::total                 192403                       # number of callpals executed
+system.cpu.kern.callpal::total                 192390                       # number of callpals executed
 system.cpu.kern.mode_switch::kernel              5869                       # number of protection mode switches
-system.cpu.kern.mode_switch::user                1735                       # number of protection mode switches
-system.cpu.kern.mode_switch::idle                2100                       # number of protection mode switches
-system.cpu.kern.mode_good::kernel                1905                      
-system.cpu.kern.mode_good::user                  1735                      
-system.cpu.kern.mode_good::idle                   170                      
-system.cpu.kern.mode_switch_good::kernel     0.324587                       # fraction of useful protection mode switches
+system.cpu.kern.mode_switch::user                1741                       # number of protection mode switches
+system.cpu.kern.mode_switch::idle                2096                       # number of protection mode switches
+system.cpu.kern.mode_good::kernel                1910                      
+system.cpu.kern.mode_good::user                  1741                      
+system.cpu.kern.mode_good::idle                   169                      
+system.cpu.kern.mode_switch_good::kernel     0.325439                       # fraction of useful protection mode switches
 system.cpu.kern.mode_switch_good::user              1                       # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::idle       0.080952                       # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::total      0.392622                       # fraction of useful protection mode switches
-system.cpu.kern.mode_ticks::kernel        36214076000      1.92%      1.92% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::user           4058025000      0.22%      2.14% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::idle         1843935646500     97.86%    100.00% # number of ticks spent at the given mode
-system.cpu.kern.swap_context                     4178                       # number of times the context was actually changed
-system.cpu.tickCycles                        85802593                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                        91013233                       # Total number of cycles that the object has spent stopped
+system.cpu.kern.mode_switch_good::idle       0.080630                       # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good::total      0.393571                       # fraction of useful protection mode switches
+system.cpu.kern.mode_ticks::kernel        36245351000      1.92%      1.92% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::user           4057630500      0.22%      2.14% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::idle         1842919968000     97.86%    100.00% # number of ticks spent at the given mode
+system.cpu.kern.swap_context                     4175                       # number of times the context was actually changed
+system.cpu.tickCycles                        85798616                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                        90977858                       # Total number of cycles that the object has spent stopped
 system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
 system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
 system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
@@ -604,12 +598,13 @@ system.tsunami.ethernet.totalRxOrn                  0                       # to
 system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
 system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
 system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
-system.iobus.throughput                       1436106                       # Throughput (bytes/s)
+system.iobus.throughput                       1436853                       # Throughput (bytes/s)
 system.iobus.trans_dist::ReadReq                 7103                       # Transaction distribution
 system.iobus.trans_dist::ReadResp                7103                       # Transaction distribution
-system.iobus.trans_dist::WriteReq               51171                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              51171                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio         5094                       # Packet count per connected master and slave (bytes)
+system.iobus.trans_dist::WriteReq               51169                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              51170                       # Transaction distribution
+system.iobus.trans_dist::WriteInvalidateReq            1                       # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio         5092                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio          472                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio           10                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio           10                       # Packet count per connected master and slave (bytes)
@@ -621,11 +616,11 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf
 system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio          102                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf          180                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total        33098                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total        33096                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side        83450                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.tsunami.ide.dma::total        83450                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  116548                       # Packet count per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio        20376                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count::total                  116546                       # Packet count per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio        20368                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio         1888                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio            5                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio            5                       # Cumulative packet size per connected master and slave (bytes)
@@ -637,12 +632,12 @@ system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf
 system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio          204                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf          299                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::total        44316                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::total        44308                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      2661608                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.tsunami.ide.dma::total      2661608                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::total              2705924                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.data_through_bus                 2705924                       # Total data (bytes)
-system.iobus.reqLayer0.occupancy              4705000                       # Layer occupancy (ticks)
+system.iobus.tot_pkt_size::total              2705916                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.data_through_bus                 2705916                       # Total data (bytes)
+system.iobus.reqLayer0.occupancy              4703000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy               353000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
@@ -664,66 +659,66 @@ system.iobus.reqLayer27.occupancy               76000                       # La
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer28.occupancy              110000                       # Layer occupancy (ticks)
 system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer29.occupancy           380105365                       # Layer occupancy (ticks)
+system.iobus.reqLayer29.occupancy           374409688                       # Layer occupancy (ticks)
 system.iobus.reqLayer29.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer30.occupancy               30000                       # Layer occupancy (ticks)
 system.iobus.reqLayer30.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy            23479000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy            23478000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer1.occupancy            43180001                       # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy            42012000                       # Layer occupancy (ticks)
 system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
-system.cpu.icache.tags.replacements           1458006                       # number of replacements
-system.cpu.icache.tags.tagsinuse           509.628197                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            18953120                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs           1458517                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             12.994789                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle       31559763000                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   509.628197                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.995368                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.995368                       # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements           1458007                       # number of replacements
+system.cpu.icache.tags.tagsinuse           509.627041                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            18950160                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs           1458518                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             12.992750                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle       31562091250                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   509.627041                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.995365                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.995365                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          104                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1           21                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          103                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           22                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::2          386                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          21870509                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         21870509                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     18953123                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        18953123                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      18953123                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         18953123                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     18953123                       # number of overall hits
-system.cpu.icache.overall_hits::total        18953123                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst      1458693                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total       1458693                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst      1458693                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total        1458693                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst      1458693                       # number of overall misses
-system.cpu.icache.overall_misses::total       1458693                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  20024605540                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  20024605540                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  20024605540                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  20024605540                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  20024605540                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  20024605540                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     20411816                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     20411816                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     20411816                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     20411816                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     20411816                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     20411816                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.071463                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.071463                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.071463                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.071463                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.071463                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.071463                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13727.772424                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13727.772424                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13727.772424                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13727.772424                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13727.772424                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13727.772424                       # average overall miss latency
+system.cpu.icache.tags.tag_accesses          21867553                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         21867553                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     18950163                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        18950163                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      18950163                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         18950163                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     18950163                       # number of overall hits
+system.cpu.icache.overall_hits::total        18950163                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst      1458695                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total       1458695                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst      1458695                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total        1458695                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst      1458695                       # number of overall misses
+system.cpu.icache.overall_misses::total       1458695                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  20021954296                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  20021954296                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  20021954296                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  20021954296                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  20021954296                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  20021954296                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     20408858                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     20408858                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     20408858                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     20408858                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     20408858                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     20408858                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.071474                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.071474                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.071474                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.071474                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.071474                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.071474                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13725.936057                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13725.936057                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13725.936057                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13725.936057                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13725.936057                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13725.936057                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -732,142 +727,143 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1458693                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total      1458693                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst      1458693                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total      1458693                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst      1458693                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total      1458693                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  17099831460                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  17099831460                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst  17099831460                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total  17099831460                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst  17099831460                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total  17099831460                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.071463                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.071463                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.071463                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.071463                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.071463                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.071463                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11722.707561                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11722.707561                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11722.707561                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 11722.707561                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11722.707561                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 11722.707561                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1458695                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total      1458695                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst      1458695                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total      1458695                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst      1458695                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total      1458695                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  17097209704                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total  17097209704                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst  17097209704                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total  17097209704                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst  17097209704                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total  17097209704                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.071474                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.071474                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.071474                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.071474                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.071474                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.071474                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11720.894158                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11720.894158                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11720.894158                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 11720.894158                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11720.894158                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 11720.894158                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.throughput               125457945                       # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq        2557417                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       2557383                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteReq          9619                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteResp         9619                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback       838210                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq           22                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp           22                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       345773                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       304222                       # Transaction distribution
+system.cpu.toL2Bus.throughput               126942050                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq        2557486                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       2557452                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteReq          9618                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteResp         9618                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback       838282                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteInvalidateReq        41557                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq           24                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp           24                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       304264                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       304264                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::BadAddressError           16                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2917325                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      3663192                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           6580517                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     93352448                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    143032604                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total      236385052                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus         236375068                       # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus        13888                       # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy     2697678498                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2917328                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      3663485                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           6580813                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     93352512                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    143044180                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total      236396692                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus         236386772                       # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus      2673536                       # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy     2697842997                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy       234000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.occupancy       232500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy    2191733540                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy    2191719796                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    2194708666                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    2194901157                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
-system.cpu.l2cache.tags.replacements           339421                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        65326.541432                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            2981708                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           404583                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             7.369830                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements           339412                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        65326.749870                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            2981869                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           404575                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             7.370374                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle       5872511750                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 54488.510247                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 10838.031185                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.831429                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.165375                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.996804                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        65162                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          230                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1         1468                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         5155                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         2781                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        55528                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.994293                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         30250697                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        30250697                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst      2261599                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        2261599                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks       838210                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total       838210                       # number of Writeback hits
+system.cpu.l2cache.tags.occ_blocks::writebacks 54484.622776                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 10842.127094                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.831369                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.165438                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.996807                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        65163                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          231                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1         1459                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         5166                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         2777                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        55530                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.994308                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         30252211                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        30252211                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.inst      2261673                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total        2261673                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks       838282                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total       838282                       # number of Writeback hits
 system.cpu.l2cache.UpgradeReq_hits::cpu.inst            4                       # number of UpgradeReq hits
 system.cpu.l2cache.UpgradeReq_hits::total            4                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.inst       187541                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       187541                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst      2449140                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         2449140                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst      2449140                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        2449140                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst       288654                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total       288654                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.inst           18                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total           18                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.inst       116680                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       116680                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst       405334                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        405334                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst       405334                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       405334                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst  18918477985                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total  18918477985                       # number of ReadReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.inst       214497                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total       214497                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst   8091487855                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   8091487855                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst  27009965840                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  27009965840                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst  27009965840                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  27009965840                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst      2550253                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total      2550253                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks       838210                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total       838210                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.inst           22                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total           22                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.inst       304221                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       304221                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst      2854474                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      2854474                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst      2854474                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      2854474                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.113186                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.113186                       # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.inst     0.818182                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.818182                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst     0.383537                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.383537                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.142000                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.142000                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.142000                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.142000                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65540.328507                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 65540.328507                       # average ReadReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.inst 11916.500000                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11916.500000                       # average UpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69347.684736                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69347.684736                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66636.319282                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 66636.319282                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66636.319282                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 66636.319282                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_hits::cpu.inst       187588                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       187588                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst      2449261                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         2449261                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst      2449261                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        2449261                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst       288648                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total       288648                       # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.inst           20                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total           20                       # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.inst       116676                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       116676                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst       405324                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        405324                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst       405324                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       405324                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst  18909912500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total  18909912500                       # number of ReadReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::cpu.inst       115495                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::total       115495                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst   8088441363                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   8088441363                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst  26998353863                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  26998353863                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst  26998353863                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  26998353863                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst      2550321                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total      2550321                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks       838282                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total       838282                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.inst           24                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total           24                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.inst       304264                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       304264                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst      2854585                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      2854585                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst      2854585                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      2854585                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.113181                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.113181                       # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.inst     0.833333                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total     0.833333                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst     0.383470                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.383470                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.141991                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.141991                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.141991                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.141991                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65512.016366                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 65512.016366                       # average ReadReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.inst  5774.750000                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total  5774.750000                       # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69323.951481                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69323.951481                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66609.314679                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 66609.314679                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66609.314679                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 66609.314679                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -876,54 +872,54 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        76620                       # number of writebacks
-system.cpu.l2cache.writebacks::total            76620                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst       288654                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total       288654                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.inst           18                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total           18                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst       116680                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       116680                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst       405334                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       405334                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst       405334                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       405334                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst  15309737015                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total  15309737015                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.inst       281515                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       281515                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst   6590751145                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   6590751145                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst  21900488160                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  21900488160                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst  21900488160                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  21900488160                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst   1333191500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   1333191500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.inst   1887604500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   1887604500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst   3220796000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total   3220796000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.113186                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.113186                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.inst     0.818182                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.818182                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst     0.383537                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.383537                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.142000                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.142000                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.142000                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.142000                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53038.367786                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53038.367786                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.inst 15639.722222                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15639.722222                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 56485.697163                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56485.697163                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54030.720739                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54030.720739                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54030.720739                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54030.720739                       # average overall mshr miss latency
+system.cpu.l2cache.writebacks::writebacks        76605                       # number of writebacks
+system.cpu.l2cache.writebacks::total            76605                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst       288648                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total       288648                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.inst           20                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total           20                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst       116676                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       116676                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst       405324                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       405324                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst       405324                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       405324                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst  15301161000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total  15301161000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.inst       201018                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       201018                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst   6587763637                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   6587763637                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst  21888924637                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  21888924637                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst  21888924637                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  21888924637                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst   1333222000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   1333222000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.inst   1887374000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   1887374000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst   3220596000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total   3220596000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.113181                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.113181                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.inst     0.833333                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.833333                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst     0.383470                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.383470                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.141991                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.141991                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.141991                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.141991                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53009.759292                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53009.759292                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.inst 10050.900000                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10050.900000                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 56462.028498                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56462.028498                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54003.524679                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54003.524679                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54003.524679                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54003.524679                       # average overall mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average WriteReq mshr uncacheable latency
@@ -931,86 +927,86 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements           1395313                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.982337                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            13766743                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           1395825                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs              9.862800                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.replacements           1395422                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.982303                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            13764943                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           1395934                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs              9.860741                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle          86814250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.inst   511.982337                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.inst     0.999966                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999966                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.inst   511.982303                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.inst     0.999965                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999965                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          231                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          234                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          232                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          233                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::2           47                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          63632966                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         63632966                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.inst      7808132                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total         7808132                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.inst      5576867                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        5576867                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.inst       182710                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       182710                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.inst       198999                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total       198999                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.inst      13384999                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         13384999                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.inst     13384999                       # number of overall hits
-system.cpu.dcache.overall_hits::total        13384999                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.inst      1201593                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       1201593                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.inst       573675                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       573675                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.inst        17309                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total        17309                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.inst      1775268                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        1775268                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.inst      1775268                       # number of overall misses
-system.cpu.dcache.overall_misses::total       1775268                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.inst  31027712510                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  31027712510                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.inst  20753893806                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  20753893806                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.inst    231648000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total    231648000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.inst  51781606316                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  51781606316                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.inst  51781606316                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  51781606316                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.inst      9009725                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total      9009725                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.inst      6150542                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total      6150542                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.inst       200019                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total       200019                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.inst       198999                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total       198999                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.inst     15160267                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     15160267                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.inst     15160267                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     15160267                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.inst     0.133366                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.133366                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.inst     0.093272                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.093272                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.inst     0.086537                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.086537                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.inst     0.117100                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.117100                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.inst     0.117100                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.117100                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 25822.148190                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 25822.148190                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 36177.092964                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 36177.092964                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.inst 13383.095499                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13383.095499                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.inst 29168.331945                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 29168.331945                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.inst 29168.331945                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 29168.331945                       # average overall miss latency
+system.cpu.dcache.tags.tag_accesses          63626016                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         63626016                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.inst      7806784                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total         7806784                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.inst      5576432                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        5576432                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.inst       182707                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total       182707                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.inst       198983                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total       198983                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.inst      13383216                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         13383216                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.inst     13383216                       # number of overall hits
+system.cpu.dcache.overall_hits::total        13383216                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.inst      1201616                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       1201616                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.inst       573699                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       573699                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.inst        17299                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total        17299                       # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.inst      1775315                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        1775315                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.inst      1775315                       # number of overall misses
+system.cpu.dcache.overall_misses::total       1775315                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.inst  31018318500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  31018318500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.inst  20748316044                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  20748316044                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.inst    231689250                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total    231689250                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.inst  51766634544                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  51766634544                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.inst  51766634544                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  51766634544                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.inst      9008400                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total      9008400                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.inst      6150131                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total      6150131                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.inst       200006                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total       200006                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.inst       198983                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total       198983                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.inst     15158531                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     15158531                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.inst     15158531                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     15158531                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.inst     0.133388                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.133388                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.inst     0.093282                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.093282                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.inst     0.086492                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.086492                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.inst     0.117117                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.117117                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.inst     0.117117                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.117117                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 25813.836117                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 25813.836117                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 36165.857085                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 36165.857085                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.inst 13393.216371                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13393.216371                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.inst 29159.126433                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 29159.126433                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.inst 29159.126433                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 29159.126433                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -1019,64 +1015,64 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       838210                       # number of writebacks
-system.cpu.dcache.writebacks::total            838210                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.inst       127240                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       127240                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.inst       269470                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       269470                       # number of WriteReq MSHR hits
+system.cpu.dcache.writebacks::writebacks       838282                       # number of writebacks
+system.cpu.dcache.writebacks::total            838282                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.inst       127187                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       127187                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.inst       269448                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       269448                       # number of WriteReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.inst            3                       # number of LoadLockedReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::total            3                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.inst       396710                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       396710                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.inst       396710                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       396710                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.inst      1074353                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      1074353                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.inst       304205                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       304205                       # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.inst        17306                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total        17306                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.inst      1378558                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      1378558                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.inst      1378558                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      1378558                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst  26912219745                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  26912219745                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst  10275413589                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  10275413589                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.inst    196866500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    196866500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.inst  37187633334                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  37187633334                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.inst  37187633334                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  37187633334                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.inst   1423283000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   1423283000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.inst   2003033000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2003033000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.inst   3426316000                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total   3426316000                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst     0.119244                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.119244                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst     0.049460                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.049460                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.inst     0.086522                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.086522                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.inst     0.090932                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.090932                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.inst     0.090932                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.090932                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 25049.699442                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25049.699442                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 33777.924719                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33777.924719                       # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.inst 11375.621172                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11375.621172                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 26975.748089                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 26975.748089                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 26975.748089                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 26975.748089                       # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_hits::cpu.inst       396635                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       396635                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.inst       396635                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       396635                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.inst      1074429                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      1074429                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.inst       304251                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       304251                       # number of WriteReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.inst        17296                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total        17296                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.inst      1378680                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      1378680                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.inst      1378680                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      1378680                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst  26906996250                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  26906996250                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst  10272860843                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  10272860843                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.inst    196930250                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    196930250                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.inst  37179857093                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  37179857093                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.inst  37179857093                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  37179857093                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.inst   1423313500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   1423313500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.inst   2002790500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2002790500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.inst   3426104000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total   3426104000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst     0.119270                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.119270                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst     0.049471                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.049471                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.inst     0.086477                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.086477                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.inst     0.090951                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.090951                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.inst     0.090951                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.090951                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 25043.065898                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25043.065898                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 33764.427538                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33764.427538                       # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.inst 11385.884019                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11385.884019                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 26967.720641                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 26967.720641                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 26967.720641                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 26967.720641                       # average overall mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average WriteReq mshr uncacheable latency
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
index 2b53a578a..683e407e9 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
@@ -1,138 +1,141 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  1.906207                       # Number of seconds simulated
-sim_ticks                                1906207240000                       # Number of ticks simulated
-final_tick                               1906207240000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  1.903124                       # Number of seconds simulated
+sim_ticks                                1903123778500                       # Number of ticks simulated
+final_tick                               1903123778500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 147655                       # Simulator instruction rate (inst/s)
-host_op_rate                                   147655                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             5021061637                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 308576                       # Number of bytes of host memory used
-host_seconds                                   379.64                       # Real time elapsed on the host
-sim_insts                                    56056069                       # Number of instructions simulated
-sim_ops                                      56056069                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 103415                       # Simulator instruction rate (inst/s)
+host_op_rate                                   103415                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             3505224116                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 322696                       # Number of bytes of host memory used
+host_seconds                                   542.94                       # Real time elapsed on the host
+sim_insts                                    56148221                       # Number of instructions simulated
+sim_ops                                      56148221                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu0.inst           903488                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data         24906304                       # Number of bytes read from this memory
-system.physmem.bytes_read::tsunami.ide        2649664                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst            74560                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data           378304                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             28912320                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       903488                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst        74560                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          978048                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7848000                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7848000                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.inst             14117                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data            389161                       # Number of read requests responded to by this memory
-system.physmem.num_reads::tsunami.ide           41401                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              1165                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data              5911                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                451755                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          122625                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               122625                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.inst              473972                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data            13065895                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::tsunami.ide           1390019                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               39114                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              198459                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                15167459                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         473972                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          39114                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             513086                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           4117076                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                4117076                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           4117076                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             473972                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data           13065895                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::tsunami.ide          1390019                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              39114                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             198459                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               19284535                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        451755                       # Number of read requests accepted
-system.physmem.writeReqs                       122625                       # Number of write requests accepted
-system.physmem.readBursts                      451755                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     122625                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 28904128                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      8192                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   7846080                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  28912320                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                7848000                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      128                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytes_read::cpu0.inst           744192                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data         24296448                       # Number of bytes read from this memory
+system.physmem.bytes_read::tsunami.ide            960                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           238144                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data          1067328                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             26347072                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       744192                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       238144                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          982336                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      5275328                       # Number of bytes written to this memory
+system.physmem.bytes_written::tsunami.ide      2659328                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7934656                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.inst             11628                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data            379632                       # Number of read requests responded to by this memory
+system.physmem.num_reads::tsunami.ide              15                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst              3721                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data             16677                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                411673                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           82427                       # Number of write requests responded to by this memory
+system.physmem.num_writes::tsunami.ide          41552                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               123979                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.inst              391037                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data            12766615                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::tsunami.ide               504                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst              125133                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              560830                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                13844119                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         391037                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst         125133                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             516170                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           2771931                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::tsunami.ide          1397349                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                4169280                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           2771931                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             391037                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data           12766615                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::tsunami.ide          1397853                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst             125133                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             560830                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               18013399                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        411673                       # Number of read requests accepted
+system.physmem.writeReqs                       123979                       # Number of write requests accepted
+system.physmem.readBursts                      411673                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     123979                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 26335040                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     12032                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   7932928                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  26347072                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                7934656                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      188                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs           3217                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               28097                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               28602                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               29043                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               27571                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               27384                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               27564                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               27744                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               27694                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               27865                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               28720                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              28531                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              28618                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              28938                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              28977                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              28277                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              28002                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                7839                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                8045                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                8418                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                7040                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                6886                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                7040                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                7326                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                7097                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                7158                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                7908                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               7739                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               7821                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               8331                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               8401                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               7959                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               7587                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs           3444                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               25632                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               25720                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               26346                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               25660                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               25672                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               25150                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               25568                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               25491                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               25973                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               26167                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              25812                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              25687                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              26023                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              25844                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              25108                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              25632                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                8431                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                7989                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                8275                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                7382                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                7684                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                7400                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                7193                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                7021                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                7374                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                7755                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               7777                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               7454                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               8052                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               8097                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               7762                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               8306                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                           8                       # Number of times write queue was full causing retry
-system.physmem.totGap                    1906202745000                       # Total gap between requests
+system.physmem.numWrRetry                           7                       # Number of times write queue was full causing retry
+system.physmem.totGap                    1903119235000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  451755                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  411673                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 122625                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    319401                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     41325                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     46009                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                      9272                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                      2017                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                      4338                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                      3935                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                      3967                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                      2525                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                      2198                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                     2156                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                     2109                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                     1642                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                     1631                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                     1933                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                     1904                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                     2142                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                     1252                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                      959                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                      893                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                       12                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21                        7                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 123979                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    317912                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     40920                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     43295                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                      9256                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                        77                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                        14                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                         3                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                         1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                         1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                         1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
@@ -158,359 +161,357 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     1164                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     1205                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     2320                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     3479                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     4546                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     5068                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     5110                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     5237                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     5411                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     5622                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     5871                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     6194                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     6561                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     7197                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     6383                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     6572                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     6556                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     6376                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      959                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      905                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      926                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      871                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      926                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      950                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                     1044                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      955                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                     1154                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                     1202                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                     1166                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                     1281                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                     1449                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                     1666                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                     1863                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                     2097                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                     1921                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                     1890                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                     1701                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                     1710                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                     1833                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                     1636                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                      833                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                      350                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                      195                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                      125                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       43                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       32                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       22                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       17                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     1682                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     2373                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     3331                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     4398                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     5849                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     7355                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     7701                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     8902                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     9229                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::25                     9073                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     9333                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     8244                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     8320                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     6563                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     6410                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     6317                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     6098                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      278                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      199                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      168                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      171                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      186                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      174                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      147                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      148                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      166                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      139                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      140                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      144                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      145                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      129                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      113                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      108                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                       81                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                       59                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                       56                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                       60                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                       65                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                       84                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                       79                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                       80                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                       77                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                       70                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                       51                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                       38                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                       23                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       14                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                       16                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        66892                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      549.396161                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     336.305192                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     420.466175                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          14808     22.14%     22.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        11177     16.71%     38.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         5157      7.71%     46.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         2881      4.31%     50.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2294      3.43%     54.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1713      2.56%     56.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1492      2.23%     59.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1822      2.72%     61.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        25548     38.19%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          66892                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          7192                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        62.794355                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev     2475.959084                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-8191           7189     99.96%     99.96% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::40960-49151            1      0.01%     99.97% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::57344-65535            1      0.01%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::196608-204799            1      0.01%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            7192                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          7192                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        17.046023                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.810949                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        3.823344                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16               5742     79.84%     79.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17                 42      0.58%     80.42% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18                691      9.61%     90.03% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19                254      3.53%     93.56% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                102      1.42%     94.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21                 28      0.39%     95.37% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22                 28      0.39%     95.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23                 90      1.25%     97.01% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24                 10      0.14%     97.15% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::25                 32      0.44%     97.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26                 22      0.31%     97.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::27                 14      0.19%     98.10% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28                 15      0.21%     98.30% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::29                  7      0.10%     98.40% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::30                  9      0.13%     98.53% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::31                 23      0.32%     98.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32                 11      0.15%     99.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::34                  2      0.03%     99.03% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::35                  2      0.03%     99.05% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36                  1      0.01%     99.07% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::37                  3      0.04%     99.11% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::38                  2      0.03%     99.14% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::39                  4      0.06%     99.19% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40                  3      0.04%     99.24% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::41                  4      0.06%     99.29% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::42                  2      0.03%     99.32% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::43                  1      0.01%     99.33% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44                  2      0.03%     99.36% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::45                  1      0.01%     99.37% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::47                  8      0.11%     99.49% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::49                  1      0.01%     99.50% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::50                  1      0.01%     99.51% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::51                  2      0.03%     99.54% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52                  4      0.06%     99.60% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::55                  2      0.03%     99.62% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56                 13      0.18%     99.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::57                 13      0.18%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::58                  1      0.01%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            7192                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     9007685000                       # Total ticks spent queuing
-system.physmem.totMemAccLat               17475691250                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   2258135000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       19944.97                       # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples        64910                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      527.930488                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     320.008348                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     417.202697                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          14944     23.02%     23.02% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        11454     17.65%     40.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         5213      8.03%     48.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         2920      4.50%     53.20% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2279      3.51%     56.71% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1787      2.75%     59.46% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1551      2.39%     61.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1716      2.64%     64.50% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        23046     35.50%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          64910                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          5635                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        73.021650                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev     2812.727565                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-8191           5632     99.95%     99.95% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::40960-49151            1      0.02%     99.96% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::57344-65535            1      0.02%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::196608-204799            1      0.02%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total            5635                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          5635                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        21.996806                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.958563                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       19.289473                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            4843     85.94%     85.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23             143      2.54%     88.48% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27              10      0.18%     88.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31             227      4.03%     92.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35              45      0.80%     93.49% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39               4      0.07%     93.56% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43              10      0.18%     93.74% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47              10      0.18%     93.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51              34      0.60%     94.52% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55               6      0.11%     94.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59               5      0.09%     94.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63               2      0.04%     94.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67               9      0.16%     94.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71               2      0.04%     94.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75               4      0.07%     95.01% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79               1      0.02%     95.03% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83              41      0.73%     95.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87              13      0.23%     95.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95               2      0.04%     96.02% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99             176      3.12%     99.15% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             5      0.09%     99.24% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115             3      0.05%     99.29% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-123             3      0.05%     99.34% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127             1      0.02%     99.36% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131             6      0.11%     99.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135             3      0.05%     99.52% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-139             6      0.11%     99.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143            10      0.18%     99.80% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147             6      0.11%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::148-151             1      0.02%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-155             1      0.02%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-163             1      0.02%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::192-195             1      0.02%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::224-227             1      0.02%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            5635                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     3887945250                       # Total ticks spent queuing
+system.physmem.totMemAccLat               11603289000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   2057425000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        9448.57                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  38694.97                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          15.16                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           4.12                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       15.17                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        4.12                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  28198.57                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          13.84                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           4.17                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       13.84                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        4.17                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           0.15                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       0.12                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                           0.14                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       0.11                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.64                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        25.04                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     408104                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     99226                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   90.36                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  80.92                       # Row buffer hit rate for writes
-system.physmem.avgGap                      3318713.65                       # Average gap between requests
-system.physmem.pageHitRate                      88.35                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE     1805036475500                       # Time in different power states
-system.physmem.memoryStateTime::REF       63652420000                       # Time in different power states
+system.physmem.avgRdQLen                         1.66                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        24.85                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     371100                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     99427                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   90.19                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  80.20                       # Row buffer hit rate for writes
+system.physmem.avgGap                      3552902.32                       # Average gap between requests
+system.physmem.pageHitRate                      87.87                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE     1802319562500                       # Time in different power states
+system.physmem.memoryStateTime::REF       63549460000                       # Time in different power states
 system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT       37517744500                       # Time in different power states
+system.physmem.memoryStateTime::ACT       37254262500                       # Time in different power states
 system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.membus.throughput                     19340215                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq              296416                       # Transaction distribution
-system.membus.trans_dist::ReadResp             296338                       # Transaction distribution
-system.membus.trans_dist::WriteReq              12317                       # Transaction distribution
-system.membus.trans_dist::WriteResp             12317                       # Transaction distribution
-system.membus.trans_dist::Writeback            122625                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             4507                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq           1033                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp            3220                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            163308                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           163210                       # Transaction distribution
-system.membus.trans_dist::BadAddressError           78                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave        39026                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       910934                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio          156                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total       950116                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       124653                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       124653                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1074769                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave        67930                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port     31453376                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::total     31521306                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port      5306944                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::total      5306944                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total            36828250                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus               36828250                       # Total data (bytes)
-system.membus.snoop_data_through_bus            38208                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy            36079499                       # Layer occupancy (ticks)
+system.membus.throughput                     18054612                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq              296849                       # Transaction distribution
+system.membus.trans_dist::ReadResp             296569                       # Transaction distribution
+system.membus.trans_dist::WriteReq              12351                       # Transaction distribution
+system.membus.trans_dist::WriteResp             12351                       # Transaction distribution
+system.membus.trans_dist::Writeback             82427                       # Transaction distribution
+system.membus.trans_dist::WriteInvalidateReq        41552                       # Transaction distribution
+system.membus.trans_dist::WriteInvalidateResp        41552                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq             5284                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq           1479                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp            3444                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            122594                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           122459                       # Transaction distribution
+system.membus.trans_dist::BadAddressError          280                       # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave        39092                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       916085                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio          560                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total       955737                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        83294                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total        83294                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                1039031                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave        68194                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port     31621440                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::total     31689634                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port      2660288                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.iocache.mem_side::total      2660288                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total            34349922                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus               34349922                       # Total data (bytes)
+system.membus.snoop_data_through_bus            10240                       # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy            35504996                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy          1585687750                       # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy          1560042750                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.1                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy               97000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy              374000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         3823460772                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         3834491323                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
-system.membus.respLayer2.occupancy          376710991                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy           43141738                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.l2c.tags.replacements                   344852                       # number of replacements
-system.l2c.tags.tagsinuse                65305.335131                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    2605080                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                   409986                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                     6.354071                       # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle               7095487750                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   53708.677879                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     5228.517850                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     6139.451939                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst      202.418952                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data       26.268512                       # Average occupied blocks per requestor
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-system.l2c.Writeback_hits::total               833565                       # number of Writeback hits
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-system.l2c.UpgradeReq_hits::total                 221                       # number of UpgradeReq hits
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-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.917415                       # miss rate for UpgradeReq accesses
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 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -519,125 +520,125 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
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 system.l2c.ReadReq_mshr_hits::total                18                       # number of ReadReq MSHR hits
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 system.l2c.demand_mshr_hits::total                 18                       # number of demand (read+write) MSHR hits
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 system.l2c.overall_mshr_hits::total                18                       # number of overall MSHR hits
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-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.917415                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.930372                       # mshr miss rate for UpgradeReq accesses
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-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10121.346380                       # average UpgradeReq mshr miss latency
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+system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.006860                       # mshr miss rate for ReadReq accesses
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+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.878444                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.938855                       # mshr miss rate for UpgradeReq accesses
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+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 65459.688256                       # average overall mshr miss latency
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 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -648,102 +649,94 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data          inf
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
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-system.iocache.tags.tagsinuse                0.491390                       # Cycle average of tags in use
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 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs                41716                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs                41711                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         1711322153000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::tsunami.ide     0.491390                       # Average occupied blocks per requestor
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-system.iocache.tags.occ_percent::total       0.030712                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         1710336549000                       # Cycle when the warmup percentage was hit.
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 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
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 system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
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 system.iocache.demand_miss_rate::tsunami.ide            1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122577.127778                       # average ReadReq miss latency
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-system.iocache.demand_avg_miss_latency::tsunami.ide 298769.045960                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 298769.045960                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::tsunami.ide 298769.045960                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 298769.045960                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs        366756                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122082.188571                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 122082.188571                       # average ReadReq miss latency
+system.iocache.demand_avg_miss_latency::tsunami.ide 122082.188571                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 122082.188571                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::tsunami.ide 122082.188571                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 122082.188571                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                28394                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs    12.916673                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.fast_writes                          0                       # number of fast writes performed
+system.iocache.fast_writes                      41552                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.writebacks::writebacks           41520                       # number of writebacks
-system.iocache.writebacks::total                41520                       # number of writebacks
-system.iocache.ReadReq_mshr_misses::tsunami.ide          180                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total          180                       # number of ReadReq MSHR misses
-system.iocache.WriteReq_mshr_misses::tsunami.ide        41552                       # number of WriteReq MSHR misses
-system.iocache.WriteReq_mshr_misses::total        41552                       # number of WriteReq MSHR misses
-system.iocache.demand_mshr_misses::tsunami.ide        41732                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total        41732                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::tsunami.ide        41732                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total        41732                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     12701883                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     12701883                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::tsunami.ide  10283217961                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::total  10283217961                       # number of WriteReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::tsunami.ide  10295919844                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total  10295919844                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::tsunami.ide  10295919844                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total  10295919844                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_misses::tsunami.ide          175                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total          175                       # number of ReadReq MSHR misses
+system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide        41552                       # number of WriteInvalidateReq MSHR misses
+system.iocache.WriteInvalidateReq_mshr_misses::total        41552                       # number of WriteInvalidateReq MSHR misses
+system.iocache.demand_mshr_misses::tsunami.ide          175                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total          175                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::tsunami.ide          175                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total          175                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     12263383                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     12263383                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide   2507056568                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::total   2507056568                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::tsunami.ide     12263383                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total     12263383                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::tsunami.ide     12263383                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total     12263383                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
-system.iocache.WriteReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteReq accesses
-system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
+system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteInvalidateReq accesses
 system.iocache.demand_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for demand accesses
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70566.016667                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 70566.016667                       # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 247478.291322                       # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total 247478.291322                       # average WriteReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 246715.226780                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 246715.226780                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 246715.226780                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 246715.226780                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70076.474286                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 70076.474286                       # average ReadReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 60335.400655                       # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60335.400655                       # average WriteInvalidateReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70076.474286                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 70076.474286                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70076.474286                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 70076.474286                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
@@ -757,35 +750,35 @@ system.disk2.dma_read_txs                           0                       # Nu
 system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
 system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
 system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
-system.cpu0.branchPred.lookups               13535285                       # Number of BP lookups
-system.cpu0.branchPred.condPredicted         11399113                       # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect           368683                       # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups             9302001                       # Number of BTB lookups
-system.cpu0.branchPred.BTBHits                5741441                       # Number of BTB hits
+system.cpu0.branchPred.lookups               13702956                       # Number of BP lookups
+system.cpu0.branchPred.condPredicted         11991857                       # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect           276088                       # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups             8588922                       # Number of BTB lookups
+system.cpu0.branchPred.BTBHits                4683455                       # Number of BTB hits
 system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct            61.722644                       # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS                 871515                       # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect             32576                       # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct            54.529020                       # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS                 677984                       # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect             15448                       # Number of incorrect RAS predictions.
 system.cpu0.dtb.fetch_hits                          0                       # ITB hits
 system.cpu0.dtb.fetch_misses                        0                       # ITB misses
 system.cpu0.dtb.fetch_acv                           0                       # ITB acv
 system.cpu0.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu0.dtb.read_hits                     9655924                       # DTB read hits
-system.cpu0.dtb.read_misses                     34371                       # DTB read misses
-system.cpu0.dtb.read_acv                          569                       # DTB read access violations
-system.cpu0.dtb.read_accesses                  673777                       # DTB read accesses
-system.cpu0.dtb.write_hits                    6329246                       # DTB write hits
-system.cpu0.dtb.write_misses                     8477                       # DTB write misses
-system.cpu0.dtb.write_acv                         351                       # DTB write access violations
-system.cpu0.dtb.write_accesses                 236111                       # DTB write accesses
-system.cpu0.dtb.data_hits                    15985170                       # DTB hits
-system.cpu0.dtb.data_misses                     42848                       # DTB misses
-system.cpu0.dtb.data_acv                          920                       # DTB access violations
-system.cpu0.dtb.data_accesses                  909888                       # DTB accesses
-system.cpu0.itb.fetch_hits                    1092484                       # ITB hits
-system.cpu0.itb.fetch_misses                    31809                       # ITB misses
-system.cpu0.itb.fetch_acv                         996                       # ITB acv
-system.cpu0.itb.fetch_accesses                1124293                       # ITB accesses
+system.cpu0.dtb.read_hits                     7950804                       # DTB read hits
+system.cpu0.dtb.read_misses                     30543                       # DTB read misses
+system.cpu0.dtb.read_acv                          546                       # DTB read access violations
+system.cpu0.dtb.read_accesses                  683229                       # DTB read accesses
+system.cpu0.dtb.write_hits                    5159026                       # DTB write hits
+system.cpu0.dtb.write_misses                     6845                       # DTB write misses
+system.cpu0.dtb.write_acv                         353                       # DTB write access violations
+system.cpu0.dtb.write_accesses                 234573                       # DTB write accesses
+system.cpu0.dtb.data_hits                    13109830                       # DTB hits
+system.cpu0.dtb.data_misses                     37388                       # DTB misses
+system.cpu0.dtb.data_acv                          899                       # DTB access violations
+system.cpu0.dtb.data_accesses                  917802                       # DTB accesses
+system.cpu0.itb.fetch_hits                    1312718                       # ITB hits
+system.cpu0.itb.fetch_misses                    29261                       # ITB misses
+system.cpu0.itb.fetch_acv                         629                       # ITB acv
+system.cpu0.itb.fetch_accesses                1341979                       # ITB accesses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.read_acv                            0                       # DTB read access violations
@@ -798,304 +791,304 @@ system.cpu0.itb.data_hits                           0                       # DT
 system.cpu0.itb.data_misses                         0                       # DTB misses
 system.cpu0.itb.data_acv                            0                       # DTB access violations
 system.cpu0.itb.data_accesses                       0                       # DTB accesses
-system.cpu0.numCycles                       120980731                       # number of cpu cycles simulated
+system.cpu0.numCycles                        99665250                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles          27854466                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts                      69491073                       # Number of instructions fetch has processed
-system.cpu0.fetch.Branches                   13535285                       # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches           6612956                       # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles                     12980522                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles                1985487                       # Number of cycles fetch has spent squashing
-system.cpu0.fetch.BlockedCycles              37586938                       # Number of cycles fetch has spent blocked
-system.cpu0.fetch.MiscStallCycles               31052                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingTrapStallCycles       209286                       # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles       361146                       # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles          209                       # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines                  8301805                       # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes               269407                       # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.rateDist::samples          80329317                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean             0.865077                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev            2.209142                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.icacheStallCycles          22511576                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts                      60582407                       # Number of instructions fetch has processed
+system.cpu0.fetch.Branches                   13702956                       # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches           5361439                       # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles                     70984108                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles                 933480                       # Number of cycles fetch has spent squashing
+system.cpu0.fetch.TlbCycles                       621                       # Number of cycles fetch has spent waiting for tlb
+system.cpu0.fetch.MiscStallCycles               27412                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingTrapStallCycles      1463366                       # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles       292819                       # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles          216                       # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines                  7109889                       # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes               200075                       # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.rateDist::samples          95746858                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean             0.632735                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev            1.928110                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0                67348795     83.84%     83.84% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1                  826622      1.03%     84.87% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2                 1640547      2.04%     86.91% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3                  764329      0.95%     87.86% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4                 2736993      3.41%     91.27% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5                  565546      0.70%     91.97% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6                  615994      0.77%     92.74% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::7                 1025224      1.28%     94.02% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::8                 4805267      5.98%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0                84335489     88.08%     88.08% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1                  757900      0.79%     88.87% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2                 1598110      1.67%     90.54% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3                  658612      0.69%     91.23% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4                 2290747      2.39%     93.62% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5                  510807      0.53%     94.16% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6                  540667      0.56%     94.72% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::7                  744782      0.78%     95.50% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::8                 4309744      4.50%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total            80329317                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate                 0.111880                       # Number of branch fetches per cycle
-system.cpu0.fetch.rate                       0.574398                       # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles                28693302                       # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles             37589637                       # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles                 12241193                       # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles               539176                       # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles               1266008                       # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved              554913                       # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred                40031                       # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts              68046301                       # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts               123637                       # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles               1266008                       # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles                29596220                       # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles               13874520                       # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles      19704370                       # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles                 11366279                       # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles              4521918                       # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts              64294985                       # Number of instructions processed by rename
-system.cpu0.rename.ROBFullEvents                 8881                       # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents                963704                       # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LQFullEvents                 49626                       # Number of times rename has blocked due to LQ full
-system.cpu0.rename.SQFullEvents               1581472                       # Number of times rename has blocked due to SQ full
-system.cpu0.rename.RenamedOperands           42969329                       # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups             77993479                       # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups        77835647                       # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups           147432                       # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps             36982529                       # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps                 5986792                       # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts           1597094                       # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts        233553                       # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts                  9775023                       # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads            10212119                       # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores            6719453                       # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads          1264075                       # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores          886942                       # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded                  56810323                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded            2002217                       # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued                 55156303                       # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued           107150                       # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined        7195907                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined      4115621                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved       1359252                       # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples     80329317                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean        0.686627                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev       1.367653                       # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total            95746858                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate                 0.137490                       # Number of branch fetches per cycle
+system.cpu0.fetch.rate                       0.607859                       # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles                18154184                       # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles             68366814                       # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles                  7221268                       # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles              1568077                       # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles                436514                       # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved              432928                       # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred                30567                       # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts              53177978                       # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts                98719                       # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles                436514                       # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles                18925396                       # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles               44877173                       # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles      16564638                       # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles                  7942906                       # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles              7000229                       # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts              51314401                       # Number of instructions processed by rename
+system.cpu0.rename.ROBFullEvents               200370                       # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents               1702156                       # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LQFullEvents                121650                       # Number of times rename has blocked due to LQ full
+system.cpu0.rename.SQFullEvents               3596195                       # Number of times rename has blocked due to SQ full
+system.cpu0.rename.RenamedOperands           34369689                       # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups             62476617                       # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups        62360377                       # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups           107565                       # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps             30276917                       # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps                 4092764                       # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts           1298231                       # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts        191875                       # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts                 11393500                       # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads             8037568                       # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores            5366781                       # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads          1135735                       # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores          800748                       # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded                  45795204                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded            1644687                       # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued                 45103865                       # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued            41971                       # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined        5328763                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined      2477826                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved       1134880                       # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples     95746858                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean        0.471074                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev       1.201865                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0           56644741     70.52%     70.52% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1           10637349     13.24%     83.76% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2            4503428      5.61%     89.36% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3            3111745      3.87%     93.24% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4            2708967      3.37%     96.61% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5            1473067      1.83%     98.44% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::6             832512      1.04%     99.48% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::7             359476      0.45%     99.93% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::8              58032      0.07%    100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0           76985468     80.41%     80.41% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1            8252195      8.62%     89.02% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2            3430688      3.58%     92.61% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3            2350675      2.46%     95.06% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4            2374207      2.48%     97.54% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5            1175968      1.23%     98.77% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::6             779493      0.81%     99.58% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::7             300669      0.31%     99.90% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::8              97495      0.10%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total       80329317                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total       95746858                       # Number of insts issued each cycle
 system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu                  91428     11.87%     11.87% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult                     0      0.00%     11.87% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv                      0      0.00%     11.87% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     11.87% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     11.87% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     11.87% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult                   0      0.00%     11.87% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     11.87% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     11.87% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     11.87% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     11.87% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     11.87% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     11.87% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     11.87% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     11.87% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult                    0      0.00%     11.87% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     11.87% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift                   0      0.00%     11.87% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     11.87% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     11.87% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     11.87% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     11.87% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     11.87% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     11.87% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     11.87% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     11.87% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     11.87% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     11.87% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     11.87% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead                367704     47.76%     59.63% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite               310812     40.37%    100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu                 143906     17.61%     17.61% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult                     0      0.00%     17.61% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv                      0      0.00%     17.61% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     17.61% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     17.61% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     17.61% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult                   0      0.00%     17.61% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     17.61% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     17.61% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     17.61% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     17.61% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     17.61% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     17.61% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     17.61% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     17.61% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult                    0      0.00%     17.61% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     17.61% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift                   0      0.00%     17.61% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     17.61% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     17.61% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     17.61% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     17.61% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     17.61% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     17.61% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     17.61% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     17.61% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     17.61% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     17.61% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     17.61% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead                398143     48.73%     66.35% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite               274956     33.65%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu0.iq.FU_type_0::No_OpClass             3793      0.01%      0.01% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu             37662855     68.28%     68.29% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult               60369      0.11%     68.40% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     68.40% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd              16864      0.03%     68.43% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     68.43% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     68.43% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     68.43% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv               1883      0.00%     68.43% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     68.43% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     68.43% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     68.43% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     68.43% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     68.43% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     68.43% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     68.43% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     68.43% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     68.43% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     68.43% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.43% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     68.43% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.43% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.43% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.43% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.43% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.43% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc             0      0.00%     68.43% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     68.43% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.43% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.43% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead            10116560     18.34%     86.78% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite            6398898     11.60%     98.38% # Type of FU issued
-system.cpu0.iq.FU_type_0::IprAccess            895081      1.62%    100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::No_OpClass             3780      0.01%      0.01% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu             30829458     68.35%     68.36% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult               46395      0.10%     68.46% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     68.46% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd              26948      0.06%     68.52% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     68.52% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     68.52% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     68.52% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv               1883      0.00%     68.53% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     68.53% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     68.53% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     68.53% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     68.53% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     68.53% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     68.53% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     68.53% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     68.53% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     68.53% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     68.53% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.53% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     68.53% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.53% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.53% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.53% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.53% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.53% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc             0      0.00%     68.53% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     68.53% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.53% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.53% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead             8252345     18.30%     86.82% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite            5217820     11.57%     98.39% # Type of FU issued
+system.cpu0.iq.FU_type_0::IprAccess            725236      1.61%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total              55156303                       # Type of FU issued
-system.cpu0.iq.rate                          0.455910                       # Inst issue rate
-system.cpu0.iq.fu_busy_cnt                     769944                       # FU busy when requested
-system.cpu0.iq.fu_busy_rate                  0.013959                       # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads         190884663                       # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes         65713674                       # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses     53746277                       # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads             634353                       # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes            307759                       # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses       299045                       # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses              55590646                       # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses                 331808                       # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads          587688                       # Number of loads that had data forwarded from stores
+system.cpu0.iq.FU_type_0::total              45103865                       # Type of FU issued
+system.cpu0.iq.rate                          0.452554                       # Inst issue rate
+system.cpu0.iq.fu_busy_cnt                     817005                       # FU busy when requested
+system.cpu0.iq.fu_busy_rate                  0.018114                       # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads         186342910                       # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes         52562719                       # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses     43916640                       # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads             470653                       # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes            221373                       # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_wakeup_accesses       216432                       # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.int_alu_accesses              45663938                       # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses                 253152                       # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads          522094                       # Number of loads that had data forwarded from stores
 system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads      1466473                       # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses         4362                       # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation        13302                       # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores       593267                       # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads       946690                       # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses         4799                       # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation        15752                       # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores       387148                       # Number of stores squashed
 system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads        18777                       # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked       290466                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.rescheduledLoads        13610                       # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked       357638                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles               1266008                       # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles               10034082                       # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles              1132931                       # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts           62323042                       # Number of instructions dispatched to IQ
-system.cpu0.iew.iewDispSquashedInsts           565721                       # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts             10212119                       # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts             6719453                       # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts           1762676                       # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents                460962                       # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents               503945                       # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents         13302                       # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect        186944                       # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect       388547                       # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts              575491                       # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts             54610252                       # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts              9715916                       # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts           546050                       # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewSquashCycles                436514                       # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles               41413967                       # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles              1424350                       # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts           50298451                       # Number of instructions dispatched to IQ
+system.cpu0.iew.iewDispSquashedInsts           103444                       # Number of squashed instructions skipped by dispatch
+system.cpu0.iew.iewDispLoadInsts              8037568                       # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts             5366781                       # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts           1456887                       # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents                 31578                       # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents              1238658                       # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents         15752                       # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect        134081                       # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect       309122                       # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts              443203                       # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts             44677716                       # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts              8001376                       # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts           426148                       # Number of squashed instructions skipped in execute
 system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu0.iew.exec_nop                      3510502                       # number of nop insts executed
-system.cpu0.iew.exec_refs                    16068148                       # number of memory reference insts executed
-system.cpu0.iew.exec_branches                 8653897                       # Number of branches executed
-system.cpu0.iew.exec_stores                   6352232                       # Number of stores executed
-system.cpu0.iew.exec_rate                    0.451396                       # Inst execution rate
-system.cpu0.iew.wb_sent                      54145867                       # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count                     54045322                       # cumulative count of insts written-back
-system.cpu0.iew.wb_producers                 27468175                       # num instructions producing a value
-system.cpu0.iew.wb_consumers                 37895992                       # num instructions consuming a value
+system.cpu0.iew.exec_nop                      2858560                       # number of nop insts executed
+system.cpu0.iew.exec_refs                    13178604                       # number of memory reference insts executed
+system.cpu0.iew.exec_branches                 7039370                       # Number of branches executed
+system.cpu0.iew.exec_stores                   5177228                       # Number of stores executed
+system.cpu0.iew.exec_rate                    0.448278                       # Inst execution rate
+system.cpu0.iew.wb_sent                      44227196                       # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count                     44133072                       # cumulative count of insts written-back
+system.cpu0.iew.wb_producers                 22691402                       # num instructions producing a value
+system.cpu0.iew.wb_consumers                 31140086                       # num instructions consuming a value
 system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu0.iew.wb_rate                      0.446727                       # insts written-back per cycle
-system.cpu0.iew.wb_fanout                    0.724831                       # average fanout of values written-back
+system.cpu0.iew.wb_rate                      0.442813                       # insts written-back per cycle
+system.cpu0.iew.wb_fanout                    0.728688                       # average fanout of values written-back
 system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.commit.commitSquashedInsts        7798809                       # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls         642965                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts           531823                       # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples     79063309                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean     0.688507                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev     1.631609                       # Number of insts commited each cycle
+system.cpu0.commit.commitSquashedInsts        5846321                       # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls         509807                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts           407712                       # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples     94708833                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean     0.468364                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev     1.405169                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0     59272342     74.97%     74.97% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1      8075780     10.21%     85.18% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2      4311536      5.45%     90.64% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3      2381088      3.01%     93.65% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4      1583020      2.00%     95.65% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5       598155      0.76%     96.41% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6       490827      0.62%     97.03% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7       478799      0.61%     97.63% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8      1871762      2.37%    100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0     79035549     83.45%     83.45% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1      6314508      6.67%     90.12% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2      3292930      3.48%     93.60% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3      1802282      1.90%     95.50% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4      1366338      1.44%     96.94% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5       489382      0.52%     97.46% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6       366889      0.39%     97.85% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7       390234      0.41%     98.26% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8      1650721      1.74%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total     79063309                       # Number of insts commited each cycle
-system.cpu0.commit.committedInsts            54435622                       # Number of instructions committed
-system.cpu0.commit.committedOps              54435622                       # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total     94708833                       # Number of insts commited each cycle
+system.cpu0.commit.committedInsts            44358216                       # Number of instructions committed
+system.cpu0.commit.committedOps              44358216                       # Number of ops (including micro ops) committed
 system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu0.commit.refs                      14871832                       # Number of memory references committed
-system.cpu0.commit.loads                      8745646                       # Number of loads committed
-system.cpu0.commit.membars                     219982                       # Number of memory barriers committed
-system.cpu0.commit.branches                   8204799                       # Number of branches committed
-system.cpu0.commit.fp_insts                    296843                       # Number of committed floating point instructions.
-system.cpu0.commit.int_insts                 50375539                       # Number of committed integer instructions.
-system.cpu0.commit.function_calls              712916                       # Number of function calls committed.
-system.cpu0.commit.op_class_0::No_OpClass      3148922      5.78%      5.78% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntAlu        35215746     64.69%     70.48% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntMult          59292      0.11%     70.59% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntDiv               0      0.00%     70.59% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatAdd         16864      0.03%     70.62% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     70.62% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     70.62% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatMult            0      0.00%     70.62% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatDiv          1883      0.00%     70.62% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     70.62% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     70.62% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     70.62% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     70.62% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     70.62% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     70.62% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     70.62% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMult             0      0.00%     70.62% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     70.62% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShift            0      0.00%     70.62% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     70.62% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     70.62% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     70.62% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     70.62% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     70.62% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     70.62% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     70.62% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMisc            0      0.00%     70.62% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     70.62% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     70.62% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     70.62% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemRead        8965628     16.47%     87.09% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemWrite       6132206     11.27%     98.36% # Class of committed instruction
-system.cpu0.commit.op_class_0::IprAccess       895081      1.64%    100.00% # Class of committed instruction
+system.cpu0.commit.refs                      12070511                       # Number of memory references committed
+system.cpu0.commit.loads                      7090878                       # Number of loads committed
+system.cpu0.commit.membars                     170277                       # Number of memory barriers committed
+system.cpu0.commit.branches                   6663650                       # Number of branches committed
+system.cpu0.commit.fp_insts                    213529                       # Number of committed floating point instructions.
+system.cpu0.commit.int_insts                 41141903                       # Number of committed integer instructions.
+system.cpu0.commit.function_calls              549728                       # Number of function calls committed.
+system.cpu0.commit.op_class_0::No_OpClass      2498518      5.63%      5.63% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntAlu        28814427     64.96%     70.59% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntMult          45393      0.10%     70.69% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntDiv               0      0.00%     70.69% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatAdd         26477      0.06%     70.75% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     70.75% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     70.75% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatMult            0      0.00%     70.75% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatDiv          1883      0.00%     70.76% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     70.76% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     70.76% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     70.76% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     70.76% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     70.76% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     70.76% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     70.76% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMult             0      0.00%     70.76% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     70.76% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShift            0      0.00%     70.76% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     70.76% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     70.76% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     70.76% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     70.76% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     70.76% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     70.76% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     70.76% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMisc            0      0.00%     70.76% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     70.76% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     70.76% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     70.76% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemRead        7261155     16.37%     87.13% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemWrite       4985127     11.24%     98.37% # Class of committed instruction
+system.cpu0.commit.op_class_0::IprAccess       725236      1.63%    100.00% # Class of committed instruction
 system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::total         54435622                       # Class of committed instruction
-system.cpu0.commit.bw_lim_events              1871762                       # number cycles where commit BW limit reached
+system.cpu0.commit.op_class_0::total         44358216                       # Class of committed instruction
+system.cpu0.commit.bw_lim_events              1650721                       # number cycles where commit BW limit reached
 system.cpu0.commit.bw_limited                       0                       # number of insts not committed due to BW limits
-system.cpu0.rob.rob_reads                   139225703                       # The number of ROB reads
-system.cpu0.rob.rob_writes                  125735253                       # The number of ROB writes
-system.cpu0.timesIdled                        1168278                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles                       40651414                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.quiesceCycles                  3691427340                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.committedInsts                   51290467                       # Number of Instructions Simulated
-system.cpu0.committedOps                     51290467                       # Number of Ops (including micro ops) Simulated
-system.cpu0.cpi                              2.358737                       # CPI: Cycles Per Instruction
-system.cpu0.cpi_total                        2.358737                       # CPI: Total CPI of All Threads
-system.cpu0.ipc                              0.423956                       # IPC: Instructions Per Cycle
-system.cpu0.ipc_total                        0.423956                       # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads                71570668                       # number of integer regfile reads
-system.cpu0.int_regfile_writes               39014056                       # number of integer regfile writes
-system.cpu0.fp_regfile_reads                   147010                       # number of floating regfile reads
-system.cpu0.fp_regfile_writes                  148900                       # number of floating regfile writes
-system.cpu0.misc_regfile_reads                1947197                       # number of misc regfile reads
-system.cpu0.misc_regfile_writes                897129                       # number of misc regfile writes
+system.cpu0.rob.rob_reads                   143064224                       # The number of ROB reads
+system.cpu0.rob.rob_writes                  101447849                       # The number of ROB writes
+system.cpu0.timesIdled                         414726                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.idleCycles                        3918392                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.quiesceCycles                  3706577488                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.committedInsts                   41863465                       # Number of Instructions Simulated
+system.cpu0.committedOps                     41863465                       # Number of Ops (including micro ops) Simulated
+system.cpu0.cpi                              2.380721                       # CPI: Cycles Per Instruction
+system.cpu0.cpi_total                        2.380721                       # CPI: Total CPI of All Threads
+system.cpu0.ipc                              0.420041                       # IPC: Instructions Per Cycle
+system.cpu0.ipc_total                        0.420041                       # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads                58777310                       # number of integer regfile reads
+system.cpu0.int_regfile_writes               31962259                       # number of integer regfile writes
+system.cpu0.fp_regfile_reads                   106639                       # number of floating regfile reads
+system.cpu0.fp_regfile_writes                  106808                       # number of floating regfile writes
+system.cpu0.misc_regfile_reads                1588469                       # number of misc regfile reads
+system.cpu0.misc_regfile_writes                729535                       # number of misc regfile writes
 system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
 system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
 system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
@@ -1127,49 +1120,50 @@ system.tsunami.ethernet.totalRxOrn                  0                       # to
 system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
 system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
 system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
-system.toL2Bus.throughput                   111935595                       # Throughput (bytes/s)
-system.toL2Bus.trans_dist::ReadReq            2200566                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           2200471                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             12317                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            12317                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback           833565                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq            4571                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq          1080                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp           5651                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           347592                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          306043                       # Transaction distribution
-system.toL2Bus.trans_dist::BadAddressError           78                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      1987262                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      3563495                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side       190571                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side       127415                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               5868743                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     63588928                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side    138451052                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side      6097280                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side      4501998                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size::total          212639258                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.data_through_bus             212628634                       # Total data (bytes)
-system.toL2Bus.snoop_data_through_bus          743808                       # Total snoop data (bytes)
-system.toL2Bus.reqLayer0.occupancy         5019455896                       # Layer occupancy (ticks)
+system.toL2Bus.throughput                   115690704                       # Throughput (bytes/s)
+system.toL2Bus.trans_dist::ReadReq            2250904                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp           2250609                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq             12351                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp            12351                       # Transaction distribution
+system.toL2Bus.trans_dist::Writeback           841911                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateReq        41559                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq            5326                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq          1552                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp           6878                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq           312265                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp          312265                       # Transaction distribution
+system.toL2Bus.trans_dist::BadAddressError          280                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      1525692                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      2740000                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side       708608                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side      1000724                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total               5975024                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     48817472                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side    104660497                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side     22674112                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side     39558737                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size::total          215710818                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.data_through_bus             215700578                       # Total data (bytes)
+system.toL2Bus.snoop_data_through_bus         4473152                       # Total snoop data (bytes)
+system.toL2Bus.reqLayer0.occupancy         5085967365                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.3                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy           747000                       # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy           720000                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy        4476579522                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy        3437989936                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.2                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy        6206391842                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy        4906988127                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.3                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy         429200431                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy         227242208                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
-system.iobus.throughput                       1431950                       # Throughput (bytes/s)
-system.iobus.trans_dist::ReadReq                 7376                       # Transaction distribution
-system.iobus.trans_dist::ReadResp                7376                       # Transaction distribution
-system.iobus.trans_dist::WriteReq               53869                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              53869                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio        10422                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio          480                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.respLayer2.occupancy        1597018302                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.utilization             0.1                       # Layer utilization (%)
+system.toL2Bus.respLayer3.occupancy        1654443775                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.utilization             0.1                       # Layer utilization (%)
+system.iobus.throughput                       1434388                       # Throughput (bytes/s)
+system.iobus.trans_dist::ReadReq                 7370                       # Transaction distribution
+system.iobus.trans_dist::ReadResp                7370                       # Transaction distribution
+system.iobus.trans_dist::WriteReq               53903                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              53903                       # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio        10492                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio          476                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio           10                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio           10                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio          180                       # Packet count per connected master and slave (bytes)
@@ -1180,12 +1174,12 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf
 system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio          102                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf          180                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total        39026                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side        83464                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.tsunami.ide.dma::total        83464                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  122490                       # Packet count per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio        41688                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio         1920                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total        39092                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side        83454                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.tsunami.ide.dma::total        83454                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  122546                       # Packet count per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio        41968                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio         1904                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio            5                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio            5                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio          160                       # Cumulative packet size per connected master and slave (bytes)
@@ -1196,14 +1190,14 @@ system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf
 system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio          204                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf          299                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::total        67930                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      2661664                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.tsunami.ide.dma::total      2661664                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::total              2729594                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.data_through_bus                 2729594                       # Total data (bytes)
-system.iobus.reqLayer0.occupancy              9777000                       # Layer occupancy (ticks)
+system.iobus.tot_pkt_size_system.bridge.master::total        68194                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      2661624                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.tsunami.ide.dma::total      2661624                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::total              2729818                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.data_through_bus                 2729818                       # Total data (bytes)
+system.iobus.reqLayer0.occupancy              9847000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy               359000                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy               356000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer2.occupancy                 9000                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
@@ -1223,267 +1217,267 @@ system.iobus.reqLayer27.occupancy               76000                       # La
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer28.occupancy              110000                       # Layer occupancy (ticks)
 system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer29.occupancy           380161835                       # Layer occupancy (ticks)
+system.iobus.reqLayer29.occupancy           374411689                       # Layer occupancy (ticks)
 system.iobus.reqLayer29.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer30.occupancy               30000                       # Layer occupancy (ticks)
 system.iobus.reqLayer30.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy            26709000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy            26741000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer1.occupancy            43245009                       # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy            42019262                       # Layer occupancy (ticks)
 system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
-system.cpu0.icache.tags.replacements           993039                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          509.694749                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs            7257459                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs           993551                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs             7.304566                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle      26718502250                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   509.694749                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.995498                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.995498                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0           71                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1           16                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2          425                       # Occupied blocks per task id
-system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses          9295490                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses         9295490                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst      7257459                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total        7257459                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst      7257459                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total         7257459                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst      7257459                       # number of overall hits
-system.cpu0.icache.overall_hits::total        7257459                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst      1044346                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total      1044346                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst      1044346                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total       1044346                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst      1044346                       # number of overall misses
-system.cpu0.icache.overall_misses::total      1044346                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  14667970749                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total  14667970749                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst  14667970749                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total  14667970749                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst  14667970749                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total  14667970749                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst      8301805                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total      8301805                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst      8301805                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total      8301805                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst      8301805                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total      8301805                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.125797                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.125797                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.125797                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.125797                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.125797                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.125797                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14045.125609                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 14045.125609                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14045.125609                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 14045.125609                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14045.125609                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 14045.125609                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs         4303                       # number of cycles access was blocked
+system.cpu0.icache.tags.replacements           762211                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          508.848890                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs            6309809                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs           762721                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs             8.272762                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle      26485928250                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   508.848890                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.993845                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.993845                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_task_id_blocks::1024          510                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0           79                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1           13                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2          418                       # Occupied blocks per task id
+system.cpu0.icache.tags.occ_task_id_percent::1024     0.996094                       # Percentage of cache occupancy per task id
+system.cpu0.icache.tags.tag_accesses          7872808                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses         7872808                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst      6309809                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total        6309809                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst      6309809                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total         6309809                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst      6309809                       # number of overall hits
+system.cpu0.icache.overall_hits::total        6309809                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst       800080                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total       800080                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst       800080                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total        800080                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst       800080                       # number of overall misses
+system.cpu0.icache.overall_misses::total       800080                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  11341096711                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total  11341096711                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst  11341096711                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total  11341096711                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst  11341096711                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total  11341096711                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst      7109889                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total      7109889                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst      7109889                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total      7109889                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst      7109889                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total      7109889                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.112531                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.112531                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.112531                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.112531                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.112531                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.112531                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14174.953393                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 14174.953393                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14174.953393                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 14174.953393                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14174.953393                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 14174.953393                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs         3387                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs              182                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs              162                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs    23.642857                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs    20.907407                       # average number of cycles each access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        50661                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total        50661                       # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu0.inst        50661                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total        50661                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu0.inst        50661                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total        50661                       # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       993685                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total       993685                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst       993685                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total       993685                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst       993685                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total       993685                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  12074149969                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total  12074149969                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  12074149969                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total  12074149969                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  12074149969                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total  12074149969                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.119695                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.119695                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.119695                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.119695                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.119695                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.119695                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12150.882794                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12150.882794                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12150.882794                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 12150.882794                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12150.882794                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 12150.882794                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        37161                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total        37161                       # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu0.inst        37161                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total        37161                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu0.inst        37161                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total        37161                       # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       762919                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total       762919                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst       762919                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total       762919                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst       762919                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total       762919                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   9350852559                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total   9350852559                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   9350852559                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total   9350852559                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   9350852559                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total   9350852559                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.107304                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.107304                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.107304                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.107304                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.107304                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.107304                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12256.678047                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12256.678047                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12256.678047                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 12256.678047                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12256.678047                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 12256.678047                       # average overall mshr miss latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.dcache.tags.replacements          1357625                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          506.932074                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           11305784                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs          1358137                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs             8.324480                       # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle         25366000                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   506.932074                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.990102                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.990102                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.replacements          1069035                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          482.779727                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs            9141371                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs          1069547                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs             8.546956                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.warmup_cycle         25151000                       # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   482.779727                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.942929                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.942929                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0          239                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          224                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           49                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0          229                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          233                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           50                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses         61088591                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses        61088591                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data      6897589                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total        6897589                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data      4012977                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total       4012977                       # number of WriteReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       181053                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       181053                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       208423                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       208423                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data     10910566                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        10910566                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data     10910566                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       10910566                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data      1718976                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total      1718976                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data      1889613                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total      1889613                       # number of WriteReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        22934                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total        22934                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data          507                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total          507                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data      3608589                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       3608589                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data      3608589                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      3608589                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  42674970043                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total  42674970043                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  81294445080                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total  81294445080                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    374188245                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total    374188245                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data      3007034                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total      3007034                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data 123969415123                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 123969415123                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data 123969415123                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 123969415123                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data      8616565                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total      8616565                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data      5902590                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total      5902590                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       203987                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       203987                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       208930                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       208930                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data     14519155                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     14519155                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data     14519155                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     14519155                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.199497                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.199497                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.320133                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.320133                       # miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.112429                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.112429                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.002427                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.002427                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.248540                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.248540                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.248540                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.248540                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 24825.809111                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 24825.809111                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 43021.743119                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 43021.743119                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16315.873594                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16315.873594                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data  5931.033531                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total  5931.033531                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 34353.985761                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 34353.985761                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 34353.985761                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 34353.985761                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs      3433420                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets          538                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs           116463                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets              7                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs    29.480779                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets    76.857143                       # average number of cycles each access was blocked
+system.cpu0.dcache.tags.tag_accesses         49546788                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses        49546788                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data      5665393                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total        5665393                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data      3152024                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total       3152024                       # number of WriteReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       147109                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       147109                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data       170256                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       170256                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data      8817417                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total         8817417                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data      8817417                       # number of overall hits
+system.cpu0.dcache.overall_hits::total        8817417                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data      1322171                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total      1322171                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data      1644281                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total      1644281                       # number of WriteReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        16610                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total        16610                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data          766                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total          766                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data      2966452                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total       2966452                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data      2966452                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      2966452                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  36169344894                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total  36169344894                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  74324803897                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total  74324803897                       # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    267182493                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total    267182493                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data      4788059                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total      4788059                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data 110494148791                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total 110494148791                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data 110494148791                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total 110494148791                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data      6987564                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total      6987564                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data      4796305                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total      4796305                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       163719                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       163719                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       171022                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       171022                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data     11783869                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     11783869                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data     11783869                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     11783869                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.189218                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.189218                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.342822                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.342822                       # miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.101454                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.101454                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.004479                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.004479                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.251738                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.251738                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.251738                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.251738                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 27356.026485                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 27356.026485                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 45202.008596                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 45202.008596                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16085.640759                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16085.640759                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data  6250.729765                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total  6250.729765                       # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 37247.913936                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 37247.913936                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 37247.913936                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 37247.913936                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs      3702426                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets         3454                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs           160595                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets             88                       # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs    23.054429                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets    39.250000                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       808609                       # number of writebacks
-system.cpu0.dcache.writebacks::total           808609                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       667238                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total       667238                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1594728                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total      1594728                       # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data         5762                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total         5762                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data      2261966                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total      2261966                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data      2261966                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total      2261966                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      1051738                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total      1051738                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       294885                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       294885                       # number of WriteReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data        17172                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total        17172                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data          507                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total          507                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data      1346623                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total      1346623                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data      1346623                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total      1346623                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  27880739944                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total  27880739944                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  12002536573                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total  12002536573                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data    202887753                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    202887753                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data      1992966                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total      1992966                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  39883276517                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  39883276517                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  39883276517                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  39883276517                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   1460997001                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   1460997001                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2069284998                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   2069284998                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   3530281999                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total   3530281999                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.122060                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.122060                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.049959                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.049959                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.084182                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.084182                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.002427                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.002427                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.092748                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.092748                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.092748                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.092748                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26509.206612                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26509.206612                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 40702.431704                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 40702.431704                       # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11815.033368                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11815.033368                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data  3930.899408                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total  3930.899408                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 29617.254805                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 29617.254805                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 29617.254805                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 29617.254805                       # average overall mshr miss latency
+system.cpu0.dcache.writebacks::writebacks       568073                       # number of writebacks
+system.cpu0.dcache.writebacks::total           568073                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       499697                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total       499697                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1402831                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total      1402831                       # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data         4326                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total         4326                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data      1902528                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total      1902528                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data      1902528                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total      1902528                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       822474                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total       822474                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       241450                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       241450                       # number of WriteReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data        12284                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total        12284                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data          766                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total          766                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data      1063924                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total      1063924                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data      1063924                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total      1063924                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  24909734008                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total  24909734008                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  10782476086                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total  10782476086                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data    145144507                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    145144507                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data      3254941                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total      3254941                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  35692210094                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  35692210094                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  35692210094                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  35692210094                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data    992378000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total    992378000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   1672126998                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   1672126998                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   2664504998                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total   2664504998                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.117705                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.117705                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.050341                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.050341                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.075031                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.075031                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.004479                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.004479                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.090286                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.090286                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.090286                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.090286                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 30286.348271                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 30286.348271                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 44657.179896                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 44657.179896                       # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11815.736486                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11815.736486                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data  4249.270235                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total  4249.270235                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 33547.706503                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 33547.706503                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 33547.706503                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 33547.706503                       # average overall mshr miss latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
@@ -1491,35 +1485,35 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf
 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.branchPred.lookups                1483279                       # Number of BP lookups
-system.cpu1.branchPred.condPredicted          1227619                       # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect            44770                       # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups              650934                       # Number of BTB lookups
-system.cpu1.branchPred.BTBHits                 463612                       # Number of BTB hits
+system.cpu1.branchPred.lookups                5770916                       # Number of BP lookups
+system.cpu1.branchPred.condPredicted          5004196                       # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect           122577                       # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups             3556553                       # Number of BTB lookups
+system.cpu1.branchPred.BTBHits                1526133                       # Number of BTB hits
 system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct            71.222582                       # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS                  99211                       # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect              4550                       # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct            42.910453                       # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS                 301064                       # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect              7748                       # Number of incorrect RAS predictions.
 system.cpu1.dtb.fetch_hits                          0                       # ITB hits
 system.cpu1.dtb.fetch_misses                        0                       # ITB misses
 system.cpu1.dtb.fetch_acv                           0                       # ITB acv
 system.cpu1.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu1.dtb.read_hits                     1187167                       # DTB read hits
-system.cpu1.dtb.read_misses                      8989                       # DTB read misses
-system.cpu1.dtb.read_acv                            6                       # DTB read access violations
-system.cpu1.dtb.read_accesses                  276351                       # DTB read accesses
-system.cpu1.dtb.write_hits                     628916                       # DTB write hits
-system.cpu1.dtb.write_misses                     1890                       # DTB write misses
-system.cpu1.dtb.write_acv                          35                       # DTB write access violations
-system.cpu1.dtb.write_accesses                 104365                       # DTB write accesses
-system.cpu1.dtb.data_hits                     1816083                       # DTB hits
-system.cpu1.dtb.data_misses                     10879                       # DTB misses
-system.cpu1.dtb.data_acv                           41                       # DTB access violations
-system.cpu1.dtb.data_accesses                  380716                       # DTB accesses
-system.cpu1.itb.fetch_hits                     316911                       # ITB hits
-system.cpu1.itb.fetch_misses                     5517                       # ITB misses
-system.cpu1.itb.fetch_acv                         125                       # ITB acv
-system.cpu1.itb.fetch_accesses                 322428                       # ITB accesses
+system.cpu1.dtb.read_hits                     3015540                       # DTB read hits
+system.cpu1.dtb.read_misses                     12269                       # DTB read misses
+system.cpu1.dtb.read_acv                            5                       # DTB read access violations
+system.cpu1.dtb.read_accesses                  293761                       # DTB read accesses
+system.cpu1.dtb.write_hits                    1836726                       # DTB write hits
+system.cpu1.dtb.write_misses                     2353                       # DTB write misses
+system.cpu1.dtb.write_acv                          39                       # DTB write access violations
+system.cpu1.dtb.write_accesses                 109652                       # DTB write accesses
+system.cpu1.dtb.data_hits                     4852266                       # DTB hits
+system.cpu1.dtb.data_misses                     14622                       # DTB misses
+system.cpu1.dtb.data_acv                           44                       # DTB access violations
+system.cpu1.dtb.data_accesses                  403413                       # DTB accesses
+system.cpu1.itb.fetch_hits                     632341                       # ITB hits
+system.cpu1.itb.fetch_misses                     5352                       # ITB misses
+system.cpu1.itb.fetch_acv                          51                       # ITB acv
+system.cpu1.itb.fetch_accesses                 637693                       # ITB accesses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.read_acv                            0                       # DTB read access violations
@@ -1532,553 +1526,554 @@ system.cpu1.itb.data_hits                           0                       # DT
 system.cpu1.itb.data_misses                         0                       # DTB misses
 system.cpu1.itb.data_acv                            0                       # DTB access violations
 system.cpu1.itb.data_accesses                       0                       # DTB accesses
-system.cpu1.numCycles                         8637240                       # number of cpu cycles simulated
+system.cpu1.numCycles                        26335588                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles           2818807                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts                       7093634                       # Number of instructions fetch has processed
-system.cpu1.fetch.Branches                    1483279                       # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches            562823                       # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles                      1271731                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles                 278690                       # Number of cycles fetch has spent squashing
-system.cpu1.fetch.BlockedCycles               3719491                       # Number of cycles fetch has spent blocked
-system.cpu1.fetch.MiscStallCycles               23500                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingTrapStallCycles        54196                       # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles        48363                       # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles           46                       # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines                   894062                       # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes                29430                       # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.rateDist::samples           8117811                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean             0.873836                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev            2.252237                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.icacheStallCycles           9800268                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts                      22981944                       # Number of instructions fetch has processed
+system.cpu1.fetch.Branches                    5770916                       # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches           1827197                       # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles                     14019681                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles                 419510                       # Number of cycles fetch has spent squashing
+system.cpu1.fetch.TlbCycles                       307                       # Number of cycles fetch has spent waiting for tlb
+system.cpu1.fetch.MiscStallCycles               23776                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingTrapStallCycles       208449                       # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles       196331                       # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles           53                       # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines                  2522136                       # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes                89875                       # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.rateDist::samples          24458620                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean             0.939626                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev            2.331670                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0                 6846080     84.33%     84.33% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1                   64163      0.79%     85.12% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2                  148479      1.83%     86.95% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3                  110798      1.36%     88.32% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4                  183312      2.26%     90.58% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5                   76211      0.94%     91.52% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6                   83539      1.03%     92.54% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7                   57250      0.71%     93.25% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8                  547979      6.75%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0                20375648     83.31%     83.31% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1                  230665      0.94%     84.25% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2                  464859      1.90%     86.15% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3                  295118      1.21%     87.36% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4                  600413      2.45%     89.81% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5                  204861      0.84%     90.65% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6                  257669      1.05%     91.70% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7                  270860      1.11%     92.81% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8                 1758527      7.19%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total             8117811                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate                 0.171731                       # Number of branch fetches per cycle
-system.cpu1.fetch.rate                       0.821285                       # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles                 2872853                       # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles              3821739                       # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles                  1206360                       # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles                38891                       # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles                177967                       # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved               63499                       # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred                 3800                       # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts               6911640                       # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts                11536                       # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles                177967                       # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles                 2981399                       # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles                 177384                       # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles       3223332                       # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles                  1138018                       # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles               419709                       # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts               6319378                       # Number of instructions processed by rename
-system.cpu1.rename.ROBFullEvents                  203                       # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents                 45248                       # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LQFullEvents                  5428                       # Number of times rename has blocked due to LQ full
-system.cpu1.rename.SQFullEvents                135690                       # Number of times rename has blocked due to SQ full
-system.cpu1.rename.RenamedOperands            4267087                       # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups              7667393                       # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups         7641550                       # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups            21648                       # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps              3453234                       # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps                  813853                       # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts            270338                       # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts         17002                       # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts                  1051064                       # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads             1262745                       # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores             687524                       # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads           118324                       # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores           74010                       # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded                   5585108                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded             271421                       # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued                  5341703                       # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued            20645                       # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined        1049804                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined       612834                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved        207573                       # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples      8117811                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean        0.658023                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev       1.347544                       # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::total            24458620                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate                 0.219130                       # Number of branch fetches per cycle
+system.cpu1.fetch.rate                       0.872657                       # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles                 8213195                       # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles             12716086                       # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles                  2925937                       # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles               406668                       # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles                196733                       # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved              189397                       # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred                13167                       # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts              19294426                       # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts                40930                       # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles                196733                       # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles                 8443455                       # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles                3954170                       # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles       7253500                       # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles                  3074788                       # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles              1535972                       # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts              18421784                       # Number of instructions processed by rename
+system.cpu1.rename.ROBFullEvents                 5378                       # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents                385976                       # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LQFullEvents                 36959                       # Number of times rename has blocked due to LQ full
+system.cpu1.rename.SQFullEvents                551165                       # Number of times rename has blocked due to SQ full
+system.cpu1.rename.RenamedOperands           12165906                       # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups             21959681                       # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups        21890085                       # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups            63650                       # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps             10221482                       # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps                 1944424                       # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts            582778                       # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts         59316                       # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts                  3316426                       # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads             3128488                       # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores            1940399                       # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads           395849                       # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores          259099                       # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded                  16224994                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded             722304                       # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued                 15758531                       # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued            26415                       # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined        2553169                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined      1203962                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved        524576                       # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples     24458620                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean        0.644294                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev       1.366216                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0            5813637     71.62%     71.62% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1            1034901     12.75%     84.36% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2             447279      5.51%     89.87% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3             322285      3.97%     93.84% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4             244246      3.01%     96.85% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5             126246      1.56%     98.41% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::6              72876      0.90%     99.31% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::7              50809      0.63%     99.93% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::8               5532      0.07%    100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0           17964380     73.45%     73.45% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1            2773024     11.34%     84.79% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2            1191873      4.87%     89.66% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3             895755      3.66%     93.32% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4             840464      3.44%     96.76% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5             400907      1.64%     98.40% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::6             238226      0.97%     99.37% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::7             113179      0.46%     99.83% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::8              40812      0.17%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total        8117811                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total       24458620                       # Number of insts issued each cycle
 system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu                   4295      3.26%      3.26% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult                     0      0.00%      3.26% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv                      0      0.00%      3.26% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      3.26% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      3.26% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      3.26% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult                   0      0.00%      3.26% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      3.26% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      3.26% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      3.26% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      3.26% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      3.26% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      3.26% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      3.26% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      3.26% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult                    0      0.00%      3.26% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      3.26% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift                   0      0.00%      3.26% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      3.26% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      3.26% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      3.26% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      3.26% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      3.26% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      3.26% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      3.26% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      3.26% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      3.26% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      3.26% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      3.26% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead                 76591     58.14%     61.40% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite                50850     38.60%    100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu                  56470     15.54%     15.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult                     0      0.00%     15.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv                      0      0.00%     15.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd                    0      0.00%     15.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp                    0      0.00%     15.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt                    0      0.00%     15.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult                   0      0.00%     15.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv                    0      0.00%     15.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%     15.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd                     0      0.00%     15.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%     15.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu                     0      0.00%     15.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp                     0      0.00%     15.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt                     0      0.00%     15.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc                    0      0.00%     15.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult                    0      0.00%     15.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%     15.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift                   0      0.00%     15.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%     15.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%     15.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%     15.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%     15.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%     15.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%     15.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%     15.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%     15.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%     15.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%     15.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%     15.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead                184321     50.72%     66.26% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite               122598     33.74%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu1.iq.FU_type_0::No_OpClass             3518      0.07%      0.07% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu              3268625     61.19%     61.26% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult                9680      0.18%     61.44% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     61.44% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd               8881      0.17%     61.60% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     61.60% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     61.60% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     61.60% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv               1759      0.03%     61.64% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     61.64% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     61.64% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     61.64% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     61.64% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     61.64% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     61.64% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     61.64% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     61.64% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     61.64% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     61.64% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     61.64% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     61.64% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     61.64% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     61.64% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     61.64% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     61.64% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     61.64% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc             0      0.00%     61.64% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     61.64% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     61.64% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     61.64% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead             1232456     23.07%     84.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite             646098     12.10%     96.80% # Type of FU issued
-system.cpu1.iq.FU_type_0::IprAccess            170686      3.20%    100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::No_OpClass             3518      0.02%      0.02% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu             10371294     65.81%     65.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult               24284      0.15%     65.99% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     65.99% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd              11773      0.07%     66.06% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     66.06% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     66.06% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     66.06% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv               1759      0.01%     66.08% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     66.08% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     66.08% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     66.08% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     66.08% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     66.08% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     66.08% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     66.08% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     66.08% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     66.08% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     66.08% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     66.08% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     66.08% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     66.08% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     66.08% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     66.08% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     66.08% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     66.08% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc             0      0.00%     66.08% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     66.08% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     66.08% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     66.08% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead             3139820     19.92%     86.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite            1865147     11.84%     97.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::IprAccess            340936      2.16%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total               5341703                       # Type of FU issued
-system.cpu1.iq.rate                          0.618450                       # Inst issue rate
-system.cpu1.iq.fu_busy_cnt                     131736                       # FU busy when requested
-system.cpu1.iq.fu_busy_rate                  0.024662                       # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads          18885884                       # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes          6873502                       # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses      5132762                       # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads              67714                       # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes             33978                       # Number of floating instruction queue writes
-system.cpu1.iq.fp_inst_queue_wakeup_accesses        32480                       # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses               5434957                       # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses                  34964                       # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads           63957                       # Number of loads that had data forwarded from stores
+system.cpu1.iq.FU_type_0::total              15758531                       # Type of FU issued
+system.cpu1.iq.rate                          0.598374                       # Inst issue rate
+system.cpu1.iq.fu_busy_cnt                     363389                       # FU busy when requested
+system.cpu1.iq.fu_busy_rate                  0.023060                       # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads          56111313                       # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes         19387392                       # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses     15262127                       # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads             254173                       # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_writes            119441                       # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_wakeup_accesses       117263                       # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.int_alu_accesses              15982004                       # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses                 136398                       # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads          157695                       # Number of loads that had data forwarded from stores
 system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads       266370                       # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses          353                       # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation         1238                       # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores        98626                       # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads       453605                       # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses         1302                       # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation         6552                       # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores       197079                       # Number of stores squashed
 system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads          353                       # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked        72939                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread0.rescheduledLoads         5589                       # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked        74646                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles                177967                       # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles                  80772                       # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles                78093                       # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts            6077668                       # Number of instructions dispatched to IQ
-system.cpu1.iew.iewDispSquashedInsts            83087                       # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts              1262745                       # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts              687524                       # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts            253926                       # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents                  4593                       # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents                73335                       # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents          1238                       # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect         19913                       # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect        60148                       # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts               80061                       # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts              5287979                       # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts              1198929                       # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts            53724                       # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewSquashCycles                196733                       # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles                3102898                       # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles               407577                       # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts           17959821                       # Number of instructions dispatched to IQ
+system.cpu1.iew.iewDispSquashedInsts            47400                       # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispLoadInsts              3128488                       # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts             1940399                       # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts            647154                       # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents                 24325                       # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents               312873                       # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents          6552                       # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect         58721                       # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect       143362                       # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts              202083                       # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts             15559963                       # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts              3035862                       # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts           198568                       # Number of squashed instructions skipped in execute
 system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu1.iew.exec_nop                       221139                       # number of nop insts executed
-system.cpu1.iew.exec_refs                     1832774                       # number of memory reference insts executed
-system.cpu1.iew.exec_branches                  762873                       # Number of branches executed
-system.cpu1.iew.exec_stores                    633845                       # Number of stores executed
-system.cpu1.iew.exec_rate                    0.612230                       # Inst execution rate
-system.cpu1.iew.wb_sent                       5189273                       # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count                      5165242                       # cumulative count of insts written-back
-system.cpu1.iew.wb_producers                  2532511                       # num instructions producing a value
-system.cpu1.iew.wb_consumers                  3587094                       # num instructions consuming a value
+system.cpu1.iew.exec_nop                      1012523                       # number of nop insts executed
+system.cpu1.iew.exec_refs                     4881099                       # number of memory reference insts executed
+system.cpu1.iew.exec_branches                 2446532                       # Number of branches executed
+system.cpu1.iew.exec_stores                   1845237                       # Number of stores executed
+system.cpu1.iew.exec_rate                    0.590834                       # Inst execution rate
+system.cpu1.iew.wb_sent                      15420680                       # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count                     15379390                       # cumulative count of insts written-back
+system.cpu1.iew.wb_producers                  7566791                       # num instructions producing a value
+system.cpu1.iew.wb_consumers                 10761562                       # num instructions consuming a value
 system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu1.iew.wb_rate                      0.598020                       # insts written-back per cycle
-system.cpu1.iew.wb_fanout                    0.706006                       # average fanout of values written-back
+system.cpu1.iew.wb_rate                      0.583977                       # insts written-back per cycle
+system.cpu1.iew.wb_fanout                    0.703131                       # average fanout of values written-back
 system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.commit.commitSquashedInsts        1065222                       # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls          63848                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts            75650                       # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples      7939844                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean     0.623951                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev     1.560784                       # Number of insts commited each cycle
+system.cpu1.commit.commitSquashedInsts        2776166                       # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls         197728                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts           185190                       # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples     23976589                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean     0.630910                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev     1.597118                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0      6043541     76.12%     76.12% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1       925286     11.65%     87.77% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2       320402      4.04%     91.81% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3       190890      2.40%     94.21% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4       129096      1.63%     95.84% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5        57238      0.72%     96.56% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6        65164      0.82%     97.38% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7        44060      0.55%     97.93% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8       164167      2.07%    100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0     18550941     77.37%     77.37% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1      2272481      9.48%     86.85% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2      1151381      4.80%     91.65% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3       578443      2.41%     94.06% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4       385291      1.61%     95.67% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5       189866      0.79%     96.46% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6       157998      0.66%     97.12% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7       143488      0.60%     97.72% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8       546700      2.28%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total      7939844                       # Number of insts commited each cycle
-system.cpu1.commit.committedInsts             4954074                       # Number of instructions committed
-system.cpu1.commit.committedOps               4954074                       # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total     23976589                       # Number of insts commited each cycle
+system.cpu1.commit.committedInsts            15127070                       # Number of instructions committed
+system.cpu1.commit.committedOps              15127070                       # Number of ops (including micro ops) committed
 system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu1.commit.refs                       1585273                       # Number of memory references committed
-system.cpu1.commit.loads                       996375                       # Number of loads committed
-system.cpu1.commit.membars                      16576                       # Number of memory barriers committed
-system.cpu1.commit.branches                    700739                       # Number of branches committed
-system.cpu1.commit.fp_insts                     31280                       # Number of committed floating point instructions.
-system.cpu1.commit.int_insts                  4632533                       # Number of committed integer instructions.
-system.cpu1.commit.function_calls               77324                       # Number of function calls committed.
-system.cpu1.commit.op_class_0::No_OpClass       191990      3.88%      3.88% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntAlu         2969211     59.93%     63.81% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntMult           9565      0.19%     64.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntDiv               0      0.00%     64.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatAdd          8881      0.18%     64.18% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     64.18% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     64.18% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatMult            0      0.00%     64.18% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatDiv          1759      0.04%     64.22% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     64.22% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     64.22% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     64.22% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     64.22% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     64.22% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     64.22% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     64.22% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMult             0      0.00%     64.22% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     64.22% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShift            0      0.00%     64.22% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     64.22% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     64.22% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     64.22% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     64.22% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     64.22% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     64.22% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     64.22% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMisc            0      0.00%     64.22% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     64.22% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     64.22% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     64.22% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemRead        1012951     20.45%     84.66% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemWrite        589031     11.89%     96.55% # Class of committed instruction
-system.cpu1.commit.op_class_0::IprAccess       170686      3.45%    100.00% # Class of committed instruction
+system.cpu1.commit.refs                       4418203                       # Number of memory references committed
+system.cpu1.commit.loads                      2674883                       # Number of loads committed
+system.cpu1.commit.membars                      66521                       # Number of memory barriers committed
+system.cpu1.commit.branches                   2263870                       # Number of branches committed
+system.cpu1.commit.fp_insts                    115331                       # Number of committed floating point instructions.
+system.cpu1.commit.int_insts                 13957396                       # Number of committed integer instructions.
+system.cpu1.commit.function_calls              240978                       # Number of function calls committed.
+system.cpu1.commit.op_class_0::No_OpClass       845832      5.59%      5.59% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntAlu         9417463     62.26%     67.85% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntMult          23911      0.16%     68.01% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntDiv               0      0.00%     68.01% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatAdd         11769      0.08%     68.08% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     68.08% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     68.08% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatMult            0      0.00%     68.08% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatDiv          1759      0.01%     68.09% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     68.09% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     68.09% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     68.09% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     68.09% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     68.09% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     68.09% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     68.09% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMult             0      0.00%     68.09% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     68.09% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShift            0      0.00%     68.09% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     68.09% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     68.09% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     68.09% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     68.09% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     68.09% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     68.09% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     68.09% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMisc            0      0.00%     68.09% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     68.09% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     68.09% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     68.09% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemRead        2741404     18.12%     86.22% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemWrite       1743996     11.53%     97.75% # Class of committed instruction
+system.cpu1.commit.op_class_0::IprAccess       340936      2.25%    100.00% # Class of committed instruction
 system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::total          4954074                       # Class of committed instruction
-system.cpu1.commit.bw_lim_events               164167                       # number cycles where commit BW limit reached
+system.cpu1.commit.op_class_0::total         15127070                       # Class of committed instruction
+system.cpu1.commit.bw_lim_events               546700                       # number cycles where commit BW limit reached
 system.cpu1.commit.bw_limited                       0                       # number of insts not committed due to BW limits
-system.cpu1.rob.rob_reads                    13715407                       # The number of ROB reads
-system.cpu1.rob.rob_writes                   12215098                       # The number of ROB writes
-system.cpu1.timesIdled                          57372                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles                         519429                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles                  3803095502                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts                    4765602                       # Number of Instructions Simulated
-system.cpu1.committedOps                      4765602                       # Number of Ops (including micro ops) Simulated
-system.cpu1.cpi                              1.812413                       # CPI: Cycles Per Instruction
-system.cpu1.cpi_total                        1.812413                       # CPI: Total CPI of All Threads
-system.cpu1.ipc                              0.551751                       # IPC: Instructions Per Cycle
-system.cpu1.ipc_total                        0.551751                       # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads                 6848640                       # number of integer regfile reads
-system.cpu1.int_regfile_writes                3746417                       # number of integer regfile writes
-system.cpu1.fp_regfile_reads                    21244                       # number of floating regfile reads
-system.cpu1.fp_regfile_writes                   19994                       # number of floating regfile writes
-system.cpu1.misc_regfile_reads                 693471                       # number of misc regfile reads
-system.cpu1.misc_regfile_writes                115172                       # number of misc regfile writes
-system.cpu1.icache.tags.replacements            94727                       # number of replacements
-system.cpu1.icache.tags.tagsinuse          453.369242                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs             794363                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs            95239                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs             8.340732                       # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle     1880860642000                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst   453.369242                       # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst     0.885487                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total     0.885487                       # Average percentage of cache occupancy
+system.cpu1.rob.rob_reads                    41251186                       # The number of ROB reads
+system.cpu1.rob.rob_writes                   36287802                       # The number of ROB writes
+system.cpu1.timesIdled                         194891                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles                        1876968                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles                  3779240330                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.committedInsts                   14284756                       # Number of Instructions Simulated
+system.cpu1.committedOps                     14284756                       # Number of Ops (including micro ops) Simulated
+system.cpu1.cpi                              1.843615                       # CPI: Cycles Per Instruction
+system.cpu1.cpi_total                        1.843615                       # CPI: Total CPI of All Threads
+system.cpu1.ipc                              0.542413                       # IPC: Instructions Per Cycle
+system.cpu1.ipc_total                        0.542413                       # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads                20099122                       # number of integer regfile reads
+system.cpu1.int_regfile_writes               11015819                       # number of integer regfile writes
+system.cpu1.fp_regfile_reads                    63024                       # number of floating regfile reads
+system.cpu1.fp_regfile_writes                   62672                       # number of floating regfile writes
+system.cpu1.misc_regfile_reads                1065455                       # number of misc regfile reads
+system.cpu1.misc_regfile_writes                283847                       # number of misc regfile writes
+system.cpu1.icache.tags.replacements           353746                       # number of replacements
+system.cpu1.icache.tags.tagsinuse          504.553851                       # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs            2153244                       # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs           354258                       # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs             6.078180                       # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle      47615844250                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tags.occ_blocks::cpu1.inst   504.553851                       # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst     0.985457                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total     0.985457                       # Average percentage of cache occupancy
 system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::2          512                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::2          508                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::3            4                       # Occupied blocks per task id
 system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses           989361                       # Number of tag accesses
-system.cpu1.icache.tags.data_accesses          989361                       # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst       794363                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total         794363                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst       794363                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total          794363                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst       794363                       # number of overall hits
-system.cpu1.icache.overall_hits::total         794363                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst        99697                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total        99697                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst        99697                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total         99697                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst        99697                       # number of overall misses
-system.cpu1.icache.overall_misses::total        99697                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   1381976879                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total   1381976879                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst   1381976879                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total   1381976879                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst   1381976879                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total   1381976879                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst       894060                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total       894060                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst       894060                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total       894060                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst       894060                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total       894060                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.111510                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.111510                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.111510                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.111510                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.111510                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.111510                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13861.769953                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 13861.769953                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13861.769953                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 13861.769953                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13861.769953                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 13861.769953                       # average overall miss latency
-system.cpu1.icache.blocked_cycles::no_mshrs          350                       # number of cycles access was blocked
+system.cpu1.icache.tags.tag_accesses          2876460                       # Number of tag accesses
+system.cpu1.icache.tags.data_accesses         2876460                       # Number of data accesses
+system.cpu1.icache.ReadReq_hits::cpu1.inst      2153244                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total        2153244                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst      2153244                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total         2153244                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst      2153244                       # number of overall hits
+system.cpu1.icache.overall_hits::total        2153244                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst       368891                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total       368891                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst       368891                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total        368891                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst       368891                       # number of overall misses
+system.cpu1.icache.overall_misses::total       368891                       # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   5137931940                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total   5137931940                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst   5137931940                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total   5137931940                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst   5137931940                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total   5137931940                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst      2522135                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total      2522135                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst      2522135                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total      2522135                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst      2522135                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total      2522135                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.146261                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.146261                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.146261                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.146261                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.146261                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.146261                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13928.049044                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 13928.049044                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13928.049044                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 13928.049044                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13928.049044                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 13928.049044                       # average overall miss latency
+system.cpu1.icache.blocked_cycles::no_mshrs         1327                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.icache.blocked::no_mshrs               23                       # number of cycles access was blocked
+system.cpu1.icache.blocked::no_mshrs               55                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_mshrs    15.217391                       # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_mshrs    24.127273                       # average number of cycles each access was blocked
 system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst         4396                       # number of ReadReq MSHR hits
-system.cpu1.icache.ReadReq_mshr_hits::total         4396                       # number of ReadReq MSHR hits
-system.cpu1.icache.demand_mshr_hits::cpu1.inst         4396                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.demand_mshr_hits::total         4396                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.overall_mshr_hits::cpu1.inst         4396                       # number of overall MSHR hits
-system.cpu1.icache.overall_mshr_hits::total         4396                       # number of overall MSHR hits
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst        95301                       # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total        95301                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst        95301                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total        95301                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst        95301                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total        95301                       # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   1139734069                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total   1139734069                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   1139734069                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total   1139734069                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   1139734069                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total   1139734069                       # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.106594                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.106594                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.106594                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.106594                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.106594                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.106594                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11959.308601                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11959.308601                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11959.308601                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 11959.308601                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11959.308601                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 11959.308601                       # average overall mshr miss latency
+system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst        14566                       # number of ReadReq MSHR hits
+system.cpu1.icache.ReadReq_mshr_hits::total        14566                       # number of ReadReq MSHR hits
+system.cpu1.icache.demand_mshr_hits::cpu1.inst        14566                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.demand_mshr_hits::total        14566                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.overall_mshr_hits::cpu1.inst        14566                       # number of overall MSHR hits
+system.cpu1.icache.overall_mshr_hits::total        14566                       # number of overall MSHR hits
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       354325                       # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total       354325                       # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst       354325                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total       354325                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst       354325                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total       354325                       # number of overall MSHR misses
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   4259071697                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total   4259071697                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   4259071697                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total   4259071697                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   4259071697                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total   4259071697                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.140486                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.140486                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.140486                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total     0.140486                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.140486                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total     0.140486                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12020.240449                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12020.240449                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12020.240449                       # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total 12020.240449                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12020.240449                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total 12020.240449                       # average overall mshr miss latency
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.dcache.tags.replacements            45361                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse          428.999436                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs            1451630                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs            45680                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs            31.778240                       # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle     1880566804000                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data   428.999436                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data     0.837890                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total     0.837890                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024          319                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2          319                       # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024     0.623047                       # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses          6609919                       # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses         6609919                       # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data       960992                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total         960992                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data       477143                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total        477143                       # number of WriteReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        12504                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total        12504                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data        10799                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total        10799                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data      1438135                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total         1438135                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data      1438135                       # number of overall hits
-system.cpu1.dcache.overall_hits::total        1438135                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data        81302                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total        81302                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data        95545                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total        95545                       # number of WriteReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data         1156                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total         1156                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data          573                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total          573                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data       176847                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total        176847                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data       176847                       # number of overall misses
-system.cpu1.dcache.overall_misses::total       176847                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   1110177095                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total   1110177095                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   5046033431                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total   5046033431                       # number of WriteReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data     13905498                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total     13905498                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data      4132075                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total      4132075                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data   6156210526                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total   6156210526                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data   6156210526                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total   6156210526                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data      1042294                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total      1042294                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data       572688                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total       572688                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        13660                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total        13660                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        11372                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total        11372                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data      1614982                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total      1614982                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data      1614982                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total      1614982                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.078003                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.078003                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.166836                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.166836                       # miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.084627                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.084627                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.050387                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total     0.050387                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.109504                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.109504                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.109504                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.109504                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13654.978906                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 13654.978906                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 52813.160615                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 52813.160615                       # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12028.977509                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 12028.977509                       # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data  7211.300175                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total  7211.300175                       # average StoreCondReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 34810.941243                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 34810.941243                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 34810.941243                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 34810.941243                       # average overall miss latency
-system.cpu1.dcache.blocked_cycles::no_mshrs       236601                       # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_mshrs             6165                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs    38.378102                       # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu1.dcache.tags.replacements           360788                       # number of replacements
+system.cpu1.dcache.tags.tagsinuse          496.086183                       # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs            3613456                       # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs           361109                       # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs            10.006552                       # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle      40126349500                       # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.occ_blocks::cpu1.data   496.086183                       # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data     0.968918                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total     0.968918                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_task_id_blocks::1024          321                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2          321                       # Occupied blocks per task id
+system.cpu1.dcache.tags.occ_task_id_percent::1024     0.626953                       # Percentage of cache occupancy per task id
+system.cpu1.dcache.tags.tag_accesses         18510307                       # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses        18510307                       # Number of data accesses
+system.cpu1.dcache.ReadReq_hits::cpu1.data      2220866                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total        2220866                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data      1307515                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total       1307515                       # number of WriteReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        45364                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total        45364                       # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data        48883                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total        48883                       # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data      3528381                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total         3528381                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data      3528381                       # number of overall hits
+system.cpu1.dcache.overall_hits::total        3528381                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data       524895                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total       524895                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data       378889                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total       378889                       # number of WriteReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data         8897                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total         8897                       # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data          786                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total          786                       # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data       903784                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total        903784                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data       903784                       # number of overall misses
+system.cpu1.dcache.overall_misses::total       903784                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   8191623763                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total   8191623763                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  14087810149                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total  14087810149                       # number of WriteReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    135761491                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total    135761491                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data      5726098                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total      5726098                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data  22279433912                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total  22279433912                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data  22279433912                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total  22279433912                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data      2745761                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total      2745761                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data      1686404                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total      1686404                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        54261                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total        54261                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        49669                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total        49669                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data      4432165                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total      4432165                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data      4432165                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total      4432165                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.191166                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.191166                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.224673                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.224673                       # miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.163967                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.163967                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.015825                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total     0.015825                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.203915                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.203915                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.203915                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.203915                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15606.214125                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 15606.214125                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 37181.892715                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 37181.892715                       # average WriteReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15259.243678                       # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15259.243678                       # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data  7285.111959                       # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total  7285.111959                       # average StoreCondReq miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 24651.281625                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 24651.281625                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 24651.281625                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 24651.281625                       # average overall miss latency
+system.cpu1.dcache.blocked_cycles::no_mshrs       560522                       # number of cycles access was blocked
+system.cpu1.dcache.blocked_cycles::no_targets          381                       # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_mshrs            27149                       # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_targets             19                       # number of cycles access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_mshrs    20.646138                       # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_targets    20.052632                       # average number of cycles each access was blocked
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks        24956                       # number of writebacks
-system.cpu1.dcache.writebacks::total            24956                       # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data        46173                       # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total        46173                       # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data        80581                       # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total        80581                       # number of WriteReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data          235                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::total          235                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data       126754                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total       126754                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data       126754                       # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total       126754                       # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data        35129                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total        35129                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        14964                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total        14964                       # number of WriteReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data          921                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total          921                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data          573                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total          573                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data        50093                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total        50093                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data        50093                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total        50093                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data    398615352                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total    398615352                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data    730663501                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total    730663501                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data      8358752                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total      8358752                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data      2984925                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total      2984925                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   1129278853                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total   1129278853                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   1129278853                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total   1129278853                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data     22397000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total     22397000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    533147000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    533147000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data    555544000                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total    555544000                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.033704                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.033704                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.026129                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.026129                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.067423                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.067423                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.050387                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.050387                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.031018                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.031018                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.031018                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.031018                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11347.187566                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11347.187566                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 48828.087477                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 48828.087477                       # average WriteReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data  9075.735071                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total  9075.735071                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data  5209.293194                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total  5209.293194                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22543.645879                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22543.645879                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22543.645879                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22543.645879                       # average overall mshr miss latency
+system.cpu1.dcache.writebacks::writebacks       273838                       # number of writebacks
+system.cpu1.dcache.writebacks::total           273838                       # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data       229504                       # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total       229504                       # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data       313811                       # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total       313811                       # number of WriteReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data         1705                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::total         1705                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data       543315                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total       543315                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data       543315                       # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total       543315                       # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       295391                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total       295391                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        65078                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total        65078                       # number of WriteReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         7192                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total         7192                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data          786                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total          786                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data       360469                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total       360469                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data       360469                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total       360469                       # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   3818838154                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total   3818838154                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   2138006676                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total   2138006676                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     81043507                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     81043507                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data      4153902                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total      4153902                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   5956844830                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total   5956844830                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   5956844830                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total   5956844830                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    490391500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total    490391500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    941927000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    941927000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   1432318500                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total   1432318500                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.107581                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.107581                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.038590                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.038590                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.132545                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.132545                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.015825                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.015825                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.081330                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total     0.081330                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.081330                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total     0.081330                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12928.078899                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12928.078899                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32852.986816                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 32852.986816                       # average WriteReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11268.563265                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11268.563265                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data  5284.862595                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total  5284.862595                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16525.262450                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16525.262450                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16525.262450                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16525.262450                       # average overall mshr miss latency
 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
@@ -2087,161 +2082,161 @@ system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf
 system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                    6410                       # number of quiesce instructions executed
-system.cpu0.kern.inst.hwrei                    202830                       # number of hwrei instructions executed
-system.cpu0.kern.ipl_count::0                   72673     40.72%     40.72% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::21                    131      0.07%     40.80% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::22                   1926      1.08%     41.87% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::30                      6      0.00%     41.88% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::31                 103726     58.12%    100.00% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::total              178462                       # number of times we switched to this ipl
-system.cpu0.kern.ipl_good::0                    71304     49.29%     49.29% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::21                     131      0.09%     49.38% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::22                    1926      1.33%     50.71% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::30                       6      0.00%     50.72% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::31                   71298     49.28%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::total               144665                       # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_ticks::0            1863558813000     97.76%     97.76% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::21               63845500      0.00%     97.77% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::22              565237000      0.03%     97.80% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::30                3385500      0.00%     97.80% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::31            42015112000      2.20%    100.00% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::total        1906206393000                       # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_used::0                 0.981162                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.inst.quiesce                    4820                       # number of quiesce instructions executed
+system.cpu0.kern.inst.hwrei                    161850                       # number of hwrei instructions executed
+system.cpu0.kern.ipl_count::0                   55184     39.67%     39.67% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::21                    131      0.09%     39.77% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::22                   1924      1.38%     41.15% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::30                     16      0.01%     41.16% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::31                  81844     58.84%    100.00% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::total              139099                       # number of times we switched to this ipl
+system.cpu0.kern.ipl_good::0                    54289     49.07%     49.07% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::21                     131      0.12%     49.19% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::22                    1924      1.74%     50.93% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::30                      16      0.01%     50.94% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::31                   54273     49.06%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::total               110633                       # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_ticks::0            1865924468000     98.05%     98.05% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::21               60967000      0.00%     98.05% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::22              531593000      0.03%     98.08% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::30                8367000      0.00%     98.08% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::31            36597541500      1.92%    100.00% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::total        1903122936500                       # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_used::0                 0.983782                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::21                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::31                0.687369                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::total             0.810621                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.syscall::2                         8      3.42%      3.42% # number of syscalls executed
-system.cpu0.kern.syscall::3                        20      8.55%     11.97% # number of syscalls executed
-system.cpu0.kern.syscall::4                         4      1.71%     13.68% # number of syscalls executed
-system.cpu0.kern.syscall::6                        33     14.10%     27.78% # number of syscalls executed
-system.cpu0.kern.syscall::12                        1      0.43%     28.21% # number of syscalls executed
-system.cpu0.kern.syscall::17                       10      4.27%     32.48% # number of syscalls executed
-system.cpu0.kern.syscall::19                       10      4.27%     36.75% # number of syscalls executed
-system.cpu0.kern.syscall::20                        6      2.56%     39.32% # number of syscalls executed
-system.cpu0.kern.syscall::23                        1      0.43%     39.74% # number of syscalls executed
-system.cpu0.kern.syscall::24                        3      1.28%     41.03% # number of syscalls executed
-system.cpu0.kern.syscall::33                        8      3.42%     44.44% # number of syscalls executed
-system.cpu0.kern.syscall::41                        2      0.85%     45.30% # number of syscalls executed
-system.cpu0.kern.syscall::45                       39     16.67%     61.97% # number of syscalls executed
-system.cpu0.kern.syscall::47                        3      1.28%     63.25% # number of syscalls executed
-system.cpu0.kern.syscall::48                       10      4.27%     67.52% # number of syscalls executed
-system.cpu0.kern.syscall::54                       10      4.27%     71.79% # number of syscalls executed
-system.cpu0.kern.syscall::58                        1      0.43%     72.22% # number of syscalls executed
-system.cpu0.kern.syscall::59                        6      2.56%     74.79% # number of syscalls executed
-system.cpu0.kern.syscall::71                       27     11.54%     86.32% # number of syscalls executed
-system.cpu0.kern.syscall::73                        3      1.28%     87.61% # number of syscalls executed
-system.cpu0.kern.syscall::74                        7      2.99%     90.60% # number of syscalls executed
-system.cpu0.kern.syscall::87                        1      0.43%     91.03% # number of syscalls executed
-system.cpu0.kern.syscall::90                        3      1.28%     92.31% # number of syscalls executed
-system.cpu0.kern.syscall::92                        9      3.85%     96.15% # number of syscalls executed
-system.cpu0.kern.syscall::97                        2      0.85%     97.01% # number of syscalls executed
-system.cpu0.kern.syscall::98                        2      0.85%     97.86% # number of syscalls executed
-system.cpu0.kern.syscall::132                       1      0.43%     98.29% # number of syscalls executed
-system.cpu0.kern.syscall::144                       2      0.85%     99.15% # number of syscalls executed
-system.cpu0.kern.syscall::147                       2      0.85%    100.00% # number of syscalls executed
-system.cpu0.kern.syscall::total                   234                       # number of syscalls executed
+system.cpu0.kern.ipl_used::31                0.663127                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used::total             0.795354                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.syscall::2                         8      3.56%      3.56% # number of syscalls executed
+system.cpu0.kern.syscall::3                        19      8.44%     12.00% # number of syscalls executed
+system.cpu0.kern.syscall::4                         4      1.78%     13.78% # number of syscalls executed
+system.cpu0.kern.syscall::6                        33     14.67%     28.44% # number of syscalls executed
+system.cpu0.kern.syscall::12                        1      0.44%     28.89% # number of syscalls executed
+system.cpu0.kern.syscall::17                        9      4.00%     32.89% # number of syscalls executed
+system.cpu0.kern.syscall::19                       10      4.44%     37.33% # number of syscalls executed
+system.cpu0.kern.syscall::20                        6      2.67%     40.00% # number of syscalls executed
+system.cpu0.kern.syscall::23                        1      0.44%     40.44% # number of syscalls executed
+system.cpu0.kern.syscall::24                        3      1.33%     41.78% # number of syscalls executed
+system.cpu0.kern.syscall::33                        7      3.11%     44.89% # number of syscalls executed
+system.cpu0.kern.syscall::41                        2      0.89%     45.78% # number of syscalls executed
+system.cpu0.kern.syscall::45                       36     16.00%     61.78% # number of syscalls executed
+system.cpu0.kern.syscall::47                        3      1.33%     63.11% # number of syscalls executed
+system.cpu0.kern.syscall::48                       10      4.44%     67.56% # number of syscalls executed
+system.cpu0.kern.syscall::54                       10      4.44%     72.00% # number of syscalls executed
+system.cpu0.kern.syscall::58                        1      0.44%     72.44% # number of syscalls executed
+system.cpu0.kern.syscall::59                        6      2.67%     75.11% # number of syscalls executed
+system.cpu0.kern.syscall::71                       25     11.11%     86.22% # number of syscalls executed
+system.cpu0.kern.syscall::73                        3      1.33%     87.56% # number of syscalls executed
+system.cpu0.kern.syscall::74                        6      2.67%     90.22% # number of syscalls executed
+system.cpu0.kern.syscall::87                        1      0.44%     90.67% # number of syscalls executed
+system.cpu0.kern.syscall::90                        3      1.33%     92.00% # number of syscalls executed
+system.cpu0.kern.syscall::92                        9      4.00%     96.00% # number of syscalls executed
+system.cpu0.kern.syscall::97                        2      0.89%     96.89% # number of syscalls executed
+system.cpu0.kern.syscall::98                        2      0.89%     97.78% # number of syscalls executed
+system.cpu0.kern.syscall::132                       1      0.44%     98.22% # number of syscalls executed
+system.cpu0.kern.syscall::144                       2      0.89%     99.11% # number of syscalls executed
+system.cpu0.kern.syscall::147                       2      0.89%    100.00% # number of syscalls executed
+system.cpu0.kern.syscall::total                   225                       # number of syscalls executed
 system.cpu0.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
-system.cpu0.kern.callpal::wripir                   95      0.05%      0.05% # number of callpals executed
-system.cpu0.kern.callpal::wrmces                    1      0.00%      0.05% # number of callpals executed
-system.cpu0.kern.callpal::wrfen                     1      0.00%      0.05% # number of callpals executed
-system.cpu0.kern.callpal::wrvptptr                  1      0.00%      0.05% # number of callpals executed
-system.cpu0.kern.callpal::swpctx                 3930      2.10%      2.15% # number of callpals executed
-system.cpu0.kern.callpal::tbi                      51      0.03%      2.18% # number of callpals executed
-system.cpu0.kern.callpal::wrent                     7      0.00%      2.18% # number of callpals executed
-system.cpu0.kern.callpal::swpipl               171605     91.48%     93.66% # number of callpals executed
-system.cpu0.kern.callpal::rdps                   6547      3.49%     97.15% # number of callpals executed
-system.cpu0.kern.callpal::wrkgp                     1      0.00%     97.15% # number of callpals executed
-system.cpu0.kern.callpal::wrusp                     4      0.00%     97.15% # number of callpals executed
-system.cpu0.kern.callpal::rdusp                     9      0.00%     97.16% # number of callpals executed
-system.cpu0.kern.callpal::whami                     2      0.00%     97.16% # number of callpals executed
-system.cpu0.kern.callpal::rti                    4793      2.56%     99.72% # number of callpals executed
-system.cpu0.kern.callpal::callsys                 394      0.21%     99.93% # number of callpals executed
-system.cpu0.kern.callpal::imb                     139      0.07%    100.00% # number of callpals executed
-system.cpu0.kern.callpal::total                187581                       # number of callpals executed
-system.cpu0.kern.mode_switch::kernel             7378                       # number of protection mode switches
-system.cpu0.kern.mode_switch::user               1370                       # number of protection mode switches
+system.cpu0.kern.callpal::wripir                  105      0.07%      0.07% # number of callpals executed
+system.cpu0.kern.callpal::wrmces                    1      0.00%      0.07% # number of callpals executed
+system.cpu0.kern.callpal::wrfen                     1      0.00%      0.07% # number of callpals executed
+system.cpu0.kern.callpal::wrvptptr                  1      0.00%      0.07% # number of callpals executed
+system.cpu0.kern.callpal::swpctx                 2905      1.98%      2.05% # number of callpals executed
+system.cpu0.kern.callpal::tbi                      50      0.03%      2.09% # number of callpals executed
+system.cpu0.kern.callpal::wrent                     7      0.00%      2.09% # number of callpals executed
+system.cpu0.kern.callpal::swpipl               132721     90.43%     92.52% # number of callpals executed
+system.cpu0.kern.callpal::rdps                   6135      4.18%     96.70% # number of callpals executed
+system.cpu0.kern.callpal::wrkgp                     1      0.00%     96.70% # number of callpals executed
+system.cpu0.kern.callpal::wrusp                     3      0.00%     96.70% # number of callpals executed
+system.cpu0.kern.callpal::rdusp                     9      0.01%     96.71% # number of callpals executed
+system.cpu0.kern.callpal::whami                     2      0.00%     96.71% # number of callpals executed
+system.cpu0.kern.callpal::rti                    4306      2.93%     99.65% # number of callpals executed
+system.cpu0.kern.callpal::callsys                 382      0.26%     99.91% # number of callpals executed
+system.cpu0.kern.callpal::imb                     138      0.09%    100.00% # number of callpals executed
+system.cpu0.kern.callpal::total                146768                       # number of callpals executed
+system.cpu0.kern.mode_switch::kernel             6331                       # number of protection mode switches
+system.cpu0.kern.mode_switch::user               1342                       # number of protection mode switches
 system.cpu0.kern.mode_switch::idle                  0                       # number of protection mode switches
-system.cpu0.kern.mode_good::kernel               1369                      
-system.cpu0.kern.mode_good::user                 1370                      
+system.cpu0.kern.mode_good::kernel               1341                      
+system.cpu0.kern.mode_good::user                 1342                      
 system.cpu0.kern.mode_good::idle                    0                      
-system.cpu0.kern.mode_switch_good::kernel     0.185552                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good::kernel     0.211815                       # fraction of useful protection mode switches
 system.cpu0.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
 system.cpu0.kern.mode_switch_good::idle           nan                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good::total     0.313100                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_ticks::kernel      1904135221500     99.89%     99.89% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks::user          2071163500      0.11%    100.00% # number of ticks spent at the given mode
+system.cpu0.kern.mode_switch_good::total     0.349668                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_ticks::kernel      1901148119000     99.90%     99.90% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks::user          1974809500      0.10%    100.00% # number of ticks spent at the given mode
 system.cpu0.kern.mode_ticks::idle                   0      0.00%    100.00% # number of ticks spent at the given mode
-system.cpu0.kern.swap_context                    3931                       # number of times the context was actually changed
+system.cpu0.kern.swap_context                    2906                       # number of times the context was actually changed
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                    2254                       # number of quiesce instructions executed
-system.cpu1.kern.inst.hwrei                     34590                       # number of hwrei instructions executed
-system.cpu1.kern.ipl_count::0                    8916     31.91%     31.91% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::22                   1925      6.89%     38.80% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::30                     95      0.34%     39.14% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::31                  17006     60.86%    100.00% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::total               27942                       # number of times we switched to this ipl
-system.cpu1.kern.ipl_good::0                     8908     45.12%     45.12% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::22                    1925      9.75%     54.88% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::30                      95      0.48%     55.36% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::31                    8813     44.64%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::total                19741                       # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_ticks::0            1876395415500     98.45%     98.45% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::22              531818000      0.03%     98.48% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::30               44293500      0.00%     98.48% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::31            28895956000      1.52%    100.00% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::total        1905867483000                       # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_used::0                 0.999103                       # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.inst.quiesce                    3853                       # number of quiesce instructions executed
+system.cpu1.kern.inst.hwrei                     75635                       # number of hwrei instructions executed
+system.cpu1.kern.ipl_count::0                   26441     39.26%     39.26% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::22                   1922      2.85%     42.12% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::30                    105      0.16%     42.27% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::31                  38878     57.73%    100.00% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::total               67346                       # number of times we switched to this ipl
+system.cpu1.kern.ipl_good::0                    25959     48.22%     48.22% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::22                    1922      3.57%     51.78% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::30                     105      0.20%     51.98% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::31                   25854     48.02%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::total                53840                       # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_ticks::0            1868834322000     98.22%     98.22% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::22              532397000      0.03%     98.24% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::30               48831000      0.00%     98.25% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::31            33374320500      1.75%    100.00% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::total        1902789870500                       # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_used::0                 0.981771                       # fraction of swpipl calls that actually changed the ipl
 system.cpu1.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu1.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::31                0.518229                       # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::total             0.706499                       # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.syscall::3                        10     10.87%     10.87% # number of syscalls executed
-system.cpu1.kern.syscall::6                         9      9.78%     20.65% # number of syscalls executed
-system.cpu1.kern.syscall::15                        1      1.09%     21.74% # number of syscalls executed
-system.cpu1.kern.syscall::17                        5      5.43%     27.17% # number of syscalls executed
-system.cpu1.kern.syscall::23                        3      3.26%     30.43% # number of syscalls executed
-system.cpu1.kern.syscall::24                        3      3.26%     33.70% # number of syscalls executed
-system.cpu1.kern.syscall::33                        3      3.26%     36.96% # number of syscalls executed
-system.cpu1.kern.syscall::45                       15     16.30%     53.26% # number of syscalls executed
-system.cpu1.kern.syscall::47                        3      3.26%     56.52% # number of syscalls executed
-system.cpu1.kern.syscall::59                        1      1.09%     57.61% # number of syscalls executed
-system.cpu1.kern.syscall::71                       27     29.35%     86.96% # number of syscalls executed
-system.cpu1.kern.syscall::74                        9      9.78%     96.74% # number of syscalls executed
-system.cpu1.kern.syscall::132                       3      3.26%    100.00% # number of syscalls executed
-system.cpu1.kern.syscall::total                    92                       # number of syscalls executed
+system.cpu1.kern.ipl_used::31                0.665003                       # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.ipl_used::total             0.799454                       # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.syscall::3                        11     10.89%     10.89% # number of syscalls executed
+system.cpu1.kern.syscall::6                         9      8.91%     19.80% # number of syscalls executed
+system.cpu1.kern.syscall::15                        1      0.99%     20.79% # number of syscalls executed
+system.cpu1.kern.syscall::17                        6      5.94%     26.73% # number of syscalls executed
+system.cpu1.kern.syscall::23                        3      2.97%     29.70% # number of syscalls executed
+system.cpu1.kern.syscall::24                        3      2.97%     32.67% # number of syscalls executed
+system.cpu1.kern.syscall::33                        4      3.96%     36.63% # number of syscalls executed
+system.cpu1.kern.syscall::45                       18     17.82%     54.46% # number of syscalls executed
+system.cpu1.kern.syscall::47                        3      2.97%     57.43% # number of syscalls executed
+system.cpu1.kern.syscall::59                        1      0.99%     58.42% # number of syscalls executed
+system.cpu1.kern.syscall::71                       29     28.71%     87.13% # number of syscalls executed
+system.cpu1.kern.syscall::74                       10      9.90%     97.03% # number of syscalls executed
+system.cpu1.kern.syscall::132                       3      2.97%    100.00% # number of syscalls executed
+system.cpu1.kern.syscall::total                   101                       # number of syscalls executed
 system.cpu1.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
-system.cpu1.kern.callpal::wripir                    6      0.02%      0.02% # number of callpals executed
+system.cpu1.kern.callpal::wripir                   16      0.02%      0.02% # number of callpals executed
 system.cpu1.kern.callpal::wrmces                    1      0.00%      0.03% # number of callpals executed
 system.cpu1.kern.callpal::wrfen                     1      0.00%      0.03% # number of callpals executed
-system.cpu1.kern.callpal::swpctx                  298      1.04%      1.07% # number of callpals executed
-system.cpu1.kern.callpal::tbi                       3      0.01%      1.08% # number of callpals executed
-system.cpu1.kern.callpal::wrent                     7      0.02%      1.11% # number of callpals executed
-system.cpu1.kern.callpal::swpipl                23527     82.20%     83.30% # number of callpals executed
-system.cpu1.kern.callpal::rdps                   2214      7.74%     91.04% # number of callpals executed
-system.cpu1.kern.callpal::wrkgp                     1      0.00%     91.04% # number of callpals executed
-system.cpu1.kern.callpal::wrusp                     3      0.01%     91.05% # number of callpals executed
-system.cpu1.kern.callpal::whami                     3      0.01%     91.06% # number of callpals executed
-system.cpu1.kern.callpal::rti                    2394      8.36%     99.43% # number of callpals executed
-system.cpu1.kern.callpal::callsys                 121      0.42%     99.85% # number of callpals executed
-system.cpu1.kern.callpal::imb                      42      0.15%    100.00% # number of callpals executed
+system.cpu1.kern.callpal::swpctx                 1334      1.92%      1.95% # number of callpals executed
+system.cpu1.kern.callpal::tbi                       3      0.00%      1.95% # number of callpals executed
+system.cpu1.kern.callpal::wrent                     7      0.01%      1.96% # number of callpals executed
+system.cpu1.kern.callpal::swpipl                62422     89.83%     91.80% # number of callpals executed
+system.cpu1.kern.callpal::rdps                   2621      3.77%     95.57% # number of callpals executed
+system.cpu1.kern.callpal::wrkgp                     1      0.00%     95.57% # number of callpals executed
+system.cpu1.kern.callpal::wrusp                     4      0.01%     95.57% # number of callpals executed
+system.cpu1.kern.callpal::whami                     3      0.00%     95.58% # number of callpals executed
+system.cpu1.kern.callpal::rti                    2896      4.17%     99.75% # number of callpals executed
+system.cpu1.kern.callpal::callsys                 133      0.19%     99.94% # number of callpals executed
+system.cpu1.kern.callpal::imb                      42      0.06%    100.00% # number of callpals executed
 system.cpu1.kern.callpal::rdunique                  1      0.00%    100.00% # number of callpals executed
-system.cpu1.kern.callpal::total                 28623                       # number of callpals executed
-system.cpu1.kern.mode_switch::kernel              659                       # number of protection mode switches
-system.cpu1.kern.mode_switch::user                367                       # number of protection mode switches
-system.cpu1.kern.mode_switch::idle               2036                       # number of protection mode switches
-system.cpu1.kern.mode_good::kernel                386                      
-system.cpu1.kern.mode_good::user                  367                      
-system.cpu1.kern.mode_good::idle                   19                      
-system.cpu1.kern.mode_switch_good::kernel     0.585736                       # fraction of useful protection mode switches
+system.cpu1.kern.callpal::total                 69486                       # number of callpals executed
+system.cpu1.kern.mode_switch::kernel             1712                       # number of protection mode switches
+system.cpu1.kern.mode_switch::user                395                       # number of protection mode switches
+system.cpu1.kern.mode_switch::idle               2056                       # number of protection mode switches
+system.cpu1.kern.mode_good::kernel                462                      
+system.cpu1.kern.mode_good::user                  395                      
+system.cpu1.kern.mode_good::idle                   67                      
+system.cpu1.kern.mode_switch_good::kernel     0.269860                       # fraction of useful protection mode switches
 system.cpu1.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::idle      0.009332                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::total     0.252123                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_ticks::kernel        1444110500      0.08%      0.08% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::user           692193000      0.04%      0.11% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::idle        1903401131500     99.89%    100.00% # number of ticks spent at the given mode
-system.cpu1.kern.swap_context                     299                       # number of times the context was actually changed
+system.cpu1.kern.mode_switch_good::idle      0.032588                       # fraction of useful protection mode switches
+system.cpu1.kern.mode_switch_good::total     0.221955                       # fraction of useful protection mode switches
+system.cpu1.kern.mode_ticks::kernel       38841912000      2.04%      2.04% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::user           712477500      0.04%      2.08% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::idle        1862932175500     97.92%    100.00% # number of ticks spent at the given mode
+system.cpu1.kern.swap_context                    1335                       # number of times the context was actually changed
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
index f07e7eac0..6fda1994e 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
@@ -1,128 +1,131 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  1.860172                       # Number of seconds simulated
-sim_ticks                                1860172195000                       # Number of ticks simulated
-final_tick                               1860172195000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  1.860009                       # Number of seconds simulated
+sim_ticks                                1860008936000                       # Number of ticks simulated
+final_tick                               1860008936000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 152063                       # Simulator instruction rate (inst/s)
-host_op_rate                                   152063                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             5340733222                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 304984                       # Number of bytes of host memory used
-host_seconds                                   348.30                       # Real time elapsed on the host
-sim_insts                                    52963419                       # Number of instructions simulated
-sim_ops                                      52963419                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 106543                       # Simulator instruction rate (inst/s)
+host_op_rate                                   106543                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             3740252336                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 320492                       # Number of bytes of host memory used
+host_seconds                                   497.30                       # Real time elapsed on the host
+sim_insts                                    52983264                       # Number of instructions simulated
+sim_ops                                      52983264                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            965120                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          24879104                       # Number of bytes read from this memory
-system.physmem.bytes_read::tsunami.ide        2652288                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             28496512                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       965120                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          965120                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7515712                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7515712                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst              15080                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             388736                       # Number of read requests responded to by this memory
-system.physmem.num_reads::tsunami.ide           41442                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                445258                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          117433                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               117433                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               518834                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             13374624                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::tsunami.ide           1425829                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                15319287                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          518834                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             518834                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           4040331                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                4040331                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           4040331                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              518834                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            13374624                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::tsunami.ide          1425829                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               19359618                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        445258                       # Number of read requests accepted
-system.physmem.writeReqs                       117433                       # Number of write requests accepted
-system.physmem.readBursts                      445258                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     117433                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 28490432                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      6080                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   7513664                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  28496512                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                7515712                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                       95                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytes_read::cpu.inst            968512                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          24900352                       # Number of bytes read from this memory
+system.physmem.bytes_read::tsunami.ide            960                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             25869824                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       968512                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          968512                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      4866048                       # Number of bytes written to this memory
+system.physmem.bytes_written::tsunami.ide      2659328                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7525376                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst              15133                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             389068                       # Number of read requests responded to by this memory
+system.physmem.num_reads::tsunami.ide              15                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                404216                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           76032                       # Number of write requests responded to by this memory
+system.physmem.num_writes::tsunami.ide          41552                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               117584                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst               520703                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             13387222                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::tsunami.ide               516                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                13908441                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          520703                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             520703                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           2616142                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::tsunami.ide          1429739                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                4045882                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           2616142                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              520703                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            13387222                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::tsunami.ide          1430255                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               17954322                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        404216                       # Number of read requests accepted
+system.physmem.writeReqs                       117584                       # Number of write requests accepted
+system.physmem.readBursts                      404216                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     117584                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 25858752                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     11072                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   7523328                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  25869824                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                7525376                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      173                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs            176                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               28223                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               27968                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               28292                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               27927                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               27805                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               27242                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               27352                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               27274                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               27691                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               27508                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              27933                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              27527                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              27552                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              28225                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              28330                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              28314                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                7932                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                7496                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                7821                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                7427                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                7353                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                6703                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                6854                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                6665                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                7118                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                6889                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               7323                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               6981                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               7116                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               7874                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               8055                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               7794                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs            213                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               25622                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               25451                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               25608                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               25528                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               25399                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               24757                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               24940                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               25074                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               24966                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               25053                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              25586                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              24884                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              24485                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              25285                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              25789                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              25616                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                7925                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                7509                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                7974                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                7525                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                7335                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                6682                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                6769                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                6701                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                7135                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                6719                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               7431                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               6970                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               7113                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               7882                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               8065                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               7817                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          10                       # Number of times write queue was full causing retry
-system.physmem.totGap                    1860166839000                       # Total gap between requests
+system.physmem.numWrRetry                           9                       # Number of times write queue was full causing retry
+system.physmem.totGap                    1860003602000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  445258                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  404216                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 117433                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    317162                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     38754                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     44609                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                      9021                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                      2051                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                      4407                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                      3954                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                      3974                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                      2513                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                      2195                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                     2171                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                     2106                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                     1630                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                     1618                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                     1898                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                     1857                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                     2113                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                     1232                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                      984                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                      899                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                        9                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21                        6                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 117584                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    315071                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     37801                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     42911                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                      8183                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                        61                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                         7                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                         1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                         1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                         1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
@@ -148,282 +151,273 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     1086                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     1114                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     2248                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     3162                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     4215                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     4772                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     4799                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     4937                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     5105                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     5276                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     5563                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     5819                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     6253                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     6876                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     6083                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     6291                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     6234                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     6019                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      966                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      924                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      969                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      901                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      939                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      988                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                     1058                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      973                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                     1128                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                     1179                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                     1174                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                     1276                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                     1414                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                     1656                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                     1874                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                     1977                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                     1860                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                     1800                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                     1689                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                     1697                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                     1803                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                     1633                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                      837                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                      395                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                      207                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                      131                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       36                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       26                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       25                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       15                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     1589                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     2253                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     3103                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::22                     8550                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::50                       93                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::52                       71                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                       66                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                       71                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                       71                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                       64                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                       71                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::61                       28                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       14                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                       16                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        63680                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      565.384925                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     351.672479                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     419.574374                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          13299     20.88%     20.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        10397     16.33%     37.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         4628      7.27%     44.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         2746      4.31%     48.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2553      4.01%     52.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1655      2.60%     55.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1376      2.16%     57.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1696      2.66%     60.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        25330     39.78%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          63680                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          6888                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        64.625581                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::gmean       16.554610                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev     2544.325145                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-8191           6885     99.96%     99.96% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::40960-49151            1      0.01%     99.97% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::57344-65535            1      0.01%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::196608-204799            1      0.01%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            6888                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          6888                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        17.044280                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.812634                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        3.762583                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16               5511     80.01%     80.01% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17                 31      0.45%     80.46% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18                662      9.61%     90.07% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19                220      3.19%     93.26% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                110      1.60%     94.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21                 25      0.36%     95.22% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22                 25      0.36%     95.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23                 91      1.32%     96.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24                 22      0.32%     97.23% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::25                 31      0.45%     97.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26                 12      0.17%     97.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::27                 22      0.32%     98.17% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28                  6      0.09%     98.26% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::29                 14      0.20%     98.46% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::30                  3      0.04%     98.50% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::31                 16      0.23%     98.74% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32                 12      0.17%     98.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::34                  7      0.10%     99.01% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::35                  1      0.01%     99.03% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36                  1      0.01%     99.04% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::37                  3      0.04%     99.09% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::38                  4      0.06%     99.14% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::39                  4      0.06%     99.20% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40                  4      0.06%     99.26% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::41                  6      0.09%     99.35% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::43                  3      0.04%     99.39% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::46                  3      0.04%     99.43% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::47                  7      0.10%     99.54% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48                  2      0.03%     99.56% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::49                  1      0.01%     99.58% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::50                  2      0.03%     99.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::51                  2      0.03%     99.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52                  1      0.01%     99.65% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::53                  1      0.01%     99.67% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::54                  1      0.01%     99.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::55                  1      0.01%     99.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56                  8      0.12%     99.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::57                 12      0.17%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::58                  1      0.01%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            6888                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     8740437500                       # Total ticks spent queuing
-system.physmem.totMemAccLat               17087243750                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   2225815000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       19634.24                       # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples        61090                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      546.434703                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     336.353089                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     417.871718                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          13232     21.66%     21.66% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        10443     17.09%     38.75% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         4742      7.76%     46.52% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         2710      4.44%     50.95% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2446      4.00%     54.96% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1597      2.61%     57.57% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1401      2.29%     59.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1610      2.64%     62.50% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        22909     37.50%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          61090                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          5256                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        76.868151                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev     2912.510758                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-8191           5253     99.94%     99.94% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::40960-49151            1      0.02%     99.96% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::57344-65535            1      0.02%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::196608-204799            1      0.02%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total            5256                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          5256                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        22.365297                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       19.103318                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       20.103778                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            4494     85.50%     85.50% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23             124      2.36%     87.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27               9      0.17%     88.03% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31             232      4.41%     92.45% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35              40      0.76%     93.21% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39               6      0.11%     93.32% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43              12      0.23%     93.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47               3      0.06%     93.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51              27      0.51%     94.12% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55               3      0.06%     94.18% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59               1      0.02%     94.20% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63               1      0.02%     94.22% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67              15      0.29%     94.50% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71               5      0.10%     94.60% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75               3      0.06%     94.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83              31      0.59%     95.24% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87               8      0.15%     95.40% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91               4      0.08%     95.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95               5      0.10%     95.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99             188      3.58%     99.14% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111             2      0.04%     99.18% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115             5      0.10%     99.28% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127             3      0.06%     99.33% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131            11      0.21%     99.54% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135             3      0.06%     99.60% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-139             1      0.02%     99.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143             7      0.13%     99.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147             5      0.10%     99.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::148-151             1      0.02%     99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-155             1      0.02%     99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-163             2      0.04%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::164-167             2      0.04%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::224-227             2      0.04%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            5256                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     3626109250                       # Total ticks spent queuing
+system.physmem.totMemAccLat               11201915500                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   2020215000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        8974.56                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  38384.24                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          15.32                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  27724.56                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          13.90                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           4.04                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       15.32                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        4.04                       # Average system write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       13.91                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        4.05                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           0.15                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       0.12                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                           0.14                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       0.11                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.65                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        24.75                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     403028                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     95855                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   90.53                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  81.63                       # Row buffer hit rate for writes
-system.physmem.avgGap                      3305840.75                       # Average gap between requests
-system.physmem.pageHitRate                      88.68                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE     1761575145500                       # Time in different power states
-system.physmem.memoryStateTime::REF       62115040000                       # Time in different power states
+system.physmem.avgRdQLen                         1.48                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        24.10                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     364992                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     95512                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   90.33                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  81.23                       # Row buffer hit rate for writes
+system.physmem.avgGap                      3564591.03                       # Average gap between requests
+system.physmem.pageHitRate                      88.28                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE     1761923491250                       # Time in different power states
+system.physmem.memoryStateTime::REF       62109580000                       # Time in different power states
 system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT       36476358250                       # Time in different power states
+system.physmem.memoryStateTime::ACT       35970256750                       # Time in different power states
 system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.membus.throughput                     19402477                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq              295985                       # Transaction distribution
-system.membus.trans_dist::ReadResp             295900                       # Transaction distribution
-system.membus.trans_dist::WriteReq               9597                       # Transaction distribution
-system.membus.trans_dist::WriteResp              9597                       # Transaction distribution
-system.membus.trans_dist::Writeback            117433                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq              178                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq              1                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp             179                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            156844                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           156844                       # Transaction distribution
-system.membus.trans_dist::BadAddressError           85                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave        33054                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       884181                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio          170                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total       917405                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       124679                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       124679                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1042084                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave        44140                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     30703168                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total     30747308                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port      5309056                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::total      5309056                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total            36056364                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus               36056364                       # Total data (bytes)
-system.membus.snoop_data_through_bus            35584                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy            29838500                       # Layer occupancy (ticks)
+system.membus.throughput                     17983494                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq              296097                       # Transaction distribution
+system.membus.trans_dist::ReadResp             296008                       # Transaction distribution
+system.membus.trans_dist::WriteReq               9598                       # Transaction distribution
+system.membus.trans_dist::WriteResp              9598                       # Transaction distribution
+system.membus.trans_dist::Writeback             76032                       # Transaction distribution
+system.membus.trans_dist::WriteInvalidateReq        41552                       # Transaction distribution
+system.membus.trans_dist::WriteInvalidateResp        41552                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq              207                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq              6                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp             213                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            115296                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           115296                       # Transaction distribution
+system.membus.trans_dist::BadAddressError           89                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave        33056                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       884860                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio          178                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total       918094                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        83292                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total        83292                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                1001386                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave        44148                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     30734912                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total     30779060                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port      2660288                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.iocache.mem_side::total      2660288                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total            33439348                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus               33439348                       # Total data (bytes)
+system.membus.snoop_data_through_bus            10112                       # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy            29284000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy          1526200750                       # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy          1484965250                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.1                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy              104500                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy              112000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         3755175800                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         3755505039                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
-system.membus.respLayer2.occupancy          376659242                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy           43151211                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
 system.iocache.tags.replacements                41685                       # number of replacements
-system.iocache.tags.tagsinuse                1.260971                       # Cycle average of tags in use
+system.iocache.tags.tagsinuse                1.268186                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs                41701                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         1710335831000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::tsunami.ide     1.260971                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::tsunami.ide     0.078811                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.078811                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         1709354954000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::tsunami.ide     1.268186                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::tsunami.ide     0.079262                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.079262                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses               375525                       # Number of tag accesses
-system.iocache.tags.data_accesses              375525                       # Number of data accesses
+system.iocache.tags.tag_accesses               376037                       # Number of tag accesses
+system.iocache.tags.data_accesses              376037                       # Number of data accesses
+system.iocache.WriteInvalidateReq_hits::tsunami.ide        41552                       # number of WriteInvalidateReq hits
+system.iocache.WriteInvalidateReq_hits::total        41552                       # number of WriteInvalidateReq hits
 system.iocache.ReadReq_misses::tsunami.ide          173                       # number of ReadReq misses
 system.iocache.ReadReq_misses::total              173                       # number of ReadReq misses
-system.iocache.WriteReq_misses::tsunami.ide        41552                       # number of WriteReq misses
-system.iocache.WriteReq_misses::total           41552                       # number of WriteReq misses
-system.iocache.demand_misses::tsunami.ide        41725                       # number of demand (read+write) misses
-system.iocache.demand_misses::total             41725                       # number of demand (read+write) misses
-system.iocache.overall_misses::tsunami.ide        41725                       # number of overall misses
-system.iocache.overall_misses::total            41725                       # number of overall misses
-system.iocache.ReadReq_miss_latency::tsunami.ide     21134383                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     21134383                       # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency::tsunami.ide  12441682213                       # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_latency::total  12441682213                       # number of WriteReq miss cycles
-system.iocache.demand_miss_latency::tsunami.ide  12462816596                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total  12462816596                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::tsunami.ide  12462816596                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total  12462816596                       # number of overall miss cycles
+system.iocache.WriteInvalidateReq_misses::tsunami.ide           64                       # number of WriteInvalidateReq misses
+system.iocache.WriteInvalidateReq_misses::total           64                       # number of WriteInvalidateReq misses
+system.iocache.demand_misses::tsunami.ide          173                       # number of demand (read+write) misses
+system.iocache.demand_misses::total               173                       # number of demand (read+write) misses
+system.iocache.overall_misses::tsunami.ide          173                       # number of overall misses
+system.iocache.overall_misses::total              173                       # number of overall misses
+system.iocache.ReadReq_miss_latency::tsunami.ide     21133383                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     21133383                       # number of ReadReq miss cycles
+system.iocache.demand_miss_latency::tsunami.ide     21133383                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total     21133383                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::tsunami.ide     21133383                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total     21133383                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::tsunami.ide          173                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            173                       # number of ReadReq accesses(hits+misses)
-system.iocache.WriteReq_accesses::tsunami.ide        41552                       # number of WriteReq accesses(hits+misses)
-system.iocache.WriteReq_accesses::total         41552                       # number of WriteReq accesses(hits+misses)
-system.iocache.demand_accesses::tsunami.ide        41725                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total           41725                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::tsunami.ide        41725                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total          41725                       # number of overall (read+write) accesses
+system.iocache.WriteInvalidateReq_accesses::tsunami.ide        41616                       # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::total        41616                       # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.demand_accesses::tsunami.ide          173                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total             173                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::tsunami.ide          173                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total            173                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
-system.iocache.WriteReq_miss_rate::tsunami.ide            1                       # miss rate for WriteReq accesses
-system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide     0.001538                       # miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::total     0.001538                       # miss rate for WriteInvalidateReq accesses
 system.iocache.demand_miss_rate::tsunami.ide            1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122164.063584                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 122164.063584                       # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::tsunami.ide 299424.389031                       # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total 299424.389031                       # average WriteReq miss latency
-system.iocache.demand_avg_miss_latency::tsunami.ide 298689.433098                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 298689.433098                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::tsunami.ide 298689.433098                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 298689.433098                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs        366119                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122158.283237                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 122158.283237                       # average ReadReq miss latency
+system.iocache.demand_avg_miss_latency::tsunami.ide 122158.283237                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 122158.283237                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::tsunami.ide 122158.283237                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 122158.283237                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                28395                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs    12.893784                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.fast_writes                          0                       # number of fast writes performed
+system.iocache.fast_writes                      41552                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.writebacks::writebacks           41512                       # number of writebacks
-system.iocache.writebacks::total                41512                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::tsunami.ide          173                       # number of ReadReq MSHR misses
 system.iocache.ReadReq_mshr_misses::total          173                       # number of ReadReq MSHR misses
-system.iocache.WriteReq_mshr_misses::tsunami.ide        41552                       # number of WriteReq MSHR misses
-system.iocache.WriteReq_mshr_misses::total        41552                       # number of WriteReq MSHR misses
-system.iocache.demand_mshr_misses::tsunami.ide        41725                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total        41725                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::tsunami.ide        41725                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total        41725                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     12137383                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     12137383                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::tsunami.ide  10278710729                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::total  10278710729                       # number of WriteReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::tsunami.ide  10290848112                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total  10290848112                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::tsunami.ide  10290848112                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total  10290848112                       # number of overall MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide        41552                       # number of WriteInvalidateReq MSHR misses
+system.iocache.WriteInvalidateReq_mshr_misses::total        41552                       # number of WriteInvalidateReq MSHR misses
+system.iocache.demand_mshr_misses::tsunami.ide          173                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total          173                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::tsunami.ide          173                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total          173                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     12136383                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     12136383                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide   2528134047                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::total   2528134047                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::tsunami.ide     12136383                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total     12136383                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::tsunami.ide     12136383                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total     12136383                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
-system.iocache.WriteReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteReq accesses
-system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
+system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide     0.998462                       # mshr miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_mshr_miss_rate::total     0.998462                       # mshr miss rate for WriteInvalidateReq accesses
 system.iocache.demand_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for demand accesses
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70158.283237                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 70158.283237                       # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 247369.819239                       # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total 247369.819239                       # average WriteReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 246635.065596                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 246635.065596                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 246635.065596                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 246635.065596                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70152.502890                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 70152.502890                       # average ReadReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 60842.656118                       # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60842.656118                       # average WriteInvalidateReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70152.502890                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 70152.502890                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70152.502890                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 70152.502890                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
@@ -437,36 +431,36 @@ system.disk2.dma_read_txs                           0                       # Nu
 system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
 system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
 system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
-system.cpu.branchPred.lookups                13973676                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          11739131                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            397652                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups              9590938                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                 5932533                       # Number of BTB hits
+system.cpu.branchPred.lookups                17833670                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          15506350                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            381114                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             12104225                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                 5926115                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             61.855608                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                  905503                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect              38808                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             48.959062                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                  921355                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect              21398                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                     10112222                       # DTB read hits
-system.cpu.dtb.read_misses                      41745                       # DTB read misses
-system.cpu.dtb.read_acv                           542                       # DTB read access violations
-system.cpu.dtb.read_accesses                   945441                       # DTB read accesses
-system.cpu.dtb.write_hits                     6611008                       # DTB write hits
-system.cpu.dtb.write_misses                     10791                       # DTB write misses
-system.cpu.dtb.write_acv                          413                       # DTB write access violations
-system.cpu.dtb.write_accesses                  339727                       # DTB write accesses
-system.cpu.dtb.data_hits                     16723230                       # DTB hits
-system.cpu.dtb.data_misses                      52536                       # DTB misses
-system.cpu.dtb.data_acv                           955                       # DTB access violations
-system.cpu.dtb.data_accesses                  1285168                       # DTB accesses
-system.cpu.itb.fetch_hits                     1309723                       # ITB hits
-system.cpu.itb.fetch_misses                     39683                       # ITB misses
-system.cpu.itb.fetch_acv                         1073                       # ITB acv
-system.cpu.itb.fetch_accesses                 1349406                       # ITB accesses
+system.cpu.dtb.read_hits                     10317598                       # DTB read hits
+system.cpu.dtb.read_misses                      42841                       # DTB read misses
+system.cpu.dtb.read_acv                           498                       # DTB read access violations
+system.cpu.dtb.read_accesses                   968680                       # DTB read accesses
+system.cpu.dtb.write_hits                     6661505                       # DTB write hits
+system.cpu.dtb.write_misses                      9470                       # DTB write misses
+system.cpu.dtb.write_acv                          409                       # DTB write access violations
+system.cpu.dtb.write_accesses                  342844                       # DTB write accesses
+system.cpu.dtb.data_hits                     16979103                       # DTB hits
+system.cpu.dtb.data_misses                      52311                       # DTB misses
+system.cpu.dtb.data_acv                           907                       # DTB access violations
+system.cpu.dtb.data_accesses                  1311524                       # DTB accesses
+system.cpu.itb.fetch_hits                     1772041                       # ITB hits
+system.cpu.itb.fetch_misses                     34420                       # ITB misses
+system.cpu.itb.fetch_acv                          658                       # ITB acv
+system.cpu.itb.fetch_accesses                 1806461                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -479,255 +473,256 @@ system.cpu.itb.data_hits                            0                       # DT
 system.cpu.itb.data_misses                          0                       # DTB misses
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
-system.cpu.numCycles                        121578156                       # number of cpu cycles simulated
+system.cpu.numCycles                        118354133                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           28154197                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                       72069959                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    13973676                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches            6838036                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      13462286                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 2111809                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles               36504135                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                32813                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles        258219                       # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles       367287                       # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles          202                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                   8654218                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                283642                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples           80169891                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              0.898965                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.245398                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles           29610053                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                       78304025                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    17833670                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches            6847470                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      80574615                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 1256858                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles                       1099                       # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles                26263                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles       1650622                       # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles       440507                       # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles          235                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                   9057340                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                272482                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes                       1                       # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples          112931823                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              0.693374                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.013486                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 66707605     83.21%     83.21% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                   850391      1.06%     84.27% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  1701562      2.12%     86.39% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                   829510      1.03%     87.43% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  2814732      3.51%     90.94% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                   566680      0.71%     91.64% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                   649069      0.81%     92.45% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  1061564      1.32%     93.78% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                  4988778      6.22%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 98319716     87.06%     87.06% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                   938849      0.83%     87.89% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  1975725      1.75%     89.64% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                   910849      0.81%     90.45% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  2798510      2.48%     92.93% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                   647409      0.57%     93.50% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                   732146      0.65%     94.15% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  1011734      0.90%     95.04% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                  5596885      4.96%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total             80169891                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.114936                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.592787                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 28969141                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              36597720                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  12749238                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles                505228                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                1348563                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved               587502                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                 42619                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts               70583559                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                129875                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                1348563                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 29902418                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                12633582                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles       20046715                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  11807818                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles               4430793                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts               66640171                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                  8986                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                 787429                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                  47943                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                1601274                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands            44565634                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups              80920867                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups         80741427                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups            166989                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps              38166970                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                  6398656                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts            1681821                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts         238696                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                   9832739                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             10696003                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores             7004082                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           1336985                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores           877203                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                   58981840                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded             2047452                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                  57223975                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            117650                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined         7712570                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined      4365148                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved        1386476                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples      80169891                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.713784                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.404933                       # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total            112931823                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.150681                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.661608                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 24101711                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              76820135                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                   9519710                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               1904377                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                 585889                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved               591731                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                 42945                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts               68430953                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                130896                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                 585889                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 25024532                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                47243324                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles       20763433                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  10413926                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles               8900717                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts               65988448                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                204336                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                2037147                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                 141186                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents                4759131                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands            44017538                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups              79991288                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups         79809724                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups            169111                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps              38182266                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                  5835264                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts            1692739                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts         242112                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  13540611                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             10451547                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores             6960595                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           1482211                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          1061862                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                   58727790                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded             2141622                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                  57666213                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued             56106                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined         7541795                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined      3548748                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved        1480432                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     112931823                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.510629                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.253101                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            56166624     70.06%     70.06% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            10391261     12.96%     83.02% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2             4679899      5.84%     88.86% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3             3142763      3.92%     92.78% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4             2796032      3.49%     96.27% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             1647190      2.05%     98.32% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6              895238      1.12%     99.44% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7              353951      0.44%     99.88% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8               96933      0.12%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            89418441     79.18%     79.18% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            10028401      8.88%     88.06% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2             4312192      3.82%     91.88% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3             2973812      2.63%     94.51% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             3078524      2.73%     97.24% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             1589541      1.41%     98.64% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             1010242      0.89%     99.54% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7              396621      0.35%     99.89% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              124049      0.11%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total        80169891                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       112931823                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                   98738     11.92%     11.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%     11.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     11.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     11.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     11.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     11.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     11.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     11.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     11.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     11.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     11.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     11.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     11.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     11.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     11.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     11.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     11.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     11.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     11.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     11.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     11.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     11.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     11.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     11.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     11.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     11.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     11.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     11.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     11.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                 400158     48.30%     60.22% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                329520     39.78%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  207021     18.24%     18.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%     18.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     18.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     18.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     18.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     18.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     18.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     18.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     18.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     18.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     18.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     18.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     18.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     18.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     18.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     18.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     18.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     18.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     18.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     18.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     18.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     18.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     18.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     18.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     18.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     18.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     18.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     18.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     18.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                 552834     48.70%     66.94% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                375297     33.06%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass              7286      0.01%      0.01% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu              38901419     67.98%     67.99% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                61759      0.11%     68.10% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     68.10% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd               25607      0.04%     68.15% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     68.15% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     68.15% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     68.15% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                3636      0.01%     68.15% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     68.15% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     68.15% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     68.15% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     68.15% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     68.15% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     68.15% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     68.15% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     68.15% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     68.15% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     68.15% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     68.15% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     68.15% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     68.15% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     68.15% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     68.15% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     68.15% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     68.15% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     68.15% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     68.15% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.15% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     68.15% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             10584317     18.50%     86.65% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite             6690891     11.69%     98.34% # Type of FU issued
-system.cpu.iq.FU_type_0::IprAccess             949060      1.66%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu              39135351     67.87%     67.88% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                61883      0.11%     67.99% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     67.99% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd               38374      0.07%     68.05% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     68.05% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     68.05% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     68.05% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                3636      0.01%     68.06% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     68.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     68.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     68.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     68.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     68.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     68.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     68.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     68.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     68.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     68.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     68.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     68.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     68.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     68.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     68.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     68.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     68.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     68.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     68.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     68.06% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             10730394     18.61%     86.67% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite             6740242     11.69%     98.35% # Type of FU issued
+system.cpu.iq.FU_type_0::IprAccess             949047      1.65%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total               57223975                       # Type of FU issued
-system.cpu.iq.rate                           0.470676                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                      828416                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.014477                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          194870458                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes          68419457                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses     55733530                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads              693448                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes             335810                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses       328249                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses               57682446                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                  362659                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads           614531                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total               57666213                       # Type of FU issued
+system.cpu.iq.rate                           0.487234                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     1135152                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.019685                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          228740415                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes          68094123                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses     55977641                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads              715091                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes             336647                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses       329707                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses               58410087                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                  383992                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads           639401                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      1606237                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses         3745                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        13777                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores       627539                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      1358213                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses         3975                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        20004                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores       581979                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads        18239                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked        375591                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads        18257                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked        542602                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                1348563                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                 9312966                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                978337                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts            64604997                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            590069                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              10696003                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts              7004082                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts            1802911                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                 468863                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                377382                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          13777                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         204854                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       411482                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts               616336                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts              56685901                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              10182131                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts            538073                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                 585889                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                44309531                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                608680                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts            64580146                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            145680                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts              10451547                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts              6960595                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts            1891521                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                  42330                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                362520                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          20004                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         191994                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       411566                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts               603560                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts              57078103                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              10388088                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts            588109                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                       3575705                       # number of nop insts executed
-system.cpu.iew.exec_refs                     16819167                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                  8947461                       # Number of branches executed
-system.cpu.iew.exec_stores                    6637036                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.466251                       # Inst execution rate
-system.cpu.iew.wb_sent                       56177988                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                      56061779                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                  28606216                       # num instructions producing a value
-system.cpu.iew.wb_consumers                  39617780                       # num instructions consuming a value
+system.cpu.iew.exec_nop                       3710734                       # number of nop insts executed
+system.cpu.iew.exec_refs                     17074164                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                  8987700                       # Number of branches executed
+system.cpu.iew.exec_stores                    6686076                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.482265                       # Inst execution rate
+system.cpu.iew.wb_sent                       56446206                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                      56307348                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                  28961590                       # num instructions producing a value
+system.cpu.iew.wb_consumers                  40346871                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.461117                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.722055                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       0.475753                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.717815                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts         8325898                       # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls          660976                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            566478                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples     78821328                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.712415                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.665597                       # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts         8290413                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls          661190                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts            549582                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    111493844                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.503831                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.456125                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     58682621     74.45%     74.45% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1      8193641     10.40%     84.85% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2      4257107      5.40%     90.25% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      2319840      2.94%     93.19% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      1767395      2.24%     95.43% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5       615421      0.78%     96.21% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6       496583      0.63%     96.84% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7       549859      0.70%     97.54% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      1938861      2.46%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     91848046     82.38%     82.38% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1      7822356      7.02%     89.40% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      4123652      3.70%     93.09% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      2157766      1.94%     95.03% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      1851713      1.66%     96.69% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5       614180      0.55%     97.24% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6       473259      0.42%     97.67% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       509141      0.46%     98.12% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      2093731      1.88%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total     78821328                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts             56153459                       # Number of instructions committed
-system.cpu.commit.committedOps               56153459                       # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total    111493844                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts             56174099                       # Number of instructions committed
+system.cpu.commit.committedOps               56174099                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                       15466309                       # Number of memory references committed
-system.cpu.commit.loads                       9089766                       # Number of loads committed
-system.cpu.commit.membars                      226357                       # Number of memory barriers committed
-system.cpu.commit.branches                    8438044                       # Number of branches committed
-system.cpu.commit.fp_insts                     324384                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                  52003822                       # Number of committed integer instructions.
-system.cpu.commit.function_calls               740374                       # Number of function calls committed.
-system.cpu.commit.op_class_0::No_OpClass      3197313      5.69%      5.69% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu         36218566     64.50%     70.19% # Class of committed instruction
-system.cpu.commit.op_class_0::IntMult           60658      0.11%     70.30% # Class of committed instruction
-system.cpu.commit.op_class_0::IntDiv                0      0.00%     70.30% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatAdd          25607      0.05%     70.35% # Class of committed instruction
+system.cpu.commit.refs                       15471950                       # Number of memory references committed
+system.cpu.commit.loads                       9093334                       # Number of loads committed
+system.cpu.commit.membars                      226345                       # Number of memory barriers committed
+system.cpu.commit.branches                    8441019                       # Number of branches committed
+system.cpu.commit.fp_insts                     324451                       # Number of committed floating point instructions.
+system.cpu.commit.int_insts                  52023449                       # Number of committed integer instructions.
+system.cpu.commit.function_calls               740634                       # Number of function calls committed.
+system.cpu.commit.op_class_0::No_OpClass      3198108      5.69%      5.69% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu         36220301     64.48%     70.17% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult           60671      0.11%     70.28% # Class of committed instruction
+system.cpu.commit.op_class_0::IntDiv                0      0.00%     70.28% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatAdd          38087      0.07%     70.35% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatCmp              0      0.00%     70.35% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatCvt              0      0.00%     70.35% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatMult             0      0.00%     70.35% # Class of committed instruction
@@ -753,30 +748,30 @@ system.cpu.commit.op_class_0::SimdFloatMisc            0      0.00%     70.35% #
 system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     70.35% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     70.35% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     70.35% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead         9316123     16.59%     86.94% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite        6382496     11.37%     98.31% # Class of committed instruction
-system.cpu.commit.op_class_0::IprAccess        949060      1.69%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead         9319679     16.59%     86.94% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite        6384570     11.37%     98.31% # Class of committed instruction
+system.cpu.commit.op_class_0::IprAccess        949047      1.69%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total          56153459                       # Class of committed instruction
-system.cpu.commit.bw_lim_events               1938861                       # number cycles where commit BW limit reached
+system.cpu.commit.op_class_0::total          56174099                       # Class of committed instruction
+system.cpu.commit.bw_lim_events               2093731                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                    141112277                       # The number of ROB reads
-system.cpu.rob.rob_writes                   130308588                       # The number of ROB writes
-system.cpu.timesIdled                         1194216                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                        41408265                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles                   3598759795                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts                    52963419                       # Number of Instructions Simulated
-system.cpu.committedOps                      52963419                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               2.295512                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         2.295512                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.435633                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.435633                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                 74250743                       # number of integer regfile reads
-system.cpu.int_regfile_writes                40442410                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                    166399                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                   167429                       # number of floating regfile writes
-system.cpu.misc_regfile_reads                 2028427                       # number of misc regfile reads
-system.cpu.misc_regfile_writes                 938976                       # number of misc regfile writes
+system.cpu.rob.rob_reads                    173614429                       # The number of ROB reads
+system.cpu.rob.rob_writes                   130369620                       # The number of ROB writes
+system.cpu.timesIdled                          576556                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                         5422310                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles                   3601657297                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts                    52983264                       # Number of Instructions Simulated
+system.cpu.committedOps                      52983264                       # Number of Ops (including micro ops) Simulated
+system.cpu.cpi                               2.233802                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         2.233802                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.447667                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.447667                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                 74755796                       # number of integer regfile reads
+system.cpu.int_regfile_writes                40630218                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                    167440                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                   167913                       # number of floating regfile writes
+system.cpu.misc_regfile_reads                 2030226                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                 939431                       # number of misc regfile writes
 system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
 system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
 system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
@@ -808,12 +803,13 @@ system.tsunami.ethernet.totalRxOrn                  0                       # to
 system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
 system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
 system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
-system.iobus.throughput                       1454569                       # Throughput (bytes/s)
+system.iobus.throughput                       1454701                       # Throughput (bytes/s)
 system.iobus.trans_dist::ReadReq                 7103                       # Transaction distribution
 system.iobus.trans_dist::ReadResp                7103                       # Transaction distribution
-system.iobus.trans_dist::WriteReq               51149                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              51149                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio         5050                       # Packet count per connected master and slave (bytes)
+system.iobus.trans_dist::WriteReq               51086                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              51150                       # Transaction distribution
+system.iobus.trans_dist::WriteInvalidateReq           64                       # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio         5052                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio          472                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio           10                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio           10                       # Packet count per connected master and slave (bytes)
@@ -825,11 +821,11 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf
 system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio          102                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf          180                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total        33054                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total        33056                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side        83450                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.tsunami.ide.dma::total        83450                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  116504                       # Packet count per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio        20200                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count::total                  116506                       # Packet count per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio        20208                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio         1888                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio            5                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio            5                       # Cumulative packet size per connected master and slave (bytes)
@@ -841,12 +837,12 @@ system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf
 system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio          204                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf          299                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::total        44140                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::total        44148                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      2661608                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.tsunami.ide.dma::total      2661608                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::total              2705748                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.data_through_bus                 2705748                       # Total data (bytes)
-system.iobus.reqLayer0.occupancy              4661000                       # Layer occupancy (ticks)
+system.iobus.tot_pkt_size::total              2705756                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.data_through_bus                 2705756                       # Total data (bytes)
+system.iobus.reqLayer0.occupancy              4663000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy               353000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
@@ -868,245 +864,250 @@ system.iobus.reqLayer27.occupancy               76000                       # La
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer28.occupancy              110000                       # Layer occupancy (ticks)
 system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer29.occupancy           380163354                       # Layer occupancy (ticks)
+system.iobus.reqLayer29.occupancy           374510641                       # Layer occupancy (ticks)
 system.iobus.reqLayer29.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer30.occupancy               30000                       # Layer occupancy (ticks)
 system.iobus.reqLayer30.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy            23457000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy            23458000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer1.occupancy            43205758                       # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy            42014789                       # Layer occupancy (ticks)
 system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.throughput               111909594                       # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq        2117185                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       2117083                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteReq          9597                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteResp         9597                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback       840753                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq           64                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::SCUpgradeReq            2                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp           66                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       342629                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       301078                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::BadAddressError           85                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2018148                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      3678150                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           5696298                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     64577024                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    143586668                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total      208163692                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus         208153644                       # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus        17472                       # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy     2479804999                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.throughput               114654995                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq        2149538                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       2149432                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteReq          9598                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteResp         9598                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback       845214                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteInvalidateReq        41561                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq           94                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::SCUpgradeReq           28                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp          122                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       302210                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       302210                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::BadAddressError           89                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2074480                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      3693292                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           5767772                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     66377344                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    144210036                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total      210587380                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus         210577396                       # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus      2681920                       # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy     2503268997                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy       235500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.occupancy       234000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy    1516964420                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy    1560084006                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    2185370157                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    2193039668                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
-system.cpu.icache.tags.replacements           1008400                       # number of replacements
-system.cpu.icache.tags.tagsinuse           509.648597                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs             7589401                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs           1008908                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs              7.522392                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle       26586363250                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   509.648597                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.995407                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.995407                       # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements           1036559                       # number of replacements
+system.cpu.icache.tags.tagsinuse           509.401978                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs             7968978                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs           1037067                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs              7.684150                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle       26427286250                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   509.401978                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.994926                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.994926                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          508                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           71                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          123                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          314                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          136                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          301                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.992188                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses           9663349                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses          9663349                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst      7589402                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total         7589402                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst       7589402                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total          7589402                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst      7589402                       # number of overall hits
-system.cpu.icache.overall_hits::total         7589402                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst      1064815                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total       1064815                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst      1064815                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total        1064815                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst      1064815                       # number of overall misses
-system.cpu.icache.overall_misses::total       1064815                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  14788071318                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  14788071318                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  14788071318                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  14788071318                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  14788071318                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  14788071318                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst      8654217                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total      8654217                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst      8654217                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total      8654217                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst      8654217                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total      8654217                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.123040                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.123040                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.123040                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.123040                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.123040                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.123040                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13887.925431                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13887.925431                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13887.925431                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13887.925431                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13887.925431                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13887.925431                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs         4640                       # number of cycles access was blocked
+system.cpu.icache.tags.tag_accesses          10094673                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         10094673                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst      7968979                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total         7968979                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst       7968979                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total          7968979                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst      7968979                       # number of overall hits
+system.cpu.icache.overall_hits::total         7968979                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst      1088360                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total       1088360                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst      1088360                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total        1088360                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst      1088360                       # number of overall misses
+system.cpu.icache.overall_misses::total       1088360                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  15140469933                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  15140469933                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  15140469933                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  15140469933                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  15140469933                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  15140469933                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst      9057339                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total      9057339                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst      9057339                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total      9057339                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst      9057339                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total      9057339                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.120163                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.120163                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.120163                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.120163                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.120163                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.120163                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13911.270106                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13911.270106                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13911.270106                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13911.270106                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13911.270106                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13911.270106                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs         4471                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs               182                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs               200                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    25.494505                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    22.355000                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst        55683                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total        55683                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst        55683                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total        55683                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst        55683                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total        55683                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1009132                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total      1009132                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst      1009132                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total      1009132                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst      1009132                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total      1009132                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  12130132326                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  12130132326                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst  12130132326                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total  12130132326                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst  12130132326                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total  12130132326                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.116606                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.116606                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.116606                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.116606                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.116606                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.116606                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12020.362377                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12020.362377                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12020.362377                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 12020.362377                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12020.362377                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 12020.362377                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst        51026                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total        51026                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst        51026                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total        51026                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst        51026                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total        51026                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1037334                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total      1037334                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst      1037334                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total      1037334                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst      1037334                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total      1037334                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  12446794989                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total  12446794989                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst  12446794989                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total  12446794989                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst  12446794989                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total  12446794989                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.114530                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.114530                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.114530                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.114530                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.114530                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.114530                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11998.830646                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11998.830646                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11998.830646                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 11998.830646                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11998.830646                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 11998.830646                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements           338319                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        65340.875442                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            2545143                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           403486                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             6.307884                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle       5540956750                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 53842.334774                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  5321.183862                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  6177.356806                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.821569                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.081195                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.094259                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.997023                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        65167                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          492                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1         3496                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         3313                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         2397                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        55469                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.994370                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         26719739                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        26719739                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst       993934                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data       827149                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        1821083                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks       840753                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total       840753                       # number of Writeback hits
+system.cpu.l2cache.tags.replacements           338424                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        65337.415563                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            2581710                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           403590                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             6.396863                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle       5538438750                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 53805.196085                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  5357.724352                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  6174.495125                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.821002                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.081752                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.094215                       # Average percentage of cache occupancy
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+system.cpu.l2cache.tags.occ_task_id_blocks::1024        65166                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          493                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1         3497                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         3323                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         2420                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        55433                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.994354                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         27024459                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        27024459                       # Number of data accesses
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 system.cpu.l2cache.UpgradeReq_hits::cpu.data           26                       # number of UpgradeReq hits
 system.cpu.l2cache.UpgradeReq_hits::total           26                       # number of UpgradeReq hits
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-system.cpu.l2cache.Writeback_accesses::writebacks       840753                       # number of Writeback accesses(hits+misses)
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-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.014947                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.248695                       # miss rate for ReadReq accesses
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-system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data     0.500000                       # miss rate for SCUpgradeReq accesses
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-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76684.971688                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 65406.591777                       # average ReadReq miss latency
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+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total  3999.852941                       # average UpgradeReq miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data         7833                       # average SCUpgradeReq miss latency
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+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 83578.047057                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76572.865733                       # average overall miss latency
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+system.cpu.l2cache.demand_avg_miss_latency::total 71204.166016                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76572.865733                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70995.456188                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 71204.166016                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1115,80 +1116,80 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        75921                       # number of writebacks
-system.cpu.l2cache.writebacks::total            75921                       # number of writebacks
+system.cpu.l2cache.writebacks::writebacks        76032                       # number of writebacks
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 system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            1                       # number of ReadReq MSHR hits
 system.cpu.l2cache.ReadReq_mshr_hits::total            1                       # number of ReadReq MSHR hits
 system.cpu.l2cache.demand_mshr_hits::cpu.inst            1                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.demand_mshr_hits::total            1                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.overall_mshr_hits::cpu.inst            1                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::total            1                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        15081                       # number of ReadReq MSHR misses
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-system.cpu.l2cache.UpgradeReq_mshr_misses::total           38                       # number of UpgradeReq MSHR misses
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-system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total        10001                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   8215113143                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   8215113143                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    966321757                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  22711287408                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  23677609165                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    966321757                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  22711287408                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  23677609165                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   1333995500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   1333995500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   1882363500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   1882363500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   3216359000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total   3216359000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.014946                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.248695                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.136913                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.593750                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.593750                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data     0.500000                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.500000                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.383397                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.383397                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.014946                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.277622                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.167693                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.014946                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.277622                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.167693                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64075.443074                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52944.197665                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53525.301064                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 13974.578947                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 13974.578947                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        15133                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data       273861                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total       288994                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data           68                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total           68                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            6                       # number of SCUpgradeReq MSHR misses
+system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            6                       # number of SCUpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       115435                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       115435                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst        15133                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       389296                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       404429                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst        15133                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       389296                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       404429                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    967955000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  14578847250                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total  15546802250                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       698067                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       698067                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data        60006                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total        60006                       # number of SCUpgradeReq MSHR miss cycles
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+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   8240977138                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    967955000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  22819824388                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  23787779388                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    967955000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  22819824388                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  23787779388                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   1333197000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   1333197000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   1882784000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   1882784000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   3215981000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total   3215981000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.014591                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.247815                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.134902                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.723404                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.723404                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data     0.214286                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.214286                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.381969                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.381969                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.014591                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.276624                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.165447                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.014591                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.276624                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.165447                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63963.193022                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 53234.477527                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53796.280373                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10265.691176                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10265.691176                       # average UpgradeReq mshr miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        10001                       # average SCUpgradeReq mshr miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        10001                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71168.420741                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71168.420741                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64075.443074                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58348.822962                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58562.427136                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64075.443074                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58348.822962                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58562.427136                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71390.627955                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71390.627955                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63963.193022                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58618.183562                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58818.184126                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63963.193022                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58618.183562                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58818.184126                       # average overall mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
@@ -1196,168 +1197,168 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements           1401429                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.994598                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            11820645                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           1401941                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs              8.431628                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle          25377000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.994598                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999989                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999989                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements           1406709                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.994656                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            11889160                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           1407221                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs              8.448680                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle          25219000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.994656                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.999990                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999990                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0          415                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1           95                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2            2                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           94                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2            3                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          63732446                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         63732446                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data      7221951                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total         7221951                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      4197394                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        4197394                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data       185535                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       185535                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data       215521                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total       215521                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      11419345                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         11419345                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     11419345                       # number of overall hits
-system.cpu.dcache.overall_hits::total        11419345                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      1789877                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       1789877                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      1948925                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      1948925                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data        23421                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total        23421                       # number of LoadLockedReq misses
-system.cpu.dcache.StoreCondReq_misses::cpu.data            2                       # number of StoreCondReq misses
-system.cpu.dcache.StoreCondReq_misses::total            2                       # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data      3738802                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        3738802                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      3738802                       # number of overall misses
-system.cpu.dcache.overall_misses::total       3738802                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  40163370133                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  40163370133                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  77928512640                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  77928512640                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    358310999                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total    358310999                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::cpu.data        38001                       # number of StoreCondReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::total        38001                       # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 118091882773                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 118091882773                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 118091882773                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 118091882773                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data      9011828                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total      9011828                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data      6146319                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total      6146319                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data       208956                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total       208956                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data       215523                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total       215523                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     15158147                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     15158147                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     15158147                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     15158147                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.198614                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.198614                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.317088                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.317088                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.112086                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.112086                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000009                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::total     0.000009                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.246653                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.246653                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.246653                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.246653                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22439.178856                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 22439.178856                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39985.383039                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 39985.383039                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15298.706247                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15298.706247                       # average LoadLockedReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 19000.500000                       # average StoreCondReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::total 19000.500000                       # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 31585.487216                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 31585.487216                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 31585.487216                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 31585.487216                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs      3437281                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets          992                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs            114395                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               8                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    30.047476                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets          124                       # average number of cycles each access was blocked
+system.cpu.dcache.tags.tag_accesses          64006618                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         64006618                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data      7294645                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total         7294645                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      4192085                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        4192085                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data       186406                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total       186406                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data       215722                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total       215722                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data      11486730                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         11486730                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     11486730                       # number of overall hits
+system.cpu.dcache.overall_hits::total        11486730                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      1781450                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       1781450                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      1956078                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      1956078                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data        23435                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total        23435                       # number of LoadLockedReq misses
+system.cpu.dcache.StoreCondReq_misses::cpu.data           28                       # number of StoreCondReq misses
+system.cpu.dcache.StoreCondReq_misses::total           28                       # number of StoreCondReq misses
+system.cpu.dcache.demand_misses::cpu.data      3737528                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        3737528                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      3737528                       # number of overall misses
+system.cpu.dcache.overall_misses::total       3737528                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  39460898751                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  39460898751                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  77926098572                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  77926098572                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    366682499                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total    366682499                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       440006                       # number of StoreCondReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::total       440006                       # number of StoreCondReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 117386997323                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 117386997323                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 117386997323                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 117386997323                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data      9076095                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total      9076095                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data      6148163                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total      6148163                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data       209841                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total       209841                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data       215750                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total       215750                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     15224258                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     15224258                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     15224258                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     15224258                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.196279                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.196279                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.318156                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.318156                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.111680                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.111680                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000130                       # miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::total     0.000130                       # miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.245498                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.245498                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.245498                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.245498                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22150.999888                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 22150.999888                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39837.930068                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 39837.930068                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15646.788948                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15646.788948                       # average LoadLockedReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15714.500000                       # average StoreCondReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15714.500000                       # average StoreCondReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 31407.656966                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 31407.656966                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 31407.656966                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 31407.656966                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs      3974317                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets         2076                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs            180350                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets              21                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    22.036690                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets    98.857143                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       840753                       # number of writebacks
-system.cpu.dcache.writebacks::total            840753                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       705849                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       705849                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1648446                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total      1648446                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data         5839                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total         5839                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      2354295                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      2354295                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      2354295                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      2354295                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1084028                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      1084028                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       300479                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       300479                       # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        17582                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total        17582                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            2                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::total            2                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      1384507                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      1384507                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      1384507                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      1384507                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  27275332511                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  27275332511                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  11834545572                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  11834545572                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    200445001                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    200445001                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data        33999                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::total        33999                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  39109878083                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  39109878083                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  39109878083                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  39109878083                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   1424085500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   1424085500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   1997539998                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   1997539998                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   3421625498                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total   3421625498                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.120289                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.120289                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.048888                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.048888                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.084142                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.084142                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000009                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000009                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.091337                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.091337                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.091337                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.091337                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25161.095941                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25161.095941                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39385.599566                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39385.599566                       # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11400.580196                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11400.580196                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 16999.500000                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 16999.500000                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28248.234269                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 28248.234269                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28248.234269                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 28248.234269                       # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks       845214                       # number of writebacks
+system.cpu.dcache.writebacks::total            845214                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       683673                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       683673                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1664672                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total      1664672                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data         5215                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total         5215                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      2348345                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      2348345                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      2348345                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      2348345                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1097777                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      1097777                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       291406                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       291406                       # number of WriteReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        18220                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total        18220                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data           28                       # number of StoreCondReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::total           28                       # number of StoreCondReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      1389183                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      1389183                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      1389183                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      1389183                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  27531600277                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  27531600277                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  11750999106                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  11750999106                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    207629251                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    207629251                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       383994                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       383994                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  39282599383                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  39282599383                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  39282599383                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  39282599383                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   1423287000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   1423287000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   1997974498                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   1997974498                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   3421261498                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total   3421261498                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.120953                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.120953                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.047397                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.047397                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.086828                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.086828                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000130                       # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000130                       # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.091248                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.091248                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.091248                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.091248                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25079.410734                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25079.410734                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40325.178981                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40325.178981                       # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11395.677881                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11395.677881                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13714.071429                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13714.071429                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28277.483516                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 28277.483516                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28277.483516                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 28277.483516                       # average overall mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
@@ -1366,28 +1367,28 @@ system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.quiesce                     6440                       # number of quiesce instructions executed
-system.cpu.kern.inst.hwrei                     211015                       # number of hwrei instructions executed
-system.cpu.kern.ipl_count::0                    74666     40.97%     40.97% # number of times we switched to this ipl
+system.cpu.kern.inst.quiesce                     6443                       # number of quiesce instructions executed
+system.cpu.kern.inst.hwrei                     211008                       # number of hwrei instructions executed
+system.cpu.kern.ipl_count::0                    74663     40.97%     40.97% # number of times we switched to this ipl
 system.cpu.kern.ipl_count::21                     131      0.07%     41.04% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::22                    1879      1.03%     42.07% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::31                  105570     57.93%    100.00% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::total               182246                       # number of times we switched to this ipl
-system.cpu.kern.ipl_good::0                     73299     49.32%     49.32% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_count::22                    1880      1.03%     42.07% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::31                  105564     57.93%    100.00% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::total               182238                       # number of times we switched to this ipl
+system.cpu.kern.ipl_good::0                     73296     49.32%     49.32% # number of times we switched to this ipl from a different ipl
 system.cpu.kern.ipl_good::21                      131      0.09%     49.41% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::22                     1879      1.26%     50.68% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::31                    73299     49.32%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::total                148608                       # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_ticks::0             1817910535000     97.73%     97.73% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::21                64222000      0.00%     97.73% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::22               554846000      0.03%     97.76% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::31             41641763000      2.24%    100.00% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::total         1860171366000                       # number of cycles we spent at this ipl
-system.cpu.kern.ipl_used::0                  0.981692                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_good::22                     1880      1.27%     50.68% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::31                    73296     49.32%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::total                148603                       # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_ticks::0             1818262027500     97.76%     97.76% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::21                61927000      0.00%     97.76% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::22               526143500      0.03%     97.79% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::31             41157993000      2.21%    100.00% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::total         1860008091000                       # number of cycles we spent at this ipl
+system.cpu.kern.ipl_used::0                  0.981691                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.ipl_used::21                        1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.ipl_used::22                        1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::31                 0.694317                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::total              0.815425                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used::31                 0.694328                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used::total              0.815434                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.syscall::2                          8      2.45%      2.45% # number of syscalls executed
 system.cpu.kern.syscall::3                         30      9.20%     11.66% # number of syscalls executed
 system.cpu.kern.syscall::4                          4      1.23%     12.88% # number of syscalls executed
@@ -1423,32 +1424,32 @@ system.cpu.kern.callpal::cserve                     1      0.00%      0.00% # nu
 system.cpu.kern.callpal::wrmces                     1      0.00%      0.00% # number of callpals executed
 system.cpu.kern.callpal::wrfen                      1      0.00%      0.00% # number of callpals executed
 system.cpu.kern.callpal::wrvptptr                   1      0.00%      0.00% # number of callpals executed
-system.cpu.kern.callpal::swpctx                  4176      2.18%      2.18% # number of callpals executed
+system.cpu.kern.callpal::swpctx                  4177      2.18%      2.18% # number of callpals executed
 system.cpu.kern.callpal::tbi                       54      0.03%      2.21% # number of callpals executed
 system.cpu.kern.callpal::wrent                      7      0.00%      2.21% # number of callpals executed
-system.cpu.kern.callpal::swpipl                175131     91.23%     93.44% # number of callpals executed
+system.cpu.kern.callpal::swpipl                175121     91.22%     93.43% # number of callpals executed
 system.cpu.kern.callpal::rdps                    6784      3.53%     96.97% # number of callpals executed
 system.cpu.kern.callpal::wrkgp                      1      0.00%     96.97% # number of callpals executed
 system.cpu.kern.callpal::wrusp                      7      0.00%     96.97% # number of callpals executed
 system.cpu.kern.callpal::rdusp                      9      0.00%     96.98% # number of callpals executed
 system.cpu.kern.callpal::whami                      2      0.00%     96.98% # number of callpals executed
-system.cpu.kern.callpal::rti                     5104      2.66%     99.64% # number of callpals executed
+system.cpu.kern.callpal::rti                     5105      2.66%     99.64% # number of callpals executed
 system.cpu.kern.callpal::callsys                  515      0.27%     99.91% # number of callpals executed
 system.cpu.kern.callpal::imb                      181      0.09%    100.00% # number of callpals executed
-system.cpu.kern.callpal::total                 191975                       # number of callpals executed
-system.cpu.kern.mode_switch::kernel              5851                       # number of protection mode switches
+system.cpu.kern.callpal::total                 191967                       # number of callpals executed
+system.cpu.kern.mode_switch::kernel              5850                       # number of protection mode switches
 system.cpu.kern.mode_switch::user                1740                       # number of protection mode switches
-system.cpu.kern.mode_switch::idle                2095                       # number of protection mode switches
+system.cpu.kern.mode_switch::idle                2098                       # number of protection mode switches
 system.cpu.kern.mode_good::kernel                1910                      
 system.cpu.kern.mode_good::user                  1740                      
 system.cpu.kern.mode_good::idle                   170                      
-system.cpu.kern.mode_switch_good::kernel     0.326440                       # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good::kernel     0.326496                       # fraction of useful protection mode switches
 system.cpu.kern.mode_switch_good::user              1                       # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::idle       0.081146                       # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::total      0.394384                       # fraction of useful protection mode switches
-system.cpu.kern.mode_ticks::kernel        29515260500      1.59%      1.59% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::user           2703792500      0.15%      1.73% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::idle         1827952305000     98.27%    100.00% # number of ticks spent at the given mode
-system.cpu.kern.swap_context                     4177                       # number of times the context was actually changed
+system.cpu.kern.mode_switch_good::idle       0.081030                       # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good::total      0.394302                       # fraction of useful protection mode switches
+system.cpu.kern.mode_ticks::kernel        29080060000      1.56%      1.56% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::user           2655672500      0.14%      1.71% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::idle         1828272350500     98.29%    100.00% # number of ticks spent at the given mode
+system.cpu.kern.swap_context                     4178                       # number of times the context was actually changed
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt
index de36b122c..6a79f5850 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt
@@ -1,147 +1,150 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  1.842688                       # Number of seconds simulated
-sim_ticks                                1842688380000                       # Number of ticks simulated
-final_tick                               1842688380000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  1.841612                       # Number of seconds simulated
+sim_ticks                                1841612285000                       # Number of ticks simulated
+final_tick                               1841612285000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 219315                       # Simulator instruction rate (inst/s)
-host_op_rate                                   219315                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             5608158508                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 303992                       # Number of bytes of host memory used
-host_seconds                                   328.57                       # Real time elapsed on the host
-sim_insts                                    72060922                       # Number of instructions simulated
-sim_ops                                      72060922                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 168459                       # Simulator instruction rate (inst/s)
+host_op_rate                                   168459                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             4750760669                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 319468                       # Number of bytes of host memory used
+host_seconds                                   387.65                       # Real time elapsed on the host
+sim_insts                                    65302548                       # Number of instructions simulated
+sim_ops                                      65302548                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu0.inst           480512                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data         20113024                       # Number of bytes read from this memory
-system.physmem.bytes_read::tsunami.ide        2652352                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           147456                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data          2236096                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.inst           291264                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.data          2520128                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             28440832                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       480512                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       147456                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu2.inst       291264                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          919232                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7466176                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7466176                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.inst              7508                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data            314266                       # Number of read requests responded to by this memory
-system.physmem.num_reads::tsunami.ide           41443                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              2304                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data             34939                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.inst              4551                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.data             39377                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                444388                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          116659                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               116659                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.inst              260767                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data            10915044                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::tsunami.ide           1439393                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               80022                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data             1213497                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst              158065                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data             1367637                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                15434423                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         260767                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          80022                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst         158065                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             498854                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           4051784                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                4051784                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           4051784                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             260767                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data           10915044                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::tsunami.ide          1439393                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              80022                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data            1213497                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst             158065                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data            1367637                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               19486207                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                         98062                       # Number of read requests accepted
-system.physmem.writeReqs                        44473                       # Number of write requests accepted
-system.physmem.readBursts                       98062                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                      44473                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                  6274816                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      1152                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   2845184                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                   6275968                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                2846272                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                       18                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytes_read::cpu0.inst           475840                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data         19999104                       # Number of bytes read from this memory
+system.physmem.bytes_read::tsunami.ide            960                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           147008                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data          2248128                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.inst           298624                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.data          2645376                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             25815040                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       475840                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       147008                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu2.inst       298624                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          921472                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      4825408                       # Number of bytes written to this memory
+system.physmem.bytes_written::tsunami.ide      2659328                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7484736                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.inst              7435                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data            312486                       # Number of read requests responded to by this memory
+system.physmem.num_reads::tsunami.ide              15                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst              2297                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data             35127                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.inst              4666                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.data             41334                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                403360                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           75397                       # Number of write requests responded to by this memory
+system.physmem.num_writes::tsunami.ide          41552                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               116949                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.inst              258382                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data            10859563                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::tsunami.ide               521                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               79826                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data             1220739                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.inst              162154                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.data             1436446                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                14017630                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         258382                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          79826                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu2.inst         162154                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             500362                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           2620208                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::tsunami.ide          1444022                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                4064230                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           2620208                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             258382                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data           10859563                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::tsunami.ide          1444543                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              79826                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data            1220739                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.inst             162154                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.data            1436446                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               18081860                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                         83439                       # Number of read requests accepted
+system.physmem.writeReqs                        46740                       # Number of write requests accepted
+system.physmem.readBursts                       83439                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                      46740                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                  5337024                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      3072                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   2989888                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                   5340096                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                2991360                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                       48                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs             40                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                6096                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                5927                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                6222                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                6258                       # Per bank write bursts
-system.physmem.perBankRdBursts::4                5693                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                6247                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                5971                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                5980                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                6426                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                5994                       # Per bank write bursts
-system.physmem.perBankRdBursts::10               6527                       # Per bank write bursts
-system.physmem.perBankRdBursts::11               6117                       # Per bank write bursts
-system.physmem.perBankRdBursts::12               5881                       # Per bank write bursts
-system.physmem.perBankRdBursts::13               6322                       # Per bank write bursts
-system.physmem.perBankRdBursts::14               6340                       # Per bank write bursts
-system.physmem.perBankRdBursts::15               6043                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                2729                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                2556                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                2841                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                3001                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                2678                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                2962                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                2867                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                2601                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                3150                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                2533                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               3049                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               2640                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               2384                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               2771                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               2950                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               2744                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs             52                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0                5256                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                5087                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                5115                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                5179                       # Per bank write bursts
+system.physmem.perBankRdBursts::4                5173                       # Per bank write bursts
+system.physmem.perBankRdBursts::5                5205                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                5267                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                5273                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                5423                       # Per bank write bursts
+system.physmem.perBankRdBursts::9                5013                       # Per bank write bursts
+system.physmem.perBankRdBursts::10               5464                       # Per bank write bursts
+system.physmem.perBankRdBursts::11               5273                       # Per bank write bursts
+system.physmem.perBankRdBursts::12               4813                       # Per bank write bursts
+system.physmem.perBankRdBursts::13               5124                       # Per bank write bursts
+system.physmem.perBankRdBursts::14               5602                       # Per bank write bursts
+system.physmem.perBankRdBursts::15               5124                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                2825                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                2787                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                2858                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                3069                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                3024                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                2822                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                3224                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                2821                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                3331                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                2683                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               3131                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               2953                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               2475                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               2748                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               3227                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               2739                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                           8                       # Number of times write queue was full causing retry
-system.physmem.totGap                    1841676054500                       # Total gap between requests
+system.physmem.numWrRetry                           1                       # Number of times write queue was full causing retry
+system.physmem.totGap                    1840600008500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                   98062                       # Read request sizes (log2)
+system.physmem.readPktSize::6                   83439                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                  44473                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                     65686                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      7740                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                      8102                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                      2064                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                       855                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                      1814                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                      1613                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                      1627                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                      1004                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                       871                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                      858                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                      847                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                      653                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                      645                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                      779                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                      766                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                      872                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                      494                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                      391                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                      362                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                        1                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                  46740                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                     66354                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      7773                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                      7422                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                      1810                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                        22                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                         1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                         1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                         1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
@@ -153,400 +156,398 @@ system.physmem.rdQLenPdf::28                        0                       # Wh
 system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                        76                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1                        52                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                        45                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                        43                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                        42                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0                        77                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1                        56                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2                        46                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3                        44                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4                        43                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::5                        42                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                        41                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                        38                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                        36                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                        36                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10                       35                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                       35                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12                       35                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13                       35                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                       35                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                      586                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                      612                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     1247                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     1386                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     1579                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     1688                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     1686                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     1737                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     1810                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     1870                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     1937                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     2004                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     2070                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     2198                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     2105                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     2188                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     2144                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     2115                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      355                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      355                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      371                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      340                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      362                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      364                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      402                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      384                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      456                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      479                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      463                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::49                      792                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                      771                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                      700                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                      689                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                      741                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                      691                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                      362                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                      181                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                      100                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       61                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       29                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       24                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       22                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       13                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       16                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        21822                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      417.926863                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     236.963090                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     396.574874                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127           6839     31.34%     31.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255         4667     21.39%     52.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         1650      7.56%     60.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         1022      4.68%     64.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639          930      4.26%     69.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767          496      2.27%     71.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895          383      1.76%     73.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          375      1.72%     74.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         5460     25.02%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          21822                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          2614                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        37.504973                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      907.786867                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047           2612     99.92%     99.92% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2048-4095            1      0.04%     99.96% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::45056-47103            1      0.04%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            2614                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          2614                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        17.006886                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.398766                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        4.165807                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::1                  24      0.92%      0.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::2                   7      0.27%      1.19% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::3                   2      0.08%      1.26% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::4                   1      0.04%      1.30% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::5                   1      0.04%      1.34% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::7                   3      0.11%      1.45% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::8                   2      0.08%      1.53% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::10                  1      0.04%      1.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::13                  1      0.04%      1.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::15                  1      0.04%      1.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16               1860     71.16%     72.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17                 26      0.99%     73.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18                431     16.49%     90.28% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19                 74      2.83%     93.11% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                 23      0.88%     93.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21                  9      0.34%     94.34% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22                 11      0.42%     94.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23                 40      1.53%     96.29% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24                  8      0.31%     96.60% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::25                 18      0.69%     97.28% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26                  8      0.31%     97.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::27                  7      0.27%     97.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28                  3      0.11%     97.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::29                  5      0.19%     98.16% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::30                  6      0.23%     98.39% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::31                  9      0.34%     98.74% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32                  5      0.19%     98.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::33                  1      0.04%     98.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::34                  1      0.04%     99.01% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::35                  1      0.04%     99.04% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36                  1      0.04%     99.08% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::37                  1      0.04%     99.12% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::39                  4      0.15%     99.27% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::41                  3      0.11%     99.39% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::42                  2      0.08%     99.46% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::43                  1      0.04%     99.50% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::47                  1      0.04%     99.54% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48                  4      0.15%     99.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::51                  1      0.04%     99.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::53                  1      0.04%     99.77% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56                  3      0.11%     99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::57                  2      0.08%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::58                  1      0.04%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            2614                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     2880597750                       # Total ticks spent queuing
-system.physmem.totMemAccLat                4718922750                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    490220000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       29380.66                       # Average queueing delay per DRAM burst
+system.physmem.wrQLenPdf::6                        42                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7                        40                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::51                       42                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                       41                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                       43                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                       39                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                       30                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                       29                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                       25                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                       17                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                       11                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                        9                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                        5                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                        3                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                        2                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        21530                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      386.758569                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     220.447203                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     381.120515                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127           7019     32.60%     32.60% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255         4847     22.51%     55.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         1849      8.59%     63.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         1051      4.88%     68.58% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639          911      4.23%     72.81% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767          506      2.35%     75.16% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          375      1.74%     76.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          418      1.94%     78.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         4554     21.15%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          21530                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          2040                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        40.873529                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev     1027.655163                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047           2038     99.90%     99.90% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2048-4095            1      0.05%     99.95% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::45056-47103            1      0.05%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total            2040                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          2040                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        22.900490                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.614282                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       22.575456                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::0-3                33      1.62%      1.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::4-7                 7      0.34%      1.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::8-11                1      0.05%      2.01% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::12-15               5      0.25%      2.25% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            1695     83.09%     85.34% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23              37      1.81%     87.16% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27               5      0.25%     87.40% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31             107      5.25%     92.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35               7      0.34%     92.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39               2      0.10%     93.09% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43               1      0.05%     93.14% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47               3      0.15%     93.28% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51               8      0.39%     93.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55               1      0.05%     93.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59               1      0.05%     93.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67               2      0.10%     93.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71               1      0.05%     93.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75               2      0.10%     94.02% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79               2      0.10%     94.12% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83               8      0.39%     94.51% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87               3      0.15%     94.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91               3      0.15%     94.80% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95               2      0.10%     94.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99              78      3.82%     98.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             1      0.05%     98.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115             2      0.10%     98.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::116-119             1      0.05%     98.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131             7      0.34%     99.26% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135             2      0.10%     99.36% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-139             3      0.15%     99.51% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143             1      0.05%     99.56% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147             3      0.15%     99.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::148-151             1      0.05%     99.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-155             1      0.05%     99.80% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::224-227             4      0.20%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            2040                       # Writes before turning the bus around for reads
+system.physmem.totQLat                      869064750                       # Total ticks spent queuing
+system.physmem.totMemAccLat                2432646000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    416955000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       10421.57                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  48130.66                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           3.41                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           1.54                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        3.41                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        1.54                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  29171.57                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           2.90                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           1.62                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        2.90                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        1.62                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.04                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
+system.physmem.busUtilRead                       0.02                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.11                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                         4.05                       # Average write queue length when enqueuing
-system.physmem.readRowHits                      85382                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     35296                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   87.09                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  79.37                       # Row buffer hit rate for writes
-system.physmem.avgGap                     12920868.94                       # Average gap between requests
-system.physmem.pageHitRate                      84.68                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE     1767714784750                       # Time in different power states
-system.physmem.memoryStateTime::REF       61531340000                       # Time in different power states
+system.physmem.avgRdQLen                         1.19                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                         8.28                       # Average write queue length when enqueuing
+system.physmem.readRowHits                      71609                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     36969                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   85.87                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  79.09                       # Row buffer hit rate for writes
+system.physmem.avgGap                     14138993.30                       # Average gap between requests
+system.physmem.pageHitRate                      83.44                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE     1766589196000                       # Time in different power states
+system.physmem.memoryStateTime::REF       61495460000                       # Time in different power states
 system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT       13440274000                       # Time in different power states
+system.physmem.memoryStateTime::ACT       13527240250                       # Time in different power states
 system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.membus.throughput                     19530148                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq               44582                       # Transaction distribution
-system.membus.trans_dist::ReadResp              44547                       # Transaction distribution
-system.membus.trans_dist::WriteReq               3734                       # Transaction distribution
-system.membus.trans_dist::WriteResp              3734                       # Transaction distribution
-system.membus.trans_dist::Writeback             44473                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq               43                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp              43                       # Transaction distribution
-system.membus.trans_dist::ReadExReq             56556                       # Transaction distribution
-system.membus.trans_dist::ReadExResp            56556                       # Transaction distribution
-system.membus.trans_dist::BadAddressError           35                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave        13238                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       190124                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio           70                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total       203432                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        50712                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total        50712                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 254144                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave        15652                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port      6962432                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::total      6978084                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port      2159808                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::total      2159808                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total             9137892                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus               35977992                       # Total data (bytes)
-system.membus.snoop_data_through_bus             9984                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy            12394500                       # Layer occupancy (ticks)
+system.membus.throughput                     18112095                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq               44765                       # Transaction distribution
+system.membus.trans_dist::ReadResp              44760                       # Transaction distribution
+system.membus.trans_dist::WriteReq               3528                       # Transaction distribution
+system.membus.trans_dist::WriteResp              3528                       # Transaction distribution
+system.membus.trans_dist::Writeback             29460                       # Transaction distribution
+system.membus.trans_dist::WriteInvalidateReq        17280                       # Transaction distribution
+system.membus.trans_dist::WriteInvalidateResp        17280                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq               50                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp              52                       # Transaction distribution
+system.membus.trans_dist::ReadExReq             41656                       # Transaction distribution
+system.membus.trans_dist::ReadExResp            41656                       # Transaction distribution
+system.membus.trans_dist::BadAddressError            5                       # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave        12900                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       196412                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio           10                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total       209322                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        34645                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total        34645                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 243967                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave        15792                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port      7224576                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::total      7240368                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port      1106880                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.iocache.mem_side::total      1106880                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total             8347248                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus               33351936                       # Total data (bytes)
+system.membus.snoop_data_through_bus             3520                       # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy            11434500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy           511002500                       # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy           517398750                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy               45000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy                6500                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy          763523207                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy          783386948                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy          153153250                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy           17911250                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.l2c.tags.replacements                   337462                       # number of replacements
-system.l2c.tags.tagsinuse                65424.483078                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    2473806                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                   402625                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                     6.144194                       # Average number of references to valid blocks.
+system.l2c.tags.replacements                   337577                       # number of replacements
+system.l2c.tags.tagsinuse                65421.096735                       # Cycle average of tags in use
+system.l2c.tags.total_refs                    2486717                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                   402739                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                     6.174513                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle                614754000                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   54864.362424                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     2329.333896                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     2645.609154                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst      576.513665                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data      589.890909                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.inst     2235.608932                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.data     2183.164099                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.837164                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.035543                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.040369                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.008797                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.009001                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.inst       0.034113                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.data       0.033312                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.998298                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1024        65163                       # Occupied blocks per task id
+system.l2c.tags.occ_blocks::writebacks   54723.362784                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     2335.935658                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     2702.236553                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst      571.913553                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data      605.884543                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.inst     2280.035703                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.data     2201.727940                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.835012                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst       0.035644                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data       0.041233                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.008727                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data       0.009245                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.inst       0.034791                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.data       0.033596                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.998247                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1024        65162                       # Occupied blocks per task id
 system.l2c.tags.age_task_id_blocks_1024::0          168                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1         1028                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         5611                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         2976                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        55380                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1024     0.994308                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                 26155869                       # Number of tag accesses
-system.l2c.tags.data_accesses                26155869                       # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.inst             519275                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data             492761                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst             124644                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data              83355                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.inst             294324                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.data             240703                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                1755062                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks          835893                       # number of Writeback hits
-system.l2c.Writeback_hits::total               835893                       # number of Writeback hits
+system.l2c.tags.age_task_id_blocks_1024::1         1013                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2         5951                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3         2686                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        55344                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1024     0.994293                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                 26259828                       # Number of tag accesses
+system.l2c.tags.data_accesses                26259828                       # Number of data accesses
+system.l2c.ReadReq_hits::cpu0.inst             505337                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.data             482025                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.inst             122124                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.data              80194                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu2.inst             322880                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu2.data             255461                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                1768021                       # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks          835818                       # number of Writeback hits
+system.l2c.Writeback_hits::total               835818                       # number of Writeback hits
 system.l2c.UpgradeReq_hits::cpu0.data               3                       # number of UpgradeReq hits
 system.l2c.UpgradeReq_hits::cpu1.data               1                       # number of UpgradeReq hits
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 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -555,97 +556,105 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
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+system.l2c.overall_mshr_uncacheable_latency::cpu2.data    716086000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total   1252840500                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.018462                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.173172                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2.inst     0.014245                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2.data     0.065871                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.020321                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data     0.565217                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.361111                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu2.data     0.222222                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.222222                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.420887                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu2.data     0.247538                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.137718                       # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.018462                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.249966                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.inst     0.014245                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.data     0.112465                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.035391                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.018462                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.249966                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.inst     0.014245                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.data     0.112465                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.035391                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 62418.807140                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 54191.652774                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 62856.729533                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 54418.035972                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 55709.549230                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10347.153846                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10347.153846                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu2.data        10001                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        10001                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 56100.022354                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 71260.107357                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 64591.095316                       # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 62418.807140                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 55187.793779                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 62856.729533                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.data 63925.748852                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 60146.065907                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 62418.807140                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 55187.793779                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 62856.729533                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.data 63925.748852                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 60146.065907                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -657,101 +666,93 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data          inf
 system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
 system.iocache.tags.replacements                41685                       # number of replacements
-system.iocache.tags.tagsinuse                1.254888                       # Cycle average of tags in use
+system.iocache.tags.tagsinuse                1.254802                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs                41701                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         1694865618000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::tsunami.ide     1.254888                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::tsunami.ide     0.078431                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.078431                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         1693889914000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::tsunami.ide     1.254802                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::tsunami.ide     0.078425                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.078425                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
 system.iocache.tags.tag_accesses               375525                       # Number of tag accesses
 system.iocache.tags.data_accesses              375525                       # Number of data accesses
+system.iocache.WriteInvalidateReq_hits::tsunami.ide        41552                       # number of WriteInvalidateReq hits
+system.iocache.WriteInvalidateReq_hits::total        41552                       # number of WriteInvalidateReq hits
 system.iocache.ReadReq_misses::tsunami.ide          173                       # number of ReadReq misses
 system.iocache.ReadReq_misses::total              173                       # number of ReadReq misses
-system.iocache.WriteReq_misses::tsunami.ide        41552                       # number of WriteReq misses
-system.iocache.WriteReq_misses::total           41552                       # number of WriteReq misses
-system.iocache.demand_misses::tsunami.ide        41725                       # number of demand (read+write) misses
-system.iocache.demand_misses::total             41725                       # number of demand (read+write) misses
-system.iocache.overall_misses::tsunami.ide        41725                       # number of overall misses
-system.iocache.overall_misses::total            41725                       # number of overall misses
-system.iocache.ReadReq_miss_latency::tsunami.ide      9303463                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total      9303463                       # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency::tsunami.ide   5047462530                       # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_latency::total   5047462530                       # number of WriteReq miss cycles
-system.iocache.demand_miss_latency::tsunami.ide   5056765993                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   5056765993                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::tsunami.ide   5056765993                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   5056765993                       # number of overall miss cycles
+system.iocache.demand_misses::tsunami.ide          173                       # number of demand (read+write) misses
+system.iocache.demand_misses::total               173                       # number of demand (read+write) misses
+system.iocache.overall_misses::tsunami.ide          173                       # number of overall misses
+system.iocache.overall_misses::total              173                       # number of overall misses
+system.iocache.ReadReq_miss_latency::tsunami.ide      9417462                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total      9417462                       # number of ReadReq miss cycles
+system.iocache.demand_miss_latency::tsunami.ide      9417462                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total      9417462                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::tsunami.ide      9417462                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total      9417462                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::tsunami.ide          173                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            173                       # number of ReadReq accesses(hits+misses)
-system.iocache.WriteReq_accesses::tsunami.ide        41552                       # number of WriteReq accesses(hits+misses)
-system.iocache.WriteReq_accesses::total         41552                       # number of WriteReq accesses(hits+misses)
-system.iocache.demand_accesses::tsunami.ide        41725                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total           41725                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::tsunami.ide        41725                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total          41725                       # number of overall (read+write) accesses
+system.iocache.WriteInvalidateReq_accesses::tsunami.ide        41552                       # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::total        41552                       # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.demand_accesses::tsunami.ide          173                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total             173                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::tsunami.ide          173                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total            173                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
-system.iocache.WriteReq_miss_rate::tsunami.ide            1                       # miss rate for WriteReq accesses
-system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
 system.iocache.demand_miss_rate::tsunami.ide            1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::tsunami.ide 53777.242775                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 53777.242775                       # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::tsunami.ide 121473.395504                       # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total 121473.395504                       # average WriteReq miss latency
-system.iocache.demand_avg_miss_latency::tsunami.ide 121192.714032                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 121192.714032                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::tsunami.ide 121192.714032                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 121192.714032                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs        149207                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::tsunami.ide 54436.196532                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 54436.196532                       # average ReadReq miss latency
+system.iocache.demand_avg_miss_latency::tsunami.ide 54436.196532                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 54436.196532                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::tsunami.ide 54436.196532                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 54436.196532                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                11483                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs    12.993730                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.fast_writes                          0                       # number of fast writes performed
+system.iocache.fast_writes                      41552                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.writebacks::writebacks           41512                       # number of writebacks
-system.iocache.writebacks::total                41512                       # number of writebacks
-system.iocache.ReadReq_mshr_misses::tsunami.ide           69                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total           69                       # number of ReadReq MSHR misses
-system.iocache.WriteReq_mshr_misses::tsunami.ide        16896                       # number of WriteReq MSHR misses
-system.iocache.WriteReq_mshr_misses::total        16896                       # number of WriteReq MSHR misses
-system.iocache.demand_mshr_misses::tsunami.ide        16965                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total        16965                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::tsunami.ide        16965                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total        16965                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::tsunami.ide      5714463                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total      5714463                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::tsunami.ide   4167935030                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::total   4167935030                       # number of WriteReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::tsunami.ide   4173649493                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   4173649493                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::tsunami.ide   4173649493                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   4173649493                       # number of overall MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_rate::tsunami.ide     0.398844                       # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::total     0.398844                       # mshr miss rate for ReadReq accesses
-system.iocache.WriteReq_mshr_miss_rate::tsunami.ide     0.406623                       # mshr miss rate for WriteReq accesses
-system.iocache.WriteReq_mshr_miss_rate::total     0.406623                       # mshr miss rate for WriteReq accesses
-system.iocache.demand_mshr_miss_rate::tsunami.ide     0.406591                       # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total     0.406591                       # mshr miss rate for demand accesses
-system.iocache.overall_mshr_miss_rate::tsunami.ide     0.406591                       # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total     0.406591                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 82818.304348                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 82818.304348                       # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 246681.760772                       # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total 246681.760772                       # average WriteReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 246015.295785                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 246015.295785                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 246015.295785                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 246015.295785                       # average overall mshr miss latency
+system.iocache.ReadReq_mshr_misses::tsunami.ide           70                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total           70                       # number of ReadReq MSHR misses
+system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide        17280                       # number of WriteInvalidateReq MSHR misses
+system.iocache.WriteInvalidateReq_mshr_misses::total        17280                       # number of WriteInvalidateReq MSHR misses
+system.iocache.demand_mshr_misses::tsunami.ide           70                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total           70                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::tsunami.ide           70                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total           70                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::tsunami.ide      5776462                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total      5776462                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide   1039320090                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::total   1039320090                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::tsunami.ide      5776462                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total      5776462                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::tsunami.ide      5776462                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total      5776462                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_rate::tsunami.ide     0.404624                       # mshr miss rate for ReadReq accesses
+system.iocache.ReadReq_mshr_miss_rate::total     0.404624                       # mshr miss rate for ReadReq accesses
+system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide     0.415864                       # mshr miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_mshr_miss_rate::total     0.415864                       # mshr miss rate for WriteInvalidateReq accesses
+system.iocache.demand_mshr_miss_rate::tsunami.ide     0.404624                       # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::total     0.404624                       # mshr miss rate for demand accesses
+system.iocache.overall_mshr_miss_rate::tsunami.ide     0.404624                       # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::total     0.404624                       # mshr miss rate for overall accesses
+system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 82520.885714                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 82520.885714                       # average ReadReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 60145.838542                       # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60145.838542                       # average WriteInvalidateReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 82520.885714                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 82520.885714                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 82520.885714                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 82520.885714                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
@@ -769,22 +770,22 @@ system.cpu0.dtb.fetch_hits                          0                       # IT
 system.cpu0.dtb.fetch_misses                        0                       # ITB misses
 system.cpu0.dtb.fetch_acv                           0                       # ITB acv
 system.cpu0.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu0.dtb.read_hits                     4913708                       # DTB read hits
-system.cpu0.dtb.read_misses                      6100                       # DTB read misses
-system.cpu0.dtb.read_acv                          126                       # DTB read access violations
-system.cpu0.dtb.read_accesses                  428235                       # DTB read accesses
-system.cpu0.dtb.write_hits                    3510172                       # DTB write hits
-system.cpu0.dtb.write_misses                      671                       # DTB write misses
-system.cpu0.dtb.write_acv                          84                       # DTB write access violations
-system.cpu0.dtb.write_accesses                 163990                       # DTB write accesses
-system.cpu0.dtb.data_hits                     8423880                       # DTB hits
-system.cpu0.dtb.data_misses                      6771                       # DTB misses
-system.cpu0.dtb.data_acv                          210                       # DTB access violations
-system.cpu0.dtb.data_accesses                  592225                       # DTB accesses
-system.cpu0.itb.fetch_hits                    2758823                       # ITB hits
-system.cpu0.itb.fetch_misses                     3034                       # ITB misses
-system.cpu0.itb.fetch_acv                         104                       # ITB acv
-system.cpu0.itb.fetch_accesses                2761857                       # ITB accesses
+system.cpu0.dtb.read_hits                     4820184                       # DTB read hits
+system.cpu0.dtb.read_misses                      5970                       # DTB read misses
+system.cpu0.dtb.read_acv                          109                       # DTB read access violations
+system.cpu0.dtb.read_accesses                  427969                       # DTB read accesses
+system.cpu0.dtb.write_hits                    3428698                       # DTB write hits
+system.cpu0.dtb.write_misses                      674                       # DTB write misses
+system.cpu0.dtb.write_acv                          81                       # DTB write access violations
+system.cpu0.dtb.write_accesses                 164325                       # DTB write accesses
+system.cpu0.dtb.data_hits                     8248882                       # DTB hits
+system.cpu0.dtb.data_misses                      6644                       # DTB misses
+system.cpu0.dtb.data_acv                          190                       # DTB access violations
+system.cpu0.dtb.data_accesses                  592294                       # DTB accesses
+system.cpu0.itb.fetch_hits                    2727685                       # ITB hits
+system.cpu0.itb.fetch_misses                     3015                       # ITB misses
+system.cpu0.itb.fetch_acv                          97                       # ITB acv
+system.cpu0.itb.fetch_accesses                2730700                       # ITB accesses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.read_acv                            0                       # DTB read access violations
@@ -797,87 +798,87 @@ system.cpu0.itb.data_hits                           0                       # DT
 system.cpu0.itb.data_misses                         0                       # DTB misses
 system.cpu0.itb.data_acv                            0                       # DTB access violations
 system.cpu0.itb.data_accesses                       0                       # DTB accesses
-system.cpu0.numCycles                       928196841                       # number of cpu cycles simulated
+system.cpu0.numCycles                       929885466                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                   33463552                       # Number of instructions committed
-system.cpu0.committedOps                     33463552                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses             31328637                       # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses                169756                       # Number of float alu accesses
-system.cpu0.num_func_calls                     812549                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts      4574772                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                    31328637                       # number of integer instructions
-system.cpu0.num_fp_insts                       169756                       # number of float instructions
-system.cpu0.num_int_register_reads           43916482                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes          22873823                       # number of times the integer registers were written
-system.cpu0.num_fp_register_reads               87693                       # number of times the floating registers were read
-system.cpu0.num_fp_register_writes              89172                       # number of times the floating registers were written
-system.cpu0.num_mem_refs                      8454037                       # number of memory refs
-system.cpu0.num_load_insts                    4935095                       # Number of load instructions
-system.cpu0.num_store_insts                   3518942                       # Number of store instructions
-system.cpu0.num_idle_cycles              904607153.884767                       # Number of idle cycles
-system.cpu0.num_busy_cycles              23589687.115233                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.025415                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.974585                       # Percentage of idle cycles
-system.cpu0.Branches                          5650356                       # Number of branches fetched
-system.cpu0.op_class::No_OpClass              1614853      4.82%      4.82% # Class of executed instruction
-system.cpu0.op_class::IntAlu                 22689020     67.79%     72.61% # Class of executed instruction
-system.cpu0.op_class::IntMult                   32419      0.10%     72.71% # Class of executed instruction
-system.cpu0.op_class::IntDiv                        0      0.00%     72.71% # Class of executed instruction
-system.cpu0.op_class::FloatAdd                  12179      0.04%     72.75% # Class of executed instruction
-system.cpu0.op_class::FloatCmp                      0      0.00%     72.75% # Class of executed instruction
-system.cpu0.op_class::FloatCvt                      0      0.00%     72.75% # Class of executed instruction
-system.cpu0.op_class::FloatMult                     0      0.00%     72.75% # Class of executed instruction
-system.cpu0.op_class::FloatDiv                   1606      0.00%     72.75% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt                     0      0.00%     72.75% # Class of executed instruction
-system.cpu0.op_class::SimdAdd                       0      0.00%     72.75% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc                    0      0.00%     72.75% # Class of executed instruction
-system.cpu0.op_class::SimdAlu                       0      0.00%     72.75% # Class of executed instruction
-system.cpu0.op_class::SimdCmp                       0      0.00%     72.75% # Class of executed instruction
-system.cpu0.op_class::SimdCvt                       0      0.00%     72.75% # Class of executed instruction
-system.cpu0.op_class::SimdMisc                      0      0.00%     72.75% # Class of executed instruction
-system.cpu0.op_class::SimdMult                      0      0.00%     72.75% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc                   0      0.00%     72.75% # Class of executed instruction
-system.cpu0.op_class::SimdShift                     0      0.00%     72.75% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc                  0      0.00%     72.75% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt                      0      0.00%     72.75% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd                  0      0.00%     72.75% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu                  0      0.00%     72.75% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp                  0      0.00%     72.75% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt                  0      0.00%     72.75% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv                  0      0.00%     72.75% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc                 0      0.00%     72.75% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult                 0      0.00%     72.75% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     72.75% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     72.75% # Class of executed instruction
-system.cpu0.op_class::MemRead                 5069147     15.15%     87.90% # Class of executed instruction
-system.cpu0.op_class::MemWrite                3522084     10.52%     98.42% # Class of executed instruction
-system.cpu0.op_class::IprAccess                529225      1.58%    100.00% # Class of executed instruction
+system.cpu0.committedInsts                   30965233                       # Number of instructions committed
+system.cpu0.committedOps                     30965233                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses             28877959                       # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses                164894                       # Number of float alu accesses
+system.cpu0.num_func_calls                     798570                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts      3871145                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                    28877959                       # number of integer instructions
+system.cpu0.num_fp_insts                       164894                       # number of float instructions
+system.cpu0.num_int_register_reads           39995093                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes          21215374                       # number of times the integer registers were written
+system.cpu0.num_fp_register_reads               85232                       # number of times the floating registers were read
+system.cpu0.num_fp_register_writes              86749                       # number of times the floating registers were written
+system.cpu0.num_mem_refs                      8278255                       # number of memory refs
+system.cpu0.num_load_insts                    4840998                       # Number of load instructions
+system.cpu0.num_store_insts                   3437257                       # Number of store instructions
+system.cpu0.num_idle_cycles              908001022.276160                       # Number of idle cycles
+system.cpu0.num_busy_cycles              21884443.723840                       # Number of busy cycles
+system.cpu0.not_idle_fraction                0.023535                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                    0.976465                       # Percentage of idle cycles
+system.cpu0.Branches                          4926958                       # Number of branches fetched
+system.cpu0.op_class::No_OpClass              1578460      5.10%      5.10% # Class of executed instruction
+system.cpu0.op_class::IntAlu                 20418617     65.93%     71.02% # Class of executed instruction
+system.cpu0.op_class::IntMult                   31850      0.10%     71.13% # Class of executed instruction
+system.cpu0.op_class::IntDiv                        0      0.00%     71.13% # Class of executed instruction
+system.cpu0.op_class::FloatAdd                  12902      0.04%     71.17% # Class of executed instruction
+system.cpu0.op_class::FloatCmp                      0      0.00%     71.17% # Class of executed instruction
+system.cpu0.op_class::FloatCvt                      0      0.00%     71.17% # Class of executed instruction
+system.cpu0.op_class::FloatMult                     0      0.00%     71.17% # Class of executed instruction
+system.cpu0.op_class::FloatDiv                   1598      0.01%     71.17% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt                     0      0.00%     71.17% # Class of executed instruction
+system.cpu0.op_class::SimdAdd                       0      0.00%     71.17% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc                    0      0.00%     71.17% # Class of executed instruction
+system.cpu0.op_class::SimdAlu                       0      0.00%     71.17% # Class of executed instruction
+system.cpu0.op_class::SimdCmp                       0      0.00%     71.17% # Class of executed instruction
+system.cpu0.op_class::SimdCvt                       0      0.00%     71.17% # Class of executed instruction
+system.cpu0.op_class::SimdMisc                      0      0.00%     71.17% # Class of executed instruction
+system.cpu0.op_class::SimdMult                      0      0.00%     71.17% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc                   0      0.00%     71.17% # Class of executed instruction
+system.cpu0.op_class::SimdShift                     0      0.00%     71.17% # Class of executed instruction
+system.cpu0.op_class::SimdShiftAcc                  0      0.00%     71.17% # Class of executed instruction
+system.cpu0.op_class::SimdSqrt                      0      0.00%     71.17% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAdd                  0      0.00%     71.17% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAlu                  0      0.00%     71.17% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCmp                  0      0.00%     71.17% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCvt                  0      0.00%     71.17% # Class of executed instruction
+system.cpu0.op_class::SimdFloatDiv                  0      0.00%     71.17% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc                 0      0.00%     71.17% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMult                 0      0.00%     71.17% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     71.17% # Class of executed instruction
+system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     71.17% # Class of executed instruction
+system.cpu0.op_class::MemRead                 4971884     16.05%     87.22% # Class of executed instruction
+system.cpu0.op_class::MemWrite                3440357     11.11%     98.33% # Class of executed instruction
+system.cpu0.op_class::IprAccess                516399      1.67%    100.00% # Class of executed instruction
 system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu0.op_class::total                  33470533                       # Class of executed instruction
+system.cpu0.op_class::total                  30972067                       # Class of executed instruction
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                    6420                       # number of quiesce instructions executed
-system.cpu0.kern.inst.hwrei                    211388                       # number of hwrei instructions executed
-system.cpu0.kern.ipl_count::0                   74806     40.97%     40.97% # number of times we switched to this ipl
+system.cpu0.kern.inst.quiesce                    6423                       # number of quiesce instructions executed
+system.cpu0.kern.inst.hwrei                    211353                       # number of hwrei instructions executed
+system.cpu0.kern.ipl_count::0                   74794     40.97%     40.97% # number of times we switched to this ipl
 system.cpu0.kern.ipl_count::21                    203      0.11%     41.08% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::22                   1879      1.03%     42.11% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::31                 105697     57.89%    100.00% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::total              182585                       # number of times we switched to this ipl
-system.cpu0.kern.ipl_good::0                    73439     49.30%     49.30% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_count::22                   1878      1.03%     42.11% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::31                 105680     57.89%    100.00% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::total              182555                       # number of times we switched to this ipl
+system.cpu0.kern.ipl_good::0                    73427     49.30%     49.30% # number of times we switched to this ipl from a different ipl
 system.cpu0.kern.ipl_good::21                     203      0.14%     49.44% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::22                    1879      1.26%     50.70% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::31                   73439     49.30%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::total               148960                       # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_ticks::0            1819515986000     98.74%     98.74% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::21               38828500      0.00%     98.74% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::22              364353500      0.02%     98.76% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::31            22768442500      1.24%    100.00% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::total        1842687610500                       # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_used::0                 0.981726                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_good::22                    1878      1.26%     50.70% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::31                   73427     49.30%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::total               148935                       # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_ticks::0            1818769989500     98.76%     98.76% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::21               39220500      0.00%     98.76% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::22              357294000      0.02%     98.78% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::31            22445011500      1.22%    100.00% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::total        1841611515500                       # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_used::0                 0.981723                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::21                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::31                0.694807                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::total             0.815839                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used::31                0.694805                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used::total             0.815836                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.syscall::2                         8      2.45%      2.45% # number of syscalls executed
 system.cpu0.kern.syscall::3                        30      9.20%     11.66% # number of syscalls executed
 system.cpu0.kern.syscall::4                         4      1.23%     12.88% # number of syscalls executed
@@ -913,33 +914,33 @@ system.cpu0.kern.callpal::cserve                    1      0.00%      0.00% # nu
 system.cpu0.kern.callpal::wrmces                    1      0.00%      0.00% # number of callpals executed
 system.cpu0.kern.callpal::wrfen                     1      0.00%      0.00% # number of callpals executed
 system.cpu0.kern.callpal::wrvptptr                  1      0.00%      0.00% # number of callpals executed
-system.cpu0.kern.callpal::swpctx                 4176      2.17%      2.17% # number of callpals executed
+system.cpu0.kern.callpal::swpctx                 4174      2.17%      2.17% # number of callpals executed
 system.cpu0.kern.callpal::tbi                      54      0.03%      2.20% # number of callpals executed
 system.cpu0.kern.callpal::wrent                     7      0.00%      2.21% # number of callpals executed
-system.cpu0.kern.callpal::swpipl               175326     91.20%     93.41% # number of callpals executed
-system.cpu0.kern.callpal::rdps                   6783      3.53%     96.94% # number of callpals executed
+system.cpu0.kern.callpal::swpipl               175298     91.20%     93.41% # number of callpals executed
+system.cpu0.kern.callpal::rdps                   6782      3.53%     96.94% # number of callpals executed
 system.cpu0.kern.callpal::wrkgp                     1      0.00%     96.94% # number of callpals executed
 system.cpu0.kern.callpal::wrusp                     7      0.00%     96.94% # number of callpals executed
 system.cpu0.kern.callpal::rdusp                     9      0.00%     96.94% # number of callpals executed
 system.cpu0.kern.callpal::whami                     2      0.00%     96.95% # number of callpals executed
-system.cpu0.kern.callpal::rti                    5176      2.69%     99.64% # number of callpals executed
+system.cpu0.kern.callpal::rti                    5175      2.69%     99.64% # number of callpals executed
 system.cpu0.kern.callpal::callsys                 515      0.27%     99.91% # number of callpals executed
 system.cpu0.kern.callpal::imb                     181      0.09%    100.00% # number of callpals executed
-system.cpu0.kern.callpal::total                192241                       # number of callpals executed
+system.cpu0.kern.callpal::total                192209                       # number of callpals executed
 system.cpu0.kern.mode_switch::kernel             5922                       # number of protection mode switches
 system.cpu0.kern.mode_switch::user               1737                       # number of protection mode switches
-system.cpu0.kern.mode_switch::idle               2096                       # number of protection mode switches
-system.cpu0.kern.mode_good::kernel               1907                      
+system.cpu0.kern.mode_switch::idle               2093                       # number of protection mode switches
+system.cpu0.kern.mode_good::kernel               1906                      
 system.cpu0.kern.mode_good::user                 1737                      
-system.cpu0.kern.mode_good::idle                  170                      
-system.cpu0.kern.mode_switch_good::kernel     0.322020                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_good::idle                  169                      
+system.cpu0.kern.mode_switch_good::kernel     0.321851                       # fraction of useful protection mode switches
 system.cpu0.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good::idle      0.081107                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good::total     0.390979                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_ticks::kernel       29751992000      1.61%      1.61% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks::user          2580511000      0.14%      1.75% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks::idle        1810355103000     98.25%    100.00% # number of ticks spent at the given mode
-system.cpu0.kern.swap_context                    4177                       # number of times the context was actually changed
+system.cpu0.kern.mode_switch_good::idle      0.080745                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good::total     0.390894                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_ticks::kernel       29707694000      1.61%      1.61% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks::user          2577107000      0.14%      1.75% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks::idle        1809326710000     98.25%    100.00% # number of ticks spent at the given mode
+system.cpu0.kern.swap_context                    4175                       # number of times the context was actually changed
 system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
 system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
 system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
@@ -971,460 +972,459 @@ system.tsunami.ethernet.totalRxOrn                  0                       # to
 system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
 system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
 system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
-system.toL2Bus.throughput                   110521342                       # Throughput (bytes/s)
-system.toL2Bus.trans_dist::ReadReq             787621                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp            787571                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq              3734                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp             3734                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback           372342                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq              13                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq             1                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp             14                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           150591                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          133695                       # Transaction distribution
-system.toL2Bus.trans_dist::BadAddressError           35                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side       851659                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      1370714                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               2222373                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     27252672                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     55368420                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size::total           82621092                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.data_through_bus             203645448                       # Total data (bytes)
-system.toL2Bus.snoop_data_through_bus           10944                       # Total snoop data (bytes)
-system.toL2Bus.reqLayer0.occupancy         2139903500                       # Layer occupancy (ticks)
+system.toL2Bus.throughput                   112481926                       # Throughput (bytes/s)
+system.toL2Bus.trans_dist::ReadReq             825463                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp            825443                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq              3528                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp             3528                       # Transaction distribution
+system.toL2Bus.trans_dist::Writeback           385263                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateReq        17281                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq              24                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq             9                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp             33                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq           137914                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp          137914                       # Transaction distribution
+system.toL2Bus.trans_dist::BadAddressError            5                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side       903973                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      1415042                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total               2319015                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     28925888                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     57212080                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size::total           86137968                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.data_through_bus             204476224                       # Total data (bytes)
+system.toL2Bus.snoop_data_through_bus         2671872                       # Total snoop data (bytes)
+system.toL2Bus.reqLayer0.occupancy         2218881500                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy           243000                       # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy           247500                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy        1918103434                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy        2036319024                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy        2234598905                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy        2306325269                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.1                       # Layer utilization (%)
-system.iobus.throughput                       1469149                       # Throughput (bytes/s)
-system.iobus.trans_dist::ReadReq                 2954                       # Transaction distribution
-system.iobus.trans_dist::ReadResp                2954                       # Transaction distribution
-system.iobus.trans_dist::WriteReq               20630                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              20630                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio         2332                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio          136                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio           66                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio         8304                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio         2378                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf           22                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total        13238                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side        33930                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.tsunami.ide.dma::total        33930                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                   47168                       # Packet count per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio         9328                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio          544                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio           61                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio         4152                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio         1550                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf           17                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::total        15652                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      1082792                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.tsunami.ide.dma::total      1082792                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::total              1098444                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.data_through_bus                 2707184                       # Total data (bytes)
-system.iobus.reqLayer0.occupancy              2201000                       # Layer occupancy (ticks)
+system.iobus.throughput                       1470003                       # Throughput (bytes/s)
+system.iobus.trans_dist::ReadReq                 2992                       # Transaction distribution
+system.iobus.trans_dist::ReadResp                2992                       # Transaction distribution
+system.iobus.trans_dist::WriteReq               20808                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              20808                       # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio         2342                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio          140                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio           54                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio         7420                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio         2926                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf           18                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total        12900                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side        34700                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.tsunami.ide.dma::total        34700                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                   47600                       # Packet count per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio         9368                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio          560                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio           55                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio         3710                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio         2083                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf           16                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::total        15792                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      1107376                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.tsunami.ide.dma::total      1107376                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::total              1123168                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.data_through_bus                 2707176                       # Total data (bytes)
+system.iobus.reqLayer0.occupancy              2208000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy               102000                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy               105000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer22.occupancy               57000                       # Layer occupancy (ticks)
+system.iobus.reqLayer22.occupancy               48000                       # Layer occupancy (ticks)
 system.iobus.reqLayer22.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy             6188000                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy             5525000                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy             1792000                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy             2081000                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer26.occupancy               13000                       # Layer occupancy (ticks)
-system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer29.occupancy           154562743                       # Layer occupancy (ticks)
+system.iobus.reqLayer28.occupancy               11000                       # Layer occupancy (ticks)
+system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer29.occupancy           155677802                       # Layer occupancy (ticks)
 system.iobus.reqLayer29.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy             9504000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy             9372000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer1.occupancy            17636750                       # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy            17532750                       # Layer occupancy (ticks)
 system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
-system.cpu0.icache.tags.replacements           951958                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.193866                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs           42822968                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs           952469                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            44.959960                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle      10341081250                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   254.383910                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu1.inst    92.394710                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu2.inst   164.415245                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.496844                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu1.inst     0.180458                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu2.inst     0.321124                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.998426                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.replacements           964098                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.196429                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs           40281211                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs           964609                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            41.759108                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle      10190294250                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   265.809335                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu1.inst    64.640468                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu2.inst   180.746626                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.519159                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu1.inst     0.126251                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu2.inst     0.353021                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.998431                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::0           63                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::1            1                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::2          447                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses         44744661                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses        44744661                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst     32943729                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu1.inst      7613321                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu2.inst      2265918                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total       42822968                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst     32943729                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu1.inst      7613321                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu2.inst      2265918                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total        42822968                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst     32943729                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu1.inst      7613321                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu2.inst      2265918                       # number of overall hits
-system.cpu0.icache.overall_hits::total       42822968                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst       526804                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu1.inst       126948                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu2.inst       315301                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total       969053                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst       526804                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu1.inst       126948                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu2.inst       315301                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total        969053                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst       526804                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu1.inst       126948                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu2.inst       315301                       # number of overall misses
-system.cpu0.icache.overall_misses::total       969053                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu1.inst   1804971752                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::cpu2.inst   4436657422                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total   6241629174                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu1.inst   1804971752                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::cpu2.inst   4436657422                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total   6241629174                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu1.inst   1804971752                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::cpu2.inst   4436657422                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total   6241629174                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst     33470533                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu1.inst      7740269                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu2.inst      2581219                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total     43792021                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst     33470533                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu1.inst      7740269                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu2.inst      2581219                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total     43792021                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst     33470533                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu1.inst      7740269                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu2.inst      2581219                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total     43792021                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.015739                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.016401                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu2.inst     0.122152                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.022129                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.015739                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu1.inst     0.016401                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu2.inst     0.122152                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.022129                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.015739                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu1.inst     0.016401                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu2.inst     0.122152                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.022129                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14218.197624                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14071.180941                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total  6440.957485                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14218.197624                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14071.180941                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total  6440.957485                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14218.197624                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14071.180941                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total  6440.957485                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs         2807                       # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_targets          180                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs              158                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_targets              1                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs    17.765823                       # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets          180                       # average number of cycles each access was blocked
+system.cpu0.icache.tags.tag_accesses         42226967                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses        42226967                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst     30459275                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu1.inst      7343645                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu2.inst      2478291                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total       40281211                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst     30459275                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu1.inst      7343645                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu2.inst      2478291                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total        40281211                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst     30459275                       # number of overall hits
+system.cpu0.icache.overall_hits::cpu1.inst      7343645                       # number of overall hits
+system.cpu0.icache.overall_hits::cpu2.inst      2478291                       # number of overall hits
+system.cpu0.icache.overall_hits::total       40281211                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst       512792                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu1.inst       124421                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu2.inst       343745                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total       980958                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst       512792                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu1.inst       124421                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu2.inst       343745                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total        980958                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst       512792                       # number of overall misses
+system.cpu0.icache.overall_misses::cpu1.inst       124421                       # number of overall misses
+system.cpu0.icache.overall_misses::cpu2.inst       343745                       # number of overall misses
+system.cpu0.icache.overall_misses::total       980958                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu1.inst   1775017500                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::cpu2.inst   4831640896                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total   6606658396                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu1.inst   1775017500                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::cpu2.inst   4831640896                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total   6606658396                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu1.inst   1775017500                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::cpu2.inst   4831640896                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total   6606658396                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst     30972067                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu1.inst      7468066                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu2.inst      2822036                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total     41262169                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst     30972067                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu1.inst      7468066                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu2.inst      2822036                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total     41262169                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst     30972067                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu1.inst      7468066                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu2.inst      2822036                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total     41262169                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.016557                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.016660                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu2.inst     0.121807                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.023774                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.016557                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu1.inst     0.016660                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu2.inst     0.121807                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.023774                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.016557                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu1.inst     0.016660                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu2.inst     0.121807                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.023774                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14266.221136                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14055.887056                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total  6734.904446                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14266.221136                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14055.887056                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total  6734.904446                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14266.221136                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14055.887056                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total  6734.904446                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs         3704                       # number of cycles access was blocked
+system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs              169                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs    21.917160                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst        16413                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total        16413                       # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu2.inst        16413                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total        16413                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu2.inst        16413                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total        16413                       # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       126948                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst       298888                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total       425836                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu1.inst       126948                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu2.inst       298888                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total       425836                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu1.inst       126948                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu2.inst       298888                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total       425836                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst   1550155248                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst   3653520809                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total   5203676057                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst   1550155248                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst   3653520809                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total   5203676057                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst   1550155248                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst   3653520809                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total   5203676057                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.016401                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.115793                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.009724                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.016401                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst     0.115793                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.009724                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.016401                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst     0.115793                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.009724                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12210.946592                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12223.711922                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12219.906389                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12210.946592                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12223.711922                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 12219.906389                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12210.946592                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12223.711922                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 12219.906389                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst        16160                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total        16160                       # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu2.inst        16160                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total        16160                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu2.inst        16160                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total        16160                       # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       124421                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst       327585                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total       452006                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu1.inst       124421                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu2.inst       327585                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total       452006                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu1.inst       124421                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu2.inst       327585                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total       452006                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst   1525261500                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst   3997287463                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total   5522548963                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst   1525261500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst   3997287463                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total   5522548963                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst   1525261500                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst   3997287463                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total   5522548963                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.016660                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.116081                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.010954                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.016660                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst     0.116081                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.010954                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.016660                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst     0.116081                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.010954                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12258.875110                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12202.290895                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12217.866495                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12258.875110                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12202.290895                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 12217.866495                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12258.875110                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12202.290895                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 12217.866495                       # average overall mshr miss latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.dcache.tags.replacements          1392214                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          511.997811                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           13295925                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs          1392726                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs             9.546691                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.replacements          1393139                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          511.997816                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs           13262993                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs          1393651                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs             9.516725                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle         10840000                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   254.443226                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu1.data   126.415700                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu2.data   131.138886                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.496959                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu1.data     0.246906                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu2.data     0.256131                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   260.896843                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu1.data    74.443174                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu2.data   176.657800                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.509564                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu1.data     0.145397                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu2.data     0.345035                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_percent::total     0.999996                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu0.dcache.tags.age_task_id_blocks_1024::0          177                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          266                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           69                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          267                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           68                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses         63306620                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses        63306620                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data      4076279                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu1.data      1084544                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu2.data      2409625                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total        7570448                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data      3214036                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu1.data       832568                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu2.data      1295168                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total       5341772                       # number of WriteReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       117096                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu1.data        19328                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu2.data        47935                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       184359                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       126165                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu1.data        21357                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu2.data        51769                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       199291                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data      7290315                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu1.data      1917112                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu2.data      3704793                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        12912220                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data      7290315                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu1.data      1917112                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu2.data      3704793                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       12912220                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data       721601                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu1.data        97990                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu2.data       534145                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total      1353736                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data       169013                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu1.data        44495                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu2.data       596516                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total       810024                       # number of WriteReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         9634                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu1.data         2159                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu2.data         7048                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total        18841                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data            1                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu2.data            1                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total            2                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data       890614                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu1.data       142485                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu2.data      1130661                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       2163760                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data       890614                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu1.data       142485                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu2.data      1130661                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      2163760                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   2236149750                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::cpu2.data   9408423500                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total  11644573250                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   1650986010                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu2.data  18036124563                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total  19687110573                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data     28476000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data    115371499                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total    143847499                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data        13000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total        13000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu1.data   3887135760                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu2.data  27444548063                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total  31331683823                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu1.data   3887135760                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu2.data  27444548063                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total  31331683823                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data      4797880                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu1.data      1182534                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu2.data      2943770                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total      8924184                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data      3383049                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu1.data       877063                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu2.data      1891684                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total      6151796                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       126730                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data        21487                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data        54983                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       203200                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       126166                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu1.data        21357                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu2.data        51770                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       199293                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data      8180929                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu1.data      2059597                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu2.data      4835454                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     15075980                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data      8180929                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu1.data      2059597                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu2.data      4835454                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     15075980                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.150400                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.082864                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu2.data     0.181449                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.151693                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.049959                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.050732                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu2.data     0.315336                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.131673                       # miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.076020                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.100479                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data     0.128185                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.092721                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.000008                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data     0.000019                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000010                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.108865                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu1.data     0.069181                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu2.data     0.233827                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.143524                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.108865                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu1.data     0.069181                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu2.data     0.233827                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.143524                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 22820.183182                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 17613.987775                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total  8601.805116                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 37104.978312                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 30235.776682                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 24304.354652                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13189.439555                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 16369.395431                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total  7634.812324                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data        13000                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total         6500                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 27281.017370                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 24273.012037                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 14480.202898                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 27281.017370                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 24273.012037                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 14480.202898                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs       642685                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets          913                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs            30067                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets              7                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs    21.375096                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets   130.428571                       # average number of cycles each access was blocked
+system.cpu0.dcache.tags.tag_accesses         63351520                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses        63351520                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data      3995753                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu1.data      1055109                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu2.data      2515938                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total        7566800                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data      3139218                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu1.data       809021                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu2.data      1363953                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total       5312192                       # number of WriteReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       114493                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu1.data        18830                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu2.data        51280                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       184603                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data       123317                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu1.data        20808                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu2.data        55196                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       199321                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data      7134971                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu1.data      1864130                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu2.data      3879891                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total        12878992                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data      7134971                       # number of overall hits
+system.cpu0.dcache.overall_hits::cpu1.data      1864130                       # number of overall hits
+system.cpu0.dcache.overall_hits::cpu2.data      3879891                       # number of overall hits
+system.cpu0.dcache.overall_hits::total       12878992                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data       711080                       # number of ReadReq misses
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+system.cpu0.dcache.ReadReq_misses::total      1369898                       # number of ReadReq misses
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+system.cpu0.dcache.LoadLockedReq_misses::cpu1.data         2106                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu2.data         7687                       # number of LoadLockedReq misses
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+system.cpu0.dcache.StoreCondReq_misses::total            9                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data       875919                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu1.data       138462                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu2.data      1192997                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total       2207378                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data       875919                       # number of overall misses
+system.cpu0.dcache.overall_misses::cpu1.data       138462                       # number of overall misses
+system.cpu0.dcache.overall_misses::cpu2.data      1192997                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      2207378                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   2196286000                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::cpu2.data   9809622346                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total  12005908346                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   1651405510                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu2.data  20350366997                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total  22001772507                       # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data     27755500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data    126986999                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total    154742499                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data       143002                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total       143002                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu1.data   3847691510                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu2.data  30159989343                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total  34007680853                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu1.data   3847691510                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu2.data  30159989343                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total  34007680853                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data      4706833                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu1.data      1149993                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu2.data      3079872                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total      8936698                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data      3304057                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu1.data       852599                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu2.data      1993016                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total      6149672                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       123864                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data        20936                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data        58967                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       203767                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       123317                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu1.data        20808                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu2.data        55205                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       199330                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data      8010890                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu1.data      2002592                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu2.data      5072888                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     15086370                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data      8010890                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu1.data      2002592                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu2.data      5072888                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     15086370                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.151074                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.082508                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu2.data     0.183103                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.153289                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.049890                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.051112                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu2.data     0.315634                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.136183                       # miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.075656                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.100592                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data     0.130361                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.094049                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data     0.000163                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000045                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.109341                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu1.data     0.069141                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu2.data     0.235171                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.146316                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.109341                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu1.data     0.069141                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu2.data     0.235171                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.146316                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 23147.063783                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 17394.983005                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total  8764.089258                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 37895.394695                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 32350.284466                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 26271.400519                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13179.249763                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 16519.708469                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total  8074.645116                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 15889.111111                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 15889.111111                       # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 27788.790498                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 25280.859334                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 15406.369391                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 27788.790498                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 25280.859334                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 15406.369391                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs       895030                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets         1251                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs            63218                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets             11                       # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs    14.157835                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets   113.727273                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       835893                       # number of writebacks
-system.cpu0.dcache.writebacks::total           835893                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data       280644                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total       280644                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data       507552                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total       507552                       # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data         1619                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total         1619                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu2.data       788196                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total       788196                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu2.data       788196                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total       788196                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data        97990                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data       253501                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       351491                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data        44495                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data        88964                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       133459                       # number of WriteReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         2159                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data         5429                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total         7588                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data            1                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total            1                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu1.data       142485                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu2.data       342465                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total       484950                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu1.data       142485                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu2.data       342465                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total       484950                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   2032617250                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data   4252838742                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total   6285455992                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   1553735990                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data   2601199489                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total   4154935479                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     24156000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data     66182251                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     90338251                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data        11000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total        11000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   3586353240                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data   6854038231                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  10440391471                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   3586353240                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data   6854038231                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  10440391471                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    290678000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data    312039500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total    602717500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    359850500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data    427676500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total    787527000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data    650528500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data    739716000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total   1390244500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.082864                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.086114                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.039386                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.050732                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.047029                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.021694                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.100479                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data     0.098740                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.037343                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data     0.000019                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000005                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.069181                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.070824                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.032167                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.069181                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.070824                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.032167                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 20743.108991                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16776.418010                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17882.267233                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34919.339027                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 29238.787476                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31132.673548                       # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11188.513201                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12190.504881                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11905.409989                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data        11000                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total        11000                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25170.040636                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 20013.835665                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21528.799816                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25170.040636                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 20013.835665                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21528.799816                       # average overall mshr miss latency
+system.cpu0.dcache.writebacks::writebacks       835818                       # number of writebacks
+system.cpu0.dcache.writebacks::total           835818                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data       296217                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total       296217                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data       534994                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total       534994                       # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data         1640                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total         1640                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu2.data       831211                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total       831211                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu2.data       831211                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total       831211                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data        94884                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data       267717                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total       362601                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data        43578                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data        94069                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       137647                       # number of WriteReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         2106                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data         6047                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total         8153                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data            9                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total            9                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu1.data       138462                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu2.data       361786                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total       500248                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu1.data       138462                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu2.data       361786                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total       500248                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   1998980000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data   4480743134                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total   6479723134                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   1555929490                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data   2922490326                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total   4478419816                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     23542500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data     72865001                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     96407501                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data       124998                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total       124998                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   3554909490                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data   7403233460                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  10958142950                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   3554909490                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data   7403233460                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  10958142950                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    249968500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data    342709000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total    592677500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    320834500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data    419662000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total    740496500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data    570803000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data    762371000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total   1333174000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.082508                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.086925                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.040574                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.051112                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.047199                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.022383                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.100592                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data     0.102549                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.040011                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data     0.000163                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000045                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.069141                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.071318                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.033159                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.069141                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.071318                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.033159                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 21067.619409                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16736.864428                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17870.119316                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35704.472211                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 31067.517737                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 32535.542482                       # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11178.774929                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12049.776914                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11824.788544                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 13888.666667                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 13888.666667                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25674.260736                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 20463.018083                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21905.420811                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25674.260736                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 20463.018083                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21905.420811                       # average overall mshr miss latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -1439,22 +1439,22 @@ system.cpu1.dtb.fetch_hits                          0                       # IT
 system.cpu1.dtb.fetch_misses                        0                       # ITB misses
 system.cpu1.dtb.fetch_acv                           0                       # ITB acv
 system.cpu1.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu1.dtb.read_hits                     1201953                       # DTB read hits
-system.cpu1.dtb.read_misses                      1367                       # DTB read misses
+system.cpu1.dtb.read_hits                     1168812                       # DTB read hits
+system.cpu1.dtb.read_misses                      1325                       # DTB read misses
 system.cpu1.dtb.read_acv                           34                       # DTB read access violations
-system.cpu1.dtb.read_accesses                  142945                       # DTB read accesses
-system.cpu1.dtb.write_hits                     898873                       # DTB write hits
-system.cpu1.dtb.write_misses                      185                       # DTB write misses
-system.cpu1.dtb.write_acv                          23                       # DTB write access violations
-system.cpu1.dtb.write_accesses                  58321                       # DTB write accesses
-system.cpu1.dtb.data_hits                     2100826                       # DTB hits
-system.cpu1.dtb.data_misses                      1552                       # DTB misses
-system.cpu1.dtb.data_acv                           57                       # DTB access violations
-system.cpu1.dtb.data_accesses                  201266                       # DTB accesses
-system.cpu1.itb.fetch_hits                     861128                       # ITB hits
-system.cpu1.itb.fetch_misses                      693                       # ITB misses
-system.cpu1.itb.fetch_acv                          30                       # ITB acv
-system.cpu1.itb.fetch_accesses                 861821                       # ITB accesses
+system.cpu1.dtb.read_accesses                  141647                       # DTB read accesses
+system.cpu1.dtb.write_hits                     873733                       # DTB write hits
+system.cpu1.dtb.write_misses                      170                       # DTB write misses
+system.cpu1.dtb.write_acv                          22                       # DTB write access violations
+system.cpu1.dtb.write_accesses                  57095                       # DTB write accesses
+system.cpu1.dtb.data_hits                     2042545                       # DTB hits
+system.cpu1.dtb.data_misses                      1495                       # DTB misses
+system.cpu1.dtb.data_acv                           56                       # DTB access violations
+system.cpu1.dtb.data_accesses                  198742                       # DTB accesses
+system.cpu1.itb.fetch_hits                     849434                       # ITB hits
+system.cpu1.itb.fetch_misses                      664                       # ITB misses
+system.cpu1.itb.fetch_acv                          34                       # ITB acv
+system.cpu1.itb.fetch_accesses                 850098                       # ITB accesses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.read_acv                            0                       # DTB read access violations
@@ -1467,64 +1467,64 @@ system.cpu1.itb.data_hits                           0                       # DT
 system.cpu1.itb.data_misses                         0                       # DTB misses
 system.cpu1.itb.data_acv                            0                       # DTB access violations
 system.cpu1.itb.data_accesses                       0                       # DTB accesses
-system.cpu1.numCycles                       953604102                       # number of cpu cycles simulated
+system.cpu1.numCycles                       953402608                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                    7738659                       # Number of instructions committed
-system.cpu1.committedOps                      7738659                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses              7195320                       # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses                 44971                       # Number of float alu accesses
-system.cpu1.num_func_calls                     212104                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts       948894                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                     7195320                       # number of integer instructions
-system.cpu1.num_fp_insts                        44971                       # number of float instructions
-system.cpu1.num_int_register_reads           10028277                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes           5244710                       # number of times the integer registers were written
-system.cpu1.num_fp_register_reads               24303                       # number of times the floating registers were read
-system.cpu1.num_fp_register_writes              24579                       # number of times the floating registers were written
-system.cpu1.num_mem_refs                      2108049                       # number of memory refs
-system.cpu1.num_load_insts                    1206835                       # Number of load instructions
-system.cpu1.num_store_insts                    901214                       # Number of store instructions
-system.cpu1.num_idle_cycles              922268722.786044                       # Number of idle cycles
-system.cpu1.num_busy_cycles              31335379.213956                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.032860                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.967140                       # Percentage of idle cycles
-system.cpu1.Branches                          1227675                       # Number of branches fetched
-system.cpu1.op_class::No_OpClass               413043      5.34%      5.34% # Class of executed instruction
-system.cpu1.op_class::IntAlu                  5041451     65.13%     70.47% # Class of executed instruction
-system.cpu1.op_class::IntMult                    8548      0.11%     70.58% # Class of executed instruction
-system.cpu1.op_class::IntDiv                        0      0.00%     70.58% # Class of executed instruction
-system.cpu1.op_class::FloatAdd                   4999      0.06%     70.64% # Class of executed instruction
-system.cpu1.op_class::FloatCmp                      0      0.00%     70.64% # Class of executed instruction
-system.cpu1.op_class::FloatCvt                      0      0.00%     70.64% # Class of executed instruction
-system.cpu1.op_class::FloatMult                     0      0.00%     70.64% # Class of executed instruction
-system.cpu1.op_class::FloatDiv                    810      0.01%     70.65% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt                     0      0.00%     70.65% # Class of executed instruction
-system.cpu1.op_class::SimdAdd                       0      0.00%     70.65% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc                    0      0.00%     70.65% # Class of executed instruction
-system.cpu1.op_class::SimdAlu                       0      0.00%     70.65% # Class of executed instruction
-system.cpu1.op_class::SimdCmp                       0      0.00%     70.65% # Class of executed instruction
-system.cpu1.op_class::SimdCvt                       0      0.00%     70.65% # Class of executed instruction
-system.cpu1.op_class::SimdMisc                      0      0.00%     70.65% # Class of executed instruction
-system.cpu1.op_class::SimdMult                      0      0.00%     70.65% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc                   0      0.00%     70.65% # Class of executed instruction
-system.cpu1.op_class::SimdShift                     0      0.00%     70.65% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc                  0      0.00%     70.65% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt                      0      0.00%     70.65% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd                  0      0.00%     70.65% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu                  0      0.00%     70.65% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp                  0      0.00%     70.65% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt                  0      0.00%     70.65% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv                  0      0.00%     70.65% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc                 0      0.00%     70.65% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult                 0      0.00%     70.65% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     70.65% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     70.65% # Class of executed instruction
-system.cpu1.op_class::MemRead                 1235944     15.97%     86.62% # Class of executed instruction
-system.cpu1.op_class::MemWrite                 902434     11.66%     98.28% # Class of executed instruction
-system.cpu1.op_class::IprAccess                133039      1.72%    100.00% # Class of executed instruction
+system.cpu1.committedInsts                    7466514                       # Number of instructions committed
+system.cpu1.committedOps                      7466514                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses              6940405                       # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses                 43972                       # Number of float alu accesses
+system.cpu1.num_func_calls                     203873                       # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts       905018                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                     6940405                       # number of integer instructions
+system.cpu1.num_fp_insts                        43972                       # number of float instructions
+system.cpu1.num_int_register_reads            9656232                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes           5062933                       # number of times the integer registers were written
+system.cpu1.num_fp_register_reads               23750                       # number of times the floating registers were read
+system.cpu1.num_fp_register_writes              24129                       # number of times the floating registers were written
+system.cpu1.num_mem_refs                      2049510                       # number of memory refs
+system.cpu1.num_load_insts                    1173515                       # Number of load instructions
+system.cpu1.num_store_insts                    875995                       # Number of store instructions
+system.cpu1.num_idle_cycles              923975227.132686                       # Number of idle cycles
+system.cpu1.num_busy_cycles              29427380.867314                       # Number of busy cycles
+system.cpu1.not_idle_fraction                0.030866                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                    0.969134                       # Percentage of idle cycles
+system.cpu1.Branches                          1173577                       # Number of branches fetched
+system.cpu1.op_class::No_OpClass               399506      5.35%      5.35% # Class of executed instruction
+system.cpu1.op_class::IntAlu                  4845173     64.88%     70.23% # Class of executed instruction
+system.cpu1.op_class::IntMult                    8216      0.11%     70.34% # Class of executed instruction
+system.cpu1.op_class::IntDiv                        0      0.00%     70.34% # Class of executed instruction
+system.cpu1.op_class::FloatAdd                   5112      0.07%     70.41% # Class of executed instruction
+system.cpu1.op_class::FloatCmp                      0      0.00%     70.41% # Class of executed instruction
+system.cpu1.op_class::FloatCvt                      0      0.00%     70.41% # Class of executed instruction
+system.cpu1.op_class::FloatMult                     0      0.00%     70.41% # Class of executed instruction
+system.cpu1.op_class::FloatDiv                    810      0.01%     70.42% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt                     0      0.00%     70.42% # Class of executed instruction
+system.cpu1.op_class::SimdAdd                       0      0.00%     70.42% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc                    0      0.00%     70.42% # Class of executed instruction
+system.cpu1.op_class::SimdAlu                       0      0.00%     70.42% # Class of executed instruction
+system.cpu1.op_class::SimdCmp                       0      0.00%     70.42% # Class of executed instruction
+system.cpu1.op_class::SimdCvt                       0      0.00%     70.42% # Class of executed instruction
+system.cpu1.op_class::SimdMisc                      0      0.00%     70.42% # Class of executed instruction
+system.cpu1.op_class::SimdMult                      0      0.00%     70.42% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc                   0      0.00%     70.42% # Class of executed instruction
+system.cpu1.op_class::SimdShift                     0      0.00%     70.42% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc                  0      0.00%     70.42% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt                      0      0.00%     70.42% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd                  0      0.00%     70.42% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu                  0      0.00%     70.42% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp                  0      0.00%     70.42% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt                  0      0.00%     70.42% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv                  0      0.00%     70.42% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc                 0      0.00%     70.42% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult                 0      0.00%     70.42% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     70.42% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     70.42% # Class of executed instruction
+system.cpu1.op_class::MemRead                 1201694     16.09%     86.51% # Class of executed instruction
+system.cpu1.op_class::MemWrite                 877208     11.75%     98.25% # Class of executed instruction
+system.cpu1.op_class::IprAccess                130346      1.75%    100.00% # Class of executed instruction
 system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu1.op_class::total                   7740268                       # Class of executed instruction
+system.cpu1.op_class::total                   7468065                       # Class of executed instruction
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
 system.cpu1.kern.inst.hwrei                         0                       # number of hwrei instructions executed
@@ -1542,35 +1542,35 @@ system.cpu1.kern.mode_ticks::kernel                 0                       # nu
 system.cpu1.kern.mode_ticks::user                   0                       # number of ticks spent at the given mode
 system.cpu1.kern.mode_ticks::idle                   0                       # number of ticks spent at the given mode
 system.cpu1.kern.swap_context                       0                       # number of times the context was actually changed
-system.cpu2.branchPred.lookups                8997141                       # Number of BP lookups
-system.cpu2.branchPred.condPredicted          8310458                       # Number of conditional branches predicted
-system.cpu2.branchPred.condIncorrect           125233                       # Number of conditional branches incorrect
-system.cpu2.branchPred.BTBLookups             7551874                       # Number of BTB lookups
-system.cpu2.branchPred.BTBHits                6369180                       # Number of BTB hits
+system.cpu2.branchPred.lookups                9007020                       # Number of BP lookups
+system.cpu2.branchPred.condPredicted          8266685                       # Number of conditional branches predicted
+system.cpu2.branchPred.condIncorrect           125563                       # Number of conditional branches incorrect
+system.cpu2.branchPred.BTBLookups             6913379                       # Number of BTB lookups
+system.cpu2.branchPred.BTBHits                4889018                       # Number of BTB hits
 system.cpu2.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu2.branchPred.BTBHitPct            84.339066                       # BTB Hit Percentage
-system.cpu2.branchPred.usedRAS                 284910                       # Number of times the RAS was used to get a target.
-system.cpu2.branchPred.RASInCorrect             13175                       # Number of incorrect RAS predictions.
+system.cpu2.branchPred.BTBHitPct            70.718212                       # BTB Hit Percentage
+system.cpu2.branchPred.usedRAS                 301119                       # Number of times the RAS was used to get a target.
+system.cpu2.branchPred.RASInCorrect              7670                       # Number of incorrect RAS predictions.
 system.cpu2.dtb.fetch_hits                          0                       # ITB hits
 system.cpu2.dtb.fetch_misses                        0                       # ITB misses
 system.cpu2.dtb.fetch_acv                           0                       # ITB acv
 system.cpu2.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu2.dtb.read_hits                     3232647                       # DTB read hits
-system.cpu2.dtb.read_misses                     11674                       # DTB read misses
-system.cpu2.dtb.read_acv                          117                       # DTB read access violations
-system.cpu2.dtb.read_accesses                  217551                       # DTB read accesses
-system.cpu2.dtb.write_hits                    2020818                       # DTB write hits
-system.cpu2.dtb.write_misses                     2669                       # DTB write misses
-system.cpu2.dtb.write_acv                         109                       # DTB write access violations
-system.cpu2.dtb.write_accesses                  82591                       # DTB write accesses
-system.cpu2.dtb.data_hits                     5253465                       # DTB hits
-system.cpu2.dtb.data_misses                     14343                       # DTB misses
-system.cpu2.dtb.data_acv                          226                       # DTB access violations
-system.cpu2.dtb.data_accesses                  300142                       # DTB accesses
-system.cpu2.itb.fetch_hits                     371576                       # ITB hits
-system.cpu2.itb.fetch_misses                     5695                       # ITB misses
-system.cpu2.itb.fetch_acv                         235                       # ITB acv
-system.cpu2.itb.fetch_accesses                 377271                       # ITB accesses
+system.cpu2.dtb.read_hits                     3485225                       # DTB read hits
+system.cpu2.dtb.read_misses                     12620                       # DTB read misses
+system.cpu2.dtb.read_acv                          152                       # DTB read access violations
+system.cpu2.dtb.read_accesses                  227645                       # DTB read accesses
+system.cpu2.dtb.write_hits                    2140940                       # DTB write hits
+system.cpu2.dtb.write_misses                     2817                       # DTB write misses
+system.cpu2.dtb.write_acv                         139                       # DTB write access violations
+system.cpu2.dtb.write_accesses                  85106                       # DTB write accesses
+system.cpu2.dtb.data_hits                     5626165                       # DTB hits
+system.cpu2.dtb.data_misses                     15437                       # DTB misses
+system.cpu2.dtb.data_acv                          291                       # DTB access violations
+system.cpu2.dtb.data_accesses                  312751                       # DTB accesses
+system.cpu2.itb.fetch_hits                     539657                       # ITB hits
+system.cpu2.itb.fetch_misses                     5944                       # ITB misses
+system.cpu2.itb.fetch_acv                         165                       # ITB acv
+system.cpu2.itb.fetch_accesses                 545601                       # ITB accesses
 system.cpu2.itb.read_hits                           0                       # DTB read hits
 system.cpu2.itb.read_misses                         0                       # DTB read misses
 system.cpu2.itb.read_acv                            0                       # DTB read access violations
@@ -1583,305 +1583,305 @@ system.cpu2.itb.data_hits                           0                       # DT
 system.cpu2.itb.data_misses                         0                       # DTB misses
 system.cpu2.itb.data_acv                            0                       # DTB access violations
 system.cpu2.itb.data_accesses                       0                       # DTB accesses
-system.cpu2.numCycles                        31002313                       # number of cpu cycles simulated
+system.cpu2.numCycles                        29515720                       # number of cpu cycles simulated
 system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu2.fetch.icacheStallCycles           8393929                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu2.fetch.Insts                      36824229                       # Number of instructions fetch has processed
-system.cpu2.fetch.Branches                    8997141                       # Number of branches that fetch encountered
-system.cpu2.fetch.predictedBranches           6654090                       # Number of branches that fetch has predicted taken
-system.cpu2.fetch.Cycles                      8723757                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu2.fetch.SquashCycles                 635832                       # Number of cycles fetch has spent squashing
-system.cpu2.fetch.BlockedCycles               9323842                       # Number of cycles fetch has spent blocked
-system.cpu2.fetch.MiscStallCycles               10747                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu2.fetch.PendingDrainCycles             1941                       # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu2.fetch.PendingTrapStallCycles        64126                       # Number of stall cycles due to pending traps
-system.cpu2.fetch.PendingQuiesceStallCycles        88179                       # Number of stall cycles due to pending quiesce instructions
-system.cpu2.fetch.IcacheWaitRetryStallCycles          311                       # Number of stall cycles due to full MSHR
-system.cpu2.fetch.CacheLines                  2581223                       # Number of cache lines fetched
-system.cpu2.fetch.IcacheSquashes                87099                       # Number of outstanding Icache misses that were squashed
-system.cpu2.fetch.rateDist::samples          27026118                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::mean             1.362542                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::stdev            2.315525                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.icacheStallCycles           9404916                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu2.fetch.Insts                      35474807                       # Number of instructions fetch has processed
+system.cpu2.fetch.Branches                    9007020                       # Number of branches that fetch encountered
+system.cpu2.fetch.predictedBranches           5190137                       # Number of branches that fetch has predicted taken
+system.cpu2.fetch.Cycles                     18003717                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu2.fetch.SquashCycles                 410566                       # Number of cycles fetch has spent squashing
+system.cpu2.fetch.TlbCycles                       517                       # Number of cycles fetch has spent waiting for tlb
+system.cpu2.fetch.MiscStallCycles                9775                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu2.fetch.PendingDrainCycles             1999                       # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu2.fetch.PendingTrapStallCycles       235781                       # Number of stall cycles due to pending traps
+system.cpu2.fetch.PendingQuiesceStallCycles        98995                       # Number of stall cycles due to pending quiesce instructions
+system.cpu2.fetch.IcacheWaitRetryStallCycles          442                       # Number of stall cycles due to full MSHR
+system.cpu2.fetch.CacheLines                  2822037                       # Number of cache lines fetched
+system.cpu2.fetch.IcacheSquashes                92550                       # Number of outstanding Icache misses that were squashed
+system.cpu2.fetch.rateDist::samples          27961187                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::mean             1.268716                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::stdev            2.388099                       # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::0                18302361     67.72%     67.72% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::1                  270640      1.00%     68.72% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::2                  435105      1.61%     70.33% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::3                 4809867     17.80%     88.13% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::4                  769933      2.85%     90.98% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::5                  167503      0.62%     91.60% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::6                  192346      0.71%     92.31% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::7                  444449      1.64%     93.95% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::8                 1633914      6.05%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::0                20241670     72.39%     72.39% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::1                  312691      1.12%     73.51% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::2                  474251      1.70%     75.21% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::3                 3278987     11.73%     86.93% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::4                  837934      3.00%     89.93% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::5                  194435      0.70%     90.63% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::6                  239683      0.86%     91.48% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::7                  437644      1.57%     93.05% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::8                 1943892      6.95%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::total            27026118                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.branchRate                 0.290209                       # Number of branch fetches per cycle
-system.cpu2.fetch.rate                       1.187790                       # Number of inst fetches per cycle
-system.cpu2.decode.IdleCycles                 8441173                       # Number of cycles decode is idle
-system.cpu2.decode.BlockedCycles              9512814                       # Number of cycles decode is blocked
-system.cpu2.decode.RunCycles                  8253964                       # Number of cycles decode is running
-system.cpu2.decode.UnblockCycles               165145                       # Number of cycles decode is unblocking
-system.cpu2.decode.SquashCycles                407122                       # Number of cycles decode is squashing
-system.cpu2.decode.BranchResolved              167309                       # Number of times decode resolved a branch
-system.cpu2.decode.BranchMispred                12818                       # Number of times decode detected a branch misprediction
-system.cpu2.decode.DecodedInsts              36409694                       # Number of instructions handled by decode
-system.cpu2.decode.SquashedInsts                40311                       # Number of squashed instructions handled by decode
-system.cpu2.rename.SquashCycles                407122                       # Number of cycles rename is squashing
-system.cpu2.rename.IdleCycles                 8734574                       # Number of cycles rename is idle
-system.cpu2.rename.BlockCycles                2556870                       # Number of cycles rename is blocking
-system.cpu2.rename.serializeStallCycles       5774789                       # count of cycles rename stalled for serializing inst
-system.cpu2.rename.RunCycles                  8067686                       # Number of cycles rename is running
-system.cpu2.rename.UnblockCycles              1239186                       # Number of cycles rename is unblocking
-system.cpu2.rename.RenamedInsts              35224318                       # Number of instructions processed by rename
-system.cpu2.rename.ROBFullEvents                 3572                       # Number of times rename has blocked due to ROB full
-system.cpu2.rename.IQFullEvents                388506                       # Number of times rename has blocked due to IQ full
-system.cpu2.rename.LQFullEvents                 20310                       # Number of times rename has blocked due to LQ full
-system.cpu2.rename.SQFullEvents                316059                       # Number of times rename has blocked due to SQ full
-system.cpu2.rename.RenamedOperands           23620864                       # Number of destination operands rename has renamed
-system.cpu2.rename.RenameLookups             44017646                       # Number of register rename lookups that rename has made
-system.cpu2.rename.int_rename_lookups        43961139                       # Number of integer rename lookups
-system.cpu2.rename.fp_rename_lookups            52746                       # Number of floating rename lookups
-system.cpu2.rename.CommittedMaps             21667069                       # Number of HB maps that are committed
-system.cpu2.rename.UndoneMaps                 1953795                       # Number of HB maps that are undone due to squashing
-system.cpu2.rename.serializingInsts            502665                       # count of serializing insts renamed
-system.cpu2.rename.tempSerializingInsts         59694                       # count of temporary serializing insts renamed
-system.cpu2.rename.skidInsts                  2961257                       # count of insts added to the skid buffer
-system.cpu2.memDep0.insertedLoads             3405802                       # Number of loads inserted to the mem dependence unit.
-system.cpu2.memDep0.insertedStores            2124807                       # Number of stores inserted to the mem dependence unit.
-system.cpu2.memDep0.conflictingLoads           397929                       # Number of conflicting loads.
-system.cpu2.memDep0.conflictingStores          274147                       # Number of conflicting stores.
-system.cpu2.iq.iqInstsAdded                  32669106                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu2.iq.iqNonSpecInstsAdded             622861                       # Number of non-speculative instructions added to the IQ
-system.cpu2.iq.iqInstsIssued                 32140552                       # Number of instructions issued
-system.cpu2.iq.iqSquashedInstsIssued            36002                       # Number of squashed instructions issued
-system.cpu2.iq.iqSquashedInstsExamined        2321360                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu2.iq.iqSquashedOperandsExamined      1217953                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu2.iq.iqSquashedNonSpecRemoved        439629                       # Number of squashed non-spec instructions that were removed
-system.cpu2.iq.issued_per_cycle::samples     27026118                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::mean        1.189240                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::stdev       1.607686                       # Number of insts issued each cycle
+system.cpu2.fetch.rateDist::total            27961187                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.branchRate                 0.305160                       # Number of branch fetches per cycle
+system.cpu2.fetch.rate                       1.201895                       # Number of inst fetches per cycle
+system.cpu2.decode.IdleCycles                 7704419                       # Number of cycles decode is idle
+system.cpu2.decode.BlockedCycles             13193149                       # Number of cycles decode is blocked
+system.cpu2.decode.RunCycles                  6090024                       # Number of cycles decode is running
+system.cpu2.decode.UnblockCycles               535254                       # Number of cycles decode is unblocking
+system.cpu2.decode.SquashCycles                192290                       # Number of cycles decode is squashing
+system.cpu2.decode.BranchResolved              176132                       # Number of times decode resolved a branch
+system.cpu2.decode.BranchMispred                13346                       # Number of times decode detected a branch misprediction
+system.cpu2.decode.DecodedInsts              32094888                       # Number of instructions handled by decode
+system.cpu2.decode.SquashedInsts                42715                       # Number of squashed instructions handled by decode
+system.cpu2.rename.SquashCycles                192290                       # Number of cycles rename is squashing
+system.cpu2.rename.IdleCycles                 7987526                       # Number of cycles rename is idle
+system.cpu2.rename.BlockCycles                4830275                       # Number of cycles rename is blocking
+system.cpu2.rename.serializeStallCycles       6354829                       # count of cycles rename stalled for serializing inst
+system.cpu2.rename.RunCycles                  6312082                       # Number of cycles rename is running
+system.cpu2.rename.UnblockCycles              2038145                       # Number of cycles rename is unblocking
+system.cpu2.rename.RenamedInsts              31271508                       # Number of instructions processed by rename
+system.cpu2.rename.ROBFullEvents                68877                       # Number of times rename has blocked due to ROB full
+system.cpu2.rename.IQFullEvents                405466                       # Number of times rename has blocked due to IQ full
+system.cpu2.rename.LQFullEvents                 55957                       # Number of times rename has blocked due to LQ full
+system.cpu2.rename.SQFullEvents                963204                       # Number of times rename has blocked due to SQ full
+system.cpu2.rename.RenamedOperands           20931686                       # Number of destination operands rename has renamed
+system.cpu2.rename.RenameLookups             38638449                       # Number of register rename lookups that rename has made
+system.cpu2.rename.int_rename_lookups        38578281                       # Number of integer rename lookups
+system.cpu2.rename.fp_rename_lookups            56251                       # Number of floating rename lookups
+system.cpu2.rename.CommittedMaps             19026086                       # Number of HB maps that are committed
+system.cpu2.rename.UndoneMaps                 1905600                       # Number of HB maps that are undone due to squashing
+system.cpu2.rename.serializingInsts            533120                       # count of serializing insts renamed
+system.cpu2.rename.tempSerializingInsts         63723                       # count of temporary serializing insts renamed
+system.cpu2.rename.skidInsts                  3942739                       # count of insts added to the skid buffer
+system.cpu2.memDep0.insertedLoads             3510198                       # Number of loads inserted to the mem dependence unit.
+system.cpu2.memDep0.insertedStores            2234995                       # Number of stores inserted to the mem dependence unit.
+system.cpu2.memDep0.conflictingLoads           462280                       # Number of conflicting loads.
+system.cpu2.memDep0.conflictingStores          329256                       # Number of conflicting stores.
+system.cpu2.iq.iqInstsAdded                  28739879                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu2.iq.iqNonSpecInstsAdded             680947                       # Number of non-speculative instructions added to the IQ
+system.cpu2.iq.iqInstsIssued                 28391596                       # Number of instructions issued
+system.cpu2.iq.iqSquashedInstsIssued            17529                       # Number of squashed instructions issued
+system.cpu2.iq.iqSquashedInstsExamined        2438506                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu2.iq.iqSquashedOperandsExamined      1151582                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu2.iq.iqSquashedNonSpecRemoved        487021                       # Number of squashed non-spec instructions that were removed
+system.cpu2.iq.issued_per_cycle::samples     27961187                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::mean        1.015393                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::stdev       1.594251                       # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::0           15119064     55.94%     55.94% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::1            2962463     10.96%     66.90% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::2            1396485      5.17%     72.07% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::3            5591038     20.69%     92.76% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::4             885243      3.28%     96.03% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::5             550698      2.04%     98.07% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::6             348435      1.29%     99.36% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::7             154603      0.57%     99.93% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::8              18089      0.07%    100.00% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::0           17574861     62.85%     62.85% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::1            2788082      9.97%     72.83% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::2            1379347      4.93%     77.76% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::3            4037262     14.44%     92.20% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::4            1018579      3.64%     95.84% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::5             572705      2.05%     97.89% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::6             385941      1.38%     99.27% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::7             155733      0.56%     99.83% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::8              48677      0.17%    100.00% # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::total       27026118                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::total       27961187                       # Number of insts issued each cycle
 system.cpu2.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntAlu                  38019     14.73%     14.73% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntMult                     0      0.00%     14.73% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntDiv                      0      0.00%     14.73% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatAdd                    0      0.00%     14.73% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCmp                    0      0.00%     14.73% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCvt                    0      0.00%     14.73% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatMult                   0      0.00%     14.73% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatDiv                    0      0.00%     14.73% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%     14.73% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAdd                     0      0.00%     14.73% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%     14.73% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAlu                     0      0.00%     14.73% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCmp                     0      0.00%     14.73% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCvt                     0      0.00%     14.73% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMisc                    0      0.00%     14.73% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMult                    0      0.00%     14.73% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%     14.73% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShift                   0      0.00%     14.73% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%     14.73% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%     14.73% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%     14.73% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%     14.73% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%     14.73% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%     14.73% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%     14.73% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%     14.73% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%     14.73% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%     14.73% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%     14.73% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemRead                117677     45.59%     60.31% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemWrite               102444     39.69%    100.00% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntAlu                  82533     21.35%     21.35% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntMult                     0      0.00%     21.35% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntDiv                      0      0.00%     21.35% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatAdd                    0      0.00%     21.35% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCmp                    0      0.00%     21.35% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCvt                    0      0.00%     21.35% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatMult                   0      0.00%     21.35% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatDiv                    0      0.00%     21.35% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%     21.35% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAdd                     0      0.00%     21.35% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%     21.35% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAlu                     0      0.00%     21.35% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCmp                     0      0.00%     21.35% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCvt                     0      0.00%     21.35% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMisc                    0      0.00%     21.35% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMult                    0      0.00%     21.35% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%     21.35% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShift                   0      0.00%     21.35% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%     21.35% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%     21.35% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%     21.35% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%     21.35% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%     21.35% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%     21.35% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%     21.35% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%     21.35% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%     21.35% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%     21.35% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%     21.35% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemRead                178965     46.29%     67.64% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemWrite               125088     32.36%    100.00% # attempts to use FU when none available
 system.cpu2.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu2.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu2.iq.FU_type_0::No_OpClass             2440      0.01%      0.01% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntAlu             26413495     82.18%     82.19% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntMult               20160      0.06%     82.25% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntDiv                    0      0.00%     82.25% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatAdd               8429      0.03%     82.28% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     82.28% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCvt                  0      0.00%     82.28% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     82.28% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatDiv               1220      0.00%     82.28% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     82.28% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     82.28% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     82.28% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     82.28% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     82.28% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     82.28% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMisc                  0      0.00%     82.28% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     82.28% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     82.28% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     82.28% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     82.28% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     82.28% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     82.28% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     82.28% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     82.28% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     82.28% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     82.28% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMisc             0      0.00%     82.28% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     82.28% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     82.28% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     82.28% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemRead             3362943     10.46%     92.74% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemWrite            2042777      6.36%     99.10% # Type of FU issued
-system.cpu2.iq.FU_type_0::IprAccess            289088      0.90%    100.00% # Type of FU issued
+system.cpu2.iq.FU_type_0::No_OpClass             2456      0.01%      0.01% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntAlu             22261960     78.41%     78.42% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntMult               21111      0.07%     78.49% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntDiv                    0      0.00%     78.49% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatAdd              20516      0.07%     78.57% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     78.57% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCvt                  0      0.00%     78.57% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     78.57% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatDiv               1228      0.00%     78.57% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     78.57% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     78.57% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     78.57% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     78.57% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     78.57% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     78.57% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMisc                  0      0.00%     78.57% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     78.57% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     78.57% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     78.57% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     78.57% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     78.57% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     78.57% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     78.57% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     78.57% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     78.57% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     78.57% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMisc             0      0.00%     78.57% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     78.57% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     78.57% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     78.57% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemRead             3614417     12.73%     91.30% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemWrite            2165470      7.63%     98.93% # Type of FU issued
+system.cpu2.iq.FU_type_0::IprAccess            304438      1.07%    100.00% # Type of FU issued
 system.cpu2.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::total              32140552                       # Type of FU issued
-system.cpu2.iq.rate                          1.036715                       # Inst issue rate
-system.cpu2.iq.fu_busy_cnt                     258140                       # FU busy when requested
-system.cpu2.iq.fu_busy_rate                  0.008032                       # FU busy rate (busy events/executed inst)
-system.cpu2.iq.int_inst_queue_reads          91366801                       # Number of integer instruction queue reads
-system.cpu2.iq.int_inst_queue_writes         35502508                       # Number of integer instruction queue writes
-system.cpu2.iq.int_inst_queue_wakeup_accesses     31706710                       # Number of integer instruction queue wakeup accesses
-system.cpu2.iq.fp_inst_queue_reads             234563                       # Number of floating instruction queue reads
-system.cpu2.iq.fp_inst_queue_writes            114868                       # Number of floating instruction queue writes
-system.cpu2.iq.fp_inst_queue_wakeup_accesses       110893                       # Number of floating instruction queue wakeup accesses
-system.cpu2.iq.int_alu_accesses              32274032                       # Number of integer alu accesses
-system.cpu2.iq.fp_alu_accesses                 122220                       # Number of floating point alu accesses
-system.cpu2.iew.lsq.thread0.forwLoads          191624                       # Number of loads that had data forwarded from stores
+system.cpu2.iq.FU_type_0::total              28391596                       # Type of FU issued
+system.cpu2.iq.rate                          0.961914                       # Inst issue rate
+system.cpu2.iq.fu_busy_cnt                     386586                       # FU busy when requested
+system.cpu2.iq.fu_busy_rate                  0.013616                       # FU busy rate (busy events/executed inst)
+system.cpu2.iq.int_inst_queue_reads          84894790                       # Number of integer instruction queue reads
+system.cpu2.iq.int_inst_queue_writes         31745632                       # Number of integer instruction queue writes
+system.cpu2.iq.int_inst_queue_wakeup_accesses     27810644                       # Number of integer instruction queue wakeup accesses
+system.cpu2.iq.fp_inst_queue_reads             253704                       # Number of floating instruction queue reads
+system.cpu2.iq.fp_inst_queue_writes            119619                       # Number of floating instruction queue writes
+system.cpu2.iq.fp_inst_queue_wakeup_accesses       117118                       # Number of floating instruction queue wakeup accesses
+system.cpu2.iq.int_alu_accesses              28639647                       # Number of integer alu accesses
+system.cpu2.iq.fp_alu_accesses                 136079                       # Number of floating point alu accesses
+system.cpu2.iew.lsq.thread0.forwLoads          206810                       # Number of loads that had data forwarded from stores
 system.cpu2.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu2.iew.lsq.thread0.squashedLoads       457264                       # Number of loads squashed
-system.cpu2.iew.lsq.thread0.ignoredResponses         1199                       # Number of memory responses ignored because the instruction is squashed
-system.cpu2.iew.lsq.thread0.memOrderViolation         4154                       # Number of memory ordering violations
-system.cpu2.iew.lsq.thread0.squashedStores       177923                       # Number of stores squashed
+system.cpu2.iew.lsq.thread0.squashedLoads       438537                       # Number of loads squashed
+system.cpu2.iew.lsq.thread0.ignoredResponses         1486                       # Number of memory responses ignored because the instruction is squashed
+system.cpu2.iew.lsq.thread0.memOrderViolation         6057                       # Number of memory ordering violations
+system.cpu2.iew.lsq.thread0.squashedStores       183313                       # Number of stores squashed
 system.cpu2.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu2.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu2.iew.lsq.thread0.rescheduledLoads         4195                       # Number of loads that were rescheduled
-system.cpu2.iew.lsq.thread0.cacheBlocked        54966                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu2.iew.lsq.thread0.rescheduledLoads         5003                       # Number of loads that were rescheduled
+system.cpu2.iew.lsq.thread0.cacheBlocked       177760                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu2.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu2.iew.iewSquashCycles                407122                       # Number of cycles IEW is squashing
-system.cpu2.iew.iewBlockCycles                1875775                       # Number of cycles IEW is blocking
-system.cpu2.iew.iewUnblockCycles               219548                       # Number of cycles IEW is unblocking
-system.cpu2.iew.iewDispatchedInsts           34577439                       # Number of instructions dispatched to IQ
-system.cpu2.iew.iewDispSquashedInsts           209711                       # Number of squashed instructions skipped by dispatch
-system.cpu2.iew.iewDispLoadInsts              3405802                       # Number of dispatched load instructions
-system.cpu2.iew.iewDispStoreInsts             2124807                       # Number of dispatched store instructions
-system.cpu2.iew.iewDispNonSpecInsts            553318                       # Number of dispatched non-speculative instructions
-system.cpu2.iew.iewIQFullEvents                 48768                       # Number of times the IQ has become full, causing a stall
-system.cpu2.iew.iewLSQFullEvents               120434                       # Number of times the LSQ has become full, causing a stall
-system.cpu2.iew.memOrderViolationEvents          4154                       # Number of memory order violations
-system.cpu2.iew.predictedTakenIncorrect         65270                       # Number of branches that were predicted taken incorrectly
-system.cpu2.iew.predictedNotTakenIncorrect       127814                       # Number of branches that were predicted not taken incorrectly
-system.cpu2.iew.branchMispredicts              193084                       # Number of branch mispredicts detected at execute
-system.cpu2.iew.iewExecutedInsts             31975437                       # Number of executed instructions
-system.cpu2.iew.iewExecLoadInsts              3252613                       # Number of load instructions executed
-system.cpu2.iew.iewExecSquashedInsts           165115                       # Number of squashed instructions skipped in execute
+system.cpu2.iew.iewSquashCycles                192290                       # Number of cycles IEW is squashing
+system.cpu2.iew.iewBlockCycles                4010862                       # Number of cycles IEW is blocking
+system.cpu2.iew.iewUnblockCycles               349296                       # Number of cycles IEW is unblocking
+system.cpu2.iew.iewDispatchedInsts           30806306                       # Number of instructions dispatched to IQ
+system.cpu2.iew.iewDispSquashedInsts            54542                       # Number of squashed instructions skipped by dispatch
+system.cpu2.iew.iewDispLoadInsts              3510198                       # Number of dispatched load instructions
+system.cpu2.iew.iewDispStoreInsts             2234995                       # Number of dispatched store instructions
+system.cpu2.iew.iewDispNonSpecInsts            606167                       # Number of dispatched non-speculative instructions
+system.cpu2.iew.iewIQFullEvents                 15566                       # Number of times the IQ has become full, causing a stall
+system.cpu2.iew.iewLSQFullEvents               285460                       # Number of times the LSQ has become full, causing a stall
+system.cpu2.iew.memOrderViolationEvents          6057                       # Number of memory order violations
+system.cpu2.iew.predictedTakenIncorrect         62858                       # Number of branches that were predicted taken incorrectly
+system.cpu2.iew.predictedNotTakenIncorrect       135105                       # Number of branches that were predicted not taken incorrectly
+system.cpu2.iew.branchMispredicts              197963                       # Number of branch mispredicts detected at execute
+system.cpu2.iew.iewExecutedInsts             28193561                       # Number of executed instructions
+system.cpu2.iew.iewExecLoadInsts              3506622                       # Number of load instructions executed
+system.cpu2.iew.iewExecSquashedInsts           198035                       # Number of squashed instructions skipped in execute
 system.cpu2.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu2.iew.exec_nop                      1285472                       # number of nop insts executed
-system.cpu2.iew.exec_refs                     5280547                       # number of memory reference insts executed
-system.cpu2.iew.exec_branches                 7393667                       # Number of branches executed
-system.cpu2.iew.exec_stores                   2027934                       # Number of stores executed
-system.cpu2.iew.exec_rate                    1.031389                       # Inst execution rate
-system.cpu2.iew.wb_sent                      31851458                       # cumulative count of insts sent to commit
-system.cpu2.iew.wb_count                     31817603                       # cumulative count of insts written-back
-system.cpu2.iew.wb_producers                 18729651                       # num instructions producing a value
-system.cpu2.iew.wb_consumers                 22311181                       # num instructions consuming a value
+system.cpu2.iew.exec_nop                      1385480                       # number of nop insts executed
+system.cpu2.iew.exec_refs                     5655108                       # number of memory reference insts executed
+system.cpu2.iew.exec_branches                 5954900                       # Number of branches executed
+system.cpu2.iew.exec_stores                   2148486                       # Number of stores executed
+system.cpu2.iew.exec_rate                    0.955205                       # Inst execution rate
+system.cpu2.iew.wb_sent                      27969918                       # cumulative count of insts sent to commit
+system.cpu2.iew.wb_count                     27927762                       # cumulative count of insts written-back
+system.cpu2.iew.wb_producers                 15888662                       # num instructions producing a value
+system.cpu2.iew.wb_consumers                 19538696                       # num instructions consuming a value
 system.cpu2.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu2.iew.wb_rate                      1.026298                       # insts written-back per cycle
-system.cpu2.iew.wb_fanout                    0.839474                       # average fanout of values written-back
+system.cpu2.iew.wb_rate                      0.946200                       # insts written-back per cycle
+system.cpu2.iew.wb_fanout                    0.813189                       # average fanout of values written-back
 system.cpu2.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu2.commit.commitSquashedInsts        2502130                       # The number of squashed insts skipped by commit
-system.cpu2.commit.commitNonSpecStalls         183232                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu2.commit.branchMispredicts           177866                       # The number of times a branch was mispredicted
-system.cpu2.commit.committed_per_cycle::samples     26618996                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::mean     1.203206                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::stdev     1.875540                       # Number of insts commited each cycle
+system.cpu2.commit.commitSquashedInsts        2672008                       # The number of squashed insts skipped by commit
+system.cpu2.commit.commitNonSpecStalls         193926                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu2.commit.branchMispredicts           180997                       # The number of times a branch was mispredicted
+system.cpu2.commit.committed_per_cycle::samples     27494343                       # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::mean     1.021637                       # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::stdev     1.858517                       # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::0     16042703     60.27%     60.27% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::1      2256116      8.48%     68.74% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::2      1167560      4.39%     73.13% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::3      5327635     20.01%     93.14% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::4       518833      1.95%     95.09% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::5       187130      0.70%     95.80% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::6       168998      0.63%     96.43% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::7       171142      0.64%     97.07% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::8       778879      2.93%    100.00% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::0     18377188     66.84%     66.84% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::1      2251123      8.19%     75.03% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::2      1180007      4.29%     79.32% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::3      3743706     13.62%     92.94% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::4       543464      1.98%     94.91% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::5       201872      0.73%     95.65% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::6       166281      0.60%     96.25% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::7       179533      0.65%     96.90% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::8       851169      3.10%    100.00% # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::total     26618996                       # Number of insts commited each cycle
-system.cpu2.commit.committedInsts            32028137                       # Number of instructions committed
-system.cpu2.commit.committedOps              32028137                       # Number of ops (including micro ops) committed
+system.cpu2.commit.committed_per_cycle::total     27494343                       # Number of insts commited each cycle
+system.cpu2.commit.committedInsts            28089240                       # Number of instructions committed
+system.cpu2.commit.committedOps              28089240                       # Number of ops (including micro ops) committed
 system.cpu2.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu2.commit.refs                       4895422                       # Number of memory references committed
-system.cpu2.commit.loads                      2948538                       # Number of loads committed
-system.cpu2.commit.membars                      64184                       # Number of memory barriers committed
-system.cpu2.commit.branches                   7237241                       # Number of branches committed
-system.cpu2.commit.fp_insts                    109664                       # Number of committed floating point instructions.
-system.cpu2.commit.int_insts                 30577389                       # Number of committed integer instructions.
-system.cpu2.commit.function_calls              229570                       # Number of function calls committed.
-system.cpu2.commit.op_class_0::No_OpClass      1171866      3.66%      3.66% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntAlu        25576585     79.86%     83.52% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntMult          19753      0.06%     83.58% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntDiv               0      0.00%     83.58% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatAdd          8429      0.03%     83.60% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatCmp             0      0.00%     83.60% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatCvt             0      0.00%     83.60% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatMult            0      0.00%     83.60% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatDiv          1220      0.00%     83.61% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatSqrt            0      0.00%     83.61% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAdd              0      0.00%     83.61% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAddAcc            0      0.00%     83.61% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAlu              0      0.00%     83.61% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdCmp              0      0.00%     83.61% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdCvt              0      0.00%     83.61% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMisc             0      0.00%     83.61% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMult             0      0.00%     83.61% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMultAcc            0      0.00%     83.61% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdShift            0      0.00%     83.61% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdShiftAcc            0      0.00%     83.61% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdSqrt             0      0.00%     83.61% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatAdd            0      0.00%     83.61% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatAlu            0      0.00%     83.61% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatCmp            0      0.00%     83.61% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatCvt            0      0.00%     83.61% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatDiv            0      0.00%     83.61% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMisc            0      0.00%     83.61% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMult            0      0.00%     83.61% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMultAcc            0      0.00%     83.61% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatSqrt            0      0.00%     83.61% # Class of committed instruction
-system.cpu2.commit.op_class_0::MemRead        3012722      9.41%     93.01% # Class of committed instruction
-system.cpu2.commit.op_class_0::MemWrite       1948474      6.08%     99.10% # Class of committed instruction
-system.cpu2.commit.op_class_0::IprAccess       289088      0.90%    100.00% # Class of committed instruction
+system.cpu2.commit.refs                       5123343                       # Number of memory references committed
+system.cpu2.commit.loads                      3071661                       # Number of loads committed
+system.cpu2.commit.membars                      68272                       # Number of memory barriers committed
+system.cpu2.commit.branches                   5784239                       # Number of branches committed
+system.cpu2.commit.fp_insts                    115390                       # Number of committed floating point instructions.
+system.cpu2.commit.int_insts                 26574373                       # Number of committed integer instructions.
+system.cpu2.commit.function_calls              240380                       # Number of function calls committed.
+system.cpu2.commit.op_class_0::No_OpClass      1220895      4.35%      4.35% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntAlu        21328709     75.93%     80.28% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntMult          20651      0.07%     80.35% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntDiv               0      0.00%     80.35% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatAdd         20067      0.07%     80.42% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatCmp             0      0.00%     80.42% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatCvt             0      0.00%     80.42% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatMult            0      0.00%     80.42% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatDiv          1228      0.00%     80.43% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatSqrt            0      0.00%     80.43% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAdd              0      0.00%     80.43% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAddAcc            0      0.00%     80.43% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAlu              0      0.00%     80.43% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdCmp              0      0.00%     80.43% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdCvt              0      0.00%     80.43% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMisc             0      0.00%     80.43% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMult             0      0.00%     80.43% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMultAcc            0      0.00%     80.43% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdShift            0      0.00%     80.43% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdShiftAcc            0      0.00%     80.43% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdSqrt             0      0.00%     80.43% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatAdd            0      0.00%     80.43% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatAlu            0      0.00%     80.43% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatCmp            0      0.00%     80.43% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatCvt            0      0.00%     80.43% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatDiv            0      0.00%     80.43% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMisc            0      0.00%     80.43% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMult            0      0.00%     80.43% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMultAcc            0      0.00%     80.43% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatSqrt            0      0.00%     80.43% # Class of committed instruction
+system.cpu2.commit.op_class_0::MemRead        3139933     11.18%     91.61% # Class of committed instruction
+system.cpu2.commit.op_class_0::MemWrite       2053319      7.31%     98.92% # Class of committed instruction
+system.cpu2.commit.op_class_0::IprAccess       304438      1.08%    100.00% # Class of committed instruction
 system.cpu2.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu2.commit.op_class_0::total         32028137                       # Class of committed instruction
-system.cpu2.commit.bw_lim_events               778879                       # number cycles where commit BW limit reached
+system.cpu2.commit.op_class_0::total         28089240                       # Class of committed instruction
+system.cpu2.commit.bw_lim_events               851169                       # number cycles where commit BW limit reached
 system.cpu2.commit.bw_limited                       0                       # number of insts not committed due to BW limits
-system.cpu2.rob.rob_reads                    60296509                       # The number of ROB reads
-system.cpu2.rob.rob_writes                   69467378                       # The number of ROB writes
-system.cpu2.timesIdled                         246541                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu2.idleCycles                        3976195                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu2.quiesceCycles                  1746763449                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu2.committedInsts                   30858711                       # Number of Instructions Simulated
-system.cpu2.committedOps                     30858711                       # Number of Ops (including micro ops) Simulated
-system.cpu2.cpi                              1.004654                       # CPI: Cycles Per Instruction
-system.cpu2.cpi_total                        1.004654                       # CPI: Total CPI of All Threads
-system.cpu2.ipc                              0.995368                       # IPC: Instructions Per Cycle
-system.cpu2.ipc_total                        0.995368                       # IPC: Total IPC of All Threads
-system.cpu2.int_regfile_reads                42053824                       # number of integer regfile reads
-system.cpu2.int_regfile_writes               22390255                       # number of integer regfile writes
-system.cpu2.fp_regfile_reads                    67731                       # number of floating regfile reads
-system.cpu2.fp_regfile_writes                   68085                       # number of floating regfile writes
-system.cpu2.misc_regfile_reads                5172203                       # number of misc regfile reads
-system.cpu2.misc_regfile_writes                258202                       # number of misc regfile writes
+system.cpu2.rob.rob_reads                    57327258                       # The number of ROB reads
+system.cpu2.rob.rob_writes                   61989353                       # The number of ROB writes
+system.cpu2.timesIdled                         175568                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu2.idleCycles                        1554533                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu2.quiesceCycles                  1746289037                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu2.committedInsts                   26870801                       # Number of Instructions Simulated
+system.cpu2.committedOps                     26870801                       # Number of Ops (including micro ops) Simulated
+system.cpu2.cpi                              1.098431                       # CPI: Cycles Per Instruction
+system.cpu2.cpi_total                        1.098431                       # CPI: Total CPI of All Threads
+system.cpu2.ipc                              0.910389                       # IPC: Instructions Per Cycle
+system.cpu2.ipc_total                        0.910389                       # IPC: Total IPC of All Threads
+system.cpu2.int_regfile_reads                36957190                       # number of integer regfile reads
+system.cpu2.int_regfile_writes               19824047                       # number of integer regfile writes
+system.cpu2.fp_regfile_reads                    70953                       # number of floating regfile reads
+system.cpu2.fp_regfile_writes                   70972                       # number of floating regfile writes
+system.cpu2.misc_regfile_reads                3637810                       # number of misc regfile reads
+system.cpu2.misc_regfile_writes                273227                       # number of misc regfile writes
 system.cpu2.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu2.kern.inst.quiesce                       0                       # number of quiesce instructions executed
 system.cpu2.kern.inst.hwrei                         0                       # number of hwrei instructions executed
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt
index d5447172f..4b75ac871 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt
@@ -1,143 +1,143 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  1.146775                       # Number of seconds simulated
-sim_ticks                                1146774863500                       # Number of ticks simulated
-final_tick                               1146774863500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  1.145505                       # Number of seconds simulated
+sim_ticks                                1145504982000                       # Number of ticks simulated
+final_tick                               1145504982000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  52366                       # Simulator instruction rate (inst/s)
-host_op_rate                                    67406                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              970268509                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 448492                       # Number of bytes of host memory used
-host_seconds                                  1181.92                       # Real time elapsed on the host
-sim_insts                                    61892059                       # Number of instructions simulated
-sim_ops                                      79667620                       # Number of ops (including micro ops) simulated
+host_inst_rate                                  75061                       # Simulator instruction rate (inst/s)
+host_op_rate                                    90396                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1390275818                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 476724                       # Number of bytes of host memory used
+host_seconds                                   823.94                       # Real time elapsed on the host
+sim_insts                                    61845931                       # Number of instructions simulated
+sim_ops                                      74481224                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::realview.clcd     50331648                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.dtb.walker         2560                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.dtb.walker          384                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.itb.walker          128                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst          7022076                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst          7004988                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu1.dtb.walker          576                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst          3606712                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             60963700                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       763904                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       275840                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         1039744                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      4294592                       # Number of bytes written to this memory
+system.physmem.bytes_read::cpu1.inst          3603320                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             60941044                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       751104                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       270784                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1021888                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      4281152                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.inst         17000                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu1.inst       3010344                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7321936                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7308496                       # Number of bytes written to this memory
 system.physmem.num_reads::realview.clcd       6291456                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.dtb.walker           40                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.dtb.walker            6                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu0.itb.walker            2                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst            109794                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst            109512                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu1.dtb.walker            9                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst             56383                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               6457684                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           67103                       # Number of write requests responded to by this memory
+system.physmem.num_reads::cpu1.inst             56320                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               6457305                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           66893                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.inst             4250                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu1.inst           752586                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               823939                       # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd        43889738                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.dtb.walker          2232                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total               823729                       # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd        43938393                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.dtb.walker           335                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu0.itb.walker           112                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst             6123326                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker           502                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst             3145092                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                53161001                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         666132                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst         240535                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             906668                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           3744930                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.inst              14824                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.inst            2625052                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                6384807                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           3744930                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd       43889738                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker         2232                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst             6115196                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker           503                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst             3145617                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                53200156                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         655697                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst         236388                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             892085                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           3737349                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.inst              14841                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1.inst            2627962                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                6380152                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           3737349                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd       43938393                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker          335                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.itb.walker          112                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst            6138150                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker          502                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst            5770144                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               59545808                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                       6457684                       # Number of read requests accepted
-system.physmem.writeReqs                       823939                       # Number of write requests accepted
-system.physmem.readBursts                     6457684                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     823939                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                413268352                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     23424                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   7334336                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  60963700                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                7321936                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      366                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                  709320                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs          12375                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0              403317                       # Per bank write bursts
-system.physmem.perBankRdBursts::1              403674                       # Per bank write bursts
-system.physmem.perBankRdBursts::2              403089                       # Per bank write bursts
-system.physmem.perBankRdBursts::3              403454                       # Per bank write bursts
-system.physmem.perBankRdBursts::4              406236                       # Per bank write bursts
-system.physmem.perBankRdBursts::5              403730                       # Per bank write bursts
-system.physmem.perBankRdBursts::6              403529                       # Per bank write bursts
-system.physmem.perBankRdBursts::7              403381                       # Per bank write bursts
-system.physmem.perBankRdBursts::8              403672                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              404158                       # Per bank write bursts
-system.physmem.perBankRdBursts::10             403104                       # Per bank write bursts
-system.physmem.perBankRdBursts::11             402562                       # Per bank write bursts
-system.physmem.perBankRdBursts::12             403651                       # Per bank write bursts
-system.physmem.perBankRdBursts::13             403575                       # Per bank write bursts
-system.physmem.perBankRdBursts::14             403252                       # Per bank write bursts
-system.physmem.perBankRdBursts::15             402934                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                7008                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                7418                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                6865                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                7084                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                7615                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                7300                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                7325                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                7167                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                7323                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                7753                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               6901                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               6492                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               7387                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               7157                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               7029                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               6775                       # Per bank write bursts
+system.physmem.bw_total::cpu0.inst            6130037                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker          503                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst            5773579                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               59580308                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                       6457305                       # Number of read requests accepted
+system.physmem.writeReqs                       823729                       # Number of write requests accepted
+system.physmem.readBursts                     6457305                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     823729                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                413239936                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     27584                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   7320448                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  60941044                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                7308496                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      431                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                  709326                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs          12284                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0              403300                       # Per bank write bursts
+system.physmem.perBankRdBursts::1              403658                       # Per bank write bursts
+system.physmem.perBankRdBursts::2              403038                       # Per bank write bursts
+system.physmem.perBankRdBursts::3              403410                       # Per bank write bursts
+system.physmem.perBankRdBursts::4              406147                       # Per bank write bursts
+system.physmem.perBankRdBursts::5              403703                       # Per bank write bursts
+system.physmem.perBankRdBursts::6              403511                       # Per bank write bursts
+system.physmem.perBankRdBursts::7              403334                       # Per bank write bursts
+system.physmem.perBankRdBursts::8              403656                       # Per bank write bursts
+system.physmem.perBankRdBursts::9              404136                       # Per bank write bursts
+system.physmem.perBankRdBursts::10             403079                       # Per bank write bursts
+system.physmem.perBankRdBursts::11             402530                       # Per bank write bursts
+system.physmem.perBankRdBursts::12             403635                       # Per bank write bursts
+system.physmem.perBankRdBursts::13             403544                       # Per bank write bursts
+system.physmem.perBankRdBursts::14             403293                       # Per bank write bursts
+system.physmem.perBankRdBursts::15             402900                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                6991                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                7395                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                6850                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                7056                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                7584                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                7290                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                7311                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                7141                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                7309                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                7743                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               6877                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               6465                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               7382                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               7153                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               7067                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               6768                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    1146771945000                       # Total gap between requests
+system.physmem.totGap                    1145502120500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::2                     109                       # Read request sizes (log2)
-system.physmem.readPktSize::3                 6291456                       # Read request sizes (log2)
+system.physmem.readPktSize::2                      59                       # Read request sizes (log2)
+system.physmem.readPktSize::3                 6291481                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  166119                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  165765                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                 756836                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                  67103                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    558746                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    398674                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                    399850                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                    441647                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                    404684                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                    430598                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                   1121698                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                   1089151                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                   1417401                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                     50859                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                    42455                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                    39349                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                    37752                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                     8359                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                     8007                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                     7903                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                      180                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                  66893                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    558286                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    398741                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                    399967                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                    444496                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                    405001                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                    431562                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                   1118263                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                   1083915                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                   1408608                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                     55788                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                    45494                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                    41962                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                    40334                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                     8421                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                     7962                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                     7851                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                      218                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::17                        5                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
@@ -168,25 +168,25 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     3958                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     3977                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     6613                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     6665                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     6671                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     6670                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     6668                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     6668                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     6670                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     6670                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     6677                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     6672                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     6683                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     6670                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     6668                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     6670                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     6669                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     6665                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     3952                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     3973                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     6584                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     6653                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     6664                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     6655                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     6658                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     6656                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     6659                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     6656                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     6662                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     6658                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     6669                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     6662                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     6657                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     6657                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     6660                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     6652                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
@@ -217,66 +217,66 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       461513                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      911.356100                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     779.117173                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     292.189115                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          24977      5.41%      5.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        21582      4.68%     10.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         5972      1.29%     11.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         2646      0.57%     11.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2555      0.55%     12.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1574      0.34%     12.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         4102      0.89%     13.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          979      0.21%     13.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151       397126     86.05%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         461513                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          6665                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean       968.839160                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev    26148.924018                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-65535          6658     99.89%     99.89% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples       460787                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      912.700193                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     781.910252                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     290.668132                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          24338      5.28%      5.28% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        21658      4.70%      9.98% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         5935      1.29%     11.27% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         2553      0.55%     11.82% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2424      0.53%     12.35% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1615      0.35%     12.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         4021      0.87%     13.57% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          977      0.21%     13.79% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151       397266     86.21%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         460787                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          6652                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean       970.665664                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev    26177.869763                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-65535          6645     99.89%     99.89% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::196608-262143            3      0.05%     99.94% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::589824-655359            1      0.02%     99.95% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::786432-851967            1      0.02%     99.97% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::983040-1.04858e+06            1      0.02%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::1.50733e+06-1.57286e+06            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            6665                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          6665                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        17.194149                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       17.165520                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        0.984786                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16               2686     40.30%     40.30% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17                 20      0.30%     40.60% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18               3941     59.13%     99.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19                 15      0.23%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                  3      0.05%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            6665                       # Writes before turning the bus around for reads
-system.physmem.totQLat                   165007028750                       # Total ticks spent queuing
-system.physmem.totMemAccLat              286081741250                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                  32286590000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       25553.49                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            6652                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          6652                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.195129                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       17.166489                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        0.984981                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               2678     40.26%     40.26% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17                 22      0.33%     40.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18               3930     59.08%     99.67% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19                 20      0.30%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                  2      0.03%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            6652                       # Writes before turning the bus around for reads
+system.physmem.totQLat                   165525335000                       # Total ticks spent queuing
+system.physmem.totMemAccLat              286591722500                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                  32284370000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       25635.52                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  44303.49                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         360.37                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           6.40                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       53.16                       # Average system read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  44385.52                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         360.75                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           6.39                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       53.20                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        6.38                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           2.87                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       2.82                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.05                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         4.16                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        21.54                       # Average write queue length when enqueuing
-system.physmem.readRowHits                    6015984                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     94420                       # Number of row buffer hits during writes
+system.physmem.avgRdQLen                         3.81                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        26.84                       # Average write queue length when enqueuing
+system.physmem.readRowHits                    6016106                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     94363                       # Number of row buffer hits during writes
 system.physmem.readRowHitRate                   93.17                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  82.38                       # Row buffer hit rate for writes
-system.physmem.avgGap                       157488.51                       # Average gap between requests
-system.physmem.pageHitRate                      92.98                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE     908124290750                       # Time in different power states
-system.physmem.memoryStateTime::REF       38293320000                       # Time in different power states
+system.physmem.writeRowHitRate                  82.48                       # Row buffer hit rate for writes
+system.physmem.avgGap                       157326.85                       # Average gap between requests
+system.physmem.pageHitRate                      92.99                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE     907058635500                       # Time in different power states
+system.physmem.memoryStateTime::REF       38250680000                       # Time in different power states
 system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT      200357121750                       # Time in different power states
+system.physmem.memoryStateTime::ACT      200188472000                       # Time in different power states
 system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
 system.realview.nvmem.bytes_read::cpu0.inst          256                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu1.inst          448                       # Number of bytes read from this memory
@@ -289,266 +289,266 @@ system.realview.nvmem.num_reads::cpu1.inst            7                       #
 system.realview.nvmem.num_reads::total             11                       # Number of read requests responded to by this memory
 system.realview.nvmem.bw_read::cpu0.inst          223                       # Total read bandwidth from this memory (bytes/s)
 system.realview.nvmem.bw_read::cpu1.inst          391                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total              614                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total              615                       # Total read bandwidth from this memory (bytes/s)
 system.realview.nvmem.bw_inst_read::cpu0.inst          223                       # Instruction read bandwidth from this memory (bytes/s)
 system.realview.nvmem.bw_inst_read::cpu1.inst          391                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total          614                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total          615                       # Instruction read bandwidth from this memory (bytes/s)
 system.realview.nvmem.bw_total::cpu0.inst          223                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::cpu1.inst          391                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total             614                       # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput                     61651742                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq             7506663                       # Transaction distribution
-system.membus.trans_dist::ReadResp            7506663                       # Transaction distribution
-system.membus.trans_dist::WriteReq             767825                       # Transaction distribution
-system.membus.trans_dist::WriteResp            767825                       # Transaction distribution
-system.membus.trans_dist::Writeback             67103                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            33483                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq          17276                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp           12375                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            137796                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           137454                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave      2382664                       # Packet count per connected master and slave (bytes)
+system.realview.nvmem.bw_total::total             615                       # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput                     61688542                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq             7506218                       # Transaction distribution
+system.membus.trans_dist::ReadResp            7506218                       # Transaction distribution
+system.membus.trans_dist::WriteReq             767823                       # Transaction distribution
+system.membus.trans_dist::WriteResp            767823                       # Transaction distribution
+system.membus.trans_dist::Writeback             66893                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq            33061                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq          17229                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp           12284                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            137868                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           137512                       # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave      2382652                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           22                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        11280                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        11272                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio            4                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio          874                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      1976707                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total      4371551                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      1975193                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total      4370017                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port     12582912                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::total     12582912                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total               16954463                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave      2390012                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count::total               16952929                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave      2389988                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port          704                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio        22560                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio        22544                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio            8                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio         1748                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port     17953988                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::total     20369020                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port     17917892                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::total     20332884                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port     50331648                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.iocache.mem_side::total     50331648                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total            70700668                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus               70700668                       # Total data (bytes)
+system.membus.tot_pkt_size::total            70664532                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus               70664532                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy          1725618000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy          1775897999                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.2                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy               16500                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy            10203000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy            10198500                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer4.occupancy                2500                       # Layer occupancy (ticks)
 system.membus.reqLayer4.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy              700000                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy              781000                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer6.occupancy          8808401000                       # Layer occupancy (ticks)
+system.membus.reqLayer6.occupancy          8866177500                       # Layer occupancy (ticks)
 system.membus.reqLayer6.utilization               0.8                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         4909176600                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         4931588899                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.4                       # Layer utilization (%)
-system.membus.respLayer2.occupancy        15579623500                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy        15569082998                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              1.4                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.l2c.tags.replacements                    73595                       # number of replacements
-system.l2c.tags.tagsinuse                53913.869309                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    2430089                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                   138750                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                    17.514155                       # Average number of references to valid blocks.
+system.l2c.tags.replacements                    73238                       # number of replacements
+system.l2c.tags.tagsinuse                53823.910561                       # Cycle average of tags in use
+system.l2c.tags.total_refs                    2398257                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                   138408                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                    17.327445                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   38825.506974                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker    30.840279                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker     0.001297                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     8944.299229                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker     7.867460                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst     6105.354070                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.592430                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000471                       # Average percentage of cache occupancy
+system.l2c.tags.occ_blocks::writebacks   38958.946929                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.dtb.walker     1.880846                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker     0.001294                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     8788.881914                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.dtb.walker     7.740937                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst     6066.458640                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.594466                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000029                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu0.itb.walker     0.000000                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.136479                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000120                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.093160                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.822660                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1023           14                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024        65141                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4           14                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0           27                       # Occupied blocks per task id
+system.l2c.tags.occ_percent::cpu0.inst       0.134108                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000118                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.092567                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.821288                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1023            6                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1024        65164                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::4            6                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0           32                       # Occupied blocks per task id
 system.l2c.tags.age_task_id_blocks_1024::1           83                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         2303                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         8599                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        54129                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1023     0.000214                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024     0.993973                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                 23296068                       # Number of tag accesses
-system.l2c.tags.data_accesses                23296068                       # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.dtb.walker        29004                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker         6772                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.inst             959141                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker        26476                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker         5085                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst             968677                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                1995155                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks          576981                       # number of Writeback hits
-system.l2c.Writeback_hits::total               576981                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.inst             913                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.inst             959                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                1872                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.inst           209                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.inst           100                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total               309                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.inst            58748                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.inst            50778                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               109526                       # number of ReadExReq hits
-system.l2c.demand_hits::cpu0.dtb.walker         29004                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker          6772                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst             1017889                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker         26476                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker          5085                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst             1019455                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 2104681                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker        29004                       # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker         6772                       # number of overall hits
-system.l2c.overall_hits::cpu0.inst            1017889                       # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker        26476                       # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker         5085                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst            1019455                       # number of overall hits
-system.l2c.overall_hits::total                2104681                       # number of overall hits
-system.l2c.ReadReq_misses::cpu0.dtb.walker           40                       # number of ReadReq misses
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+system.l2c.tags.age_task_id_blocks_1024::4        53947                       # Occupied blocks per task id
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+system.l2c.tags.occ_task_id_percent::1024     0.994324                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                 23040420                       # Number of tag accesses
+system.l2c.tags.data_accesses                23040420                       # Number of data accesses
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+system.l2c.UpgradeReq_miss_rate::cpu1.inst     0.798349                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.818698                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.inst     0.773942                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.inst     0.761421                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.770124                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.inst     0.611822                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.inst     0.483194                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.561182                       # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker     0.000269                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker     0.000305                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.097242                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.dtb.walker     0.000396                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.053589                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.073988                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker     0.000269                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker     0.000305                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.097242                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.dtb.walker     0.000396                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.053589                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.073988                       # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 98666.666667                       # average ReadReq miss latency
 system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker        74750                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.inst 70713.081715                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 73472.222222                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.inst 75389.928283                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 72482.696723                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.inst  1688.596134                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.inst  3312.875914                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total  2431.796988                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.inst   986.780381                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.inst  6746.480645                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total  2784.874119                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.inst 68352.360174                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.inst 70946.600321                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 69231.283268                       # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 75981.250000                       # average overall miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.inst 70406.981437                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 79583.333333                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.inst 74776.525199                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 72069.061946                       # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu0.inst  1670.249231                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.inst  3352.884047                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total  2434.689744                       # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.inst  1000.676259                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.inst  7273.020000                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::total  2891.835176                       # average SCUpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0.inst 69232.056366                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.inst 71404.852120                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 69968.594666                       # average ReadExReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 98666.666667                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::cpu0.itb.walker        74750                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 68707.454054                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 73472.222222                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 71715.354525                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 69746.528915                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 75981.250000                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.inst 69406.384305                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 79583.333333                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 71982.513092                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 70297.070621                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 98666.666667                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu0.itb.walker        74750                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 68707.454054                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 73472.222222                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 71715.354525                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 69746.528915                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.inst 69406.384305                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 79583.333333                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 71982.513092                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 70297.070621                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -557,134 +557,134 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks               67103                       # number of writebacks
-system.l2c.writebacks::total                    67103                       # number of writebacks
+system.l2c.writebacks::writebacks               66893                       # number of writebacks
+system.l2c.writebacks::total                    66893                       # number of writebacks
 system.l2c.ReadReq_mshr_hits::cpu0.inst            49                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu1.inst            19                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::total                68                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu1.inst            22                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::total                71                       # number of ReadReq MSHR hits
 system.l2c.demand_mshr_hits::cpu0.inst             49                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.inst             19                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total                 68                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu1.inst             22                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::total                 71                       # number of demand (read+write) MSHR hits
 system.l2c.overall_mshr_hits::cpu0.inst            49                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.inst            19                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total                68                       # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker           40                       # number of ReadReq MSHR misses
+system.l2c.overall_mshr_hits::cpu1.inst            22                       # number of overall MSHR hits
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 system.l2c.ReadReq_mshr_misses::cpu0.itb.walker            2                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.inst        16325                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu0.inst        16058                       # number of ReadReq MSHR misses
 system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker            9                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.inst         9895                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total           26271                       # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0.inst         4863                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.inst         4102                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total         8965                       # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu0.inst          683                       # number of SCUpgradeReq MSHR misses
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-system.l2c.SCUpgradeReq_mshr_misses::total          993                       # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu0.inst        92483                       # number of ReadExReq MSHR misses
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+system.l2c.SCUpgradeReq_mshr_misses::cpu0.inst          695                       # number of SCUpgradeReq MSHR misses
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 system.l2c.demand_mshr_misses::cpu0.itb.walker            2                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.inst       108808                       # number of demand (read+write) MSHR misses
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 system.l2c.demand_mshr_misses::cpu1.dtb.walker            9                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst        57283                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total           166142                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu0.dtb.walker           40                       # number of overall MSHR misses
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 system.l2c.overall_mshr_misses::cpu0.itb.walker            2                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.inst       108808                       # number of overall MSHR misses
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 system.l2c.overall_mshr_misses::cpu1.dtb.walker            9                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst        57283                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total          166142                       # number of overall MSHR misses
-system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker      2549250                       # number of ReadReq MSHR miss cycles
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+system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker       518500                       # number of ReadReq MSHR miss cycles
 system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker       125000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    950227250                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker       549750                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    622555749                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total   1576006999                       # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu0.inst     48716838                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.inst     41086590                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total     89803428                       # number of UpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.inst      6847181                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.inst      3100809                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::total      9947990                       # number of SCUpgradeReq MSHR miss cycles
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-system.l2c.ReadExReq_mshr_miss_latency::cpu1.inst   2766953994                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total   7927077156                       # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker      2549250                       # number of demand (read+write) MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    929504000                       # number of ReadReq MSHR miss cycles
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+system.l2c.UpgradeReq_mshr_miss_latency::cpu0.inst     48881350                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.inst     40684546                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total     89565896                       # number of UpgradeReq MSHR miss cycles
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+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.inst      3002299                       # number of SCUpgradeReq MSHR miss cycles
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+system.l2c.ReadExReq_mshr_miss_latency::total   8003811840                       # number of ReadExReq MSHR miss cycles
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 system.l2c.demand_mshr_miss_latency::cpu0.itb.walker       125000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.inst   6110350412                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker       549750                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst   3389509743                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total   9503084155                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker      2549250                       # number of overall MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.inst   6157493883                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker       603750                       # number of demand (read+write) MSHR miss cycles
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+system.l2c.demand_mshr_miss_latency::total   9543895090                       # number of demand (read+write) MSHR miss cycles
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 system.l2c.overall_mshr_miss_latency::cpu0.itb.walker       125000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.inst   6110350412                       # number of overall MSHR miss cycles
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-system.l2c.overall_mshr_miss_latency::total   9503084155                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 156402291235                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst  10978060744                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total 167380351979                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.inst   1364398990                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.inst  15414990793                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total  16779389783                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 157766690225                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.inst  26393051537                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total 184159741762                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.001377                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.000295                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.016735                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.000340                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.010111                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.012996                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.inst     0.841932                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.inst     0.810512                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.827258                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.inst     0.765695                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.inst     0.756098                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.762673                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.inst     0.611535                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.inst     0.482733                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.560837                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.001377                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.000295                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.096568                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.000340                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.053200                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.073162                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.001377                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.000295                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.096568                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.000340                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.053200                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.073162                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 63731.250000                       # average ReadReq mshr miss latency
+system.l2c.overall_mshr_miss_latency::cpu0.inst   6157493883                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker       603750                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst   3385153957                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total   9543895090                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 156449024487                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst  10979297747                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total 167428322234                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.inst   1364347483                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.inst  15414886347                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total  16779233830                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 157813371970                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.inst  26394184094                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total 184207556064                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.000269                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.000305                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.016636                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.000396                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.010088                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.012983                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.inst     0.836448                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.inst     0.798349                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.818698                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.inst     0.773942                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.inst     0.761421                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.770124                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.inst     0.611822                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.inst     0.483194                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.561182                       # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.000269                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.000305                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.097198                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.000396                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.053569                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.073956                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.000269                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.000305                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.097198                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.000396                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.053569                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.073956                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 86416.666667                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker        62500                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 58206.875957                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 61083.333333                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 62916.194947                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 59990.369571                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 10017.856878                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 10016.233545                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10017.114110                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 10025.155198                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 10002.609677                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10018.116818                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.inst 55795.369549                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.inst 58389.338947                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 56674.200914                       # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 63731.250000                       # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 57884.169884                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 67083.333333                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 62303.885481                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 59566.167086                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 10018.723099                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 10015.890202                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10017.436081                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 10062.861871                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 10007.663333                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10046.219095                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.inst 56549.376777                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.inst 58549.292491                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 57227.311883                       # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 86416.666667                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker        62500                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 56157.179729                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 61083.333333                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 59171.302882                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 57198.566016                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 63731.250000                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 56746.911592                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 67083.333333                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 59191.361374                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 57592.222128                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 86416.666667                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker        62500                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 56157.179729                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 61083.333333                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 59171.302882                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 57198.566016                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 56746.911592                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 67083.333333                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 59191.361374                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 57592.222128                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -701,62 +701,62 @@ system.cf0.dma_read_txs                             0                       # Nu
 system.cf0.dma_write_full_pages                     0                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                          0                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
-system.toL2Bus.throughput                   164548117                       # Throughput (bytes/s)
-system.toL2Bus.trans_dist::ReadReq            3298522                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           3298521                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq            767825                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp           767825                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback           576981                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq           32938                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq         17585                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp          50523                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           260723                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          260723                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      1574360                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      3288712                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side        16464                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        66826                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side      1600801                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side      2571055                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side        13478                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side        62668                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               9194364                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     50355392                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     43867388                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side        27096                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side       116176                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side     51198592                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side     38125568                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side        20340                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side       105940                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size::total          183816492                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.data_through_bus             183816492                       # Total data (bytes)
-system.toL2Bus.snoop_data_through_bus         4883152                       # Total snoop data (bytes)
-system.toL2Bus.reqLayer0.occupancy         5169541990                       # Layer occupancy (ticks)
-system.toL2Bus.reqLayer0.utilization              0.5                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy        3546630183                       # Layer occupancy (ticks)
+system.toL2Bus.throughput                   163445997                       # Throughput (bytes/s)
+system.toL2Bus.trans_dist::ReadReq            3265310                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp           3265309                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq            767823                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp           767823                       # Transaction distribution
+system.toL2Bus.trans_dist::Writeback           575172                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq           32693                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq         17526                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp          50219                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq           260531                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp          260531                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      1555911                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      3285118                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side        16087                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        52607                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side      1583939                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side      2567940                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side        13476                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side        53641                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total               9128719                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     49766528                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     43750900                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side        26264                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        89112                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side     50661248                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side     38001760                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side        20756                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side        90928                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size::total          182407496                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.data_through_bus             182407496                       # Total data (bytes)
+system.toL2Bus.snoop_data_through_bus         4820708                       # Total snoop data (bytes)
+system.toL2Bus.reqLayer0.occupancy         5144551012                       # Layer occupancy (ticks)
+system.toL2Bus.reqLayer0.utilization              0.4                       # Layer utilization (%)
+system.toL2Bus.respLayer0.occupancy        3505001405                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.3                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy        2800512724                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy        2792622052                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.2                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy           9693493                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy           9525491                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy          37783748                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy          30330496                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer6.occupancy        3604679924                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer6.occupancy        3566573438                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer6.utilization             0.3                       # Layer utilization (%)
-system.toL2Bus.respLayer7.occupancy        1938501968                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer7.occupancy        1934335367                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer7.utilization             0.2                       # Layer utilization (%)
-system.toL2Bus.respLayer8.occupancy           8396493                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer8.occupancy           8290992                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer8.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer9.occupancy          36187242                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer9.occupancy          30912744                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer9.utilization             0.0                       # Layer utilization (%)
-system.iobus.throughput                      45973854                       # Throughput (bytes/s)
-system.iobus.trans_dist::ReadReq              7474822                       # Transaction distribution
-system.iobus.trans_dist::ReadResp             7474822                       # Transaction distribution
+system.iobus.throughput                      46024799                       # Throughput (bytes/s)
+system.iobus.trans_dist::ReadReq              7474816                       # Transaction distribution
+system.iobus.trans_dist::ReadResp             7474816                       # Transaction distribution
 system.iobus.trans_dist::WriteReq                7966                       # Transaction distribution
 system.iobus.trans_dist::WriteResp               7966                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        30566                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio         8050                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio         8038                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio          732                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio           36                       # Packet count per connected master and slave (bytes)
@@ -778,12 +778,12 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total      2382664                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total      2382652                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side     12582912                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.clcd.dma::total     12582912                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                14965576                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                14965564                       # Packet count per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio        40335                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio        16100                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio        16076                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio         1464                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio           72                       # Cumulative packet size per connected master and slave (bytes)
@@ -805,14 +805,14 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::total      2390012                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::total      2389988                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side     50331648                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.realview.clcd.dma::total     50331648                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::total             52721660                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.data_through_bus                52721660                       # Total data (bytes)
+system.iobus.tot_pkt_size::total             52721636                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.data_through_bus                52721636                       # Total data (bytes)
 system.iobus.reqLayer0.occupancy             21429000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy              4031000                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy              4025000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer2.occupancy                34000                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
@@ -858,19 +858,19 @@ system.iobus.reqLayer23.occupancy                8000                       # La
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer25.occupancy          6291456000                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.5                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy          2374698000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy          2374686000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.2                       # Layer utilization (%)
-system.iobus.respLayer1.occupancy         15850285500                       # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy         15862213002                       # Layer occupancy (ticks)
 system.iobus.respLayer1.utilization               1.4                       # Layer utilization (%)
-system.cpu0.branchPred.lookups                6861856                       # Number of BP lookups
-system.cpu0.branchPred.condPredicted          5181081                       # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect           652173                       # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups             4714052                       # Number of BTB lookups
-system.cpu0.branchPred.BTBHits                3350352                       # Number of BTB hits
+system.cpu0.branchPred.lookups                6670288                       # Number of BP lookups
+system.cpu0.branchPred.condPredicted          4756995                       # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect           639495                       # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups             4605007                       # Number of BTB lookups
+system.cpu0.branchPred.BTBHits                3289427                       # Number of BTB hits
 system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct            71.071596                       # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS                 844036                       # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect             70439                       # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct            71.431531                       # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS                 870926                       # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect             69312                       # Number of incorrect RAS predictions.
 system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -894,25 +894,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # D
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                     8249046                       # DTB read hits
-system.cpu0.dtb.read_misses                     22426                       # DTB read misses
-system.cpu0.dtb.write_hits                    6048331                       # DTB write hits
-system.cpu0.dtb.write_misses                     1452                       # DTB write misses
+system.cpu0.dtb.read_hits                     7193152                       # DTB read hits
+system.cpu0.dtb.read_misses                     17493                       # DTB read misses
+system.cpu0.dtb.write_hits                    6058571                       # DTB write hits
+system.cpu0.dtb.write_misses                     1416                       # DTB write misses
 system.cpu0.dtb.flush_tlb                           4                       # Number of times complete TLB was flushed
 system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
 system.cpu0.dtb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.dtb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                    1952                       # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults                     1134                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                   199                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_entries                    1942                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults                     1486                       # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults                   207                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                      288                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                 8271472                       # DTB read accesses
-system.cpu0.dtb.write_accesses                6049783                       # DTB write accesses
+system.cpu0.dtb.perms_faults                      320                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses                 7210645                       # DTB read accesses
+system.cpu0.dtb.write_accesses                6059987                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                         14297377                       # DTB hits
-system.cpu0.dtb.misses                          23878                       # DTB misses
-system.cpu0.dtb.accesses                     14321255                       # DTB accesses
+system.cpu0.dtb.hits                         13251723                       # DTB hits
+system.cpu0.dtb.misses                          18909                       # DTB misses
+system.cpu0.dtb.accesses                     13270632                       # DTB accesses
 system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -934,8 +934,8 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.inst_hits                    12515958                       # ITB inst hits
-system.cpu0.itb.inst_misses                      4886                       # ITB inst misses
+system.cpu0.itb.inst_hits                    12268451                       # ITB inst hits
+system.cpu0.itb.inst_misses                      4809                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
@@ -944,82 +944,82 @@ system.cpu0.itb.flush_tlb                           4                       # Nu
 system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
 system.cpu0.itb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.itb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                    1295                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_entries                    1294                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults                     2118                       # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults                     2809                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses                12520844                       # ITB inst accesses
-system.cpu0.itb.hits                         12515958                       # DTB hits
-system.cpu0.itb.misses                           4886                       # DTB misses
-system.cpu0.itb.accesses                     12520844                       # DTB accesses
-system.cpu0.numCycles                       433909161                       # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses                12273260                       # ITB inst accesses
+system.cpu0.itb.hits                         12268451                       # DTB hits
+system.cpu0.itb.misses                           4809                       # DTB misses
+system.cpu0.itb.accesses                     12273260                       # DTB accesses
+system.cpu0.numCycles                       431172708                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                   29915294                       # Number of instructions committed
-system.cpu0.committedOps                     39343022                       # Number of ops (including micro ops) committed
-system.cpu0.discardedOps                      1900672                       # Number of ops (including micro ops) which were discarded before commit
-system.cpu0.numFetchSuspends                    39481                       # Number of times Execute suspended instruction fetching
-system.cpu0.quiesceCycles                  1859706962                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.cpi                             14.504593                       # CPI: cycles per instruction
-system.cpu0.ipc                              0.068944                       # IPC: instructions per cycle
+system.cpu0.committedInsts                   29878954                       # Number of instructions committed
+system.cpu0.committedOps                     36403873                       # Number of ops (including micro ops) committed
+system.cpu0.discardedOps                      1704985                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu0.numFetchSuspends                    39450                       # Number of times Execute suspended instruction fetching
+system.cpu0.quiesceCycles                  1859905219                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.cpi                             14.430649                       # CPI: cycles per instruction
+system.cpu0.ipc                              0.069297                       # IPC: instructions per cycle
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                   50347                       # number of quiesce instructions executed
-system.cpu0.tickCycles                      353761855                       # Number of cycles that the object actually ticked
-system.cpu0.idleCycles                       80147306                       # Total number of cycles that the object has spent stopped
-system.cpu0.icache.tags.replacements           784713                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          510.784867                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs           11728456                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs           785225                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            14.936427                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle      10280766000                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   510.784867                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.997627                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.997627                       # Average percentage of cache occupancy
+system.cpu0.kern.inst.quiesce                   50317                       # number of quiesce instructions executed
+system.cpu0.tickCycles                      351703832                       # Number of cycles that the object actually ticked
+system.cpu0.idleCycles                       79468876                       # Total number of cycles that the object has spent stopped
+system.cpu0.icache.tags.replacements           775463                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          510.771777                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs           11489502                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs           775975                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            14.806536                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle      10202297000                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   510.771777                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.997601                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.997601                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2          506                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::3            6                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2          507                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::3            5                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses         13298912                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses        13298912                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst     11728456                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total       11728456                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst     11728456                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total        11728456                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst     11728456                       # number of overall hits
-system.cpu0.icache.overall_hits::total       11728456                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst       785228                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total       785228                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst       785228                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total        785228                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst       785228                       # number of overall misses
-system.cpu0.icache.overall_misses::total       785228                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  10819127683                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total  10819127683                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst  10819127683                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total  10819127683                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst  10819127683                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total  10819127683                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst     12513684                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total     12513684                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst     12513684                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total     12513684                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst     12513684                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total     12513684                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.062750                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.062750                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.062750                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.062750                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.062750                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.062750                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13778.326401                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 13778.326401                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13778.326401                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 13778.326401                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13778.326401                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 13778.326401                       # average overall miss latency
+system.cpu0.icache.tags.tag_accesses         13041458                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses        13041458                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst     11489502                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total       11489502                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst     11489502                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total        11489502                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst     11489502                       # number of overall hits
+system.cpu0.icache.overall_hits::total       11489502                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst       775978                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total       775978                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst       775978                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total        775978                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst       775978                       # number of overall misses
+system.cpu0.icache.overall_misses::total       775978                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  10689826155                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total  10689826155                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst  10689826155                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total  10689826155                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst  10689826155                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total  10689826155                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst     12265480                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total     12265480                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst     12265480                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total     12265480                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst     12265480                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total     12265480                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.063265                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.063265                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.063265                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.063265                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.063265                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.063265                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13775.939724                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 13775.939724                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13775.939724                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 13775.939724                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13775.939724                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 13775.939724                       # average overall miss latency
 system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1028,125 +1028,125 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       785228                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total       785228                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst       785228                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total       785228                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst       785228                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total       785228                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   9244507317                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total   9244507317                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   9244507317                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total   9244507317                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   9244507317                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total   9244507317                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    171313500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total    171313500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    171313500                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::total    171313500                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.062750                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.062750                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.062750                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.062750                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.062750                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.062750                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11773.023016                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11773.023016                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11773.023016                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 11773.023016                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11773.023016                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 11773.023016                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       775978                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total       775978                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst       775978                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total       775978                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst       775978                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total       775978                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   9133730845                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total   9133730845                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   9133730845                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total   9133730845                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   9133730845                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total   9133730845                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    171406750                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total    171406750                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    171406750                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::total    171406750                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.063265                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.063265                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.063265                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.063265                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.063265                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.063265                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11770.605410                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11770.605410                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11770.605410                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 11770.605410                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11770.605410                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 11770.605410                       # average overall mshr miss latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.dcache.tags.replacements           332522                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          495.116335                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           12493941                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs           332889                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            37.531853                       # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle        236260250                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.inst   495.116335                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.inst     0.967024                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.967024                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_task_id_blocks::1024          367                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2          367                       # Occupied blocks per task id
-system.cpu0.dcache.tags.occ_task_id_percent::1024     0.716797                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses         52581205                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses        52581205                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.inst      6652234                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total        6652234                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.inst      5513247                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total       5513247                       # number of WriteReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.inst       152467                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       152467                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.inst       153686                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       153686                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.inst     12165481                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        12165481                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.inst     12165481                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       12165481                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.inst       257861                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total       257861                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.inst       307489                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total       307489                       # number of WriteReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.inst         8753                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total         8753                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.inst         7461                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total         7461                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.inst       565350                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total        565350                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.inst       565350                       # number of overall misses
-system.cpu0.dcache.overall_misses::total       565350                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.inst   3878128215                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total   3878128215                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.inst  15135680350                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total  15135680350                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.inst     89040000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total     89040000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.inst     47241681                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total     47241681                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.inst  19013808565                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total  19013808565                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.inst  19013808565                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total  19013808565                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.inst      6910095                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total      6910095                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.inst      5820736                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total      5820736                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.inst       161220                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       161220                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.inst       161147                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       161147                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.inst     12730831                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     12730831                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.inst     12730831                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     12730831                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.inst     0.037317                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.037317                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.inst     0.052826                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.052826                       # miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.inst     0.054292                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.054292                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.inst     0.046299                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.046299                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.inst     0.044408                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.044408                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.inst     0.044408                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.044408                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.inst 15039.607444                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 15039.607444                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.inst 49223.485556                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 49223.485556                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.inst 10172.512282                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10172.512282                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.inst  6331.816244                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total  6331.816244                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.inst 33631.924587                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 33631.924587                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.inst 33631.924587                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 33631.924587                       # average overall miss latency
+system.cpu0.dcache.tags.replacements           331184                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          495.308279                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs           11419092                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs           331547                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            34.441850                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.warmup_cycle        235572250                       # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.tags.occ_blocks::cpu0.inst   495.308279                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.inst     0.967399                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.967399                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_task_id_blocks::1024          363                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2          363                       # Occupied blocks per task id
+system.cpu0.dcache.tags.occ_task_id_percent::1024     0.708984                       # Percentage of cache occupancy per task id
+system.cpu0.dcache.tags.tag_accesses         48281639                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses        48281639                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.inst      5587990                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total        5587990                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.inst      5501455                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total       5501455                       # number of WriteReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.inst       152609                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       152609                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.inst       153662                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       153662                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.inst     11089445                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total        11089445                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.inst     11089445                       # number of overall hits
+system.cpu0.dcache.overall_hits::total       11089445                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.inst       255115                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total       255115                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.inst       311930                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total       311930                       # number of WriteReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.inst         8548                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total         8548                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.inst         7439                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total         7439                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.inst       567045                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total        567045                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.inst       567045                       # number of overall misses
+system.cpu0.dcache.overall_misses::total       567045                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.inst   3832963977                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total   3832963977                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.inst  15354005377                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total  15354005377                       # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.inst     89150250                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total     89150250                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.inst     47371188                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total     47371188                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.inst  19186969354                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total  19186969354                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.inst  19186969354                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total  19186969354                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.inst      5843105                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total      5843105                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.inst      5813385                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total      5813385                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.inst       161157                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       161157                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.inst       161101                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       161101                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.inst     11656490                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     11656490                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.inst     11656490                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     11656490                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.inst     0.043661                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.043661                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.inst     0.053657                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.053657                       # miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.inst     0.053041                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.053041                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.inst     0.046176                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.046176                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.inst     0.048646                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.048646                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.inst     0.048646                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.048646                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.inst 15024.455547                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 15024.455547                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.inst 49222.599227                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 49222.599227                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.inst 10429.369443                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10429.369443                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.inst  6367.951069                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total  6367.951069                       # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.inst 33836.766666                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 33836.766666                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.inst 33836.766666                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 33836.766666                       # average overall miss latency
 system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1155,72 +1155,72 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       307804                       # number of writebacks
-system.cpu0.dcache.writebacks::total           307804                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.inst        51446                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total        51446                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.inst       139700                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total       139700                       # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.inst           20                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total           20                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.inst       191146                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total       191146                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.inst       191146                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total       191146                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.inst       206415                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       206415                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.inst       167789                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       167789                       # number of WriteReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.inst         8733                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total         8733                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.inst         7461                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total         7461                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.inst       374204                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total       374204                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.inst       374204                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total       374204                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.inst   2545797312                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total   2545797312                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.inst   7212492893                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total   7212492893                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.inst     71207000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     71207000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.inst     32318319                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total     32318319                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.inst   9758290205                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total   9758290205                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.inst   9758290205                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total   9758290205                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.inst 170750199252                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 170750199252                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.inst   1513150500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   1513150500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.inst 172263349752                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total 172263349752                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.inst     0.029872                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.029872                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.inst     0.028826                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.028826                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.inst     0.054168                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.054168                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.inst     0.046299                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.046299                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.inst     0.029394                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.029394                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.inst     0.029394                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.029394                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12333.392980                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12333.392980                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.inst 42985.493048                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 42985.493048                       # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.inst  8153.784496                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total  8153.784496                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.inst  4331.633695                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total  4331.633695                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.inst 26077.460970                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26077.460970                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.inst 26077.460970                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26077.460970                       # average overall mshr miss latency
+system.cpu0.dcache.writebacks::writebacks       307170                       # number of writebacks
+system.cpu0.dcache.writebacks::total           307170                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.inst        50178                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total        50178                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.inst       144238                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total       144238                       # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.inst           22                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total           22                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.inst       194416                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total       194416                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.inst       194416                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total       194416                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.inst       204937                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total       204937                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.inst       167692                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       167692                       # number of WriteReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.inst         8526                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total         8526                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.inst         7439                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total         7439                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.inst       372629                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total       372629                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.inst       372629                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total       372629                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.inst   2523643558                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total   2523643558                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.inst   7293302576                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total   7293302576                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.inst     71695750                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     71695750                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.inst     32490812                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total     32490812                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.inst   9816946134                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total   9816946134                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.inst   9816946134                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total   9816946134                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.inst 170796520252                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 170796520252                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.inst   1513122000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   1513122000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.inst 172309642252                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 172309642252                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.inst     0.035073                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.035073                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.inst     0.028846                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.028846                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.inst     0.052905                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.052905                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.inst     0.046176                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.046176                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.inst     0.031968                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.031968                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.inst     0.031968                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.031968                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12314.240757                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12314.240757                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.inst 43492.251127                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43492.251127                       # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.inst  8409.072250                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total  8409.072250                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.inst  4367.631671                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total  4367.631671                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.inst 26345.094273                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26345.094273                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.inst 26345.094273                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26345.094273                       # average overall mshr miss latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average WriteReq mshr uncacheable latency
@@ -1228,15 +1228,15 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf
 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.branchPred.lookups                6346953                       # Number of BP lookups
-system.cpu1.branchPred.condPredicted          4931527                       # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect           433505                       # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups             4095605                       # Number of BTB lookups
-system.cpu1.branchPred.BTBHits                3083437                       # Number of BTB hits
+system.cpu1.branchPred.lookups                6159330                       # Number of BP lookups
+system.cpu1.branchPred.condPredicted          4534606                       # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect           426160                       # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups             3924244                       # Number of BTB lookups
+system.cpu1.branchPred.BTBHits                3043762                       # Number of BTB hits
 system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct            75.286484                       # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS                 663921                       # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect             63861                       # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct            77.563016                       # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS                 713205                       # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect             64399                       # Number of incorrect RAS predictions.
 system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -1260,25 +1260,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # D
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                     7581512                       # DTB read hits
-system.cpu1.dtb.read_misses                     20239                       # DTB read misses
-system.cpu1.dtb.write_hits                    5551171                       # DTB write hits
-system.cpu1.dtb.write_misses                     2521                       # DTB write misses
+system.cpu1.dtb.read_hits                     6763605                       # DTB read hits
+system.cpu1.dtb.read_misses                     17087                       # DTB read misses
+system.cpu1.dtb.write_hits                    5563764                       # DTB write hits
+system.cpu1.dtb.write_misses                     2456                       # DTB write misses
 system.cpu1.dtb.flush_tlb                           4                       # Number of times complete TLB was flushed
 system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
 system.cpu1.dtb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.dtb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                    1717                       # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults                     2404                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                   233                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.flush_entries                    1713                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults                     1918                       # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults                   230                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                      237                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                 7601751                       # DTB read accesses
-system.cpu1.dtb.write_accesses                5553692                       # DTB write accesses
+system.cpu1.dtb.perms_faults                      260                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses                 6780692                       # DTB read accesses
+system.cpu1.dtb.write_accesses                5566220                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                         13132683                       # DTB hits
-system.cpu1.dtb.misses                          22760                       # DTB misses
-system.cpu1.dtb.accesses                     13155443                       # DTB accesses
+system.cpu1.dtb.hits                         12327369                       # DTB hits
+system.cpu1.dtb.misses                          19543                       # DTB misses
+system.cpu1.dtb.accesses                     12346912                       # DTB accesses
 system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -1300,8 +1300,8 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.inst_hits                    11349850                       # ITB inst hits
-system.cpu1.itb.inst_misses                      4207                       # ITB inst misses
+system.cpu1.itb.inst_hits                    11206823                       # ITB inst hits
+system.cpu1.itb.inst_misses                      4156                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
@@ -1310,84 +1310,84 @@ system.cpu1.itb.flush_tlb                           4                       # Nu
 system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
 system.cpu1.itb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.itb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                    1191                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries                    1190                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults                     2046                       # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults                     2956                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses                11354057                       # ITB inst accesses
-system.cpu1.itb.hits                         11349850                       # DTB hits
-system.cpu1.itb.misses                           4207                       # DTB misses
-system.cpu1.itb.accesses                     11354057                       # DTB accesses
-system.cpu1.numCycles                       149527233                       # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses                11210979                       # ITB inst accesses
+system.cpu1.itb.hits                         11206823                       # DTB hits
+system.cpu1.itb.misses                           4156                       # DTB misses
+system.cpu1.itb.accesses                     11210979                       # DTB accesses
+system.cpu1.numCycles                       147611080                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                   31976765                       # Number of instructions committed
-system.cpu1.committedOps                     40324598                       # Number of ops (including micro ops) committed
-system.cpu1.discardedOps                      1783017                       # Number of ops (including micro ops) which were discarded before commit
-system.cpu1.numFetchSuspends                    39969                       # Number of times Execute suspended instruction fetching
-system.cpu1.quiesceCycles                  2144960974                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.cpi                              4.676121                       # CPI: cycles per instruction
-system.cpu1.ipc                              0.213852                       # IPC: instructions per cycle
+system.cpu1.committedInsts                   31966977                       # Number of instructions committed
+system.cpu1.committedOps                     38077351                       # Number of ops (including micro ops) committed
+system.cpu1.discardedOps                      1608279                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu1.numFetchSuspends                    39953                       # Number of times Execute suspended instruction fetching
+system.cpu1.quiesceCycles                  2144312243                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.cpi                              4.617611                       # CPI: cycles per instruction
+system.cpu1.ipc                              0.216562                       # IPC: instructions per cycle
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                   40497                       # number of quiesce instructions executed
-system.cpu1.tickCycles                      120083069                       # Number of cycles that the object actually ticked
-system.cpu1.idleCycles                       29444164                       # Total number of cycles that the object has spent stopped
-system.cpu1.icache.tags.replacements           800234                       # number of replacements
-system.cpu1.icache.tags.tagsinuse          480.617194                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs           10546899                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs           800746                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs            13.171341                       # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle      82063984250                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst   480.617194                       # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst     0.938705                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total     0.938705                       # Average percentage of cache occupancy
+system.cpu1.kern.inst.quiesce                   40481                       # number of quiesce instructions executed
+system.cpu1.tickCycles                      117794277                       # Number of cycles that the object actually ticked
+system.cpu1.idleCycles                       29816803                       # Total number of cycles that the object has spent stopped
+system.cpu1.icache.tags.replacements           791766                       # number of replacements
+system.cpu1.icache.tags.tagsinuse          480.612166                       # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs           10411414                       # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs           792278                       # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs            13.141112                       # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle      82581306250                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tags.occ_blocks::cpu1.inst   480.612166                       # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst     0.938696                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total     0.938696                       # Average percentage of cache occupancy
 system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::0          114                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::1          196                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::2          194                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::0          119                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::1          186                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::2          199                       # Occupied blocks per task id
 system.cpu1.icache.tags.age_task_id_blocks_1024::3            8                       # Occupied blocks per task id
 system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses         12148392                       # Number of tag accesses
-system.cpu1.icache.tags.data_accesses        12148392                       # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst     10546899                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total       10546899                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst     10546899                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total        10546899                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst     10546899                       # number of overall hits
-system.cpu1.icache.overall_hits::total       10546899                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst       800747                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total       800747                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst       800747                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total        800747                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst       800747                       # number of overall misses
-system.cpu1.icache.overall_misses::total       800747                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst  10721128674                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total  10721128674                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst  10721128674                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total  10721128674                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst  10721128674                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total  10721128674                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst     11347646                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total     11347646                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst     11347646                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total     11347646                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst     11347646                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total     11347646                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.070565                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.070565                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.070565                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.070565                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.070565                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.070565                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13388.908949                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 13388.908949                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13388.908949                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 13388.908949                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13388.908949                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 13388.908949                       # average overall miss latency
+system.cpu1.icache.tags.tag_accesses         11995971                       # Number of tag accesses
+system.cpu1.icache.tags.data_accesses        11995971                       # Number of data accesses
+system.cpu1.icache.ReadReq_hits::cpu1.inst     10411414                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total       10411414                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst     10411414                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total        10411414                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst     10411414                       # number of overall hits
+system.cpu1.icache.overall_hits::total       10411414                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst       792279                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total       792279                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst       792279                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total        792279                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst       792279                       # number of overall misses
+system.cpu1.icache.overall_misses::total       792279                       # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst  10606605688                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total  10606605688                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst  10606605688                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total  10606605688                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst  10606605688                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total  10606605688                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst     11203693                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total     11203693                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst     11203693                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total     11203693                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst     11203693                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total     11203693                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.070716                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.070716                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.070716                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.070716                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.070716                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.070716                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13387.462861                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 13387.462861                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13387.462861                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 13387.462861                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13387.462861                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 13387.462861                       # average overall miss latency
 system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1396,128 +1396,128 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       800747                       # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total       800747                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst       800747                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total       800747                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst       800747                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total       800747                       # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   9117705326                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total   9117705326                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   9117705326                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total   9117705326                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   9117705326                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total   9117705326                       # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      5654750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      5654750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      5654750                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::total      5654750                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.070565                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.070565                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.070565                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.070565                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.070565                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.070565                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11386.499514                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11386.499514                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11386.499514                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 11386.499514                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11386.499514                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 11386.499514                       # average overall mshr miss latency
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       792279                       # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total       792279                       # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst       792279                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total       792279                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst       792279                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total       792279                       # number of overall MSHR misses
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   9020137312                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total   9020137312                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   9020137312                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total   9020137312                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   9020137312                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total   9020137312                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      5771250                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      5771250                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      5771250                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::total      5771250                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.070716                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.070716                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.070716                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total     0.070716                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.070716                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total     0.070716                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11385.051619                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11385.051619                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11385.051619                       # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total 11385.051619                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11385.051619                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total 11385.051619                       # average overall mshr miss latency
 system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
 system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.dcache.tags.replacements           301108                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse          446.775625                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs           11731236                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs           301620                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs            38.894092                       # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle      76702840250                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.inst   446.775625                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.inst     0.872609                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total     0.872609                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.replacements           300206                       # number of replacements
+system.cpu1.dcache.tags.tagsinuse          447.094079                       # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs           10899911                       # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs           300718                       # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs            36.246287                       # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle      76416861250                       # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.occ_blocks::cpu1.inst   447.094079                       # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.inst     0.873231                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total     0.873231                       # Average percentage of cache occupancy
 system.cpu1.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::0          106                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::1          344                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2           61                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::0          116                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::1          350                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2           44                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
 system.cpu1.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses         49070289                       # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses        49070289                       # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.inst      7114972                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total        7114972                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.inst      4425981                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total       4425981                       # number of WriteReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.inst        78462                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total        78462                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.inst        79072                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total        79072                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.inst     11540953                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total        11540953                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.inst     11540953                       # number of overall hits
-system.cpu1.dcache.overall_hits::total       11540953                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.inst       243175                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total       243175                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.inst       224036                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total       224036                       # number of WriteReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.inst        10782                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total        10782                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.inst        10124                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total        10124                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.inst       467211                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total        467211                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.inst       467211                       # number of overall misses
-system.cpu1.dcache.overall_misses::total       467211                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.inst   3616409978                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total   3616409978                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.inst   8727689439                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total   8727689439                       # number of WriteReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.inst     90341500                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total     90341500                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.inst     50520310                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total     50520310                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.inst  12344099417                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total  12344099417                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.inst  12344099417                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total  12344099417                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.inst      7358147                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total      7358147                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.inst      4650017                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total      4650017                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.inst        89244                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total        89244                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.inst        89196                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total        89196                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.inst     12008164                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total     12008164                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.inst     12008164                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total     12008164                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.inst     0.033048                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.033048                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.inst     0.048180                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.048180                       # miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.inst     0.120815                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.120815                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.inst     0.113503                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total     0.113503                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.inst     0.038908                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.038908                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.inst     0.038908                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.038908                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.inst 14871.635563                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 14871.635563                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.inst 38956.638393                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 38956.638393                       # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.inst  8378.918568                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total  8378.918568                       # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.inst  4990.153102                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total  4990.153102                       # average StoreCondReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.inst 26420.823604                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 26420.823604                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.inst 26420.823604                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 26420.823604                       # average overall miss latency
+system.cpu1.dcache.tags.tag_accesses         45736548                       # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses        45736548                       # Number of data accesses
+system.cpu1.dcache.ReadReq_hits::cpu1.inst      6288103                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total        6288103                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.inst      4421998                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total       4421998                       # number of WriteReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.inst        78443                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total        78443                       # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.inst        79055                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total        79055                       # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.inst     10710101                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total        10710101                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.inst     10710101                       # number of overall hits
+system.cpu1.dcache.overall_hits::total       10710101                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.inst       241320                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total       241320                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.inst       223635                       # number of WriteReq misses
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+system.cpu1.dcache.LoadLockedReq_misses::cpu1.inst        10750                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total        10750                       # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.inst        10087                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total        10087                       # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.inst       464955                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total        464955                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.inst       464955                       # number of overall misses
+system.cpu1.dcache.overall_misses::total       464955                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.inst   3586794993                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total   3586794993                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.inst   8773828993                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total   8773828993                       # number of WriteReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.inst     90116500                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total     90116500                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.inst     50277799                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total     50277799                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.inst  12360623986                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total  12360623986                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.inst  12360623986                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total  12360623986                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.inst      6529423                       # number of ReadReq accesses(hits+misses)
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+system.cpu1.dcache.LoadLockedReq_accesses::total        89193                       # number of LoadLockedReq accesses(hits+misses)
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+system.cpu1.dcache.StoreCondReq_accesses::total        89142                       # number of StoreCondReq accesses(hits+misses)
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+system.cpu1.dcache.overall_accesses::cpu1.inst     11175056                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total     11175056                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.inst     0.036959                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.036959                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.inst     0.048139                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.048139                       # miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.inst     0.120525                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.120525                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.inst     0.113157                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total     0.113157                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.inst     0.041607                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.041607                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.inst     0.041607                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.041607                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.inst 14863.231365                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 14863.231365                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.inst 39232.807892                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 39232.807892                       # average WriteReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.inst  8382.930233                       # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total  8382.930233                       # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.inst  4984.415485                       # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total  4984.415485                       # average StoreCondReq miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.inst 26584.559766                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 26584.559766                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.inst 26584.559766                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 26584.559766                       # average overall miss latency
 system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1526,72 +1526,72 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks       269177                       # number of writebacks
-system.cpu1.dcache.writebacks::total           269177                       # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.inst        37509                       # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total        37509                       # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.inst        98167                       # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total        98167                       # number of WriteReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.inst           30                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::total           30                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.inst       135676                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total       135676                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.inst       135676                       # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total       135676                       # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.inst       205666                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total       205666                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.inst       125869                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total       125869                       # number of WriteReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.inst        10752                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total        10752                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.inst        10124                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total        10124                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.inst       331535                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total       331535                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.inst       331535                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total       331535                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.inst   2422782037                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total   2422782037                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.inst   4131508096                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total   4131508096                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.inst     68345000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     68345000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.inst     30271690                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total     30271690                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.inst   6554290133                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total   6554290133                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.inst   6554290133                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total   6554290133                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.inst  11992419500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total  11992419500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.inst  24672512707                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total  24672512707                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.inst  36664932207                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total  36664932207                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.inst     0.027951                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.027951                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.inst     0.027069                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.027069                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.inst     0.120479                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.120479                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.inst     0.113503                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.113503                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.inst     0.027609                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.027609                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.inst     0.027609                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.027609                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11780.177749                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11780.177749                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.inst 32823.873202                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 32823.873202                       # average WriteReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.inst  6356.491815                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total  6356.491815                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.inst  2990.091861                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total  2990.091861                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.inst 19769.526997                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19769.526997                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.inst 19769.526997                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19769.526997                       # average overall mshr miss latency
+system.cpu1.dcache.writebacks::writebacks       268002                       # number of writebacks
+system.cpu1.dcache.writebacks::total           268002                       # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.inst        36395                       # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total        36395                       # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.inst        98109                       # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total        98109                       # number of WriteReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.inst           34                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::total           34                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.inst       134504                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total       134504                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.inst       134504                       # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total       134504                       # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.inst       204925                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total       204925                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.inst       125526                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total       125526                       # number of WriteReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.inst        10716                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total        10716                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.inst        10087                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total        10087                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.inst       330451                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total       330451                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.inst       330451                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total       330451                       # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.inst   2412502275                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total   2412502275                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.inst   4153602004                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total   4153602004                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.inst     68123500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     68123500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.inst     30103201                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total     30103201                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.inst   6566104279                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total   6566104279                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.inst   6566104279                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total   6566104279                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.inst  11993503500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total  11993503500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.inst  24672579152                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total  24672579152                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.inst  36666082652                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total  36666082652                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.inst     0.031385                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.031385                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.inst     0.027020                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.027020                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.inst     0.120144                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.120144                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.inst     0.113157                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.113157                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.inst     0.029570                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total     0.029570                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.inst     0.029570                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total     0.029570                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11772.610833                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11772.610833                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.inst 33089.575100                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 33089.575100                       # average WriteReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.inst  6357.176185                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total  6357.176185                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.inst  2984.356201                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total  2984.356201                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.inst 19870.129850                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19870.129850                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.inst 19870.129850                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19870.129850                       # average overall mshr miss latency
 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average WriteReq mshr uncacheable latency
@@ -1615,10 +1615,10 @@ system.iocache.avg_blocked_cycles::no_mshrs          nan                       #
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 721880739500                       # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 721880739500                       # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 721880739500                       # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 721880739500                       # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 722335941002                       # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 722335941002                       # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 722335941002                       # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 722335941002                       # number of overall MSHR uncacheable cycles
 system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average ReadReq mshr uncacheable latency
 system.iocache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average overall mshr uncacheable latency
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt
index 4491c3f13..4c74a9fb4 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt
@@ -1,132 +1,132 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.567677                       # Number of seconds simulated
-sim_ticks                                2567677478000                       # Number of ticks simulated
-final_tick                               2567677478000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.566439                       # Number of seconds simulated
+sim_ticks                                2566439177500                       # Number of ticks simulated
+final_tick                               2566439177500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  53140                       # Simulator instruction rate (inst/s)
-host_op_rate                                    68307                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2251849348                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 443244                       # Number of bytes of host memory used
-host_seconds                                  1140.25                       # Real time elapsed on the host
-sim_insts                                    60592948                       # Number of instructions simulated
-sim_ops                                      77887482                       # Number of ops (including micro ops) simulated
+host_inst_rate                                  73545                       # Simulator instruction rate (inst/s)
+host_op_rate                                    88536                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             3115018228                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 470576                       # Number of bytes of host memory used
+host_seconds                                   823.89                       # Real time elapsed on the host
+sim_insts                                    60593470                       # Number of instructions simulated
+sim_ops                                      72944147                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::realview.clcd    121110528                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.dtb.walker         1152                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker         1344                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.itb.walker          128                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst          10106264                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            131218072                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst      1017856                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         1017856                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      3829760                       # Number of bytes written to this memory
+system.physmem.bytes_read::cpu.inst          10079960                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            131191960                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst      1001344                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1001344                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      3811328                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu.inst        3016072                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           6845832                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           6827400                       # Number of bytes written to this memory
 system.physmem.num_reads::realview.clcd      15138816                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.dtb.walker           18                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.dtb.walker           21                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.itb.walker            2                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst             157946                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total              15296782                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           59840                       # Number of write requests responded to by this memory
+system.physmem.num_reads::cpu.inst             157525                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total              15296364                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           59552                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu.inst            754018                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               813858                       # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd        47167344                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.dtb.walker            449                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total               813570                       # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd        47190103                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.dtb.walker            524                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu.itb.walker             50                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst              3935955                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                51103798                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          396411                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             396411                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1491527                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.inst             1174630                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2666157                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1491527                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd       47167344                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker           449                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst              3927605                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                51118281                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          390169                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             390169                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1485065                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.inst             1175197                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                2660262                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1485065                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd       47190103                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker           524                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.itb.walker            50                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             5110586                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               53769956                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                      15296782                       # Number of read requests accepted
-system.physmem.writeReqs                       813858                       # Number of write requests accepted
-system.physmem.readBursts                    15296782                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     813858                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                978883904                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                    110144                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   6853696                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                 131218072                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                6845832                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                     1721                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                  706743                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs           4671                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0              955926                       # Per bank write bursts
-system.physmem.perBankRdBursts::1              955615                       # Per bank write bursts
-system.physmem.perBankRdBursts::2              955732                       # Per bank write bursts
-system.physmem.perBankRdBursts::3              955955                       # Per bank write bursts
-system.physmem.perBankRdBursts::4              957630                       # Per bank write bursts
-system.physmem.perBankRdBursts::5              955653                       # Per bank write bursts
-system.physmem.perBankRdBursts::6              955569                       # Per bank write bursts
-system.physmem.perBankRdBursts::7              955430                       # Per bank write bursts
-system.physmem.perBankRdBursts::8              956341                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              955977                       # Per bank write bursts
-system.physmem.perBankRdBursts::10             955547                       # Per bank write bursts
-system.physmem.perBankRdBursts::11             955151                       # Per bank write bursts
-system.physmem.perBankRdBursts::12             956306                       # Per bank write bursts
-system.physmem.perBankRdBursts::13             956026                       # Per bank write bursts
-system.physmem.perBankRdBursts::14             956165                       # Per bank write bursts
-system.physmem.perBankRdBursts::15             956038                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                6624                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                6445                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                6544                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                6594                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                6491                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                6747                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                6783                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                6690                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                7075                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                6811                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               6482                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               6150                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               7106                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               6684                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               7011                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               6852                       # Per bank write bursts
+system.physmem.bw_total::cpu.inst             5102802                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               53778543                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                      15296364                       # Number of read requests accepted
+system.physmem.writeReqs                       813570                       # Number of write requests accepted
+system.physmem.readBursts                    15296364                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     813570                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                978868736                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     98560                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   6836224                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                 131191960                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                6827400                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                     1540                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                  706728                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs           4670                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0              955903                       # Per bank write bursts
+system.physmem.perBankRdBursts::1              955584                       # Per bank write bursts
+system.physmem.perBankRdBursts::2              955711                       # Per bank write bursts
+system.physmem.perBankRdBursts::3              955912                       # Per bank write bursts
+system.physmem.perBankRdBursts::4              957606                       # Per bank write bursts
+system.physmem.perBankRdBursts::5              955733                       # Per bank write bursts
+system.physmem.perBankRdBursts::6              955604                       # Per bank write bursts
+system.physmem.perBankRdBursts::7              955438                       # Per bank write bursts
+system.physmem.perBankRdBursts::8              956293                       # Per bank write bursts
+system.physmem.perBankRdBursts::9              955954                       # Per bank write bursts
+system.physmem.perBankRdBursts::10             955536                       # Per bank write bursts
+system.physmem.perBankRdBursts::11             955097                       # Per bank write bursts
+system.physmem.perBankRdBursts::12             956286                       # Per bank write bursts
+system.physmem.perBankRdBursts::13             955995                       # Per bank write bursts
+system.physmem.perBankRdBursts::14             956150                       # Per bank write bursts
+system.physmem.perBankRdBursts::15             956022                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                6610                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                6419                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                6537                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                6577                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                6482                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                6744                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                6779                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                6682                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                7031                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                6794                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               6476                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               6093                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               7096                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               6664                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               6987                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               6845                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    2567675574500                       # Total gap between requests
+system.physmem.totGap                    2566437420000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::2                      38                       # Read request sizes (log2)
-system.physmem.readPktSize::3                15138816                       # Read request sizes (log2)
+system.physmem.readPktSize::2                      18                       # Read request sizes (log2)
+system.physmem.readPktSize::3                15138826                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  157928                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  157520                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                 754018                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                  59840                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                   1112326                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    958648                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                    963944                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                   1085542                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                    974308                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                   1043218                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                   2679684                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                   2578598                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                   3358182                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                    142716                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                   121801                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                   111705                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                   108393                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                    19289                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                    18414                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                    18153                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                      135                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                        4                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                        1                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                  59552                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                   1111382                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    958419                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                    963594                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                   1074014                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                    973771                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                   1037292                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                   2691805                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                   2600171                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                   3390697                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                    128159                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                   109522                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                   101552                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                    98177                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                    19262                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                    18514                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                    18294                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                      197                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                        2                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
@@ -155,25 +155,25 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     3806                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     3819                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     6193                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     6217                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     6223                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     6217                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     6218                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     6219                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     6219                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     6220                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     6221                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     6217                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     6225                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     6219                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     6217                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     6216                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     6218                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     6216                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     3800                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     3820                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     6181                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     6199                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     6202                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     6201                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     6201                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     6202                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     6203                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     6202                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     6203                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     6203                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     6206                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     6200                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     6204                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     6199                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     6201                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     6199                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
@@ -204,63 +204,64 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples      1015088                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      971.085857                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     904.509360                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     205.145024                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          22501      2.22%      2.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        22772      2.24%      4.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         8563      0.84%      5.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         2455      0.24%      5.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2778      0.27%      5.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1897      0.19%      6.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         8457      0.83%      6.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          971      0.10%      6.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151       944694     93.07%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total        1015088                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          6216                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean      2460.593951                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev    115853.550339                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-524287         6211     99.92%     99.92% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples      1014534                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      971.583959                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     905.812030                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     204.103928                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          21965      2.17%      2.17% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        22634      2.23%      4.40% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         8771      0.86%      5.26% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         2477      0.24%      5.50% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2600      0.26%      5.76% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1707      0.17%      5.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         8766      0.86%      6.79% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1031      0.10%      6.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151       944583     93.11%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total        1014534                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          6199                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean      2467.302629                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev    115861.516346                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-524287         6194     99.92%     99.92% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::524288-1.04858e+06            2      0.03%     99.95% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::1.04858e+06-1.57286e+06            2      0.03%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::8.38861e+06-8.9129e+06            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            6216                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          6216                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        17.227960                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       17.199911                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        0.974162                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16               2395     38.53%     38.53% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17                 16      0.26%     38.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18               3798     61.10%     99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19                  7      0.11%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            6216                       # Writes before turning the bus around for reads
-system.physmem.totQLat                   396370290250                       # Total ticks spent queuing
-system.physmem.totMemAccLat              683152684000                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                  76475305000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       25914.92                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            6199                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          6199                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.231166                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       17.203067                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        0.975146                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               2381     38.41%     38.41% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17                 18      0.29%     38.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18               3787     61.09%     99.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19                 12      0.19%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                  1      0.02%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            6199                       # Writes before turning the bus around for reads
+system.physmem.totQLat                   394563559000                       # Total ticks spent queuing
+system.physmem.totMemAccLat              681341509000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                  76474120000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       25797.20                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  44664.92                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         381.23                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           2.67                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       51.10                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        2.67                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  44547.20                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         381.41                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           2.66                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       51.12                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        2.66                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           3.00                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       2.98                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         6.49                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        27.85                       # Average write queue length when enqueuing
-system.physmem.readRowHits                   14297424                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     89638                       # Number of row buffer hits during writes
+system.physmem.avgRdQLen                         6.61                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        26.40                       # Average write queue length when enqueuing
+system.physmem.readRowHits                   14297661                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     89445                       # Number of row buffer hits during writes
 system.physmem.readRowHitRate                   93.48                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  83.68                       # Row buffer hit rate for writes
-system.physmem.avgGap                       159377.63                       # Average gap between requests
+system.physmem.writeRowHitRate                  83.72                       # Row buffer hit rate for writes
+system.physmem.avgGap                       159307.76                       # Average gap between requests
 system.physmem.pageHitRate                      93.41                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE     2210132306750                       # Time in different power states
-system.physmem.memoryStateTime::REF       85740200000                       # Time in different power states
+system.physmem.memoryStateTime::IDLE     2209628504250                       # Time in different power states
+system.physmem.memoryStateTime::REF       85698860000                       # Time in different power states
 system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT      271799415750                       # Time in different power states
+system.physmem.memoryStateTime::ACT      271106544500                       # Time in different power states
 system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
 system.realview.nvmem.bytes_read::cpu.inst          256                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total           256                       # Number of bytes read from this memory
@@ -274,49 +275,49 @@ system.realview.nvmem.bw_inst_read::cpu.inst          100
 system.realview.nvmem.bw_inst_read::total          100                       # Instruction read bandwidth from this memory (bytes/s)
 system.realview.nvmem.bw_total::cpu.inst          100                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::total             100                       # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput                     54704015                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq            16349240                       # Transaction distribution
-system.membus.trans_dist::ReadResp           16349240                       # Transaction distribution
+system.membus.throughput                     54713053                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq            16348871                       # Transaction distribution
+system.membus.trans_dist::ReadResp           16348871                       # Transaction distribution
 system.membus.trans_dist::WriteReq             763365                       # Transaction distribution
 system.membus.trans_dist::WriteResp            763365                       # Transaction distribution
-system.membus.trans_dist::Writeback             59840                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             4671                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp            4671                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            131634                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           131634                       # Transaction distribution
+system.membus.trans_dist::Writeback             59552                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq             4670                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp            4670                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            131585                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           131585                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave      2383068                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port            8                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         3800                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio            2                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1893150                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total      4280028                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1892024                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total      4278902                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port     30277632                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::total     30277632                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total               34557660                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total               34556534                       # Packet count per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave      2390502                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port          256                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio         7600                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio            4                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     16953376                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total     19351738                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     16908832                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total     19307194                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port    121110528                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.iocache.mem_side::total    121110528                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total           140462266                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus              140462266                       # Total data (bytes)
+system.membus.tot_pkt_size::total           140417722                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus              140417722                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy          1731218500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy          1781248000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.1                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy                6000                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             3525000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             3519500                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer4.occupancy                1500                       # Layer occupancy (ticks)
 system.membus.reqLayer4.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer6.occupancy         17560732500                       # Layer occupancy (ticks)
+system.membus.reqLayer6.occupancy         17618628000                       # Layer occupancy (ticks)
 system.membus.reqLayer6.utilization               0.7                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         4805026968                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         4827706725                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
-system.membus.respLayer2.occupancy        37408380500                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy        37448813750                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              1.5                       # Layer utilization (%)
 system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
 system.cf0.dma_read_bytes                           0                       # Number of bytes transfered via DMA reads (not PRD).
@@ -324,7 +325,7 @@ system.cf0.dma_read_txs                             0                       # Nu
 system.cf0.dma_write_full_pages                     0                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                          0                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
-system.iobus.throughput                      48098342                       # Throughput (bytes/s)
+system.iobus.throughput                      48121550                       # Throughput (bytes/s)
 system.iobus.trans_dist::ReadReq             16322172                       # Transaction distribution
 system.iobus.trans_dist::ReadResp            16322172                       # Transaction distribution
 system.iobus.trans_dist::WriteReq                8178                       # Transaction distribution
@@ -434,18 +435,18 @@ system.iobus.reqLayer25.occupancy         15138816000                       # La
 system.iobus.reqLayer25.utilization               0.6                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy          2374890000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.1                       # Layer utilization (%)
-system.iobus.respLayer1.occupancy         38224979500                       # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy         38181688250                       # Layer occupancy (ticks)
 system.iobus.respLayer1.utilization               1.5                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.branchPred.lookups                12907759                       # Number of BP lookups
-system.cpu.branchPred.condPredicted           9898849                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           1085572                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups              8888360                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                 6291175                       # Number of BTB hits
+system.cpu.branchPred.lookups                12541574                       # Number of BP lookups
+system.cpu.branchPred.condPredicted           9090690                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           1061681                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups              8536244                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                 6183587                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             70.779930                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 1515479                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect             141893                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             72.439202                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 1558068                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect             139509                       # Number of incorrect RAS predictions.
 system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -469,25 +470,25 @@ system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DT
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.read_hits                     15416418                       # DTB read hits
-system.cpu.dtb.read_misses                      42733                       # DTB read misses
-system.cpu.dtb.write_hits                    11344011                       # DTB write hits
-system.cpu.dtb.write_misses                      3796                       # DTB write misses
+system.cpu.dtb.read_hits                     13629654                       # DTB read hits
+system.cpu.dtb.read_misses                      33608                       # DTB read misses
+system.cpu.dtb.write_hits                    11376786                       # DTB write hits
+system.cpu.dtb.write_misses                      3775                       # DTB write misses
 system.cpu.dtb.flush_tlb                            2                       # Number of times complete TLB was flushed
 system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
 system.cpu.dtb.flush_tlb_mva_asid                1439                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.dtb.flush_tlb_asid                      63                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries                     3452                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults                      1264                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults                    262                       # Number of TLB faults due to prefetch
+system.cpu.dtb.flush_entries                     3449                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                      1586                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                    251                       # Number of TLB faults due to prefetch
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults                       531                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses                 15459151                       # DTB read accesses
-system.cpu.dtb.write_accesses                11347807                       # DTB write accesses
+system.cpu.dtb.perms_faults                       593                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                 13663262                       # DTB read accesses
+system.cpu.dtb.write_accesses                11380561                       # DTB write accesses
 system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.hits                          26760429                       # DTB hits
-system.cpu.dtb.misses                           46529                       # DTB misses
-system.cpu.dtb.accesses                      26806958                       # DTB accesses
+system.cpu.dtb.hits                          25006440                       # DTB hits
+system.cpu.dtb.misses                           37383                       # DTB misses
+system.cpu.dtb.accesses                      25043823                       # DTB accesses
 system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -509,8 +510,8 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.inst_hits                     23352687                       # ITB inst hits
-system.cpu.itb.inst_misses                       9286                       # ITB inst misses
+system.cpu.itb.inst_hits                     22903214                       # ITB inst hits
+system.cpu.itb.inst_misses                       9061                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.write_hits                           0                       # DTB write hits
@@ -519,84 +520,84 @@ system.cpu.itb.flush_tlb                            2                       # Nu
 system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
 system.cpu.itb.flush_tlb_mva_asid                1439                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.itb.flush_tlb_asid                      63                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries                     2392                       # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_entries                     2388                       # Number of entries that have been flushed from TLB
 system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
 system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults                      4189                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults                      5760                       # Number of TLB faults due to permissions restrictions
 system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.inst_accesses                 23361973                       # ITB inst accesses
-system.cpu.itb.hits                          23352687                       # DTB hits
-system.cpu.itb.misses                            9286                       # DTB misses
-system.cpu.itb.accesses                      23361973                       # DTB accesses
-system.cpu.numCycles                        576983411                       # number of cpu cycles simulated
+system.cpu.itb.inst_accesses                 22912275                       # ITB inst accesses
+system.cpu.itb.hits                          22903214                       # DTB hits
+system.cpu.itb.misses                            9061                       # DTB misses
+system.cpu.itb.accesses                      22912275                       # DTB accesses
+system.cpu.numCycles                        572663270                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                    60592948                       # Number of instructions committed
-system.cpu.committedOps                      77887482                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                       3584241                       # Number of ops (including micro ops) which were discarded before commit
-system.cpu.numFetchSuspends                     77491                       # Number of times Execute suspended instruction fetching
-system.cpu.quiesceCycles                   4560301069                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.cpi                               9.522287                       # CPI: cycles per instruction
-system.cpu.ipc                               0.105017                       # IPC: instructions per cycle
+system.cpu.committedInsts                    60593470                       # Number of instructions committed
+system.cpu.committedOps                      72944147                       # Number of ops (including micro ops) committed
+system.cpu.discardedOps                       3225433                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.numFetchSuspends                     77492                       # Number of times Execute suspended instruction fetching
+system.cpu.quiesceCycles                   4562060973                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.cpi                               9.450907                       # CPI: cycles per instruction
+system.cpu.ipc                               0.105810                       # IPC: instructions per cycle
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.quiesce                    82977                       # number of quiesce instructions executed
-system.cpu.tickCycles                       470832364                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                       106151047                       # Total number of cycles that the object has spent stopped
-system.cpu.icache.tags.replacements           1545254                       # number of replacements
-system.cpu.icache.tags.tagsinuse           511.467506                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            21802506                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs           1545766                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             14.104661                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle       10068892000                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   511.467506                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.998960                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.998960                       # Average percentage of cache occupancy
+system.cpu.kern.inst.quiesce                    82978                       # number of quiesce instructions executed
+system.cpu.tickCycles                       466702382                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                       105960888                       # Total number of cycles that the object has spent stopped
+system.cpu.icache.tags.replacements           1529303                       # number of replacements
+system.cpu.icache.tags.tagsinuse           511.463660                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            21367406                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs           1529815                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             13.967314                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle        9992606000                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   511.463660                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.998952                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.998952                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          119                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          206                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          186                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          125                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          196                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          190                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          24894039                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         24894039                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     21802506                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        21802506                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      21802506                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         21802506                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     21802506                       # number of overall hits
-system.cpu.icache.overall_hits::total        21802506                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst      1545767                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total       1545767                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst      1545767                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total        1545767                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst      1545767                       # number of overall misses
-system.cpu.icache.overall_misses::total       1545767                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  20898816329                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  20898816329                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  20898816329                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  20898816329                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  20898816329                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  20898816329                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     23348273                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     23348273                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     23348273                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     23348273                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     23348273                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     23348273                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.066205                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.066205                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.066205                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.066205                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.066205                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.066205                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13520.030075                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13520.030075                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13520.030075                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13520.030075                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13520.030075                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13520.030075                       # average overall miss latency
+system.cpu.icache.tags.tag_accesses          24427037                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         24427037                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     21367406                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        21367406                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      21367406                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         21367406                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     21367406                       # number of overall hits
+system.cpu.icache.overall_hits::total        21367406                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst      1529816                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total       1529816                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst      1529816                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total        1529816                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst      1529816                       # number of overall misses
+system.cpu.icache.overall_misses::total       1529816                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  20677210137                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  20677210137                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  20677210137                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  20677210137                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  20677210137                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  20677210137                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     22897222                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     22897222                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     22897222                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     22897222                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     22897222                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     22897222                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.066812                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.066812                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.066812                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.066812                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.066812                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.066812                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13516.141900                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13516.141900                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13516.141900                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13516.141900                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13516.141900                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13516.141900                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -605,198 +606,198 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1545767                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total      1545767                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst      1545767                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total      1545767                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst      1545767                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total      1545767                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  17801487671                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  17801487671                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst  17801487671                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total  17801487671                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst  17801487671                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total  17801487671                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst    172412750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::total    172412750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst    172412750                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::total    172412750                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.066205                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.066205                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.066205                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.066205                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.066205                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.066205                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11516.281348                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11516.281348                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11516.281348                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 11516.281348                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11516.281348                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 11516.281348                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1529816                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total      1529816                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst      1529816                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total      1529816                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst      1529816                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total      1529816                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  17611902863                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total  17611902863                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst  17611902863                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total  17611902863                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst  17611902863                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total  17611902863                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst    172141250                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_uncacheable_latency::total    172141250                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst    172141250                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_latency::total    172141250                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.066812                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.066812                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.066812                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.066812                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.066812                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.066812                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11512.432125                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11512.432125                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11512.432125                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 11512.432125                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11512.432125                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 11512.432125                       # average overall mshr miss latency
 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.throughput                71776562                       # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq        3214470                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       3214469                       # Transaction distribution
+system.cpu.toL2Bus.throughput                71285625                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq        3182019                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       3182018                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteReq        763365                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteResp       763365                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback       602969                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq         2961                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp         2961                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       247546                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       247546                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      3094256                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      5780457                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        29847                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       126652                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           9031212                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     98954304                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     84855034                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        45620                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       214364                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total      184069322                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus         184069322                       # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus       229740                       # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy     3400466435                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.trans_dist::Writeback       600964                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq         2972                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp         2972                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       247467                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       247467                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      3062398                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      5774016                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        28971                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       100817                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           8966202                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     97936512                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     84584698                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        43908                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       166616                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total      182731734                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus         182731734                       # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus       218488                       # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy     3381194945                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy    2325579079                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy    2301585887                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    2551211790                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    2547997212                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy      18447489                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.occupancy      18000487                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy      73062749                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy      59164999                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.cpu.l2cache.tags.replacements            65493                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        51631.050557                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            2439202                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           130882                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            18.636650                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle     2525290748000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 36364.368368                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker    13.573566                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.replacements            65085                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        51558.734735                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            2407104                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           130473                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            18.449058                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle     2524856942500                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 36497.819876                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker    14.059887                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.000576                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 15253.108047                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.554876                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000207                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 15046.854396                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.556913                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000215                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000000                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.232744                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.787827                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1023           10                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        65379                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1023::4           10                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           30                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1           80                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2430                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         6701                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        56138                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1023     0.000153                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.997604                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         23227461                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        23227461                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker        53573                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.itb.walker        11403                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.inst      1910560                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        1975536                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks       602969                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total       602969                       # number of Writeback hits
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.229597                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.786724                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1023           14                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        65374                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1023::4           14                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           28                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1           84                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2560                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         6585                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        56117                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1023     0.000214                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.997528                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         22967155                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        22967155                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker        41633                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.itb.walker        10975                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.inst      1892880                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total        1945488                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks       600964                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total       600964                       # number of Writeback hits
 system.cpu.l2cache.UpgradeReq_hits::cpu.inst           25                       # number of UpgradeReq hits
 system.cpu.l2cache.UpgradeReq_hits::total           25                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.inst       114177                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       114177                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.dtb.walker        53573                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.itb.walker        11403                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.inst      2024737                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         2089713                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.dtb.walker        53573                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.itb.walker        11403                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.inst      2024737                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        2089713                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker           18                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_hits::cpu.inst       114159                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       114159                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.dtb.walker        41633                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.itb.walker        10975                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.inst      2007039                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         2059647                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.dtb.walker        41633                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.itb.walker        10975                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.inst      2007039                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        2059647                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker           21                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_misses::cpu.itb.walker            2                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.inst        24020                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total        24040                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.inst         2936                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total         2936                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.inst       133369                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       133369                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.dtb.walker           18                       # number of demand (read+write) misses
+system.cpu.l2cache.ReadReq_misses::cpu.inst        23661                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total        23684                       # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.inst         2947                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total         2947                       # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.inst       133308                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       133308                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.dtb.walker           21                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::cpu.itb.walker            2                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.inst       157389                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        157409                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.dtb.walker           18                       # number of overall misses
+system.cpu.l2cache.demand_misses::cpu.inst       156969                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        156992                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.dtb.walker           21                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.itb.walker            2                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.inst       157389                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       157409                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker      1388250                       # number of ReadReq miss cycles
+system.cpu.l2cache.overall_misses::cpu.inst       156969                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       156992                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker      1631500                       # number of ReadReq miss cycles
 system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker       149500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst   1729894000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total   1731431750                       # number of ReadReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.inst       394983                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total       394983                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst   9208617265                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   9208617265                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker      1388250                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst   1700660750                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total   1702441750                       # number of ReadReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::cpu.inst       347985                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::total       347985                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst   9353977027                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   9353977027                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker      1631500                       # number of demand (read+write) miss cycles
 system.cpu.l2cache.demand_miss_latency::cpu.itb.walker       149500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst  10938511265                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  10940049015                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker      1388250                       # number of overall miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst  11054637777                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  11056418777                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker      1631500                       # number of overall miss cycles
 system.cpu.l2cache.overall_miss_latency::cpu.itb.walker       149500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst  10938511265                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  10940049015                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker        53591                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker        11405                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.inst      1934580                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total      1999576                       # number of ReadReq accesses(hits+misses)
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-system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.000336                       # miss rate for ReadReq accesses
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-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.991557                       # miss rate for UpgradeReq accesses
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-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker        77125                       # average ReadReq miss latency
+system.cpu.l2cache.overall_miss_latency::cpu.inst  11054637777                       # number of overall miss cycles
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 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker        74750                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72018.900916                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 72022.951331                       # average ReadReq miss latency
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-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total   134.530995                       # average UpgradeReq miss latency
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-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69046.159640                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker        77125                       # average overall miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71876.114704                       # average ReadReq miss latency
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+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70168.159653                       # average ReadExReq miss latency
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 system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker        74750                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69499.846018                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 69500.784676                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker        77125                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70425.611280                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 70426.638154                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 77690.476190                       # average overall miss latency
 system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker        74750                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69499.846018                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 69500.784676                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70425.611280                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 70426.638154                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -805,84 +806,84 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        59840                       # number of writebacks
-system.cpu.l2cache.writebacks::total            59840                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst           70                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total           70                       # number of ReadReq MSHR hits
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-system.cpu.l2cache.demand_mshr_hits::total           70                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst           70                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total           70                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker           18                       # number of ReadReq MSHR misses
+system.cpu.l2cache.writebacks::writebacks        59552                       # number of writebacks
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 system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker            2                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        23950                       # number of ReadReq MSHR misses
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 system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            2                       # number of demand (read+write) MSHR misses
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 system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            2                       # number of overall MSHR misses
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 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker       125000                       # number of ReadReq MSHR miss cycles
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 system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       125000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   8961241985                       # number of demand (read+write) MSHR miss cycles
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 system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       125000                       # number of overall MSHR miss cycles
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-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167312402000                       # number of ReadReq MSHR uncacheable cycles
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-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000336                       # mshr miss rate for ReadReq accesses
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-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.012380                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.011988                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.inst     0.991557                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.991557                       # mshr miss rate for UpgradeReq accesses
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-system.cpu.l2cache.overall_mshr_miss_rate::total     0.070018                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 64736.111111                       # average ReadReq mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   9056055223                       # number of overall MSHR miss cycles
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+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000504                       # mshr miss rate for ReadReq accesses
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+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000504                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000182                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.072504                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.070793                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000504                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000182                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.072504                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.070793                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 65238.095238                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker        62500                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59520.365344                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59524.530663                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.inst 10001.340599                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001.340599                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 56502.854749                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56502.854749                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 64736.111111                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59377.532638                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59383.008681                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.inst 10001.339328                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001.339328                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 57425.064310                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57425.064310                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 65238.095238                       # average overall mshr miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker        62500                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56962.235871                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56963.195616                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 64736.111111                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57718.643869                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57719.711088                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 65238.095238                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker        62500                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56962.235871                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56963.195616                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57718.643869                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57719.711088                       # average overall mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average WriteReq mshr uncacheable latency
@@ -890,86 +891,86 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements            637780                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.959208                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            23638258                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs            638292                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             37.033612                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         227414250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.inst   511.959208                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.replacements            635561                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.959259                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            21828853                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            636073                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             34.318157                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle         227074250                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.inst   511.959259                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.inst     0.999920                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.999920                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          115                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          342                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2           55                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          113                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          343                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           56                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          98967232                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         98967232                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.inst     13401610                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        13401610                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.inst      9749262                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        9749262                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.inst       236772                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       236772                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.inst       247602                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total       247602                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.inst      23150872                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         23150872                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.inst     23150872                       # number of overall hits
-system.cpu.dcache.overall_hits::total        23150872                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.inst       462868                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        462868                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.inst       473290                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       473290                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.inst        10831                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total        10831                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.inst       936158                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total         936158                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.inst       936158                       # number of overall misses
-system.cpu.dcache.overall_misses::total        936158                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.inst   7014286436                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total   7014286436                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.inst  21912161323                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  21912161323                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.inst    150765000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total    150765000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.inst  28926447759                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  28926447759                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.inst  28926447759                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  28926447759                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.inst     13864478                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     13864478                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.inst     10222552                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total     10222552                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.inst       247603                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total       247603                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.inst       247602                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total       247602                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.inst     24087030                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     24087030                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.inst     24087030                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     24087030                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.inst     0.033385                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.033385                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.inst     0.046299                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.046299                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.inst     0.043743                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.043743                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.inst     0.038866                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.038866                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.inst     0.038866                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.038866                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 15153.967083                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 15153.967083                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 46297.537077                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 46297.537077                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.inst 13919.767335                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13919.767335                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.inst 30899.108654                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 30899.108654                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.inst 30899.108654                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 30899.108654                       # average overall miss latency
+system.cpu.dcache.tags.tag_accesses          91724261                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         91724261                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.inst     11595405                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        11595405                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.inst      9746069                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        9746069                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.inst       236744                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total       236744                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.inst       247613                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total       247613                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.inst      21341474                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         21341474                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.inst     21341474                       # number of overall hits
+system.cpu.dcache.overall_hits::total        21341474                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.inst       458732                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        458732                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.inst       476614                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       476614                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.inst        10870                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total        10870                       # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.inst       935346                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total         935346                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.inst       935346                       # number of overall misses
+system.cpu.dcache.overall_misses::total        935346                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.inst   6943170934                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total   6943170934                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.inst  22231593506                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  22231593506                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.inst    151835000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total    151835000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.inst  29174764440                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  29174764440                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.inst  29174764440                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  29174764440                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.inst     12054137                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     12054137                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.inst     10222683                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total     10222683                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.inst       247614                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total       247614                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.inst       247613                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total       247613                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.inst     22276820                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     22276820                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.inst     22276820                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     22276820                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.inst     0.038056                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.038056                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.inst     0.046623                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.046623                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.inst     0.043899                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.043899                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.inst     0.041987                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.041987                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.inst     0.041987                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.041987                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 15135.571388                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 15135.571388                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 46644.860424                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 46644.860424                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.inst 13968.261270                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13968.261270                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.inst 31191.414129                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 31191.414129                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.inst 31191.414129                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 31191.414129                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -978,64 +979,64 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       602969                       # number of writebacks
-system.cpu.dcache.writebacks::total            602969                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.inst        82884                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total        82884                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.inst       222784                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       222784                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.inst           68                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total           68                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.inst       305668                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       305668                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.inst       305668                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       305668                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.inst       379984                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       379984                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.inst       250506                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       250506                       # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.inst        10763                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total        10763                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.inst       630490                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       630490                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.inst       630490                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       630490                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst   4859150309                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   4859150309                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst  10668108512                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  10668108512                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.inst    128265000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    128265000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.inst  15527258821                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  15527258821                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.inst  15527258821                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  15527258821                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.inst 182582279000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182582279000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.inst  26058245639                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total  26058245639                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.inst 208640524639                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total 208640524639                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst     0.027407                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.027407                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst     0.024505                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.024505                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.inst     0.043469                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.043469                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.inst     0.026175                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.026175                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.inst     0.026175                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.026175                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 12787.776088                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12787.776088                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 42586.239499                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42586.239499                       # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.inst 11917.216389                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11917.216389                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 24627.288016                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 24627.288016                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 24627.288016                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 24627.288016                       # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks       600964                       # number of writebacks
+system.cpu.dcache.writebacks::total            600964                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.inst        80923                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total        80923                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.inst       226176                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       226176                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.inst           72                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total           72                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.inst       307099                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       307099                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.inst       307099                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       307099                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.inst       377809                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       377809                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.inst       250438                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       250438                       # number of WriteReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.inst        10798                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total        10798                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.inst       628247                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       628247                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.inst       628247                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       628247                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst   4823958811                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   4823958811                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst  10813361832                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  10813361832                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.inst    129211000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    129211000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.inst  15637320643                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  15637320643                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.inst  15637320643                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  15637320643                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.inst 182632094250                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182632094250                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.inst  26058171145                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total  26058171145                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.inst 208690265395                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total 208690265395                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst     0.031343                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.031343                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst     0.024498                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.024498                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.inst     0.043608                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.043608                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.inst     0.028202                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.028202                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.inst     0.028202                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.028202                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 12768.247477                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12768.247477                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 43177.799823                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43177.799823                       # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.inst 11966.197444                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11966.197444                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 24890.402410                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 24890.402410                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 24890.402410                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 24890.402410                       # average overall mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average WriteReq mshr uncacheable latency
@@ -1059,10 +1060,10 @@ system.iocache.avg_blocked_cycles::no_mshrs          nan                       #
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1738541884500                       # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1738541884500                       # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1738541884500                       # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1738541884500                       # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1736623648250                       # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1736623648250                       # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1736623648250                       # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1736623648250                       # number of overall MSHR uncacheable cycles
 system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average ReadReq mshr uncacheable latency
 system.iocache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average overall mshr uncacheable latency
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt
index 76ba3533e..05396d247 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt
@@ -1,149 +1,149 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.525889                       # Number of seconds simulated
-sim_ticks                                2525888859000                       # Number of ticks simulated
-final_tick                               2525888859000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.542203                       # Number of seconds simulated
+sim_ticks                                2542202956000                       # Number of ticks simulated
+final_tick                               2542202956000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  55568                       # Simulator instruction rate (inst/s)
-host_op_rate                                    71500                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2327295647                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 420424                       # Number of bytes of host memory used
-host_seconds                                  1085.33                       # Real time elapsed on the host
-sim_insts                                    60309513                       # Number of instructions simulated
-sim_ops                                      77601128                       # Number of ops (including micro ops) simulated
+host_inst_rate                                  40853                       # Simulator instruction rate (inst/s)
+host_op_rate                                    49218                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1721973071                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 411692                       # Number of bytes of host memory used
+host_seconds                                  1476.33                       # Real time elapsed on the host
+sim_insts                                    60311945                       # Number of instructions simulated
+sim_ops                                      72661478                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.realview.nvmem.bytes_read::cpu.inst           64                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total            64                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu.inst           64                       # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total           64                       # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu.inst            1                       # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total              1                       # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu.inst            25                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total               25                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu.inst           25                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total           25                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu.inst           25                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total              25                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bytes_read::realview.clcd    119537664                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.dtb.walker         3072                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker           64                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst            797248                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           9094168                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            129432216                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       797248                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          797248                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      3785024                       # Number of bytes written to this memory
+system.realview.nvmem.bytes_read::cpu.inst           48                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total            48                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu.inst           48                       # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total           48                       # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu.inst            3                       # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total              3                       # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu.inst            19                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total               19                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu.inst           19                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total           19                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu.inst           19                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total              19                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::realview.clcd    121110528                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker          640                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker          192                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst            798576                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           9072728                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            130982664                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       798576                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          798576                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      3743232                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu.data        3016072                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           6801096                       # Number of bytes written to this memory
-system.physmem.num_reads::realview.clcd      14942208                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.dtb.walker           48                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker            1                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst              12457                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             142132                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total              15096846                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           59141                       # Number of write requests responded to by this memory
+system.physmem.bytes_written::total           6759304                       # Number of bytes written to this memory
+system.physmem.num_reads::realview.clcd      15138816                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.dtb.walker           10                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker            3                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst              14991                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             141787                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total              15295607                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           58488                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu.data            754018                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               813159                       # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd        47324990                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.dtb.walker           1216                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker             25                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               315631                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              3600383                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                51242245                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          315631                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             315631                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1498492                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data             1194064                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2692556                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1498492                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd       47324990                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker          1216                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker            25                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              315631                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             4794447                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               53934801                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                      15096846                       # Number of read requests accepted
-system.physmem.writeReqs                       813159                       # Number of write requests accepted
-system.physmem.readBursts                    15096846                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     813159                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                961407104                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                   4791040                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   6818432                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                 129432216                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                6801096                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                    74860                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                  706594                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs           4696                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0              943526                       # Per bank write bursts
-system.physmem.perBankRdBursts::1              937990                       # Per bank write bursts
-system.physmem.perBankRdBursts::2              937469                       # Per bank write bursts
-system.physmem.perBankRdBursts::3              937431                       # Per bank write bursts
-system.physmem.perBankRdBursts::4              943079                       # Per bank write bursts
-system.physmem.perBankRdBursts::5              938170                       # Per bank write bursts
-system.physmem.perBankRdBursts::6              937203                       # Per bank write bursts
-system.physmem.perBankRdBursts::7              936910                       # Per bank write bursts
-system.physmem.perBankRdBursts::8              943866                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              938107                       # Per bank write bursts
-system.physmem.perBankRdBursts::10             936563                       # Per bank write bursts
-system.physmem.perBankRdBursts::11             936045                       # Per bank write bursts
-system.physmem.perBankRdBursts::12             943886                       # Per bank write bursts
-system.physmem.perBankRdBursts::13             937531                       # Per bank write bursts
-system.physmem.perBankRdBursts::14             937186                       # Per bank write bursts
-system.physmem.perBankRdBursts::15             937024                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                6617                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                6376                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                6529                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                6558                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                6459                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                6705                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                6711                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                6649                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                7036                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                6794                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               6454                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               6111                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               7073                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               6679                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               6963                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               6824                       # Per bank write bursts
+system.physmem.num_writes::total               812506                       # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd        47639992                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.dtb.walker            252                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker             76                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               314128                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              3568845                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                51523292                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          314128                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             314128                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1472436                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data             1186401                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                2658837                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1472436                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd       47639992                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker           252                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker            76                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              314128                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             4755246                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               54182129                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                      15295607                       # Number of read requests accepted
+system.physmem.writeReqs                       812506                       # Number of write requests accepted
+system.physmem.readBursts                    15295607                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     812506                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                976934144                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                   1984704                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   6778304                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                 130982664                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                6759304                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                    31011                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                  706576                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs           4612                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0              955786                       # Per bank write bursts
+system.physmem.perBankRdBursts::1              955478                       # Per bank write bursts
+system.physmem.perBankRdBursts::2              953003                       # Per bank write bursts
+system.physmem.perBankRdBursts::3              951059                       # Per bank write bursts
+system.physmem.perBankRdBursts::4              958601                       # Per bank write bursts
+system.physmem.perBankRdBursts::5              955602                       # Per bank write bursts
+system.physmem.perBankRdBursts::6              952653                       # Per bank write bursts
+system.physmem.perBankRdBursts::7              950407                       # Per bank write bursts
+system.physmem.perBankRdBursts::8              956154                       # Per bank write bursts
+system.physmem.perBankRdBursts::9              955874                       # Per bank write bursts
+system.physmem.perBankRdBursts::10             952889                       # Per bank write bursts
+system.physmem.perBankRdBursts::11             950148                       # Per bank write bursts
+system.physmem.perBankRdBursts::12             956166                       # Per bank write bursts
+system.physmem.perBankRdBursts::13             955918                       # Per bank write bursts
+system.physmem.perBankRdBursts::14             953918                       # Per bank write bursts
+system.physmem.perBankRdBursts::15             950940                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                6546                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                6352                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                6488                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                6518                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                6421                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                6701                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                6665                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                6611                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                6966                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                6759                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               6421                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               6055                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               7037                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               6645                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               6920                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               6806                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    2525887732500                       # Total gap between requests
+system.physmem.totGap                    2542201638000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::2                      38                       # Read request sizes (log2)
-system.physmem.readPktSize::3                14942208                       # Read request sizes (log2)
-system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
+system.physmem.readPktSize::2                      18                       # Read request sizes (log2)
+system.physmem.readPktSize::3                15138826                       # Read request sizes (log2)
+system.physmem.readPktSize::4                    3351                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  154600                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  153412                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                 754018                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                  59141                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                   1057329                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    995712                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                    953847                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                   1057444                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                    956989                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                   1015779                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                   2635918                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                   2545995                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                   3318157                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                    125455                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                   108163                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                    99319                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                    95398                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                    19431                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                    18601                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                    18316                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                      110                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                       12                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                        6                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                        5                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                  58488                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                   1110293                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    964892                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                    965548                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                   1076032                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                    973735                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                   1036027                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                   2680967                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                   2587988                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                   3368391                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                    128855                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                   111642                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                   103064                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                    98734                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                    20085                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                    19255                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                    18985                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                       85                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                       10                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                        5                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                        3                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
@@ -171,28 +171,28 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     2592                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     2806                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     4314                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     6296                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     6465                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     6394                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     6388                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     6736                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     6476                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     6428                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     6463                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     6391                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     6379                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     6746                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     6351                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     6353                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     6486                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     6262                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      124                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                       66                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                       31                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                        3                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     2635                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     2946                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     5311                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     6283                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     6365                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     6331                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     6319                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     6592                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     6454                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     6382                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     6354                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     6272                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     6263                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     6280                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     6248                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     6241                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     6236                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     6213                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                       87                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                       62                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                       37                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                        4                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
@@ -220,113 +220,113 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       995372                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      972.727318                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     907.205467                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     202.336600                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          22984      2.31%      2.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        19752      1.98%      4.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         8337      0.84%      5.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         2265      0.23%      5.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2301      0.23%      5.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1840      0.18%      5.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         8587      0.86%      6.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          978      0.10%      6.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151       928328     93.26%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         995372                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          6241                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean      2406.981894                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev    114987.414706                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-524287         6237     99.94%     99.94% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::524288-1.04858e+06            2      0.03%     99.97% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2.09715e+06-2.62144e+06            1      0.02%     99.98% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples      1010606                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      973.388688                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     909.020446                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     200.819397                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          22711      2.25%      2.25% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        19828      1.96%      4.21% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         8563      0.85%      5.06% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         2249      0.22%      5.28% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2594      0.26%      5.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1688      0.17%      5.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         8931      0.88%      6.59% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          959      0.09%      6.68% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151       943083     93.32%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total        1010606                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          6196                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean      2463.620239                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev    113702.310017                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-524287         6191     99.92%     99.92% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::524288-1.04858e+06            2      0.03%     99.95% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1.04858e+06-1.57286e+06            2      0.03%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::8.38861e+06-8.9129e+06            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            6241                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          6241                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        17.070662                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       17.017388                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        1.386394                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16               3585     57.44%     57.44% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17                 32      0.51%     57.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18               1616     25.89%     83.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19                845     13.54%     97.39% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                 54      0.87%     98.25% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21                 36      0.58%     98.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22                 33      0.53%     99.36% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23                 31      0.50%     99.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24                  9      0.14%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            6241                       # Writes before turning the bus around for reads
-system.physmem.totQLat                   389024977250                       # Total ticks spent queuing
-system.physmem.totMemAccLat              670687214750                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                  75109930000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       25897.04                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            6196                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          6196                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.093447                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       17.042337                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        1.354685                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               3441     55.54%     55.54% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17                 45      0.73%     56.26% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18               1714     27.66%     83.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19                868     14.01%     97.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                 47      0.76%     98.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                 22      0.36%     99.05% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22                 27      0.44%     99.48% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23                 21      0.34%     99.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24                 10      0.16%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::27                  1      0.02%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            6196                       # Writes before turning the bus around for reads
+system.physmem.totQLat                   395449280750                       # Total ticks spent queuing
+system.physmem.totMemAccLat              681660455750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                  76322980000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       25906.31                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  44647.04                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         380.62                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           2.70                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       51.24                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        2.69                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  44656.31                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         384.29                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           2.67                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       51.52                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        2.66                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           2.99                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       2.97                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                           3.02                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       3.00                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         6.85                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        24.12                       # Average write queue length when enqueuing
-system.physmem.readRowHits                   14042089                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     91063                       # Number of row buffer hits during writes
+system.physmem.avgRdQLen                         6.20                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        23.61                       # Average write queue length when enqueuing
+system.physmem.readRowHits                   14269193                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     90708                       # Number of row buffer hits during writes
 system.physmem.readRowHitRate                   93.48                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  85.45                       # Row buffer hit rate for writes
-system.physmem.avgGap                       158760.96                       # Average gap between requests
+system.physmem.writeRowHitRate                  85.63                       # Row buffer hit rate for writes
+system.physmem.avgGap                       157821.19                       # Average gap between requests
 system.physmem.pageHitRate                      93.42                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE     2186215098000                       # Time in different power states
-system.physmem.memoryStateTime::REF       84344780000                       # Time in different power states
+system.physmem.memoryStateTime::IDLE     2194513894000                       # Time in different power states
+system.physmem.memoryStateTime::REF       84889480000                       # Time in different power states
 system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT      255323240750                       # Time in different power states
+system.physmem.memoryStateTime::ACT      262799464750                       # Time in different power states
 system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.membus.throughput                     54884184                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq            16149487                       # Transaction distribution
-system.membus.trans_dist::ReadResp           16149487                       # Transaction distribution
-system.membus.trans_dist::WriteReq             763349                       # Transaction distribution
-system.membus.trans_dist::WriteResp            763349                       # Transaction distribution
-system.membus.trans_dist::Writeback             59141                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             4693                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq              3                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp            4696                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            131431                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           131431                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave      2383042                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port            2                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         3760                       # Packet count per connected master and slave (bytes)
+system.membus.throughput                     55125441                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq            16348039                       # Transaction distribution
+system.membus.trans_dist::ReadResp           16348039                       # Transaction distribution
+system.membus.trans_dist::WriteReq             763357                       # Transaction distribution
+system.membus.trans_dist::WriteResp            763357                       # Transaction distribution
+system.membus.trans_dist::Writeback             58488                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq             4612                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp            4612                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            131651                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           131651                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave      2383056                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port            6                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         3780                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio            2                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1885845                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total      4272651                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port     29884416                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total     29884416                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total               34157067                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave      2390450                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port           64                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio         7520                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1889330                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total      4276174                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port     30277632                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total     30277632                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total               34553806                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave      2390478                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port           48                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio         7560                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio            4                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     16695648                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total     19093686                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port    119537664                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::total    119537664                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total           138631350                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus              138631350                       # Total data (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     16631440                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total     19029530                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port    121110528                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.iocache.mem_side::total    121110528                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total           140140058                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus              140140058                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy          1486861000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy          1558440500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.1                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy                1000                       # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy                3500                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             3602500                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             3512000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer4.occupancy                1500                       # Layer occupancy (ticks)
+system.membus.reqLayer4.occupancy                1000                       # Layer occupancy (ticks)
 system.membus.reqLayer4.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer6.occupancy         17311099000                       # Layer occupancy (ticks)
+system.membus.reqLayer6.occupancy         17513415500                       # Layer occupancy (ticks)
 system.membus.reqLayer6.utilization               0.7                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         4710414902                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         4726913870                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
-system.membus.respLayer2.occupancy        36916757411                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy        37423565460                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              1.5                       # Layer utilization (%)
 system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
 system.cf0.dma_read_bytes                           0                       # Number of bytes transfered via DMA reads (not PRD).
@@ -334,15 +334,15 @@ system.cf0.dma_read_txs                             0                       # Nu
 system.cf0.dma_write_full_pages                     0                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                          0                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
-system.iobus.throughput                      48271369                       # Throughput (bytes/s)
-system.iobus.trans_dist::ReadReq             16125555                       # Transaction distribution
-system.iobus.trans_dist::ReadResp            16125555                       # Transaction distribution
-system.iobus.trans_dist::WriteReq                8174                       # Transaction distribution
-system.iobus.trans_dist::WriteResp               8174                       # Transaction distribution
+system.iobus.throughput                      48580309                       # Throughput (bytes/s)
+system.iobus.trans_dist::ReadReq             16322168                       # Transaction distribution
+system.iobus.trans_dist::ReadResp            16322168                       # Transaction distribution
+system.iobus.trans_dist::WriteReq                8176                       # Transaction distribution
+system.iobus.trans_dist::WriteResp               8176                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        30038                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio         7934                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio          516                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio         1024                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio         7940                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio          520                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio         1028                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio           36                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          746                       # Packet count per connected master and slave (bytes)
@@ -362,14 +362,14 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total      2383042                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side     29884416                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.clcd.dma::total     29884416                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                32267458                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total      2383056                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side     30277632                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.clcd.dma::total     30277632                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                32660688                       # Packet count per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio        39333                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio        15868                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio         1032                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio         2048                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio        15880                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio         1040                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio         2056                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio           72                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio          397                       # Cumulative packet size per connected master and slave (bytes)
@@ -389,18 +389,18 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::total      2390450                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side    119537664                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.realview.clcd.dma::total    119537664                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::total            121928114                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.data_through_bus               121928114                       # Total data (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::total      2390478                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side    121110528                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.realview.clcd.dma::total    121110528                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::total            123501006                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.data_through_bus               123501006                       # Total data (bytes)
 system.iobus.reqLayer0.occupancy             21111000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy              3972000                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy              3975000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy               516000                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy               520000                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy               518000                       # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy               520000                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer4.occupancy                27000                       # Layer occupancy (ticks)
 system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
@@ -440,22 +440,22 @@ system.iobus.reqLayer22.occupancy                8000                       # La
 system.iobus.reqLayer22.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer23.occupancy                8000                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy         14942208000                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy         15138816000                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.6                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy          2374868000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy          2374880000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.1                       # Layer utilization (%)
-system.iobus.respLayer1.occupancy         37649719589                       # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy         38173420540                       # Layer occupancy (ticks)
 system.iobus.respLayer1.utilization               1.5                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.branchPred.lookups                14910337                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          11976867                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            705848                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups              9580478                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                 7742107                       # Number of BTB hits
+system.cpu.branchPred.lookups                13201290                       # Number of BP lookups
+system.cpu.branchPred.condPredicted           9675974                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            704139                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups              8377301                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                 6024680                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             80.811281                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 1408303                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect              72648                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             71.916719                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 1435837                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect              30801                       # Number of incorrect RAS predictions.
 system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.checker.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -479,25 +479,25 @@ system.cpu.checker.dstage2_mmu.stage2_tlb.misses            0
 system.cpu.checker.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu.checker.dtb.inst_hits                    0                       # ITB inst hits
 system.cpu.checker.dtb.inst_misses                  0                       # ITB inst misses
-system.cpu.checker.dtb.read_hits             14987595                       # DTB read hits
-system.cpu.checker.dtb.read_misses               7306                       # DTB read misses
-system.cpu.checker.dtb.write_hits            11227720                       # DTB write hits
-system.cpu.checker.dtb.write_misses              2191                       # DTB write misses
+system.cpu.checker.dtb.read_hits             13156743                       # DTB read hits
+system.cpu.checker.dtb.read_misses               7321                       # DTB read misses
+system.cpu.checker.dtb.write_hits            11227340                       # DTB write hits
+system.cpu.checker.dtb.write_misses              2193                       # DTB write misses
 system.cpu.checker.dtb.flush_tlb                    4                       # Number of times complete TLB was flushed
 system.cpu.checker.dtb.flush_tlb_mva                0                       # Number of times TLB was flushed by MVA
 system.cpu.checker.dtb.flush_tlb_mva_asid         2878                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.checker.dtb.flush_tlb_asid             126                       # Number of times TLB was flushed by ASID
-system.cpu.checker.dtb.flush_entries             3398                       # Number of entries that have been flushed from TLB
+system.cpu.checker.dtb.flush_entries             3404                       # Number of entries that have been flushed from TLB
 system.cpu.checker.dtb.align_faults                 0                       # Number of TLB faults due to alignment restrictions
 system.cpu.checker.dtb.prefetch_faults            180                       # Number of TLB faults due to prefetch
 system.cpu.checker.dtb.domain_faults                0                       # Number of TLB faults due to domain restrictions
 system.cpu.checker.dtb.perms_faults               452                       # Number of TLB faults due to permissions restrictions
-system.cpu.checker.dtb.read_accesses         14994901                       # DTB read accesses
-system.cpu.checker.dtb.write_accesses        11229911                       # DTB write accesses
+system.cpu.checker.dtb.read_accesses         13164064                       # DTB read accesses
+system.cpu.checker.dtb.write_accesses        11229533                       # DTB write accesses
 system.cpu.checker.dtb.inst_accesses                0                       # ITB inst accesses
-system.cpu.checker.dtb.hits                  26215315                       # DTB hits
-system.cpu.checker.dtb.misses                    9497                       # DTB misses
-system.cpu.checker.dtb.accesses              26224812                       # DTB accesses
+system.cpu.checker.dtb.hits                  24384083                       # DTB hits
+system.cpu.checker.dtb.misses                    9514                       # DTB misses
+system.cpu.checker.dtb.accesses              24393597                       # DTB accesses
 system.cpu.checker.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.checker.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.checker.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -519,7 +519,7 @@ system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.checker.istage2_mmu.stage2_tlb.hits            0                       # DTB hits
 system.cpu.checker.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.checker.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.checker.itb.inst_hits             61483491                       # ITB inst hits
+system.cpu.checker.itb.inst_hits             61486079                       # ITB inst hits
 system.cpu.checker.itb.inst_misses               4473                       # ITB inst misses
 system.cpu.checker.itb.read_hits                    0                       # DTB read hits
 system.cpu.checker.itb.read_misses                  0                       # DTB read misses
@@ -536,11 +536,11 @@ system.cpu.checker.itb.domain_faults                0                       # Nu
 system.cpu.checker.itb.perms_faults                 0                       # Number of TLB faults due to permissions restrictions
 system.cpu.checker.itb.read_accesses                0                       # DTB read accesses
 system.cpu.checker.itb.write_accesses               0                       # DTB write accesses
-system.cpu.checker.itb.inst_accesses         61487964                       # ITB inst accesses
-system.cpu.checker.itb.hits                  61483491                       # DTB hits
+system.cpu.checker.itb.inst_accesses         61490552                       # ITB inst accesses
+system.cpu.checker.itb.hits                  61486079                       # DTB hits
 system.cpu.checker.itb.misses                    4473                       # DTB misses
-system.cpu.checker.itb.accesses              61487964                       # DTB accesses
-system.cpu.checker.numCycles                 77886925                       # number of cpu cycles simulated
+system.cpu.checker.itb.accesses              61490552                       # DTB accesses
+system.cpu.checker.numCycles                 72947431                       # number of cpu cycles simulated
 system.cpu.checker.numWorkItemsStarted              0                       # number of work items this cpu started
 system.cpu.checker.numWorkItemsCompleted            0                       # number of work items this cpu completed
 system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
@@ -566,25 +566,25 @@ system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DT
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.read_hits                     51097792                       # DTB read hits
-system.cpu.dtb.read_misses                      64987                       # DTB read misses
-system.cpu.dtb.write_hits                    11709971                       # DTB write hits
-system.cpu.dtb.write_misses                     15921                       # DTB write misses
+system.cpu.dtb.read_hits                     31642294                       # DTB read hits
+system.cpu.dtb.read_misses                      39524                       # DTB read misses
+system.cpu.dtb.write_hits                    11381361                       # DTB write hits
+system.cpu.dtb.write_misses                     10135                       # DTB write misses
 system.cpu.dtb.flush_tlb                            4                       # Number of times complete TLB was flushed
 system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
 system.cpu.dtb.flush_tlb_mva_asid                2878                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.dtb.flush_tlb_asid                     126                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries                     3472                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults                      2569                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults                    428                       # Number of TLB faults due to prefetch
+system.cpu.dtb.flush_entries                     3437                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                       348                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                    314                       # Number of TLB faults due to prefetch
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults                      1363                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses                 51162779                       # DTB read accesses
-system.cpu.dtb.write_accesses                11725892                       # DTB write accesses
+system.cpu.dtb.perms_faults                      1342                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                 31681818                       # DTB read accesses
+system.cpu.dtb.write_accesses                11391496                       # DTB write accesses
 system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.hits                          62807763                       # DTB hits
-system.cpu.dtb.misses                           80908                       # DTB misses
-system.cpu.dtb.accesses                      62888671                       # DTB accesses
+system.cpu.dtb.hits                          43023655                       # DTB hits
+system.cpu.dtb.misses                           49659                       # DTB misses
+system.cpu.dtb.accesses                      43073314                       # DTB accesses
 system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -606,8 +606,8 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.inst_hits                     11575507                       # ITB inst hits
-system.cpu.itb.inst_misses                      11335                       # ITB inst misses
+system.cpu.itb.inst_hits                     24159481                       # ITB inst hits
+system.cpu.itb.inst_misses                      10516                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.write_hits                           0                       # DTB write hits
@@ -616,607 +616,598 @@ system.cpu.itb.flush_tlb                            4                       # Nu
 system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
 system.cpu.itb.flush_tlb_mva_asid                2878                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.itb.flush_tlb_asid                     126                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries                     2514                       # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_entries                     2464                       # Number of entries that have been flushed from TLB
 system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
 system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults                      2954                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults                      4176                       # Number of TLB faults due to permissions restrictions
 system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.inst_accesses                 11586842                       # ITB inst accesses
-system.cpu.itb.hits                          11575507                       # DTB hits
-system.cpu.itb.misses                           11335                       # DTB misses
-system.cpu.itb.accesses                      11586842                       # DTB accesses
-system.cpu.numCycles                        476238509                       # number of cpu cycles simulated
+system.cpu.itb.inst_accesses                 24169997                       # ITB inst accesses
+system.cpu.itb.hits                          24159481                       # DTB hits
+system.cpu.itb.misses                           10516                       # DTB misses
+system.cpu.itb.accesses                      24169997                       # DTB accesses
+system.cpu.numCycles                        499350041                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           29789702                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                       91027179                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    14910337                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches            9150410                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      20302096                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 4754274                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles                     125108                       # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.BlockedCycles               93772455                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                 2699                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles         88682                       # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles      2727734                       # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles          553                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                  11572027                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                712397                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes                    5390                       # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples          150113292                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              0.756026                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.113644                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles           43030629                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                       74131140                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    13201290                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches            7460517                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     448266810                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 1858598                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles                     133224                       # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles                12550                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles        145871                       # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles      3032125                       # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles           42                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                  24158180                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                404816                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes                    4527                       # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples          495550550                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              0.179793                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             0.652924                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                129826802     86.49%     86.49% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  1312716      0.87%     87.36% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  1720953      1.15%     88.51% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  2304331      1.54%     90.04% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  2116294      1.41%     91.45% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  1112529      0.74%     92.19% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  2605432      1.74%     93.93% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                   752346      0.50%     94.43% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                  8361889      5.57%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                454644690     91.75%     91.75% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 13614673      2.75%     94.49% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  6391682      1.29%     95.78% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 20899505      4.22%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            150113292                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.031309                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.191138                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 31268958                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              96222513                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  18495001                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles                992442                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                3134378                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved              1970530                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                172531                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              108153308                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                572201                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                3134378                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 32906794                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                14229038                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles       56831984                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  17995352                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              25015746                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              103064055                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                  1610                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents               17097046                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents               19764397                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                2757051                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.FullRegisterEvents             1781                       # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands           107250734                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             477314257                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        435890251                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups             10500                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps              78727504                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 28523229                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts            1172187                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts        1078501                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  11007211                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             19896895                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            13369840                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           2003415                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          2457274                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                   95806828                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded             1986007                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 122955094                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            190842                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        19616274                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     49695395                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved         503680                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     150113292                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.819082                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.543742                       # Number of insts issued each cycle
+system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::total            495550550                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.026437                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.148455                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 35577628                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             424964763                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  30286365                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               4037656                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                 684138                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              1691487                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                250438                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts               80256354                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts               2078563                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                 684138                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 38799814                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles               217885603                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles       28702319                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  30653900                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles             178824776                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts               78213523                       # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts                597412                       # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents              61147213                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents               42400387                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents              160465829                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents               14695892                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands            82092463                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             364185184                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups         97017359                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups              9816                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps              75931181                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                  6161276                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts            1134052                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts         964724                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                   8995770                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             14558741                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            12101093                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads            791110                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          1256144                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                   75819284                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded             1655722                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                  93902738                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            178739                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined         4397586                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined      8688962                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved         172255                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     495550550                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.189492                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        0.548412                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           106692829     71.07%     71.07% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            13471343      8.97%     80.05% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2             6554897      4.37%     84.42% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3             5548193      3.70%     88.11% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            12665338      8.44%     96.55% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             2805396      1.87%     98.42% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             1723552      1.15%     99.57% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7              514218      0.34%     99.91% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              137526      0.09%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           430558497     86.88%     86.88% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            42998311      8.68%     95.56% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            15714626      3.17%     98.73% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3             5641325      1.14%     99.87% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4              637755      0.13%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                  36      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6                   0      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       150113292                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       495550550                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                   66740      0.75%      0.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      6      0.00%      0.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      0.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      0.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      0.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      0.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      0.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      0.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      0.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      0.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      0.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      0.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      0.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      0.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      0.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      0.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      0.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      0.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      0.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      0.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      0.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      0.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      0.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      0.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      0.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      0.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      0.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      0.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      0.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                8421993     94.18%     94.93% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                453824      5.07%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                 4849757     15.79%     15.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                    148      0.00%     15.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     15.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     15.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     15.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     15.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     15.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     15.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     15.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     15.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     15.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     15.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     15.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     15.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     15.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     15.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     15.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     15.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     15.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     15.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     15.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     15.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     15.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     15.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     15.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     15.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     15.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     15.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     15.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead               20356138     66.26%     82.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               5517293     17.96%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass             28518      0.02%      0.02% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu              58064867     47.22%     47.25% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                93414      0.08%     47.32% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     47.32% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     47.32% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     47.32% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     47.32% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     47.32% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     47.32% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     47.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     47.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     47.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     47.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     47.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     47.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                  21      0.00%     47.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     47.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     47.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     47.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc              15      0.00%     47.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     47.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     47.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     47.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     47.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     47.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     47.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc           2113      0.00%     47.33% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     47.33% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc           16      0.00%     47.33% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     47.33% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             52433900     42.64%     89.97% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            12332230     10.03%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass             28518      0.03%      0.03% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu              49538159     52.75%     52.79% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                91859      0.10%     52.88% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     52.88% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     52.88% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     52.88% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     52.88% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     52.88% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     52.88% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     52.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     52.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     52.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     52.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     52.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     52.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     52.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     52.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     52.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     52.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     52.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     52.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     52.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     52.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     52.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     52.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     52.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc           2111      0.00%     52.89% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     52.89% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     52.89% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     52.89% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             32267131     34.36%     87.25% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            11974960     12.75%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              122955094                       # Type of FU issued
-system.cpu.iq.rate                           0.258180                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     8942563                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.072730                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          405214220                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         117427083                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses     85619955                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads               23208                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes              12528                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses        10296                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              131856805                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                   12334                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads           652625                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total               93902738                       # Type of FU issued
+system.cpu.iq.rate                           0.188050                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    30723336                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.327183                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          714225557                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes          81867089                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses     74968821                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads               32544                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes              12124                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses        10212                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              124576093                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                   21463                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads           210027                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      4242114                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses         5511                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        31676                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      1637740                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      1045815                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses          542                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation         6661                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores       369450                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads     33981236                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked        675243                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads     17074256                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked       1003626                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                3134378                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                11621778                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles               1344860                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts            98019144                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            177250                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              19896895                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             13369840                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts            1412264                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                 282212                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                925122                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          31676                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         351157                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       270951                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts               622108                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             120868290                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              51786364                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           2086804                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                 684138                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                94162664                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles              98281305                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts            77651016                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts              14558741                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             12101093                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts            1114432                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                  20278                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents              98196726                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents           6661                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         210280                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       275497                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts               485777                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts              93247730                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              32000327                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts            605564                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                        226309                       # number of nop insts executed
-system.cpu.iew.exec_refs                     64008543                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 11843747                       # Number of branches executed
-system.cpu.iew.exec_stores                   12222179                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.253798                       # Inst execution rate
-system.cpu.iew.wb_sent                      119919333                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                      85630251                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                  47892202                       # num instructions producing a value
-system.cpu.iew.wb_consumers                  88557277                       # num instructions consuming a value
+system.cpu.iew.exec_nop                        176010                       # number of nop insts executed
+system.cpu.iew.exec_refs                     43889216                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 10791342                       # Number of branches executed
+system.cpu.iew.exec_stores                   11888889                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.186738                       # Inst execution rate
+system.cpu.iew.wb_sent                       92183788                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                      74979033                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                  35465784                       # num instructions producing a value
+system.cpu.iew.wb_consumers                  52709939                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.179805                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.540805                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       0.150153                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.672848                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts        19373634                       # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls         1482327                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            535963                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    146978914                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.528998                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.513466                       # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts         3942514                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls         1483467                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts            458978                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    494644570                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.147200                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     0.699335                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    118714103     80.77%     80.77% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     14514329      9.88%     90.64% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2      3718532      2.53%     93.17% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      2215097      1.51%     94.68% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      1629859      1.11%     95.79% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      1057435      0.72%     96.51% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      1495738      1.02%     97.53% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7       696782      0.47%     98.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      2937039      2.00%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    457921524     92.58%     92.58% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     22157230      4.48%     97.06% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      6973464      1.41%     98.47% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      2402706      0.49%     98.95% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      1803578      0.36%     99.32% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      1042786      0.21%     99.53% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6       592301      0.12%     99.65% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       490313      0.10%     99.75% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      1260668      0.25%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    146978914                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts             60459894                       # Number of instructions committed
-system.cpu.commit.committedOps               77751509                       # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total    494644570                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts             60462326                       # Number of instructions committed
+system.cpu.commit.committedOps               72811859                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                       27386881                       # Number of memory references committed
-system.cpu.commit.loads                      15654781                       # Number of loads committed
-system.cpu.commit.membars                      403574                       # Number of memory barriers committed
-system.cpu.commit.branches                   10306383                       # Number of branches committed
+system.cpu.commit.refs                       25244569                       # Number of memory references committed
+system.cpu.commit.loads                      13512926                       # Number of loads committed
+system.cpu.commit.membars                      403660                       # Number of memory barriers committed
+system.cpu.commit.branches                   10308073                       # Number of branches committed
 system.cpu.commit.fp_insts                      10212                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                  69191543                       # Number of committed integer instructions.
-system.cpu.commit.function_calls               991261                       # Number of function calls committed.
+system.cpu.commit.int_insts                  64250122                       # Number of committed integer instructions.
+system.cpu.commit.function_calls               991634                       # Number of function calls committed.
 system.cpu.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu         50274580     64.66%     64.66% # Class of committed instruction
-system.cpu.commit.op_class_0::IntMult           87935      0.11%     64.77% # Class of committed instruction
-system.cpu.commit.op_class_0::IntDiv                0      0.00%     64.77% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatAdd              0      0.00%     64.77% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatCmp              0      0.00%     64.77% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatCvt              0      0.00%     64.77% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMult             0      0.00%     64.77% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatDiv              0      0.00%     64.77% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     64.77% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAdd               0      0.00%     64.77% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     64.77% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAlu               0      0.00%     64.77% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdCmp               0      0.00%     64.77% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdCvt               0      0.00%     64.77% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMisc              0      0.00%     64.77% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMult              0      0.00%     64.77% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     64.77% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdShift             0      0.00%     64.77% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     64.77% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     64.77% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     64.77% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     64.77% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     64.77% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     64.77% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     64.77% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMisc         2113      0.00%     64.78% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     64.78% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     64.78% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     64.78% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead        15654781     20.13%     84.91% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite       11732100     15.09%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu         47477289     65.21%     65.21% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult           87890      0.12%     65.33% # Class of committed instruction
+system.cpu.commit.op_class_0::IntDiv                0      0.00%     65.33% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatAdd              0      0.00%     65.33% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCmp              0      0.00%     65.33% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCvt              0      0.00%     65.33% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatMult             0      0.00%     65.33% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatDiv              0      0.00%     65.33% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     65.33% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAdd               0      0.00%     65.33% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     65.33% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAlu               0      0.00%     65.33% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCmp               0      0.00%     65.33% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCvt               0      0.00%     65.33% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMisc              0      0.00%     65.33% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMult              0      0.00%     65.33% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     65.33% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShift             0      0.00%     65.33% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     65.33% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     65.33% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     65.33% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     65.33% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     65.33% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     65.33% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     65.33% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMisc         2111      0.00%     65.33% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     65.33% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     65.33% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     65.33% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead        13512926     18.56%     83.89% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite       11731643     16.11%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total          77751509                       # Class of committed instruction
-system.cpu.commit.bw_lim_events               2937039                       # number cycles where commit BW limit reached
+system.cpu.commit.op_class_0::total          72811859                       # Class of committed instruction
+system.cpu.commit.bw_lim_events               1260668                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                    239318561                       # The number of ROB reads
-system.cpu.rob.rob_writes                   197472000                       # The number of ROB writes
-system.cpu.timesIdled                         1764819                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                       326125217                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles                   4575456172                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts                    60309513                       # Number of Instructions Simulated
-system.cpu.committedOps                      77601128                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               7.896574                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         7.896574                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.126637                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.126637                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                548833946                       # number of integer regfile reads
-system.cpu.int_regfile_writes                87707846                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                      8328                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                     2914                       # number of floating regfile writes
-system.cpu.misc_regfile_reads               264312368                       # number of misc regfile reads
-system.cpu.misc_regfile_writes                1173237                       # number of misc regfile writes
-system.cpu.toL2Bus.throughput                58892733                       # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq        2658790                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       2658789                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteReq        763349                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteResp       763349                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback       607940                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq         2966                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::SCUpgradeReq           11                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp         2977                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       246105                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       246105                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1961974                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      5797376                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        30926                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       128827                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           7919103                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     62745984                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     85556470                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        42736                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       216536                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total      148561726                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus         148561726                       # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus       194772                       # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy     3129487727                       # Layer occupancy (ticks)
+system.cpu.rob.rob_reads                    568287463                       # The number of ROB reads
+system.cpu.rob.rob_writes                   154414560                       # The number of ROB writes
+system.cpu.timesIdled                          544007                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                         3799491                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles                   4584972685                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts                    60311945                       # Number of Instructions Simulated
+system.cpu.committedOps                      72661478                       # Number of Ops (including micro ops) Simulated
+system.cpu.cpi                               8.279455                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         8.279455                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.120781                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.120781                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                109116898                       # number of integer regfile reads
+system.cpu.int_regfile_writes                47012348                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                      8305                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                     2780                       # number of floating regfile writes
+system.cpu.cc_regfile_reads                 320404209                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                 30332896                       # number of cc regfile writes
+system.cpu.misc_regfile_reads               605539146                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                1173999                       # number of misc regfile writes
+system.cpu.toL2Bus.throughput                57498963                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq        2604292                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       2604292                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteReq        763357                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteResp       763357                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback       599976                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq         2950                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::SCUpgradeReq            2                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp         2952                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       246570                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       246570                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1926546                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      5768452                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        27160                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side        85384                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           7807542                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     61456864                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     84377274                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        37916                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       135596                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total      146007650                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus         146007650                       # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus       166384                       # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy     3090458553                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy    1474700416                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy    1447056987                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    2550487184                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    2544187527                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy      20248986                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.occupancy      17686240                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy      74797546                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy      51535649                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.cpu.icache.tags.replacements            980898                       # number of replacements
-system.cpu.icache.tags.tagsinuse           511.584882                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            10510158                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs            981410                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             10.709243                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle        6868426250                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   511.584882                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.999189                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.999189                       # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements            959881                       # number of replacements
+system.cpu.icache.tags.tagsinuse           511.383361                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            23149457                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs            960393                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             24.104150                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle       11344582250                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   511.383361                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.998796                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.998796                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          137                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          214                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          160                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          118                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          171                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          221                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          12553342                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         12553342                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     10510158                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        10510158                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      10510158                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         10510158                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     10510158                       # number of overall hits
-system.cpu.icache.overall_hits::total        10510158                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst      1061739                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total       1061739                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst      1061739                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total        1061739                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst      1061739                       # number of overall misses
-system.cpu.icache.overall_misses::total       1061739                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  14266290615                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  14266290615                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  14266290615                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  14266290615                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  14266290615                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  14266290615                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     11571897                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     11571897                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     11571897                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     11571897                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     11571897                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     11571897                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.091752                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.091752                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.091752                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.091752                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.091752                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.091752                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13436.720903                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13436.720903                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13436.720903                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13436.720903                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13436.720903                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13436.720903                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs         7331                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets          116                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs               335                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               1                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    21.883582                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets          116                       # average number of cycles each access was blocked
+system.cpu.icache.tags.tag_accesses          25115239                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         25115239                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     23149457                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        23149457                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      23149457                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         23149457                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     23149457                       # number of overall hits
+system.cpu.icache.overall_hits::total        23149457                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst      1005369                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total       1005369                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst      1005369                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total        1005369                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst      1005369                       # number of overall misses
+system.cpu.icache.overall_misses::total       1005369                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  13656038478                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  13656038478                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  13656038478                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  13656038478                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  13656038478                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  13656038478                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     24154826                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     24154826                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     24154826                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     24154826                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     24154826                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     24154826                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.041622                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.041622                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.041622                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.041622                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.041622                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.041622                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13583.110756                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13583.110756                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13583.110756                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13583.110756                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13583.110756                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13583.110756                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs         1617                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs               119                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    13.588235                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst        80293                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total        80293                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst        80293                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total        80293                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst        80293                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total        80293                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst       981446                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total       981446                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst       981446                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total       981446                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst       981446                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total       981446                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  11573178578                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  11573178578                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst  11573178578                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total  11573178578                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst  11573178578                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total  11573178578                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst      8964000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::total      8964000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst      8964000                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::total      8964000                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.084813                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.084813                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.084813                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.084813                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.084813                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.084813                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11791.966729                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11791.966729                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11791.966729                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 11791.966729                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11791.966729                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 11791.966729                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst        44956                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total        44956                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst        44956                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total        44956                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst        44956                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total        44956                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst       960413                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total       960413                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst       960413                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total       960413                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst       960413                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total       960413                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  11283890760                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total  11283890760                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst  11283890760                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total  11283890760                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst  11283890760                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total  11283890760                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst    223026500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_uncacheable_latency::total    223026500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst    223026500                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_latency::total    223026500                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.039761                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.039761                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.039761                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.039761                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.039761                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.039761                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11748.998358                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11748.998358                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11748.998358                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 11748.998358                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11748.998358                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 11748.998358                       # average overall mshr miss latency
 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements            64369                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        51363.817213                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            1888922                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           129761                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            14.556932                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle     2490733870000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 36937.336839                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker    33.862464                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.000252                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  8170.435646                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  6222.182012                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.563619                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000517                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.replacements            63302                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        51128.734687                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            1829071                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           128690                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            14.213000                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle     2530789670500                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 37302.599889                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker     6.814194                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.000703                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  7723.154288                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  6096.165612                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.569193                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000104                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000000                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.124671                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.094943                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.783750                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1023           23                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        65369                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1023::4           22                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           39                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          352                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         3050                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         6967                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        54961                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1023     0.000351                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.997452                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         18802940                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        18802940                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker        54086                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.itb.walker        10683                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.inst       967938                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data       387449                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        1420156                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks       607940                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total       607940                       # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data           43                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total           43                       # number of UpgradeReq hits
-system.cpu.l2cache.SCUpgradeReq_hits::cpu.data            8                       # number of SCUpgradeReq hits
-system.cpu.l2cache.SCUpgradeReq_hits::total            8                       # number of SCUpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       112904                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       112904                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.dtb.walker        54086                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.itb.walker        10683                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.inst       967938                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data       500353                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         1533060                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.dtb.walker        54086                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.itb.walker        10683                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.inst       967938                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data       500353                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        1533060                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker           48                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.itb.walker            1                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.inst        12347                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data        10729                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total        23125                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data         2923                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total         2923                       # number of UpgradeReq misses
-system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            3                       # number of SCUpgradeReq misses
-system.cpu.l2cache.SCUpgradeReq_misses::total            3                       # number of SCUpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       133201                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       133201                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.dtb.walker           48                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.itb.walker            1                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.inst        12347                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       143930                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        156326                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.dtb.walker           48                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.itb.walker            1                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.inst        12347                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       143930                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       156326                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker      3943500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker        83000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    890764250                       # number of ReadReq miss cycles
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-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74599.729611                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 73304.702659                       # average ReadReq miss latency
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-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total   199.615121                       # average UpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73415.259495                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73415.259495                       # average ReadExReq miss latency
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+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.997635                       # Percentage of cache occupancy per task id
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+system.cpu.l2cache.overall_avg_miss_latency::total 70444.865605                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1225,109 +1216,104 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        59141                       # number of writebacks
-system.cpu.l2cache.writebacks::total            59141                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst           11                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           66                       # number of ReadReq MSHR hits
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-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166948483750                       # number of ReadReq MSHR uncacheable cycles
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-system.cpu.l2cache.overall_mshr_uncacheable_latency::total 184446561900                       # number of overall MSHR uncacheable cycles
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-system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data     0.272727                       # mshr miss rate for SCUpgradeReq accesses
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-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.012584                       # mshr miss rate for demand accesses
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-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61172.228765                       # average overall mshr miss latency
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-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61049.192436                       # average overall mshr miss latency
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+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167188737750                       # number of ReadReq MSHR uncacheable cycles
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+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000295                       # mshr miss rate for ReadReq accesses
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+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.226345                       # mshr miss rate for overall accesses
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+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 67083.333333                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58717.826375                       # average ReadReq mshr miss latency
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+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10005.812650                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57564.727740                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57564.727740                       # average ReadExReq mshr miss latency
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+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 67083.333333                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58717.826375                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57916.238816                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57976.678284                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker        59625                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 67083.333333                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58717.826375                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57916.238816                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57976.678284                       # average overall mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -1337,168 +1323,184 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements            643771                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.993313                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            21491250                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs            644283                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             33.356848                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle          42393250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.993313                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999987                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999987                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements            633309                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.949942                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            19068560                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            633821                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             30.085087                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle         267154250                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.949942                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.999902                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999902                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          195                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          299                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2           18                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          170                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          320                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           22                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         101573451                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        101573451                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     13743815                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        13743815                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      7253892                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        7253892                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data       242816                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       242816                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data       247598                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total       247598                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      20997707                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         20997707                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     20997707                       # number of overall hits
-system.cpu.dcache.overall_hits::total        20997707                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       762201                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        762201                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      2968429                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      2968429                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data        13530                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total        13530                       # number of LoadLockedReq misses
-system.cpu.dcache.StoreCondReq_misses::cpu.data           11                       # number of StoreCondReq misses
-system.cpu.dcache.StoreCondReq_misses::total           11                       # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data      3730630                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        3730630                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      3730630                       # number of overall misses
-system.cpu.dcache.overall_misses::total       3730630                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  10170757825                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  10170757825                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 136412874713                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 136412874713                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    184826749                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total    184826749                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       180503                       # number of StoreCondReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::total       180503                       # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 146583632538                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 146583632538                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 146583632538                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 146583632538                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     14506016                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     14506016                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data     10222321                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total     10222321                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data       256346                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total       256346                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data       247609                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total       247609                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     24728337                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     24728337                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     24728337                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     24728337                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.052544                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.052544                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.290387                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.290387                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.052780                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.052780                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000044                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::total     0.000044                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.150865                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.150865                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.150865                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.150865                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13343.931358                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 13343.931358                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45954.568802                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 45954.568802                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13660.513599                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13660.513599                       # average LoadLockedReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16409.363636                       # average StoreCondReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16409.363636                       # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 39291.924564                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 39291.924564                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 39291.924564                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 39291.924564                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs        33676                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets        25542                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs              2667                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets             316                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    12.626922                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets    80.829114                       # average number of cycles each access was blocked
+system.cpu.dcache.tags.tag_accesses          91797001                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         91797001                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     11311240                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        11311240                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      7209458                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        7209458                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data        60823                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total         60823                       # number of SoftPFReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data       236444                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total       236444                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data       247594                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total       247594                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data      18520698                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         18520698                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     18581521                       # number of overall hits
+system.cpu.dcache.overall_hits::total        18581521                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       573261                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        573261                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      3012484                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      3012484                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data       126501                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total       126501                       # number of SoftPFReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data        12988                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total        12988                       # number of LoadLockedReq misses
+system.cpu.dcache.StoreCondReq_misses::cpu.data            2                       # number of StoreCondReq misses
+system.cpu.dcache.StoreCondReq_misses::total            2                       # number of StoreCondReq misses
+system.cpu.dcache.demand_misses::cpu.data      3585745                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        3585745                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      3712246                       # number of overall misses
+system.cpu.dcache.overall_misses::total       3712246                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data   7216358166                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total   7216358166                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 126016512064                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 126016512064                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    178185500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total    178185500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::cpu.data        26000                       # number of StoreCondReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::total        26000                       # number of StoreCondReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 133232870230                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 133232870230                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 133232870230                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 133232870230                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     11884501                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     11884501                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data     10221942                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total     10221942                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data       187324                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total       187324                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data       249432                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total       249432                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data       247596                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total       247596                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     22106443                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     22106443                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     22293767                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     22293767                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.048236                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.048236                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.294708                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.294708                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.675306                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.675306                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.052070                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.052070                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000008                       # miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::total     0.000008                       # miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.162204                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.162204                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.166515                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.166515                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12588.259390                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 12588.259390                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41831.429499                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 41831.429499                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13719.240838                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13719.240838                       # average LoadLockedReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        13000                       # average StoreCondReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::total        13000                       # average StoreCondReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 37156.259084                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 37156.259084                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 35890.097324                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 35890.097324                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs        18826                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs              1227                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    15.343113                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       607940                       # number of writebacks
-system.cpu.dcache.writebacks::total            607940                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       376141                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       376141                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data      2719425                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total      2719425                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data         1345                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total         1345                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      3095566                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      3095566                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      3095566                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      3095566                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       386060                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       386060                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       249004                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       249004                       # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        12185                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total        12185                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data           11                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::total           11                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       635064                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       635064                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       635064                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       635064                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   4968476363                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   4968476363                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  11232028289                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  11232028289                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    145250501                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    145250501                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       158497                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       158497                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  16200504652                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  16200504652                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  16200504652                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  16200504652                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182335641750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182335641750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data  26891357119                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total  26891357119                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209226998869                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total 209226998869                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.026614                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.026614                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.024359                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.024359                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.047533                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.047533                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000044                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000044                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.025682                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.025682                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.025682                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.025682                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12869.699951                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12869.699951                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45107.822722                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45107.822722                       # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11920.435043                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11920.435043                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14408.818182                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14408.818182                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25510.034661                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 25510.034661                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25510.034661                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 25510.034661                       # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks       599976                       # number of writebacks
+system.cpu.dcache.writebacks::total            599976                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       271755                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       271755                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data      2763119                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total      2763119                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data         1233                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total         1233                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      3034874                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      3034874                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      3034874                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      3034874                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       301506                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       301506                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       249365                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       249365                       # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data        74145                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total        74145                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        11755                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total        11755                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            2                       # number of StoreCondReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::total            2                       # number of StoreCondReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       550871                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       550871                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       625016                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       625016                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   3569781578                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   3569781578                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  10783879319                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  10783879319                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   1231283000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   1231283000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    140188500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    140188500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data        22000                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::total        22000                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  14353660897                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  14353660897                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  15584943897                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  15584943897                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182408022250                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182408022250                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data  26599942575                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total  26599942575                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209007964825                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total 209007964825                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.025370                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.025370                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.024395                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.024395                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.395812                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.395812                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.047127                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.047127                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000008                       # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000008                       # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.024919                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.024919                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.028035                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.028035                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11839.835950                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11839.835950                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43245.360492                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43245.360492                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16606.419853                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16606.419853                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11925.861336                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11925.861336                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        11000                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        11000                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26056.301561                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 26056.301561                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24935.271892                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 24935.271892                       # average overall mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
@@ -1522,16 +1524,16 @@ system.iocache.avg_blocked_cycles::no_mshrs          nan                       #
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1711484214589                       # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1711484214589                       # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1711484214589                       # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1711484214589                       # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1736929447540                       # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1736929447540                       # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1736929447540                       # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1736929447540                       # number of overall MSHR uncacheable cycles
 system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average ReadReq mshr uncacheable latency
 system.iocache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average overall mshr uncacheable latency
 system.iocache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.quiesce                    83038                       # number of quiesce instructions executed
+system.cpu.kern.inst.quiesce                    83187                       # number of quiesce instructions executed
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
index fcbba5f01..b3c80425c 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
@@ -1,155 +1,155 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.605246                       # Number of seconds simulated
-sim_ticks                                2605245500000                       # Number of ticks simulated
-final_tick                               2605245500000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.621647                       # Number of seconds simulated
+sim_ticks                                2621647051000                       # Number of ticks simulated
+final_tick                               2621647051000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  66179                       # Simulator instruction rate (inst/s)
-host_op_rate                                    85203                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2745863070                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 426204                       # Number of bytes of host memory used
-host_seconds                                   948.79                       # Real time elapsed on the host
-sim_insts                                    62790043                       # Number of instructions simulated
-sim_ops                                      80839298                       # Number of ops (including micro ops) simulated
+host_inst_rate                                  56801                       # Simulator instruction rate (inst/s)
+host_op_rate                                    68443                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2377539464                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 411700                       # Number of bytes of host memory used
+host_seconds                                  1102.67                       # Real time elapsed on the host
+sim_insts                                    62632896                       # Number of instructions simulated
+sim_ops                                      75470296                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::realview.clcd    121110528                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.dtb.walker          896                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker           64                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst           393536                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data          4351548                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker          832                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           427968                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data          5241528                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            131526900                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       393536                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       427968                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          821504                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      4250944                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0.data         17000                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1.data       3012136                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7280080                       # Number of bytes written to this memory
+system.physmem.bytes_read::cpu0.dtb.walker          448                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker          128                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst           516048                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data          6568572                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker           64                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           301968                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data          2981560                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            131479316                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       516048                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       301968                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          818016                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      4189696                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0.data       3029096                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1.data            40                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7218832                       # Number of bytes written to this memory
 system.physmem.num_reads::realview.clcd      15138816                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.dtb.walker           14                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker            1                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst              6149                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data             68067                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker           13                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              6687                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data             81927                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total              15301674                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           66421                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0.data             4250                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1.data           753034                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               823705                       # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd        46487184                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.dtb.walker           344                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker            25                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst              151055                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data             1670302                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker           319                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst              164272                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data             2011913                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                50485415                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         151055                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst         164272                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             315327                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1631687                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data               6525                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data            1156181                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2794393                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1631687                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd       46487184                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker          344                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker           25                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             151055                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data            1676828                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker          319                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst             164272                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data            3168095                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               53279808                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                      15301674                       # Number of read requests accepted
-system.physmem.writeReqs                       823705                       # Number of write requests accepted
-system.physmem.readBursts                    15301674                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     823705                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                974584832                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                   4722304                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   7299840                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                 131526900                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                7280080                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                    73786                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                  709619                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs          14174                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0              956301                       # Per bank write bursts
-system.physmem.perBankRdBursts::1              950868                       # Per bank write bursts
-system.physmem.perBankRdBursts::2              950386                       # Per bank write bursts
-system.physmem.perBankRdBursts::3              950557                       # Per bank write bursts
-system.physmem.perBankRdBursts::4              956616                       # Per bank write bursts
-system.physmem.perBankRdBursts::5              950990                       # Per bank write bursts
-system.physmem.perBankRdBursts::6              949776                       # Per bank write bursts
-system.physmem.perBankRdBursts::7              949548                       # Per bank write bursts
-system.physmem.perBankRdBursts::8              956645                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              951285                       # Per bank write bursts
-system.physmem.perBankRdBursts::10             949982                       # Per bank write bursts
-system.physmem.perBankRdBursts::11             948991                       # Per bank write bursts
-system.physmem.perBankRdBursts::12             956228                       # Per bank write bursts
-system.physmem.perBankRdBursts::13             950424                       # Per bank write bursts
-system.physmem.perBankRdBursts::14             949846                       # Per bank write bursts
-system.physmem.perBankRdBursts::15             949445                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                7049                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                6917                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                7321                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                7203                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                7749                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                7300                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                7008                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                6995                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                7363                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                7456                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               6910                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               6580                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               7092                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               7012                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               7131                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               6974                       # Per bank write bursts
+system.physmem.num_reads::cpu0.dtb.walker            7                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker            2                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             10590                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data            102693                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker            1                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst              4761                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data             46605                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total              15303475                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           65464                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0.data           757274                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu1.data               10                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               822748                       # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd        46196351                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.dtb.walker           171                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker            49                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst              196841                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data             2505513                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker            24                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst              115183                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data             1137285                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                50151418                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         196841                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst         115183                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             312024                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1598116                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data            1155417                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1.data                 15                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                2753548                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1598116                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd       46196351                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker          171                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker           49                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             196841                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data            3660931                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker           24                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst             115183                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data            1137300                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               52904966                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                      15303475                       # Number of read requests accepted
+system.physmem.writeReqs                       822748                       # Number of write requests accepted
+system.physmem.readBursts                    15303475                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     822748                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                977402304                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                   2020096                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   7239040                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                 131479316                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                7218832                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                    31564                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                  709609                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs          12033                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0              956536                       # Per bank write bursts
+system.physmem.perBankRdBursts::1              956505                       # Per bank write bursts
+system.physmem.perBankRdBursts::2              953083                       # Per bank write bursts
+system.physmem.perBankRdBursts::3              951219                       # Per bank write bursts
+system.physmem.perBankRdBursts::4              959451                       # Per bank write bursts
+system.physmem.perBankRdBursts::5              955886                       # Per bank write bursts
+system.physmem.perBankRdBursts::6              953593                       # Per bank write bursts
+system.physmem.perBankRdBursts::7              950807                       # Per bank write bursts
+system.physmem.perBankRdBursts::8              956024                       # Per bank write bursts
+system.physmem.perBankRdBursts::9              956507                       # Per bank write bursts
+system.physmem.perBankRdBursts::10             953309                       # Per bank write bursts
+system.physmem.perBankRdBursts::11             950948                       # Per bank write bursts
+system.physmem.perBankRdBursts::12             956403                       # Per bank write bursts
+system.physmem.perBankRdBursts::13             956390                       # Per bank write bursts
+system.physmem.perBankRdBursts::14             954120                       # Per bank write bursts
+system.physmem.perBankRdBursts::15             951130                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                7301                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                7301                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                6635                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                6826                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                7245                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                6961                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                7187                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                6869                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                6823                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                7301                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               6956                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               6738                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               7232                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               7102                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               7378                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               7255                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    2605244301000                       # Total gap between requests
+system.physmem.totGap                    2621645657000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::2                     109                       # Read request sizes (log2)
-system.physmem.readPktSize::3                15138816                       # Read request sizes (log2)
-system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
+system.physmem.readPktSize::2                      59                       # Read request sizes (log2)
+system.physmem.readPktSize::3                15138841                       # Read request sizes (log2)
+system.physmem.readPktSize::4                    3426                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  162749                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  161149                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                 757284                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                  66421                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                   1076672                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                   1007796                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                    966781                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                   1073648                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                    970528                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                   1031139                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                   2669789                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                   2577083                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                   3357471                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                    128637                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                  65464                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                   1118217                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    965108                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                    965171                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                   1074431                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                    973448                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                   1034951                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                   2682221                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                   2590422                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                   3372339                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                    127125                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::10                   110466                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                   102015                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                    98116                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                    19856                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                    18946                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                    18627                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                      197                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                       98                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                       12                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                       10                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                   101918                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                    97549                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                    20170                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                    19294                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                    19015                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                       55                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                        6                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                        3                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                        2                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
@@ -176,28 +176,28 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     2761                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     2986                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     4505                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     6717                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     6884                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     6834                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     6859                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     7222                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     6902                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     6949                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     6984                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     6828                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     6821                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     7238                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     6837                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     6807                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     6970                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     6705                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      126                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                       79                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                       43                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                        9                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     2804                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     3130                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     5680                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     6732                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     6830                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     6759                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     6721                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     7049                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     6856                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     6815                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     6768                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     6678                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     6706                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     6721                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     6692                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     6660                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     6669                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     6637                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                       96                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                       62                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                       41                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                       13                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::37                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::38                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::39                        1                       # What write queue length does an incoming req see
@@ -225,383 +225,385 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples      1012037                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      970.206299                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     901.657757                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     207.022901                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          24841      2.45%      2.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        20798      2.06%      4.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         8822      0.87%      5.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         2548      0.25%      5.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2540      0.25%      5.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1879      0.19%      6.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         8798      0.87%      6.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1115      0.11%      7.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151       940696     92.95%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total        1012037                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          6684                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean      2278.257181                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev    111148.889106                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-524287         6680     99.94%     99.94% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::524288-1.04858e+06            2      0.03%     99.97% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2.09715e+06-2.62144e+06            1      0.01%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::8.38861e+06-8.9129e+06            1      0.01%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            6684                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          6684                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        17.064632                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       17.010880                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        1.396865                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16               3849     57.59%     57.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17                 42      0.63%     58.21% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18               1749     26.17%     84.38% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19                863     12.91%     97.29% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                 73      1.09%     98.38% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21                 28      0.42%     98.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22                 31      0.46%     99.27% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23                 31      0.46%     99.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24                 14      0.21%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::25                  3      0.04%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::29                  1      0.01%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            6684                       # Writes before turning the bus around for reads
-system.physmem.totQLat                   394529621500                       # Total ticks spent queuing
-system.physmem.totMemAccLat              680052521500                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                  76139440000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       25908.36                       # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples      1014826                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      970.256324                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     901.955292                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     206.811149                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          24748      2.44%      2.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        20792      2.05%      4.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         9109      0.90%      5.39% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         2441      0.24%      5.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2631      0.26%      5.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1759      0.17%      6.06% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         9074      0.89%      6.95% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1088      0.11%      7.06% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151       943184     92.94%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total        1014826                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          6619                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean      2307.281009                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev    96810.313262                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-262143         6612     99.89%     99.89% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::262144-524287            1      0.02%     99.91% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::524288-786431            1      0.02%     99.92% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::786432-1.04858e+06            1      0.02%     99.94% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1.04858e+06-1.31072e+06            2      0.03%     99.97% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1.31072e+06-1.57286e+06            1      0.02%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::7.34003e+06-7.60218e+06            1      0.02%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total            6619                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          6619                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.088684                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       17.037372                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        1.359683                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               3686     55.69%     55.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17                 52      0.79%     56.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18               1827     27.60%     84.08% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19                927     14.01%     98.08% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                 37      0.56%     98.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                 27      0.41%     99.05% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22                 28      0.42%     99.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23                 21      0.32%     99.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24                 11      0.17%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25                  1      0.02%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28                  2      0.03%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            6619                       # Writes before turning the bus around for reads
+system.physmem.totQLat                   395207982750                       # Total ticks spent queuing
+system.physmem.totMemAccLat              681556314000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                  76359555000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       25878.10                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  44658.36                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         374.09                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           2.80                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       50.49                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        2.79                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  44628.10                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         372.82                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           2.76                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       50.15                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        2.75                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           2.94                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       2.92                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                           2.93                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       2.91                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         6.23                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        24.94                       # Average write queue length when enqueuing
-system.physmem.readRowHits                   14233868                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     96043                       # Number of row buffer hits during writes
+system.physmem.avgRdQLen                         5.85                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        27.60                       # Average write queue length when enqueuing
+system.physmem.readRowHits                   14274861                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     95334                       # Number of row buffer hits during writes
 system.physmem.readRowHitRate                   93.47                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  84.18                       # Row buffer hit rate for writes
-system.physmem.avgGap                       161561.74                       # Average gap between requests
+system.physmem.writeRowHitRate                  84.26                       # Row buffer hit rate for writes
+system.physmem.avgGap                       162570.35                       # Average gap between requests
 system.physmem.pageHitRate                      93.40                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE     2261037204000                       # Time in different power states
-system.physmem.memoryStateTime::REF       86994700000                       # Time in different power states
+system.physmem.memoryStateTime::IDLE     2271344460000                       # Time in different power states
+system.physmem.memoryStateTime::REF       87542520000                       # Time in different power states
 system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT      257208674750                       # Time in different power states
+system.physmem.memoryStateTime::ACT      262759227500                       # Time in different power states
 system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.realview.nvmem.bytes_read::cpu0.inst           64                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::cpu1.inst          384                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total           448                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu0.inst           64                       # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu1.inst          384                       # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total          448                       # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu0.inst            1                       # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::cpu1.inst            6                       # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total              7                       # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu0.inst           25                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::cpu1.inst          147                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total              172                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu0.inst           25                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu1.inst          147                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total          172                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu0.inst           25                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu1.inst          147                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total             172                       # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput                     54210578                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq            16352619                       # Transaction distribution
-system.membus.trans_dist::ReadResp           16352619                       # Transaction distribution
-system.membus.trans_dist::WriteReq             769183                       # Transaction distribution
-system.membus.trans_dist::WriteResp            769183                       # Transaction distribution
-system.membus.trans_dist::Writeback             66421                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            35773                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq          18321                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp           14174                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            137666                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           137285                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave      2384364                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           14                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        13834                       # Packet count per connected master and slave (bytes)
+system.realview.nvmem.bytes_read::cpu0.inst           48                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::cpu1.inst          144                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total           192                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu0.inst           48                       # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu1.inst          144                       # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total          192                       # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu0.inst            3                       # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::cpu1.inst            9                       # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total             12                       # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu0.inst           18                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::cpu1.inst           55                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total               73                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu0.inst           18                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu1.inst           55                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total           73                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu0.inst           18                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu1.inst           55                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total              73                       # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput                     53827614                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq            16353736                       # Transaction distribution
+system.membus.trans_dist::ReadResp           16353736                       # Transaction distribution
+system.membus.trans_dist::WriteReq             768463                       # Transaction distribution
+system.membus.trans_dist::WriteResp            768463                       # Transaction distribution
+system.membus.trans_dist::Writeback             65464                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq            28363                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq          16887                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp           12033                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            137713                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           137251                       # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave      2384346                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           24                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        10950                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio            4                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio         2042                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      1975354                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total      4375612                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio         2058                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      1967095                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total      4364477                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port     30277632                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::total     30277632                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total               34653244                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave      2392677                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port          448                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio        27668                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count::total               34642109                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave      2392641                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port          192                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio        21900                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio            8                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio         4084                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port     17696452                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::total     20121337                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio         4116                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port     17587620                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::total     20006477                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port    121110528                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.iocache.mem_side::total    121110528                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total           141231865                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus              141231865                       # Total data (bytes)
+system.membus.tot_pkt_size::total           141117005                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus              141117005                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy          1487709500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy          1559281500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.1                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy                7000                       # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy               14500                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy            11701000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             9763000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer4.occupancy                3000                       # Layer occupancy (ticks)
+system.membus.reqLayer4.occupancy                2500                       # Layer occupancy (ticks)
 system.membus.reqLayer4.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy             1799000                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy             1786500                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer6.occupancy         17608394498                       # Layer occupancy (ticks)
+system.membus.reqLayer6.occupancy         17605374000                       # Layer occupancy (ticks)
 system.membus.reqLayer6.utilization               0.7                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         4825319244                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         4830238688                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
-system.membus.respLayer2.occupancy        37398632151                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy        37428300697                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              1.4                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.l2c.tags.replacements                    72458                       # number of replacements
-system.l2c.tags.tagsinuse                53011.924457                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    1875821                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                   137631                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                    13.629349                       # Average number of references to valid blocks.
+system.l2c.tags.replacements                    71035                       # number of replacements
+system.l2c.tags.tagsinuse                52844.560777                       # Cycle average of tags in use
+system.l2c.tags.total_refs                    1830685                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                   136207                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                    13.440462                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   37713.505334                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker     5.216539                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker     0.000245                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     4181.052971                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     2965.825646                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker    11.076579                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst     4028.442908                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data     4106.804235                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.575462                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000080                       # Average percentage of cache occupancy
+system.l2c.tags.occ_blocks::writebacks   37821.803984                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.dtb.walker     5.739512                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker     0.000522                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     5415.027395                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     6377.582658                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.dtb.walker     0.953654                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst     2390.174334                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data      833.278718                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.577115                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000088                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu0.itb.walker     0.000000                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.063798                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.045255                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000169                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.061469                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.062665                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.808898                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1023            5                       # Occupied blocks per task id
+system.l2c.tags.occ_percent::cpu0.inst       0.082627                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data       0.097314                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000015                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.036471                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data       0.012715                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.806344                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1023            4                       # Occupied blocks per task id
 system.l2c.tags.occ_task_id_blocks::1024        65168                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::3            2                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4            3                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0           25                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1          325                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         3104                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         8671                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        53043                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1023     0.000076                       # Percentage of cache occupancy per task id
+system.l2c.tags.age_task_id_blocks_1023::4            4                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0           37                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1          183                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2         3098                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3         8323                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        53527                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1023     0.000061                       # Percentage of cache occupancy per task id
 system.l2c.tags.occ_task_id_percent::1024     0.994385                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                 18870937                       # Number of tag accesses
-system.l2c.tags.data_accesses                18870937                       # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.dtb.walker        23602                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker         4624                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.inst             393472                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data             166101                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker        33133                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker         5623                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst             609766                       # number of ReadReq hits
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-system.l2c.ReadReq_hits::total                1437806                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks          583097                       # number of Writeback hits
-system.l2c.Writeback_hits::total               583097                       # number of Writeback hits
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-system.l2c.UpgradeReq_hits::cpu1.data             849                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                1858                       # number of UpgradeReq hits
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-system.l2c.SCUpgradeReq_hits::total               380                       # number of SCUpgradeReq hits
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-system.l2c.UpgradeReq_misses::total             10191                       # number of UpgradeReq misses
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-system.l2c.demand_misses::cpu0.inst              6027                       # number of demand (read+write) misses
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-system.l2c.UpgradeReq_miss_latency::cpu1.data     12322478                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total     21692557                       # number of UpgradeReq miss cycles
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-system.l2c.SCUpgradeReq_miss_latency::total      3652842                       # number of SCUpgradeReq miss cycles
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-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.850408                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.839932                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.845796                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.786151                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.776610                       # miss rate for SCUpgradeReq accesses
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-system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker       293000                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.inst 72581.134893                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.data 74350.870784                       # average ReadReq miss latency
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-system.l2c.ReadReq_avg_miss_latency::cpu1.inst 72892.513530                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.data 76197.826429                       # average ReadReq miss latency
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-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  1633.556311                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  2765.988328                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total  2128.599450                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data   691.680052                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  5277.267343                       # average SCUpgradeReq miss latency
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-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 68744.792128                       # average ReadExReq miss latency
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-system.l2c.demand_avg_miss_latency::cpu1.data 77476.596262                       # average overall miss latency
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-system.l2c.overall_avg_miss_latency::cpu0.data 69254.758661                       # average overall miss latency
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-system.l2c.overall_avg_miss_latency::cpu1.data 77476.596262                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 73662.757309                       # average overall miss latency
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+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.910870                       # miss rate for UpgradeReq accesses
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 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -610,168 +612,171 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
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-system.l2c.writebacks::total                    66421                       # number of writebacks
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-system.l2c.UpgradeReq_mshr_misses::cpu1.data         4455                       # number of UpgradeReq MSHR misses
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+system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.000373                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.013034                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.038974                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.000064                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.010709                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.017257                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.016899                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.771693                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.910870                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.830226                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.655654                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.842953                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.746736                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.589536                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.506032                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.559394                       # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.000335                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.000373                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.013034                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.251882                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.000064                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.010709                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.225648                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.098358                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.000335                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.000373                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.013034                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.251882                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.000064                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.010709                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.225648                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.098358                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 56428.571429                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker        62500                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 59721.956793                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 61615.031614                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker        71000                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 58417.995111                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 66037.248806                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 60800.160892                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10013.300954                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10032.830443                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10022.312231                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data        10001                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10024.084395                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10013.672203                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 55258.513343                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 59790.479096                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 56738.321690                       # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 56428.571429                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker        62500                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 59721.956793                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 55861.716055                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker        71000                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 58417.995111                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 60064.524512                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 57331.418810                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 56428.571429                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker        62500                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 59721.956793                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 55861.716055                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker        71000                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 58417.995111                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 60064.524512                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 57331.418810                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
@@ -792,64 +797,66 @@ system.cf0.dma_read_txs                             0                       # Nu
 system.cf0.dma_write_full_pages                     0                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                          0                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
-system.toL2Bus.throughput                    58770672                       # Throughput (bytes/s)
-system.toL2Bus.trans_dist::ReadReq            2743232                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           2743231                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq            769183                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp           769183                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback           583097                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq           35011                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq         18701                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp          53712                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           259154                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          259154                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side       799809                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      1073837                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side        14034                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        57985                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side      1233533                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side      4820063                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side        15283                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side        75701                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               8090245                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     25576064                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     34728353                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side        18500                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        94464                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side     39453888                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side     48201112                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side        22492                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side       132584                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size::total          148227457                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.data_through_bus             148227457                       # Total data (bytes)
-system.toL2Bus.snoop_data_through_bus         4884572                       # Total snoop data (bytes)
-system.toL2Bus.reqLayer0.occupancy         4922251450                       # Layer occupancy (ticks)
+system.toL2Bus.throughput                    57560286                       # Throughput (bytes/s)
+system.toL2Bus.trans_dist::ReadReq            2682607                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp           2682607                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq            768463                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp           768463                       # Transaction distribution
+system.toL2Bus.trans_dist::Writeback           583269                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq           27558                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq         17275                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp          44833                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeFailReq            1                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeFailResp            1                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq           261997                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp          261997                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      1115277                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      2956767                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side        14518                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        50368                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side       879187                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side      2909426                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side        12099                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side        38611                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total               7976253                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     35510400                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     53724619                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side        21456                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        83524                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side     28114656                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side     29015778                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side        17296                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side        62840                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size::total          146550569                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.data_through_bus             146550569                       # Total data (bytes)
+system.toL2Bus.snoop_data_through_bus         4352184                       # Total snoop data (bytes)
+system.toL2Bus.reqLayer0.occupancy         4888594820                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.2                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy        1802620121                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy        2503079453                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy        1515652575                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy        2482730980                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy           9436941                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy           9171959                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy          34537141                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy          29595779                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer6.occupancy        2778792830                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer6.occupancy        1980581418                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer6.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer7.occupancy        3257203486                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer7.occupancy        2244583247                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer7.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer8.occupancy           9681453                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer8.occupancy           7797450                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer8.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer9.occupancy          42845398                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer9.occupancy          22968355                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer9.utilization             0.0                       # Layer utilization (%)
-system.iobus.throughput                      47405592                       # Throughput (bytes/s)
-system.iobus.trans_dist::ReadReq             16322915                       # Transaction distribution
-system.iobus.trans_dist::ReadResp            16322915                       # Transaction distribution
+system.iobus.throughput                      47108999                       # Throughput (bytes/s)
+system.iobus.trans_dist::ReadReq             16322906                       # Transaction distribution
+system.iobus.trans_dist::ReadResp            16322906                       # Transaction distribution
 system.iobus.trans_dist::WriteReq                8083                       # Transaction distribution
 system.iobus.trans_dist::WriteResp               8083                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        30944                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio         8836                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio         8814                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio         1030                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio         1034                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio           36                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          736                       # Packet count per connected master and slave (bytes)
@@ -869,14 +876,14 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total      2384364                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total      2384346                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side     30277632                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.clcd.dma::total     30277632                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                32661996                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                32661978                       # Packet count per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio        40713                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio        17672                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio        17628                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio         2060                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio         2068                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio           72                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio          392                       # Cumulative packet size per connected master and slave (bytes)
@@ -896,18 +903,18 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::total      2392677                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::total      2392641                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side    121110528                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.realview.clcd.dma::total    121110528                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::total            123503205                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.data_through_bus               123503205                       # Total data (bytes)
+system.iobus.tot_pkt_size::total            123503169                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.data_through_bus               123503169                       # Total data (bytes)
 system.iobus.reqLayer0.occupancy             21713000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy              4424000                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy              4413000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer2.occupancy                34000                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy               521000                       # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy               523000                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer4.occupancy                27000                       # Layer occupancy (ticks)
 system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
@@ -949,19 +956,19 @@ system.iobus.reqLayer23.occupancy                8000                       # La
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer25.occupancy         15138816000                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.6                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy          2376281000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy          2376263000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.1                       # Layer utilization (%)
-system.iobus.respLayer1.occupancy         38152801849                       # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy         38168032303                       # Layer occupancy (ticks)
 system.iobus.respLayer1.utilization               1.5                       # Layer utilization (%)
-system.cpu0.branchPred.lookups                6193187                       # Number of BP lookups
-system.cpu0.branchPred.condPredicted          4738042                       # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect           296192                       # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups             3876930                       # Number of BTB lookups
-system.cpu0.branchPred.BTBHits                2986045                       # Number of BTB hits
+system.cpu0.branchPred.lookups                8682194                       # Number of BP lookups
+system.cpu0.branchPred.condPredicted          6490987                       # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect           415813                       # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups             5217710                       # Number of BTB lookups
+system.cpu0.branchPred.BTBHits                4131218                       # Number of BTB hits
 system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct            77.020864                       # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS                 687525                       # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect             28310                       # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct            79.176842                       # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS                 908190                       # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect             19748                       # Number of incorrect RAS predictions.
 system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -985,25 +992,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # D
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                     8977307                       # DTB read hits
-system.cpu0.dtb.read_misses                     29619                       # DTB read misses
-system.cpu0.dtb.write_hits                    5215302                       # DTB write hits
-system.cpu0.dtb.write_misses                     5680                       # DTB write misses
+system.cpu0.dtb.read_hits                    10917771                       # DTB read hits
+system.cpu0.dtb.read_misses                     23643                       # DTB read misses
+system.cpu0.dtb.write_hits                    7767808                       # DTB write hits
+system.cpu0.dtb.write_misses                     8146                       # DTB write misses
 system.cpu0.dtb.flush_tlb                           4                       # Number of times complete TLB was flushed
 system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
 system.cpu0.dtb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.dtb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                    1732                       # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults                      993                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                   285                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_entries                    1721                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults                      163                       # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults                   270                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                      620                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                 9006926                       # DTB read accesses
-system.cpu0.dtb.write_accesses                5220982                       # DTB write accesses
+system.cpu0.dtb.perms_faults                      598                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses                10941414                       # DTB read accesses
+system.cpu0.dtb.write_accesses                7775954                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                         14192609                       # DTB hits
-system.cpu0.dtb.misses                          35299                       # DTB misses
-system.cpu0.dtb.accesses                     14227908                       # DTB accesses
+system.cpu0.dtb.hits                         18685579                       # DTB hits
+system.cpu0.dtb.misses                          31789                       # DTB misses
+system.cpu0.dtb.accesses                     18717368                       # DTB accesses
 system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -1025,8 +1032,8 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.inst_hits                     4299863                       # ITB inst hits
-system.cpu0.itb.inst_misses                      5195                       # ITB inst misses
+system.cpu0.itb.inst_hits                    16449037                       # ITB inst hits
+system.cpu0.itb.inst_misses                      5743                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
@@ -1035,580 +1042,593 @@ system.cpu0.itb.flush_tlb                           4                       # Nu
 system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
 system.cpu0.itb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.itb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                    1219                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_entries                    1206                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults                     1331                       # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults                     2114                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses                 4305058                       # ITB inst accesses
-system.cpu0.itb.hits                          4299863                       # DTB hits
-system.cpu0.itb.misses                           5195                       # DTB misses
-system.cpu0.itb.accesses                      4305058                       # DTB accesses
-system.cpu0.numCycles                        69478980                       # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses                16454780                       # ITB inst accesses
+system.cpu0.itb.hits                         16449037                       # DTB hits
+system.cpu0.itb.misses                           5743                       # DTB misses
+system.cpu0.itb.accesses                     16454780                       # DTB accesses
+system.cpu0.numCycles                       110984158                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles          11944453                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts                      32774113                       # Number of instructions fetch has processed
-system.cpu0.fetch.Branches                    6193187                       # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches           3673570                       # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles                      7678957                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles                1502530                       # Number of cycles fetch has spent squashing
-system.cpu0.fetch.TlbCycles                     63317                       # Number of cycles fetch has spent waiting for tlb
-system.cpu0.fetch.BlockedCycles              19508655                       # Number of cycles fetch has spent blocked
-system.cpu0.fetch.MiscStallCycles                6049                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingTrapStallCycles        47760                       # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles      1413705                       # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles          248                       # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines                  4298413                       # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes               159366                       # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.ItlbSquashes                   2185                       # Number of outstanding ITLB misses that were squashed
-system.cpu0.fetch.rateDist::samples          41753011                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean             1.013655                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev            2.394447                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.icacheStallCycles          29010417                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts                      51007104                       # Number of instructions fetch has processed
+system.cpu0.fetch.Branches                    8682194                       # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches           5039408                       # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles                     76702951                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles                1090474                       # Number of cycles fetch has spent squashing
+system.cpu0.fetch.TlbCycles                     80643                       # Number of cycles fetch has spent waiting for tlb
+system.cpu0.fetch.MiscStallCycles               23949                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingTrapStallCycles        71996                       # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles      1961272                       # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles           13                       # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines                 16450117                       # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes               242573                       # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.ItlbSquashes                   2510                       # Number of outstanding ITLB misses that were squashed
+system.cpu0.fetch.rateDist::samples         108396478                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean             0.561251                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev            1.057421                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0                34081524     81.63%     81.63% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1                  576095      1.38%     83.01% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2                  828597      1.98%     84.99% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3                  688423      1.65%     86.64% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4                  783359      1.88%     88.52% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5                  570610      1.37%     89.88% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6                  698382      1.67%     91.56% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::7                  360373      0.86%     92.42% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::8                 3165648      7.58%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0                80471532     74.24%     74.24% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1                 9354408      8.63%     82.87% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2                 4228353      3.90%     86.77% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3                14342185     13.23%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total            41753011                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate                 0.089138                       # Number of branch fetches per cycle
-system.cpu0.fetch.rate                       0.471713                       # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles                12274082                       # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles             20961054                       # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles                  7066192                       # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles               425731                       # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles               1025952                       # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved              955706                       # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred                65065                       # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts              40945366                       # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts               213036                       # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles               1025952                       # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles                12760478                       # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles                3004976                       # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles      13648632                       # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles                  7041602                       # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles              4271371                       # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts              39802599                       # Number of instructions processed by rename
-system.cpu0.rename.ROBFullEvents                 1199                       # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents               1526731                       # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LQFullEvents               1438820                       # Number of times rename has blocked due to LQ full
-system.cpu0.rename.SQFullEvents               1837389                       # Number of times rename has blocked due to SQ full
-system.cpu0.rename.FullRegisterEvents             522                       # Number of times there has been no free registers
-system.cpu0.rename.RenamedOperands           40279465                       # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups            182145305                       # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups       165318292                       # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups             4116                       # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps             31479900                       # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps                 8799564                       # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts            460456                       # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts        417031                       # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts                  4293085                       # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads             7837564                       # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores            5796369                       # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads          1159621                       # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores         1213862                       # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded                  37649045                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded             906994                       # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued                 37770468                       # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued            93887                       # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined        6620221                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined     14342287                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved        258409                       # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples     41753011                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean        0.904617                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev       1.539726                       # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::max_value               3                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::total           108396478                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate                 0.078229                       # Number of branch fetches per cycle
+system.cpu0.fetch.rate                       0.459589                       # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles                24273364                       # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles             59696324                       # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles                 21865637                       # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles              2148424                       # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles                412729                       # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved             1100967                       # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred               134603                       # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts              56048449                       # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts              1161275                       # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles                412729                       # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles                26181144                       # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles               23163659                       # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles      11818847                       # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles                 22001270                       # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles             24818829                       # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts              54863842                       # Number of instructions processed by rename
+system.cpu0.rename.SquashedInsts               371818                       # Number of squashed instructions processed by rename
+system.cpu0.rename.ROBFullEvents              4330145                       # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents               2622839                       # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LQFullEvents               9842391                       # Number of times rename has blocked due to LQ full
+system.cpu0.rename.SQFullEvents              13156385                       # Number of times rename has blocked due to SQ full
+system.cpu0.rename.RenamedOperands           58083982                       # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups            254404471                       # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups        69151408                       # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups             3820                       # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps             54276662                       # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps                 3807314                       # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts            540800                       # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts        442723                       # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts                  4591136                       # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads             9492850                       # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores            8297955                       # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads           506397                       # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores          589876                       # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded                  53569882                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded             859573                       # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued                 55433156                       # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued           105167                       # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined        2762956                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined      5503873                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved         84823                       # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples    108396478                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean        0.511393                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev       0.864824                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0           26686839     63.92%     63.92% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1            5690671     13.63%     77.55% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2            3035101      7.27%     84.81% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3            2408430      5.77%     90.58% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4            2094356      5.02%     95.60% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5             953036      2.28%     97.88% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::6             611124      1.46%     99.35% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::7             212675      0.51%     99.85% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::8              60779      0.15%    100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0           74367725     68.61%     68.61% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1           17769290     16.39%     85.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2           11558620     10.66%     95.66% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3            4256755      3.93%     99.59% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4             444079      0.41%    100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5                  9      0.00%    100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::6                  0      0.00%    100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::7                  0      0.00%    100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::8                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total       41753011                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total      108396478                       # Number of insts issued each cycle
 system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu                  29050      2.58%      2.58% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult                   460      0.04%      2.62% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv                      0      0.00%      2.62% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd                    0      0.00%      2.62% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp                    0      0.00%      2.62% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt                    0      0.00%      2.62% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult                   0      0.00%      2.62% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv                    0      0.00%      2.62% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%      2.62% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd                     0      0.00%      2.62% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%      2.62% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu                     0      0.00%      2.62% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp                     0      0.00%      2.62% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt                     0      0.00%      2.62% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc                    0      0.00%      2.62% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult                    0      0.00%      2.62% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%      2.62% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift                   0      0.00%      2.62% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%      2.62% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%      2.62% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%      2.62% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%      2.62% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%      2.62% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%      2.62% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%      2.62% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%      2.62% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%      2.62% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%      2.62% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%      2.62% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead                862862     76.64%     79.26% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite               233562     20.74%    100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu                3788078     33.87%     33.87% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult                   172      0.00%     33.87% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv                      0      0.00%     33.87% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     33.87% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     33.87% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     33.87% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult                   0      0.00%     33.87% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     33.87% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     33.87% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     33.87% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     33.87% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     33.87% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     33.87% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     33.87% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     33.87% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult                    0      0.00%     33.87% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     33.87% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift                   0      0.00%     33.87% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     33.87% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     33.87% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     33.87% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     33.87% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     33.87% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     33.87% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     33.87% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     33.87% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     33.87% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     33.87% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     33.87% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead               3595287     32.14%     66.01% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite              3801407     33.99%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu0.iq.FU_type_0::No_OpClass            14549      0.04%      0.04% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu             22728130     60.17%     60.21% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult               48220      0.13%     60.34% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     60.34% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     60.34% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     60.34% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     60.34% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     60.34% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     60.34% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     60.34% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     60.34% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     60.34% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu                   1      0.00%     60.34% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     60.34% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     60.34% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc                 11      0.00%     60.34% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     60.34% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     60.34% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     60.34% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc              8      0.00%     60.34% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     60.34% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     60.34% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     60.34% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     60.34% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     60.34% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     60.34% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc           680      0.00%     60.34% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     60.34% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc           11      0.00%     60.34% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     60.34% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead             9442602     25.00%     85.34% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite            5536256     14.66%    100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::No_OpClass            14948      0.03%      0.03% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu             35826739     64.63%     64.66% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult               64782      0.12%     64.77% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     64.77% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     64.77% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     64.77% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     64.77% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     64.77% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     64.77% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     64.77% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     64.77% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     64.77% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     64.77% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     64.77% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     64.77% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     64.77% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     64.77% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     64.77% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     64.77% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     64.77% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     64.77% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     64.77% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     64.77% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     64.77% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     64.77% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     64.77% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc           722      0.00%     64.78% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     64.78% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     64.78% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     64.78% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead            11302035     20.39%     85.16% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite            8223930     14.84%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total              37770468                       # Type of FU issued
-system.cpu0.iq.rate                          0.543624                       # Inst issue rate
-system.cpu0.iq.fu_busy_cnt                    1125934                       # FU busy when requested
-system.cpu0.iq.fu_busy_rate                  0.029810                       # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads         118540397                       # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes         45184408                       # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses     34905571                       # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads               8382                       # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes              4748                       # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses         3872                       # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses              38877516                       # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses                   4337                       # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads          330330                       # Number of loads that had data forwarded from stores
+system.cpu0.iq.FU_type_0::total              55433156                       # Type of FU issued
+system.cpu0.iq.rate                          0.499469                       # Inst issue rate
+system.cpu0.iq.fu_busy_cnt                   11184944                       # FU busy when requested
+system.cpu0.iq.fu_busy_rate                  0.201774                       # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads         230540772                       # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes         57191232                       # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses     52885161                       # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads              12129                       # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes              4604                       # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_wakeup_accesses         3838                       # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.int_alu_accesses              66595213                       # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses                   7939                       # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads          146965                       # Number of loads that had data forwarded from stores
 system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads      1458060                       # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses         2363                       # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation        13414                       # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores       565962                       # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads       634189                       # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses          503                       # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation         3442                       # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores       242149                       # Number of stores squashed
 system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads      2141820                       # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked         5981                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.rescheduledLoads      1082260                       # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked      1003693                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles               1025952                       # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles                2385802                       # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles               275075                       # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts           38676599                       # Number of instructions dispatched to IQ
-system.cpu0.iew.iewDispSquashedInsts            76106                       # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts              7837564                       # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts             5796369                       # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts            579111                       # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents                 58653                       # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents               199282                       # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents         13414                       # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect        149919                       # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect       118426                       # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts              268345                       # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts             37387044                       # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts              9294285                       # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts           383424                       # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewSquashCycles                412729                       # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles                7302695                       # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles              6441595                       # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts           54523303                       # Number of instructions dispatched to IQ
+system.cpu0.iew.iewDispSquashedInsts                0                       # Number of squashed instructions skipped by dispatch
+system.cpu0.iew.iewDispLoadInsts              9492850                       # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts             8297955                       # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts            524870                       # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents                 12318                       # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents              6420937                       # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents          3442                       # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect        134210                       # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect       165432                       # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts              299642                       # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts             55026621                       # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts             11133456                       # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts           374843                       # Number of squashed instructions skipped in execute
 system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu0.iew.exec_nop                       120560                       # number of nop insts executed
-system.cpu0.iew.exec_refs                    14782259                       # number of memory reference insts executed
-system.cpu0.iew.exec_branches                 4971290                       # Number of branches executed
-system.cpu0.iew.exec_stores                   5487974                       # Number of stores executed
-system.cpu0.iew.exec_rate                    0.538106                       # Inst execution rate
-system.cpu0.iew.wb_sent                      37190474                       # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count                     34909443                       # cumulative count of insts written-back
-system.cpu0.iew.wb_producers                 18996365                       # num instructions producing a value
-system.cpu0.iew.wb_consumers                 36943291                       # num instructions consuming a value
+system.cpu0.iew.exec_nop                        93848                       # number of nop insts executed
+system.cpu0.iew.exec_refs                    19301977                       # number of memory reference insts executed
+system.cpu0.iew.exec_branches                 7332190                       # Number of branches executed
+system.cpu0.iew.exec_stores                   8168521                       # Number of stores executed
+system.cpu0.iew.exec_rate                    0.495806                       # Inst execution rate
+system.cpu0.iew.wb_sent                      54039254                       # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count                     52888999                       # cumulative count of insts written-back
+system.cpu0.iew.wb_producers                 25110485                       # num instructions producing a value
+system.cpu0.iew.wb_consumers                 37735585                       # num instructions consuming a value
 system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu0.iew.wb_rate                      0.502446                       # insts written-back per cycle
-system.cpu0.iew.wb_fanout                    0.514203                       # average fanout of values written-back
+system.cpu0.iew.wb_rate                      0.476545                       # insts written-back per cycle
+system.cpu0.iew.wb_fanout                    0.665433                       # average fanout of values written-back
 system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.commit.commitSquashedInsts        6443412                       # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls         648585                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts           232277                       # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples     40727059                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean     0.780301                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev     1.748318                       # Number of insts commited each cycle
+system.cpu0.commit.commitSquashedInsts        2480238                       # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls         774750                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts           283305                       # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples    107840192                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean     0.477624                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev     1.224539                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0     28935599     71.05%     71.05% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1      5796697     14.23%     85.28% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2      1842943      4.53%     89.81% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3      1067095      2.62%     92.43% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4       737891      1.81%     94.24% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5       511993      1.26%     95.49% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6       448684      1.10%     96.60% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7       197374      0.48%     97.08% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8      1188783      2.92%    100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0     82912194     76.88%     76.88% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1     14339479     13.30%     90.18% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2      5152045      4.78%     94.96% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3      1572745      1.46%     96.42% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4      1370622      1.27%     97.69% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5       690625      0.64%     98.33% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6       401555      0.37%     98.70% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7       407085      0.38%     99.08% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8       993842      0.92%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total     40727059                       # Number of insts commited each cycle
-system.cpu0.commit.committedInsts            24067678                       # Number of instructions committed
-system.cpu0.commit.committedOps              31779383                       # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total    107840192                       # Number of insts commited each cycle
+system.cpu0.commit.committedInsts            43173906                       # Number of instructions committed
+system.cpu0.commit.committedOps              51507078                       # Number of ops (including micro ops) committed
 system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu0.commit.refs                      11609911                       # Number of memory references committed
-system.cpu0.commit.loads                      6379504                       # Number of loads committed
-system.cpu0.commit.membars                     231786                       # Number of memory barriers committed
-system.cpu0.commit.branches                   4350837                       # Number of branches committed
+system.cpu0.commit.refs                      16914467                       # Number of memory references committed
+system.cpu0.commit.loads                      8858661                       # Number of loads committed
+system.cpu0.commit.membars                     263890                       # Number of memory barriers committed
+system.cpu0.commit.branches                   7043091                       # Number of branches committed
 system.cpu0.commit.fp_insts                      3838                       # Number of committed floating point instructions.
-system.cpu0.commit.int_insts                 28125415                       # Number of committed integer instructions.
-system.cpu0.commit.function_calls              498912                       # Number of function calls committed.
+system.cpu0.commit.int_insts                 45505753                       # Number of committed integer instructions.
+system.cpu0.commit.function_calls              666034                       # Number of function calls committed.
 system.cpu0.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntAlu        20129006     63.34%     63.34% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntMult          39786      0.13%     63.47% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntDiv               0      0.00%     63.47% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     63.47% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     63.47% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     63.47% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatMult            0      0.00%     63.47% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     63.47% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     63.47% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     63.47% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     63.47% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     63.47% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     63.47% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     63.47% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     63.47% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMult             0      0.00%     63.47% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     63.47% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShift            0      0.00%     63.47% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     63.47% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     63.47% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     63.47% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     63.47% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     63.47% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     63.47% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     63.47% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMisc          680      0.00%     63.47% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     63.47% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     63.47% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     63.47% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemRead        6379504     20.07%     83.54% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemWrite       5230407     16.46%    100.00% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntAlu        34530023     67.04%     67.04% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntMult          61866      0.12%     67.16% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntDiv               0      0.00%     67.16% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     67.16% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     67.16% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     67.16% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatMult            0      0.00%     67.16% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     67.16% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     67.16% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     67.16% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     67.16% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     67.16% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     67.16% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     67.16% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     67.16% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMult             0      0.00%     67.16% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     67.16% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShift            0      0.00%     67.16% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     67.16% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     67.16% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     67.16% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     67.16% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     67.16% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     67.16% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     67.16% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMisc          722      0.00%     67.16% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     67.16% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     67.16% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     67.16% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemRead        8858661     17.20%     84.36% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemWrite       8055806     15.64%    100.00% # Class of committed instruction
 system.cpu0.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::total         31779383                       # Class of committed instruction
-system.cpu0.commit.bw_lim_events              1188783                       # number cycles where commit BW limit reached
+system.cpu0.commit.op_class_0::total         51507078                       # Class of committed instruction
+system.cpu0.commit.bw_lim_events               993842                       # number cycles where commit BW limit reached
 system.cpu0.commit.bw_limited                       0                       # number of insts not committed due to BW limits
-system.cpu0.rob.rob_reads                    76892389                       # The number of ROB reads
-system.cpu0.rob.rob_writes                   77473478                       # The number of ROB writes
-system.cpu0.timesIdled                         368167                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles                       27725969                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.quiesceCycles                  5140969387                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.committedInsts                   23986936                       # Number of Instructions Simulated
-system.cpu0.committedOps                     31698641                       # Number of Ops (including micro ops) Simulated
-system.cpu0.cpi                              2.896534                       # CPI: Cycles Per Instruction
-system.cpu0.cpi_total                        2.896534                       # CPI: Total CPI of All Threads
-system.cpu0.ipc                              0.345240                       # IPC: Instructions Per Cycle
-system.cpu0.ipc_total                        0.345240                       # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads               174527841                       # number of integer regfile reads
-system.cpu0.int_regfile_writes               34672219                       # number of integer regfile writes
-system.cpu0.fp_regfile_reads                     3319                       # number of floating regfile reads
-system.cpu0.fp_regfile_writes                     920                       # number of floating regfile writes
-system.cpu0.misc_regfile_reads               78617689                       # number of misc regfile reads
-system.cpu0.misc_regfile_writes                500675                       # number of misc regfile writes
-system.cpu0.icache.tags.replacements           399525                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.581560                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs            3866760                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs           400037                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs             9.666006                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle       6951542250                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.581560                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999183                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.999183                       # Average percentage of cache occupancy
+system.cpu0.rob.rob_reads                   159811836                       # The number of ROB reads
+system.cpu0.rob.rob_writes                  108530018                       # The number of ROB writes
+system.cpu0.timesIdled                         338876                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.idleCycles                        2587680                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.quiesceCycles                  5132257518                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.committedInsts                   43093164                       # Number of Instructions Simulated
+system.cpu0.committedOps                     51426336                       # Number of Ops (including micro ops) Simulated
+system.cpu0.cpi                              2.575447                       # CPI: Cycles Per Instruction
+system.cpu0.cpi_total                        2.575447                       # CPI: Total CPI of All Threads
+system.cpu0.ipc                              0.388282                       # IPC: Instructions Per Cycle
+system.cpu0.ipc_total                        0.388282                       # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads                67127966                       # number of integer regfile reads
+system.cpu0.int_regfile_writes               33211893                       # number of integer regfile writes
+system.cpu0.fp_regfile_reads                     3352                       # number of floating regfile reads
+system.cpu0.fp_regfile_writes                     840                       # number of floating regfile writes
+system.cpu0.cc_regfile_reads                191848471                       # number of cc regfile reads
+system.cpu0.cc_regfile_writes                22040987                       # number of cc regfile writes
+system.cpu0.misc_regfile_reads              169210728                       # number of misc regfile reads
+system.cpu0.misc_regfile_writes                593502                       # number of misc regfile writes
+system.cpu0.icache.tags.replacements           554010                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.387606                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs           15866984                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs           554522                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            28.613804                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle      18806389250                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.387606                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.998804                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.998804                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0          132                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          209                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2          168                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::3            3                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0          123                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1          152                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2          231                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::3            6                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses          4698333                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses         4698333                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst      3866760                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total        3866760                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst      3866760                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total         3866760                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst      3866760                       # number of overall hits
-system.cpu0.icache.overall_hits::total        3866760                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst       431519                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total       431519                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst       431519                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total        431519                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst       431519                       # number of overall misses
-system.cpu0.icache.overall_misses::total       431519                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst   5963742706                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total   5963742706                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst   5963742706                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total   5963742706                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst   5963742706                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total   5963742706                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst      4298279                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total      4298279                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst      4298279                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total      4298279                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst      4298279                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total      4298279                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.100393                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.100393                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.100393                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.100393                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.100393                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.100393                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13820.347901                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 13820.347901                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13820.347901                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 13820.347901                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13820.347901                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 13820.347901                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs         4778                       # number of cycles access was blocked
+system.cpu0.icache.tags.tag_accesses         17001271                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses        17001271                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst     15866984                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total       15866984                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst     15866984                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total        15866984                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst     15866984                       # number of overall hits
+system.cpu0.icache.overall_hits::total       15866984                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst       579761                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total       579761                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst       579761                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total        579761                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst       579761                       # number of overall misses
+system.cpu0.icache.overall_misses::total       579761                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst   8029558142                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total   8029558142                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst   8029558142                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total   8029558142                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst   8029558142                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total   8029558142                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst     16446745                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total     16446745                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst     16446745                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total     16446745                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst     16446745                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total     16446745                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.035251                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.035251                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.035251                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.035251                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.035251                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.035251                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13849.772824                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 13849.772824                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13849.772824                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 13849.772824                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13849.772824                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 13849.772824                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs          739                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs              162                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs               55                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs    29.493827                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs    13.436364                       # average number of cycles each access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        31464                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total        31464                       # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu0.inst        31464                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total        31464                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu0.inst        31464                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total        31464                       # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       400055                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total       400055                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst       400055                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total       400055                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst       400055                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total       400055                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   4860147872                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total   4860147872                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   4860147872                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total   4860147872                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   4860147872                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total   4860147872                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst      9713500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total      9713500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst      9713500                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::total      9713500                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.093073                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.093073                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.093073                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.093073                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.093073                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.093073                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12148.699234                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12148.699234                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12148.699234                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 12148.699234                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12148.699234                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 12148.699234                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        25235                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total        25235                       # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu0.inst        25235                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total        25235                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu0.inst        25235                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total        25235                       # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       554526                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total       554526                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst       554526                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total       554526                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst       554526                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total       554526                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   6629844046                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total   6629844046                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   6629844046                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total   6629844046                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   6629844046                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total   6629844046                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    226658500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total    226658500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    226658500                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::total    226658500                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.033716                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.033716                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.033716                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.033716                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.033716                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.033716                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11955.875912                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11955.875912                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11955.875912                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 11955.875912                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11955.875912                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 11955.875912                       # average overall mshr miss latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.dcache.tags.replacements           275167                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          480.361699                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs            9408418                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs           275679                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            34.128164                       # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle         42907250                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   480.361699                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.938206                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.938206                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.replacements           409126                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          483.194796                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs           12942599                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs           409638                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            31.595211                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.warmup_cycle        271704250                       # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   483.194796                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.943740                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.943740                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0          175                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          313                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           24                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0          146                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          346                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           19                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses         45804428                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses        45804428                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data      5867272                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total        5867272                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data      3220606                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total       3220606                       # number of WriteReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       139465                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       139465                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       137168                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       137168                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data      9087878                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total         9087878                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data      9087878                       # number of overall hits
-system.cpu0.dcache.overall_hits::total        9087878                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data       403110                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total       403110                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data      1588797                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total      1588797                       # number of WriteReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         8920                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total         8920                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data         7758                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total         7758                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data      1991907                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       1991907                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data      1991907                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      1991907                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   5653636758                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total   5653636758                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  74855868606                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total  74855868606                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data     91362982                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total     91362982                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data     50049767                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total     50049767                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data  80509505364                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total  80509505364                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data  80509505364                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total  80509505364                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data      6270382                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total      6270382                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data      4809403                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total      4809403                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       148385                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       148385                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       144926                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       144926                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data     11079785                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     11079785                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data     11079785                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     11079785                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.064288                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.064288                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.330352                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.330352                       # miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.060114                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.060114                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.053531                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.053531                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.179778                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.179778                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.179778                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.179778                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14025.047153                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 14025.047153                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 47114.809888                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 47114.809888                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10242.486771                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10242.486771                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data  6451.374968                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total  6451.374968                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 40418.305355                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 40418.305355                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 40418.305355                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 40418.305355                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs         9294                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets         6492                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs              635                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets            113                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs    14.636220                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets    57.451327                       # average number of cycles each access was blocked
+system.cpu0.dcache.tags.tag_accesses         63030887                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses        63030887                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data      8037454                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total        8037454                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data      4509267                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total       4509267                       # number of WriteReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu0.data        46089                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::total        46089                       # number of SoftPFReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       156971                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       156971                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data       159079                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       159079                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data     12546721                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total        12546721                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data     12592810                       # number of overall hits
+system.cpu0.dcache.overall_hits::total       12592810                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data       406720                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total       406720                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data      2221250                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total      2221250                       # number of WriteReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu0.data        92142                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::total        92142                       # number of SoftPFReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        10979                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total        10979                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data         7659                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total         7659                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data      2627970                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total       2627970                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data      2720112                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      2720112                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   5668958645                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total   5668958645                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 107130503686                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total 107130503686                       # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    114563996                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total    114563996                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data     44413016                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total     44413016                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data 112799462331                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total 112799462331                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data 112799462331                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total 112799462331                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data      8444174                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total      8444174                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data      6730517                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total      6730517                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       138231                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total       138231                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       167950                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       167950                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       166738                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       166738                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data     15174691                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     15174691                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data     15312922                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     15312922                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.048166                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.048166                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.330027                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.330027                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.666580                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.666580                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.065371                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.065371                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.045934                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.045934                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.173181                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.173181                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.177635                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.177635                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13938.234277                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 13938.234277                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 48229.827208                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 48229.827208                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10434.829766                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10434.829766                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data  5798.800888                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total  5798.800888                       # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 42922.659821                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 42922.659821                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 41468.683029                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 41468.683029                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs        14275                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs             1041                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs    13.712776                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       255545                       # number of writebacks
-system.cpu0.dcache.writebacks::total           255545                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       213826                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total       213826                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1457949                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total      1457949                       # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data          469                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total          469                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data      1671775                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total      1671775                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data      1671775                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total      1671775                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       189284                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       189284                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       130848                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       130848                       # number of WriteReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         8451                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total         8451                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data         7758                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total         7758                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data       320132                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total       320132                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data       320132                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total       320132                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   2416725188                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total   2416725188                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   5154000431                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total   5154000431                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     69605516                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     69605516                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data     34529233                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total     34529233                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   7570725619                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total   7570725619                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data   7570725619                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total   7570725619                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data  13434660545                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total  13434660545                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   1206058380                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   1206058380                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data  14640718925                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total  14640718925                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.030187                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.030187                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.027207                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.027207                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.056953                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.056953                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.053531                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.053531                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.028893                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.028893                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.028893                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.028893                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12767.720399                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12767.720399                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 39389.218261                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 39389.218261                       # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data  8236.364454                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total  8236.364454                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data  4450.790539                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total  4450.790539                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23648.762445                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23648.762445                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23648.762445                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23648.762445                       # average overall mshr miss latency
+system.cpu0.dcache.writebacks::writebacks       375988                       # number of writebacks
+system.cpu0.dcache.writebacks::total           375988                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       193747                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total       193747                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      2045363                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total      2045363                       # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data         1054                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total         1054                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data      2239110                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total      2239110                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data      2239110                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total      2239110                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       212973                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total       212973                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       175887                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       175887                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data        54623                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total        54623                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         9925                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total         9925                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data         7659                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total         7659                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data       388860                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total       388860                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data       443483                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total       443483                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   2487825853                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total   2487825853                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   7369362883                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total   7369362883                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data   1035896777                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1035896777                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     82981003                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     82981003                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data     29093984                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total     29093984                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   9857188736                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total   9857188736                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  10893085513                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  10893085513                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data  13737621002                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total  13737621002                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data  26275689041                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total  26275689041                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data  40013310043                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total  40013310043                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.025221                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.025221                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.026133                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.026133                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.395157                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.395157                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.059095                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.059095                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.045934                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.045934                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.025626                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.025626                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.028961                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.028961                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11681.414325                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11681.414325                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 41898.280618                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 41898.280618                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 18964.479743                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 18964.479743                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data  8360.806348                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total  8360.806348                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data  3798.666144                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total  3798.666144                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 25348.939814                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25348.939814                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24562.577400                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24562.577400                       # average overall mshr miss latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
@@ -1616,15 +1636,15 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf
 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.branchPred.lookups                9402679                       # Number of BP lookups
-system.cpu1.branchPred.condPredicted          7728805                       # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect           418099                       # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups             6037829                       # Number of BTB lookups
-system.cpu1.branchPred.BTBHits                5108046                       # Number of BTB hits
+system.cpu1.branchPred.lookups                5001209                       # Number of BP lookups
+system.cpu1.branchPred.condPredicted          3530067                       # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect           291977                       # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups             3184313                       # Number of BTB lookups
+system.cpu1.branchPred.BTBHits                2141032                       # Number of BTB hits
 system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct            84.600707                       # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS                 802186                       # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect             44176                       # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct            67.236858                       # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS                 582225                       # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect             13211                       # Number of incorrect RAS predictions.
 system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -1648,25 +1668,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # D
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                    42878527                       # DTB read hits
-system.cpu1.dtb.read_misses                     38253                       # DTB read misses
-system.cpu1.dtb.write_hits                    6985734                       # DTB write hits
-system.cpu1.dtb.write_misses                    10793                       # DTB write misses
+system.cpu1.dtb.read_hits                    21293354                       # DTB read hits
+system.cpu1.dtb.read_misses                     17527                       # DTB read misses
+system.cpu1.dtb.write_hits                    4063342                       # DTB write hits
+system.cpu1.dtb.write_misses                     3266                       # DTB write misses
 system.cpu1.dtb.flush_tlb                           4                       # Number of times complete TLB was flushed
 system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
 system.cpu1.dtb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.dtb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                    1922                       # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults                     2963                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                   279                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.flush_entries                    1908                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults                      789                       # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults                   274                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                      687                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                42916780                       # DTB read accesses
-system.cpu1.dtb.write_accesses                6996527                       # DTB write accesses
+system.cpu1.dtb.perms_faults                      694                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses                21310881                       # DTB read accesses
+system.cpu1.dtb.write_accesses                4066608                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                         49864261                       # DTB hits
-system.cpu1.dtb.misses                          49046                       # DTB misses
-system.cpu1.dtb.accesses                     49913307                       # DTB accesses
+system.cpu1.dtb.hits                         25356696                       # DTB hits
+system.cpu1.dtb.misses                          20793                       # DTB misses
+system.cpu1.dtb.accesses                     25377489                       # DTB accesses
 system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -1688,8 +1708,8 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.inst_hits                     7755980                       # ITB inst hits
-system.cpu1.itb.inst_misses                      5491                       # ITB inst misses
+system.cpu1.itb.inst_hits                     8626509                       # ITB inst hits
+system.cpu1.itb.inst_misses                      4363                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
@@ -1698,579 +1718,595 @@ system.cpu1.itb.flush_tlb                           4                       # Nu
 system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
 system.cpu1.itb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.itb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                    1362                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries                    1319                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults                     1507                       # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults                     2055                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses                 7761471                       # ITB inst accesses
-system.cpu1.itb.hits                          7755980                       # DTB hits
-system.cpu1.itb.misses                           5491                       # DTB misses
-system.cpu1.itb.accesses                      7761471                       # DTB accesses
-system.cpu1.numCycles                       413132210                       # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses                 8630872                       # ITB inst accesses
+system.cpu1.itb.hits                          8626509                       # DTB hits
+system.cpu1.itb.misses                           4363                       # DTB misses
+system.cpu1.itb.accesses                      8630872                       # DTB accesses
+system.cpu1.numCycles                       396849081                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles          19420388                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts                      61788688                       # Number of instructions fetch has processed
-system.cpu1.fetch.Branches                    9402679                       # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches           5910232                       # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles                     13466568                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles                3411318                       # Number of cycles fetch has spent squashing
-system.cpu1.fetch.TlbCycles                     67616                       # Number of cycles fetch has spent waiting for tlb
-system.cpu1.fetch.BlockedCycles              77041165                       # Number of cycles fetch has spent blocked
-system.cpu1.fetch.MiscStallCycles                5941                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingTrapStallCycles        42813                       # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles      1523639                       # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles          257                       # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines                  7754163                       # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes               555305                       # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.ItlbSquashes                   2851                       # Number of outstanding ITLB misses that were squashed
-system.cpu1.fetch.rateDist::samples         113918823                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean             0.663934                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev            1.994464                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.icacheStallCycles          18444788                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts                      25760845                       # Number of instructions fetch has processed
+system.cpu1.fetch.Branches                    5001209                       # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches           2723257                       # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles                    375027882                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles                 802688                       # Number of cycles fetch has spent squashing
+system.cpu1.fetch.TlbCycles                     60706                       # Number of cycles fetch has spent waiting for tlb
+system.cpu1.fetch.MiscStallCycles               28139                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingTrapStallCycles        75697                       # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles      1303305                       # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.CacheLines                  8624270                       # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes               181619                       # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.ItlbSquashes                   1774                       # Number of outstanding ITLB misses that were squashed
+system.cpu1.fetch.rateDist::samples         395341861                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean             0.079415                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev            0.442124                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0               100459727     88.19%     88.19% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1                  820479      0.72%     88.91% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2                  969052      0.85%     89.76% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3                 1718827      1.51%     91.27% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4                 1427854      1.25%     92.52% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5                  590556      0.52%     93.04% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6                 1988498      1.75%     94.78% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7                  426289      0.37%     95.16% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8                 5517541      4.84%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0               380851246     96.33%     96.33% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1                 4867429      1.23%     97.57% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2                 2340779      0.59%     98.16% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3                 7282407      1.84%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total           113918823                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate                 0.022759                       # Number of branch fetches per cycle
-system.cpu1.fetch.rate                       0.149562                       # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles                20573629                       # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles             78271180                       # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles                 12141436                       # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles               681674                       # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles               2250904                       # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved             1146333                       # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred               101070                       # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts              71648546                       # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts               337709                       # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles               2250904                       # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles                21753755                       # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles               11785871                       # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles      44839476                       # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles                 11758144                       # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles             21530673                       # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts              67615561                       # Number of instructions processed by rename
-system.cpu1.rename.ROBFullEvents                  613                       # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents              15671923                       # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LQFullEvents              18336953                       # Number of times rename has blocked due to LQ full
-system.cpu1.rename.SQFullEvents               1545811                       # Number of times rename has blocked due to SQ full
-system.cpu1.rename.FullRegisterEvents            1295                       # Number of times there has been no free registers
-system.cpu1.rename.RenamedOperands           71310682                       # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups            315205355                       # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups       288681323                       # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups             6622                       # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps             50413608                       # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps                20897074                       # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts            766814                       # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts        706637                       # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts                  7207016                       # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads            12951593                       # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores            8155935                       # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads          1106689                       # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores         1533453                       # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded                  62295252                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded            1184366                       # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued                 88905891                       # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued           106644                       # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined       13983630                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined     37714490                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved        285025                       # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples    113918823                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean        0.780432                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev       1.530885                       # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::max_value               3                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::total           395341861                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate                 0.012602                       # Number of branch fetches per cycle
+system.cpu1.fetch.rate                       0.064913                       # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles                15111141                       # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles            368322319                       # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles                  9619404                       # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles              1988623                       # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles                300374                       # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved              680085                       # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred               102949                       # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts              27336312                       # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts               828595                       # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles                300374                       # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles                16508550                       # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles              196017158                       # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles      17889321                       # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles                  9851688                       # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles            154774770                       # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts              26427025                       # Number of instructions processed by rename
+system.cpu1.rename.SquashedInsts               243114                       # Number of squashed instructions processed by rename
+system.cpu1.rename.ROBFullEvents             56891125                       # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents              39780893                       # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LQFullEvents             150628157                       # Number of times rename has blocked due to LQ full
+system.cpu1.rename.SQFullEvents               2138867                       # Number of times rename has blocked due to SQ full
+system.cpu1.rename.RenamedOperands           27113530                       # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups            124075273                       # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups        31437770                       # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups             6241                       # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps             24483458                       # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps                 2630072                       # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts            642693                       # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts        559165                       # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts                  4862604                       # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads             5657845                       # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores            4330093                       # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads           343073                       # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores          498131                       # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded                  25260320                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded             861912                       # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued                 41442639                       # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued            78274                       # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined        1902061                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined      3789747                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved         92749                       # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples    395341861                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean        0.104827                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev       0.383209                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0           83813472     73.57%     73.57% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1            8528665      7.49%     81.06% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2            3988574      3.50%     84.56% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3            3433815      3.01%     87.58% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4           10704573      9.40%     96.97% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5            1891022      1.66%     98.63% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::6            1169449      1.03%     99.66% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::7             305487      0.27%     99.93% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::8              83766      0.07%    100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0          362283147     91.64%     91.64% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1           26570133      6.72%     98.36% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2            4792582      1.21%     99.57% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3            1496663      0.38%     99.95% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4             199327      0.05%    100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5                  9      0.00%    100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::6                  0      0.00%    100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::7                  0      0.00%    100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::8                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total      113918823                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total      395341861                       # Number of insts issued each cycle
 system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu                  34951      0.44%      0.44% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult                   989      0.01%      0.45% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv                      0      0.00%      0.45% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      0.45% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      0.45% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      0.45% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult                   0      0.00%      0.45% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      0.45% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      0.45% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      0.45% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      0.45% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      0.45% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      0.45% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      0.45% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      0.45% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult                    0      0.00%      0.45% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      0.45% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift                   0      0.00%      0.45% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      0.45% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      0.45% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      0.45% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      0.45% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      0.45% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      0.45% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      0.45% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      0.45% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      0.45% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      0.45% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      0.45% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead               7593663     95.44%     95.90% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite               326577      4.10%    100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu                1195141      5.96%      5.96% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult                   685      0.00%      5.96% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv                      0      0.00%      5.96% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      5.96% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      5.96% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      5.96% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult                   0      0.00%      5.96% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      5.96% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      5.96% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      5.96% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      5.96% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      5.96% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      5.96% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      5.96% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      5.96% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult                    0      0.00%      5.96% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      5.96% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift                   0      0.00%      5.96% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      5.96% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      5.96% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      5.96% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      5.96% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      5.96% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      5.96% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      5.96% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      5.96% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      5.96% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      5.96% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      5.96% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead              16909984     84.32%     90.29% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite              1947822      9.71%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu1.iq.FU_type_0::No_OpClass            14267      0.02%      0.02% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu             37698483     42.40%     42.42% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult               61348      0.07%     42.49% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     42.49% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     42.49% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     42.49% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     42.49% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     42.49% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     42.49% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     42.49% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     42.49% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     42.49% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     42.49% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     42.49% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     42.49% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc                 12      0.00%     42.49% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     42.49% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     42.49% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     42.49% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc             10      0.00%     42.49% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     42.49% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     42.49% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     42.49% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     42.49% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     42.49% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     42.49% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc          1706      0.00%     42.49% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     42.49% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc           10      0.00%     42.49% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     42.49% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead            43772925     49.24%     91.72% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite            7357130      8.28%    100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::No_OpClass            13868      0.03%      0.03% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu             15563362     37.55%     37.59% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult               33954      0.08%     37.67% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     37.67% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     37.67% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     37.67% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     37.67% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     37.67% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     37.67% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     37.67% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     37.67% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     37.67% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     37.67% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     37.67% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     37.67% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     37.67% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     37.67% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     37.67% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     37.67% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     37.67% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     37.67% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     37.67% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     37.67% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     37.67% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     37.67% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     37.67% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc          1648      0.00%     37.67% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     37.67% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     37.67% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     37.67% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead            21553207     52.01%     89.68% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite            4276600     10.32%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total              88905891                       # Type of FU issued
-system.cpu1.iq.rate                          0.215200                       # Inst issue rate
-system.cpu1.iq.fu_busy_cnt                    7956180                       # FU busy when requested
-system.cpu1.iq.fu_busy_rate                  0.089490                       # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads         299826864                       # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes         77472999                       # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses     54370047                       # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads              15424                       # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes              8128                       # Number of floating instruction queue writes
-system.cpu1.iq.fp_inst_queue_wakeup_accesses         6867                       # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses              96839621                       # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses                   8183                       # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads          371805                       # Number of loads that had data forwarded from stores
+system.cpu1.iq.FU_type_0::total              41442639                       # Type of FU issued
+system.cpu1.iq.rate                          0.104429                       # Inst issue rate
+system.cpu1.iq.fu_busy_cnt                   20053632                       # FU busy when requested
+system.cpu1.iq.fu_busy_rate                  0.483889                       # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads         498337881                       # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes         28019357                       # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses     25018416                       # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads              21164                       # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_writes              7936                       # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_wakeup_accesses         6759                       # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.int_alu_accesses              61468547                       # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses                  13856                       # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads           72058                       # Number of loads that had data forwarded from stores
 system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads      2971595                       # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses         3826                       # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation        18443                       # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores      1153168                       # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads       455146                       # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses          306                       # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation         3014                       # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores       163146                       # Number of stores squashed
 system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads     31846626                       # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked       675699                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread0.rescheduledLoads     15996057                       # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked         1487                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles               2250904                       # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles                9489416                       # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles              1235015                       # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts           63585663                       # Number of instructions dispatched to IQ
-system.cpu1.iew.iewDispSquashedInsts           104803                       # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts             12951593                       # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts             8155935                       # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts            886916                       # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents                232294                       # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents               885959                       # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents         18443                       # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect        206591                       # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect       158855                       # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts              365446                       # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts             87166570                       # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts             43262018                       # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts          1739321                       # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewSquashCycles                300374                       # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles               87167513                       # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles             92299631                       # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts           26204459                       # Number of instructions dispatched to IQ
+system.cpu1.iew.iewDispSquashedInsts                0                       # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispLoadInsts              5657845                       # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts             4330093                       # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts            630570                       # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents                  9334                       # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents             92232105                       # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents          3014                       # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect         83298                       # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect       118271                       # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts              201569                       # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts             41178523                       # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts             21441390                       # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts           243431                       # Number of squashed instructions skipped in execute
 system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu1.iew.exec_nop                       106045                       # number of nop insts executed
-system.cpu1.iew.exec_refs                    50553896                       # number of memory reference insts executed
-system.cpu1.iew.exec_branches                 7398817                       # Number of branches executed
-system.cpu1.iew.exec_stores                   7291878                       # Number of stores executed
-system.cpu1.iew.exec_rate                    0.210990                       # Inst execution rate
-system.cpu1.iew.wb_sent                      86399299                       # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count                     54376914                       # cumulative count of insts written-back
-system.cpu1.iew.wb_producers                 30829889                       # num instructions producing a value
-system.cpu1.iew.wb_consumers                 55266228                       # num instructions consuming a value
+system.cpu1.iew.exec_nop                        82227                       # number of nop insts executed
+system.cpu1.iew.exec_refs                    25682989                       # number of memory reference insts executed
+system.cpu1.iew.exec_branches                 3899404                       # Number of branches executed
+system.cpu1.iew.exec_stores                   4241599                       # Number of stores executed
+system.cpu1.iew.exec_rate                    0.103764                       # Inst execution rate
+system.cpu1.iew.wb_sent                      41086324                       # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count                     25025175                       # cumulative count of insts written-back
+system.cpu1.iew.wb_producers                 11348419                       # num instructions producing a value
+system.cpu1.iew.wb_consumers                 16538487                       # num instructions consuming a value
 system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu1.iew.wb_rate                      0.131621                       # insts written-back per cycle
-system.cpu1.iew.wb_fanout                    0.557843                       # average fanout of values written-back
+system.cpu1.iew.wb_rate                      0.063060                       # insts written-back per cycle
+system.cpu1.iew.wb_fanout                    0.686182                       # average fanout of values written-back
 system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.commit.commitSquashedInsts       13879712                       # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls         899341                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts           318567                       # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples    111667919                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean     0.440684                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev     1.404622                       # Number of insts commited each cycle
+system.cpu1.commit.commitSquashedInsts        1702265                       # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls         769163                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts           191007                       # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples    394940200                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean     0.061056                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev     0.422241                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0     93786179     83.99%     83.99% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1      9487781      8.50%     92.48% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2      2098555      1.88%     94.36% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3      1338170      1.20%     95.56% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4       960614      0.86%     96.42% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5       571645      0.51%     96.93% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6      1030883      0.92%     97.86% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7       527820      0.47%     98.33% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8      1866272      1.67%    100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0    381244473     96.53%     96.53% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1      9114140      2.31%     98.84% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2      2236589      0.57%     99.41% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3       955406      0.24%     99.65% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4       446570      0.11%     99.76% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5       403381      0.10%     99.86% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6       181575      0.05%     99.91% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7        97100      0.02%     99.93% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8       260966      0.07%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total    111667919                       # Number of insts commited each cycle
-system.cpu1.commit.committedInsts            38872746                       # Number of instructions committed
-system.cpu1.commit.committedOps              49210296                       # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total    394940200                       # Number of insts commited each cycle
+system.cpu1.commit.committedInsts            19609371                       # Number of instructions committed
+system.cpu1.commit.committedOps              24113599                       # Number of ops (including micro ops) committed
 system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu1.commit.refs                      16982765                       # Number of memory references committed
-system.cpu1.commit.loads                      9979998                       # Number of loads committed
-system.cpu1.commit.membars                     195533                       # Number of memory barriers committed
-system.cpu1.commit.branches                   6424967                       # Number of branches committed
-system.cpu1.commit.fp_insts                      6822                       # Number of committed floating point instructions.
-system.cpu1.commit.int_insts                 43922606                       # Number of committed integer instructions.
-system.cpu1.commit.function_calls              553368                       # Number of function calls committed.
+system.cpu1.commit.refs                       9369646                       # Number of memory references committed
+system.cpu1.commit.loads                      5202699                       # Number of loads committed
+system.cpu1.commit.membars                     162322                       # Number of memory barriers committed
+system.cpu1.commit.branches                   3698878                       # Number of branches committed
+system.cpu1.commit.fp_insts                      6758                       # Number of committed floating point instructions.
+system.cpu1.commit.int_insts                 21204966                       # Number of committed integer instructions.
+system.cpu1.commit.function_calls              385194                       # Number of function calls committed.
 system.cpu1.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntAlu        32167564     65.37%     65.37% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntMult          58261      0.12%     65.49% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntDiv               0      0.00%     65.49% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     65.49% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     65.49% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     65.49% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatMult            0      0.00%     65.49% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     65.49% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     65.49% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     65.49% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     65.49% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     65.49% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     65.49% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     65.49% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     65.49% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMult             0      0.00%     65.49% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     65.49% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShift            0      0.00%     65.49% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     65.49% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     65.49% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     65.49% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     65.49% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     65.49% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     65.49% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     65.49% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMisc         1706      0.00%     65.49% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     65.49% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     65.49% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     65.49% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemRead        9979998     20.28%     85.77% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemWrite       7002767     14.23%    100.00% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntAlu        14709151     61.00%     61.00% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntMult          33154      0.14%     61.14% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntDiv               0      0.00%     61.14% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     61.14% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     61.14% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     61.14% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatMult            0      0.00%     61.14% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     61.14% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     61.14% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     61.14% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     61.14% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     61.14% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     61.14% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     61.14% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     61.14% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMult             0      0.00%     61.14% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     61.14% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShift            0      0.00%     61.14% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     61.14% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     61.14% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     61.14% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     61.14% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     61.14% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     61.14% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     61.14% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMisc         1648      0.01%     61.14% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     61.14% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     61.14% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     61.14% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemRead        5202699     21.58%     82.72% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemWrite       4166947     17.28%    100.00% # Class of committed instruction
 system.cpu1.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::total         49210296                       # Class of committed instruction
-system.cpu1.commit.bw_lim_events              1866272                       # number cycles where commit BW limit reached
+system.cpu1.commit.op_class_0::total         24113599                       # Class of committed instruction
+system.cpu1.commit.bw_lim_events               260966                       # number cycles where commit BW limit reached
 system.cpu1.commit.bw_limited                       0                       # number of insts not committed due to BW limits
-system.cpu1.rob.rob_reads                   171825162                       # The number of ROB reads
-system.cpu1.rob.rob_writes                  128514038                       # The number of ROB writes
-system.cpu1.timesIdled                        1427088                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles                      299213387                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles                  4796716848                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts                   38803107                       # Number of Instructions Simulated
-system.cpu1.committedOps                     49140657                       # Number of Ops (including micro ops) Simulated
-system.cpu1.cpi                             10.646885                       # CPI: Cycles Per Instruction
-system.cpu1.cpi_total                       10.646885                       # CPI: Total CPI of All Threads
-system.cpu1.ipc                              0.093924                       # IPC: Instructions Per Cycle
-system.cpu1.ipc_total                        0.093924                       # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads               391718305                       # number of integer regfile reads
-system.cpu1.int_regfile_writes               56505033                       # number of integer regfile writes
-system.cpu1.fp_regfile_reads                     5108                       # number of floating regfile reads
-system.cpu1.fp_regfile_writes                    2336                       # number of floating regfile writes
-system.cpu1.misc_regfile_reads              199117817                       # number of misc regfile reads
-system.cpu1.misc_regfile_writes                722972                       # number of misc regfile writes
-system.cpu1.icache.tags.replacements           616464                       # number of replacements
-system.cpu1.icache.tags.tagsinuse          498.721065                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs            7090163                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs           616976                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs            11.491797                       # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle      74744507500                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst   498.721065                       # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst     0.974065                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total     0.974065                       # Average percentage of cache occupancy
+system.cpu1.rob.rob_reads                   419589246                       # The number of ROB reads
+system.cpu1.rob.rob_writes                   52032512                       # The number of ROB writes
+system.cpu1.timesIdled                         248745                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles                        1507220                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles                  4845699469                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.committedInsts                   19539732                       # Number of Instructions Simulated
+system.cpu1.committedOps                     24043960                       # Number of Ops (including micro ops) Simulated
+system.cpu1.cpi                             20.309853                       # CPI: Cycles Per Instruction
+system.cpu1.cpi_total                       20.309853                       # CPI: Total CPI of All Threads
+system.cpu1.ipc                              0.049237                       # IPC: Instructions Per Cycle
+system.cpu1.ipc_total                        0.049237                       # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads                45343306                       # number of integer regfile reads
+system.cpu1.int_regfile_writes               15599183                       # number of integer regfile writes
+system.cpu1.fp_regfile_reads                     5046                       # number of floating regfile reads
+system.cpu1.fp_regfile_writes                    2260                       # number of floating regfile writes
+system.cpu1.cc_regfile_reads                139131439                       # number of cc regfile reads
+system.cpu1.cc_regfile_writes                 9348976                       # number of cc regfile writes
+system.cpu1.misc_regfile_reads              454367618                       # number of misc regfile reads
+system.cpu1.misc_regfile_writes                623445                       # number of misc regfile writes
+system.cpu1.icache.tags.replacements           439266                       # number of replacements
+system.cpu1.icache.tags.tagsinuse          497.815366                       # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs            8166304                       # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs           439778                       # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs            18.569151                       # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle     119618152250                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tags.occ_blocks::cpu1.inst   497.815366                       # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst     0.972296                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total     0.972296                       # Average percentage of cache occupancy
 system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::2          512                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::2          509                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::3            3                       # Occupied blocks per task id
 system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses          8371129                       # Number of tag accesses
-system.cpu1.icache.tags.data_accesses         8371129                       # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst      7090163                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total        7090163                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst      7090163                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total         7090163                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst      7090163                       # number of overall hits
-system.cpu1.icache.overall_hits::total        7090163                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst       663949                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total       663949                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst       663949                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total        663949                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst       663949                       # number of overall misses
-system.cpu1.icache.overall_misses::total       663949                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   9003300184                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total   9003300184                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst   9003300184                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total   9003300184                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst   9003300184                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total   9003300184                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst      7754112                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total      7754112                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst      7754112                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total      7754112                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst      7754112                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total      7754112                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.085625                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.085625                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.085625                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.085625                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.085625                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.085625                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13560.228548                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 13560.228548                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13560.228548                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 13560.228548                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13560.228548                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 13560.228548                       # average overall miss latency
-system.cpu1.icache.blocked_cycles::no_mshrs         3101                       # number of cycles access was blocked
-system.cpu1.icache.blocked_cycles::no_targets          648                       # number of cycles access was blocked
-system.cpu1.icache.blocked::no_mshrs              217                       # number of cycles access was blocked
-system.cpu1.icache.blocked::no_targets              1                       # number of cycles access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_mshrs    14.290323                       # average number of cycles each access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_targets          648                       # average number of cycles each access was blocked
+system.cpu1.icache.tags.tag_accesses          9063984                       # Number of tag accesses
+system.cpu1.icache.tags.data_accesses         9063984                       # Number of data accesses
+system.cpu1.icache.ReadReq_hits::cpu1.inst      8166304                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total        8166304                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst      8166304                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total         8166304                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst      8166304                       # number of overall hits
+system.cpu1.icache.overall_hits::total        8166304                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst       457900                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total       457900                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst       457900                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total        457900                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst       457900                       # number of overall misses
+system.cpu1.icache.overall_misses::total       457900                       # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   6264180115                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total   6264180115                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst   6264180115                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total   6264180115                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst   6264180115                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total   6264180115                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst      8624204                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total      8624204                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst      8624204                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total      8624204                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst      8624204                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total      8624204                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.053095                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.053095                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.053095                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.053095                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.053095                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.053095                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13680.236111                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 13680.236111                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13680.236111                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 13680.236111                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13680.236111                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 13680.236111                       # average overall miss latency
+system.cpu1.icache.blocked_cycles::no_mshrs          882                       # number of cycles access was blocked
+system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu1.icache.blocked::no_mshrs               53                       # number of cycles access was blocked
+system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_mshrs    16.641509                       # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst        46932                       # number of ReadReq MSHR hits
-system.cpu1.icache.ReadReq_mshr_hits::total        46932                       # number of ReadReq MSHR hits
-system.cpu1.icache.demand_mshr_hits::cpu1.inst        46932                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.demand_mshr_hits::total        46932                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.overall_mshr_hits::cpu1.inst        46932                       # number of overall MSHR hits
-system.cpu1.icache.overall_mshr_hits::total        46932                       # number of overall MSHR hits
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       617017                       # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total       617017                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst       617017                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total       617017                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst       617017                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total       617017                       # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   7343865656                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total   7343865656                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   7343865656                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total   7343865656                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   7343865656                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total   7343865656                       # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      4135000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      4135000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      4135000                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::total      4135000                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.079573                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.079573                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.079573                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.079573                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.079573                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.079573                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11902.209592                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11902.209592                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11902.209592                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 11902.209592                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11902.209592                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 11902.209592                       # average overall mshr miss latency
+system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst        18120                       # number of ReadReq MSHR hits
+system.cpu1.icache.ReadReq_mshr_hits::total        18120                       # number of ReadReq MSHR hits
+system.cpu1.icache.demand_mshr_hits::cpu1.inst        18120                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.demand_mshr_hits::total        18120                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.overall_mshr_hits::cpu1.inst        18120                       # number of overall MSHR hits
+system.cpu1.icache.overall_mshr_hits::total        18120                       # number of overall MSHR hits
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       439780                       # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total       439780                       # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst       439780                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total       439780                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst       439780                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total       439780                       # number of overall MSHR misses
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   5188034078                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total   5188034078                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   5188034078                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total   5188034078                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   5188034078                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total   5188034078                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      4304000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      4304000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      4304000                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::total      4304000                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.050994                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.050994                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.050994                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total     0.050994                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.050994                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total     0.050994                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11796.884983                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11796.884983                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11796.884983                       # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total 11796.884983                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11796.884983                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total 11796.884983                       # average overall mshr miss latency
 system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
 system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.dcache.tags.replacements           363234                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse          485.053035                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs           13011922                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs           363603                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs            35.786069                       # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle      70837218250                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data   485.053035                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data     0.947369                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total     0.947369                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024          369                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2          369                       # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024     0.720703                       # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses         60324528                       # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses        60324528                       # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data      8516413                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total        8516413                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data      4259216                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total       4259216                       # number of WriteReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        99616                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total        99616                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data        97058                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total        97058                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data     12775629                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total        12775629                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data     12775629                       # number of overall hits
-system.cpu1.dcache.overall_hits::total       12775629                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data       409488                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total       409488                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data      1576995                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total      1576995                       # number of WriteReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        14210                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total        14210                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data        10944                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total        10944                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data      1986483                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total       1986483                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data      1986483                       # number of overall misses
-system.cpu1.dcache.overall_misses::total      1986483                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   6227092173                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total   6227092173                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  74233295889                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total  74233295889                       # number of WriteReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    131030244                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total    131030244                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data     58441088                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total     58441088                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data  80460388062                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total  80460388062                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data  80460388062                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total  80460388062                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data      8925901                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total      8925901                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data      5836211                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total      5836211                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data       113826                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total       113826                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data       108002                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total       108002                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data     14762112                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total     14762112                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data     14762112                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total     14762112                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.045876                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.045876                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.270209                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.270209                       # miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.124840                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.124840                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.101331                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total     0.101331                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.134566                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.134566                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.134566                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.134566                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15207.019920                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 15207.019920                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 47072.626032                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 47072.626032                       # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data  9220.988318                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total  9220.988318                       # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data  5340.011696                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total  5340.011696                       # average StoreCondReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 40503.939909                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 40503.939909                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 40503.939909                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 40503.939909                       # average overall miss latency
-system.cpu1.dcache.blocked_cycles::no_mshrs        30714                       # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_targets        17665                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_mshrs             3287                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_targets            190                       # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs     9.344083                       # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets    92.973684                       # average number of cycles each access was blocked
+system.cpu1.dcache.tags.replacements           227040                       # number of replacements
+system.cpu1.dcache.tags.tagsinuse          492.830733                       # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs            7082160                       # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs           227406                       # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs            31.143242                       # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle      99092137500                       # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.occ_blocks::cpu1.data   492.830733                       # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data     0.962560                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total     0.962560                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_task_id_blocks::1024          366                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2          366                       # Occupied blocks per task id
+system.cpu1.dcache.tags.occ_task_id_percent::1024     0.714844                       # Percentage of cache occupancy per task id
+system.cpu1.dcache.tags.tag_accesses         32684037                       # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses        32684037                       # Number of data accesses
+system.cpu1.dcache.ReadReq_hits::cpu1.data      3792757                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total        3792757                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data      3094601                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total       3094601                       # number of WriteReq hits
+system.cpu1.dcache.SoftPFReq_hits::cpu1.data        14161                       # number of SoftPFReq hits
+system.cpu1.dcache.SoftPFReq_hits::total        14161                       # number of SoftPFReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        75622                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total        75622                       # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data        75613                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total        75613                       # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data      6887358                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total         6887358                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data      6901519                       # number of overall hits
+system.cpu1.dcache.overall_hits::total        6901519                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data       187422                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total       187422                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data       806941                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total       806941                       # number of WriteReq misses
+system.cpu1.dcache.SoftPFReq_misses::cpu1.data        41483                       # number of SoftPFReq misses
+system.cpu1.dcache.SoftPFReq_misses::total        41483                       # number of SoftPFReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        10414                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total        10414                       # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data         9617                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total         9617                       # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data       994363                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total        994363                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data      1035846                       # number of overall misses
+system.cpu1.dcache.overall_misses::total      1035846                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   2444126213                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total   2444126213                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  27779707617                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total  27779707617                       # number of WriteReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data     86490246                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total     86490246                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data     53209125                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total     53209125                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data        14000                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::total        14000                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data  30223833830                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total  30223833830                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data  30223833830                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total  30223833830                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data      3980179                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total      3980179                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data      3901542                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total      3901542                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::cpu1.data        55644                       # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::total        55644                       # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        86036                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total        86036                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        85230                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total        85230                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data      7881721                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total      7881721                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data      7937365                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total      7937365                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.047089                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.047089                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.206826                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.206826                       # miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.745507                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::total     0.745507                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.121042                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.121042                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.112836                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total     0.112836                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.126161                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.126161                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.130503                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.130503                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13040.764761                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 13040.764761                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 34425.946404                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 34425.946404                       # average WriteReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data  8305.189745                       # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total  8305.189745                       # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data  5532.819486                       # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total  5532.819486                       # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
+system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 30395.171411                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 30395.171411                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 29177.922037                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 29177.922037                       # average overall miss latency
+system.cpu1.dcache.blocked_cycles::no_mshrs         4476                       # number of cycles access was blocked
+system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_mshrs              723                       # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_mshrs     6.190871                       # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks       327552                       # number of writebacks
-system.cpu1.dcache.writebacks::total           327552                       # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data       178171                       # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total       178171                       # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data      1413840                       # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total      1413840                       # number of WriteReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data         1455                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::total         1455                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data      1592011                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total      1592011                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data      1592011                       # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total      1592011                       # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       231317                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total       231317                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data       163155                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total       163155                       # number of WriteReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data        12755                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total        12755                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        10944                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total        10944                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data       394472                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total       394472                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data       394472                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total       394472                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   2894401946                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total   2894401946                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   6921941032                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total   6921941032                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     89586755                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     89586755                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data     36550912                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total     36550912                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data         1000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total         1000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   9816342978                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total   9816342978                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   9816342978                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total   9816342978                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 169231628259                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 169231628259                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data  25874415734                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total  25874415734                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 195106043993                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total 195106043993                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.025915                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.025915                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.027956                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.027956                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.112057                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.112057                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.101331                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.101331                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.026722                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.026722                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.026722                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.026722                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12512.707436                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12512.707436                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 42425.552585                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 42425.552585                       # average WriteReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data  7023.657781                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total  7023.657781                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data  3339.812865                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total  3339.812865                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.writebacks::writebacks       207281                       # number of writebacks
+system.cpu1.dcache.writebacks::total           207281                       # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data        70540                       # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total        70540                       # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data       693700                       # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total       693700                       # number of WriteReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data          500                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::total          500                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data       764240                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total       764240                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data       764240                       # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total       764240                       # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       116882                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total       116882                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data       113241                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total       113241                       # number of WriteReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data        23891                       # number of SoftPFReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::total        23891                       # number of SoftPFReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         9914                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total         9914                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data         9617                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total         9617                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data       230123                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total       230123                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data       254014                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total       254014                       # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   1203808322                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1203808322                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   3988299754                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total   3988299754                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    341716536                       # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total    341716536                       # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     60834504                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     60834504                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data     33974875                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total     33974875                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data        12000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total        12000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   5192108076                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total   5192108076                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   5533824612                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total   5533824612                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168973544758                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168973544758                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    522517625                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    522517625                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 169496062383                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total 169496062383                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.029366                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.029366                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.029025                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.029025                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.429354                       # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.429354                       # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.115231                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.115231                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.112836                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.112836                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.029197                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total     0.029197                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.032002                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total     0.032002                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10299.347393                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10299.347393                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35219.573776                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 35219.573776                       # average WriteReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 14303.149136                       # average SoftPFReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 14303.149136                       # average SoftPFReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data  6136.221908                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total  6136.221908                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data  3532.793491                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total  3532.793491                       # average StoreCondReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 24884.764896                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 24884.764896                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 24884.764896                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 24884.764896                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22562.317004                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22562.317004                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 21785.510295                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 21785.510295                       # average overall mshr miss latency
 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
@@ -2294,18 +2330,18 @@ system.iocache.avg_blocked_cycles::no_mshrs          nan                       #
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1734300149849                       # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1734300149849                       # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1734300149849                       # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1734300149849                       # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1736665659303                       # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1736665659303                       # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1736665659303                       # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1736665659303                       # number of overall MSHR uncacheable cycles
 system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average ReadReq mshr uncacheable latency
 system.iocache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average overall mshr uncacheable latency
 system.iocache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                   42635                       # number of quiesce instructions executed
+system.cpu0.kern.inst.quiesce                   52427                       # number of quiesce instructions executed
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                   50404                       # number of quiesce instructions executed
+system.cpu1.kern.inst.quiesce                   40685                       # number of quiesce instructions executed
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
index 8259c3ed2..e77a65365 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
@@ -1,137 +1,137 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.525889                       # Number of seconds simulated
-sim_ticks                                2525888859000                       # Number of ticks simulated
-final_tick                               2525888859000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.542203                       # Number of seconds simulated
+sim_ticks                                2542202956000                       # Number of ticks simulated
+final_tick                               2542202956000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  66506                       # Simulator instruction rate (inst/s)
-host_op_rate                                    85575                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2785423099                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 419792                       # Number of bytes of host memory used
-host_seconds                                   906.82                       # Real time elapsed on the host
-sim_insts                                    60309513                       # Number of instructions simulated
-sim_ops                                      77601128                       # Number of ops (including micro ops) simulated
+host_inst_rate                                  47189                       # Simulator instruction rate (inst/s)
+host_op_rate                                    56852                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1989066585                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 412724                       # Number of bytes of host memory used
+host_seconds                                  1278.09                       # Real time elapsed on the host
+sim_insts                                    60311945                       # Number of instructions simulated
+sim_ops                                      72661478                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::realview.clcd    119537664                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.dtb.walker         3072                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker           64                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst            797248                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           9094168                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            129432216                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       797248                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          797248                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      3785024                       # Number of bytes written to this memory
+system.physmem.bytes_read::realview.clcd    121110528                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker          640                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker          192                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst            798576                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           9072728                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            130982664                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       798576                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          798576                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      3743232                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu.data        3016072                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           6801096                       # Number of bytes written to this memory
-system.physmem.num_reads::realview.clcd      14942208                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.dtb.walker           48                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker            1                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst              12457                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             142132                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total              15096846                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           59141                       # Number of write requests responded to by this memory
+system.physmem.bytes_written::total           6759304                       # Number of bytes written to this memory
+system.physmem.num_reads::realview.clcd      15138816                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.dtb.walker           10                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker            3                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst              14991                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             141787                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total              15295607                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           58488                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu.data            754018                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               813159                       # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd        47324990                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.dtb.walker           1216                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker             25                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               315631                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              3600383                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                51242245                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          315631                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             315631                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1498492                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data             1194064                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2692556                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1498492                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd       47324990                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker          1216                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker            25                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              315631                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             4794447                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               53934801                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                      15096846                       # Number of read requests accepted
-system.physmem.writeReqs                       813159                       # Number of write requests accepted
-system.physmem.readBursts                    15096846                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     813159                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                961407104                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                   4791040                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   6818432                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                 129432216                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                6801096                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                    74860                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                  706594                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs           4696                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0              943526                       # Per bank write bursts
-system.physmem.perBankRdBursts::1              937990                       # Per bank write bursts
-system.physmem.perBankRdBursts::2              937469                       # Per bank write bursts
-system.physmem.perBankRdBursts::3              937431                       # Per bank write bursts
-system.physmem.perBankRdBursts::4              943079                       # Per bank write bursts
-system.physmem.perBankRdBursts::5              938170                       # Per bank write bursts
-system.physmem.perBankRdBursts::6              937203                       # Per bank write bursts
-system.physmem.perBankRdBursts::7              936910                       # Per bank write bursts
-system.physmem.perBankRdBursts::8              943866                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              938107                       # Per bank write bursts
-system.physmem.perBankRdBursts::10             936563                       # Per bank write bursts
-system.physmem.perBankRdBursts::11             936045                       # Per bank write bursts
-system.physmem.perBankRdBursts::12             943886                       # Per bank write bursts
-system.physmem.perBankRdBursts::13             937531                       # Per bank write bursts
-system.physmem.perBankRdBursts::14             937186                       # Per bank write bursts
-system.physmem.perBankRdBursts::15             937024                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                6617                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                6376                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                6529                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                6558                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                6459                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                6705                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                6711                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                6649                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                7036                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                6794                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               6454                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               6111                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               7073                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               6679                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               6963                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               6824                       # Per bank write bursts
+system.physmem.num_writes::total               812506                       # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd        47639992                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.dtb.walker            252                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker             76                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               314128                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              3568845                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                51523292                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          314128                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             314128                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1472436                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data             1186401                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                2658837                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1472436                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd       47639992                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker           252                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker            76                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              314128                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             4755246                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               54182129                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                      15295607                       # Number of read requests accepted
+system.physmem.writeReqs                       812506                       # Number of write requests accepted
+system.physmem.readBursts                    15295607                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     812506                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                976934144                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                   1984704                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   6778304                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                 130982664                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                6759304                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                    31011                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                  706576                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs           4612                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0              955786                       # Per bank write bursts
+system.physmem.perBankRdBursts::1              955478                       # Per bank write bursts
+system.physmem.perBankRdBursts::2              953003                       # Per bank write bursts
+system.physmem.perBankRdBursts::3              951059                       # Per bank write bursts
+system.physmem.perBankRdBursts::4              958601                       # Per bank write bursts
+system.physmem.perBankRdBursts::5              955602                       # Per bank write bursts
+system.physmem.perBankRdBursts::6              952653                       # Per bank write bursts
+system.physmem.perBankRdBursts::7              950407                       # Per bank write bursts
+system.physmem.perBankRdBursts::8              956154                       # Per bank write bursts
+system.physmem.perBankRdBursts::9              955874                       # Per bank write bursts
+system.physmem.perBankRdBursts::10             952889                       # Per bank write bursts
+system.physmem.perBankRdBursts::11             950148                       # Per bank write bursts
+system.physmem.perBankRdBursts::12             956166                       # Per bank write bursts
+system.physmem.perBankRdBursts::13             955918                       # Per bank write bursts
+system.physmem.perBankRdBursts::14             953918                       # Per bank write bursts
+system.physmem.perBankRdBursts::15             950940                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                6546                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                6352                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                6488                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                6518                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                6421                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                6701                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                6665                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                6611                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                6966                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                6759                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               6421                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               6055                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               7037                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               6645                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               6920                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               6806                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    2525887732500                       # Total gap between requests
+system.physmem.totGap                    2542201638000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::2                      38                       # Read request sizes (log2)
-system.physmem.readPktSize::3                14942208                       # Read request sizes (log2)
-system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
+system.physmem.readPktSize::2                      18                       # Read request sizes (log2)
+system.physmem.readPktSize::3                15138826                       # Read request sizes (log2)
+system.physmem.readPktSize::4                    3351                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  154600                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  153412                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                 754018                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                  59141                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                   1057329                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    995712                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                    953847                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                   1057444                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                    956989                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                   1015779                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                   2635918                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                   2545995                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                   3318157                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                    125455                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                   108163                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                    99319                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                    95398                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                    19431                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                    18601                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                    18316                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                      110                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                       12                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                        6                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                        5                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                  58488                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                   1110293                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    964892                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                    965548                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                   1076032                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                    973735                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                   1036027                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                   2680967                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                   2587988                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                   3368391                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                    128855                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                   111642                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                   103064                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                    98734                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                    20085                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                    19255                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                    18985                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                       85                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                       10                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                        5                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                        3                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
@@ -159,28 +159,28 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     2592                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     2806                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     4314                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     6296                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     6465                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     6394                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     6388                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     6736                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     6476                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     6428                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     6463                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     6391                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     6379                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     6746                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     6351                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     6353                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     6486                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     6262                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      124                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                       66                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                       31                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                        3                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     2635                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     2946                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     5311                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     6283                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     6365                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     6331                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     6319                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     6592                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     6454                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     6382                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     6354                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     6272                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     6263                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     6280                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     6248                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     6241                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     6236                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     6213                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                       87                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                       62                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                       37                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                        4                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
@@ -208,125 +208,125 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       995372                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      972.727318                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     907.205467                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     202.336600                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          22984      2.31%      2.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        19752      1.98%      4.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         8337      0.84%      5.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         2265      0.23%      5.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2301      0.23%      5.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1840      0.18%      5.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         8587      0.86%      6.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          978      0.10%      6.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151       928328     93.26%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         995372                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          6241                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean      2406.981894                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev    114987.414706                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-524287         6237     99.94%     99.94% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::524288-1.04858e+06            2      0.03%     99.97% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2.09715e+06-2.62144e+06            1      0.02%     99.98% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples      1010606                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      973.388688                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     909.020446                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     200.819397                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          22711      2.25%      2.25% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        19828      1.96%      4.21% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         8563      0.85%      5.06% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         2249      0.22%      5.28% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2594      0.26%      5.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1688      0.17%      5.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         8931      0.88%      6.59% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          959      0.09%      6.68% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151       943083     93.32%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total        1010606                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          6196                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean      2463.620239                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev    113702.310017                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-524287         6191     99.92%     99.92% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::524288-1.04858e+06            2      0.03%     99.95% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1.04858e+06-1.57286e+06            2      0.03%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::8.38861e+06-8.9129e+06            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            6241                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          6241                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        17.070662                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       17.017388                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        1.386394                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16               3585     57.44%     57.44% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17                 32      0.51%     57.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18               1616     25.89%     83.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19                845     13.54%     97.39% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                 54      0.87%     98.25% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21                 36      0.58%     98.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22                 33      0.53%     99.36% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23                 31      0.50%     99.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24                  9      0.14%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            6241                       # Writes before turning the bus around for reads
-system.physmem.totQLat                   389024977250                       # Total ticks spent queuing
-system.physmem.totMemAccLat              670687214750                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                  75109930000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       25897.04                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            6196                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          6196                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.093447                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       17.042337                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        1.354685                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               3441     55.54%     55.54% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17                 45      0.73%     56.26% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18               1714     27.66%     83.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19                868     14.01%     97.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                 47      0.76%     98.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                 22      0.36%     99.05% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22                 27      0.44%     99.48% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23                 21      0.34%     99.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24                 10      0.16%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::27                  1      0.02%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            6196                       # Writes before turning the bus around for reads
+system.physmem.totQLat                   395449280750                       # Total ticks spent queuing
+system.physmem.totMemAccLat              681660455750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                  76322980000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       25906.31                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  44647.04                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         380.62                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           2.70                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       51.24                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        2.69                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  44656.31                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         384.29                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           2.67                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       51.52                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        2.66                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           2.99                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       2.97                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                           3.02                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       3.00                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         6.85                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        24.12                       # Average write queue length when enqueuing
-system.physmem.readRowHits                   14042089                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     91063                       # Number of row buffer hits during writes
+system.physmem.avgRdQLen                         6.20                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        23.61                       # Average write queue length when enqueuing
+system.physmem.readRowHits                   14269193                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     90708                       # Number of row buffer hits during writes
 system.physmem.readRowHitRate                   93.48                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  85.45                       # Row buffer hit rate for writes
-system.physmem.avgGap                       158760.96                       # Average gap between requests
+system.physmem.writeRowHitRate                  85.63                       # Row buffer hit rate for writes
+system.physmem.avgGap                       157821.19                       # Average gap between requests
 system.physmem.pageHitRate                      93.42                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE     2186215098000                       # Time in different power states
-system.physmem.memoryStateTime::REF       84344780000                       # Time in different power states
+system.physmem.memoryStateTime::IDLE     2194513894000                       # Time in different power states
+system.physmem.memoryStateTime::REF       84889480000                       # Time in different power states
 system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT      255323240750                       # Time in different power states
+system.physmem.memoryStateTime::ACT      262799464750                       # Time in different power states
 system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.realview.nvmem.bytes_read::cpu.inst           64                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total            64                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu.inst           64                       # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total           64                       # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu.inst            1                       # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total              1                       # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu.inst            25                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total               25                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu.inst           25                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total           25                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu.inst           25                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total              25                       # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput                     54884184                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq            16149487                       # Transaction distribution
-system.membus.trans_dist::ReadResp           16149487                       # Transaction distribution
-system.membus.trans_dist::WriteReq             763349                       # Transaction distribution
-system.membus.trans_dist::WriteResp            763349                       # Transaction distribution
-system.membus.trans_dist::Writeback             59141                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             4693                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq              3                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp            4696                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            131431                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           131431                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave      2383042                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port            2                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         3760                       # Packet count per connected master and slave (bytes)
+system.realview.nvmem.bytes_read::cpu.inst           48                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total            48                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu.inst           48                       # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total           48                       # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu.inst            3                       # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total              3                       # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu.inst            19                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total               19                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu.inst           19                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total           19                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu.inst           19                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total              19                       # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput                     55125441                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq            16348039                       # Transaction distribution
+system.membus.trans_dist::ReadResp           16348039                       # Transaction distribution
+system.membus.trans_dist::WriteReq             763357                       # Transaction distribution
+system.membus.trans_dist::WriteResp            763357                       # Transaction distribution
+system.membus.trans_dist::Writeback             58488                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq             4612                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp            4612                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            131651                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           131651                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave      2383056                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port            6                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         3780                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio            2                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1885845                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total      4272651                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port     29884416                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total     29884416                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total               34157067                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave      2390450                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port           64                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio         7520                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1889330                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total      4276174                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port     30277632                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total     30277632                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total               34553806                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave      2390478                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port           48                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio         7560                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio            4                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     16695648                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total     19093686                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port    119537664                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::total    119537664                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total           138631350                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus              138631350                       # Total data (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     16631440                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total     19029530                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port    121110528                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.iocache.mem_side::total    121110528                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total           140140058                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus              140140058                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy          1486861000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy          1558440500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.1                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy                1000                       # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy                3500                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             3602500                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             3512000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer4.occupancy                1500                       # Layer occupancy (ticks)
+system.membus.reqLayer4.occupancy                1000                       # Layer occupancy (ticks)
 system.membus.reqLayer4.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer6.occupancy         17311099000                       # Layer occupancy (ticks)
+system.membus.reqLayer6.occupancy         17513415500                       # Layer occupancy (ticks)
 system.membus.reqLayer6.utilization               0.7                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         4710414902                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         4726913870                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
-system.membus.respLayer2.occupancy        36916757411                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy        37423565460                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              1.5                       # Layer utilization (%)
 system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
 system.cf0.dma_read_bytes                           0                       # Number of bytes transfered via DMA reads (not PRD).
@@ -334,15 +334,15 @@ system.cf0.dma_read_txs                             0                       # Nu
 system.cf0.dma_write_full_pages                     0                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                          0                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
-system.iobus.throughput                      48271369                       # Throughput (bytes/s)
-system.iobus.trans_dist::ReadReq             16125555                       # Transaction distribution
-system.iobus.trans_dist::ReadResp            16125555                       # Transaction distribution
-system.iobus.trans_dist::WriteReq                8174                       # Transaction distribution
-system.iobus.trans_dist::WriteResp               8174                       # Transaction distribution
+system.iobus.throughput                      48580309                       # Throughput (bytes/s)
+system.iobus.trans_dist::ReadReq             16322168                       # Transaction distribution
+system.iobus.trans_dist::ReadResp            16322168                       # Transaction distribution
+system.iobus.trans_dist::WriteReq                8176                       # Transaction distribution
+system.iobus.trans_dist::WriteResp               8176                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        30038                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio         7934                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio          516                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio         1024                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio         7940                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio          520                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio         1028                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio           36                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          746                       # Packet count per connected master and slave (bytes)
@@ -362,14 +362,14 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total      2383042                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side     29884416                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.clcd.dma::total     29884416                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                32267458                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total      2383056                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side     30277632                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.clcd.dma::total     30277632                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                32660688                       # Packet count per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio        39333                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio        15868                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio         1032                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio         2048                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio        15880                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio         1040                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio         2056                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio           72                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio          397                       # Cumulative packet size per connected master and slave (bytes)
@@ -389,18 +389,18 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::total      2390450                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side    119537664                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.realview.clcd.dma::total    119537664                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::total            121928114                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.data_through_bus               121928114                       # Total data (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::total      2390478                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side    121110528                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.realview.clcd.dma::total    121110528                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::total            123501006                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.data_through_bus               123501006                       # Total data (bytes)
 system.iobus.reqLayer0.occupancy             21111000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy              3972000                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy              3975000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy               516000                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy               520000                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy               518000                       # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy               520000                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer4.occupancy                27000                       # Layer occupancy (ticks)
 system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
@@ -440,22 +440,22 @@ system.iobus.reqLayer22.occupancy                8000                       # La
 system.iobus.reqLayer22.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer23.occupancy                8000                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy         14942208000                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy         15138816000                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.6                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy          2374868000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy          2374880000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.1                       # Layer utilization (%)
-system.iobus.respLayer1.occupancy         37649719589                       # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy         38173420540                       # Layer occupancy (ticks)
 system.iobus.respLayer1.utilization               1.5                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.branchPred.lookups                14910337                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          11976867                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            705848                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups              9580478                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                 7742107                       # Number of BTB hits
+system.cpu.branchPred.lookups                13201290                       # Number of BP lookups
+system.cpu.branchPred.condPredicted           9675974                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            704139                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups              8377301                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                 6024680                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             80.811281                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 1408303                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect              72648                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             71.916719                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 1435837                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect              30801                       # Number of incorrect RAS predictions.
 system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -479,25 +479,25 @@ system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DT
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.read_hits                     51097792                       # DTB read hits
-system.cpu.dtb.read_misses                      64987                       # DTB read misses
-system.cpu.dtb.write_hits                    11709971                       # DTB write hits
-system.cpu.dtb.write_misses                     15921                       # DTB write misses
+system.cpu.dtb.read_hits                     31642294                       # DTB read hits
+system.cpu.dtb.read_misses                      39524                       # DTB read misses
+system.cpu.dtb.write_hits                    11381361                       # DTB write hits
+system.cpu.dtb.write_misses                     10135                       # DTB write misses
 system.cpu.dtb.flush_tlb                            2                       # Number of times complete TLB was flushed
 system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
 system.cpu.dtb.flush_tlb_mva_asid                1439                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.dtb.flush_tlb_asid                      63                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries                     3472                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults                      2569                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults                    428                       # Number of TLB faults due to prefetch
+system.cpu.dtb.flush_entries                     3437                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                       348                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                    314                       # Number of TLB faults due to prefetch
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults                      1363                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses                 51162779                       # DTB read accesses
-system.cpu.dtb.write_accesses                11725892                       # DTB write accesses
+system.cpu.dtb.perms_faults                      1342                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                 31681818                       # DTB read accesses
+system.cpu.dtb.write_accesses                11391496                       # DTB write accesses
 system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.hits                          62807763                       # DTB hits
-system.cpu.dtb.misses                           80908                       # DTB misses
-system.cpu.dtb.accesses                      62888671                       # DTB accesses
+system.cpu.dtb.hits                          43023655                       # DTB hits
+system.cpu.dtb.misses                           49659                       # DTB misses
+system.cpu.dtb.accesses                      43073314                       # DTB accesses
 system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -519,8 +519,8 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.inst_hits                     11575507                       # ITB inst hits
-system.cpu.itb.inst_misses                      11335                       # ITB inst misses
+system.cpu.itb.inst_hits                     24159481                       # ITB inst hits
+system.cpu.itb.inst_misses                      10516                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.write_hits                           0                       # DTB write hits
@@ -529,607 +529,598 @@ system.cpu.itb.flush_tlb                            2                       # Nu
 system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
 system.cpu.itb.flush_tlb_mva_asid                1439                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.itb.flush_tlb_asid                      63                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries                     2514                       # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_entries                     2464                       # Number of entries that have been flushed from TLB
 system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
 system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults                      2954                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults                      4176                       # Number of TLB faults due to permissions restrictions
 system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.inst_accesses                 11586842                       # ITB inst accesses
-system.cpu.itb.hits                          11575507                       # DTB hits
-system.cpu.itb.misses                           11335                       # DTB misses
-system.cpu.itb.accesses                      11586842                       # DTB accesses
-system.cpu.numCycles                        476238509                       # number of cpu cycles simulated
+system.cpu.itb.inst_accesses                 24169997                       # ITB inst accesses
+system.cpu.itb.hits                          24159481                       # DTB hits
+system.cpu.itb.misses                           10516                       # DTB misses
+system.cpu.itb.accesses                      24169997                       # DTB accesses
+system.cpu.numCycles                        499350041                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           29789702                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                       91027179                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    14910337                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches            9150410                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      20302096                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 4754274                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles                     125108                       # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.BlockedCycles               93772455                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                 2699                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles         88682                       # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles      2727734                       # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles          553                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                  11572027                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                712397                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes                    5390                       # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples          150113292                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              0.756026                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.113644                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles           43030629                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                       74131140                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    13201290                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches            7460517                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     448266810                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 1858598                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles                     133224                       # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles                12550                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles        145871                       # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles      3032125                       # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles           42                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                  24158180                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                404816                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes                    4527                       # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples          495550550                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              0.179793                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             0.652924                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                129826802     86.49%     86.49% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  1312716      0.87%     87.36% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  1720953      1.15%     88.51% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  2304331      1.54%     90.04% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  2116294      1.41%     91.45% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  1112529      0.74%     92.19% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  2605432      1.74%     93.93% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                   752346      0.50%     94.43% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                  8361889      5.57%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                454644690     91.75%     91.75% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 13614673      2.75%     94.49% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  6391682      1.29%     95.78% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 20899505      4.22%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            150113292                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.031309                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.191138                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 31268958                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              96222513                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  18495001                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles                992442                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                3134378                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved              1970530                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                172531                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              108153308                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                572201                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                3134378                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 32906794                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                14229038                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles       56831984                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  17995352                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              25015746                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              103064055                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                  1610                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents               17097046                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents               19764397                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                2757051                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.FullRegisterEvents             1781                       # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands           107250734                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             477314257                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        435890251                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups             10500                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps              78727504                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 28523229                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts            1172187                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts        1078501                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  11007211                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             19896895                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            13369840                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           2003415                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          2457274                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                   95806828                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded             1986007                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 122955094                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            190842                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        19616274                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     49695395                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved         503680                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     150113292                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.819082                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.543742                       # Number of insts issued each cycle
+system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::total            495550550                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.026437                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.148455                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 35577628                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             424964763                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  30286365                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               4037656                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                 684138                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              1691487                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                250438                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts               80256354                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts               2078563                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                 684138                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 38799814                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles               217885603                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles       28702319                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  30653900                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles             178824776                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts               78213523                       # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts                597412                       # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents              61147213                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents               42400387                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents              160465829                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents               14695892                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands            82092463                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             364185184                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups         97017359                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups              9816                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps              75931181                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                  6161276                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts            1134052                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts         964724                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                   8995770                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             14558741                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            12101093                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads            791110                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          1256144                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                   75819284                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded             1655722                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                  93902738                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            178739                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined         4397586                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined      8688962                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved         172255                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     495550550                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.189492                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        0.548412                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           106692829     71.07%     71.07% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            13471343      8.97%     80.05% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2             6554897      4.37%     84.42% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3             5548193      3.70%     88.11% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            12665338      8.44%     96.55% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             2805396      1.87%     98.42% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             1723552      1.15%     99.57% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7              514218      0.34%     99.91% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              137526      0.09%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           430558497     86.88%     86.88% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            42998311      8.68%     95.56% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            15714626      3.17%     98.73% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3             5641325      1.14%     99.87% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4              637755      0.13%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                  36      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6                   0      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       150113292                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       495550550                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                   66740      0.75%      0.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      6      0.00%      0.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      0.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      0.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      0.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      0.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      0.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      0.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      0.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      0.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      0.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      0.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      0.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      0.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      0.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      0.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      0.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      0.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      0.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      0.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      0.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      0.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      0.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      0.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      0.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      0.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      0.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      0.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      0.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                8421993     94.18%     94.93% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                453824      5.07%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                 4849757     15.79%     15.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                    148      0.00%     15.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     15.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     15.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     15.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     15.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     15.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     15.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     15.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     15.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     15.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     15.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     15.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     15.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     15.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     15.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     15.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     15.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     15.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     15.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     15.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     15.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     15.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     15.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     15.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     15.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     15.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     15.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     15.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead               20356138     66.26%     82.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               5517293     17.96%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass             28518      0.02%      0.02% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu              58064867     47.22%     47.25% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                93414      0.08%     47.32% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     47.32% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     47.32% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     47.32% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     47.32% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     47.32% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     47.32% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     47.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     47.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     47.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     47.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     47.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     47.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                  21      0.00%     47.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     47.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     47.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     47.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc              15      0.00%     47.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     47.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     47.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     47.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     47.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     47.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     47.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc           2113      0.00%     47.33% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     47.33% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc           16      0.00%     47.33% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     47.33% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             52433900     42.64%     89.97% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            12332230     10.03%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass             28518      0.03%      0.03% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu              49538159     52.75%     52.79% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                91859      0.10%     52.88% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     52.88% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     52.88% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     52.88% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     52.88% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     52.88% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     52.88% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     52.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     52.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     52.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     52.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     52.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     52.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     52.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     52.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     52.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     52.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     52.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     52.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     52.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     52.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     52.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     52.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     52.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc           2111      0.00%     52.89% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     52.89% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     52.89% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     52.89% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             32267131     34.36%     87.25% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            11974960     12.75%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              122955094                       # Type of FU issued
-system.cpu.iq.rate                           0.258180                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     8942563                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.072730                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          405214220                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         117427083                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses     85619955                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads               23208                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes              12528                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses        10296                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              131856805                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                   12334                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads           652625                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total               93902738                       # Type of FU issued
+system.cpu.iq.rate                           0.188050                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    30723336                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.327183                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          714225557                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes          81867089                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses     74968821                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads               32544                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes              12124                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses        10212                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              124576093                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                   21463                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads           210027                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      4242114                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses         5511                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        31676                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      1637740                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      1045815                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses          542                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation         6661                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores       369450                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads     33981236                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked        675243                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads     17074256                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked       1003626                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                3134378                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                11621778                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles               1344860                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts            98019144                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            177250                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              19896895                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             13369840                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts            1412264                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                 282212                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                925122                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          31676                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         351157                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       270951                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts               622108                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             120868290                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              51786364                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           2086804                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                 684138                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                94162664                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles              98281305                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts            77651016                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts              14558741                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             12101093                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts            1114432                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                  20278                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents              98196726                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents           6661                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         210280                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       275497                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts               485777                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts              93247730                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              32000327                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts            605564                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                        226309                       # number of nop insts executed
-system.cpu.iew.exec_refs                     64008543                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 11843747                       # Number of branches executed
-system.cpu.iew.exec_stores                   12222179                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.253798                       # Inst execution rate
-system.cpu.iew.wb_sent                      119919333                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                      85630251                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                  47892202                       # num instructions producing a value
-system.cpu.iew.wb_consumers                  88557277                       # num instructions consuming a value
+system.cpu.iew.exec_nop                        176010                       # number of nop insts executed
+system.cpu.iew.exec_refs                     43889216                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 10791342                       # Number of branches executed
+system.cpu.iew.exec_stores                   11888889                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.186738                       # Inst execution rate
+system.cpu.iew.wb_sent                       92183788                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                      74979033                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                  35465784                       # num instructions producing a value
+system.cpu.iew.wb_consumers                  52709939                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.179805                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.540805                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       0.150153                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.672848                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts        19373634                       # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls         1482327                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            535963                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    146978914                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.528998                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.513466                       # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts         3942514                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls         1483467                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts            458978                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    494644570                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.147200                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     0.699335                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    118714103     80.77%     80.77% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     14514329      9.88%     90.64% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2      3718532      2.53%     93.17% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      2215097      1.51%     94.68% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      1629859      1.11%     95.79% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      1057435      0.72%     96.51% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      1495738      1.02%     97.53% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7       696782      0.47%     98.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      2937039      2.00%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    457921524     92.58%     92.58% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     22157230      4.48%     97.06% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      6973464      1.41%     98.47% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      2402706      0.49%     98.95% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      1803578      0.36%     99.32% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      1042786      0.21%     99.53% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6       592301      0.12%     99.65% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       490313      0.10%     99.75% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      1260668      0.25%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    146978914                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts             60459894                       # Number of instructions committed
-system.cpu.commit.committedOps               77751509                       # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total    494644570                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts             60462326                       # Number of instructions committed
+system.cpu.commit.committedOps               72811859                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                       27386881                       # Number of memory references committed
-system.cpu.commit.loads                      15654781                       # Number of loads committed
-system.cpu.commit.membars                      403574                       # Number of memory barriers committed
-system.cpu.commit.branches                   10306383                       # Number of branches committed
+system.cpu.commit.refs                       25244569                       # Number of memory references committed
+system.cpu.commit.loads                      13512926                       # Number of loads committed
+system.cpu.commit.membars                      403660                       # Number of memory barriers committed
+system.cpu.commit.branches                   10308073                       # Number of branches committed
 system.cpu.commit.fp_insts                      10212                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                  69191543                       # Number of committed integer instructions.
-system.cpu.commit.function_calls               991261                       # Number of function calls committed.
+system.cpu.commit.int_insts                  64250122                       # Number of committed integer instructions.
+system.cpu.commit.function_calls               991634                       # Number of function calls committed.
 system.cpu.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu         50274580     64.66%     64.66% # Class of committed instruction
-system.cpu.commit.op_class_0::IntMult           87935      0.11%     64.77% # Class of committed instruction
-system.cpu.commit.op_class_0::IntDiv                0      0.00%     64.77% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatAdd              0      0.00%     64.77% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatCmp              0      0.00%     64.77% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatCvt              0      0.00%     64.77% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMult             0      0.00%     64.77% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatDiv              0      0.00%     64.77% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     64.77% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAdd               0      0.00%     64.77% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     64.77% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAlu               0      0.00%     64.77% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdCmp               0      0.00%     64.77% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdCvt               0      0.00%     64.77% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMisc              0      0.00%     64.77% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMult              0      0.00%     64.77% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     64.77% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdShift             0      0.00%     64.77% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     64.77% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     64.77% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     64.77% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     64.77% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     64.77% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     64.77% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     64.77% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMisc         2113      0.00%     64.78% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     64.78% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     64.78% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     64.78% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead        15654781     20.13%     84.91% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite       11732100     15.09%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu         47477289     65.21%     65.21% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult           87890      0.12%     65.33% # Class of committed instruction
+system.cpu.commit.op_class_0::IntDiv                0      0.00%     65.33% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatAdd              0      0.00%     65.33% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCmp              0      0.00%     65.33% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCvt              0      0.00%     65.33% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatMult             0      0.00%     65.33% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatDiv              0      0.00%     65.33% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     65.33% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAdd               0      0.00%     65.33% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     65.33% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAlu               0      0.00%     65.33% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCmp               0      0.00%     65.33% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCvt               0      0.00%     65.33% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMisc              0      0.00%     65.33% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMult              0      0.00%     65.33% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     65.33% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShift             0      0.00%     65.33% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     65.33% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     65.33% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     65.33% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     65.33% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     65.33% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     65.33% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     65.33% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMisc         2111      0.00%     65.33% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     65.33% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     65.33% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     65.33% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead        13512926     18.56%     83.89% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite       11731643     16.11%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total          77751509                       # Class of committed instruction
-system.cpu.commit.bw_lim_events               2937039                       # number cycles where commit BW limit reached
+system.cpu.commit.op_class_0::total          72811859                       # Class of committed instruction
+system.cpu.commit.bw_lim_events               1260668                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                    239318561                       # The number of ROB reads
-system.cpu.rob.rob_writes                   197472000                       # The number of ROB writes
-system.cpu.timesIdled                         1764819                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                       326125217                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles                   4575456172                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts                    60309513                       # Number of Instructions Simulated
-system.cpu.committedOps                      77601128                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               7.896574                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         7.896574                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.126637                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.126637                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                548833940                       # number of integer regfile reads
-system.cpu.int_regfile_writes                87707844                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                      8328                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                     2914                       # number of floating regfile writes
-system.cpu.misc_regfile_reads               264312368                       # number of misc regfile reads
-system.cpu.misc_regfile_writes                1173237                       # number of misc regfile writes
-system.cpu.toL2Bus.throughput                58892733                       # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq        2658790                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       2658789                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteReq        763349                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteResp       763349                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback       607940                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq         2966                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::SCUpgradeReq           11                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp         2977                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       246105                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       246105                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1961974                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      5797376                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        30926                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       128827                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           7919103                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     62745984                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     85556470                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        42736                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       216536                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total      148561726                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus         148561726                       # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus       194772                       # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy     3129487727                       # Layer occupancy (ticks)
+system.cpu.rob.rob_reads                    568287463                       # The number of ROB reads
+system.cpu.rob.rob_writes                   154414560                       # The number of ROB writes
+system.cpu.timesIdled                          544007                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                         3799491                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles                   4584972685                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts                    60311945                       # Number of Instructions Simulated
+system.cpu.committedOps                      72661478                       # Number of Ops (including micro ops) Simulated
+system.cpu.cpi                               8.279455                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         8.279455                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.120781                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.120781                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                109116898                       # number of integer regfile reads
+system.cpu.int_regfile_writes                47012340                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                      8305                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                     2780                       # number of floating regfile writes
+system.cpu.cc_regfile_reads                 320404185                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                 30332896                       # number of cc regfile writes
+system.cpu.misc_regfile_reads               605539146                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                1173999                       # number of misc regfile writes
+system.cpu.toL2Bus.throughput                57498963                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq        2604292                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       2604292                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteReq        763357                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteResp       763357                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback       599976                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq         2950                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::SCUpgradeReq            2                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp         2952                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       246570                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       246570                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1926546                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      5768452                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        27160                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side        85384                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           7807542                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     61456864                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     84377274                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        37916                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       135596                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total      146007650                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus         146007650                       # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus       166384                       # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy     3090458553                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy    1474700416                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy    1447056987                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    2550487184                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    2544187527                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy      20248986                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.occupancy      17686240                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy      74797546                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy      51535649                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.cpu.icache.tags.replacements            980898                       # number of replacements
-system.cpu.icache.tags.tagsinuse           511.584882                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            10510158                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs            981410                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             10.709243                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle        6868426250                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   511.584882                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.999189                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.999189                       # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements            959881                       # number of replacements
+system.cpu.icache.tags.tagsinuse           511.383361                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            23149457                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs            960393                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             24.104150                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle       11344582250                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   511.383361                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.998796                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.998796                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          137                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          214                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          160                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          118                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          171                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          221                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          12553342                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         12553342                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     10510158                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        10510158                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      10510158                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         10510158                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     10510158                       # number of overall hits
-system.cpu.icache.overall_hits::total        10510158                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst      1061739                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total       1061739                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst      1061739                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total        1061739                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst      1061739                       # number of overall misses
-system.cpu.icache.overall_misses::total       1061739                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  14266290615                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  14266290615                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  14266290615                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  14266290615                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  14266290615                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  14266290615                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     11571897                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     11571897                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     11571897                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     11571897                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     11571897                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     11571897                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.091752                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.091752                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.091752                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.091752                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.091752                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.091752                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13436.720903                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13436.720903                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13436.720903                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13436.720903                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13436.720903                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13436.720903                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs         7331                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets          116                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs               335                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               1                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    21.883582                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets          116                       # average number of cycles each access was blocked
+system.cpu.icache.tags.tag_accesses          25115239                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         25115239                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     23149457                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        23149457                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      23149457                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         23149457                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     23149457                       # number of overall hits
+system.cpu.icache.overall_hits::total        23149457                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst      1005369                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total       1005369                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst      1005369                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total        1005369                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst      1005369                       # number of overall misses
+system.cpu.icache.overall_misses::total       1005369                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  13656038478                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  13656038478                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  13656038478                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  13656038478                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  13656038478                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  13656038478                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     24154826                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     24154826                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     24154826                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     24154826                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     24154826                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     24154826                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.041622                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.041622                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.041622                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.041622                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.041622                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.041622                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13583.110756                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13583.110756                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13583.110756                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13583.110756                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13583.110756                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13583.110756                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs         1617                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs               119                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    13.588235                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst        80293                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total        80293                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst        80293                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total        80293                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst        80293                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total        80293                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst       981446                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total       981446                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst       981446                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total       981446                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst       981446                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total       981446                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  11573178578                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  11573178578                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst  11573178578                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total  11573178578                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst  11573178578                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total  11573178578                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst      8964000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::total      8964000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst      8964000                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::total      8964000                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.084813                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.084813                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.084813                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.084813                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.084813                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.084813                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11791.966729                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11791.966729                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11791.966729                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 11791.966729                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11791.966729                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 11791.966729                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst        44956                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total        44956                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst        44956                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total        44956                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst        44956                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total        44956                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst       960413                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total       960413                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst       960413                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total       960413                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst       960413                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total       960413                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  11283890760                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total  11283890760                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst  11283890760                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total  11283890760                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst  11283890760                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total  11283890760                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst    223026500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_uncacheable_latency::total    223026500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst    223026500                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_latency::total    223026500                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.039761                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.039761                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.039761                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.039761                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.039761                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.039761                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11748.998358                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11748.998358                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11748.998358                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 11748.998358                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11748.998358                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 11748.998358                       # average overall mshr miss latency
 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements            64369                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        51363.817213                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            1888922                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           129761                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            14.556932                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle     2490733870000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 36937.336839                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker    33.862464                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.000252                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  8170.435646                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  6222.182012                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.563619                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000517                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.replacements            63302                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        51128.734687                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            1829071                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           128690                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            14.213000                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle     2530789670500                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 37302.599889                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker     6.814194                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.000703                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  7723.154288                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  6096.165612                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.569193                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000104                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000000                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.124671                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.094943                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.783750                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1023           23                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        65369                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1023::4           22                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           39                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          352                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         3050                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         6967                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        54961                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1023     0.000351                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.997452                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         18802940                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        18802940                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker        54086                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.itb.walker        10683                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.inst       967938                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data       387449                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        1420156                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks       607940                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total       607940                       # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data           43                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total           43                       # number of UpgradeReq hits
-system.cpu.l2cache.SCUpgradeReq_hits::cpu.data            8                       # number of SCUpgradeReq hits
-system.cpu.l2cache.SCUpgradeReq_hits::total            8                       # number of SCUpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       112904                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       112904                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.dtb.walker        54086                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.itb.walker        10683                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.inst       967938                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data       500353                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         1533060                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.dtb.walker        54086                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.itb.walker        10683                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.inst       967938                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data       500353                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        1533060                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker           48                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.itb.walker            1                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.inst        12347                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data        10729                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total        23125                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data         2923                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total         2923                       # number of UpgradeReq misses
-system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            3                       # number of SCUpgradeReq misses
-system.cpu.l2cache.SCUpgradeReq_misses::total            3                       # number of SCUpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       133201                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       133201                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.dtb.walker           48                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.itb.walker            1                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.inst        12347                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       143930                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        156326                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.dtb.walker           48                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.itb.walker            1                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.inst        12347                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       143930                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       156326                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker      3943500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker        83000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    890764250                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data    800380499                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total   1695171249                       # number of ReadReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data       583475                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total       583475                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   9778985980                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   9778985980                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker      3943500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.itb.walker        83000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    890764250                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  10579366479                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  11474157229                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker      3943500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.itb.walker        83000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    890764250                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  10579366479                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  11474157229                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker        54134                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker        10684                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.inst       980285                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data       398178                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total      1443281                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks       607940                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total       607940                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data         2966                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total         2966                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data           11                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu.l2cache.SCUpgradeReq_accesses::total           11                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       246105                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       246105                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.dtb.walker        54134                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.itb.walker        10684                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.inst       980285                       # number of demand (read+write) accesses
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-system.cpu.l2cache.demand_accesses::total      1689386                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.dtb.walker        54134                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.itb.walker        10684                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst       980285                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data       644283                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      1689386                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.000887                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.000094                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.012595                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.026945                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.016023                       # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.985502                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.985502                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data     0.272727                       # miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_miss_rate::total     0.272727                       # miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.541236                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.541236                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.000887                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000094                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.012595                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.223396                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.092534                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.000887                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000094                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.012595                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.223396                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.092534                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 82156.250000                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker        83000                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72144.184822                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74599.729611                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 73304.702659                       # average ReadReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data   199.615121                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total   199.615121                       # average UpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73415.259495                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73415.259495                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 82156.250000                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker        83000                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72144.184822                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73503.553665                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 73398.905038                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 82156.250000                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker        83000                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72144.184822                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73503.553665                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 73398.905038                       # average overall miss latency
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.117846                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.093020                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.780163                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1023            7                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        65381                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1023::4            7                       # Occupied blocks per task id
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+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          268                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         3024                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         6221                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        55835                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1023     0.000107                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.997635                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         18316308                       # Number of tag accesses
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+system.cpu.l2cache.ReadReq_hits::total        1368238                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks       599976                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total       599976                       # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data           41                       # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total           41                       # number of UpgradeReq hits
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+system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker       790250                       # number of ReadReq miss cycles
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+system.cpu.l2cache.Writeback_accesses::writebacks       599976                       # number of Writeback accesses(hits+misses)
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+system.cpu.l2cache.UpgradeReq_accesses::cpu.data         2950                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total         2950                       # number of UpgradeReq accesses(hits+misses)
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+system.cpu.l2cache.SCUpgradeReq_accesses::total            2                       # number of SCUpgradeReq accesses(hits+misses)
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+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71242.942252                       # average ReadReq miss latency
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+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70027.594200                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70027.594200                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 71840.909091                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 79583.333333                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71242.942252                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70379.754617                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 70444.865605                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 71840.909091                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 79583.333333                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71242.942252                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70379.754617                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 70444.865605                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1138,109 +1129,104 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        59141                       # number of writebacks
-system.cpu.l2cache.writebacks::total            59141                       # number of writebacks
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-system.cpu.l2cache.demand_mshr_hits::cpu.data           66                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total           77                       # number of demand (read+write) MSHR hits
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-system.cpu.l2cache.UpgradeReq_mshr_misses::total         2923                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            3                       # number of SCUpgradeReq MSHR misses
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-system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data        30003                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total        30003                       # number of SCUpgradeReq MSHR miss cycles
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-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   8800481519                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total   9538875269                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst      6435500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166942048250                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166948483750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data  17498078150                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total  17498078150                       # number of WriteReq MSHR uncacheable cycles
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-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 184440126400                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total 184446561900                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000887                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000094                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.012584                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.026779                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.015969                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.985502                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.985502                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data     0.272727                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.272727                       # mshr miss rate for SCUpgradeReq accesses
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-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.541236                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000887                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000094                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.012584                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.223293                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.092489                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000887                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000094                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.012584                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.223293                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.092489                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 69812.500000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker        71000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59579.422017                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62212.229110                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60819.279287                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10002.368115                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10002.368115                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        10001                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        10001                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61088.974707                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61088.974707                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 69812.500000                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker        71000                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59579.422017                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61172.228765                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61049.192436                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 69812.500000                       # average overall mshr miss latency
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-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59579.422017                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61172.228765                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61049.192436                       # average overall mshr miss latency
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+system.cpu.l2cache.writebacks::total            58488                       # number of writebacks
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+system.cpu.l2cache.ReadExReq_mshr_misses::total       133354                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker           10                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            3                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst        11640                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       143462                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       155115                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker           10                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            3                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst        11640                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       143462                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       155115                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker       596250                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker       201250                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    683475499                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data    632292750                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1316565749                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     29106909                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     29106909                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   7676486703                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   7676486703                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker       596250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       201250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    683475499                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   8308779453                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total   8993052452                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker       596250                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       201250                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    683475499                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   8308779453                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total   8993052452                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst    174348000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 167014389750                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167188737750                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data  17147727018                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total  17147727018                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst    174348000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 184162116768                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total 184336464768                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000295                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000316                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.012132                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.026102                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.015655                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.986102                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.986102                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.540836                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.540836                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000295                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000316                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.012132                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.226345                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.094777                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000295                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000316                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.012132                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.226345                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.094777                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker        59625                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 67083.333333                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58717.826375                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62553.695093                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60501.160287                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10005.812650                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10005.812650                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57564.727740                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57564.727740                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker        59625                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 67083.333333                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58717.826375                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57916.238816                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57976.678284                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker        59625                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 67083.333333                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58717.826375                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57916.238816                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57976.678284                       # average overall mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -1250,168 +1236,184 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements            643771                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.993313                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            21491250                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs            644283                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             33.356848                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle          42393250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.993313                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999987                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999987                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements            633309                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.949942                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            19068560                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            633821                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             30.085087                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle         267154250                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.949942                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.999902                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999902                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          195                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          299                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2           18                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          170                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          320                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           22                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         101573451                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        101573451                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     13743815                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        13743815                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      7253892                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        7253892                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data       242816                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       242816                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data       247598                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total       247598                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      20997707                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         20997707                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     20997707                       # number of overall hits
-system.cpu.dcache.overall_hits::total        20997707                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       762201                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        762201                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      2968429                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      2968429                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data        13530                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total        13530                       # number of LoadLockedReq misses
-system.cpu.dcache.StoreCondReq_misses::cpu.data           11                       # number of StoreCondReq misses
-system.cpu.dcache.StoreCondReq_misses::total           11                       # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data      3730630                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        3730630                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      3730630                       # number of overall misses
-system.cpu.dcache.overall_misses::total       3730630                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  10170757825                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  10170757825                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 136412874713                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 136412874713                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    184826749                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total    184826749                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       180503                       # number of StoreCondReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::total       180503                       # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 146583632538                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 146583632538                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 146583632538                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 146583632538                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     14506016                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     14506016                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data     10222321                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total     10222321                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data       256346                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total       256346                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data       247609                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total       247609                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     24728337                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     24728337                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     24728337                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     24728337                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.052544                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.052544                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.290387                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.290387                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.052780                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.052780                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000044                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::total     0.000044                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.150865                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.150865                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.150865                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.150865                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13343.931358                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 13343.931358                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45954.568802                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 45954.568802                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13660.513599                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13660.513599                       # average LoadLockedReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16409.363636                       # average StoreCondReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16409.363636                       # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 39291.924564                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 39291.924564                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 39291.924564                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 39291.924564                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs        33676                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets        25542                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs              2667                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets             316                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    12.626922                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets    80.829114                       # average number of cycles each access was blocked
+system.cpu.dcache.tags.tag_accesses          91797001                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         91797001                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     11311240                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        11311240                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      7209458                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        7209458                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data        60823                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total         60823                       # number of SoftPFReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data       236444                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total       236444                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data       247594                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total       247594                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data      18520698                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         18520698                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     18581521                       # number of overall hits
+system.cpu.dcache.overall_hits::total        18581521                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       573261                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        573261                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      3012484                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      3012484                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data       126501                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total       126501                       # number of SoftPFReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data        12988                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total        12988                       # number of LoadLockedReq misses
+system.cpu.dcache.StoreCondReq_misses::cpu.data            2                       # number of StoreCondReq misses
+system.cpu.dcache.StoreCondReq_misses::total            2                       # number of StoreCondReq misses
+system.cpu.dcache.demand_misses::cpu.data      3585745                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        3585745                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      3712246                       # number of overall misses
+system.cpu.dcache.overall_misses::total       3712246                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data   7216358166                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total   7216358166                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 126016512064                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 126016512064                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    178185500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total    178185500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::cpu.data        26000                       # number of StoreCondReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::total        26000                       # number of StoreCondReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 133232870230                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 133232870230                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 133232870230                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 133232870230                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     11884501                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     11884501                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data     10221942                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total     10221942                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data       187324                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total       187324                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data       249432                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total       249432                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data       247596                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total       247596                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     22106443                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     22106443                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     22293767                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     22293767                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.048236                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.048236                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.294708                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.294708                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.675306                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.675306                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.052070                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.052070                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000008                       # miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::total     0.000008                       # miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.162204                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.162204                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.166515                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.166515                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12588.259390                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 12588.259390                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41831.429499                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 41831.429499                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13719.240838                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13719.240838                       # average LoadLockedReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        13000                       # average StoreCondReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::total        13000                       # average StoreCondReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 37156.259084                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 37156.259084                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 35890.097324                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 35890.097324                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs        18826                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs              1227                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    15.343113                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       607940                       # number of writebacks
-system.cpu.dcache.writebacks::total            607940                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       376141                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       376141                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data      2719425                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total      2719425                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data         1345                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total         1345                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      3095566                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      3095566                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      3095566                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      3095566                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       386060                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       386060                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       249004                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       249004                       # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        12185                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total        12185                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data           11                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::total           11                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       635064                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       635064                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       635064                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       635064                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   4968476363                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   4968476363                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  11232028289                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  11232028289                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    145250501                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    145250501                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       158497                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       158497                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  16200504652                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  16200504652                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  16200504652                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  16200504652                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182335641750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182335641750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data  26891357119                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total  26891357119                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209226998869                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total 209226998869                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.026614                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.026614                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.024359                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.024359                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.047533                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.047533                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000044                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000044                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.025682                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.025682                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.025682                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.025682                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12869.699951                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12869.699951                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45107.822722                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45107.822722                       # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11920.435043                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11920.435043                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14408.818182                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14408.818182                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25510.034661                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 25510.034661                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25510.034661                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 25510.034661                       # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks       599976                       # number of writebacks
+system.cpu.dcache.writebacks::total            599976                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       271755                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       271755                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data      2763119                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total      2763119                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data         1233                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total         1233                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      3034874                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      3034874                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      3034874                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      3034874                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       301506                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       301506                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       249365                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       249365                       # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data        74145                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total        74145                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        11755                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total        11755                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            2                       # number of StoreCondReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::total            2                       # number of StoreCondReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       550871                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       550871                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       625016                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       625016                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   3569781578                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   3569781578                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  10783879319                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  10783879319                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   1231283000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   1231283000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    140188500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    140188500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data        22000                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::total        22000                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  14353660897                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  14353660897                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  15584943897                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  15584943897                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182408022250                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182408022250                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data  26599942575                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total  26599942575                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209007964825                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total 209007964825                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.025370                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.025370                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.024395                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.024395                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.395812                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.395812                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.047127                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.047127                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000008                       # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000008                       # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.024919                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.024919                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.028035                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.028035                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11839.835950                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11839.835950                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43245.360492                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43245.360492                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16606.419853                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16606.419853                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11925.861336                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11925.861336                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        11000                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        11000                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26056.301561                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 26056.301561                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24935.271892                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 24935.271892                       # average overall mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
@@ -1435,16 +1437,16 @@ system.iocache.avg_blocked_cycles::no_mshrs          nan                       #
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1711484214589                       # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1711484214589                       # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1711484214589                       # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1711484214589                       # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1736929447540                       # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1736929447540                       # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1736929447540                       # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1736929447540                       # number of overall MSHR uncacheable cycles
 system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average ReadReq mshr uncacheable latency
 system.iocache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average overall mshr uncacheable latency
 system.iocache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.quiesce                    83038                       # number of quiesce instructions executed
+system.cpu.kern.inst.quiesce                    83187                       # number of quiesce instructions executed
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt
index d741bed70..3b38aee5d 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt
@@ -1,168 +1,168 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.403860                       # Number of seconds simulated
-sim_ticks                                2403859810000                       # Number of ticks simulated
-final_tick                               2403859810000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.400983                       # Number of seconds simulated
+sim_ticks                                2400982506000                       # Number of ticks simulated
+final_tick                               2400982506000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 189252                       # Simulator instruction rate (inst/s)
-host_op_rate                                   243065                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             7540617560                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 419508                       # Number of bytes of host memory used
-host_seconds                                   318.79                       # Real time elapsed on the host
-sim_insts                                    60331162                       # Number of instructions simulated
-sim_ops                                      77486236                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 112943                       # Simulator instruction rate (inst/s)
+host_op_rate                                   135898                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             4496473277                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 411684                       # Number of bytes of host memory used
+host_seconds                                   533.97                       # Real time elapsed on the host
+sim_insts                                    60307964                       # Number of instructions simulated
+sim_ops                                      72565708                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::realview.clcd    114819072                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.dtb.walker           64                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.itb.walker          128                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst           510792                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data          7044824                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst           493064                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data          6826968                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu1.dtb.walker           64                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst            65024                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data           679232                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.dtb.walker          768                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst            75520                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data           799936                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.dtb.walker          704                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu2.inst           188416                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.data          1352768                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            124661152                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       510792                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst        65024                       # Number of instructions bytes read from this memory
+system.physmem.bytes_read::cpu2.data          1451264                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            124655200                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       493064                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst        75520                       # Number of instructions bytes read from this memory
 system.physmem.bytes_inst_read::cpu2.inst       188416                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          764232                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      3745216                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0.data       1298452                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1.data        159256                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu2.data       1558108                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           6761032                       # Number of bytes written to this memory
+system.physmem.bytes_inst_read::total          757000                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      3741312                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0.data       1144164                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1.data        159264                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu2.data       1712388                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           6757128                       # Number of bytes written to this memory
 system.physmem.num_reads::realview.clcd      14352384                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu0.dtb.walker            1                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu0.itb.walker            2                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             14193                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data            110111                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             13916                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data            106697                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu1.dtb.walker            1                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              1016                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data             10613                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.dtb.walker           12                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst              1180                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data             12499                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.dtb.walker           11                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu2.inst              2944                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.data             21137                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total              14512414                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           58519                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0.data           324613                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1.data            39814                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu2.data           389527                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               812473                       # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd        47764463                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_reads::cpu2.data             22676                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total              14512311                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           58458                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0.data           286041                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu1.data            39816                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu2.data           428097                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               812412                       # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd        47821703                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu0.dtb.walker            27                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu0.itb.walker            53                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst              212488                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data             2930630                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst              205359                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data             2843406                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu1.dtb.walker            27                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               27050                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              282559                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.dtb.walker           319                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst               78381                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data              562748                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                51858745                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         212488                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          27050                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst          78381                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             317919                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1558001                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data             540153                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data              66250                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu2.data             648169                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2812573                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1558001                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd       47764463                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               31454                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              333170                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.dtb.walker           293                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.inst               78475                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.data              604446                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                51918412                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         205359                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          31454                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu2.inst          78475                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             315288                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1558242                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data             476540                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1.data              66333                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu2.data             713203                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                2814318                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1558242                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd       47821703                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.dtb.walker           27                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.itb.walker           53                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             212488                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data            3470783                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             205359                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data            3319946                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu1.dtb.walker           27                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              27050                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             348809                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.dtb.walker          319                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst              78381                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data            1210918                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               54671318                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                      13444811                       # Number of read requests accepted
-system.physmem.writeReqs                       446538                       # Number of write requests accepted
-system.physmem.readBursts                    13444811                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     446538                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                860467840                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                        64                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   2823232                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                 109558976                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                2817972                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                        1                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                  402393                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs           2368                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0              835670                       # Per bank write bursts
-system.physmem.perBankRdBursts::1              835346                       # Per bank write bursts
-system.physmem.perBankRdBursts::2              835517                       # Per bank write bursts
-system.physmem.perBankRdBursts::3              836010                       # Per bank write bursts
-system.physmem.perBankRdBursts::4              837094                       # Per bank write bursts
-system.physmem.perBankRdBursts::5              837780                       # Per bank write bursts
-system.physmem.perBankRdBursts::6              837922                       # Per bank write bursts
-system.physmem.perBankRdBursts::7              839142                       # Per bank write bursts
-system.physmem.perBankRdBursts::8              840618                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              843327                       # Per bank write bursts
-system.physmem.perBankRdBursts::10             843373                       # Per bank write bursts
-system.physmem.perBankRdBursts::11             843894                       # Per bank write bursts
-system.physmem.perBankRdBursts::12             845193                       # Per bank write bursts
-system.physmem.perBankRdBursts::13             844981                       # Per bank write bursts
-system.physmem.perBankRdBursts::14             844356                       # Per bank write bursts
-system.physmem.perBankRdBursts::15             844587                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                2683                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                2536                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                2524                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                3040                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                3434                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                3138                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                2510                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                2271                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                2160                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                2378                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               2319                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               2803                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               3771                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               3447                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               2601                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               2498                       # Per bank write bursts
+system.physmem.bw_total::cpu1.inst              31454                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             399503                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.dtb.walker          293                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.inst              78475                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.data            1317649                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               54732730                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                      13448319                       # Number of read requests accepted
+system.physmem.writeReqs                       485647                       # Number of write requests accepted
+system.physmem.readBursts                    13448319                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     485647                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                860692416                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   3019520                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                 109787968                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                3006628                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                  438446                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs           2870                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0              835559                       # Per bank write bursts
+system.physmem.perBankRdBursts::1              835684                       # Per bank write bursts
+system.physmem.perBankRdBursts::2              835582                       # Per bank write bursts
+system.physmem.perBankRdBursts::3              835955                       # Per bank write bursts
+system.physmem.perBankRdBursts::4              836860                       # Per bank write bursts
+system.physmem.perBankRdBursts::5              838029                       # Per bank write bursts
+system.physmem.perBankRdBursts::6              838426                       # Per bank write bursts
+system.physmem.perBankRdBursts::7              839444                       # Per bank write bursts
+system.physmem.perBankRdBursts::8              841128                       # Per bank write bursts
+system.physmem.perBankRdBursts::9              843519                       # Per bank write bursts
+system.physmem.perBankRdBursts::10             843777                       # Per bank write bursts
+system.physmem.perBankRdBursts::11             843721                       # Per bank write bursts
+system.physmem.perBankRdBursts::12             845312                       # Per bank write bursts
+system.physmem.perBankRdBursts::13             845603                       # Per bank write bursts
+system.physmem.perBankRdBursts::14             845260                       # Per bank write bursts
+system.physmem.perBankRdBursts::15             844460                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                2621                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                2605                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                2850                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                3117                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                3557                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                3522                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                2837                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                2549                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                2654                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                2632                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               2402                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               2522                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               3817                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               3843                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               3141                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               2511                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    2402823771000                       # Total gap between requests
+system.physmem.totGap                    2398981428000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::3                13409088                       # Read request sizes (log2)
+system.physmem.readPktSize::3                13409008                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                   35723                       # Read request sizes (log2)
+system.physmem.readPktSize::6                   39311                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::2                 429341                       # Write request sizes (log2)
+system.physmem.writePktSize::2                 467913                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                  17197                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    877930                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    852855                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                    852810                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                    941410                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                    861042                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                    915654                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                   2398641                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                   2321801                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                   3038639                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                     92226                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                    84687                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                    80541                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                    77647                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                    16577                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                    16214                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                    16108                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                       28                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                  17734                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    878886                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    855155                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                    852902                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                    940592                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                    861312                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                    914649                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                   2399113                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                   2323436                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                   3041002                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                     91615                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                    84284                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                    79661                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                    76726                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                    16593                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                    16236                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                    16118                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                       39                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
@@ -178,42 +178,42 @@ system.physmem.rdQLenPdf::28                        0                       # Wh
 system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                       100                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1                       100                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                        98                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                        97                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                        96                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                        95                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                        95                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                        94                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                        94                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                        93                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10                       93                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                       93                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12                       92                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13                       92                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                       92                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     1920                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     2109                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     2300                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     2423                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     2579                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     2455                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     2431                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     2665                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     2414                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     2438                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     2433                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     2373                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     2390                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     2400                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     2348                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     2337                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     2336                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     2315                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                       27                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                       19                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                        9                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0                        99                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1                        96                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2                        95                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3                        93                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4                        93                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5                        92                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6                        92                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7                        92                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8                        90                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9                        90                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10                       90                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11                       90                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12                       90                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13                       88                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14                       88                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     2036                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     2365                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     2560                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     2603                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     2671                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     2642                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     2604                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     2620                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     2614                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     2693                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     2702                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     2526                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     2527                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     2628                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     2514                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     2506                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     2513                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     2480                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                       14                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                        4                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
@@ -242,83 +242,84 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       865990                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      996.883419                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     964.040735                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     145.863432                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127           8417      0.97%      0.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255         8847      1.02%      1.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         6111      0.71%      2.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511          842      0.10%      2.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639          894      0.10%      2.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767          743      0.09%      2.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         7672      0.89%      3.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          243      0.03%      3.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151       832221     96.10%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         865990                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          2416                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean      5564.893626                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev    258050.737776                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-524287         2415     99.96%     99.96% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples       866402                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      996.895132                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     964.187701                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     145.697526                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127           8320      0.96%      0.96% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255         8911      1.03%      1.99% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         6111      0.71%      2.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511          785      0.09%      2.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639          956      0.11%      2.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767          773      0.09%      2.98% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         7768      0.90%      3.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          290      0.03%      3.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151       832488     96.09%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         866402                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          2583                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean      5206.469222                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev    249565.705681                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-524287         2582     99.96%     99.96% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::1.25829e+07-1.31072e+07            1      0.04%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            2416                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          2416                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        18.258692                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.106432                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        2.116221                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::1                   1      0.04%      0.04% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::2                   2      0.08%      0.12% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::3                   2      0.08%      0.21% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::4                   1      0.04%      0.25% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::5                   1      0.04%      0.29% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::7                   1      0.04%      0.33% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::9                   1      0.04%      0.37% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::11                  2      0.08%      0.46% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::15                  5      0.21%      0.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16                486     20.12%     20.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17                 13      0.54%     21.32% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18                855     35.39%     56.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19                862     35.68%     92.38% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                 56      2.32%     94.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21                 20      0.83%     95.53% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22                 20      0.83%     96.36% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23                 33      1.37%     97.72% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24                 16      0.66%     98.39% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::25                  6      0.25%     98.63% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26                  6      0.25%     98.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::27                  4      0.17%     99.05% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28                  7      0.29%     99.34% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::29                  6      0.25%     99.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::30                  4      0.17%     99.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::31                  4      0.17%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32                  2      0.08%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            2416                       # Writes before turning the bus around for reads
-system.physmem.totQLat                   346456254750                       # Total ticks spent queuing
-system.physmem.totMemAccLat              598546442250                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                  67224050000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       25768.77                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            2583                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          2583                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        18.265583                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.091885                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        2.157240                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::1                   3      0.12%      0.12% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::2                   1      0.04%      0.15% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::3                   2      0.08%      0.23% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::4                   2      0.08%      0.31% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::5                   1      0.04%      0.35% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::6                   1      0.04%      0.39% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::8                   2      0.08%      0.46% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::9                   1      0.04%      0.50% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::13                  3      0.12%      0.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::15                  4      0.15%      0.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16                537     20.79%     21.56% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17                  7      0.27%     21.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18                754     29.19%     51.03% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19               1050     40.65%     91.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                100      3.87%     95.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                 31      1.20%     96.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22                 20      0.77%     97.52% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23                 15      0.58%     98.10% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24                  9      0.35%     98.45% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25                  3      0.12%     98.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26                  7      0.27%     98.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::27                  5      0.19%     99.03% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28                  5      0.19%     99.23% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::29                  5      0.19%     99.42% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::30                  6      0.23%     99.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::31                  4      0.15%     99.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32                  5      0.19%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            2583                       # Writes before turning the bus around for reads
+system.physmem.totQLat                   346447958000                       # Total ticks spent queuing
+system.physmem.totMemAccLat              598603939250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                  67241595000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       25761.43                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  44518.77                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         357.95                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           1.17                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       45.58                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        1.17                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  44511.43                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         358.48                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           1.26                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       45.73                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        1.25                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           2.81                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       2.80                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         8.26                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                         5.37                       # Average write queue length when enqueuing
-system.physmem.readRowHits                   12585053                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     37880                       # Number of row buffer hits during writes
+system.physmem.avgRdQLen                         7.91                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                         2.57                       # Average write queue length when enqueuing
+system.physmem.readRowHits                   12588353                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     40744                       # Number of row buffer hits during writes
 system.physmem.readRowHitRate                   93.61                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  85.81                       # Row buffer hit rate for writes
-system.physmem.avgGap                       172972.67                       # Average gap between requests
+system.physmem.writeRowHitRate                  86.32                       # Row buffer hit rate for writes
+system.physmem.avgGap                       172167.88                       # Average gap between requests
 system.physmem.pageHitRate                      93.58                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE     2167576169750                       # Time in different power states
-system.physmem.memoryStateTime::REF       80270060000                       # Time in different power states
+system.physmem.memoryStateTime::IDLE     2165142880250                       # Time in different power states
+system.physmem.memoryStateTime::REF       80173860000                       # Time in different power states
 system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT      156010779000                       # Time in different power states
+system.physmem.memoryStateTime::ACT      155659356000                       # Time in different power states
 system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
 system.realview.nvmem.bytes_read::cpu0.inst           20                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total            20                       # Number of bytes read from this memory
@@ -332,322 +333,323 @@ system.realview.nvmem.bw_inst_read::cpu0.inst            8
 system.realview.nvmem.bw_inst_read::total            8                       # Instruction read bandwidth from this memory (bytes/s)
 system.realview.nvmem.bw_total::cpu0.inst            8                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::total               8                       # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput                     55668579                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq            13780402                       # Transaction distribution
-system.membus.trans_dist::ReadResp           13780402                       # Transaction distribution
-system.membus.trans_dist::WriteReq             432242                       # Transaction distribution
-system.membus.trans_dist::WriteResp            432242                       # Transaction distribution
-system.membus.trans_dist::Writeback             17197                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             2368                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp            2368                       # Transaction distribution
-system.membus.trans_dist::ReadExReq             28083                       # Transaction distribution
-system.membus.trans_dist::ReadExResp            28083                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       732930                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio          220                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       952061                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total      1685211                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port     26818176                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total     26818176                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total               28503387                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave       736825                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio          440                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port      5104244                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::total      5841509                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port    107272704                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::total    107272704                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total           113114213                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus              133819459                       # Total data (bytes)
+system.membus.throughput                     55731244                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq            13775425                       # Transaction distribution
+system.membus.trans_dist::ReadResp           13775425                       # Transaction distribution
+system.membus.trans_dist::WriteReq             471057                       # Transaction distribution
+system.membus.trans_dist::WriteResp            471057                       # Transaction distribution
+system.membus.trans_dist::Writeback             17734                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq             2870                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp            2870                       # Transaction distribution
+system.membus.trans_dist::ReadExReq             31339                       # Transaction distribution
+system.membus.trans_dist::ReadExResp            31339                       # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       722736                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio          440                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio            2                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      1037922                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total      1761100                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port     26818016                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total     26818016                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total               28579116                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave       726717                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio          880                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio            4                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port      5522532                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::total      6250133                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port    107272064                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.iocache.mem_side::total    107272064                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total           113522197                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus              133809743                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy           417666500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy           411651000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy              209500                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy              449000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer6.occupancy         14570118500                       # Layer occupancy (ticks)
+system.membus.reqLayer4.occupancy                1500                       # Layer occupancy (ticks)
+system.membus.reqLayer4.utilization               0.0                       # Layer utilization (%)
+system.membus.reqLayer6.occupancy         14677819500                       # Layer occupancy (ticks)
 system.membus.reqLayer6.utilization               0.6                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         1595700088                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         1677943291                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
-system.membus.respLayer2.occupancy        33207877250                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy        33210614750                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              1.4                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.l2c.tags.replacements                    63255                       # number of replacements
-system.l2c.tags.tagsinuse                50395.732810                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    1749595                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                   128654                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                    13.599227                       # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle             2375537274500                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   36859.250431                       # Average occupied blocks per requestor
+system.l2c.tags.replacements                    63162                       # number of replacements
+system.l2c.tags.tagsinuse                50410.338960                       # Cycle average of tags in use
+system.l2c.tags.total_refs                    1759139                       # Total number of references to valid blocks.
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+system.l2c.tags.avg_refs                    13.684154                       # Average number of references to valid blocks.
+system.l2c.tags.warmup_cycle             2389834567500                       # Cycle when the warmup percentage was hit.
+system.l2c.tags.occ_blocks::writebacks   36865.555388                       # Average occupied blocks per requestor
 system.l2c.tags.occ_blocks::cpu0.dtb.walker     0.000018                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker     0.000124                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     5225.740605                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     3831.207928                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker     0.993318                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst      514.351835                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data      694.414886                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.dtb.walker    10.820575                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.inst     1674.526375                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.data     1584.426715                       # Average occupied blocks per requestor
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 system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000000                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu0.itb.walker     0.000000                       # Average percentage of cache occupancy
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 system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000015                       # Average percentage of cache occupancy
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-system.l2c.tags.occ_percent::cpu2.inst       0.025551                       # Average percentage of cache occupancy
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-system.l2c.tags.occ_task_id_blocks::1023            6                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024        65393                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4            6                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0           41                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1          343                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         2636                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         6462                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        55911                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1023     0.000092                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024     0.997818                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                 17684075                       # Number of tag accesses
-system.l2c.tags.data_accesses                17684075                       # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.dtb.walker         8753                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker         3188                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.inst             465928                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data             176871                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker         2616                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker         1178                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst             130375                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data              64441                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.dtb.walker        18901                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.itb.walker         4190                       # number of ReadReq hits
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-system.l2c.ReadReq_hits::cpu2.data             131860                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                1291106                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks          597736                       # number of Writeback hits
-system.l2c.Writeback_hits::total               597736                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data              14                       # number of UpgradeReq hits
+system.l2c.tags.occ_percent::cpu1.inst       0.012124                       # Average percentage of cache occupancy
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+system.l2c.tags.age_task_id_blocks_1024::0           40                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1          351                       # Occupied blocks per task id
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+system.l2c.tags.age_task_id_blocks_1024::3         6074                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        55872                       # Occupied blocks per task id
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 system.l2c.UpgradeReq_hits::cpu1.data               4                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu2.data              12                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                  30                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu2.data             3                       # number of SCUpgradeReq hits
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-system.l2c.overall_hits::cpu0.data             238574                       # number of overall hits
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-system.l2c.overall_hits::cpu1.data              83088                       # number of overall hits
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 system.l2c.ReadReq_misses::cpu0.itb.walker            2                       # number of ReadReq misses
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 system.l2c.ReadReq_misses::cpu1.dtb.walker            1                       # number of ReadReq misses
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-system.l2c.ReadReq_misses::cpu2.data             2552                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total                21680                       # number of ReadReq misses
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 system.l2c.UpgradeReq_misses::cpu1.data           481                       # number of UpgradeReq misses
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-system.l2c.UpgradeReq_misses::total              2906                       # number of UpgradeReq misses
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+system.l2c.UpgradeReq_misses::total              2904                       # number of UpgradeReq misses
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-system.l2c.UpgradeReq_miss_rate::cpu2.data     0.988304                       # miss rate for UpgradeReq accesses
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-system.l2c.overall_miss_rate::cpu1.inst      0.007733                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.115803                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.dtb.walker     0.000634                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.inst      0.010306                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.data      0.116373                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.099396                       # miss rate for overall accesses
+system.l2c.UpgradeReq_miss_rate::cpu2.data     0.989630                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.990788                       # miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.658652                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.401497                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu2.data     0.321652                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.540225                       # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker     0.000122                       # miss rate for demand accesses
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+system.l2c.overall_miss_rate::total          0.098749                       # miss rate for overall accesses
 system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker        74500                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.inst 70692.421260                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.data 75989.564831                       # average ReadReq miss latency
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-system.l2c.ReadReq_avg_miss_latency::total 26648.892989                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data   195.417879                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu2.data   137.568047                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total    80.347557                       # average UpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 72459.023268                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu2.data 73534.890417                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 15888.030827                       # average ReadExReq miss latency
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 system.l2c.demand_avg_miss_latency::cpu1.dtb.walker        74500                       # average overall miss latency
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 system.l2c.overall_avg_miss_latency::cpu1.dtb.walker        74500                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 70692.421260                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 72824.341206                       # average overall miss latency
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-system.l2c.overall_avg_miss_latency::cpu2.data 73876.431868                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 17392.803827                       # average overall miss latency
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+system.l2c.overall_avg_miss_latency::total 19033.703086                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -656,134 +658,134 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks               58519                       # number of writebacks
-system.l2c.writebacks::total                    58519                       # number of writebacks
-system.l2c.ReadReq_mshr_hits::cpu2.inst             1                       # number of ReadReq MSHR hits
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-system.l2c.demand_mshr_hits::cpu2.data             11                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total                 12                       # number of demand (read+write) MSHR hits
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-system.l2c.overall_mshr_hits::total                12                       # number of overall MSHR hits
+system.l2c.writebacks::writebacks               58458                       # number of writebacks
+system.l2c.writebacks::total                    58458                       # number of writebacks
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 system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker            1                       # number of ReadReq MSHR misses
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 system.l2c.ReadReq_mshr_misses::cpu2.inst         2944                       # number of ReadReq MSHR misses
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 system.l2c.UpgradeReq_mshr_misses::cpu1.data          481                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu2.data         1014                       # number of UpgradeReq MSHR misses
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 system.l2c.demand_mshr_misses::cpu1.dtb.walker            1                       # number of demand (read+write) MSHR misses
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 system.l2c.overall_mshr_misses::cpu1.dtb.walker            1                       # number of overall MSHR misses
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 system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker        62500                       # number of ReadReq MSHR miss cycles
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 system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data      4810481                       # number of UpgradeReq MSHR miss cycles
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-system.l2c.ReadReq_mshr_uncacheable_latency::total  51327074500                       # number of ReadReq MSHR uncacheable cycles
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-system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.000382                       # mshr miss rate for ReadReq accesses
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+system.l2c.overall_mshr_miss_latency::cpu1.data    752025752                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker       715000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.inst    182019500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.data   1438762796                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total   2443553298                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data  25042687500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data  25560602500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total  50603290000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    991271590                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data   9138698000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total  10129969590                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data  26033959090                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu2.data  34699300500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total  60733259590                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.000497                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.009810                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.020215                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker     0.000552                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2.inst     0.008790                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2.data     0.018911                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.006029                       # mshr miss rate for ReadReq accesses
 system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.991753                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data     0.988304                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.509196                       # mshr miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.343485                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu2.data     0.365679                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.117225                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.000382                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.007733                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.115803                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker     0.000634                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.inst     0.010303                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.data     0.116314                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.023462                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.000382                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.007733                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.115803                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker     0.000634                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.inst     0.010303                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.data     0.116314                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.023462                       # mshr miss rate for overall accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data     0.989630                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.619925                       # mshr miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.401497                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu2.data     0.321652                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.131182                       # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.000497                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.009810                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.143003                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker     0.000552                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.inst     0.008790                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.data     0.115601                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.025724                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.000497                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.009810                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.143003                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker     0.000552                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.inst     0.008790                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.data     0.115601                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.025724                       # mshr miss rate for overall accesses
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker        62500                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 58003.444882                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 63559.280639                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 61354.166667                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 63638.417120                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 64023.022432                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 63001.570681                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 59294.703390                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 62712.152209                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker        65000                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 61827.275815                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 64938.215379                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 62612.580908                       # average ReadReq mshr miss latency
 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data        10001                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10003.464497                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10002.671572                       # average UpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 59804.455617                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 61130.396042                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 60683.653578                       # average ReadExReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10011.104042                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10008.429279                       # average UpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 58581.967387                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 60826.070124                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 60027.346351                       # average ReadExReq mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker        62500                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 58003.444882                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 60192.980978                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 61354.166667                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 63638.417120                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.data 61468.474495                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 61167.555826                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 59294.703390                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 58977.786213                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker        65000                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 61827.275815                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.data 61283.928781                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 60537.937221                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker        62500                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 58003.444882                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 60192.980978                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 61354.166667                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 63638.417120                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.data 61468.474495                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 61167.555826                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 59294.703390                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 58977.786213                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker        65000                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 61827.275815                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.data 61283.928781                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 60537.937221                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -800,52 +802,51 @@ system.cf0.dma_read_txs                             0                       # Nu
 system.cf0.dma_write_full_pages                     0                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                          0                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
-system.toL2Bus.throughput                    58812389                       # Throughput (bytes/s)
-system.toL2Bus.trans_dist::ReadReq            1022771                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           1022770                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq            432242                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp           432242                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback           265826                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq            1511                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq             3                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp           1514                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq            80908                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp           80908                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side       834992                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      2422460                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side        15408                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        52756                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               3325616                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     26696960                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     37444261                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side        21472                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        86120                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size::total           64248813                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.data_through_bus             141273763                       # Total data (bytes)
-system.toL2Bus.snoop_data_through_bus          102976                       # Total snoop data (bytes)
-system.toL2Bus.reqLayer0.occupancy         2181217728                       # Layer occupancy (ticks)
+system.toL2Bus.throughput                    59108244                       # Throughput (bytes/s)
+system.toL2Bus.trans_dist::ReadReq            1059674                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp           1059674                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq            471057                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp           471057                       # Transaction distribution
+system.toL2Bus.trans_dist::Writeback           275568                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq            1835                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp           1835                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq            93577                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp           93577                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side       911138                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      2522746                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side        20145                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        55378                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total               3509407                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     29133952                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     38939733                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side        27844                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        87712                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size::total           68189241                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.data_through_bus             141801951                       # Total data (bytes)
+system.toL2Bus.snoop_data_through_bus          115908                       # Total snoop data (bytes)
+system.toL2Bus.reqLayer0.occupancy         2288858155                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy        1881226404                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy        2052757055                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy        1849082178                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy        1915102818                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy          10054967                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy          13212439                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy          31351984                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy          33686507                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
-system.iobus.throughput                      48758810                       # Throughput (bytes/s)
-system.iobus.trans_dist::ReadReq             13772718                       # Transaction distribution
-system.iobus.trans_dist::ReadResp            13772718                       # Transaction distribution
-system.iobus.trans_dist::WriteReq                2835                       # Transaction distribution
-system.iobus.trans_dist::WriteResp               2835                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        11646                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio         3040                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           20                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio          258                       # Packet count per connected master and slave (bytes)
+system.iobus.throughput                      48817267                       # Throughput (bytes/s)
+system.iobus.trans_dist::ReadReq             13767391                       # Transaction distribution
+system.iobus.trans_dist::ReadResp            13767391                       # Transaction distribution
+system.iobus.trans_dist::WriteReq                2985                       # Transaction distribution
+system.iobus.trans_dist::WriteResp               2985                       # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        12256                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio         3140                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           18                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio          288                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio       717678                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio       706746                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
@@ -861,18 +862,18 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total       732930                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side     26818176                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.clcd.dma::total     26818176                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                27551106                       # Packet count per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio        15610                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio         6080                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio           40                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio          516                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total       722736                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side     26818016                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.clcd.dma::total     26818016                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                27540752                       # Packet count per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio        16027                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio         6280                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio           36                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio          576                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio       714003                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio       703222                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
@@ -888,18 +889,18 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::total       736825                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side    107272704                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.realview.clcd.dma::total    107272704                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::total            108009529                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.data_through_bus               117209343                       # Total data (bytes)
-system.iobus.reqLayer0.occupancy              8145000                       # Layer occupancy (ticks)
+system.iobus.tot_pkt_size_system.bridge.master::total       726717                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side    107272064                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.realview.clcd.dma::total    107272064                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::total            107998781                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.data_through_bus               117209403                       # Total data (bytes)
+system.iobus.reqLayer0.occupancy              8657000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy              1520000                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy              1570000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy                20000                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy                18000                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy               129000                       # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy               144000                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer4.occupancy                 8000                       # Layer occupancy (ticks)
 system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
@@ -907,7 +908,7 @@ system.iobus.reqLayer5.occupancy                 8000                       # La
 system.iobus.reqLayer5.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer6.occupancy                 8000                       # Layer occupancy (ticks)
 system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer7.occupancy            359342000                       # Layer occupancy (ticks)
+system.iobus.reqLayer7.occupancy            353820000                       # Layer occupancy (ticks)
 system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer9.occupancy                 8000                       # Layer occupancy (ticks)
 system.iobus.reqLayer9.utilization                0.0                       # Layer utilization (%)
@@ -939,11 +940,11 @@ system.iobus.reqLayer22.occupancy                8000                       # La
 system.iobus.reqLayer22.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer23.occupancy                8000                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy         13409088000                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy         13409008000                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.6                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy           730095000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy           719751000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer1.occupancy         33780437750                       # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy         33775984250                       # Layer occupancy (ticks)
 system.iobus.respLayer1.utilization               1.4                       # Layer utilization (%)
 system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
@@ -968,25 +969,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # D
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                     7992228                       # DTB read hits
-system.cpu0.dtb.read_misses                      6211                       # DTB read misses
-system.cpu0.dtb.write_hits                    6585208                       # DTB write hits
-system.cpu0.dtb.write_misses                     1983                       # DTB write misses
-system.cpu0.dtb.flush_tlb                         556                       # Number of times complete TLB was flushed
+system.cpu0.dtb.read_hits                     6543805                       # DTB read hits
+system.cpu0.dtb.read_misses                      5435                       # DTB read misses
+system.cpu0.dtb.write_hits                    6063639                       # DTB write hits
+system.cpu0.dtb.write_misses                     1808                       # DTB write misses
+system.cpu0.dtb.flush_tlb                         554                       # Number of times complete TLB was flushed
 system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid                676                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid                     30                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                    5702                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.flush_tlb_mva_asid                493                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid                     23                       # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries                    5223                       # Number of entries that have been flushed from TLB
 system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                   117                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.prefetch_faults                   107                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                      210                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                 7998439                       # DTB read accesses
-system.cpu0.dtb.write_accesses                6587191                       # DTB write accesses
+system.cpu0.dtb.perms_faults                      162                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses                 6549240                       # DTB read accesses
+system.cpu0.dtb.write_accesses                6065447                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                         14577436                       # DTB hits
-system.cpu0.dtb.misses                           8194                       # DTB misses
-system.cpu0.dtb.accesses                     14585630                       # DTB accesses
+system.cpu0.dtb.hits                         12607444                       # DTB hits
+system.cpu0.dtb.misses                           7243                       # DTB misses
+system.cpu0.dtb.accesses                     12614687                       # DTB accesses
 system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -1008,468 +1009,486 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.inst_hits                    32348466                       # ITB inst hits
-system.cpu0.itb.inst_misses                      3468                       # ITB inst misses
+system.cpu0.itb.inst_hits                    30119411                       # ITB inst hits
+system.cpu0.itb.inst_misses                      2986                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
 system.cpu0.itb.write_misses                        0                       # DTB write misses
-system.cpu0.itb.flush_tlb                         556                       # Number of times complete TLB was flushed
+system.cpu0.itb.flush_tlb                         554                       # Number of times complete TLB was flushed
 system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid                676                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid                     30                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                    2648                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_tlb_mva_asid                493                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid                     23                       # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries                    2362                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses                32351934                       # ITB inst accesses
-system.cpu0.itb.hits                         32348466                       # DTB hits
-system.cpu0.itb.misses                           3468                       # DTB misses
-system.cpu0.itb.accesses                     32351934                       # DTB accesses
-system.cpu0.numCycles                       113676157                       # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses                30122397                       # ITB inst accesses
+system.cpu0.itb.hits                         30119411                       # DTB hits
+system.cpu0.itb.misses                           2986                       # DTB misses
+system.cpu0.itb.accesses                     30122397                       # DTB accesses
+system.cpu0.numCycles                       109377986                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                   31863567                       # Number of instructions committed
-system.cpu0.committedOps                     42010857                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses             37388293                       # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses                  5018                       # Number of float alu accesses
-system.cpu0.num_func_calls                    1197302                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts      4248978                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                    37388293                       # number of integer instructions
-system.cpu0.num_fp_insts                         5018                       # number of float instructions
-system.cpu0.num_int_register_reads          193803982                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes          39520708                       # number of times the integer registers were written
-system.cpu0.num_fp_register_reads                3589                       # number of times the floating registers were read
-system.cpu0.num_fp_register_writes               1430                       # number of times the floating registers were written
-system.cpu0.num_mem_refs                     15242780                       # number of memory refs
-system.cpu0.num_load_insts                    8359522                       # Number of load instructions
-system.cpu0.num_store_insts                   6883258                       # Number of store instructions
-system.cpu0.num_idle_cycles              110978931.176812                       # Number of idle cycles
-system.cpu0.num_busy_cycles              2697225.823188                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.023727                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.976273                       # Percentage of idle cycles
-system.cpu0.Branches                          5616963                       # Number of branches fetched
-system.cpu0.op_class::No_OpClass                14526      0.03%      0.03% # Class of executed instruction
-system.cpu0.op_class::IntAlu                 26777156     63.63%     63.66% # Class of executed instruction
-system.cpu0.op_class::IntMult                   49712      0.12%     63.78% # Class of executed instruction
-system.cpu0.op_class::IntDiv                        0      0.00%     63.78% # Class of executed instruction
-system.cpu0.op_class::FloatAdd                      0      0.00%     63.78% # Class of executed instruction
-system.cpu0.op_class::FloatCmp                      0      0.00%     63.78% # Class of executed instruction
-system.cpu0.op_class::FloatCvt                      0      0.00%     63.78% # Class of executed instruction
-system.cpu0.op_class::FloatMult                     0      0.00%     63.78% # Class of executed instruction
-system.cpu0.op_class::FloatDiv                      0      0.00%     63.78% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt                     0      0.00%     63.78% # Class of executed instruction
-system.cpu0.op_class::SimdAdd                       0      0.00%     63.78% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc                    0      0.00%     63.78% # Class of executed instruction
-system.cpu0.op_class::SimdAlu                       0      0.00%     63.78% # Class of executed instruction
-system.cpu0.op_class::SimdCmp                       0      0.00%     63.78% # Class of executed instruction
-system.cpu0.op_class::SimdCvt                       0      0.00%     63.78% # Class of executed instruction
-system.cpu0.op_class::SimdMisc                      0      0.00%     63.78% # Class of executed instruction
-system.cpu0.op_class::SimdMult                      0      0.00%     63.78% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc                   0      0.00%     63.78% # Class of executed instruction
-system.cpu0.op_class::SimdShift                     0      0.00%     63.78% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc                  0      0.00%     63.78% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt                      0      0.00%     63.78% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd                  0      0.00%     63.78% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu                  0      0.00%     63.78% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp                  0      0.00%     63.78% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt                  0      0.00%     63.78% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv                  0      0.00%     63.78% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc              1435      0.00%     63.78% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult                 0      0.00%     63.78% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     63.78% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     63.78% # Class of executed instruction
-system.cpu0.op_class::MemRead                 8359522     19.86%     83.64% # Class of executed instruction
-system.cpu0.op_class::MemWrite                6883258     16.36%    100.00% # Class of executed instruction
+system.cpu0.committedInsts                   29708958                       # Number of instructions committed
+system.cpu0.committedOps                     36436691                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses             32091710                       # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses                  4289                       # Number of float alu accesses
+system.cpu0.num_func_calls                    1119227                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts      3806697                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                    32091710                       # number of integer instructions
+system.cpu0.num_fp_insts                         4289                       # number of float instructions
+system.cpu0.num_int_register_reads           59433720                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes          21150393                       # number of times the integer registers were written
+system.cpu0.num_fp_register_reads                3327                       # number of times the floating registers were read
+system.cpu0.num_fp_register_writes                964                       # number of times the floating registers were written
+system.cpu0.num_cc_register_reads           109113758                       # number of times the CC registers were read
+system.cpu0.num_cc_register_writes           14198144                       # number of times the CC registers were written
+system.cpu0.num_mem_refs                     13068134                       # number of memory refs
+system.cpu0.num_load_insts                    6718957                       # Number of load instructions
+system.cpu0.num_store_insts                   6349177                       # Number of store instructions
+system.cpu0.num_idle_cycles              107075141.411044                       # Number of idle cycles
+system.cpu0.num_busy_cycles              2302844.588956                       # Number of busy cycles
+system.cpu0.not_idle_fraction                0.021054                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                    0.978946                       # Percentage of idle cycles
+system.cpu0.Branches                          5297571                       # Number of branches fetched
+system.cpu0.op_class::No_OpClass                11842      0.03%      0.03% # Class of executed instruction
+system.cpu0.op_class::IntAlu                 23375924     64.04%     64.07% # Class of executed instruction
+system.cpu0.op_class::IntMult                   45526      0.12%     64.20% # Class of executed instruction
+system.cpu0.op_class::IntDiv                        0      0.00%     64.20% # Class of executed instruction
+system.cpu0.op_class::FloatAdd                      0      0.00%     64.20% # Class of executed instruction
+system.cpu0.op_class::FloatCmp                      0      0.00%     64.20% # Class of executed instruction
+system.cpu0.op_class::FloatCvt                      0      0.00%     64.20% # Class of executed instruction
+system.cpu0.op_class::FloatMult                     0      0.00%     64.20% # Class of executed instruction
+system.cpu0.op_class::FloatDiv                      0      0.00%     64.20% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt                     0      0.00%     64.20% # Class of executed instruction
+system.cpu0.op_class::SimdAdd                       0      0.00%     64.20% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc                    0      0.00%     64.20% # Class of executed instruction
+system.cpu0.op_class::SimdAlu                       0      0.00%     64.20% # Class of executed instruction
+system.cpu0.op_class::SimdCmp                       0      0.00%     64.20% # Class of executed instruction
+system.cpu0.op_class::SimdCvt                       0      0.00%     64.20% # Class of executed instruction
+system.cpu0.op_class::SimdMisc                      0      0.00%     64.20% # Class of executed instruction
+system.cpu0.op_class::SimdMult                      0      0.00%     64.20% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc                   0      0.00%     64.20% # Class of executed instruction
+system.cpu0.op_class::SimdShift                     0      0.00%     64.20% # Class of executed instruction
+system.cpu0.op_class::SimdShiftAcc                  0      0.00%     64.20% # Class of executed instruction
+system.cpu0.op_class::SimdSqrt                      0      0.00%     64.20% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAdd                  0      0.00%     64.20% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAlu                  0      0.00%     64.20% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCmp                  0      0.00%     64.20% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCvt                  0      0.00%     64.20% # Class of executed instruction
+system.cpu0.op_class::SimdFloatDiv                  0      0.00%     64.20% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc              1430      0.00%     64.20% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMult                 0      0.00%     64.20% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     64.20% # Class of executed instruction
+system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     64.20% # Class of executed instruction
+system.cpu0.op_class::MemRead                 6718957     18.41%     82.61% # Class of executed instruction
+system.cpu0.op_class::MemWrite                6349177     17.39%    100.00% # Class of executed instruction
 system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu0.op_class::total                  42085609                       # Class of executed instruction
+system.cpu0.op_class::total                  36502856                       # Class of executed instruction
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                   82892                       # number of quiesce instructions executed
-system.cpu0.icache.tags.replacements           891568                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.602608                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs           43675041                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs           892080                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            48.958660                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle       8174940250                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   493.966915                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu1.inst     7.710732                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu2.inst     9.924961                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.964779                       # Average percentage of cache occupancy
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 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
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 system.cpu0.icache.tags.age_task_id_blocks_1024::2          164                       # Occupied blocks per task id
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 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
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 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
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+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst   1401871250                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst   3957248170                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total   5359119420                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst   1401871250                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst   3957248170                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total   5359119420                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst   1401871250                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst   3957248170                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total   5359119420                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.015103                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.082809                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.010816                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.015103                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst     0.082809                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.010816                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.015103                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst     0.082809                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.010816                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11630.215204                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 11799.191283                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11754.517064                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11630.215204                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 11799.191283                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 11754.517064                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11630.215204                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 11799.191283                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 11754.517064                       # average overall mshr miss latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.dcache.tags.replacements           629808                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          511.997118                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           23216736                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs           630320                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            36.833253                       # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle         21768000                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   497.011918                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu1.data     8.087644                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu2.data     6.897556                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.970726                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu1.data     0.015796                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu2.data     0.013472                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.replacements           630291                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          511.997117                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs           21342473                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs           630803                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            33.833817                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.warmup_cycle         21757000                       # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   497.608321                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu1.data     7.871908                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu2.data     6.516888                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.971891                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu1.data     0.015375                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu2.data     0.012728                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_percent::total     0.999994                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0          196                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0          194                       # Occupied blocks per task id
 system.cpu0.dcache.tags.age_task_id_blocks_1024::1          298                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           18                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           20                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses         98838984                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses        98838984                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data      6862400                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu1.data      1819912                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu2.data      4640111                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total       13322423                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data      5954558                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu1.data      1318615                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu2.data      2132591                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total       9405764                       # number of WriteReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       131484                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu1.data        33204                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu2.data        73477                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       238165                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       137939                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu1.data        34940                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu2.data        74507                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       247386                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data     12816958                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu1.data      3138527                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu2.data      6772702                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        22728187                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data     12816958                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu1.data      3138527                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu2.data      6772702                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       22728187                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data       176874                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu1.data        63831                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu2.data       275088                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total       515793                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data       167529                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu1.data        28888                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu2.data       614266                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total       810683                       # number of WriteReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         6455                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu1.data         1736                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu2.data         3758                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total        11949                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu2.data            3                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total            3                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data       344403                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu1.data        92719                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu2.data       889354                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       1326476                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data       344403                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu1.data        92719                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu2.data       889354                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      1326476                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu1.data    908477250                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::cpu2.data   3946035800                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total   4854513050                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu1.data    993858250                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu2.data  22101160686                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total  23095018936                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data     22777000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data     50452248                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total     73229248                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data        39000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total        39000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu1.data   1902335500                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu2.data  26047196486                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total  27949531986                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu1.data   1902335500                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu2.data  26047196486                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total  27949531986                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data      7039274                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu1.data      1883743                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu2.data      4915199                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total     13838216                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data      6122087                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu1.data      1347503                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu2.data      2746857                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total     10216447                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       137939                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data        34940                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data        77235                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       250114                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       137939                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu1.data        34940                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu2.data        74510                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       247389                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data     13161361                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu1.data      3231246                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu2.data      7662056                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     24054663                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data     13161361                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu1.data      3231246                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu2.data      7662056                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     24054663                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.025127                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.033885                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu2.data     0.055967                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.037273                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.027365                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.021438                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu2.data     0.223625                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.079351                       # miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.046796                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.049685                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data     0.048657                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.047774                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data     0.000040                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000012                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.026168                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu1.data     0.028695                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu2.data     0.116073                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.055144                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.026168                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu1.data     0.028695                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu2.data     0.116073                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.055144                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14232.539832                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14344.630809                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total  9411.746670                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 34403.844157                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 35979.788375                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 28488.347401                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13120.391705                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 13425.292177                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total  6128.483388                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data        13000                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total        13000                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 20517.213300                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 29287.771220                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 21070.514646                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 20517.213300                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 29287.771220                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 21070.514646                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs         7838                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets         2641                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs              847                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets             52                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs     9.253837                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets    50.788462                       # average number of cycles each access was blocked
+system.cpu0.dcache.tags.tag_accesses         92219903                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses        92219903                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data      5361652                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu1.data      1457794                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu2.data      4730320                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total       11549766                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data      5493900                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu1.data      1274863                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu2.data      2443484                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total       9212247                       # number of WriteReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu0.data        53400                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu1.data        14515                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu2.data        23676                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::total        91591                       # number of SoftPFReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       122744                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu1.data        31335                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu2.data        84381                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       238460                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data       128815                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu1.data        32780                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu2.data        85814                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       247409                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data     10855552                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu1.data      2732657                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu2.data      7173804                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total        20762013                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data     10908952                       # number of overall hits
+system.cpu0.dcache.overall_hits::cpu1.data      2747172                       # number of overall hits
+system.cpu0.dcache.overall_hits::cpu2.data      7197480                       # number of overall hits
+system.cpu0.dcache.overall_hits::total       20853604                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data       142161                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::cpu1.data        45809                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::cpu2.data       256649                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total       444619                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data       154444                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu1.data        29861                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu2.data       820607                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total      1004912                       # number of WriteReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu0.data        36971                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu1.data        17584                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu2.data        41738                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::total        96293                       # number of SoftPFReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         6071                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu1.data         1446                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu2.data         4461                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total        11978                       # number of LoadLockedReq misses
+system.cpu0.dcache.demand_misses::cpu0.data       296605                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu1.data        75670                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu2.data      1077256                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total       1449531                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data       333576                       # number of overall misses
+system.cpu0.dcache.overall_misses::cpu1.data        93254                       # number of overall misses
+system.cpu0.dcache.overall_misses::cpu2.data      1118994                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      1545824                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu1.data    618572999                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::cpu2.data   3601097882                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total   4219670881                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   1127965983                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu2.data  26744225136                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total  27872191119                       # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data     19459500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data     65741241                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total     85200741                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu1.data   1746538982                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu2.data  30345323018                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total  32091862000                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu1.data   1746538982                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu2.data  30345323018                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total  32091862000                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data      5503813                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu1.data      1503603                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu2.data      4986969                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total     11994385                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data      5648344                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu1.data      1304724                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu2.data      3264091                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total     10217159                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu0.data        90371                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu1.data        32099                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu2.data        65414                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total       187884                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       128815                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data        32781                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data        88842                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       250438                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       128815                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu1.data        32780                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu2.data        85814                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       247409                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data     11152157                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu1.data      2808327                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu2.data      8251060                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     22211544                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data     11242528                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu1.data      2840426                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu2.data      8316474                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     22399428                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.025830                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.030466                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu2.data     0.051464                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.037069                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.027343                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.022887                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu2.data     0.251404                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.098355                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.409102                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.547805                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data     0.638059                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.512513                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.047130                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.044111                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data     0.050213                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.047828                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.026596                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu1.data     0.026945                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu2.data     0.130560                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.065260                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.029671                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu1.data     0.032831                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu2.data     0.134551                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.069012                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 13503.307189                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14031.217273                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total  9490.532076                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 37773.885101                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 32590.783574                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 27735.952122                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13457.468880                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 14736.884331                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total  7113.102438                       # average LoadLockedReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 23080.996194                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 28169.091672                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 22139.479597                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 18728.837176                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 27118.396540                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 20760.359523                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs        38637                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets         6212                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs             5775                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets            192                       # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs     6.690390                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets    32.354167                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       597736                       # number of writebacks
-system.cpu0.dcache.writebacks::total           597736                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data       143982                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total       143982                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data       560780                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total       560780                       # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data          407                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total          407                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu2.data       704762                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total       704762                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu2.data       704762                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total       704762                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data        63831                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data       131106                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       194937                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data        28888                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data        53486                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total        82374                       # number of WriteReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         1736                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data         3351                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total         5087                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data            3                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total            3                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu1.data        92719                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu2.data       184592                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total       277311                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu1.data        92719                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu2.data       184592                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total       277311                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data    780623750                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data   1700229865                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total   2480853615                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data    933509750                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data   1853484745                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total   2786994495                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     19304000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data     38850752                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     58154752                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data        33000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total        33000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   1714133500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data   3553714610                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total   5267848110                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   1714133500                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data   3553714610                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total   5267848110                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data  27350994000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data  28703901500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total  56054895500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   1444132955                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data  13356723550                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total  14800856505                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data  28795126955                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data  42060625050                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total  70855752005                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.033885                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.026674                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.014087                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.021438                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.019472                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.008063                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.049685                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data     0.043387                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.020339                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data     0.000040                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000012                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.028695                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.024092                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.011528                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.028695                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.024092                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.011528                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12229.539722                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12968.360449                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12726.437849                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32314.793340                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 34653.642916                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33833.424321                       # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11119.815668                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 11593.778574                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11432.033025                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data        11000                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total        11000                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 18487.402798                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 19251.726023                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18996.174367                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 18487.402798                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 19251.726023                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18996.174367                       # average overall mshr miss latency
+system.cpu0.dcache.writebacks::writebacks       597941                       # number of writebacks
+system.cpu0.dcache.writebacks::total           597941                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data           82                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data       146159                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total       146241                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data          661                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data       754425                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total       755086                       # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data          467                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total          467                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu1.data          743                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu2.data       900584                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total       901327                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu1.data          743                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu2.data       900584                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total       901327                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data        45727                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data       110490                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total       156217                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data        29200                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data        66182                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total        95382                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data        13278                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data        23770                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total        37048                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         1446                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data         3994                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total         5440                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu1.data        74927                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu2.data       176672                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total       251599                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu1.data        88205                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu2.data       200442                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total       288647                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data    526256000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data   1348662754                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total   1874918754                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   1036082517                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data   2113089467                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total   3149171984                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    204786500                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data    440091753                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total    644878253                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     16565500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data     51817259                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     68382759                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   1562338517                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data   3461752221                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total   5024090738                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   1767125017                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data   3901843974                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total   5668968991                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data  27358748000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data  27904372000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total  55263120000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   1501669410                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data  14569249955                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total  16070919365                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data  28860417410                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data  42473621955                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total  71334039365                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.030412                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.022156                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.013024                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.022380                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.020276                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.009335                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.413658                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data     0.363378                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.197185                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.044111                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data     0.044956                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.021722                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.026680                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.021412                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.011327                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.031053                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.024102                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.012886                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11508.649157                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12206.197430                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12002.014851                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35482.277979                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 31928.461923                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33016.418024                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15422.992921                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 18514.587842                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 17406.560489                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11456.085754                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12973.775413                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12570.360110                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 20851.475663                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 19594.232368                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19968.643508                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 20034.295301                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 19466.199569                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19639.798754                       # average overall mshr miss latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -1503,25 +1522,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # D
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                     2096820                       # DTB read hits
-system.cpu1.dtb.read_misses                      2107                       # DTB read misses
-system.cpu1.dtb.write_hits                    1423125                       # DTB write hits
-system.cpu1.dtb.write_misses                      370                       # DTB write misses
-system.cpu1.dtb.flush_tlb                         554                       # Number of times complete TLB was flushed
+system.cpu1.dtb.read_hits                     1746639                       # DTB read hits
+system.cpu1.dtb.read_misses                      1917                       # DTB read misses
+system.cpu1.dtb.write_hits                    1378449                       # DTB write hits
+system.cpu1.dtb.write_misses                      367                       # DTB write misses
+system.cpu1.dtb.flush_tlb                         552                       # Number of times complete TLB was flushed
 system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid                233                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid                     12                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                    1777                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.flush_tlb_mva_asid                251                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid                     10                       # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries                    1626                       # Number of entries that have been flushed from TLB
 system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                    37                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.prefetch_faults                    33                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                       78                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                 2098927                       # DTB read accesses
-system.cpu1.dtb.write_accesses                1423495                       # DTB write accesses
+system.cpu1.dtb.perms_faults                       77                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses                 1748556                       # DTB read accesses
+system.cpu1.dtb.write_accesses                1378816                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                          3519945                       # DTB hits
-system.cpu1.dtb.misses                           2477                       # DTB misses
-system.cpu1.dtb.accesses                      3522422                       # DTB accesses
+system.cpu1.dtb.hits                          3125088                       # DTB hits
+system.cpu1.dtb.misses                           2284                       # DTB misses
+system.cpu1.dtb.accesses                      3127372                       # DTB accesses
 system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -1543,96 +1562,98 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.inst_hits                     8175454                       # ITB inst hits
-system.cpu1.itb.inst_misses                      1196                       # ITB inst misses
+system.cpu1.itb.inst_hits                     7981130                       # ITB inst hits
+system.cpu1.itb.inst_misses                      1058                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
 system.cpu1.itb.write_misses                        0                       # DTB write misses
-system.cpu1.itb.flush_tlb                         554                       # Number of times complete TLB was flushed
+system.cpu1.itb.flush_tlb                         552                       # Number of times complete TLB was flushed
 system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid                233                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid                     12                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                     946                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_tlb_mva_asid                251                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid                     10                       # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries                     834                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses                 8176650                       # ITB inst accesses
-system.cpu1.itb.hits                          8175454                       # DTB hits
-system.cpu1.itb.misses                           1196                       # DTB misses
-system.cpu1.itb.accesses                      8176650                       # DTB accesses
-system.cpu1.numCycles                       584791217                       # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses                 7982188                       # ITB inst accesses
+system.cpu1.itb.hits                          7981130                       # DTB hits
+system.cpu1.itb.misses                           1058                       # DTB misses
+system.cpu1.itb.accesses                      7982188                       # DTB accesses
+system.cpu1.numCycles                       582833153                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                    7972563                       # Number of instructions committed
-system.cpu1.committedOps                     10134873                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses              9111769                       # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses                  2002                       # Number of float alu accesses
-system.cpu1.num_func_calls                     305506                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts      1114419                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                     9111769                       # number of integer instructions
-system.cpu1.num_fp_insts                         2002                       # number of float instructions
-system.cpu1.num_int_register_reads           53111503                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes           9891567                       # number of times the integer registers were written
-system.cpu1.num_fp_register_reads                1488                       # number of times the floating registers were read
-system.cpu1.num_fp_register_writes                516                       # number of times the floating registers were written
-system.cpu1.num_mem_refs                      3688880                       # number of memory refs
-system.cpu1.num_load_insts                    2190803                       # Number of load instructions
-system.cpu1.num_store_insts                   1498077                       # Number of store instructions
-system.cpu1.num_idle_cycles              549443201.253140                       # Number of idle cycles
-system.cpu1.num_busy_cycles              35348015.746859                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.060446                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.939554                       # Percentage of idle cycles
-system.cpu1.Branches                          1447411                       # Number of branches fetched
-system.cpu1.op_class::No_OpClass                 5397      0.05%      0.05% # Class of executed instruction
-system.cpu1.op_class::IntAlu                  6618001     64.10%     64.15% # Class of executed instruction
-system.cpu1.op_class::IntMult                   11557      0.11%     64.27% # Class of executed instruction
-system.cpu1.op_class::IntDiv                        0      0.00%     64.27% # Class of executed instruction
-system.cpu1.op_class::FloatAdd                      0      0.00%     64.27% # Class of executed instruction
-system.cpu1.op_class::FloatCmp                      0      0.00%     64.27% # Class of executed instruction
-system.cpu1.op_class::FloatCvt                      0      0.00%     64.27% # Class of executed instruction
-system.cpu1.op_class::FloatMult                     0      0.00%     64.27% # Class of executed instruction
-system.cpu1.op_class::FloatDiv                      0      0.00%     64.27% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt                     0      0.00%     64.27% # Class of executed instruction
-system.cpu1.op_class::SimdAdd                       0      0.00%     64.27% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc                    0      0.00%     64.27% # Class of executed instruction
-system.cpu1.op_class::SimdAlu                       0      0.00%     64.27% # Class of executed instruction
-system.cpu1.op_class::SimdCmp                       0      0.00%     64.27% # Class of executed instruction
-system.cpu1.op_class::SimdCvt                       0      0.00%     64.27% # Class of executed instruction
-system.cpu1.op_class::SimdMisc                      0      0.00%     64.27% # Class of executed instruction
-system.cpu1.op_class::SimdMult                      0      0.00%     64.27% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc                   0      0.00%     64.27% # Class of executed instruction
-system.cpu1.op_class::SimdShift                     0      0.00%     64.27% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc                  0      0.00%     64.27% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt                      0      0.00%     64.27% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd                  0      0.00%     64.27% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu                  0      0.00%     64.27% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp                  0      0.00%     64.27% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt                  0      0.00%     64.27% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv                  0      0.00%     64.27% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc               298      0.00%     64.27% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult                 0      0.00%     64.27% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     64.27% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     64.27% # Class of executed instruction
-system.cpu1.op_class::MemRead                 2190803     21.22%     85.49% # Class of executed instruction
-system.cpu1.op_class::MemWrite                1498077     14.51%    100.00% # Class of executed instruction
+system.cpu1.committedInsts                    7797141                       # Number of instructions committed
+system.cpu1.committedOps                      9191219                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses              8219243                       # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses                  1689                       # Number of float alu accesses
+system.cpu1.num_func_calls                     289029                       # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts       993030                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                     8219243                       # number of integer instructions
+system.cpu1.num_fp_insts                         1689                       # number of float instructions
+system.cpu1.num_int_register_reads           14554839                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes           5500250                       # number of times the integer registers were written
+system.cpu1.num_fp_register_reads                1177                       # number of times the floating registers were read
+system.cpu1.num_fp_register_writes                512                       # number of times the floating registers were written
+system.cpu1.num_cc_register_reads            33218155                       # number of times the CC registers were read
+system.cpu1.num_cc_register_writes            3793046                       # number of times the CC registers were written
+system.cpu1.num_mem_refs                      3251661                       # number of memory refs
+system.cpu1.num_load_insts                    1804549                       # Number of load instructions
+system.cpu1.num_store_insts                   1447112                       # Number of store instructions
+system.cpu1.num_idle_cycles              548698663.963538                       # Number of idle cycles
+system.cpu1.num_busy_cycles              34134489.036462                       # Number of busy cycles
+system.cpu1.not_idle_fraction                0.058566                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                    0.941434                       # Percentage of idle cycles
+system.cpu1.Branches                          1360376                       # Number of branches fetched
+system.cpu1.op_class::No_OpClass                 4595      0.05%      0.05% # Class of executed instruction
+system.cpu1.op_class::IntAlu                  6078995     65.05%     65.10% # Class of executed instruction
+system.cpu1.op_class::IntMult                   10163      0.11%     65.20% # Class of executed instruction
+system.cpu1.op_class::IntDiv                        0      0.00%     65.20% # Class of executed instruction
+system.cpu1.op_class::FloatAdd                      0      0.00%     65.20% # Class of executed instruction
+system.cpu1.op_class::FloatCmp                      0      0.00%     65.20% # Class of executed instruction
+system.cpu1.op_class::FloatCvt                      0      0.00%     65.20% # Class of executed instruction
+system.cpu1.op_class::FloatMult                     0      0.00%     65.20% # Class of executed instruction
+system.cpu1.op_class::FloatDiv                      0      0.00%     65.20% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt                     0      0.00%     65.20% # Class of executed instruction
+system.cpu1.op_class::SimdAdd                       0      0.00%     65.20% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc                    0      0.00%     65.20% # Class of executed instruction
+system.cpu1.op_class::SimdAlu                       0      0.00%     65.20% # Class of executed instruction
+system.cpu1.op_class::SimdCmp                       0      0.00%     65.20% # Class of executed instruction
+system.cpu1.op_class::SimdCvt                       0      0.00%     65.20% # Class of executed instruction
+system.cpu1.op_class::SimdMisc                      0      0.00%     65.20% # Class of executed instruction
+system.cpu1.op_class::SimdMult                      0      0.00%     65.20% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc                   0      0.00%     65.20% # Class of executed instruction
+system.cpu1.op_class::SimdShift                     0      0.00%     65.20% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc                  0      0.00%     65.20% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt                      0      0.00%     65.20% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd                  0      0.00%     65.20% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu                  0      0.00%     65.20% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp                  0      0.00%     65.20% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt                  0      0.00%     65.20% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv                  0      0.00%     65.20% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc               281      0.00%     65.21% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult                 0      0.00%     65.21% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     65.21% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     65.21% # Class of executed instruction
+system.cpu1.op_class::MemRead                 1804549     19.31%     84.52% # Class of executed instruction
+system.cpu1.op_class::MemWrite                1447112     15.48%    100.00% # Class of executed instruction
 system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu1.op_class::total                  10324133                       # Class of executed instruction
+system.cpu1.op_class::total                   9345695                       # Class of executed instruction
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
-system.cpu2.branchPred.lookups                4844951                       # Number of BP lookups
-system.cpu2.branchPred.condPredicted          3958364                       # Number of conditional branches predicted
-system.cpu2.branchPred.condIncorrect           223288                       # Number of conditional branches incorrect
-system.cpu2.branchPred.BTBLookups             3209464                       # Number of BTB lookups
-system.cpu2.branchPred.BTBHits                2561917                       # Number of BTB hits
+system.cpu2.branchPred.lookups                5844133                       # Number of BP lookups
+system.cpu2.branchPred.condPredicted          4389690                       # Number of conditional branches predicted
+system.cpu2.branchPred.condIncorrect           248799                       # Number of conditional branches incorrect
+system.cpu2.branchPred.BTBLookups             3701982                       # Number of BTB lookups
+system.cpu2.branchPred.BTBHits                2861782                       # Number of BTB hits
 system.cpu2.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu2.branchPred.BTBHitPct            79.823827                       # BTB Hit Percentage
-system.cpu2.branchPred.usedRAS                 415777                       # Number of times the RAS was used to get a target.
-system.cpu2.branchPred.RASInCorrect             21493                       # Number of incorrect RAS predictions.
+system.cpu2.branchPred.BTBHitPct            77.304050                       # BTB Hit Percentage
+system.cpu2.branchPred.usedRAS                 588875                       # Number of times the RAS was used to get a target.
+system.cpu2.branchPred.RASInCorrect             15609                       # Number of incorrect RAS predictions.
 system.cpu2.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu2.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu2.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -1656,25 +1677,25 @@ system.cpu2.dstage2_mmu.stage2_tlb.misses            0                       # D
 system.cpu2.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu2.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu2.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu2.dtb.read_hits                    10946099                       # DTB read hits
-system.cpu2.dtb.read_misses                     23259                       # DTB read misses
-system.cpu2.dtb.write_hits                    3358425                       # DTB write hits
-system.cpu2.dtb.write_misses                     6569                       # DTB write misses
-system.cpu2.dtb.flush_tlb                         552                       # Number of times complete TLB was flushed
+system.cpu2.dtb.read_hits                    13926534                       # DTB read hits
+system.cpu2.dtb.read_misses                     28241                       # DTB read misses
+system.cpu2.dtb.write_hits                    3979346                       # DTB write hits
+system.cpu2.dtb.write_misses                     9743                       # DTB write misses
+system.cpu2.dtb.flush_tlb                         550                       # Number of times complete TLB was flushed
 system.cpu2.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu2.dtb.flush_tlb_mva_asid                530                       # Number of times TLB was flushed by MVA & ASID
-system.cpu2.dtb.flush_tlb_asid                     21                       # Number of times TLB was flushed by ASID
-system.cpu2.dtb.flush_entries                    2341                       # Number of entries that have been flushed from TLB
-system.cpu2.dtb.align_faults                      761                       # Number of TLB faults due to alignment restrictions
-system.cpu2.dtb.prefetch_faults                   169                       # Number of TLB faults due to prefetch
+system.cpu2.dtb.flush_tlb_mva_asid                695                       # Number of times TLB was flushed by MVA & ASID
+system.cpu2.dtb.flush_tlb_asid                     30                       # Number of times TLB was flushed by ASID
+system.cpu2.dtb.flush_entries                    2739                       # Number of entries that have been flushed from TLB
+system.cpu2.dtb.align_faults                      445                       # Number of TLB faults due to alignment restrictions
+system.cpu2.dtb.prefetch_faults                   255                       # Number of TLB faults due to prefetch
 system.cpu2.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu2.dtb.perms_faults                      490                       # Number of TLB faults due to permissions restrictions
-system.cpu2.dtb.read_accesses                10969358                       # DTB read accesses
-system.cpu2.dtb.write_accesses                3364994                       # DTB write accesses
+system.cpu2.dtb.perms_faults                      656                       # Number of TLB faults due to permissions restrictions
+system.cpu2.dtb.read_accesses                13954775                       # DTB read accesses
+system.cpu2.dtb.write_accesses                3989089                       # DTB write accesses
 system.cpu2.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu2.dtb.hits                         14304524                       # DTB hits
-system.cpu2.dtb.misses                          29828                       # DTB misses
-system.cpu2.dtb.accesses                     14334352                       # DTB accesses
+system.cpu2.dtb.hits                         17905880                       # DTB hits
+system.cpu2.dtb.misses                          37984                       # DTB misses
+system.cpu2.dtb.accesses                     17943864                       # DTB accesses
 system.cpu2.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu2.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu2.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -1696,329 +1717,329 @@ system.cpu2.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu2.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu2.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu2.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu2.itb.inst_hits                     4066170                       # ITB inst hits
-system.cpu2.itb.inst_misses                      4558                       # ITB inst misses
+system.cpu2.itb.inst_hits                     4053038                       # ITB inst hits
+system.cpu2.itb.inst_misses                      6578                       # ITB inst misses
 system.cpu2.itb.read_hits                           0                       # DTB read hits
 system.cpu2.itb.read_misses                         0                       # DTB read misses
 system.cpu2.itb.write_hits                          0                       # DTB write hits
 system.cpu2.itb.write_misses                        0                       # DTB write misses
-system.cpu2.itb.flush_tlb                         552                       # Number of times complete TLB was flushed
+system.cpu2.itb.flush_tlb                         550                       # Number of times complete TLB was flushed
 system.cpu2.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu2.itb.flush_tlb_mva_asid                530                       # Number of times TLB was flushed by MVA & ASID
-system.cpu2.itb.flush_tlb_asid                     21                       # Number of times TLB was flushed by ASID
-system.cpu2.itb.flush_entries                    1650                       # Number of entries that have been flushed from TLB
+system.cpu2.itb.flush_tlb_mva_asid                695                       # Number of times TLB was flushed by MVA & ASID
+system.cpu2.itb.flush_tlb_asid                     30                       # Number of times TLB was flushed by ASID
+system.cpu2.itb.flush_entries                    2058                       # Number of entries that have been flushed from TLB
 system.cpu2.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu2.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu2.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu2.itb.perms_faults                     1020                       # Number of TLB faults due to permissions restrictions
+system.cpu2.itb.perms_faults                     2441                       # Number of TLB faults due to permissions restrictions
 system.cpu2.itb.read_accesses                       0                       # DTB read accesses
 system.cpu2.itb.write_accesses                      0                       # DTB write accesses
-system.cpu2.itb.inst_accesses                 4070728                       # ITB inst accesses
-system.cpu2.itb.hits                          4066170                       # DTB hits
-system.cpu2.itb.misses                           4558                       # DTB misses
-system.cpu2.itb.accesses                      4070728                       # DTB accesses
-system.cpu2.numCycles                        88357644                       # number of cpu cycles simulated
+system.cpu2.itb.inst_accesses                 4059616                       # ITB inst accesses
+system.cpu2.itb.hits                          4053038                       # DTB hits
+system.cpu2.itb.misses                           6578                       # DTB misses
+system.cpu2.itb.accesses                      4059616                       # DTB accesses
+system.cpu2.numCycles                        88208146                       # number of cpu cycles simulated
 system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu2.fetch.icacheStallCycles           9387256                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu2.fetch.Insts                      32765333                       # Number of instructions fetch has processed
-system.cpu2.fetch.Branches                    4844951                       # Number of branches that fetch encountered
-system.cpu2.fetch.predictedBranches           2977694                       # Number of branches that fetch has predicted taken
-system.cpu2.fetch.Cycles                      6914165                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu2.fetch.SquashCycles                1793026                       # Number of cycles fetch has spent squashing
-system.cpu2.fetch.TlbCycles                     51157                       # Number of cycles fetch has spent waiting for tlb
-system.cpu2.fetch.BlockedCycles              18399919                       # Number of cycles fetch has spent blocked
-system.cpu2.fetch.MiscStallCycles                 356                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu2.fetch.PendingDrainCycles              937                       # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu2.fetch.PendingTrapStallCycles        34522                       # Number of stall cycles due to pending traps
-system.cpu2.fetch.PendingQuiesceStallCycles       732881                       # Number of stall cycles due to pending quiesce instructions
-system.cpu2.fetch.IcacheWaitRetryStallCycles          499                       # Number of stall cycles due to full MSHR
-system.cpu2.fetch.CacheLines                  4064781                       # Number of cache lines fetched
-system.cpu2.fetch.IcacheSquashes               291170                       # Number of outstanding Icache misses that were squashed
-system.cpu2.fetch.ItlbSquashes                   1939                       # Number of outstanding ITLB misses that were squashed
-system.cpu2.fetch.rateDist::samples          36763653                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::mean             1.071353                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::stdev            2.456601                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.icacheStallCycles          10487397                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu2.fetch.Insts                      32911643                       # Number of instructions fetch has processed
+system.cpu2.fetch.Branches                    5844133                       # Number of branches that fetch encountered
+system.cpu2.fetch.predictedBranches           3450657                       # Number of branches that fetch has predicted taken
+system.cpu2.fetch.Cycles                     74966701                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu2.fetch.SquashCycles                 679472                       # Number of cycles fetch has spent squashing
+system.cpu2.fetch.TlbCycles                     80302                       # Number of cycles fetch has spent waiting for tlb
+system.cpu2.fetch.MiscStallCycles                 630                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu2.fetch.PendingDrainCycles              972                       # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu2.fetch.PendingTrapStallCycles        72243                       # Number of stall cycles due to pending traps
+system.cpu2.fetch.PendingQuiesceStallCycles      1263867                       # Number of stall cycles due to pending quiesce instructions
+system.cpu2.fetch.IcacheWaitRetryStallCycles          410                       # Number of stall cycles due to full MSHR
+system.cpu2.fetch.CacheLines                  4050067                       # Number of cache lines fetched
+system.cpu2.fetch.IcacheSquashes               153217                       # Number of outstanding Icache misses that were squashed
+system.cpu2.fetch.ItlbSquashes                   2804                       # Number of outstanding ITLB misses that were squashed
+system.cpu2.fetch.rateDist::samples          87212188                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::mean             0.443226                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::stdev            1.629212                       # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::0                29854695     81.21%     81.21% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::1                  388351      1.06%     82.26% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::2                  517738      1.41%     83.67% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::3                  822514      2.24%     85.91% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::4                  639820      1.74%     87.65% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::5                  344469      0.94%     88.59% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::6                 1061447      2.89%     91.47% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::7                  231777      0.63%     92.10% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::8                 2902842      7.90%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::0                79899565     91.62%     91.62% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::1                  625094      0.72%     92.33% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::2                  698013      0.80%     93.13% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::3                  764181      0.88%     94.01% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::4                  868461      1.00%     95.00% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::5                  574503      0.66%     95.66% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::6                  981504      1.13%     96.79% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::7                  301305      0.35%     97.13% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::8                 2499562      2.87%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::total            36763653                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.branchRate                 0.054833                       # Number of branch fetches per cycle
-system.cpu2.fetch.rate                       0.370826                       # Number of inst fetches per cycle
-system.cpu2.decode.IdleCycles                 9873812                       # Number of cycles decode is idle
-system.cpu2.decode.BlockedCycles             19124591                       # Number of cycles decode is blocked
-system.cpu2.decode.RunCycles                  6319657                       # Number of cycles decode is running
-system.cpu2.decode.UnblockCycles               254865                       # Number of cycles decode is unblocking
-system.cpu2.decode.SquashCycles               1189808                       # Number of cycles decode is squashing
-system.cpu2.decode.BranchResolved              613364                       # Number of times decode resolved a branch
-system.cpu2.decode.BranchMispred                53448                       # Number of times decode detected a branch misprediction
-system.cpu2.decode.DecodedInsts              37275302                       # Number of instructions handled by decode
-system.cpu2.decode.SquashedInsts               179889                       # Number of squashed instructions handled by decode
-system.cpu2.rename.SquashCycles               1189808                       # Number of cycles rename is squashing
-system.cpu2.rename.IdleCycles                10379118                       # Number of cycles rename is idle
-system.cpu2.rename.BlockCycles                2802247                       # Number of cycles rename is blocking
-system.cpu2.rename.serializeStallCycles      11780210                       # count of cycles rename stalled for serializing inst
-system.cpu2.rename.RunCycles                  6098002                       # Number of cycles rename is running
-system.cpu2.rename.UnblockCycles              4513356                       # Number of cycles rename is unblocking
-system.cpu2.rename.RenamedInsts              35160533                       # Number of instructions processed by rename
-system.cpu2.rename.ROBFullEvents                  386                       # Number of times rename has blocked due to ROB full
-system.cpu2.rename.IQFullEvents               2869122                       # Number of times rename has blocked due to IQ full
-system.cpu2.rename.LQFullEvents               3154793                       # Number of times rename has blocked due to LQ full
-system.cpu2.rename.SQFullEvents                689173                       # Number of times rename has blocked due to SQ full
-system.cpu2.rename.FullRegisterEvents             383                       # Number of times there has been no free registers
-system.cpu2.rename.RenamedOperands           37744497                       # Number of destination operands rename has renamed
-system.cpu2.rename.RenameLookups            162187083                       # Number of register rename lookups that rename has made
-system.cpu2.rename.int_rename_lookups       149521715                       # Number of integer rename lookups
-system.cpu2.rename.fp_rename_lookups             3412                       # Number of floating rename lookups
-system.cpu2.rename.CommittedMaps             26544575                       # Number of HB maps that are committed
-system.cpu2.rename.UndoneMaps                11199921                       # Number of HB maps that are undone due to squashing
-system.cpu2.rename.serializingInsts            286052                       # count of serializing insts renamed
-system.cpu2.rename.tempSerializingInsts        262435                       # count of temporary serializing insts renamed
-system.cpu2.rename.skidInsts                  2598030                       # count of insts added to the skid buffer
-system.cpu2.memDep0.insertedLoads             6687505                       # Number of loads inserted to the mem dependence unit.
-system.cpu2.memDep0.insertedStores            3927813                       # Number of stores inserted to the mem dependence unit.
-system.cpu2.memDep0.conflictingLoads           542106                       # Number of conflicting loads.
-system.cpu2.memDep0.conflictingStores          758032                       # Number of conflicting stores.
-system.cpu2.iq.iqInstsAdded                  32441943                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu2.iq.iqNonSpecInstsAdded             511673                       # Number of non-speculative instructions added to the IQ
-system.cpu2.iq.iqInstsIssued                 34839204                       # Number of instructions issued
-system.cpu2.iq.iqSquashedInstsIssued            63540                       # Number of squashed instructions issued
-system.cpu2.iq.iqSquashedInstsExamined        7431415                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu2.iq.iqSquashedOperandsExamined     19915523                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu2.iq.iqSquashedNonSpecRemoved        154345                       # Number of squashed non-spec instructions that were removed
-system.cpu2.iq.issued_per_cycle::samples     36763653                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::mean        0.947653                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::stdev       1.617979                       # Number of insts issued each cycle
+system.cpu2.fetch.rateDist::total            87212188                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.branchRate                 0.066254                       # Number of branch fetches per cycle
+system.cpu2.fetch.rate                       0.373113                       # Number of inst fetches per cycle
+system.cpu2.decode.IdleCycles                 8569138                       # Number of cycles decode is idle
+system.cpu2.decode.BlockedCycles             72587758                       # Number of cycles decode is blocked
+system.cpu2.decode.RunCycles                  4831209                       # Number of cycles decode is running
+system.cpu2.decode.UnblockCycles               941079                       # Number of cycles decode is unblocking
+system.cpu2.decode.SquashCycles                281926                       # Number of cycles decode is squashing
+system.cpu2.decode.BranchResolved              736866                       # Number of times decode resolved a branch
+system.cpu2.decode.BranchMispred                58789                       # Number of times decode detected a branch misprediction
+system.cpu2.decode.DecodedInsts              34844703                       # Number of instructions handled by decode
+system.cpu2.decode.SquashedInsts               196626                       # Number of squashed instructions handled by decode
+system.cpu2.rename.SquashCycles                281926                       # Number of cycles rename is squashing
+system.cpu2.rename.IdleCycles                 9031224                       # Number of cycles rename is idle
+system.cpu2.rename.BlockCycles               19204705                       # Number of cycles rename is blocking
+system.cpu2.rename.serializeStallCycles      13140033                       # count of cycles rename stalled for serializing inst
+system.cpu2.rename.RunCycles                  5253439                       # Number of cycles rename is running
+system.cpu2.rename.UnblockCycles             40299841                       # Number of cycles rename is unblocking
+system.cpu2.rename.RenamedInsts              33794581                       # Number of instructions processed by rename
+system.cpu2.rename.ROBFullEvents                74120                       # Number of times rename has blocked due to ROB full
+system.cpu2.rename.IQFullEvents              29618551                       # Number of times rename has blocked due to IQ full
+system.cpu2.rename.LQFullEvents              37683898                       # Number of times rename has blocked due to LQ full
+system.cpu2.rename.SQFullEvents               1100267                       # Number of times rename has blocked due to SQ full
+system.cpu2.rename.RenamedOperands           36626919                       # Number of destination operands rename has renamed
+system.cpu2.rename.RenameLookups            154339316                       # Number of register rename lookups that rename has made
+system.cpu2.rename.int_rename_lookups        41664821                       # Number of integer rename lookups
+system.cpu2.rename.fp_rename_lookups             4127                       # Number of floating rename lookups
+system.cpu2.rename.CommittedMaps             28795876                       # Number of HB maps that are committed
+system.cpu2.rename.UndoneMaps                 7831027                       # Number of HB maps that are undone due to squashing
+system.cpu2.rename.serializingInsts            344066                       # count of serializing insts renamed
+system.cpu2.rename.tempSerializingInsts        286541                       # count of temporary serializing insts renamed
+system.cpu2.rename.skidInsts                  5082070                       # count of insts added to the skid buffer
+system.cpu2.memDep0.insertedLoads             6089915                       # Number of loads inserted to the mem dependence unit.
+system.cpu2.memDep0.insertedStores            4400227                       # Number of stores inserted to the mem dependence unit.
+system.cpu2.memDep0.conflictingLoads           719431                       # Number of conflicting loads.
+system.cpu2.memDep0.conflictingStores         1142118                       # Number of conflicting stores.
+system.cpu2.iq.iqInstsAdded                  32029170                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu2.iq.iqNonSpecInstsAdded             669683                       # Number of non-speculative instructions added to the IQ
+system.cpu2.iq.iqInstsIssued                 38616590                       # Number of instructions issued
+system.cpu2.iq.iqSquashedInstsIssued            44993                       # Number of squashed instructions issued
+system.cpu2.iq.iqSquashedInstsExamined        5567256                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu2.iq.iqSquashedOperandsExamined     12099893                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu2.iq.iqSquashedNonSpecRemoved        238978                       # Number of squashed non-spec instructions that were removed
+system.cpu2.iq.issued_per_cycle::samples     87212188                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::mean        0.442789                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::stdev       1.239118                       # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::0           24294475     66.08%     66.08% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::1            3786923     10.30%     76.38% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::2            2217252      6.03%     82.41% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::3            1918473      5.22%     87.63% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::4            2844306      7.74%     95.37% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::5             967223      2.63%     98.00% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::6             535277      1.46%     99.46% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::7             160435      0.44%     99.89% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::8              39289      0.11%    100.00% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::0           73763195     84.58%     84.58% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::1            4095516      4.70%     89.28% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::2            2328743      2.67%     91.95% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::3            2051674      2.35%     94.30% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::4            2976748      3.41%     97.71% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::5             798764      0.92%     98.63% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::6             739781      0.85%     99.48% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::7             293068      0.34%     99.81% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::8             164699      0.19%    100.00% # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::total       36763653                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::total       87212188                       # Number of insts issued each cycle
 system.cpu2.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntAlu                  19487      1.25%      1.25% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntMult                     1      0.00%      1.25% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntDiv                      0      0.00%      1.25% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatAdd                    0      0.00%      1.25% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCmp                    0      0.00%      1.25% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCvt                    0      0.00%      1.25% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatMult                   0      0.00%      1.25% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatDiv                    0      0.00%      1.25% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%      1.25% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAdd                     0      0.00%      1.25% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%      1.25% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAlu                     0      0.00%      1.25% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCmp                     0      0.00%      1.25% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCvt                     0      0.00%      1.25% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMisc                    0      0.00%      1.25% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMult                    0      0.00%      1.25% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%      1.25% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShift                   0      0.00%      1.25% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%      1.25% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%      1.25% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%      1.25% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%      1.25% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%      1.25% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%      1.25% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%      1.25% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%      1.25% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%      1.25% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%      1.25% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%      1.25% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemRead               1415927     90.74%     91.99% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemWrite               124952      8.01%    100.00% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntAlu                 122993      5.40%      5.40% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntMult                     1      0.00%      5.40% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntDiv                      0      0.00%      5.40% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatAdd                    0      0.00%      5.40% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCmp                    0      0.00%      5.40% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCvt                    0      0.00%      5.40% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatMult                   0      0.00%      5.40% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatDiv                    0      0.00%      5.40% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%      5.40% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAdd                     0      0.00%      5.40% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%      5.40% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAlu                     0      0.00%      5.40% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCmp                     0      0.00%      5.40% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCvt                     0      0.00%      5.40% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMisc                    0      0.00%      5.40% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMult                    0      0.00%      5.40% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%      5.40% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShift                   0      0.00%      5.40% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%      5.40% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%      5.40% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%      5.40% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%      5.40% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%      5.40% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%      5.40% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%      5.40% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%      5.40% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%      5.40% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%      5.40% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%      5.40% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemRead               1970586     86.46%     91.85% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemWrite               185678      8.15%    100.00% # attempts to use FU when none available
 system.cpu2.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu2.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu2.iq.FU_type_0::No_OpClass             8595      0.02%      0.02% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntAlu             19842102     56.95%     56.98% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntMult               28105      0.08%     57.06% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntDiv                    0      0.00%     57.06% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatAdd                  0      0.00%     57.06% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     57.06% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCvt                  0      0.00%     57.06% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     57.06% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatDiv                  0      0.00%     57.06% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     57.06% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     57.06% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     57.06% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     57.06% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     57.06% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     57.06% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMisc                 10      0.00%     57.06% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     57.06% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     57.06% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     57.06% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShiftAcc             10      0.00%     57.06% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     57.06% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     57.06% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     57.06% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     57.06% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     57.06% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     57.06% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMisc           382      0.00%     57.06% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     57.06% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMultAcc           10      0.00%     57.06% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     57.06% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemRead            11432468     32.81%     89.87% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemWrite            3527522     10.13%    100.00% # Type of FU issued
+system.cpu2.iq.FU_type_0::No_OpClass            12081      0.03%      0.03% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntAlu             20207276     52.33%     52.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntMult               34218      0.09%     52.45% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntDiv                    0      0.00%     52.45% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatAdd                  0      0.00%     52.45% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     52.45% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCvt                  0      0.00%     52.45% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     52.45% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatDiv                  0      0.00%     52.45% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     52.45% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     52.45% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     52.45% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     52.45% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     52.45% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     52.45% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMisc                  0      0.00%     52.45% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     52.45% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     52.45% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     52.45% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     52.45% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     52.45% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     52.45% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     52.45% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     52.45% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     52.45% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     52.45% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMisc           404      0.00%     52.45% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     52.45% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     52.45% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     52.45% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemRead            14176555     36.71%     89.16% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemWrite            4186056     10.84%    100.00% # Type of FU issued
 system.cpu2.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu2.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::total              34839204                       # Type of FU issued
-system.cpu2.iq.rate                          0.394298                       # Inst issue rate
-system.cpu2.iq.fu_busy_cnt                    1560367                       # FU busy when requested
-system.cpu2.iq.fu_busy_rate                  0.044788                       # FU busy rate (busy events/executed inst)
-system.cpu2.iq.int_inst_queue_reads         108088247                       # Number of integer instruction queue reads
-system.cpu2.iq.int_inst_queue_writes         40390587                       # Number of integer instruction queue writes
-system.cpu2.iq.int_inst_queue_wakeup_accesses     28132113                       # Number of integer instruction queue wakeup accesses
-system.cpu2.iq.fp_inst_queue_reads               7428                       # Number of floating instruction queue reads
-system.cpu2.iq.fp_inst_queue_writes              3949                       # Number of floating instruction queue writes
-system.cpu2.iq.fp_inst_queue_wakeup_accesses         3288                       # Number of floating instruction queue wakeup accesses
-system.cpu2.iq.int_alu_accesses              36387010                       # Number of integer alu accesses
-system.cpu2.iq.fp_alu_accesses                   3966                       # Number of floating point alu accesses
-system.cpu2.iew.lsq.thread0.forwLoads          216264                       # Number of loads that had data forwarded from stores
+system.cpu2.iq.FU_type_0::total              38616590                       # Type of FU issued
+system.cpu2.iq.rate                          0.437789                       # Inst issue rate
+system.cpu2.iq.fu_busy_cnt                    2279258                       # FU busy when requested
+system.cpu2.iq.fu_busy_rate                  0.059023                       # FU busy rate (busy events/executed inst)
+system.cpu2.iq.int_inst_queue_reads         166760031                       # Number of integer instruction queue reads
+system.cpu2.iq.int_inst_queue_writes         38278238                       # Number of integer instruction queue writes
+system.cpu2.iq.int_inst_queue_wakeup_accesses     29588244                       # Number of integer instruction queue wakeup accesses
+system.cpu2.iq.fp_inst_queue_reads               9588                       # Number of floating instruction queue reads
+system.cpu2.iq.fp_inst_queue_writes              5150                       # Number of floating instruction queue writes
+system.cpu2.iq.fp_inst_queue_wakeup_accesses         4304                       # Number of floating instruction queue wakeup accesses
+system.cpu2.iq.int_alu_accesses              40878658                       # Number of integer alu accesses
+system.cpu2.iq.fp_alu_accesses                   5109                       # Number of floating point alu accesses
+system.cpu2.iew.lsq.thread0.forwLoads          176007                       # Number of loads that had data forwarded from stores
 system.cpu2.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu2.iew.lsq.thread0.squashedLoads      1592400                       # Number of loads squashed
-system.cpu2.iew.lsq.thread0.ignoredResponses         1668                       # Number of memory responses ignored because the instruction is squashed
-system.cpu2.iew.lsq.thread0.memOrderViolation         9845                       # Number of memory ordering violations
-system.cpu2.iew.lsq.thread0.squashedStores       582754                       # Number of stores squashed
+system.cpu2.iew.lsq.thread0.squashedLoads      1107424                       # Number of loads squashed
+system.cpu2.iew.lsq.thread0.ignoredResponses         2018                       # Number of memory responses ignored because the instruction is squashed
+system.cpu2.iew.lsq.thread0.memOrderViolation        18033                       # Number of memory ordering violations
+system.cpu2.iew.lsq.thread0.squashedStores       469449                       # Number of stores squashed
 system.cpu2.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu2.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu2.iew.lsq.thread0.rescheduledLoads      5289504                       # Number of loads that were rescheduled
-system.cpu2.iew.lsq.thread0.cacheBlocked       343573                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu2.iew.lsq.thread0.rescheduledLoads      5207867                       # Number of loads that were rescheduled
+system.cpu2.iew.lsq.thread0.cacheBlocked      3518142                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu2.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu2.iew.iewSquashCycles               1189808                       # Number of cycles IEW is squashing
-system.cpu2.iew.iewBlockCycles                2192287                       # Number of cycles IEW is blocking
-system.cpu2.iew.iewUnblockCycles               292580                       # Number of cycles IEW is unblocking
-system.cpu2.iew.iewDispatchedInsts           33037931                       # Number of instructions dispatched to IQ
-system.cpu2.iew.iewDispSquashedInsts            55534                       # Number of squashed instructions skipped by dispatch
-system.cpu2.iew.iewDispLoadInsts              6687505                       # Number of dispatched load instructions
-system.cpu2.iew.iewDispStoreInsts             3927813                       # Number of dispatched store instructions
-system.cpu2.iew.iewDispNonSpecInsts            368987                       # Number of dispatched non-speculative instructions
-system.cpu2.iew.iewIQFullEvents                 60475                       # Number of times the IQ has become full, causing a stall
-system.cpu2.iew.iewLSQFullEvents               207427                       # Number of times the LSQ has become full, causing a stall
-system.cpu2.iew.memOrderViolationEvents          9845                       # Number of memory order violations
-system.cpu2.iew.predictedTakenIncorrect        107337                       # Number of branches that were predicted taken incorrectly
-system.cpu2.iew.predictedNotTakenIncorrect        89487                       # Number of branches that were predicted not taken incorrectly
-system.cpu2.iew.branchMispredicts              196824                       # Number of branch mispredicts detected at execute
-system.cpu2.iew.iewExecutedInsts             33922204                       # Number of executed instructions
-system.cpu2.iew.iewExecLoadInsts             11159492                       # Number of load instructions executed
-system.cpu2.iew.iewExecSquashedInsts           917000                       # Number of squashed instructions skipped in execute
+system.cpu2.iew.iewSquashCycles                281926                       # Number of cycles IEW is squashing
+system.cpu2.iew.iewBlockCycles               17856855                       # Number of cycles IEW is blocking
+system.cpu2.iew.iewUnblockCycles               716566                       # Number of cycles IEW is unblocking
+system.cpu2.iew.iewDispatchedInsts           32817404                       # Number of instructions dispatched to IQ
+system.cpu2.iew.iewDispSquashedInsts            57776                       # Number of squashed instructions skipped by dispatch
+system.cpu2.iew.iewDispLoadInsts              6089915                       # Number of dispatched load instructions
+system.cpu2.iew.iewDispStoreInsts             4400227                       # Number of dispatched store instructions
+system.cpu2.iew.iewDispNonSpecInsts            491578                       # Number of dispatched non-speculative instructions
+system.cpu2.iew.iewIQFullEvents                 63121                       # Number of times the IQ has become full, causing a stall
+system.cpu2.iew.iewLSQFullEvents               616282                       # Number of times the LSQ has become full, causing a stall
+system.cpu2.iew.memOrderViolationEvents         18033                       # Number of memory order violations
+system.cpu2.iew.predictedTakenIncorrect        121106                       # Number of branches that were predicted taken incorrectly
+system.cpu2.iew.predictedNotTakenIncorrect       106258                       # Number of branches that were predicted not taken incorrectly
+system.cpu2.iew.branchMispredicts              227364                       # Number of branch mispredicts detected at execute
+system.cpu2.iew.iewExecutedInsts             38297957                       # Number of executed instructions
+system.cpu2.iew.iewExecLoadInsts             14051286                       # Number of load instructions executed
+system.cpu2.iew.iewExecSquashedInsts           280797                       # Number of squashed instructions skipped in execute
 system.cpu2.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu2.iew.exec_nop                        84315                       # number of nop insts executed
-system.cpu2.iew.exec_refs                    14652861                       # number of memory reference insts executed
-system.cpu2.iew.exec_branches                 3774133                       # Number of branches executed
-system.cpu2.iew.exec_stores                   3493369                       # Number of stores executed
-system.cpu2.iew.exec_rate                    0.383919                       # Inst execution rate
-system.cpu2.iew.wb_sent                      33519345                       # cumulative count of insts sent to commit
-system.cpu2.iew.wb_count                     28135401                       # cumulative count of insts written-back
-system.cpu2.iew.wb_producers                 16326972                       # num instructions producing a value
-system.cpu2.iew.wb_consumers                 29693548                       # num instructions consuming a value
+system.cpu2.iew.exec_nop                       118551                       # number of nop insts executed
+system.cpu2.iew.exec_refs                    18186993                       # number of memory reference insts executed
+system.cpu2.iew.exec_branches                 4220297                       # Number of branches executed
+system.cpu2.iew.exec_stores                   4135707                       # Number of stores executed
+system.cpu2.iew.exec_rate                    0.434177                       # Inst execution rate
+system.cpu2.iew.wb_sent                      34852514                       # cumulative count of insts sent to commit
+system.cpu2.iew.wb_count                     29592548                       # cumulative count of insts written-back
+system.cpu2.iew.wb_producers                 17266310                       # num instructions producing a value
+system.cpu2.iew.wb_consumers                 30698955                       # num instructions consuming a value
 system.cpu2.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu2.iew.wb_rate                      0.318426                       # insts written-back per cycle
-system.cpu2.iew.wb_fanout                    0.549849                       # average fanout of values written-back
+system.cpu2.iew.wb_rate                      0.335485                       # insts written-back per cycle
+system.cpu2.iew.wb_fanout                    0.562440                       # average fanout of values written-back
 system.cpu2.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu2.commit.commitSquashedInsts        7376982                       # The number of squashed insts skipped by commit
-system.cpu2.commit.commitNonSpecStalls         357328                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu2.commit.branchMispredicts           170683                       # The number of times a branch was mispredicted
-system.cpu2.commit.committed_per_cycle::samples     35573653                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::mean     0.713892                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::stdev     1.756913                       # Number of insts commited each cycle
+system.cpu2.commit.commitSquashedInsts        5479640                       # The number of squashed insts skipped by commit
+system.cpu2.commit.commitNonSpecStalls         430705                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu2.commit.branchMispredicts           190919                       # The number of times a branch was mispredicted
+system.cpu2.commit.committed_per_cycle::samples     86342246                       # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::mean     0.312843                       # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::stdev     1.237203                       # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::0     26733174     75.15%     75.15% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::1      4358118     12.25%     87.40% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::2      1232607      3.46%     90.86% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::3       662996      1.86%     92.73% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::4       505200      1.42%     94.15% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::5       312825      0.88%     95.03% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::6       424269      1.19%     96.22% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::7       302810      0.85%     97.07% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::8      1041654      2.93%    100.00% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::0     77364915     89.60%     89.60% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::1      4177735      4.84%     94.44% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::2      1290086      1.49%     95.94% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::3       753837      0.87%     96.81% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::4       490440      0.57%     97.38% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::5       381562      0.44%     97.82% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::6       374801      0.43%     98.25% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::7       197147      0.23%     98.48% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::8      1311723      1.52%    100.00% # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::total     35573653                       # Number of insts commited each cycle
-system.cpu2.commit.committedInsts            20550287                       # Number of instructions committed
-system.cpu2.commit.committedOps              25395761                       # Number of ops (including micro ops) committed
+system.cpu2.commit.committed_per_cycle::total     86342246                       # Number of insts commited each cycle
+system.cpu2.commit.committedInsts            22875674                       # Number of instructions committed
+system.cpu2.commit.committedOps              27011607                       # Number of ops (including micro ops) committed
 system.cpu2.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu2.commit.refs                       8440164                       # Number of memory references committed
-system.cpu2.commit.loads                      5095105                       # Number of loads committed
-system.cpu2.commit.membars                      94591                       # Number of memory barriers committed
-system.cpu2.commit.branches                   3237542                       # Number of branches committed
-system.cpu2.commit.fp_insts                      3235                       # Number of committed floating point instructions.
-system.cpu2.commit.int_insts                 22655353                       # Number of committed integer instructions.
-system.cpu2.commit.function_calls              295831                       # Number of function calls committed.
+system.cpu2.commit.refs                       8913269                       # Number of memory references committed
+system.cpu2.commit.loads                      4982491                       # Number of loads committed
+system.cpu2.commit.membars                     117220                       # Number of memory barriers committed
+system.cpu2.commit.branches                   3644555                       # Number of branches committed
+system.cpu2.commit.fp_insts                      4270                       # Number of committed floating point instructions.
+system.cpu2.commit.int_insts                 23908542                       # Number of committed integer instructions.
+system.cpu2.commit.function_calls              341319                       # Number of function calls committed.
 system.cpu2.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntAlu        16928638     66.66%     66.66% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntMult          26577      0.10%     66.76% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntDiv               0      0.00%     66.76% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatAdd             0      0.00%     66.76% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatCmp             0      0.00%     66.76% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatCvt             0      0.00%     66.76% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatMult            0      0.00%     66.76% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatDiv             0      0.00%     66.76% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatSqrt            0      0.00%     66.76% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAdd              0      0.00%     66.76% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAddAcc            0      0.00%     66.76% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAlu              0      0.00%     66.76% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdCmp              0      0.00%     66.76% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdCvt              0      0.00%     66.76% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMisc             0      0.00%     66.76% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMult             0      0.00%     66.76% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMultAcc            0      0.00%     66.76% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdShift            0      0.00%     66.76% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdShiftAcc            0      0.00%     66.76% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdSqrt             0      0.00%     66.76% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatAdd            0      0.00%     66.76% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatAlu            0      0.00%     66.76% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatCmp            0      0.00%     66.76% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatCvt            0      0.00%     66.76% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatDiv            0      0.00%     66.76% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMisc          382      0.00%     66.77% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMult            0      0.00%     66.77% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMultAcc            0      0.00%     66.77% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatSqrt            0      0.00%     66.77% # Class of committed instruction
-system.cpu2.commit.op_class_0::MemRead        5095105     20.06%     86.83% # Class of committed instruction
-system.cpu2.commit.op_class_0::MemWrite       3345059     13.17%    100.00% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntAlu        18065773     66.88%     66.88% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntMult          32161      0.12%     67.00% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntDiv               0      0.00%     67.00% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatAdd             0      0.00%     67.00% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatCmp             0      0.00%     67.00% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatCvt             0      0.00%     67.00% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatMult            0      0.00%     67.00% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatDiv             0      0.00%     67.00% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatSqrt            0      0.00%     67.00% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAdd              0      0.00%     67.00% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAddAcc            0      0.00%     67.00% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAlu              0      0.00%     67.00% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdCmp              0      0.00%     67.00% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdCvt              0      0.00%     67.00% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMisc             0      0.00%     67.00% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMult             0      0.00%     67.00% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMultAcc            0      0.00%     67.00% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdShift            0      0.00%     67.00% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdShiftAcc            0      0.00%     67.00% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdSqrt             0      0.00%     67.00% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatAdd            0      0.00%     67.00% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatAlu            0      0.00%     67.00% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatCmp            0      0.00%     67.00% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatCvt            0      0.00%     67.00% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatDiv            0      0.00%     67.00% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMisc          404      0.00%     67.00% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMult            0      0.00%     67.00% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMultAcc            0      0.00%     67.00% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatSqrt            0      0.00%     67.00% # Class of committed instruction
+system.cpu2.commit.op_class_0::MemRead        4982491     18.45%     85.45% # Class of committed instruction
+system.cpu2.commit.op_class_0::MemWrite       3930778     14.55%    100.00% # Class of committed instruction
 system.cpu2.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu2.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu2.commit.op_class_0::total         25395761                       # Class of committed instruction
-system.cpu2.commit.bw_lim_events              1041654                       # number cycles where commit BW limit reached
+system.cpu2.commit.op_class_0::total         27011607                       # Class of committed instruction
+system.cpu2.commit.bw_lim_events              1311723                       # number cycles where commit BW limit reached
 system.cpu2.commit.bw_limited                       0                       # number of insts not committed due to BW limits
-system.cpu2.rob.rob_reads                    66778885                       # The number of ROB reads
-system.cpu2.rob.rob_writes                   66779605                       # The number of ROB writes
-system.cpu2.timesIdled                         362907                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu2.idleCycles                       51593991                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu2.quiesceCycles                  3545947336                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu2.committedInsts                   20495032                       # Number of Instructions Simulated
-system.cpu2.committedOps                     25340506                       # Number of Ops (including micro ops) Simulated
-system.cpu2.cpi                              4.311174                       # CPI: Cycles Per Instruction
-system.cpu2.cpi_total                        4.311174                       # CPI: Total CPI of All Threads
-system.cpu2.ipc                              0.231955                       # IPC: Instructions Per Cycle
-system.cpu2.ipc_total                        0.231955                       # IPC: Total IPC of All Threads
-system.cpu2.int_regfile_reads               157422880                       # number of integer regfile reads
-system.cpu2.int_regfile_writes               29963931                       # number of integer regfile writes
-system.cpu2.fp_regfile_reads                    46839                       # number of floating regfile reads
-system.cpu2.fp_regfile_writes                   45210                       # number of floating regfile writes
-system.cpu2.misc_regfile_reads               66597785                       # number of misc regfile reads
-system.cpu2.misc_regfile_writes                297300                       # number of misc regfile writes
+system.cpu2.rob.rob_reads                   116854146                       # The number of ROB reads
+system.cpu2.rob.rob_writes                   65855440                       # The number of ROB writes
+system.cpu2.timesIdled                         179134                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu2.idleCycles                         995958                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu2.quiesceCycles                  3544369510                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu2.committedInsts                   22801865                       # Number of Instructions Simulated
+system.cpu2.committedOps                     26937798                       # Number of Ops (including micro ops) Simulated
+system.cpu2.cpi                              3.868462                       # CPI: Cycles Per Instruction
+system.cpu2.cpi_total                        3.868462                       # CPI: Total CPI of All Threads
+system.cpu2.ipc                              0.258501                       # IPC: Instructions Per Cycle
+system.cpu2.ipc_total                        0.258501                       # IPC: Total IPC of All Threads
+system.cpu2.int_regfile_reads                45014030                       # number of integer regfile reads
+system.cpu2.int_regfile_writes               19144459                       # number of integer regfile writes
+system.cpu2.fp_regfile_reads                    47113                       # number of floating regfile reads
+system.cpu2.fp_regfile_writes                   45464                       # number of floating regfile writes
+system.cpu2.cc_regfile_reads                130800569                       # number of cc regfile reads
+system.cpu2.cc_regfile_writes                12559359                       # number of cc regfile writes
+system.cpu2.misc_regfile_reads              124603397                       # number of misc regfile reads
+system.cpu2.misc_regfile_writes                350092                       # number of misc regfile writes
 system.iocache.tags.replacements                    0                       # number of replacements
 system.iocache.tags.tagsinuse                       0                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
@@ -2035,10 +2056,10 @@ system.iocache.avg_blocked_cycles::no_mshrs          nan                       #
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1536043103750                       # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1536043103750                       # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1536043103750                       # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1536043103750                       # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1536004079250                       # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1536004079250                       # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1536004079250                       # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1536004079250                       # number of overall MSHR uncacheable cycles
 system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average ReadReq mshr uncacheable latency
 system.iocache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average overall mshr uncacheable latency
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt
index 4b7f3d43e..055919fe9 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt
@@ -1,154 +1,154 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.550237                       # Number of seconds simulated
-sim_ticks                                2550237191000                       # Number of ticks simulated
-final_tick                               2550237191000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.539697                       # Number of seconds simulated
+sim_ticks                                2539696838000                       # Number of ticks simulated
+final_tick                               2539696838000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  66377                       # Simulator instruction rate (inst/s)
-host_op_rate                                    85409                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2806608319                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 421988                       # Number of bytes of host memory used
-host_seconds                                   908.65                       # Real time elapsed on the host
-sim_insts                                    60314055                       # Number of instructions simulated
-sim_ops                                      77607027                       # Number of ops (including micro ops) simulated
+host_inst_rate                                  33216                       # Simulator instruction rate (inst/s)
+host_op_rate                                    40018                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1398403355                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 411672                       # Number of bytes of host memory used
+host_seconds                                  1816.14                       # Real time elapsed on the host
+sim_insts                                    60325607                       # Number of instructions simulated
+sim_ops                                      72677421                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::realview.clcd    121110528                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.dtb.walker         2240                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.dtb.walker          896                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.itb.walker           64                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst           507520                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data          5298200                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker          704                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           292352                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data          3795584                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            131007192                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       507520                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       292352                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          799872                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      3786240                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0.data       1521400                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1.data       1494672                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           6802312                       # Number of bytes written to this memory
+system.physmem.bytes_read::cpu0.inst           469568                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data          3933400                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker          640                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           314240                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data          5155776                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            130985112                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       469568                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       314240                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          783808                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      3774400                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0.data       1328880                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1.data       1687192                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           6790472                       # Number of bytes written to this memory
 system.physmem.num_reads::realview.clcd      15138816                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.dtb.walker           35                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.dtb.walker           14                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu0.itb.walker            1                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst              7930                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data             82820                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker           11                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              4568                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data             59306                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total              15293487                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           59160                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0.data           380350                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1.data           373668                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               813178                       # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd        47489907                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.dtb.walker           878                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_reads::cpu0.inst              7337                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data             61485                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker           10                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst              4910                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data             80559                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total              15293132                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           58975                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0.data           332220                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu1.data           421798                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               812993                       # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd        47687002                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.dtb.walker           353                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu0.itb.walker            25                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst              199009                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data             2077532                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker           276                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst              114637                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data             1488326                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                51370591                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         199009                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst         114637                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             313646                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1484662                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data             596572                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data             586091                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2667325                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1484662                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd       47489907                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker          878                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst              184891                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data             1548768                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker           252                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst              123731                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data             2030075                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                51575097                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         184891                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst         123731                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             308623                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1486162                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data             523244                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1.data             664328                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                2673733                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1486162                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd       47687002                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker          353                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.itb.walker           25                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             199009                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data            2674104                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker          276                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst             114637                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data            2074417                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               54037916                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                      15293487                       # Number of read requests accepted
-system.physmem.writeReqs                       813178                       # Number of write requests accepted
-system.physmem.readBursts                    15293487                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     813178                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                977052352                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                   1730816                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   6829312                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                 131007192                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                6802312                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                    27044                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                  706441                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs           4687                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0              955866                       # Per bank write bursts
-system.physmem.perBankRdBursts::1              953274                       # Per bank write bursts
-system.physmem.perBankRdBursts::2              953247                       # Per bank write bursts
-system.physmem.perBankRdBursts::3              953514                       # Per bank write bursts
-system.physmem.perBankRdBursts::4              955750                       # Per bank write bursts
-system.physmem.perBankRdBursts::5              953800                       # Per bank write bursts
-system.physmem.perBankRdBursts::6              953588                       # Per bank write bursts
-system.physmem.perBankRdBursts::7              953504                       # Per bank write bursts
-system.physmem.perBankRdBursts::8              956261                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              953859                       # Per bank write bursts
-system.physmem.perBankRdBursts::10             953506                       # Per bank write bursts
-system.physmem.perBankRdBursts::11             952990                       # Per bank write bursts
-system.physmem.perBankRdBursts::12             956201                       # Per bank write bursts
-system.physmem.perBankRdBursts::13             953861                       # Per bank write bursts
-system.physmem.perBankRdBursts::14             953718                       # Per bank write bursts
-system.physmem.perBankRdBursts::15             953504                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                6593                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                6395                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                6535                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                6562                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                6485                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                6754                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                6752                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                6692                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                7013                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                6813                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               6467                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               6119                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               7057                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               6685                       # Per bank write bursts
+system.physmem.bw_total::cpu0.inst             184891                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data            2072011                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker          252                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst             123731                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data            2694403                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               54248831                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                      15293132                       # Number of read requests accepted
+system.physmem.writeReqs                       812993                       # Number of write requests accepted
+system.physmem.readBursts                    15293132                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     812993                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                975241856                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                   3518592                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   6826496                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                 130985112                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                6790472                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                    54978                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                  706304                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs           4635                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0              954958                       # Per bank write bursts
+system.physmem.perBankRdBursts::1              950647                       # Per bank write bursts
+system.physmem.perBankRdBursts::2              950811                       # Per bank write bursts
+system.physmem.perBankRdBursts::3              950999                       # Per bank write bursts
+system.physmem.perBankRdBursts::4              954856                       # Per bank write bursts
+system.physmem.perBankRdBursts::5              951881                       # Per bank write bursts
+system.physmem.perBankRdBursts::6              951736                       # Per bank write bursts
+system.physmem.perBankRdBursts::7              951699                       # Per bank write bursts
+system.physmem.perBankRdBursts::8              955454                       # Per bank write bursts
+system.physmem.perBankRdBursts::9              951840                       # Per bank write bursts
+system.physmem.perBankRdBursts::10             951452                       # Per bank write bursts
+system.physmem.perBankRdBursts::11             951010                       # Per bank write bursts
+system.physmem.perBankRdBursts::12             955349                       # Per bank write bursts
+system.physmem.perBankRdBursts::13             951888                       # Per bank write bursts
+system.physmem.perBankRdBursts::14             952124                       # Per bank write bursts
+system.physmem.perBankRdBursts::15             951450                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                6588                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                6390                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                6534                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                6563                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                6471                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                6764                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                6747                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                6681                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                6996                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                6810                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               6454                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               6114                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               7081                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               6669                       # Per bank write bursts
 system.physmem.perBankWrBursts::14               6965                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               6821                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               6837                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    2550236004000                       # Total gap between requests
+system.physmem.totGap                    2539695718000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::2                      38                       # Read request sizes (log2)
-system.physmem.readPktSize::3                15138816                       # Read request sizes (log2)
+system.physmem.readPktSize::2                      18                       # Read request sizes (log2)
+system.physmem.readPktSize::3                15138826                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  154633                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  154288                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                 754018                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                  59160                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                   1068642                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                   1003556                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                    964678                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                   1068028                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                    971433                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                   1034228                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                   2693278                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                   2602966                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                   3400925                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                    112135                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                   102170                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                    95874                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                    92374                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                    19109                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                    18588                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                    18396                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                       38                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                       14                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                        8                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                        3                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                  58975                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                   1062531                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                   1005454                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                    961588                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                   1062790                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                    969024                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                   1031345                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                   2691523                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                   2602840                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                   3403260                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                    108695                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                    99295                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                    93778                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                    90278                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                    18929                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                    18461                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                    18290                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                       57                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                       13                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                        3                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
@@ -161,43 +161,43 @@ system.physmem.rdQLenPdf::28                        0                       # Wh
 system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                       298                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1                       293                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                       288                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                       286                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                       283                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                       282                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                       279                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                       278                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                       274                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0                       292                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1                       289                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2                       287                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3                       282                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4                       278                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5                       276                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6                       274                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7                       273                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8                       272                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::9                       269                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::10                      267                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                      265                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12                      264                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11                      264                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12                      265                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                      263                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                      260                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     3279                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     3544                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     4723                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     6033                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     6237                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     6102                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     6064                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     6482                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     6060                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     6076                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     6103                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     5934                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     5931                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     6266                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     5878                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     5861                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     5998                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     5786                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      113                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                       83                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                       31                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                        4                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14                      261                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     3218                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     3706                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     4802                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     6037                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     6146                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     6104                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     6080                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     6091                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     6085                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     6239                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     6283                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     5902                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     5897                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     6338                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     5876                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     5895                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     6007                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     5773                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                       58                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                       25                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                       13                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                        2                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
@@ -225,96 +225,96 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples      1011151                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      973.031391                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     908.214038                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     201.586844                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          22832      2.26%      2.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        19987      1.98%      4.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         8899      0.88%      5.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         2276      0.23%      5.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2117      0.21%      5.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1805      0.18%      5.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         9141      0.90%      6.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          764      0.08%      6.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151       943330     93.29%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total        1011151                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          6075                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean      2512.992263                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev    47101.457482                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-65535          6047     99.54%     99.54% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::65536-131071            1      0.02%     99.56% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::131072-196607            8      0.13%     99.69% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::196608-262143            7      0.12%     99.80% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples      1008721                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      973.577780                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     909.477346                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     200.561203                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          22290      2.21%      2.21% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        20048      1.99%      4.20% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         8821      0.87%      5.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         2154      0.21%      5.29% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2027      0.20%      5.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1663      0.16%      5.65% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         9185      0.91%      6.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          821      0.08%      6.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151       941712     93.36%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total        1008721                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          6071                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean      2509.988470                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev    47472.970867                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-65535          6043     99.54%     99.54% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::65536-131071            3      0.05%     99.59% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::131072-196607            8      0.13%     99.72% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::196608-262143            5      0.08%     99.80% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::393216-458751            1      0.02%     99.82% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::589824-655359            2      0.03%     99.85% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::589824-655359            1      0.02%     99.84% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::786432-851967            1      0.02%     99.85% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::983040-1.04858e+06            2      0.03%     99.88% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::1.17965e+06-1.24518e+06            6      0.10%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::1.37626e+06-1.44179e+06            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            6075                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          6075                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        17.565103                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       17.376946                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        2.337614                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::1                   6      0.10%      0.10% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::2                   5      0.08%      0.18% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::3                   2      0.03%      0.21% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::4                   4      0.07%      0.28% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::5                   2      0.03%      0.31% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::6                   2      0.03%      0.35% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::7                   2      0.03%      0.38% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::8                   4      0.07%      0.44% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::9                   5      0.08%      0.53% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::10                  2      0.03%      0.56% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::11                  3      0.05%      0.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::12                  3      0.05%      0.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::13                  1      0.02%      0.67% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::14                  4      0.07%      0.74% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::15                 11      0.18%      0.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16               2721     44.79%     45.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17                 38      0.63%     46.34% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18               1583     26.06%     72.40% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19               1297     21.35%     93.74% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                 91      1.50%     95.24% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21                 44      0.72%     95.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22                 54      0.89%     96.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23                 48      0.79%     97.65% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24                 29      0.48%     98.12% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::25                 18      0.30%     98.42% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26                 20      0.33%     98.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::27                 17      0.28%     99.03% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28                 13      0.21%     99.24% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::29                 16      0.26%     99.51% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::30                 12      0.20%     99.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::31                 10      0.16%     99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32                  8      0.13%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            6075                       # Writes before turning the bus around for reads
-system.physmem.totQLat                   393209260500                       # Total ticks spent queuing
-system.physmem.totMemAccLat              679455066750                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                  76332215000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       25756.44                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            6071                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          6071                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.569428                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       17.390583                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        2.344347                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::1                   4      0.07%      0.07% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::2                   2      0.03%      0.10% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::3                   6      0.10%      0.20% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::4                   3      0.05%      0.25% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::5                   4      0.07%      0.31% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::6                   3      0.05%      0.36% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::7                   1      0.02%      0.38% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::8                   3      0.05%      0.43% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::9                   4      0.07%      0.49% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::10                  3      0.05%      0.54% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::11                  3      0.05%      0.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::13                  1      0.02%      0.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::14                  3      0.05%      0.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::15                 10      0.16%      0.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               2784     45.86%     46.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17                 49      0.81%     47.49% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18               1358     22.37%     69.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19               1417     23.34%     93.20% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                155      2.55%     95.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                 60      0.99%     96.74% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22                 36      0.59%     97.33% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23                 21      0.35%     97.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24                 24      0.40%     98.07% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25                 17      0.28%     98.35% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26                 23      0.38%     98.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::27                 14      0.23%     98.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28                 10      0.16%     99.13% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::29                 12      0.20%     99.32% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::30                 16      0.26%     99.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::31                 11      0.18%     99.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32                 14      0.23%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            6071                       # Writes before turning the bus around for reads
+system.physmem.totQLat                   392019251500                       # Total ticks spent queuing
+system.physmem.totMemAccLat              677734639000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                  76190770000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       25726.16                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  44506.44                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         383.12                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           2.68                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       51.37                       # Average system read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  44476.16                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         384.00                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           2.69                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       51.58                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        2.67                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           3.01                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       2.99                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                           3.02                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       3.00                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         6.37                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        14.37                       # Average write queue length when enqueuing
-system.physmem.readRowHits                   14270960                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     91040                       # Number of row buffer hits during writes
+system.physmem.avgRdQLen                         5.74                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        14.90                       # Average write queue length when enqueuing
+system.physmem.readRowHits                   14244888                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     91209                       # Number of row buffer hits during writes
 system.physmem.readRowHitRate                   93.48                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  85.29                       # Row buffer hit rate for writes
-system.physmem.avgGap                       158334.21                       # Average gap between requests
-system.physmem.pageHitRate                      93.42                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE     2202305646000                       # Time in different power states
-system.physmem.memoryStateTime::REF       85157800000                       # Time in different power states
+system.physmem.writeRowHitRate                  85.49                       # Row buffer hit rate for writes
+system.physmem.avgGap                       157685.09                       # Average gap between requests
+system.physmem.pageHitRate                      93.43                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE     2193828681000                       # Time in different power states
+system.physmem.memoryStateTime::REF       84806020000                       # Time in different power states
 system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT      262767276500                       # Time in different power states
+system.physmem.memoryStateTime::ACT      261061225250                       # Time in different power states
 system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
 system.realview.nvmem.bytes_read::cpu0.inst           64                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total            64                       # Number of bytes read from this memory
@@ -328,289 +328,280 @@ system.realview.nvmem.bw_inst_read::cpu0.inst           25
 system.realview.nvmem.bw_inst_read::total           25                       # Instruction read bandwidth from this memory (bytes/s)
 system.realview.nvmem.bw_total::cpu0.inst           25                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::total              25                       # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput                     54978267                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq            16346128                       # Transaction distribution
-system.membus.trans_dist::ReadResp           16346128                       # Transaction distribution
-system.membus.trans_dist::WriteReq             763361                       # Transaction distribution
-system.membus.trans_dist::WriteResp            763361                       # Transaction distribution
-system.membus.trans_dist::Writeback             59160                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             4685                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp            4687                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            131439                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           131439                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave      2383052                       # Packet count per connected master and slave (bytes)
+system.membus.throughput                     55193080                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq            16345666                       # Transaction distribution
+system.membus.trans_dist::ReadResp           16345666                       # Transaction distribution
+system.membus.trans_dist::WriteReq             763357                       # Transaction distribution
+system.membus.trans_dist::WriteResp            763357                       # Transaction distribution
+system.membus.trans_dist::Writeback             58975                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq             4635                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp            4635                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            131547                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           131547                       # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave      2383056                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port            2                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         3790                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         3780                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio            2                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      1885912                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total      4272758                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      1884913                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total      4271753                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port     30277632                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::total     30277632                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total               34550390                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave      2390470                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count::total               34549385                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave      2390478                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port           64                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio         7580                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio         7560                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio            4                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port     16698976                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::total     19097094                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port     16665056                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::total     19063162                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port    121110528                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.iocache.mem_side::total    121110528                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total           140207622                       # Cumulative packet size per connected master and slave (bytes)
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 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
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 system.membus.reqLayer0.utilization               0.1                       # Layer utilization (%)
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 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
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 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer4.occupancy                1500                       # Layer occupancy (ticks)
 system.membus.reqLayer4.utilization               0.0                       # Layer utilization (%)
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 system.membus.reqLayer6.utilization               0.7                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         4714051227                       # Layer occupancy (ticks)
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 system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
-system.membus.respLayer2.occupancy        37455331951                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy        37450374673                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              1.5                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.l2c.tags.replacements                    64405                       # number of replacements
-system.l2c.tags.tagsinuse                51448.142618                       # Cycle average of tags in use
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-system.l2c.tags.avg_refs                    14.672643                       # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle             2540066144500                       # Cycle when the warmup percentage was hit.
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-system.l2c.tags.occ_blocks::cpu0.dtb.walker    24.124150                       # Average occupied blocks per requestor
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 system.l2c.tags.occ_blocks::cpu0.itb.walker     0.000251                       # Average occupied blocks per requestor
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 system.l2c.tags.age_task_id_blocks_1024::0           38                       # Occupied blocks per task id
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-system.l2c.Writeback_hits::writebacks          608464                       # number of Writeback hits
-system.l2c.Writeback_hits::total               608464                       # number of Writeback hits
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-system.l2c.UpgradeReq_hits::total                  38                       # number of UpgradeReq hits
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-system.l2c.Writeback_accesses::total           608464                       # number of Writeback accesses(hits+misses)
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-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.991228                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.987101                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.111111                       # miss rate for SCUpgradeReq accesses
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-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data   190.257375                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total   168.665406                       # average UpgradeReq miss latency
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+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.991618                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.989779                       # miss rate for UpgradeReq accesses
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 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -619,166 +610,154 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks               59160                       # number of writebacks
-system.l2c.writebacks::total                    59160                       # number of writebacks
-system.l2c.ReadReq_mshr_hits::cpu0.inst             8                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu0.data            43                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu1.inst             6                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu1.data            22                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::total                79                       # number of ReadReq MSHR hits
-system.l2c.demand_mshr_hits::cpu0.inst              8                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu0.data             43                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.inst              6                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.data             22                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total                 79                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits::cpu0.inst             8                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu0.data            43                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.inst             6                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.data            22                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total                79                       # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker           35                       # number of ReadReq MSHR misses
+system.l2c.writebacks::writebacks               58975                       # number of writebacks
+system.l2c.writebacks::total                    58975                       # number of writebacks
+system.l2c.ReadReq_mshr_hits::cpu0.inst             7                       # number of ReadReq MSHR hits
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+system.l2c.demand_mshr_hits::cpu0.inst              7                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu0.data             39                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu1.inst              4                       # number of demand (read+write) MSHR hits
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+system.l2c.overall_mshr_hits::total                68                       # number of overall MSHR hits
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 system.l2c.ReadReq_mshr_misses::cpu0.itb.walker            1                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.inst         7812                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.data         6215                       # number of ReadReq MSHR misses
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-system.l2c.ReadReq_mshr_misses::cpu1.inst         4568                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.data         4434                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total           23076                       # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0.data         1552                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data         1356                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total         2908                       # number of UpgradeReq MSHR misses
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-system.l2c.SCUpgradeReq_mshr_misses::total            2                       # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu0.data        77511                       # number of ReadExReq MSHR misses
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 system.l2c.demand_mshr_misses::cpu0.itb.walker            1                       # number of demand (read+write) MSHR misses
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 system.l2c.overall_mshr_misses::cpu0.itb.walker            1                       # number of overall MSHR misses
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-system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker      3127750                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker       281000                       # number of ReadReq MSHR miss cycles
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-system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     15521552                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     13562356                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total     29083908                       # number of UpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data        10001                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data        10001                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::total        20002                       # number of SCUpgradeReq MSHR miss cycles
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-system.l2c.overall_mshr_miss_latency::total   9481351276                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst      6525500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data  83923690500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data  83019017000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total 166949233000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   8966653586                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   8434821998                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total  17401475584                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.inst      6525500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data  92890344086                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data  91453838998                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total 184350708584                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.001080                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.000146                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.015261                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.031382                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.000355                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.009692                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.022143                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.015820                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.983523                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.991228                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.987101                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.111111                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.111111                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.111111                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.572590                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.502313                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.540944                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.001080                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.000146                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.015261                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.251119                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.000355                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.009692                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.193285                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.091673                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.001080                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.000146                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.015261                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.251119                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.000355                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.009692                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.193285                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.091673                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 89364.285714                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker       281000                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 58891.705069                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 61505.752051                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker        70750                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 60247.646673                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 64344.497068                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 60973.392226                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data        10001                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001.737463                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10001.343879                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data        10001                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data        10001                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        10001                       # average SCUpgradeReq mshr miss latency
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-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 59331.574060                       # average ReadExReq mshr miss latency
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-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 89364.285714                       # average overall mshr miss latency
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-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 59701.172833                       # average overall mshr miss latency
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+system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    294835000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.data    281582243                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total   1371510988                       # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     13679367                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     15384538                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total     29063905                       # number of UpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   3324764073                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   4773094655                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total   8097858728                       # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker      1163500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.itb.walker        70000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.inst    427109500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.data   3690889818                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker       625000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst    294835000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data   5054676898                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total   9469369716                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker      1163500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.itb.walker        70000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.inst    427109500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.data   3690889818                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker       625000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst    294835000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data   5054676898                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total   9469369716                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst      6117750                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data  83698669250                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data  83244575500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total 166949362500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   7714617000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   9329751845                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total  17044368845                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.inst      6117750                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data  91413286250                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data  92574327345                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total 183993731345                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.000505                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.000134                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.014912                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.033208                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.000335                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.009751                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.020750                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.015526                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.987717                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.991618                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.989779                       # mshr miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.504178                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.572862                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.541691                       # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.000505                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.000134                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.014912                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.213414                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.000335                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.009751                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.232382                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.091527                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.000505                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.000134                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.014912                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.213414                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.000335                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.009751                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.232382                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.091527                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 83107.142857                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker        70000                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 59140.058156                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 61194.341467                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker        62500                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 60047.861507                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 62769.113464                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 60616.591002                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10006.852231                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10002.950585                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10004.786575                       # average UpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 59057.570972                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 62004.347298                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 60759.611396                       # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 83107.142857                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker        70000                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 59140.058156                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 59262.842293                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker        62500                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 60047.861507                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 62046.459848                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 60738.855032                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 83107.142857                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker        70000                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 59140.058156                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 59262.842293                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker        62500                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60047.861507                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 62046.459848                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 60738.855032                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
@@ -797,48 +776,48 @@ system.cf0.dma_read_txs                             0                       # Nu
 system.cf0.dma_write_full_pages                     0                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                          0                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
-system.toL2Bus.throughput                    58447524                       # Throughput (bytes/s)
-system.toL2Bus.trans_dist::ReadReq            2676676                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           2676675                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq            763361                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp           763361                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback           608464                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq            2946                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq            18                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp           2964                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           246266                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          246266                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      1967872                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      5798454                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side        37749                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side       149111                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               7953186                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     62935104                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     85607366                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side        55020                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side       253376                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size::total          148850866                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.data_through_bus             148850866                       # Total data (bytes)
-system.toL2Bus.snoop_data_through_bus          204184                       # Total snoop data (bytes)
-system.toL2Bus.reqLayer0.occupancy         4964883974                       # Layer occupancy (ticks)
+system.toL2Bus.throughput                    58696725                       # Throughput (bytes/s)
+system.toL2Bus.trans_dist::ReadReq            2675214                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp           2675214                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq            763357                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp           763357                       # Transaction distribution
+system.toL2Bus.trans_dist::Writeback           606690                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq            2935                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq             2                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp           2937                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq           246039                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp          246039                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      1976942                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      5792286                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side        42218                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side       136665                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total               7948111                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     63231360                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     85355770                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side        62032                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side       230312                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size::total          148879474                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.data_through_bus             148879474                       # Total data (bytes)
+system.toL2Bus.snoop_data_through_bus          192412                       # Total snoop data (bytes)
+system.toL2Bus.reqLayer0.occupancy         4956067661                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.2                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy        4433375902                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy        4453658755                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.2                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy        4485758372                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy        4478828129                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.2                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy          24044394                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy          26774357                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy          86236537                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy          79740148                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
-system.iobus.throughput                      48427259                       # Throughput (bytes/s)
-system.iobus.trans_dist::ReadReq             16322165                       # Transaction distribution
-system.iobus.trans_dist::ReadResp            16322165                       # Transaction distribution
-system.iobus.trans_dist::WriteReq                8177                       # Transaction distribution
-system.iobus.trans_dist::WriteResp               8177                       # Transaction distribution
+system.iobus.throughput                      48628247                       # Throughput (bytes/s)
+system.iobus.trans_dist::ReadReq             16322168                       # Transaction distribution
+system.iobus.trans_dist::ReadResp            16322168                       # Transaction distribution
+system.iobus.trans_dist::WriteReq                8176                       # Transaction distribution
+system.iobus.trans_dist::WriteResp               8176                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        30038                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio         7932                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio          522                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio         1030                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio         7940                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio          520                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio         1028                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio           36                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          746                       # Packet count per connected master and slave (bytes)
@@ -858,14 +837,14 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total      2383052                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total      2383056                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side     30277632                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.clcd.dma::total     30277632                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                32660684                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                32660688                       # Packet count per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio        39333                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio        15864                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio         1044                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio         2060                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio        15880                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio         1040                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio         2056                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio           72                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio          397                       # Cumulative packet size per connected master and slave (bytes)
@@ -885,18 +864,18 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::total      2390470                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::total      2390478                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side    121110528                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.realview.clcd.dma::total    121110528                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::total            123500998                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.data_through_bus               123500998                       # Total data (bytes)
+system.iobus.tot_pkt_size::total            123501006                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.data_through_bus               123501006                       # Total data (bytes)
 system.iobus.reqLayer0.occupancy             21111000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy              3971000                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy              3975000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy               522000                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy               520000                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy               521000                       # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy               520000                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer4.occupancy                27000                       # Layer occupancy (ticks)
 system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
@@ -938,19 +917,19 @@ system.iobus.reqLayer23.occupancy                8000                       # La
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer25.occupancy         15138816000                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.6                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy          2374875000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy          2374880000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.1                       # Layer utilization (%)
-system.iobus.respLayer1.occupancy         38148865049                       # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy         38124261327                       # Layer occupancy (ticks)
 system.iobus.respLayer1.utilization               1.5                       # Layer utilization (%)
-system.cpu0.branchPred.lookups                7661485                       # Number of BP lookups
-system.cpu0.branchPred.condPredicted          6126508                       # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect           381527                       # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups             4905065                       # Number of BTB lookups
-system.cpu0.branchPred.BTBHits                3983490                       # Number of BTB hits
+system.cpu0.branchPred.lookups                7765284                       # Number of BP lookups
+system.cpu0.branchPred.condPredicted          5771603                       # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect           325703                       # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups             4845901                       # Number of BTB lookups
+system.cpu0.branchPred.BTBHits                3829041                       # Number of BTB hits
 system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct            81.211768                       # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS                 723596                       # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect             38982                       # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct            79.016080                       # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS                 808445                       # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect             22619                       # Number of incorrect RAS predictions.
 system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -974,25 +953,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # D
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                    25785436                       # DTB read hits
-system.cpu0.dtb.read_misses                     39736                       # DTB read misses
-system.cpu0.dtb.write_hits                    6191742                       # DTB write hits
-system.cpu0.dtb.write_misses                    10170                       # DTB write misses
-system.cpu0.dtb.flush_tlb                         514                       # Number of times complete TLB was flushed
+system.cpu0.dtb.read_hits                    27181562                       # DTB read hits
+system.cpu0.dtb.read_misses                     37782                       # DTB read misses
+system.cpu0.dtb.write_hits                    5596065                       # DTB write hits
+system.cpu0.dtb.write_misses                    10098                       # DTB write misses
+system.cpu0.dtb.flush_tlb                         510                       # Number of times complete TLB was flushed
 system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid                714                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid                     33                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                    5474                       # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults                     1453                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                   252                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_tlb_mva_asid                731                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid                     31                       # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries                    5491                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults                      645                       # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults                   284                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                      628                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                25825172                       # DTB read accesses
-system.cpu0.dtb.write_accesses                6201912                       # DTB write accesses
+system.cpu0.dtb.perms_faults                      704                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses                27219344                       # DTB read accesses
+system.cpu0.dtb.write_accesses                5606163                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                         31977178                       # DTB hits
-system.cpu0.dtb.misses                          49906                       # DTB misses
-system.cpu0.dtb.accesses                     32027084                       # DTB accesses
+system.cpu0.dtb.hits                         32777627                       # DTB hits
+system.cpu0.dtb.misses                          47880                       # DTB misses
+system.cpu0.dtb.accesses                     32825507                       # DTB accesses
 system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -1014,696 +993,712 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.inst_hits                     5958651                       # ITB inst hits
-system.cpu0.itb.inst_misses                      7224                       # ITB inst misses
+system.cpu0.itb.inst_hits                     5349242                       # ITB inst hits
+system.cpu0.itb.inst_misses                      7594                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
 system.cpu0.itb.write_misses                        0                       # DTB write misses
-system.cpu0.itb.flush_tlb                         514                       # Number of times complete TLB was flushed
+system.cpu0.itb.flush_tlb                         510                       # Number of times complete TLB was flushed
 system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid                714                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid                     33                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                    2573                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_tlb_mva_asid                731                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid                     31                       # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries                    2632                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults                     1518                       # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults                     2439                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses                 5965875                       # ITB inst accesses
-system.cpu0.itb.hits                          5958651                       # DTB hits
-system.cpu0.itb.misses                           7224                       # DTB misses
-system.cpu0.itb.accesses                      5965875                       # DTB accesses
-system.cpu0.numCycles                       242096947                       # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses                 5356836                       # ITB inst accesses
+system.cpu0.itb.hits                          5349242                       # DTB hits
+system.cpu0.itb.misses                           7594                       # DTB misses
+system.cpu0.itb.accesses                      5356836                       # DTB accesses
+system.cpu0.numCycles                       234138431                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles          15548527                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts                      46430150                       # Number of instructions fetch has processed
-system.cpu0.fetch.Branches                    7661485                       # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches           4707086                       # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles                     10443980                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles                2504010                       # Number of cycles fetch has spent squashing
-system.cpu0.fetch.TlbCycles                     87505                       # Number of cycles fetch has spent waiting for tlb
-system.cpu0.fetch.BlockedCycles              47991707                       # Number of cycles fetch has spent blocked
-system.cpu0.fetch.MiscStallCycles                1669                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingDrainCycles             1947                       # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu0.fetch.PendingTrapStallCycles        50069                       # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles      1492171                       # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles          279                       # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines                  5956718                       # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes               371320                       # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.ItlbSquashes                   2975                       # Number of outstanding ITLB misses that were squashed
-system.cpu0.fetch.rateDist::samples          77361996                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean             0.753757                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev            2.110815                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.icacheStallCycles          14733348                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts                      42294638                       # Number of instructions fetch has processed
+system.cpu0.fetch.Branches                    7765284                       # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches           4637486                       # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles                    215157682                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles                 899672                       # Number of cycles fetch has spent squashing
+system.cpu0.fetch.TlbCycles                    103093                       # Number of cycles fetch has spent waiting for tlb
+system.cpu0.fetch.MiscStallCycles                 978                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingDrainCycles             1882                       # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu0.fetch.PendingTrapStallCycles       100153                       # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles      1830103                       # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles          127                       # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines                  5346345                       # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes               204670                       # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.ItlbSquashes                   3021                       # Number of outstanding ITLB misses that were squashed
+system.cpu0.fetch.rateDist::samples         232377075                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean             0.216391                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev            1.156919                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0                66925381     86.51%     86.51% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1                  685980      0.89%     87.40% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2                  883677      1.14%     88.54% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3                 1195178      1.54%     90.08% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4                 1096516      1.42%     91.50% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5                  566437      0.73%     92.23% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6                 1314357      1.70%     93.93% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::7                  386846      0.50%     94.43% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::8                 4307624      5.57%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0               222728537     95.85%     95.85% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1                  885926      0.38%     96.23% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2                  959241      0.41%     96.64% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3                 1030592      0.44%     97.09% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4                 1233052      0.53%     97.62% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5                  718062      0.31%     97.93% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6                 1129349      0.49%     98.41% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::7                  448984      0.19%     98.60% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::8                 3243332      1.40%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total            77361996                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate                 0.031646                       # Number of branch fetches per cycle
-system.cpu0.fetch.rate                       0.191783                       # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles                16313273                       # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles             49370536                       # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles                  9491475                       # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles               529288                       # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles               1655237                       # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved             1021533                       # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred                91523                       # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts              55531280                       # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts               303986                       # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles               1655237                       # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles                17162522                       # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles                7654348                       # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles      28580121                       # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles                  9244360                       # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles             13063308                       # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts              52889125                       # Number of instructions processed by rename
-system.cpu0.rename.ROBFullEvents                 1160                       # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents               8605902                       # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LQFullEvents               9933616                       # Number of times rename has blocked due to LQ full
-system.cpu0.rename.SQFullEvents               1829408                       # Number of times rename has blocked due to SQ full
-system.cpu0.rename.FullRegisterEvents             705                       # Number of times there has been no free registers
-system.cpu0.rename.RenamedOperands           54696180                       # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups            245103090                       # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups       223663577                       # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups             5274                       # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps             39761499                       # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps                14934681                       # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts            590339                       # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts        538925                       # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts                  5812671                       # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads            10214201                       # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores            7053988                       # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads          1084092                       # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores         1355038                       # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded                  49147671                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded            1004891                       # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued                 62507144                       # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued           106564                       # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined       10354652                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined     26208427                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved        256708                       # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples     77361996                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean        0.807983                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev       1.536259                       # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total           232377075                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate                 0.033165                       # Number of branch fetches per cycle
+system.cpu0.fetch.rate                       0.180639                       # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles                12160999                       # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles            212353937                       # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles                  6177683                       # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles              1309281                       # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles                372986                       # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved              974074                       # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred                78107                       # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts              45045632                       # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts               258698                       # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles                372986                       # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles                12774661                       # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles               53419035                       # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles      30524585                       # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles                  6795741                       # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles            128487965                       # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts              43632543                       # Number of instructions processed by rename
+system.cpu0.rename.ROBFullEvents                 1343                       # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents              95385189                       # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LQFullEvents             124519108                       # Number of times rename has blocked due to LQ full
+system.cpu0.rename.SQFullEvents               1934134                       # Number of times rename has blocked due to SQ full
+system.cpu0.rename.RenamedOperands           46283925                       # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups            200651385                       # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups        53129662                       # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups             5272                       # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps             36330469                       # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps                 9953456                       # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts            576590                       # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts        492282                       # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts                  7436987                       # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads             7977179                       # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores            6240861                       # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads          1088795                       # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores         1688387                       # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded                  41277277                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded            1012498                       # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued                 59014531                       # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued            58753                       # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined        7256631                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined     15830718                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved        292140                       # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples    232377075                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean        0.253960                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev       0.959343                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0           55228815     71.39%     71.39% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1            6921867      8.95%     80.34% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2            3371546      4.36%     84.70% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3            2828196      3.66%     88.35% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4            6343832      8.20%     96.55% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5            1429149      1.85%     98.40% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::6             903697      1.17%     99.57% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::7             264810      0.34%     99.91% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::8              70084      0.09%    100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0          212079469     91.27%     91.27% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1            6238226      2.68%     93.95% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2            2924438      1.26%     95.21% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3            2416467      1.04%     96.25% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4            6166815      2.65%     98.90% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5            1071194      0.46%     99.36% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::6             901941      0.39%     99.75% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::7             385048      0.17%     99.92% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::8             193477      0.08%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total       77361996                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total      232377075                       # Number of insts issued each cycle
 system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu                  34065      0.76%      0.76% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult                     2      0.00%      0.76% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv                      0      0.00%      0.76% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd                    0      0.00%      0.76% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp                    0      0.00%      0.76% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt                    0      0.00%      0.76% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult                   0      0.00%      0.76% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv                    0      0.00%      0.76% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%      0.76% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd                     0      0.00%      0.76% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%      0.76% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu                     0      0.00%      0.76% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp                     0      0.00%      0.76% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt                     0      0.00%      0.76% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc                    0      0.00%      0.76% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult                    0      0.00%      0.76% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%      0.76% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift                   0      0.00%      0.76% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%      0.76% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%      0.76% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%      0.76% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%      0.76% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%      0.76% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%      0.76% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%      0.76% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%      0.76% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%      0.76% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%      0.76% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%      0.76% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead               4230863     93.99%     94.75% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite               236461      5.25%    100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu                 114630      2.27%      2.27% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult                     3      0.00%      2.27% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv                      0      0.00%      2.27% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd                    0      0.00%      2.27% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp                    0      0.00%      2.27% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt                    0      0.00%      2.27% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult                   0      0.00%      2.27% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv                    0      0.00%      2.27% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%      2.27% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd                     0      0.00%      2.27% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%      2.27% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu                     0      0.00%      2.27% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp                     0      0.00%      2.27% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt                     0      0.00%      2.27% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc                    0      0.00%      2.27% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult                    0      0.00%      2.27% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%      2.27% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift                   0      0.00%      2.27% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%      2.27% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%      2.27% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%      2.27% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%      2.27% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%      2.27% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%      2.27% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%      2.27% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%      2.27% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%      2.27% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%      2.27% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%      2.27% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead               4666706     92.48%     94.76% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite               264598      5.24%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu0.iq.FU_type_0::No_OpClass            14977      0.02%      0.02% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu             29471794     47.15%     47.17% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult               48326      0.08%     47.25% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     47.25% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     47.25% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     47.25% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     47.25% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     47.25% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     47.25% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     47.25% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     47.25% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     47.25% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     47.25% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     47.25% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     47.25% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc                 10      0.00%     47.25% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     47.25% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     47.25% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     47.25% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc              7      0.00%     47.25% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     47.25% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     47.25% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     47.25% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     47.25% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     47.25% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     47.25% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc          1252      0.00%     47.25% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     47.25% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc           10      0.00%     47.25% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     47.25% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead            26467836     42.34%     89.60% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite            6502932     10.40%    100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::No_OpClass            15012      0.03%      0.03% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu             25515552     43.24%     43.26% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult               47770      0.08%     43.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     43.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     43.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     43.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     43.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     43.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     43.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     43.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     43.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     43.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     43.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     43.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     43.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     43.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     43.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     43.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     43.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     43.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     43.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     43.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     43.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     43.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     43.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     43.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc           902      0.00%     43.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     43.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     43.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     43.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead            27508063     46.61%     89.96% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite            5927232     10.04%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total              62507144                       # Type of FU issued
-system.cpu0.iq.rate                          0.258191                       # Inst issue rate
-system.cpu0.iq.fu_busy_cnt                    4501391                       # FU busy when requested
-system.cpu0.iq.fu_busy_rate                  0.072014                       # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads         207022163                       # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes         60516960                       # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses     43741315                       # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads              11807                       # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes              6284                       # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses         5315                       # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses              66987291                       # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses                   6267                       # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads          331575                       # Number of loads that had data forwarded from stores
+system.cpu0.iq.FU_type_0::total              59014531                       # Type of FU issued
+system.cpu0.iq.rate                          0.252050                       # Inst issue rate
+system.cpu0.iq.fu_busy_cnt                    5045937                       # FU busy when requested
+system.cpu0.iq.fu_busy_rate                  0.085503                       # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads         355498871                       # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes         49563440                       # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses     38260615                       # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads              11956                       # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes              6482                       # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_wakeup_accesses         5191                       # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.int_alu_accesses              64039026                       # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses                   6430                       # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads          226085                       # Number of loads that had data forwarded from stores
 system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads      2258680                       # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses         3312                       # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation        16640                       # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores       890724                       # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads      1459518                       # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses         2588                       # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation        24632                       # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores       672041                       # Number of stores squashed
 system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads     17025951                       # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked       348422                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.rescheduledLoads     17098280                       # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked      3147229                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles               1655237                       # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles                6199849                       # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles               752551                       # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts           50264845                       # Number of instructions dispatched to IQ
-system.cpu0.iew.iewDispSquashedInsts            98291                       # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts             10214201                       # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts             7053988                       # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts            705061                       # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents                147463                       # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents               536075                       # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents         16640                       # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect        186895                       # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect       147787                       # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts              334682                       # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts             61435794                       # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts             26133192                       # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts          1071350                       # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewSquashCycles                372986                       # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles               50915247                       # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles              1803662                       # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts           42401043                       # Number of instructions dispatched to IQ
+system.cpu0.iew.iewDispSquashedInsts            79571                       # Number of squashed instructions skipped by dispatch
+system.cpu0.iew.iewDispLoadInsts              7977179                       # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts             6240861                       # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts            734817                       # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents                139591                       # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents              1596321                       # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents         24632                       # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect        160350                       # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect       132588                       # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts              292938                       # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts             58604130                       # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts             27345857                       # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts           362682                       # Number of squashed instructions skipped in execute
 system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu0.iew.exec_nop                       112283                       # number of nop insts executed
-system.cpu0.iew.exec_refs                    32576038                       # number of memory reference insts executed
-system.cpu0.iew.exec_branches                 6024055                       # Number of branches executed
-system.cpu0.iew.exec_stores                   6442846                       # Number of stores executed
-system.cpu0.iew.exec_rate                    0.253765                       # Inst execution rate
-system.cpu0.iew.wb_sent                      60932314                       # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count                     43746630                       # cumulative count of insts written-back
-system.cpu0.iew.wb_producers                 24175990                       # num instructions producing a value
-system.cpu0.iew.wb_consumers                 44857309                       # num instructions consuming a value
+system.cpu0.iew.exec_nop                       111268                       # number of nop insts executed
+system.cpu0.iew.exec_refs                    33208867                       # number of memory reference insts executed
+system.cpu0.iew.exec_branches                 5668977                       # Number of branches executed
+system.cpu0.iew.exec_stores                   5863010                       # Number of stores executed
+system.cpu0.iew.exec_rate                    0.250297                       # Inst execution rate
+system.cpu0.iew.wb_sent                      55434698                       # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count                     38265806                       # cumulative count of insts written-back
+system.cpu0.iew.wb_producers                 21645924                       # num instructions producing a value
+system.cpu0.iew.wb_consumers                 38521221                       # num instructions consuming a value
 system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu0.iew.wb_rate                      0.180699                       # insts written-back per cycle
-system.cpu0.iew.wb_fanout                    0.538953                       # average fanout of values written-back
+system.cpu0.iew.wb_rate                      0.163432                       # insts written-back per cycle
+system.cpu0.iew.wb_fanout                    0.561922                       # average fanout of values written-back
 system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.commit.commitSquashedInsts       10244306                       # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls         748183                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts           291383                       # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples     75706759                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean     0.522606                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev     1.501619                       # Number of insts commited each cycle
+system.cpu0.commit.commitSquashedInsts        7110536                       # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls         720358                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts           248726                       # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples    231246727                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean     0.150700                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev     0.849611                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0     61320530     81.00%     81.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1      7333121      9.69%     90.68% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2      1910409      2.52%     93.21% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3      1174950      1.55%     94.76% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4       814971      1.08%     95.84% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5       569506      0.75%     96.59% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6       771340      1.02%     97.61% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7       344904      0.46%     98.06% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8      1467028      1.94%    100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0    218753445     94.60%     94.60% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1      6297983      2.72%     97.32% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2      1708084      0.74%     98.06% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3      1059115      0.46%     98.52% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4       644957      0.28%     98.80% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5       581299      0.25%     99.05% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6       449364      0.19%     99.24% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7       245033      0.11%     99.35% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8      1507447      0.65%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total     75706759                       # Number of insts commited each cycle
-system.cpu0.commit.committedInsts            30422123                       # Number of instructions committed
-system.cpu0.commit.committedOps              39564795                       # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total    231246727                       # Number of insts commited each cycle
+system.cpu0.commit.committedInsts            29059194                       # Number of instructions committed
+system.cpu0.commit.committedOps              34848810                       # Number of ops (including micro ops) committed
 system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu0.commit.refs                      14118785                       # Number of memory references committed
-system.cpu0.commit.loads                      7955521                       # Number of loads committed
-system.cpu0.commit.membars                     210845                       # Number of memory barriers committed
-system.cpu0.commit.branches                   5215430                       # Number of branches committed
-system.cpu0.commit.fp_insts                      5270                       # Number of committed floating point instructions.
-system.cpu0.commit.int_insts                 35234514                       # Number of committed integer instructions.
-system.cpu0.commit.function_calls              505825                       # Number of function calls committed.
+system.cpu0.commit.refs                      12086481                       # Number of memory references committed
+system.cpu0.commit.loads                      6517661                       # Number of loads committed
+system.cpu0.commit.membars                     192728                       # Number of memory barriers committed
+system.cpu0.commit.branches                   4958536                       # Number of branches committed
+system.cpu0.commit.fp_insts                      5174                       # Number of committed floating point instructions.
+system.cpu0.commit.int_insts                 30757342                       # Number of committed integer instructions.
+system.cpu0.commit.function_calls              472350                       # Number of function calls committed.
 system.cpu0.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntAlu        25399613     64.20%     64.20% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntMult          45146      0.11%     64.31% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntDiv               0      0.00%     64.31% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     64.31% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     64.31% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     64.31% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatMult            0      0.00%     64.31% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     64.31% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     64.31% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     64.31% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     64.31% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     64.31% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     64.31% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     64.31% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     64.31% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMult             0      0.00%     64.31% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     64.31% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShift            0      0.00%     64.31% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     64.31% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     64.31% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     64.31% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     64.31% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     64.31% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     64.31% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     64.31% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMisc         1251      0.00%     64.31% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     64.31% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     64.31% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     64.31% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemRead        7955521     20.11%     84.42% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemWrite       6163264     15.58%    100.00% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntAlu        22717072     65.19%     65.19% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntMult          44355      0.13%     65.31% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntDiv               0      0.00%     65.31% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     65.31% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     65.31% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     65.31% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatMult            0      0.00%     65.31% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     65.31% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     65.31% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     65.31% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     65.31% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     65.31% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     65.31% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     65.31% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     65.31% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMult             0      0.00%     65.31% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     65.31% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShift            0      0.00%     65.31% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     65.31% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     65.31% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     65.31% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     65.31% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     65.31% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     65.31% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     65.31% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMisc          902      0.00%     65.32% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     65.32% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     65.32% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     65.32% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemRead        6517661     18.70%     84.02% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemWrite       5568820     15.98%    100.00% # Class of committed instruction
 system.cpu0.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::total         39564795                       # Class of committed instruction
-system.cpu0.commit.bw_lim_events              1467028                       # number cycles where commit BW limit reached
+system.cpu0.commit.op_class_0::total         34848810                       # Class of committed instruction
+system.cpu0.commit.bw_lim_events              1507447                       # number cycles where commit BW limit reached
 system.cpu0.commit.bw_limited                       0                       # number of insts not committed due to BW limits
-system.cpu0.rob.rob_reads                   123090455                       # The number of ROB reads
-system.cpu0.rob.rob_writes                  101316686                       # The number of ROB writes
-system.cpu0.timesIdled                         905863                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles                      164734951                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.quiesceCycles                  2248240039                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.committedInsts                   30347856                       # Number of Instructions Simulated
-system.cpu0.committedOps                     39490528                       # Number of Ops (including micro ops) Simulated
-system.cpu0.cpi                              7.977399                       # CPI: Cycles Per Instruction
-system.cpu0.cpi_total                        7.977399                       # CPI: Total CPI of All Threads
-system.cpu0.ipc                              0.125354                       # IPC: Instructions Per Cycle
-system.cpu0.ipc_total                        0.125354                       # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads               279159718                       # number of integer regfile reads
-system.cpu0.int_regfile_writes               44499662                       # number of integer regfile writes
-system.cpu0.fp_regfile_reads                    45106                       # number of floating regfile reads
-system.cpu0.fp_regfile_writes                   42408                       # number of floating regfile writes
-system.cpu0.misc_regfile_reads              136236681                       # number of misc regfile reads
-system.cpu0.misc_regfile_writes                579467                       # number of misc regfile writes
-system.cpu0.icache.tags.replacements           983848                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.584983                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs           10572279                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs           984360                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            10.740257                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle       6906897250                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   320.103204                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu1.inst   191.481778                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.625202                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu1.inst     0.373988                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.999189                       # Average percentage of cache occupancy
+system.cpu0.rob.rob_reads                   270795640                       # The number of ROB reads
+system.cpu0.rob.rob_writes                   85052492                       # The number of ROB writes
+system.cpu0.timesIdled                         264396                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.idleCycles                        1761356                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.quiesceCycles                  2270391996                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.committedInsts                   28992496                       # Number of Instructions Simulated
+system.cpu0.committedOps                     34782112                       # Number of Ops (including micro ops) Simulated
+system.cpu0.cpi                              8.075829                       # CPI: Cycles Per Instruction
+system.cpu0.cpi_total                        8.075829                       # CPI: Total CPI of All Threads
+system.cpu0.ipc                              0.123826                       # IPC: Instructions Per Cycle
+system.cpu0.ipc_total                        0.123826                       # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads                66468797                       # number of integer regfile reads
+system.cpu0.int_regfile_writes               24185826                       # number of integer regfile writes
+system.cpu0.fp_regfile_reads                    44758                       # number of floating regfile reads
+system.cpu0.fp_regfile_writes                   41844                       # number of floating regfile writes
+system.cpu0.cc_regfile_reads                196782773                       # number of cc regfile reads
+system.cpu0.cc_regfile_writes                15711716                       # number of cc regfile writes
+system.cpu0.misc_regfile_reads              291428250                       # number of misc regfile reads
+system.cpu0.misc_regfile_writes                565781                       # number of misc regfile writes
+system.cpu0.icache.tags.replacements           988317                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.592753                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs            9970376                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs           988829                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            10.083013                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle       6654117250                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   184.676713                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu1.inst   326.916040                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.360697                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu1.inst     0.638508                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.999205                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0          138                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          211                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2          162                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0          133                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1          223                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2          155                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses         12622728                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses        12622728                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst      5401219                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu1.inst      5171060                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total       10572279                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst      5401219                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu1.inst      5171060                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total        10572279                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst      5401219                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu1.inst      5171060                       # number of overall hits
-system.cpu0.icache.overall_hits::total       10572279                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst       555378                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu1.inst       510680                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total      1066058                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst       555378                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu1.inst       510680                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total       1066058                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst       555378                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu1.inst       510680                       # number of overall misses
-system.cpu0.icache.overall_misses::total      1066058                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst   7663232618                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::cpu1.inst   6859208809                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total  14522441427                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst   7663232618                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::cpu1.inst   6859208809                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total  14522441427                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst   7663232618                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::cpu1.inst   6859208809                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total  14522441427                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst      5956597                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu1.inst      5681740                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total     11638337                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst      5956597                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu1.inst      5681740                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total     11638337                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst      5956597                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu1.inst      5681740                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total     11638337                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.093237                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.089881                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.091599                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.093237                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu1.inst     0.089881                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.091599                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.093237                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu1.inst     0.089881                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.091599                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13798.228626                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13431.520343                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 13622.562212                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13798.228626                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13431.520343                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 13622.562212                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13798.228626                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13431.520343                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 13622.562212                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs         6762                       # number of cycles access was blocked
+system.cpu0.icache.tags.tag_accesses         12025421                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses        12025421                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst      4823915                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu1.inst      5146461                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total        9970376                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst      4823915                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu1.inst      5146461                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total         9970376                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst      4823915                       # number of overall hits
+system.cpu0.icache.overall_hits::cpu1.inst      5146461                       # number of overall hits
+system.cpu0.icache.overall_hits::total        9970376                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst       522311                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu1.inst       543898                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total      1066209                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst       522311                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu1.inst       543898                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total       1066209                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst       522311                       # number of overall misses
+system.cpu0.icache.overall_misses::cpu1.inst       543898                       # number of overall misses
+system.cpu0.icache.overall_misses::total      1066209                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst   7237674573                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::cpu1.inst   7341681631                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total  14579356204                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst   7237674573                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::cpu1.inst   7341681631                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total  14579356204                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst   7237674573                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::cpu1.inst   7341681631                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total  14579356204                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst      5346226                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu1.inst      5690359                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total     11036585                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst      5346226                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu1.inst      5690359                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total     11036585                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst      5346226                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu1.inst      5690359                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total     11036585                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.097697                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.095582                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.096607                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.097697                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu1.inst     0.095582                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.096607                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.097697                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu1.inst     0.095582                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.096607                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13857.021148                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13498.269218                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 13674.013448                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13857.021148                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13498.269218                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 13674.013448                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13857.021148                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13498.269218                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 13674.013448                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs         4158                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs              376                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs              274                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs    17.984043                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs    15.175182                       # average number of cycles each access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        42863                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst        38803                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total        81666                       # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu0.inst        42863                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu1.inst        38803                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total        81666                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu0.inst        42863                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu1.inst        38803                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total        81666                       # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       512515                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       471877                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total       984392                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst       512515                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu1.inst       471877                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total       984392                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst       512515                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu1.inst       471877                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total       984392                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   6228172986                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst   5583639583                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total  11811812569                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   6228172986                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst   5583639583                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total  11811812569                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   6228172986                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst   5583639583                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total  11811812569                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst      8994500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total      8994500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst      8994500                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::total      8994500                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.086042                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.083051                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.084582                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.086042                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.083051                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.084582                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.086042                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.083051                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.084582                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12152.176982                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11832.828434                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11999.094435                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12152.176982                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11832.828434                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 11999.094435                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12152.176982                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11832.828434                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 11999.094435                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        37549                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst        39824                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total        77373                       # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu0.inst        37549                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu1.inst        39824                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total        77373                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu0.inst        37549                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu1.inst        39824                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total        77373                       # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       484762                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       504074                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total       988836                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst       484762                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu1.inst       504074                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total       988836                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst       484762                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu1.inst       504074                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total       988836                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   5888564763                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst   5971220456                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total  11859785219                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   5888564763                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst   5971220456                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total  11859785219                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   5888564763                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst   5971220456                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total  11859785219                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst      8523250                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total      8523250                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst      8523250                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::total      8523250                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.090674                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.088584                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.089596                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.090674                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.088584                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.089596                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.090674                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.088584                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.089596                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12147.331604                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11845.920353                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11993.682693                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12147.331604                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11845.920353                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 11993.682693                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12147.331604                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11845.920353                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 11993.682693                       # average overall mshr miss latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.dcache.tags.replacements           644041                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          511.993361                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           21521749                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs           644553                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            33.390193                       # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle         42479250                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   255.642215                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu1.data   256.351146                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.499301                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu1.data     0.500686                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.replacements           641884                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          511.993418                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs           19756750                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs           642396                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            30.754784                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.warmup_cycle         42094250                       # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   133.972457                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu1.data   378.020960                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.261665                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu1.data     0.738322                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_percent::total     0.999987                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0          193                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          302                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           17                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0          198                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          296                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           18                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses        101726761                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses       101726761                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data      7076892                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu1.data      6698233                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total       13775125                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data      3751457                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu1.data      3500966                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total       7252423                       # number of WriteReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       118146                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu1.data       125300                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       243446                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       120516                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu1.data       127110                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       247626                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data     10828349                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu1.data     10199199                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        21027548                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data     10828349                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu1.data     10199199                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       21027548                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data       365609                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu1.data       402058                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total       767667                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data      1663469                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu1.data      1307220                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total      2970689                       # number of WriteReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         7411                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu1.data         6147                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total        13558                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data            9                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu1.data            9                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total           18                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data      2029078                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu1.data      1709278                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       3738356                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data      2029078                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu1.data      1709278                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      3738356                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   5771940837                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   5897981485                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total  11669922322                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  84085334445                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu1.data  56096709102                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total 140182043547                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    106232248                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data     81884247                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total    188116495                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data       129501                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data       129501                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total       259002                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data  89857275282                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu1.data  61994690587                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 151851965869                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data  89857275282                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu1.data  61994690587                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 151851965869                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data      7442501                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu1.data      7100291                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total     14542792                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data      5414926                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu1.data      4808186                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total     10223112                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       125557                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data       131447                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       257004                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       120525                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu1.data       127119                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       247644                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data     12857427                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu1.data     11908477                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     24765904                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data     12857427                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu1.data     11908477                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     24765904                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.049124                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.056626                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.052787                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.307201                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.271874                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.290586                       # miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.059025                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.046764                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.052754                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.000075                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data     0.000071                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000073                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.157814                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu1.data     0.143535                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.150948                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.157814                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu1.data     0.143535                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.150948                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15787.195712                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14669.479242                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 15201.802763                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 50548.182410                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 42912.982591                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 47188.394190                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14334.401295                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13321.009761                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13874.944313                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data        14389                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data        14389                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total        14389                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 44284.781207                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 36269.518818                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 40619.985328                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 44284.781207                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 36269.518818                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 40619.985328                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs        36311                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets        24635                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs             3444                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets            311                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs    10.543264                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets    79.212219                       # average number of cycles each access was blocked
+system.cpu0.dcache.tags.tag_accesses         95317436                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses        95317436                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data      5857300                       # number of ReadReq hits
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+system.cpu0.dcache.SoftPFReq_misses::total       128509                       # number of SoftPFReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         6350                       # number of LoadLockedReq misses
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+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   4378228092                       # number of ReadReq miss cycles
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+system.cpu0.dcache.ReadReq_miss_latency::total  10133390730                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  57860586634                       # number of WriteReq miss cycles
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+system.cpu0.dcache.WriteReq_miss_latency::total 143890414211                       # number of WriteReq miss cycles
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+system.cpu0.dcache.LoadLockedReq_miss_latency::total    187029228                       # number of LoadLockedReq miss cycles
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+system.cpu0.dcache.StoreCondReq_miss_latency::total        26000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data  62238814726                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu1.data  91784990215                       # number of demand (read+write) miss cycles
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+system.cpu0.dcache.overall_miss_latency::total 154023804941                       # number of overall miss cycles
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+system.cpu0.dcache.SoftPFReq_accesses::cpu1.data        84499                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total       193548                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       116532                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data       140170                       # number of LoadLockedReq accesses(hits+misses)
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+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.048056                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.060107                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.054290                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.280045                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.320702                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.301359                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.676787                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.647416                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.663964                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.054491                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.049797                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.051928                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.000018                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000008                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.150484                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu1.data     0.176964                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.164263                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.155642                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu1.data     0.180266                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.168439                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14806.968490                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14522.200645                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 14643.882163                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 42473.998435                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 50045.856114                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 46698.275038                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14594.998425                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13517.333524                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14030.699775                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data        13000                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total        13000                       # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 37539.711623                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 43390.572975                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 40819.747169                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 35939.858909                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 42296.704241                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 39475.306871                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs       204060                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets        43131                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs            27157                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets            778                       # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs     7.514085                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets    55.438303                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       608464                       # number of writebacks
-system.cpu0.dcache.writebacks::total           608464                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       174205                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data       207237                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total       381442                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1526591                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data      1195009                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total      2721600                       # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data          704                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data          669                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total         1373                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data      1700796                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu1.data      1402246                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total      3103042                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data      1700796                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu1.data      1402246                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total      3103042                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       191404                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       194821                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       386225                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       136878                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data       112211                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       249089                       # number of WriteReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         6707                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         5478                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total        12185                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data            9                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data            9                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total           18                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data       328282                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu1.data       307032                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total       635314                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data       328282                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu1.data       307032                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total       635314                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   2672225710                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   2597817092                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total   5270042802                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   6526900100                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   4738022235                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total  11264922335                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     84662502                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     63153752                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    147816254                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data       111499                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data       111499                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total       222998                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   9199125810                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   7335839327                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  16534965137                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data   9199125810                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   7335839327                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  16534965137                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data  91653477500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data  90683023500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182336501000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data  13720132000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data  13077337591                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total  26797469591                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 105373609500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 103760361091                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total 209133970591                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.025718                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.027438                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.026558                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.025278                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.023337                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.024365                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.053418                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.041675                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.047412                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.000075                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.000071                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000073                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.025532                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.025783                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.025653                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.025532                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.025783                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.025653                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13961.180069                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13334.379210                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13645.006931                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 47684.069756                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 42224.222536                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 45224.487372                       # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12623.006113                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11528.614823                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12131.001559                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 12388.777778                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 12388.777778                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 12388.777778                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 28022.023169                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 23892.751658                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26026.445407                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 28022.023169                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 23892.751658                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26026.445407                       # average overall mshr miss latency
+system.cpu0.dcache.writebacks::writebacks       606690                       # number of writebacks
+system.cpu0.dcache.writebacks::total           606690                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       164206                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data       218384                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total       382590                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1249257                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data      1583126                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total      2832383                       # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data          616                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data          758                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total         1374                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data      1413463                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu1.data      1801510                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total      3214973                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data      1413463                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu1.data      1801510                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total      3214973                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       131481                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       177917                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total       309398                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       113002                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data       135894                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       248896                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data        42994                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data        32087                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total        75081                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         5734                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         6222                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total        11956                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data            2                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total            2                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data       244483                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu1.data       313811                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total       558294                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data       287477                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu1.data       345898                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total       633375                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   1725190273                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   2222171472                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total   3947361745                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   4787330436                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   6538944348                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total  11326274784                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data    807768256                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    644366504                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1452134760                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     73471759                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     72597010                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    146068769                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data        22000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total        22000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   6512520709                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   8761115820                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  15273636529                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data   7320288965                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   9405482324                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  16725771289                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data  91407551750                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data  90929310002                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182336861752                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data  11972132389                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data  14721058995                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total  26693191384                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 103379684139                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 105650368997                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 209030053136                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.021369                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.026985                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.024274                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.023230                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.025353                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.024343                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.394263                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.379732                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.387919                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.049205                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.044389                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.046575                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.000018                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000008                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.022191                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.026253                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.024304                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.025837                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.028734                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.027343                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13121.213506                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12489.933351                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12758.200586                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 42365.006248                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 48117.976864                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 45506.053870                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 18787.929851                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 20081.855705                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 19340.908619                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12813.351761                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11667.793314                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12217.193794                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data        11000                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total        11000                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 26637.928645                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 27918.447154                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 27357.694206                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 25463.911774                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 27191.490914                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26407.375234                       # average overall mshr miss latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -1714,15 +1709,15 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf
 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.branchPred.lookups                7344792                       # Number of BP lookups
-system.cpu1.branchPred.condPredicted          5924572                       # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect           342317                       # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups             4758265                       # Number of BTB lookups
-system.cpu1.branchPred.BTBHits                3794052                       # Number of BTB hits
+system.cpu1.branchPred.lookups                8288231                       # Number of BP lookups
+system.cpu1.branchPred.condPredicted          6165176                       # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect           342380                       # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups             5156418                       # Number of BTB lookups
+system.cpu1.branchPred.BTBHits                4057157                       # Number of BTB hits
 system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct            79.736038                       # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS                 685317                       # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect             35371                       # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct            78.681693                       # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS                 881950                       # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect             23449                       # Number of incorrect RAS predictions.
 system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -1746,25 +1741,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # D
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                    25350014                       # DTB read hits
-system.cpu1.dtb.read_misses                     36246                       # DTB read misses
-system.cpu1.dtb.write_hits                    5533315                       # DTB write hits
-system.cpu1.dtb.write_misses                     8540                       # DTB write misses
-system.cpu1.dtb.flush_tlb                         510                       # Number of times complete TLB was flushed
+system.cpu1.dtb.read_hits                    28293531                       # DTB read hits
+system.cpu1.dtb.read_misses                     40544                       # DTB read misses
+system.cpu1.dtb.write_hits                    6190636                       # DTB write hits
+system.cpu1.dtb.write_misses                    14491                       # DTB write misses
+system.cpu1.dtb.flush_tlb                         506                       # Number of times complete TLB was flushed
 system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid                725                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid                     30                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                    5471                       # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults                     1908                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                   249                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.flush_tlb_mva_asid                708                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid                     32                       # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries                    5400                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults                      865                       # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults                   285                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                      710                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                25386260                       # DTB read accesses
-system.cpu1.dtb.write_accesses                5541855                       # DTB write accesses
+system.cpu1.dtb.perms_faults                      723                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses                28334075                       # DTB read accesses
+system.cpu1.dtb.write_accesses                6205127                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                         30883329                       # DTB hits
-system.cpu1.dtb.misses                          44786                       # DTB misses
-system.cpu1.dtb.accesses                     30928115                       # DTB accesses
+system.cpu1.dtb.hits                         34484167                       # DTB hits
+system.cpu1.dtb.misses                          55035                       # DTB misses
+system.cpu1.dtb.accesses                     34539202                       # DTB accesses
 system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -1786,329 +1781,329 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.inst_hits                     5683844                       # ITB inst hits
-system.cpu1.itb.inst_misses                      6848                       # ITB inst misses
+system.cpu1.itb.inst_hits                     5693555                       # ITB inst hits
+system.cpu1.itb.inst_misses                      8207                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
 system.cpu1.itb.write_misses                        0                       # DTB write misses
-system.cpu1.itb.flush_tlb                         510                       # Number of times complete TLB was flushed
+system.cpu1.itb.flush_tlb                         506                       # Number of times complete TLB was flushed
 system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid                725                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid                     30                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                    2653                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_tlb_mva_asid                708                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid                     32                       # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries                    2675                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults                     1514                       # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults                     2702                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses                 5690692                       # ITB inst accesses
-system.cpu1.itb.hits                          5683844                       # DTB hits
-system.cpu1.itb.misses                           6848                       # DTB misses
-system.cpu1.itb.accesses                      5690692                       # DTB accesses
-system.cpu1.numCycles                       235812118                       # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses                 5701762                       # ITB inst accesses
+system.cpu1.itb.hits                          5693555                       # DTB hits
+system.cpu1.itb.misses                           8207                       # DTB misses
+system.cpu1.itb.accesses                      5701762                       # DTB accesses
+system.cpu1.numCycles                       237058963                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles          14488159                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts                      45028124                       # Number of instructions fetch has processed
-system.cpu1.fetch.Branches                    7344792                       # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches           4479369                       # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles                      9950354                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles                2325910                       # Number of cycles fetch has spent squashing
-system.cpu1.fetch.TlbCycles                     82893                       # Number of cycles fetch has spent waiting for tlb
-system.cpu1.fetch.BlockedCycles              46948697                       # Number of cycles fetch has spent blocked
-system.cpu1.fetch.MiscStallCycles                1099                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingDrainCycles             1893                       # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu1.fetch.PendingTrapStallCycles        45519                       # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles      1268155                       # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles          161                       # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines                  5681743                       # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes               353393                       # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.ItlbSquashes                   2950                       # Number of outstanding ITLB misses that were squashed
-system.cpu1.fetch.rateDist::samples          74402978                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean             0.748631                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev            2.104884                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.icacheStallCycles          15389347                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts                      44896719                       # Number of instructions fetch has processed
+system.cpu1.fetch.Branches                    8288231                       # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches           4939107                       # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles                    217242159                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles                 949095                       # Number of cycles fetch has spent squashing
+system.cpu1.fetch.TlbCycles                    106364                       # Number of cycles fetch has spent waiting for tlb
+system.cpu1.fetch.MiscStallCycles                1987                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingDrainCycles             1943                       # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu1.fetch.PendingTrapStallCycles        92979                       # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles      2091650                       # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles          112                       # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines                  5690360                       # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes               215494                       # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.ItlbSquashes                   3361                       # Number of outstanding ITLB misses that were squashed
+system.cpu1.fetch.rateDist::samples         235400962                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean             0.228809                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev            1.188674                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0                64461074     86.64%     86.64% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1                  633258      0.85%     87.49% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2                  845202      1.14%     88.62% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3                 1118143      1.50%     90.13% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4                 1030578      1.39%     91.51% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5                  551741      0.74%     92.25% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6                 1296054      1.74%     94.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7                  370486      0.50%     94.49% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8                 4096442      5.51%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0               225085908     95.62%     95.62% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1                  947634      0.40%     96.02% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2                 1047135      0.44%     96.47% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3                 1048515      0.45%     96.91% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4                 1240998      0.53%     97.44% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5                  829745      0.35%     97.79% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6                 1296822      0.55%     98.34% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7                  452969      0.19%     98.53% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8                 3451236      1.47%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total            74402978                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate                 0.031147                       # Number of branch fetches per cycle
-system.cpu1.fetch.rate                       0.190949                       # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles                15290128                       # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles             48029788                       # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles                  9010807                       # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles               535995                       # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles               1534066                       # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved              962796                       # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred                84486                       # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts              53087117                       # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts               281620                       # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles               1534066                       # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles                16089413                       # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles                6996685                       # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles      28422508                       # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles                  8819964                       # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles             12538212                       # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts              50579819                       # Number of instructions processed by rename
-system.cpu1.rename.ROBFullEvents                  715                       # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents               8590875                       # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LQFullEvents               9852379                       # Number of times rename has blocked due to LQ full
-system.cpu1.rename.SQFullEvents               1395671                       # Number of times rename has blocked due to SQ full
-system.cpu1.rename.FullRegisterEvents            1301                       # Number of times there has been no free registers
-system.cpu1.rename.RenamedOperands           52976488                       # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups            233969396                       # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups       213834273                       # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups             5207                       # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps             38971918                       # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps                14004569                       # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts            583497                       # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts        540607                       # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts                  5363476                       # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads             9768473                       # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores            6353478                       # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads           903299                       # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores         1144541                       # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded                  47001226                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded             985413                       # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued                 60595640                       # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued            98989                       # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined        9593116                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined     24473464                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved        250944                       # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples     74402978                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean        0.814425                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev       1.533021                       # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::total           235400962                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate                 0.034963                       # Number of branch fetches per cycle
+system.cpu1.fetch.rate                       0.189391                       # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles                12590716                       # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles            214453384                       # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles                  6500032                       # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles              1465156                       # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles                389454                       # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved             1047596                       # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred                86470                       # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts              48240012                       # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts               288766                       # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles                389454                       # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles                13272686                       # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles               54002992                       # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles      31282477                       # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles                  7201814                       # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles            129249426                       # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts              46761611                       # Number of instructions processed by rename
+system.cpu1.rename.ROBFullEvents                 1258                       # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents              95572539                       # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LQFullEvents             124561907                       # Number of times rename has blocked due to LQ full
+system.cpu1.rename.SQFullEvents               2450017                       # Number of times rename has blocked due to SQ full
+system.cpu1.rename.RenamedOperands           49620172                       # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups            215588900                       # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups        57377506                       # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups             4944                       # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps             39615169                       # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps                10004995                       # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts            609511                       # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts        515718                       # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts                  8221045                       # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads             8459299                       # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores            6818667                       # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads          1033426                       # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores         1557443                       # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded                  44314605                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded            1045489                       # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued                 62743783                       # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued            61525                       # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined        7205140                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined     16025571                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved        281591                       # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples    235400962                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean        0.266540                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev       0.981476                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0           52794785     70.96%     70.96% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1            6823804      9.17%     80.13% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2            3272663      4.40%     84.53% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3            2786608      3.75%     88.27% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4            6272134      8.43%     96.70% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5            1319081      1.77%     98.48% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::6             820611      1.10%     99.58% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::7             247257      0.33%     99.91% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::8              66035      0.09%    100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0          213793871     90.82%     90.82% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1            6637383      2.82%     93.64% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2            3199231      1.36%     95.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3            2579548      1.10%     96.10% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4            6422119      2.73%     98.82% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5            1152982      0.49%     99.31% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::6            1001630      0.43%     99.74% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::7             407456      0.17%     99.91% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::8             206742      0.09%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total       74402978                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total      235400962                       # Number of insts issued each cycle
 system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu                  29526      0.66%      0.66% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult                     4      0.00%      0.66% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv                      0      0.00%      0.66% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      0.66% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      0.66% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      0.66% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult                   0      0.00%      0.66% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      0.66% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      0.66% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      0.66% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      0.66% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      0.66% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      0.66% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      0.66% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      0.66% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult                    0      0.00%      0.66% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      0.66% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift                   0      0.00%      0.66% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      0.66% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      0.66% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      0.66% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      0.66% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      0.66% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      0.66% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      0.66% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      0.66% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      0.66% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      0.66% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      0.66% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead               4196905     94.38%     95.05% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite               220217      4.95%    100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu                 146491      2.81%      2.81% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult                     1      0.00%      2.81% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv                      0      0.00%      2.81% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      2.81% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      2.81% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      2.81% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult                   0      0.00%      2.81% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      2.81% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      2.81% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      2.81% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      2.81% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      2.81% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      2.81% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      2.81% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      2.81% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult                    0      0.00%      2.81% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      2.81% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift                   0      0.00%      2.81% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      2.81% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      2.81% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      2.81% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      2.81% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      2.81% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      2.81% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      2.81% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      2.81% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      2.81% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      2.81% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      2.81% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead               4788852     91.80%     94.61% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite               281237      5.39%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu1.iq.FU_type_0::No_OpClass            13541      0.02%      0.02% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu             28679065     47.33%     47.35% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult               45344      0.07%     47.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     47.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     47.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     47.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     47.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     47.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     47.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     47.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     47.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     47.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     47.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     47.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     47.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc                 13      0.00%     47.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     47.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     47.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     47.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc              9      0.00%     47.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     47.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     47.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     47.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     47.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     47.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     47.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc           858      0.00%     47.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     47.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc            9      0.00%     47.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     47.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead            26009717     42.92%     90.35% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite            5847084      9.65%    100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::No_OpClass            13506      0.02%      0.02% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu             27516436     43.86%     43.88% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult               46370      0.07%     43.95% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     43.95% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     43.95% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     43.95% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     43.95% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     43.95% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     43.95% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     43.95% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     43.95% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     43.95% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     43.95% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     43.95% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     43.95% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     43.95% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     43.95% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     43.95% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     43.95% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     43.95% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     43.95% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     43.95% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     43.95% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     43.95% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     43.95% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     43.95% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc          1209      0.00%     43.95% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     43.95% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     43.95% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     43.95% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead            28654021     45.67%     89.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite            6512241     10.38%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total              60595640                       # Type of FU issued
-system.cpu1.iq.rate                          0.256966                       # Inst issue rate
-system.cpu1.iq.fu_busy_cnt                    4446652                       # FU busy when requested
-system.cpu1.iq.fu_busy_rate                  0.073382                       # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads         200172970                       # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes         57588554                       # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses     41991709                       # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads              11520                       # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes              6240                       # Number of floating instruction queue writes
-system.cpu1.iq.fp_inst_queue_wakeup_accesses         4992                       # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses              65022566                       # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses                   6185                       # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads          323560                       # Number of loads that had data forwarded from stores
+system.cpu1.iq.FU_type_0::total              62743783                       # Type of FU issued
+system.cpu1.iq.rate                          0.264676                       # Inst issue rate
+system.cpu1.iq.fu_busy_cnt                    5216581                       # FU busy when requested
+system.cpu1.iq.fu_busy_rate                  0.083141                       # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads         366155152                       # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes         52582376                       # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses     41291326                       # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads              11482                       # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_writes              6074                       # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_wakeup_accesses         5054                       # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.int_alu_accesses              67940659                       # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses                   6199                       # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads          226253                       # Number of loads that had data forwarded from stores
 system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads      2067890                       # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses         2468                       # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation        15600                       # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores       783792                       # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads      1460814                       # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses         2639                       # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation        24306                       # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores       652998                       # Number of stores squashed
 system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads     16950409                       # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked       331839                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread0.rescheduledLoads     17101900                       # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked      3881798                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles               1534066                       # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles                5578937                       # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles               735039                       # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts           48101549                       # Number of instructions dispatched to IQ
-system.cpu1.iew.iewDispSquashedInsts            89840                       # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts              9768473                       # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts             6353478                       # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts            710230                       # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents                138266                       # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents               531900                       # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents         15600                       # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect        167974                       # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect       132221                       # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts              300195                       # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts             59563474                       # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts             25690610                       # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts          1032166                       # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewSquashCycles                389454                       # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles               50160792                       # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles              3093797                       # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts           45494090                       # Number of instructions dispatched to IQ
+system.cpu1.iew.iewDispSquashedInsts            85835                       # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispLoadInsts              8459299                       # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts             6818667                       # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts            741438                       # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents                149727                       # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents              2862513                       # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents         24306                       # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect        166054                       # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect       139765                       # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts              305819                       # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts             62318890                       # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts             28486625                       # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts           369994                       # Number of squashed instructions skipped in execute
 system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu1.iew.exec_nop                       114910                       # number of nop insts executed
-system.cpu1.iew.exec_refs                    31485549                       # number of memory reference insts executed
-system.cpu1.iew.exec_branches                 5840798                       # Number of branches executed
-system.cpu1.iew.exec_stores                   5794939                       # Number of stores executed
-system.cpu1.iew.exec_rate                    0.252589                       # Inst execution rate
-system.cpu1.iew.wb_sent                      59096440                       # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count                     41996701                       # cumulative count of insts written-back
-system.cpu1.iew.wb_producers                 23719594                       # num instructions producing a value
-system.cpu1.iew.wb_consumers                 43668575                       # num instructions consuming a value
+system.cpu1.iew.exec_nop                       133996                       # number of nop insts executed
+system.cpu1.iew.exec_refs                    34929125                       # number of memory reference insts executed
+system.cpu1.iew.exec_branches                 6064585                       # Number of branches executed
+system.cpu1.iew.exec_stores                   6442500                       # Number of stores executed
+system.cpu1.iew.exec_rate                    0.262884                       # Inst execution rate
+system.cpu1.iew.wb_sent                      58464614                       # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count                     41296380                       # cumulative count of insts written-back
+system.cpu1.iew.wb_producers                 23329556                       # num instructions producing a value
+system.cpu1.iew.wb_consumers                 41830645                       # num instructions consuming a value
 system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu1.iew.wb_rate                      0.178094                       # insts written-back per cycle
-system.cpu1.iew.wb_fanout                    0.543173                       # average fanout of values written-back
+system.cpu1.iew.wb_rate                      0.174203                       # insts written-back per cycle
+system.cpu1.iew.wb_fanout                    0.557714                       # average fanout of values written-back
 system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.commit.commitSquashedInsts        9469311                       # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls         734469                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts           259123                       # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples     72868911                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean     0.524128                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev     1.502288                       # Number of insts commited each cycle
+system.cpu1.commit.commitSquashedInsts        7169441                       # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls         763898                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts           257160                       # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples    234250313                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean     0.162130                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev     0.884909                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0     58802570     80.70%     80.70% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1      7335717     10.07%     90.76% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2      1834357      2.52%     93.28% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3      1110131      1.52%     94.80% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4       806352      1.11%     95.91% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5       478738      0.66%     96.57% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6       708592      0.97%     97.54% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7       352493      0.48%     98.02% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8      1439961      1.98%    100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0    220821840     94.27%     94.27% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1      6746509      2.88%     97.15% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2      1771690      0.76%     97.90% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3      1085849      0.46%     98.37% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4       731494      0.31%     98.68% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5       648369      0.28%     98.96% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6       505518      0.22%     99.17% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7       281725      0.12%     99.29% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8      1657319      0.71%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total     72868911                       # Number of insts commited each cycle
-system.cpu1.commit.committedInsts            30042313                       # Number of instructions committed
-system.cpu1.commit.committedOps              38192613                       # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total    234250313                       # Number of insts commited each cycle
+system.cpu1.commit.committedInsts            31416794                       # Number of instructions committed
+system.cpu1.commit.committedOps              37978992                       # Number of ops (including micro ops) committed
 system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu1.commit.refs                      13270269                       # Number of memory references committed
-system.cpu1.commit.loads                      7700583                       # Number of loads committed
-system.cpu1.commit.membars                     192827                       # Number of memory barriers committed
-system.cpu1.commit.branches                   5091642                       # Number of branches committed
-system.cpu1.commit.fp_insts                      4942                       # Number of committed floating point instructions.
-system.cpu1.commit.int_insts                 33962282                       # Number of committed integer instructions.
-system.cpu1.commit.function_calls              485556                       # Number of function calls committed.
+system.cpu1.commit.refs                      13164154                       # Number of memory references committed
+system.cpu1.commit.loads                      6998485                       # Number of loads committed
+system.cpu1.commit.membars                     211048                       # Number of memory barriers committed
+system.cpu1.commit.branches                   5351716                       # Number of branches committed
+system.cpu1.commit.fp_insts                      5038                       # Number of committed floating point instructions.
+system.cpu1.commit.int_insts                 33506635                       # Number of committed integer instructions.
+system.cpu1.commit.function_calls              519749                       # Number of function calls committed.
 system.cpu1.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntAlu        24878693     65.14%     65.14% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntMult          42793      0.11%     65.25% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntDiv               0      0.00%     65.25% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     65.25% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     65.25% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     65.25% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatMult            0      0.00%     65.25% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     65.25% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     65.25% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     65.25% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     65.25% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     65.25% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     65.25% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     65.25% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     65.25% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMult             0      0.00%     65.25% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     65.25% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShift            0      0.00%     65.25% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     65.25% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     65.25% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     65.25% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     65.25% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     65.25% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     65.25% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     65.25% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMisc          858      0.00%     65.25% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     65.25% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     65.25% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     65.25% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemRead        7700583     20.16%     85.42% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemWrite       5569686     14.58%    100.00% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntAlu        24770094     65.22%     65.22% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntMult          43535      0.11%     65.34% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntDiv               0      0.00%     65.34% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     65.34% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     65.34% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     65.34% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatMult            0      0.00%     65.34% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     65.34% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     65.34% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     65.34% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     65.34% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     65.34% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     65.34% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     65.34% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     65.34% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMult             0      0.00%     65.34% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     65.34% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShift            0      0.00%     65.34% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     65.34% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     65.34% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     65.34% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     65.34% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     65.34% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     65.34% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     65.34% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMisc         1209      0.00%     65.34% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     65.34% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     65.34% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     65.34% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemRead        6998485     18.43%     83.77% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemWrite       6165669     16.23%    100.00% # Class of committed instruction
 system.cpu1.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::total         38192613                       # Class of committed instruction
-system.cpu1.commit.bw_lim_events              1439961                       # number cycles where commit BW limit reached
+system.cpu1.commit.op_class_0::total         37978992                       # Class of committed instruction
+system.cpu1.commit.bw_lim_events              1657319                       # number cycles where commit BW limit reached
 system.cpu1.commit.bw_limited                       0                       # number of insts not committed due to BW limits
-system.cpu1.rob.rob_reads                   118199712                       # The number of ROB reads
-system.cpu1.rob.rob_writes                   96901530                       # The number of ROB writes
-system.cpu1.timesIdled                         866503                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles                      161409140                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles                  2317329341                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts                   29966199                       # Number of Instructions Simulated
-system.cpu1.committedOps                     38116499                       # Number of Ops (including micro ops) Simulated
-system.cpu1.cpi                              7.869270                       # CPI: Cycles Per Instruction
-system.cpu1.cpi_total                        7.869270                       # CPI: Total CPI of All Threads
-system.cpu1.ipc                              0.127077                       # IPC: Instructions Per Cycle
-system.cpu1.ipc_total                        0.127077                       # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads               270334360                       # number of integer regfile reads
-system.cpu1.int_regfile_writes               43344614                       # number of integer regfile writes
-system.cpu1.fp_regfile_reads                    45048                       # number of floating regfile reads
-system.cpu1.fp_regfile_writes                   42280                       # number of floating regfile writes
-system.cpu1.misc_regfile_reads              130449609                       # number of misc regfile reads
-system.cpu1.misc_regfile_writes                594503                       # number of misc regfile writes
+system.cpu1.rob.rob_reads                   276790751                       # The number of ROB reads
+system.cpu1.rob.rob_writes                   91451122                       # The number of ROB writes
+system.cpu1.timesIdled                         270857                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles                        1658001                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles                  2279071980                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.committedInsts                   31333111                       # Number of Instructions Simulated
+system.cpu1.committedOps                     37895309                       # Number of Ops (including micro ops) Simulated
+system.cpu1.cpi                              7.565765                       # CPI: Cycles Per Instruction
+system.cpu1.cpi_total                        7.565765                       # CPI: Total CPI of All Threads
+system.cpu1.ipc                              0.132174                       # IPC: Instructions Per Cycle
+system.cpu1.ipc_total                        0.132174                       # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads                71132794                       # number of integer regfile reads
+system.cpu1.int_regfile_writes               26016814                       # number of integer regfile writes
+system.cpu1.fp_regfile_reads                    44316                       # number of floating regfile reads
+system.cpu1.fp_regfile_writes                   42056                       # number of floating regfile writes
+system.cpu1.cc_regfile_reads                209312794                       # number of cc regfile reads
+system.cpu1.cc_regfile_writes                17049814                       # number of cc regfile writes
+system.cpu1.misc_regfile_reads              299103919                       # number of misc regfile reads
+system.cpu1.misc_regfile_writes                609097                       # number of misc regfile writes
 system.iocache.tags.replacements                    0                       # number of replacements
 system.iocache.tags.tagsinuse                       0                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
@@ -2125,17 +2120,17 @@ system.iocache.avg_blocked_cycles::no_mshrs          nan                       #
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1734330533049                       # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1734330533049                       # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1734330533049                       # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1734330533049                       # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1732377463327                       # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1732377463327                       # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1732377463327                       # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1732377463327                       # number of overall MSHR uncacheable cycles
 system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average ReadReq mshr uncacheable latency
 system.iocache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average overall mshr uncacheable latency
 system.iocache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                   83063                       # number of quiesce instructions executed
+system.cpu0.kern.inst.quiesce                   83365                       # number of quiesce instructions executed
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
 
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt
index cce768d16..936db738a 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt
@@ -1,16 +1,16 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.631271                       # Number of seconds simulated
-sim_ticks                                2631271319500                       # Number of ticks simulated
-final_tick                               2631271319500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.626162                       # Number of seconds simulated
+sim_ticks                                2626161554000                       # Number of ticks simulated
+final_tick                               2626161554000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 354699                       # Simulator instruction rate (inst/s)
-host_op_rate                                   451347                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            15499898557                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 465856                       # Number of bytes of host memory used
-host_seconds                                   169.76                       # Real time elapsed on the host
-sim_insts                                    60213853                       # Number of instructions simulated
-sim_ops                                      76620850                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 476066                       # Simulator instruction rate (inst/s)
+host_op_rate                                   568569                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            20761634862                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 472496                       # Number of bytes of host memory used
+host_seconds                                   126.49                       # Real time elapsed on the host
+sim_insts                                    60218144                       # Number of instructions simulated
+sim_ops                                      71918894                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.realview.nvmem.bytes_read::cpu0.inst           20                       # Number of bytes read from this memory
@@ -27,134 +27,134 @@ system.realview.nvmem.bw_total::cpu0.inst            8                       # T
 system.realview.nvmem.bw_total::total               8                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bytes_read::realview.clcd    124256256                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.itb.walker          128                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst           299528                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data          4518680                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst           306888                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data          4490328                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu1.dtb.walker           64                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           404800                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data          4542464                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            134021920                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       299528                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       404800                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          704328                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      3690624                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0.data       1524152                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1.data       1491920                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           6706696                       # Number of bytes written to this memory
+system.physmem.bytes_read::cpu1.inst           399040                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data          4560448                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            134013152                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       306888                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       399040                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          705928                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      3677952                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0.data       1536620                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1.data       1479452                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           6694024                       # Number of bytes written to this memory
 system.physmem.num_reads::realview.clcd      15532032                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu0.itb.walker            2                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             10892                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data             70640                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             11007                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data             70187                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu1.dtb.walker            1                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              6325                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data             70976                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total              15690868                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           57666                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0.data           381038                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1.data           372980                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               811684                       # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd        47222898                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_reads::cpu1.inst              6235                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data             71257                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total              15690721                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           57468                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0.data           384155                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu1.data           369863                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               811486                       # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd        47314780                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu0.itb.walker            49                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst              113834                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data             1717299                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst              116858                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data             1709845                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu1.dtb.walker            24                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst              153842                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data             1726338                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                50934284                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         113834                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst         153842                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             267676                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1402601                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data             579245                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data             566996                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2548842                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1402601                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd       47222898                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst              151948                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data             1736545                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                51030049                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         116858                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst         151948                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             268806                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1400505                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data             585120                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1.data             563351                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                2548976                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1400505                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd       47314780                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.itb.walker           49                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             113834                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data            2296545                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             116858                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data            2294965                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu1.dtb.walker           24                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst             153842                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data            2293334                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               53483126                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                      15690868                       # Number of read requests accepted
-system.physmem.writeReqs                       811684                       # Number of write requests accepted
-system.physmem.readBursts                    15690868                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     811684                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM               1004214848                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                       704                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   6724608                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                 134021920                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                6706696                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                       11                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                  706598                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs           4517                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0              980391                       # Per bank write bursts
-system.physmem.perBankRdBursts::1              980206                       # Per bank write bursts
-system.physmem.perBankRdBursts::2              980222                       # Per bank write bursts
-system.physmem.perBankRdBursts::3              980428                       # Per bank write bursts
-system.physmem.perBankRdBursts::4              986950                       # Per bank write bursts
-system.physmem.perBankRdBursts::5              980708                       # Per bank write bursts
-system.physmem.perBankRdBursts::6              980611                       # Per bank write bursts
-system.physmem.perBankRdBursts::7              980420                       # Per bank write bursts
-system.physmem.perBankRdBursts::8              980615                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              980431                       # Per bank write bursts
-system.physmem.perBankRdBursts::10             979815                       # Per bank write bursts
-system.physmem.perBankRdBursts::11             979544                       # Per bank write bursts
-system.physmem.perBankRdBursts::12             980153                       # Per bank write bursts
-system.physmem.perBankRdBursts::13             980076                       # Per bank write bursts
-system.physmem.perBankRdBursts::14             980177                       # Per bank write bursts
-system.physmem.perBankRdBursts::15             980110                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                6626                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                6496                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                6497                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                6558                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                6634                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                6937                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                6920                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                6772                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                6893                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                6718                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               6212                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               6014                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               6499                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               6274                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               6516                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               6506                       # Per bank write bursts
+system.physmem.bw_total::cpu1.inst             151948                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data            2299897                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               53579025                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                      15690721                       # Number of read requests accepted
+system.physmem.writeReqs                       811486                       # Number of write requests accepted
+system.physmem.readBursts                    15690721                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     811486                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM               1004205504                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                       640                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   6711360                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                 134013152                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                6694024                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                       10                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                  706602                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs           4522                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0              980414                       # Per bank write bursts
+system.physmem.perBankRdBursts::1              980046                       # Per bank write bursts
+system.physmem.perBankRdBursts::2              979991                       # Per bank write bursts
+system.physmem.perBankRdBursts::3              980262                       # Per bank write bursts
+system.physmem.perBankRdBursts::4              986671                       # Per bank write bursts
+system.physmem.perBankRdBursts::5              980424                       # Per bank write bursts
+system.physmem.perBankRdBursts::6              980568                       # Per bank write bursts
+system.physmem.perBankRdBursts::7              980428                       # Per bank write bursts
+system.physmem.perBankRdBursts::8              980784                       # Per bank write bursts
+system.physmem.perBankRdBursts::9              980432                       # Per bank write bursts
+system.physmem.perBankRdBursts::10             979731                       # Per bank write bursts
+system.physmem.perBankRdBursts::11             979594                       # Per bank write bursts
+system.physmem.perBankRdBursts::12             980346                       # Per bank write bursts
+system.physmem.perBankRdBursts::13             980257                       # Per bank write bursts
+system.physmem.perBankRdBursts::14             980396                       # Per bank write bursts
+system.physmem.perBankRdBursts::15             980367                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                6649                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                6328                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                6318                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                6427                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                6389                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                6673                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                6856                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                6766                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                7040                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                6684                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               6144                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               6041                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               6664                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               6480                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               6708                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               6698                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    2631266900000                       # Total gap between requests
+system.physmem.totGap                    2626157242500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::2                    6664                       # Read request sizes (log2)
-system.physmem.readPktSize::3                15532032                       # Read request sizes (log2)
+system.physmem.readPktSize::2                    6644                       # Read request sizes (log2)
+system.physmem.readPktSize::3                15532042                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  152172                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  152035                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                 754018                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                  57666                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                   1139961                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    982153                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                    987606                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                   1093203                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                    997403                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                   1062031                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                   2774379                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                   2684271                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                   3510460                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                    111897                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                   101929                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                    96137                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                    92760                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                    19230                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                    18784                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                    18633                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                       20                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                  57468                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                   1139192                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    982322                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                    987642                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                   1099516                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                    997956                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                   1065450                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                   2766854                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                   2672571                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                   3490866                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                    121692                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                   109210                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                   101989                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                    98650                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                    19380                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                    18786                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                    18596                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                       38                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                        1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
@@ -169,39 +169,39 @@ system.physmem.rdQLenPdf::28                        0                       # Wh
 system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                       363                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1                       356                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                       352                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                       346                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                       342                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                       339                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                       339                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                       337                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                       334                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                       329                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10                      326                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                      323                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12                      318                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0                       352                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1                       350                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2                       347                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3                       343                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4                       338                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5                       333                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6                       331                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7                       328                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8                       328                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9                       323                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10                      320                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11                      318                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12                      317                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                      316                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                      313                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     4037                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     4046                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     5873                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     5848                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     5837                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     5822                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     5807                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     5788                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     5769                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     5755                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     5749                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     5727                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     5704                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     5685                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     5667                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     5659                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     5646                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     5634                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14                      315                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     3909                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     3896                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     5890                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     5873                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     5857                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     5833                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     5813                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     5801                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     5781                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     5767                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     5740                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     5719                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     5709                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     5701                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     5681                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     5668                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     5649                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     5638                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
@@ -233,350 +233,349 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples      1040545                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      971.548041                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     905.383017                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     204.411888                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          22983      2.21%      2.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        22832      2.19%      4.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         9281      0.89%      5.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         2277      0.22%      5.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2320      0.22%      5.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1623      0.16%      5.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         9470      0.91%      6.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          703      0.07%      6.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151       969056     93.13%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total        1040545                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          6005                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean      2612.962531                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev    47489.703553                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-65535          5977     99.53%     99.53% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::131072-196607           11      0.18%     99.72% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::196608-262143            3      0.05%     99.77% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::393216-458751            2      0.03%     99.80% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::589824-655359            3      0.05%     99.85% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::786432-851967            1      0.02%     99.87% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::983040-1.04858e+06            1      0.02%     99.88% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1.17965e+06-1.24518e+06            6      0.10%     99.98% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples      1040256                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      971.796235                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     905.926694                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     203.945376                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          22813      2.19%      2.19% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        22914      2.20%      4.40% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         8969      0.86%      5.26% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         2415      0.23%      5.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2270      0.22%      5.71% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1819      0.17%      5.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         9086      0.87%      6.76% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          877      0.08%      6.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151       969093     93.16%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total        1040256                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          5997                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean      2616.425880                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev    48628.845120                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-65535          5973     99.60%     99.60% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::131072-196607            7      0.12%     99.72% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::196608-262143            4      0.07%     99.78% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::393216-458751            2      0.03%     99.82% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::589824-655359            1      0.02%     99.83% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::786432-851967            1      0.02%     99.85% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::983040-1.04858e+06            1      0.02%     99.87% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1.17965e+06-1.24518e+06            7      0.12%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::1.37626e+06-1.44179e+06            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            6005                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          6005                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        17.497419                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       17.315574                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        2.169730                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::1                   7      0.12%      0.12% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::2                   6      0.10%      0.22% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::3                   6      0.10%      0.32% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::4                   4      0.07%      0.38% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::5                   3      0.05%      0.43% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::6                   1      0.02%      0.45% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::7                   3      0.05%      0.50% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::8                   3      0.05%      0.55% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::9                   4      0.07%      0.62% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::10                  3      0.05%      0.67% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::11                  4      0.07%      0.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::12                  8      0.13%      0.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::13                  3      0.05%      0.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::14                  4      0.07%      0.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::15                 16      0.27%      1.25% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16               1890     31.47%     32.72% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17                 59      0.98%     33.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18               3765     62.70%     96.40% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19                 21      0.35%     96.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                 14      0.23%     96.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21                 16      0.27%     97.25% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22                 19      0.32%     97.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23                 20      0.33%     97.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24                 12      0.20%     98.10% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::25                  6      0.10%     98.20% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26                 23      0.38%     98.58% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::27                 21      0.35%     98.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28                 18      0.30%     99.23% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::29                 14      0.23%     99.47% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::30                 10      0.17%     99.63% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::31                 11      0.18%     99.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32                 11      0.18%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            6005                       # Writes before turning the bus around for reads
-system.physmem.totQLat                   402822623250                       # Total ticks spent queuing
-system.physmem.totMemAccLat              697026192000                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                  78454285000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       25672.44                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            5997                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          5997                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.486243                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       17.330739                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        2.155795                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::1                   3      0.05%      0.05% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::2                   3      0.05%      0.10% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::3                   4      0.07%      0.17% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::4                   5      0.08%      0.25% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::5                   8      0.13%      0.38% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::6                   1      0.02%      0.40% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::7                   4      0.07%      0.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::9                   6      0.10%      0.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::10                  3      0.05%      0.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::11                  2      0.03%      0.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::12                  3      0.05%      0.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::13                  2      0.03%      0.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::15                 11      0.18%      0.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               2055     34.27%     35.18% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17                 30      0.50%     35.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18               3613     60.25%     95.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19                 37      0.62%     96.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                 21      0.35%     96.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                 16      0.27%     97.17% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22                 14      0.23%     97.40% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23                 18      0.30%     97.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24                 13      0.22%     97.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25                 29      0.48%     98.40% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26                 18      0.30%     98.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::27                 15      0.25%     98.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28                  9      0.15%     99.10% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::29                 11      0.18%     99.28% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::30                 15      0.25%     99.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::31                 16      0.27%     99.80% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32                 11      0.18%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::33                  1      0.02%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            5997                       # Writes before turning the bus around for reads
+system.physmem.totQLat                   404022182250                       # Total ticks spent queuing
+system.physmem.totMemAccLat              698223013500                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                  78453555000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       25749.13                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  44422.44                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         381.65                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  44499.13                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         382.39                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           2.56                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       50.93                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       51.03                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        2.55                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           3.00                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       2.98                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                           3.01                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       2.99                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         6.85                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        14.68                       # Average write queue length when enqueuing
-system.physmem.readRowHits                   14667283                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     88101                       # Number of row buffer hits during writes
+system.physmem.avgRdQLen                         6.57                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        16.75                       # Average write queue length when enqueuing
+system.physmem.readRowHits                   14667428                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     87892                       # Number of row buffer hits during writes
 system.physmem.readRowHitRate                   93.48                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  83.84                       # Row buffer hit rate for writes
-system.physmem.avgGap                       159446.06                       # Average gap between requests
+system.physmem.writeRowHitRate                  83.80                       # Row buffer hit rate for writes
+system.physmem.avgGap                       159139.76                       # Average gap between requests
 system.physmem.pageHitRate                      93.41                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE     2257272287500                       # Time in different power states
-system.physmem.memoryStateTime::REF       87863880000                       # Time in different power states
+system.physmem.memoryStateTime::IDLE     2253794386750                       # Time in different power states
+system.physmem.memoryStateTime::REF       87693060000                       # Time in different power states
 system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT      286133845000                       # Time in different power states
+system.physmem.memoryStateTime::ACT      284666999500                       # Time in different power states
 system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.membus.throughput                     54394584                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq            16743630                       # Transaction distribution
-system.membus.trans_dist::ReadResp           16743630                       # Transaction distribution
+system.membus.throughput                     54492260                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq            16743274                       # Transaction distribution
+system.membus.trans_dist::ReadResp           16743274                       # Transaction distribution
 system.membus.trans_dist::WriteReq             763389                       # Transaction distribution
 system.membus.trans_dist::WriteResp            763389                       # Transaction distribution
-system.membus.trans_dist::Writeback             57666                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             4517                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp            4517                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            131349                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           131349                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave      2383092                       # Packet count per connected master and slave (bytes)
+system.membus.trans_dist::Writeback             57468                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq             4522                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp            4522                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            131560                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           131560                       # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave      2383096                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           10                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         3860                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio            2                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      1892408                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total      4279372                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      1891926                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total      4278894                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port     31064064                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::total     31064064                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total               35343436                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave      2390550                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count::total               35342958                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave      2390558                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port           20                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio         7720                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio            4                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port     16472360                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::total     18870654                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port     16450920                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::total     18849222                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port    124256256                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.iocache.mem_side::total    124256256                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total           143126910                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus              143126910                       # Total data (bytes)
+system.membus.tot_pkt_size::total           143105478                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus              143105478                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy          1225776000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy          1225841000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy                5000                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             3753500                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             3816000                       # Layer occupancy (ticks)
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 system.membus.reqLayer6.utilization               0.7                       # Layer utilization (%)
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 system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
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 system.membus.respLayer2.utilization              1.5                       # Layer utilization (%)
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-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.989885                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.992318                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.991081                       # miss rate for UpgradeReq accesses
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-system.l2c.ReadReq_avg_miss_latency::cpu0.inst 70201.125176                       # average ReadReq miss latency
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-system.l2c.demand_avg_miss_latency::cpu1.inst 69810.988142                       # average overall miss latency
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-system.l2c.overall_avg_miss_latency::cpu0.inst 70201.125176                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 69904.184824                       # average overall miss latency
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 system.l2c.overall_avg_miss_latency::cpu1.dtb.walker        89250                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 69810.988142                       # average overall miss latency
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 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -585,127 +584,127 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks               57666                       # number of writebacks
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 system.l2c.ReadReq_mshr_misses::cpu0.itb.walker            2                       # number of ReadReq MSHR misses
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+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   3862282315                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total   7556765895                       # number of ReadExReq MSHR miss cycles
 system.l2c.demand_mshr_miss_latency::cpu0.itb.walker       125000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.inst    245455500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.data   4081898078                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.inst    254926750                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.data   4038177830                       # number of demand (read+write) MSHR miss cycles
 system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker        76250                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst    361377500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data   4102621300                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total   8791553628                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst    356241750                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data   4131173815                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total   8780721395                       # number of demand (read+write) MSHR miss cycles
 system.l2c.overall_mshr_miss_latency::cpu0.itb.walker       125000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.inst    245455500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.data   4081898078                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.inst    254926750                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.data   4038177830                       # number of overall MSHR miss cycles
 system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker        76250                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst    361377500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data   4102621300                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total   8791553628                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst    349718500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data  83155205750                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data  83528725500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total 167033649750                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   8440426101                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   8262522003                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total  16702948104                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.inst    349718500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data  91595631851                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data  91791247503                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total 183736597854                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.000546                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.010094                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.027322                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.000102                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.014626                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.026407                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.016488                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.989885                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.992318                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.991081                       # mshr miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.533876                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.540653                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.537259                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.000546                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.010094                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.225664                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.000102                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.014626                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.230301                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.101826                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.000546                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.010094                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.225664                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.000102                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.014626                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.230301                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.101826                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_latency::cpu1.inst    356241750                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data   4131173815                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total   8780721395                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst    349507750                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data  83968607250                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data  82715661500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total 167033776500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   8327021074                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   8376108487                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total  16703129561                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.inst    349507750                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data  92295628324                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data  91091769987                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total 183736906061                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.000571                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.009392                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.028594                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.000100                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.016037                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.023110                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.016217                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.989496                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.992542                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.991044                       # mshr miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.519633                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.556560                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.537780                       # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.000571                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.009392                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.222187                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.000100                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.016037                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.233432                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.101756                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.000571                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.009392                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.222187                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.000100                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.016037                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.233432                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.101756                       # mshr miss rate for overall accesses
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker        62500                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 57537.623066                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 61362.314709                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 58189.169139                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 62105.936032                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker        76250                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 57134.782609                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 62978.457822                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 59680.965759                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 57135.805934                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 62214.599722                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 59778.046398                       # average ReadReq mshr miss latency
 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data        10001                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10003.814919                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10002.384562                       # average UpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 56810.083092                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 56725.999491                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 56767.838634                       # average ReadExReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001.341530                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10001.173792                       # average UpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 56443.107173                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 57007.857048                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 56730.347172                       # average ReadExReq mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker        62500                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 57537.623066                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 57145.430183                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 58189.169139                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 56884.557185                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker        76250                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 57134.782609                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 57158.678388                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 57162.247256                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 57135.805934                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 57320.094003                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 57136.396376                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker        62500                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 57537.623066                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 57145.430183                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 58189.169139                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 56884.557185                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker        76250                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 57134.782609                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 57158.678388                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 57162.247256                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 57135.805934                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 57320.094003                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 57136.396376                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
@@ -724,47 +723,47 @@ system.cf0.dma_read_txs                             0                       # Nu
 system.cf0.dma_write_full_pages                     0                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                          0                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
-system.toL2Bus.throughput                    52759012                       # Throughput (bytes/s)
-system.toL2Bus.trans_dist::ReadReq            2471877                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           2471877                       # Transaction distribution
+system.toL2Bus.throughput                    52868072                       # Throughput (bytes/s)
+system.toL2Bus.trans_dist::ReadReq            2471434                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp           2471434                       # Transaction distribution
 system.toL2Bus.trans_dist::WriteReq            763389                       # Transaction distribution
 system.toL2Bus.trans_dist::WriteResp           763389                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback           596476                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq            2915                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp           2915                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           247510                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          247510                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      1725028                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      5753762                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side        20291                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        50582                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               7549663                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     54751132                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     83793442                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side        28936                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        79664                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size::total          138653174                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.data_through_bus             138653174                       # Total data (bytes)
-system.toL2Bus.snoop_data_through_bus          170100                       # Total snoop data (bytes)
-system.toL2Bus.reqLayer0.occupancy         4808682000                       # Layer occupancy (ticks)
+system.toL2Bus.trans_dist::Writeback           596521                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq            2903                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp           2903                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq           247694                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp          247694                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      1725408                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      5753877                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side        20010                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        49988                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total               7549283                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     54763036                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     83799850                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side        28424                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        78676                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size::total          138669986                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.data_through_bus             138669986                       # Total data (bytes)
+system.toL2Bus.snoop_data_through_bus          170112                       # Total snoop data (bytes)
+system.toL2Bus.reqLayer0.occupancy         4808749000                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.2                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy        3865303000                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy        3866196743                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy        4420412121                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy        4420580083                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.2                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy          13057000                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy          12904000                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy          30666250                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy          30319250                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
-system.iobus.throughput                      48131413                       # Throughput (bytes/s)
-system.iobus.trans_dist::ReadReq             16715394                       # Transaction distribution
-system.iobus.trans_dist::ReadResp            16715394                       # Transaction distribution
+system.iobus.throughput                      48225066                       # Throughput (bytes/s)
+system.iobus.trans_dist::ReadReq             16715396                       # Transaction distribution
+system.iobus.trans_dist::ReadResp            16715396                       # Transaction distribution
 system.iobus.trans_dist::WriteReq                8184                       # Transaction distribution
 system.iobus.trans_dist::WriteResp               8184                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        30038                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio         7946                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio         7948                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio          536                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio         1042                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio         1044                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio           36                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          746                       # Packet count per connected master and slave (bytes)
@@ -784,14 +783,14 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total      2383092                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total      2383096                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side     31064064                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.clcd.dma::total     31064064                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                33447156                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                33447160                       # Packet count per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio        39333                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio        15892                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio        15896                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio         1072                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio         2084                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio         2088                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio           72                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio          397                       # Cumulative packet size per connected master and slave (bytes)
@@ -811,18 +810,18 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::total      2390550                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::total      2390558                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side    124256256                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.realview.clcd.dma::total    124256256                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::total            126646806                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.data_through_bus               126646806                       # Total data (bytes)
+system.iobus.tot_pkt_size::total            126646814                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.data_through_bus               126646814                       # Total data (bytes)
 system.iobus.reqLayer0.occupancy             21111000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy              3978000                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy              3979000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer2.occupancy               536000                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy               527000                       # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy               528000                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer4.occupancy                27000                       # Layer occupancy (ticks)
 system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
@@ -864,9 +863,9 @@ system.iobus.reqLayer23.occupancy                8000                       # La
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer25.occupancy         15532032000                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.6                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy          2374908000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy          2374912000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.1                       # Layer utilization (%)
-system.iobus.respLayer1.occupancy         39139813250                       # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy         39164946750                       # Layer occupancy (ticks)
 system.iobus.respLayer1.utilization               1.5                       # Layer utilization (%)
 system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
@@ -891,25 +890,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # D
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                     7447963                       # DTB read hits
-system.cpu0.dtb.read_misses                      7119                       # DTB read misses
-system.cpu0.dtb.write_hits                    5549645                       # DTB write hits
-system.cpu0.dtb.write_misses                     1815                       # DTB write misses
-system.cpu0.dtb.flush_tlb                        2495                       # Number of times complete TLB was flushed
+system.cpu0.dtb.read_hits                     6652404                       # DTB read hits
+system.cpu0.dtb.read_misses                      6867                       # DTB read misses
+system.cpu0.dtb.write_hits                    5702862                       # DTB write hits
+system.cpu0.dtb.write_misses                     1758                       # DTB write misses
+system.cpu0.dtb.flush_tlb                        2489                       # Number of times complete TLB was flushed
 system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid                725                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid                     29                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                    6552                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.flush_tlb_mva_asid                727                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid                     33                       # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries                    6327                       # Number of entries that have been flushed from TLB
 system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                   134                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.prefetch_faults                   129                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                      230                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                 7455082                       # DTB read accesses
-system.cpu0.dtb.write_accesses                5551460                       # DTB write accesses
+system.cpu0.dtb.perms_faults                      214                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses                 6659271                       # DTB read accesses
+system.cpu0.dtb.write_accesses                5704620                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                         12997608                       # DTB hits
-system.cpu0.dtb.misses                           8934                       # DTB misses
-system.cpu0.dtb.accesses                     13006542                       # DTB accesses
+system.cpu0.dtb.hits                         12355266                       # DTB hits
+system.cpu0.dtb.misses                           8625                       # DTB misses
+system.cpu0.dtb.accesses                     12363891                       # DTB accesses
 system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -931,160 +930,162 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.inst_hits                    30500446                       # ITB inst hits
-system.cpu0.itb.inst_misses                      3756                       # ITB inst misses
+system.cpu0.itb.inst_hits                    30639417                       # ITB inst hits
+system.cpu0.itb.inst_misses                      3605                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
 system.cpu0.itb.write_misses                        0                       # DTB write misses
-system.cpu0.itb.flush_tlb                        2495                       # Number of times complete TLB was flushed
+system.cpu0.itb.flush_tlb                        2489                       # Number of times complete TLB was flushed
 system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid                725                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid                     29                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                    2854                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_tlb_mva_asid                727                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid                     33                       # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries                    2770                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses                30504202                       # ITB inst accesses
-system.cpu0.itb.hits                         30500446                       # DTB hits
-system.cpu0.itb.misses                           3756                       # DTB misses
-system.cpu0.itb.accesses                     30504202                       # DTB accesses
-system.cpu0.numCycles                      2629256644                       # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses                30643022                       # ITB inst accesses
+system.cpu0.itb.hits                         30639417                       # DTB hits
+system.cpu0.itb.misses                           3605                       # DTB misses
+system.cpu0.itb.accesses                     30643022                       # DTB accesses
+system.cpu0.numCycles                      2625139831                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                   29876886                       # Number of instructions committed
-system.cpu0.committedOps                     37981807                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses             34283991                       # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses                  4842                       # Number of float alu accesses
-system.cpu0.num_func_calls                    1058651                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts      3976280                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                    34283991                       # number of integer instructions
-system.cpu0.num_fp_insts                         4842                       # number of float instructions
-system.cpu0.num_int_register_reads          198984803                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes          36984019                       # number of times the integer registers were written
-system.cpu0.num_fp_register_reads                3491                       # number of times the floating registers were read
-system.cpu0.num_fp_register_writes               1354                       # number of times the floating registers were written
-system.cpu0.num_mem_refs                     13572889                       # number of memory refs
-system.cpu0.num_load_insts                    7771976                       # Number of load instructions
-system.cpu0.num_store_insts                   5800913                       # Number of store instructions
-system.cpu0.num_idle_cycles              2280913483.245505                       # Number of idle cycles
-system.cpu0.num_busy_cycles              348343160.754495                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.132487                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.867513                       # Percentage of idle cycles
-system.cpu0.Branches                          5129174                       # Number of branches fetched
-system.cpu0.op_class::No_OpClass                12846      0.03%      0.03% # Class of executed instruction
-system.cpu0.op_class::IntAlu                 24984996     64.70%     64.73% # Class of executed instruction
-system.cpu0.op_class::IntMult                   44336      0.11%     64.85% # Class of executed instruction
-system.cpu0.op_class::IntDiv                        0      0.00%     64.85% # Class of executed instruction
-system.cpu0.op_class::FloatAdd                      0      0.00%     64.85% # Class of executed instruction
-system.cpu0.op_class::FloatCmp                      0      0.00%     64.85% # Class of executed instruction
-system.cpu0.op_class::FloatCvt                      0      0.00%     64.85% # Class of executed instruction
-system.cpu0.op_class::FloatMult                     0      0.00%     64.85% # Class of executed instruction
-system.cpu0.op_class::FloatDiv                      0      0.00%     64.85% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt                     0      0.00%     64.85% # Class of executed instruction
-system.cpu0.op_class::SimdAdd                       0      0.00%     64.85% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc                    0      0.00%     64.85% # Class of executed instruction
-system.cpu0.op_class::SimdAlu                       0      0.00%     64.85% # Class of executed instruction
-system.cpu0.op_class::SimdCmp                       0      0.00%     64.85% # Class of executed instruction
-system.cpu0.op_class::SimdCvt                       0      0.00%     64.85% # Class of executed instruction
-system.cpu0.op_class::SimdMisc                      0      0.00%     64.85% # Class of executed instruction
-system.cpu0.op_class::SimdMult                      0      0.00%     64.85% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc                   0      0.00%     64.85% # Class of executed instruction
-system.cpu0.op_class::SimdShift                     0      0.00%     64.85% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc                  0      0.00%     64.85% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt                      0      0.00%     64.85% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd                  0      0.00%     64.85% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu                  0      0.00%     64.85% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp                  0      0.00%     64.85% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt                  0      0.00%     64.85% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv                  0      0.00%     64.85% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc               930      0.00%     64.85% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult                 0      0.00%     64.85% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     64.85% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     64.85% # Class of executed instruction
-system.cpu0.op_class::MemRead                 7771976     20.13%     84.98% # Class of executed instruction
-system.cpu0.op_class::MemWrite                5800913     15.02%    100.00% # Class of executed instruction
+system.cpu0.committedInsts                   30062808                       # Number of instructions committed
+system.cpu0.committedOps                     36081752                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses             32258130                       # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses                  5851                       # Number of float alu accesses
+system.cpu0.num_func_calls                    1105626                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts      3807715                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                    32258130                       # number of integer instructions
+system.cpu0.num_fp_insts                         5851                       # number of float instructions
+system.cpu0.num_int_register_reads           58404320                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes          21560333                       # number of times the integer registers were written
+system.cpu0.num_fp_register_reads                4184                       # number of times the floating registers were read
+system.cpu0.num_fp_register_writes               1670                       # number of times the floating registers were written
+system.cpu0.num_cc_register_reads           129650201                       # number of times the CC registers were read
+system.cpu0.num_cc_register_writes           14353458                       # number of times the CC registers were written
+system.cpu0.num_mem_refs                     12793226                       # number of memory refs
+system.cpu0.num_load_insts                    6826552                       # Number of load instructions
+system.cpu0.num_store_insts                   5966674                       # Number of store instructions
+system.cpu0.num_idle_cycles              2291568668.895058                       # Number of idle cycles
+system.cpu0.num_busy_cycles              333571162.104942                       # Number of busy cycles
+system.cpu0.not_idle_fraction                0.127068                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                    0.872932                       # Percentage of idle cycles
+system.cpu0.Branches                          5192489                       # Number of branches fetched
+system.cpu0.op_class::No_OpClass                12678      0.03%      0.03% # Class of executed instruction
+system.cpu0.op_class::IntAlu                 23764768     64.90%     64.94% # Class of executed instruction
+system.cpu0.op_class::IntMult                   45316      0.12%     65.06% # Class of executed instruction
+system.cpu0.op_class::IntDiv                        0      0.00%     65.06% # Class of executed instruction
+system.cpu0.op_class::FloatAdd                      0      0.00%     65.06% # Class of executed instruction
+system.cpu0.op_class::FloatCmp                      0      0.00%     65.06% # Class of executed instruction
+system.cpu0.op_class::FloatCvt                      0      0.00%     65.06% # Class of executed instruction
+system.cpu0.op_class::FloatMult                     0      0.00%     65.06% # Class of executed instruction
+system.cpu0.op_class::FloatDiv                      0      0.00%     65.06% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt                     0      0.00%     65.06% # Class of executed instruction
+system.cpu0.op_class::SimdAdd                       0      0.00%     65.06% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc                    0      0.00%     65.06% # Class of executed instruction
+system.cpu0.op_class::SimdAlu                       0      0.00%     65.06% # Class of executed instruction
+system.cpu0.op_class::SimdCmp                       0      0.00%     65.06% # Class of executed instruction
+system.cpu0.op_class::SimdCvt                       0      0.00%     65.06% # Class of executed instruction
+system.cpu0.op_class::SimdMisc                      0      0.00%     65.06% # Class of executed instruction
+system.cpu0.op_class::SimdMult                      0      0.00%     65.06% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc                   0      0.00%     65.06% # Class of executed instruction
+system.cpu0.op_class::SimdShift                     0      0.00%     65.06% # Class of executed instruction
+system.cpu0.op_class::SimdShiftAcc                  0      0.00%     65.06% # Class of executed instruction
+system.cpu0.op_class::SimdSqrt                      0      0.00%     65.06% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAdd                  0      0.00%     65.06% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAlu                  0      0.00%     65.06% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCmp                  0      0.00%     65.06% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCvt                  0      0.00%     65.06% # Class of executed instruction
+system.cpu0.op_class::SimdFloatDiv                  0      0.00%     65.06% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc              1041      0.00%     65.06% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMult                 0      0.00%     65.06% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     65.06% # Class of executed instruction
+system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     65.06% # Class of executed instruction
+system.cpu0.op_class::MemRead                 6826552     18.64%     83.71% # Class of executed instruction
+system.cpu0.op_class::MemWrite                5966674     16.29%    100.00% # Class of executed instruction
 system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu0.op_class::total                  38615997                       # Class of executed instruction
+system.cpu0.op_class::total                  36617029                       # Class of executed instruction
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                   83028                       # number of quiesce instructions executed
-system.cpu0.icache.tags.replacements           856182                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          510.863139                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs           60651276                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs           856694                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            70.796896                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle      20196898250                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   155.776297                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu1.inst   355.086842                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.304251                       # Average percentage of cache occupancy
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+system.cpu0.icache.tags.warmup_cycle      19833794250                       # Cycle when the warmup percentage was hit.
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 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::0           44                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          195                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2          266                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::3            7                       # Occupied blocks per task id
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 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses         62364664                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses        62364664                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst     30077042                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu1.inst     30574234                       # number of ReadReq hits
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-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.013882                       # miss rate for ReadReq accesses
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-system.cpu0.icache.ReadReq_miss_rate::total     0.013928                       # miss rate for ReadReq accesses
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-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13633.919377                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13901.283205                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 13769.143942                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13633.919377                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13901.283205                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 13769.143942                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13633.919377                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13901.283205                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 13769.143942                       # average overall miss latency
+system.cpu0.icache.tags.tag_accesses         62369216                       # Number of tag accesses
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+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.015252                       # miss rate for ReadReq accesses
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+system.cpu0.icache.ReadReq_miss_rate::total     0.013930                       # miss rate for ReadReq accesses
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+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13599.567191                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13988.578023                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 13776.428183                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13599.567191                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13988.578023                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 13776.428183                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13599.567191                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13988.578023                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 13776.428183                       # average overall miss latency
 system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1093,244 +1094,280 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       423404                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       433290                       # number of ReadReq MSHR misses
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-system.cpu0.icache.overall_mshr_misses::cpu1.inst       433290                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total       856694                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   4924249000                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst   5154307000                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total  10078556000                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   4924249000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst   5154307000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total  10078556000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   4924249000                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst   5154307000                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total  10078556000                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    441046000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total    441046000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    441046000                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::total    441046000                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.013882                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.013974                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.013928                       # mshr miss rate for ReadReq accesses
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-system.cpu0.icache.demand_mshr_miss_rate::total     0.013928                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.013882                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.013974                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.013928                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11630.142842                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11895.744190                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11764.475997                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11630.142842                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11895.744190                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 11764.475997                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11630.142842                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11895.744190                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 11764.475997                       # average overall mshr miss latency
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+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst   4668092751                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total  10087040007                       # number of ReadReq MSHR miss cycles
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+system.cpu0.icache.overall_mshr_miss_latency::total  10087040007                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    440846250                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total    440846250                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    440846250                       # number of overall MSHR uncacheable cycles
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+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.015252                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.012619                       # mshr miss rate for ReadReq accesses
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+system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.012619                       # mshr miss rate for overall accesses
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+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11596.043860                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11982.434201                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11771.713464                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11596.043860                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11982.434201                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 11771.713464                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11596.043860                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11982.434201                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 11771.713464                       # average overall mshr miss latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.dcache.tags.replacements           627683                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          511.876343                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           23661001                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs           628195                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            37.665058                       # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle        669376250                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   147.481748                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu1.data   364.394596                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.288050                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu1.data     0.711708                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.replacements           627738                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          511.876206                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs           21798920                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs           628250                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            34.697843                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.warmup_cycle        668864250                       # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   154.066297                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu1.data   357.809909                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.300911                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu1.data     0.698847                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_percent::total     0.999758                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0           73                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          329                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2          110                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0           76                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          331                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2          105                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses         97784979                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses        97784979                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data      6545596                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu1.data      6653610                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total       13199206                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data      4917377                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu1.data      5057557                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total       9974934                       # number of WriteReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       119123                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu1.data       117066                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       236189                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       125242                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu1.data       122515                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       247757                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data     11462973                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu1.data     11711167                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        23174140                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data     11462973                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu1.data     11711167                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       23174140                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data       186473                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu1.data       182643                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total       369116                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data       125422                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu1.data       125003                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total       250425                       # number of WriteReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         6121                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu1.data         5448                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total        11569                       # number of LoadLockedReq misses
-system.cpu0.dcache.demand_misses::cpu0.data       311895                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu1.data       307646                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total        619541                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data       311895                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu1.data       307646                       # number of overall misses
-system.cpu0.dcache.overall_misses::total       619541                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   2771059250                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   2705059750                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total   5476119000                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data   5617953546                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   5645844221                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total  11263797767                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data     82277250                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data     78257750                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total    160535000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data   8389012796                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu1.data   8350903971                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total  16739916767                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data   8389012796                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu1.data   8350903971                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total  16739916767                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data      6732069                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu1.data      6836253                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total     13568322                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data      5042799                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu1.data      5182560                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total     10225359                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       125244                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data       122514                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       247758                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       125242                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu1.data       122515                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       247757                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data     11774868                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu1.data     12018813                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     23793681                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data     11774868                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu1.data     12018813                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     23793681                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.027699                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.026717                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.027204                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.024872                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.024120                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.024491                       # miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.048873                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.044468                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.046695                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.026488                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu1.data     0.025597                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.026038                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.026488                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu1.data     0.025597                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.026038                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14860.377910                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14810.640156                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 14835.767076                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44792.409195                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 45165.669792                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 44978.727232                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13441.798726                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14364.491557                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13876.307373                       # average LoadLockedReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 26896.913371                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 27144.523156                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 27019.869173                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 26896.913371                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 27144.523156                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 27019.869173                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu0.dcache.tags.tag_accesses         90464778                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses        90464778                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data      5681092                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu1.data      5575113                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total       11256205                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data      5059212                       # number of WriteReq hits
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+system.cpu0.dcache.SoftPFReq_hits::cpu0.data        43677                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu1.data        40519                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::total        84196                       # number of SoftPFReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       123460                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu1.data       112914                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       236374                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data       129861                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu1.data       117956                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       247817                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data     10740304                       # number of demand (read+write) hits
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+system.cpu0.dcache.demand_hits::total        21227630                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data     10783981                       # number of overall hits
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+system.cpu0.dcache.overall_hits::total       21311826                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data       148158                       # number of ReadReq misses
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+system.cpu0.dcache.ReadReq_misses::total       296063                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data       129911                       # number of WriteReq misses
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+system.cpu0.dcache.SoftPFReq_misses::cpu0.data        52745                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu1.data        47443                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::total       100188                       # number of SoftPFReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         6399                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu1.data         5045                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total        11444                       # number of LoadLockedReq misses
+system.cpu0.dcache.demand_misses::cpu0.data       278069                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu1.data       273414                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total        551483                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data       330814                       # number of overall misses
+system.cpu0.dcache.overall_misses::cpu1.data       320857                       # number of overall misses
+system.cpu0.dcache.overall_misses::total       651671                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   2069842250                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   2010175249                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total   4080017499                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data   5698764993                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   5806816529                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total  11505581522                       # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data     85596250                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data     73843500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total    159439750                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data   7768607243                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu1.data   7816991778                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total  15585599021                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data   7768607243                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu1.data   7816991778                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total  15585599021                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data      5829250                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu1.data      5723018                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total     11552268                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data      5189123                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu1.data      5037722                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total     10226845                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu0.data        96422                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu1.data        87962                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total       184384                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       129859                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data       117959                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       247818                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       129861                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu1.data       117956                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       247817                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data     11018373                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu1.data     10760740                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     21779113                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data     11114795                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu1.data     10848702                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     21963497                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.025416                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.025844                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.025628                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.025035                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.024914                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.024975                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.547022                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.539358                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.543366                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.049277                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.042769                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.046179                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.025237                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu1.data     0.025408                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.025322                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.029763                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu1.data     0.029576                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.029671                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13970.506149                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 13590.989142                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 13780.909803                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 43866.685600                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 46266.136524                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 45045.734563                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13376.504141                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14636.967294                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13932.169696                       # average LoadLockedReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 27937.696194                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 28590.312778                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 28261.250158                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 23483.308575                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 24362.852542                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 23916.361202                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs           58                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs                1                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs           58                       # average number of cycles each access was blocked
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       596476                       # number of writebacks
-system.cpu0.dcache.writebacks::total           596476                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       186473                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       182643                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       369116                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       125422                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data       125003                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       250425                       # number of WriteReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         6121                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         5448                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total        11569                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data       311895                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu1.data       307646                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total       619541                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data       311895                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu1.data       307646                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total       619541                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   2396807750                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   2338699250                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total   4735507000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   5342161454                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   5370757779                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total  10712919233                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     70030750                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     67311250                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    137342000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   7738969204                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   7709457029                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  15448426233                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data   7738969204                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   7709457029                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  15448426233                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data  90834275250                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data  91243928750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182078204000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data  13255943399                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data  12983118997                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total  26239062396                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 104090218649                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 104227047747                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total 208317266396                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.027699                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.026717                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.027204                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.024872                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.024120                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.024491                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.048873                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.044468                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.046695                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.026488                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.025597                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.026038                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.026488                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.025597                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.026038                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12853.376896                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12804.757094                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12829.319238                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 42593.495990                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 42965.031071                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 42778.952712                       # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11441.063552                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12355.222100                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11871.553289                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24812.738915                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25059.506800                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24935.276653                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24812.738915                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25059.506800                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24935.276653                       # average overall mshr miss latency
+system.cpu0.dcache.writebacks::writebacks       596521                       # number of writebacks
+system.cpu0.dcache.writebacks::total           596521                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data          239                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data          285                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total          524                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data         2519                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data         2304                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total         4823                       # number of WriteReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data         2758                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu1.data         2589                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total         5347                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data         2758                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu1.data         2589                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total         5347                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       147919                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       147620                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total       295539                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       127392                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data       123205                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       250597                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data        39219                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data        34354                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total        73573                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         6399                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         5045                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total        11444                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data       275311                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu1.data       270825                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total       546136                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data       314530                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu1.data       305179                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total       619709                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   1770558000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   1711285000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total   3481843000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   5304830507                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   5433667721                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total  10738498228                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data    656374250                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    573183000                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1229557250                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     72793750                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     63702500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    136496250                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   7075388507                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   7144952721                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  14220341228                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data   7731762757                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   7718135721                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  15449898478                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data  91728534250                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data  90349964750                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182078499000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data  13171576426                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data  13067690513                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total  26239266939                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 104900110676                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 103417655263                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 208317765939                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.025375                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.025794                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.025583                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.024550                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.024456                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.024504                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.406743                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.390555                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.399021                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.049277                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.042769                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.046179                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.024987                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.025168                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.025076                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.028298                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.028130                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.028215                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11969.780758                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11592.501016                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11781.331736                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 41641.786823                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 44102.655907                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 42851.663140                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16736.129172                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16684.607324                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16712.071684                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11375.800906                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12626.858276                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11927.319993                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 25699.621544                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 26382.175652                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26038.095324                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24581.956433                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25290.520386                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24930.892529                       # average overall mshr miss latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -1364,25 +1401,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # D
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                     7552227                       # DTB read hits
-system.cpu1.dtb.read_misses                      6971                       # DTB read misses
-system.cpu1.dtb.write_hits                    5683121                       # DTB write hits
-system.cpu1.dtb.write_misses                     1859                       # DTB write misses
-system.cpu1.dtb.flush_tlb                        2493                       # Number of times complete TLB was flushed
+system.cpu1.dtb.read_hits                     6516178                       # DTB read hits
+system.cpu1.dtb.read_misses                      7066                       # DTB read misses
+system.cpu1.dtb.write_hits                    5531450                       # DTB write hits
+system.cpu1.dtb.write_misses                     1844                       # DTB write misses
+system.cpu1.dtb.flush_tlb                        2489                       # Number of times complete TLB was flushed
 system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid                714                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid                     34                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                    6603                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.flush_tlb_mva_asid                712                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid                     30                       # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries                    6501                       # Number of entries that have been flushed from TLB
 system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                   141                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.prefetch_faults                   152                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                      222                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                 7559198                       # DTB read accesses
-system.cpu1.dtb.write_accesses                5684980                       # DTB write accesses
+system.cpu1.dtb.perms_faults                      238                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses                 6523244                       # DTB read accesses
+system.cpu1.dtb.write_accesses                5533294                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                         13235348                       # DTB hits
-system.cpu1.dtb.misses                           8830                       # DTB misses
-system.cpu1.dtb.accesses                     13244178                       # DTB accesses
+system.cpu1.dtb.hits                         12047628                       # DTB hits
+system.cpu1.dtb.misses                           8910                       # DTB misses
+system.cpu1.dtb.accesses                     12056538                       # DTB accesses
 system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -1404,85 +1441,87 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.inst_hits                    31007524                       # ITB inst hits
-system.cpu1.itb.inst_misses                      3606                       # ITB inst misses
+system.cpu1.itb.inst_hits                    30872911                       # ITB inst hits
+system.cpu1.itb.inst_misses                      3673                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
 system.cpu1.itb.write_misses                        0                       # DTB write misses
-system.cpu1.itb.flush_tlb                        2493                       # Number of times complete TLB was flushed
+system.cpu1.itb.flush_tlb                        2489                       # Number of times complete TLB was flushed
 system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid                714                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid                     34                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                    2820                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_tlb_mva_asid                712                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid                     30                       # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries                    2794                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses                31011130                       # ITB inst accesses
-system.cpu1.itb.hits                         31007524                       # DTB hits
-system.cpu1.itb.misses                           3606                       # DTB misses
-system.cpu1.itb.accesses                     31011130                       # DTB accesses
-system.cpu1.numCycles                      2633285995                       # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses                30876584                       # ITB inst accesses
+system.cpu1.itb.hits                         30872911                       # DTB hits
+system.cpu1.itb.misses                           3673                       # DTB misses
+system.cpu1.itb.accesses                     30876584                       # DTB accesses
+system.cpu1.numCycles                      2627183277                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                   30336967                       # Number of instructions committed
-system.cpu1.committedOps                     38639043                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses             34937438                       # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses                  5427                       # Number of float alu accesses
-system.cpu1.num_func_calls                    1081754                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts      3973481                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                    34937438                       # number of integer instructions
-system.cpu1.num_fp_insts                         5427                       # number of float instructions
-system.cpu1.num_int_register_reads          202463130                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes          37550545                       # number of times the integer registers were written
-system.cpu1.num_fp_register_reads                4002                       # number of times the floating registers were read
-system.cpu1.num_fp_register_writes               1426                       # number of times the floating registers were written
-system.cpu1.num_mem_refs                     13827657                       # number of memory refs
-system.cpu1.num_load_insts                    7892397                       # Number of load instructions
-system.cpu1.num_store_insts                   5935260                       # Number of store instructions
-system.cpu1.num_idle_cycles              2291893093.755996                       # Number of idle cycles
-system.cpu1.num_busy_cycles              341392901.244004                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.129645                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.870355                       # Percentage of idle cycles
-system.cpu1.Branches                          5180924                       # Number of branches fetched
-system.cpu1.op_class::No_OpClass                15672      0.04%      0.04% # Class of executed instruction
-system.cpu1.op_class::IntAlu                 25411566     64.66%     64.70% # Class of executed instruction
-system.cpu1.op_class::IntMult                   43588      0.11%     64.81% # Class of executed instruction
-system.cpu1.op_class::IntDiv                        0      0.00%     64.81% # Class of executed instruction
-system.cpu1.op_class::FloatAdd                      0      0.00%     64.81% # Class of executed instruction
-system.cpu1.op_class::FloatCmp                      0      0.00%     64.81% # Class of executed instruction
-system.cpu1.op_class::FloatCvt                      0      0.00%     64.81% # Class of executed instruction
-system.cpu1.op_class::FloatMult                     0      0.00%     64.81% # Class of executed instruction
-system.cpu1.op_class::FloatDiv                      0      0.00%     64.81% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt                     0      0.00%     64.81% # Class of executed instruction
-system.cpu1.op_class::SimdAdd                       0      0.00%     64.81% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc                    0      0.00%     64.81% # Class of executed instruction
-system.cpu1.op_class::SimdAlu                       0      0.00%     64.81% # Class of executed instruction
-system.cpu1.op_class::SimdCmp                       0      0.00%     64.81% # Class of executed instruction
-system.cpu1.op_class::SimdCvt                       0      0.00%     64.81% # Class of executed instruction
-system.cpu1.op_class::SimdMisc                      0      0.00%     64.81% # Class of executed instruction
-system.cpu1.op_class::SimdMult                      0      0.00%     64.81% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc                   0      0.00%     64.81% # Class of executed instruction
-system.cpu1.op_class::SimdShift                     0      0.00%     64.81% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc                  0      0.00%     64.81% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt                      0      0.00%     64.81% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd                  0      0.00%     64.81% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu                  0      0.00%     64.81% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp                  0      0.00%     64.81% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt                  0      0.00%     64.81% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv                  0      0.00%     64.81% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc              1181      0.00%     64.81% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult                 0      0.00%     64.81% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     64.81% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     64.81% # Class of executed instruction
-system.cpu1.op_class::MemRead                 7892397     20.08%     84.90% # Class of executed instruction
-system.cpu1.op_class::MemWrite                5935260     15.10%    100.00% # Class of executed instruction
+system.cpu1.committedInsts                   30155336                       # Number of instructions committed
+system.cpu1.committedOps                     35837142                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses             32021976                       # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses                  4418                       # Number of float alu accesses
+system.cpu1.num_func_calls                    1035067                       # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts      3744201                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                    32021976                       # number of integer instructions
+system.cpu1.num_fp_insts                         4418                       # number of float instructions
+system.cpu1.num_int_register_reads           57765753                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes          21325005                       # number of times the integer registers were written
+system.cpu1.num_fp_register_reads                3309                       # number of times the floating registers were read
+system.cpu1.num_fp_register_writes               1110                       # number of times the floating registers were written
+system.cpu1.num_cc_register_reads           128250854                       # number of times the CC registers were read
+system.cpu1.num_cc_register_writes           14653287                       # number of times the CC registers were written
+system.cpu1.num_mem_refs                     12466012                       # number of memory refs
+system.cpu1.num_load_insts                    6694911                       # Number of load instructions
+system.cpu1.num_store_insts                   5771101                       # Number of store instructions
+system.cpu1.num_idle_cycles              2287259017.662607                       # Number of idle cycles
+system.cpu1.num_busy_cycles              339924259.337393                       # Number of busy cycles
+system.cpu1.not_idle_fraction                0.129387                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                    0.870613                       # Percentage of idle cycles
+system.cpu1.Branches                          5118153                       # Number of branches fetched
+system.cpu1.op_class::No_OpClass                15840      0.04%      0.04% # Class of executed instruction
+system.cpu1.op_class::IntAlu                 23832212     65.55%     65.59% # Class of executed instruction
+system.cpu1.op_class::IntMult                   42672      0.12%     65.71% # Class of executed instruction
+system.cpu1.op_class::IntDiv                        0      0.00%     65.71% # Class of executed instruction
+system.cpu1.op_class::FloatAdd                      0      0.00%     65.71% # Class of executed instruction
+system.cpu1.op_class::FloatCmp                      0      0.00%     65.71% # Class of executed instruction
+system.cpu1.op_class::FloatCvt                      0      0.00%     65.71% # Class of executed instruction
+system.cpu1.op_class::FloatMult                     0      0.00%     65.71% # Class of executed instruction
+system.cpu1.op_class::FloatDiv                      0      0.00%     65.71% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt                     0      0.00%     65.71% # Class of executed instruction
+system.cpu1.op_class::SimdAdd                       0      0.00%     65.71% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc                    0      0.00%     65.71% # Class of executed instruction
+system.cpu1.op_class::SimdAlu                       0      0.00%     65.71% # Class of executed instruction
+system.cpu1.op_class::SimdCmp                       0      0.00%     65.71% # Class of executed instruction
+system.cpu1.op_class::SimdCvt                       0      0.00%     65.71% # Class of executed instruction
+system.cpu1.op_class::SimdMisc                      0      0.00%     65.71% # Class of executed instruction
+system.cpu1.op_class::SimdMult                      0      0.00%     65.71% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc                   0      0.00%     65.71% # Class of executed instruction
+system.cpu1.op_class::SimdShift                     0      0.00%     65.71% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc                  0      0.00%     65.71% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt                      0      0.00%     65.71% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd                  0      0.00%     65.71% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu                  0      0.00%     65.71% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp                  0      0.00%     65.71% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt                  0      0.00%     65.71% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv                  0      0.00%     65.71% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc              1070      0.00%     65.71% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult                 0      0.00%     65.71% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     65.71% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     65.71% # Class of executed instruction
+system.cpu1.op_class::MemRead                 6694911     18.41%     84.13% # Class of executed instruction
+system.cpu1.op_class::MemWrite                5771101     15.87%    100.00% # Class of executed instruction
 system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu1.op_class::total                  39299664                       # Class of executed instruction
+system.cpu1.op_class::total                  36357806                       # Class of executed instruction
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
 system.iocache.tags.replacements                    0                       # number of replacements
@@ -1501,10 +1540,10 @@ system.iocache.avg_blocked_cycles::no_mshrs          nan                       #
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1779915025250                       # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1779915025250                       # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1779915025250                       # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1779915025250                       # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1781125703750                       # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1781125703750                       # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1781125703750                       # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1781125703750                       # number of overall MSHR uncacheable cycles
 system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average ReadReq mshr uncacheable latency
 system.iocache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average overall mshr uncacheable latency
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
index aa05e00b0..bca94218b 100644
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
@@ -1,136 +1,139 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  5.137926                       # Number of seconds simulated
-sim_ticks                                5137926173000                       # Number of ticks simulated
-final_tick                               5137926173000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  5.129874                       # Number of seconds simulated
+sim_ticks                                5129873616500                       # Number of ticks simulated
+final_tick                               5129873616500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 165389                       # Simulator instruction rate (inst/s)
-host_op_rate                                   326926                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2083966500                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 742788                       # Number of bytes of host memory used
-host_seconds                                  2465.46                       # Real time elapsed on the host
-sim_insts                                   407759509                       # Number of instructions simulated
-sim_ops                                     806020953                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 122712                       # Simulator instruction rate (inst/s)
+host_op_rate                                   242564                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1543734215                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 750608                       # Number of bytes of host memory used
+host_seconds                                  3323.03                       # Real time elapsed on the host
+sim_insts                                   407773893                       # Number of instructions simulated
+sim_ops                                     806048632                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::pc.south_bridge.ide      2427584                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.dtb.walker         3776                       # Number of bytes read from this memory
+system.physmem.bytes_read::pc.south_bridge.ide        28352                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker         4224                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.itb.walker          320                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst           1035776                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          10808512                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             14275968                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst      1035776                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         1035776                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      9555328                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           9555328                       # Number of bytes written to this memory
-system.physmem.num_reads::pc.south_bridge.ide        37931                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.dtb.walker           59                       # Number of read requests responded to by this memory
+system.physmem.bytes_read::cpu.inst           1049344                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          10817792                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             11900032                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst      1049344                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1049344                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      6600896                       # Number of bytes written to this memory
+system.physmem.bytes_written::pc.south_bridge.ide      2990080                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           9590976                       # Number of bytes written to this memory
+system.physmem.num_reads::pc.south_bridge.ide          443                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.dtb.walker           66                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.itb.walker            5                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst              16184                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             168883                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                223062                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          149302                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               149302                       # Number of write requests responded to by this memory
-system.physmem.bw_read::pc.south_bridge.ide       472483                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.dtb.walker            735                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_reads::cpu.inst              16396                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             169028                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                185938                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          103139                       # Number of write requests responded to by this memory
+system.physmem.num_writes::pc.south_bridge.ide        46720                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               149859                       # Number of write requests responded to by this memory
+system.physmem.bw_read::pc.south_bridge.ide         5527                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.dtb.walker            823                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu.itb.walker             62                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               201594                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              2103672                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 2778547                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          201594                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             201594                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1859764                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1859764                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1859764                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::pc.south_bridge.ide       472483                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker           735                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               204556                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              2108783                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 2319751                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          204556                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             204556                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1286756                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::pc.south_bridge.ide       582876                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                1869632                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1286756                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::pc.south_bridge.ide       588403                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker           823                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.itb.walker            62                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              201594                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             2103672                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                4638310                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        223062                       # Number of read requests accepted
-system.physmem.writeReqs                       149302                       # Number of write requests accepted
-system.physmem.readBursts                      223062                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     149302                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 14267968                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      8000                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   9553728                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  14275968                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                9555328                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      125                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bw_total::cpu.inst              204556                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             2108783                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                4189384                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        185938                       # Number of read requests accepted
+system.physmem.writeReqs                       149859                       # Number of write requests accepted
+system.physmem.readBursts                      185938                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     149859                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 11881152                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     18880                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   9589248                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  11900032                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                9590976                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      295                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs           1775                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               14642                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               13963                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               14587                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               13341                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               14143                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               13526                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               13007                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               13123                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               13660                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               13743                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              13657                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              13667                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              14668                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              14755                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              14289                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              14166                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               10056                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                9321                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                9829                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                8830                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                9558                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                8986                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                8593                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                8747                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                8969                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                9193                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               9160                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               9087                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               9894                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               9881                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               9649                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               9524                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs           1710                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               11383                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               10659                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               11850                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               11657                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               11883                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               11508                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               11028                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               11462                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               11217                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               11477                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              11649                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              12129                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              11737                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              12518                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              12268                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              11218                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               10090                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                9375                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                9103                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                8918                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                9314                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                9243                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                8603                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                8925                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                9240                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                9268                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               9747                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               9397                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               9475                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               9702                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              10013                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               9419                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    5137926057000                       # Total gap between requests
+system.physmem.numWrRetry                           4                       # Number of times write queue was full causing retry
+system.physmem.totGap                    5129873502000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  223062                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  185938                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 149302                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    173856                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     14004                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                      5938                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                      3116                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                      2938                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                      3695                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                      3277                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                      3105                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                      2401                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                      1802                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                     1616                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                     1416                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                     1120                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                     1019                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                      848                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                      763                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                      690                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                      540                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                      420                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                      347                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                       24                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21                        2                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 149859                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    170868                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     11901                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                      2132                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                       408                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                        52                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                        38                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                        33                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                        31                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                        28                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                        29                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                       29                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                       29                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                       27                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                       26                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                        8                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                        2                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
@@ -156,287 +159,277 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     1696                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     1831                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     6323                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     6727                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     6895                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     7003                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     7119                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     7385                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     7803                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     8119                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     8610                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     8803                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     8913                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     9245                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     9110                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     9225                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     9112                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     9115                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                     1831                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                     1696                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                     1783                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                     1762                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                     1670                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                     1529                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                     1335                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                     1057                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      857                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      652                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      516                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      372                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      247                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      185                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::48                      118                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                       94                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                       86                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                       80                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                       69                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                       54                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                       50                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       34                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                       21                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                        8                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                        3                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                        2                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        75897                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      313.867900                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     181.633012                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     336.529129                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          29529     38.91%     38.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        16915     22.29%     61.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         7566      9.97%     71.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         4259      5.61%     76.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2981      3.93%     80.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         2008      2.65%     83.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1459      1.92%     85.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1171      1.54%     86.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        10009     13.19%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          75897                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          8307                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        26.835320                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      526.600201                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047           8306     99.99%     99.99% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::15                     2274                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::62                        5                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                        7                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        71875                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      298.717718                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     177.081512                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     320.465816                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          27438     38.17%     38.17% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        17395     24.20%     62.38% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         7359     10.24%     72.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         4225      5.88%     78.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2947      4.10%     82.59% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         2054      2.86%     85.45% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1404      1.95%     87.40% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1166      1.62%     89.03% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         7887     10.97%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          71875                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          7354                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        25.241501                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      560.072825                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047           7353     99.99%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::47104-49151            1      0.01%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            8307                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          8307                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        17.970025                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       17.437156                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        5.734930                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-17            6174     74.32%     74.32% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18-19            1334     16.06%     90.38% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-21              66      0.79%     91.18% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22-23              64      0.77%     91.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-25              51      0.61%     92.56% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26-27              45      0.54%     93.10% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-29             113      1.36%     94.46% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::30-31              87      1.05%     95.51% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-33              56      0.67%     96.18% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::34-35              56      0.67%     96.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-37              34      0.41%     97.27% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::38-39              52      0.63%     97.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-41              60      0.72%     98.62% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::42-43              31      0.37%     98.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-45              10      0.12%     99.11% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::46-47              10      0.12%     99.23% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-49              28      0.34%     99.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::50-51               7      0.08%     99.65% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-53               4      0.05%     99.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::54-55               3      0.04%     99.74% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-57               5      0.06%     99.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::58-59               4      0.05%     99.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-61               2      0.02%     99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::62-63               3      0.04%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-65               2      0.02%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::66-67               1      0.01%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-69               2      0.02%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-77               1      0.01%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::78-79               1      0.01%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::90-91               1      0.01%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            8307                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     4966355250                       # Total ticks spent queuing
-system.physmem.totMemAccLat                9146424000                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   1114685000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       22276.94                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            7354                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          7354                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        20.374218                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.656947                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       12.477131                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            6319     85.93%     85.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23              51      0.69%     86.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27              33      0.45%     87.07% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31             263      3.58%     90.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35             273      3.71%     94.36% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39              24      0.33%     94.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43              24      0.33%     95.01% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47              15      0.20%     95.21% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51              39      0.53%     95.74% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55               6      0.08%     95.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59               3      0.04%     95.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63               1      0.01%     95.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67             229      3.11%     98.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71               5      0.07%     99.06% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75               3      0.04%     99.10% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79               2      0.03%     99.13% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83              25      0.34%     99.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99              13      0.18%     99.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             2      0.03%     99.67% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107             3      0.04%     99.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115             5      0.07%     99.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::116-119             1      0.01%     99.80% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127             2      0.03%     99.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131            10      0.14%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135             1      0.01%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143             2      0.03%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            7354                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     1988147750                       # Total ticks spent queuing
+system.physmem.totMemAccLat                5468954000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    928215000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       10709.52                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  41026.94                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           2.78                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           1.86                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        2.78                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        1.86                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  29459.52                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           2.32                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           1.87                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        2.32                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        1.87                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           0.04                       # Data bus utilization in percentage
+system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.02                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.07                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        25.93                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     185691                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    110625                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   83.29                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  74.09                       # Row buffer hit rate for writes
-system.physmem.avgGap                     13798127.79                       # Average gap between requests
-system.physmem.pageHitRate                      79.60                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE     4930575819000                       # Time in different power states
-system.physmem.memoryStateTime::REF      171566460000                       # Time in different power states
+system.physmem.avgWrQLen                        22.59                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     152685                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    110914                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   82.25                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  74.01                       # Row buffer hit rate for writes
+system.physmem.avgGap                     15276710.34                       # Average gap between requests
+system.physmem.pageHitRate                      78.57                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE     4923726743250                       # Time in different power states
+system.physmem.memoryStateTime::REF      171297620000                       # Time in different power states
 system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT       35783789000                       # Time in different power states
+system.physmem.memoryStateTime::ACT       34849149750                       # Time in different power states
 system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.membus.throughput                      5117506                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq              662560                       # Transaction distribution
-system.membus.trans_dist::ReadResp             662552                       # Transaction distribution
-system.membus.trans_dist::WriteReq              13764                       # Transaction distribution
-system.membus.trans_dist::WriteResp             13764                       # Transaction distribution
-system.membus.trans_dist::Writeback            149302                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             2261                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp            1794                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            180173                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           180170                       # Transaction distribution
-system.membus.trans_dist::MessageReq             1643                       # Transaction distribution
-system.membus.trans_dist::MessageResp            1643                       # Transaction distribution
-system.membus.trans_dist::BadAddressError            8                       # Transaction distribution
-system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave         3286                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.apicbridge.master::total         3286                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       471036                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio       775076                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       477605                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio           16                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1723733                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       132228                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       132228                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1859247                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave         6572                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.apicbridge.master::total         6572                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       241801                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio      1550149                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     18417024                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total     20208974                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port      5414272                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::total      5414272                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total            25629818                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus               25629818                       # Total data (bytes)
-system.membus.snoop_data_through_bus           663552                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy           250523000                       # Layer occupancy (ticks)
+system.membus.throughput                      4545861                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq              662568                       # Transaction distribution
+system.membus.trans_dist::ReadResp             662557                       # Transaction distribution
+system.membus.trans_dist::WriteReq              13776                       # Transaction distribution
+system.membus.trans_dist::WriteResp             13776                       # Transaction distribution
+system.membus.trans_dist::Writeback            103139                       # Transaction distribution
+system.membus.trans_dist::WriteInvalidateReq        46720                       # Transaction distribution
+system.membus.trans_dist::WriteInvalidateResp        46720                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq             2217                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp            1710                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            133156                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           133153                       # Transaction distribution
+system.membus.trans_dist::MessageReq             1644                       # Transaction distribution
+system.membus.trans_dist::MessageResp            1644                       # Transaction distribution
+system.membus.trans_dist::BadAddressError           11                       # Transaction distribution
+system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave         3288                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.apicbridge.master::total         3288                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       471084                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio       775070                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       478059                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio           22                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1724235                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        94797                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total        94797                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                1822320                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave         6576                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.apicbridge.master::total         6576                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       241828                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio      1550137                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     18472576                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total     20264541                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port      3018432                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.iocache.mem_side::total      3018432                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total            23289549                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus               23289549                       # Total data (bytes)
+system.membus.snoop_data_through_bus            30144                       # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy           251288000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy           583102000                       # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy           583699000                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             3286000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             3288000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer3.occupancy          1620731000                       # Layer occupancy (ticks)
+system.membus.reqLayer3.occupancy          1574361000                       # Layer occupancy (ticks)
 system.membus.reqLayer3.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer4.occupancy                9000                       # Layer occupancy (ticks)
+system.membus.reqLayer4.occupancy               13500                       # Layer occupancy (ticks)
 system.membus.reqLayer4.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer0.occupancy            1643000                       # Layer occupancy (ticks)
+system.membus.respLayer0.occupancy            1644000                       # Layer occupancy (ticks)
 system.membus.respLayer0.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         3164060842                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         3158618040                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.1                       # Layer utilization (%)
-system.membus.respLayer4.occupancy          429649499                       # Layer occupancy (ticks)
+system.membus.respLayer4.occupancy           54966743                       # Layer occupancy (ticks)
 system.membus.respLayer4.utilization              0.0                       # Layer utilization (%)
-system.iocache.tags.replacements                47575                       # number of replacements
-system.iocache.tags.tagsinuse                0.116331                       # Cycle average of tags in use
+system.iocache.tags.replacements                47579                       # number of replacements
+system.iocache.tags.tagsinuse                0.103859                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs                47591                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs                47595                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         4992948576000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::pc.south_bridge.ide     0.116331                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::pc.south_bridge.ide     0.007271                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.007271                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         4992945696000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::pc.south_bridge.ide     0.103859                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::pc.south_bridge.ide     0.006491                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.006491                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses               428670                       # Number of tag accesses
-system.iocache.tags.data_accesses              428670                       # Number of data accesses
-system.iocache.ReadReq_misses::pc.south_bridge.ide          910                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total              910                       # number of ReadReq misses
-system.iocache.WriteReq_misses::pc.south_bridge.ide        46720                       # number of WriteReq misses
-system.iocache.WriteReq_misses::total           46720                       # number of WriteReq misses
-system.iocache.demand_misses::pc.south_bridge.ide        47630                       # number of demand (read+write) misses
-system.iocache.demand_misses::total             47630                       # number of demand (read+write) misses
-system.iocache.overall_misses::pc.south_bridge.ide        47630                       # number of overall misses
-system.iocache.overall_misses::total            47630                       # number of overall misses
-system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    151620185                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total    151620185                       # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency::pc.south_bridge.ide  11039278588                       # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_latency::total  11039278588                       # number of WriteReq miss cycles
-system.iocache.demand_miss_latency::pc.south_bridge.ide  11190898773                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total  11190898773                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::pc.south_bridge.ide  11190898773                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total  11190898773                       # number of overall miss cycles
-system.iocache.ReadReq_accesses::pc.south_bridge.ide          910                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total            910                       # number of ReadReq accesses(hits+misses)
-system.iocache.WriteReq_accesses::pc.south_bridge.ide        46720                       # number of WriteReq accesses(hits+misses)
-system.iocache.WriteReq_accesses::total         46720                       # number of WriteReq accesses(hits+misses)
-system.iocache.demand_accesses::pc.south_bridge.ide        47630                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total           47630                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::pc.south_bridge.ide        47630                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total          47630                       # number of overall (read+write) accesses
+system.iocache.tags.tag_accesses               428706                       # Number of tag accesses
+system.iocache.tags.data_accesses              428706                       # Number of data accesses
+system.iocache.WriteInvalidateReq_hits::pc.south_bridge.ide        46720                       # number of WriteInvalidateReq hits
+system.iocache.WriteInvalidateReq_hits::total        46720                       # number of WriteInvalidateReq hits
+system.iocache.ReadReq_misses::pc.south_bridge.ide          914                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total              914                       # number of ReadReq misses
+system.iocache.demand_misses::pc.south_bridge.ide          914                       # number of demand (read+write) misses
+system.iocache.demand_misses::total               914                       # number of demand (read+write) misses
+system.iocache.overall_misses::pc.south_bridge.ide          914                       # number of overall misses
+system.iocache.overall_misses::total              914                       # number of overall misses
+system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    152667446                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total    152667446                       # number of ReadReq miss cycles
+system.iocache.demand_miss_latency::pc.south_bridge.ide    152667446                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total    152667446                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::pc.south_bridge.ide    152667446                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total    152667446                       # number of overall miss cycles
+system.iocache.ReadReq_accesses::pc.south_bridge.ide          914                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total            914                       # number of ReadReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide        46720                       # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::total        46720                       # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.demand_accesses::pc.south_bridge.ide          914                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total             914                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::pc.south_bridge.ide          914                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total            914                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
-system.iocache.WriteReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for WriteReq accesses
-system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
 system.iocache.demand_miss_rate::pc.south_bridge.ide            1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::pc.south_bridge.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 166615.587912                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 166615.587912                       # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 236285.928682                       # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total 236285.928682                       # average WriteReq miss latency
-system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 234954.834621                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 234954.834621                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 234954.834621                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 234954.834621                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs        159238                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 167032.216630                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 167032.216630                       # average ReadReq miss latency
+system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 167032.216630                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 167032.216630                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 167032.216630                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 167032.216630                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs           308                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                14593                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                   26                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs    10.911944                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs    11.846154                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.fast_writes                          0                       # number of fast writes performed
+system.iocache.fast_writes                      46720                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.writebacks::writebacks           46667                       # number of writebacks
-system.iocache.writebacks::total                46667                       # number of writebacks
-system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          910                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total          910                       # number of ReadReq MSHR misses
-system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide        46720                       # number of WriteReq MSHR misses
-system.iocache.WriteReq_mshr_misses::total        46720                       # number of WriteReq MSHR misses
-system.iocache.demand_mshr_misses::pc.south_bridge.ide        47630                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total        47630                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::pc.south_bridge.ide        47630                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total        47630                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide    104274685                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total    104274685                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide   8607905090                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::total   8607905090                       # number of WriteReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide   8712179775                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   8712179775                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide   8712179775                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   8712179775                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          914                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total          914                       # number of ReadReq MSHR misses
+system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide        46720                       # number of WriteInvalidateReq MSHR misses
+system.iocache.WriteInvalidateReq_mshr_misses::total        46720                       # number of WriteInvalidateReq MSHR misses
+system.iocache.demand_mshr_misses::pc.south_bridge.ide          914                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total          914                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::pc.south_bridge.ide          914                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total          914                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide    105114946                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total    105114946                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide   2850047667                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::total   2850047667                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide    105114946                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total    105114946                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide    105114946                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total    105114946                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
-system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for WriteReq accesses
-system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
+system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteInvalidateReq accesses
 system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for demand accesses
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 114587.565934                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 114587.565934                       # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 184244.543878                       # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total 184244.543878                       # average WriteReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 182913.705123                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 182913.705123                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 182913.705123                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 182913.705123                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 115005.411379                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 115005.411379                       # average ReadReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 61002.732598                       # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 61002.732598                       # average WriteInvalidateReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 115005.411379                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 115005.411379                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 115005.411379                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 115005.411379                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
 system.pc.south_bridge.ide.disks0.dma_read_bytes        34816                       # Number of bytes transfered via DMA reads (not PRD).
-system.pc.south_bridge.ide.disks0.dma_read_txs           31                       # Number of DMA read transactions (not PRD).
+system.pc.south_bridge.ide.disks0.dma_read_txs           32                       # Number of DMA read transactions (not PRD).
 system.pc.south_bridge.ide.disks0.dma_write_full_pages          693                       # Number of full page size DMA writes.
 system.pc.south_bridge.ide.disks0.dma_write_bytes      2985984                       # Number of bytes transfered via DMA writes.
 system.pc.south_bridge.ide.disks0.dma_write_txs          812                       # Number of DMA write transactions.
@@ -446,22 +439,22 @@ system.pc.south_bridge.ide.disks1.dma_read_txs            0
 system.pc.south_bridge.ide.disks1.dma_write_full_pages            1                       # Number of full page size DMA writes.
 system.pc.south_bridge.ide.disks1.dma_write_bytes         4096                       # Number of bytes transfered via DMA writes.
 system.pc.south_bridge.ide.disks1.dma_write_txs            1                       # Number of DMA write transactions.
-system.iobus.throughput                        637650                       # Throughput (bytes/s)
-system.iobus.trans_dist::ReadReq               225557                       # Transaction distribution
-system.iobus.trans_dist::ReadResp              225557                       # Transaction distribution
-system.iobus.trans_dist::WriteReq               57591                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              57591                       # Transaction distribution
-system.iobus.trans_dist::MessageReq              1643                       # Transaction distribution
-system.iobus.trans_dist::MessageResp             1643                       # Transaction distribution
+system.iobus.throughput                        638663                       # Throughput (bytes/s)
+system.iobus.trans_dist::ReadReq               225570                       # Transaction distribution
+system.iobus.trans_dist::ReadResp              225570                       # Transaction distribution
+system.iobus.trans_dist::WriteReq               57606                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              57606                       # Transaction distribution
+system.iobus.trans_dist::MessageReq              1644                       # Transaction distribution
+system.iobus.trans_dist::MessageResp             1644                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio           44                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio            6                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio        11134                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio        11180                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf          180                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio         1364                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio           78                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio           54                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio           30                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio       427354                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio       427356                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio         1210                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio          170                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio            2                       # Packet count per connected master and slave (bytes)
@@ -471,21 +464,21 @@ system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio
 system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio           12                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio           10                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio         2128                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total       471036                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side        95260                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total        95260                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         3286                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total         3286                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  569582                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total       471084                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side        95268                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total        95268                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         3288                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total         3288                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  569640                       # Packet count per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio           22                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio            3                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio         6712                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio         6738                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf          221                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio          682                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio           39                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio           27                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio           15                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio       213677                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio       213678                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio         2420                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.pc.i_dont_exist.pio           85                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.pc.behind_pci.pio            1                       # Cumulative packet size per connected master and slave (bytes)
@@ -495,20 +488,20 @@ system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_3.pio
 system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_4.pio            6                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_floppy.pio            5                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio         4256                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::total       241801                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side      3027824                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total      3027824                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         6572                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total         6572                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::total              3276197                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.data_through_bus                 3276197                       # Total data (bytes)
-system.iobus.reqLayer0.occupancy              3919904                       # Layer occupancy (ticks)
+system.iobus.tot_pkt_size_system.bridge.master::total       241828                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side      3027856                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total      3027856                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         6576                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total         6576                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::total              3276260                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.data_through_bus                 3276260                       # Total data (bytes)
+system.iobus.reqLayer0.occupancy              3918185                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy                34000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer2.occupancy                 6000                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy              8851000                       # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy              8889000                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer4.occupancy               122000                       # Layer occupancy (ticks)
 system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
@@ -520,7 +513,7 @@ system.iobus.reqLayer7.occupancy                50000                       # La
 system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer8.occupancy                26000                       # Layer occupancy (ticks)
 system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer9.occupancy            213678000                       # Layer occupancy (ticks)
+system.iobus.reqLayer9.occupancy            213679000                       # Layer occupancy (ticks)
 system.iobus.reqLayer9.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer10.occupancy             1014000                       # Layer occupancy (ticks)
 system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
@@ -538,274 +531,273 @@ system.iobus.reqLayer16.occupancy                9000                       # La
 system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer17.occupancy               10000                       # Layer occupancy (ticks)
 system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer18.occupancy           424855274                       # Layer occupancy (ticks)
+system.iobus.reqLayer18.occupancy           422017356                       # Layer occupancy (ticks)
 system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer19.occupancy             1064000                       # Layer occupancy (ticks)
 system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy           460165000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy           460198000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer1.occupancy            53596501                       # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy            52370257                       # Layer occupancy (ticks)
 system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer2.occupancy             1643000                       # Layer occupancy (ticks)
+system.iobus.respLayer2.occupancy             1644000                       # Layer occupancy (ticks)
 system.iobus.respLayer2.utilization               0.0                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.branchPred.lookups                85854110                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          85854110                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            890492                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             79431123                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                77651636                       # Number of BTB hits
+system.cpu.branchPred.lookups                86877356                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          86877356                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            902542                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             80133511                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                78163225                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             97.759711                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 1460640                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect             181048                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             97.541246                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 1555611                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect             178528                       # Number of incorrect RAS predictions.
 system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
-system.cpu.numCycles                        452853570                       # number of cpu cycles simulated
+system.cpu.numCycles                        449309558                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           25683785                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      423946474                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    85854110                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           79112276                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     162997927                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 4233083                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles                     105681                       # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.BlockedCycles               69250991                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                42777                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles         91487                       # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles          266                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                   8611652                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                409614                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes                    2534                       # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples          261469410                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              3.201181                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.413215                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles           27651859                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      428959611                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    86877356                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           79718836                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     417653044                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 1892712                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles                     141479                       # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles                49827                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles        205407                       # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles       127451                       # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles          417                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                   9182196                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                444767                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes                    5009                       # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples          446775840                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.894723                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.051895                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 98890192     37.82%     37.82% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  1558006      0.60%     38.42% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 71842115     27.48%     65.89% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                   921619      0.35%     66.25% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  1585920      0.61%     66.85% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  2431144      0.93%     67.78% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  1036910      0.40%     68.18% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  1345104      0.51%     68.69% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                 81858400     31.31%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                281257253     62.95%     62.95% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  2318085      0.52%     63.47% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 72134929     16.15%     79.62% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  1613434      0.36%     79.98% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  2149929      0.48%     80.46% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  2328393      0.52%     80.98% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  1530698      0.34%     81.32% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  1882713      0.42%     81.74% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 81560406     18.26%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            261469410                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.189585                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.936167                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 29046589                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              66961601                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 159616384                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               2548340                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                3296496                       # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts              834624632                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                   895                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                3296496                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 31320829                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                35759496                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles       12826241                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 159575235                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              18691113                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              831621243                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                271968                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                7201596                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                 103405                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                9490411                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands           993545092                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            1805477878                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       1109904628                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups               111                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps             963933701                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 29611389                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts             457228                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts         464601                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  24223020                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             16966534                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores             9968316                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           1221781                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores           988150                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  826572087                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded             1194475                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 821819105                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            208862                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        20915933                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     32275833                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved         139879                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     261469410                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         3.143079                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        2.407689                       # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total            446775840                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.193357                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.954708                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 23023114                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             264661195                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 150717323                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               7427852                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                 946356                       # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts              838299668                       # Number of instructions handled by decode
+system.cpu.rename.SquashCycles                 946356                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 25879231                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles               223164657                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles       13208529                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 154609969                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              28967098                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              834812666                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                479412                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents               12346095                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                 191662                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents               13684658                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands           997151203                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            1813191058                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       1114665342                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups               185                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps             963963482                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                 33187719                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts             468373                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts         472487                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  39006494                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             17336272                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            10188880                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           1345741                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          1123547                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  829275749                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded             1209290                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 824021244                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            242579                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        23492118                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     36175819                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved         154222                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     446775840                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.844373                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        2.418251                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            76437702     29.23%     29.23% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            14614697      5.59%     34.82% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            10065724      3.85%     38.67% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3             7027094      2.69%     41.36% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            75658650     28.94%     70.30% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             3979218      1.52%     71.82% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6            72575299     27.76%     99.58% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7              879014      0.34%     99.91% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              232012      0.09%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           262561849     58.77%     58.77% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            13882888      3.11%     61.88% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            10086827      2.26%     64.13% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3             6921999      1.55%     65.68% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            74315249     16.63%     82.32% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             4452451      1.00%     83.31% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6            72780033     16.29%     99.60% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             1201096      0.27%     99.87% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              573448      0.13%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       261469410                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       446775840                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                  395534     35.48%     35.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                    246      0.02%     35.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                     260      0.02%     35.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     35.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     35.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     35.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     35.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     35.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     35.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     35.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     35.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     35.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     35.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     35.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     35.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     35.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     35.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     35.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     35.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     35.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     35.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     35.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     35.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     35.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     35.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     35.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     35.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     35.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     35.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                 578947     51.93%     87.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                139812     12.54%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                 1974933     71.79%     71.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                    151      0.01%     71.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                     606      0.02%     71.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     71.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     71.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     71.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     71.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     71.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     71.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     71.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     71.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     71.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     71.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     71.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     71.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     71.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     71.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     71.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     71.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     71.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     71.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     71.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     71.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     71.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     71.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     71.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     71.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     71.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     71.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                 614459     22.33%     94.15% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                161026      5.85%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass            313841      0.04%      0.04% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             794169455     96.64%     96.67% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult               150148      0.02%     96.69% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                125336      0.02%     96.71% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     96.71% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     96.71% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     96.71% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     96.71% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     96.71% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     96.71% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     96.71% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     96.71% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     96.71% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     96.71% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     96.71% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     96.71% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     96.71% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     96.71% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     96.71% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     96.71% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     96.71% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     96.71% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     96.71% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     96.71% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     96.71% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     96.71% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     96.71% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     96.71% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     96.71% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     96.71% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             17790783      2.16%     98.87% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite             9269542      1.13%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass            292875      0.04%      0.04% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             795624977     96.55%     96.59% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult               150449      0.02%     96.61% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                125321      0.02%     96.62% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     96.62% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     96.62% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     96.62% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     96.62% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     96.62% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     96.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     96.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     96.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     96.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     96.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     96.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     96.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     96.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     96.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     96.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     96.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     96.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     96.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     96.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     96.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     96.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     96.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     96.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     96.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     96.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     96.62% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             18429310      2.24%     98.86% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite             9398312      1.14%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              821819105                       # Type of FU issued
-system.cpu.iq.rate                           1.814757                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     1114799                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.001357                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         1906543911                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         848693742                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    817833447                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads                 176                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes                182                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses           50                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              822619981                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                      82                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads          1787791                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              824021244                       # Type of FU issued
+system.cpu.iq.rate                           1.833972                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     2751175                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.003339                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         2097811864                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         853989635                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    819447653                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads                 217                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes                292                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses           60                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              826479445                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                      99                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads          1882501                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      2974113                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        16000                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        13012                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      1545780                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      3343168                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        14800                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        14469                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      1764190                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads      1935112                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked         35450                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads      2224524                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked         72794                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                3296496                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                15966541                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles              12762115                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           827766562                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            204474                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              16966534                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts              9968316                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts             698992                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                1766485                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents              10560079                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          13012                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         503157                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       519909                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              1023066                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             820377360                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              17471183                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           1441744                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                 946356                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles               205489198                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles               9385897                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           830485039                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            188872                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts              17336272                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             10188880                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts             713065                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                 415930                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents               8070911                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          14469                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         518528                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       536731                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              1055259                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             822394413                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              18030482                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           1492613                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                             0                       # number of nop insts executed
-system.cpu.iew.exec_refs                     26545601                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 83164783                       # Number of branches executed
-system.cpu.iew.exec_stores                    9074418                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.811573                       # Inst execution rate
-system.cpu.iew.wb_sent                      819943769                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     817833497                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 640559141                       # num instructions producing a value
-system.cpu.iew.wb_consumers                1047723157                       # num instructions consuming a value
+system.cpu.iew.exec_refs                     27200783                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 83281301                       # Number of branches executed
+system.cpu.iew.exec_stores                    9170301                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.830351                       # Inst execution rate
+system.cpu.iew.wb_sent                      821885746                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     819447713                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 640810294                       # num instructions producing a value
+system.cpu.iew.wb_consumers                1050192124                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.805956                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.611382                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.823793                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.610184                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts        21640086                       # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls         1054596                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            900184                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    258172914                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     3.122020                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.868515                       # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts        24342460                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls         1055068                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts            914367                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    443118746                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.819035                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.675250                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     87519981     33.90%     33.90% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     11178946      4.33%     38.23% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2      3524931      1.37%     39.60% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     74556840     28.88%     68.47% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      2487891      0.96%     69.44% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      1503617      0.58%     70.02% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6       865491      0.34%     70.36% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7     70822706     27.43%     97.79% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      5712511      2.21%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    272366005     61.47%     61.47% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     11194221      2.53%     63.99% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      3590232      0.81%     64.80% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     74521712     16.82%     81.62% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      2434404      0.55%     82.17% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      1603700      0.36%     82.53% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6       952599      0.21%     82.75% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7     71009883     16.03%     98.77% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      5445990      1.23%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    258172914                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts            407759509                       # Number of instructions committed
-system.cpu.commit.committedOps              806020953                       # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total    443118746                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts            407773893                       # Number of instructions committed
+system.cpu.commit.committedOps              806048632                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                       22414956                       # Number of memory references committed
-system.cpu.commit.loads                      13992420                       # Number of loads committed
-system.cpu.commit.membars                      474659                       # Number of memory barriers committed
-system.cpu.commit.branches                   82156165                       # Number of branches committed
+system.cpu.commit.refs                       22417793                       # Number of memory references committed
+system.cpu.commit.loads                      13993103                       # Number of loads committed
+system.cpu.commit.membars                      474875                       # Number of memory barriers committed
+system.cpu.commit.branches                   82158924                       # Number of branches committed
 system.cpu.commit.fp_insts                          0                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                 734866809                       # Number of committed integer instructions.
-system.cpu.commit.function_calls              1155346                       # Number of function calls committed.
-system.cpu.commit.op_class_0::No_OpClass       174342      0.02%      0.02% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu        783165220     97.16%     97.19% # Class of committed instruction
-system.cpu.commit.op_class_0::IntMult          144784      0.02%     97.20% # Class of committed instruction
-system.cpu.commit.op_class_0::IntDiv           121651      0.02%     97.22% # Class of committed instruction
+system.cpu.commit.int_insts                 734892496                       # Number of committed integer instructions.
+system.cpu.commit.function_calls              1155452                       # Number of function calls committed.
+system.cpu.commit.op_class_0::No_OpClass       174150      0.02%      0.02% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu        783190673     97.16%     97.19% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult          144749      0.02%     97.20% # Class of committed instruction
+system.cpu.commit.op_class_0::IntDiv           121267      0.02%     97.22% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatAdd              0      0.00%     97.22% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatCmp              0      0.00%     97.22% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatCvt              0      0.00%     97.22% # Class of committed instruction
@@ -832,213 +824,214 @@ system.cpu.commit.op_class_0::SimdFloatMisc            0      0.00%     97.22% #
 system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     97.22% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     97.22% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     97.22% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead        13992420      1.74%     98.96% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite        8422536      1.04%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead        13993103      1.74%     98.95% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite        8424690      1.05%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total         806020953                       # Class of committed instruction
-system.cpu.commit.bw_lim_events               5712511                       # number cycles where commit BW limit reached
+system.cpu.commit.op_class_0::total         806048632                       # Class of committed instruction
+system.cpu.commit.bw_lim_events               5445990                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                   1080043164                       # The number of ROB reads
-system.cpu.rob.rob_writes                  1658634797                       # The number of ROB writes
-system.cpu.timesIdled                         1275471                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                       191384160                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles                   9823003775                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts                   407759509                       # Number of Instructions Simulated
-system.cpu.committedOps                     806020953                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               1.110590                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         1.110590                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.900422                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.900422                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               1089597141                       # number of integer regfile reads
-system.cpu.int_regfile_writes               654482969                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                        50                       # number of floating regfile reads
-system.cpu.cc_regfile_reads                 415870022                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                321677512                       # number of cc regfile writes
-system.cpu.misc_regfile_reads               264445635                       # number of misc regfile reads
-system.cpu.misc_regfile_writes                 402422                       # number of misc regfile writes
-system.cpu.toL2Bus.throughput                53724216                       # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq        3026047                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       3025482                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteReq         13764                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteResp        13764                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      1581183                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq         2322                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp         2322                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       334322                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       287613                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::BadAddressError            8                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1928223                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      6126020                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side        18717                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       156212                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           8229172                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     61697728                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    207710542                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       574144                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side      5436928                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total      275419342                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus         275396046                       # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus       635008                       # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy     4043112921                       # Layer occupancy (ticks)
+system.cpu.rob.rob_reads                   1267985613                       # The number of ROB reads
+system.cpu.rob.rob_writes                  1664458820                       # The number of ROB writes
+system.cpu.timesIdled                          297027                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                         2533718                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles                   9810435335                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts                   407773893                       # Number of Instructions Simulated
+system.cpu.committedOps                     806048632                       # Number of Ops (including micro ops) Simulated
+system.cpu.cpi                               1.101860                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         1.101860                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.907557                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.907557                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               1092201088                       # number of integer regfile reads
+system.cpu.int_regfile_writes               655889202                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                        60                       # number of floating regfile reads
+system.cpu.cc_regfile_reads                 416095530                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                321948927                       # number of cc regfile writes
+system.cpu.misc_regfile_reads               265553416                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                 402606                       # number of misc regfile writes
+system.cpu.toL2Bus.throughput                55008962                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq        3071462                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       3070914                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteReq         13776                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteResp        13776                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback      1585837                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteInvalidateReq        46724                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq         2242                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp         2242                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       287030                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       287030                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::BadAddressError           11                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1996026                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      6130754                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side        30653                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       164256                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           8321689                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     63869504                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    207903453                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       978368                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side      5729920                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total      278481245                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus         278457117                       # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus      3731904                       # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy     4072507880                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy       546000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.occupancy       565500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy    1449735220                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy    1501244795                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    3140330868                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    3142652109                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy      14620748                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.occupancy      23061226                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy     106945143                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy     112150627                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.cpu.icache.tags.replacements            963566                       # number of replacements
-system.cpu.icache.tags.tagsinuse           509.311037                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs             7590970                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs            964078                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs              7.873813                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle      147613206250                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   509.311037                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.994748                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.994748                       # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements            997506                       # number of replacements
+system.cpu.icache.tags.tagsinuse           509.982226                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs             8120756                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs            998018                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs              8.136883                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle      147598371250                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   509.982226                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.996059                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.996059                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          101                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          231                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          180                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          126                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          246                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          140                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses           9575846                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses          9575846                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst      7590970                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total         7590970                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst       7590970                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total          7590970                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst      7590970                       # number of overall hits
-system.cpu.icache.overall_hits::total         7590970                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst      1020680                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total       1020680                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst      1020680                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total        1020680                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst      1020680                       # number of overall misses
-system.cpu.icache.overall_misses::total       1020680                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  14179701612                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  14179701612                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  14179701612                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  14179701612                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  14179701612                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  14179701612                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst      8611650                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total      8611650                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst      8611650                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total      8611650                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst      8611650                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total      8611650                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.118523                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.118523                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.118523                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.118523                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.118523                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.118523                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13892.406643                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13892.406643                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13892.406643                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13892.406643                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13892.406643                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13892.406643                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs         4723                       # number of cycles access was blocked
+system.cpu.icache.tags.tag_accesses          10180257                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         10180257                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst      8120756                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total         8120756                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst       8120756                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total          8120756                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst      8120756                       # number of overall hits
+system.cpu.icache.overall_hits::total         8120756                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst      1061436                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total       1061436                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst      1061436                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total        1061436                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst      1061436                       # number of overall misses
+system.cpu.icache.overall_misses::total       1061436                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  14736249127                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  14736249127                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  14736249127                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  14736249127                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  14736249127                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  14736249127                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst      9182192                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total      9182192                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst      9182192                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total      9182192                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst      9182192                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total      9182192                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.115597                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.115597                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.115597                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.115597                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.115597                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.115597                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13883.313857                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13883.313857                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13883.313857                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13883.313857                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13883.313857                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13883.313857                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs         6673                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs               198                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs               292                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    23.853535                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    22.852740                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst        56484                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total        56484                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst        56484                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total        56484                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst        56484                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total        56484                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst       964196                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total       964196                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst       964196                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total       964196                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst       964196                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total       964196                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  11690907021                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  11690907021                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst  11690907021                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total  11690907021                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst  11690907021                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total  11690907021                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.111964                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.111964                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.111964                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.111964                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.111964                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.111964                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12125.031654                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12125.031654                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12125.031654                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 12125.031654                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12125.031654                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 12125.031654                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst        63371                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total        63371                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst        63371                       # number of demand (read+write) MSHR hits
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+system.cpu.icache.overall_mshr_hits::cpu.inst        63371                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total        63371                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst       998065                       # number of ReadReq MSHR misses
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+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  12095503951                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total  12095503951                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst  12095503951                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total  12095503951                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst  12095503951                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total  12095503951                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.108696                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.108696                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.108696                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.108696                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.108696                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.108696                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12118.954127                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12118.954127                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12118.954127                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 12118.954127                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12118.954127                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 12118.954127                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.itb_walker_cache.tags.replacements         8862                       # number of replacements
-system.cpu.itb_walker_cache.tags.tagsinuse     6.026427                       # Cycle average of tags in use
-system.cpu.itb_walker_cache.tags.total_refs        19635                       # Total number of references to valid blocks.
-system.cpu.itb_walker_cache.tags.sampled_refs         8877                       # Sample count of references to valid blocks.
-system.cpu.itb_walker_cache.tags.avg_refs     2.211896                       # Average number of references to valid blocks.
-system.cpu.itb_walker_cache.tags.warmup_cycle 5109382719500                       # Cycle when the warmup percentage was hit.
-system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker     6.026427                       # Average occupied blocks per requestor
-system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker     0.376652                       # Average percentage of cache occupancy
-system.cpu.itb_walker_cache.tags.occ_percent::total     0.376652                       # Average percentage of cache occupancy
+system.cpu.itb_walker_cache.tags.replacements        14491                       # number of replacements
+system.cpu.itb_walker_cache.tags.tagsinuse     6.005977                       # Cycle average of tags in use
+system.cpu.itb_walker_cache.tags.total_refs        26506                       # Total number of references to valid blocks.
+system.cpu.itb_walker_cache.tags.sampled_refs        14506                       # Sample count of references to valid blocks.
+system.cpu.itb_walker_cache.tags.avg_refs     1.827244                       # Average number of references to valid blocks.
+system.cpu.itb_walker_cache.tags.warmup_cycle 5104029760000                       # Cycle when the warmup percentage was hit.
+system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker     6.005977                       # Average occupied blocks per requestor
+system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker     0.375374                       # Average percentage of cache occupancy
+system.cpu.itb_walker_cache.tags.occ_percent::total     0.375374                       # Average percentage of cache occupancy
 system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024           15                       # Occupied blocks per task id
 system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0            9                       # Occupied blocks per task id
-system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1            4                       # Occupied blocks per task id
-system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2            2                       # Occupied blocks per task id
+system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1            3                       # Occupied blocks per task id
+system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2            3                       # Occupied blocks per task id
 system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024     0.937500                       # Percentage of cache occupancy per task id
-system.cpu.itb_walker_cache.tags.tag_accesses        68718                       # Number of tag accesses
-system.cpu.itb_walker_cache.tags.data_accesses        68718                       # Number of data accesses
-system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker        19738                       # number of ReadReq hits
-system.cpu.itb_walker_cache.ReadReq_hits::total        19738                       # number of ReadReq hits
+system.cpu.itb_walker_cache.tags.tag_accesses        99110                       # Number of tag accesses
+system.cpu.itb_walker_cache.tags.data_accesses        99110                       # Number of data accesses
+system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker        26504                       # number of ReadReq hits
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 system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker            2                       # number of WriteReq hits
 system.cpu.itb_walker_cache.WriteReq_hits::total            2                       # number of WriteReq hits
-system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker        19740                       # number of demand (read+write) hits
-system.cpu.itb_walker_cache.demand_hits::total        19740                       # number of demand (read+write) hits
-system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker        19740                       # number of overall hits
-system.cpu.itb_walker_cache.overall_hits::total        19740                       # number of overall hits
-system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker         9746                       # number of ReadReq misses
-system.cpu.itb_walker_cache.ReadReq_misses::total         9746                       # number of ReadReq misses
-system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker         9746                       # number of demand (read+write) misses
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-system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker         9746                       # number of overall misses
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-system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker    105945749                       # number of ReadReq miss cycles
-system.cpu.itb_walker_cache.ReadReq_miss_latency::total    105945749                       # number of ReadReq miss cycles
-system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker    105945749                       # number of demand (read+write) miss cycles
-system.cpu.itb_walker_cache.demand_miss_latency::total    105945749                       # number of demand (read+write) miss cycles
-system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker    105945749                       # number of overall miss cycles
-system.cpu.itb_walker_cache.overall_miss_latency::total    105945749                       # number of overall miss cycles
-system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker        29484                       # number of ReadReq accesses(hits+misses)
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+system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker    173869741                       # number of ReadReq miss cycles
+system.cpu.itb_walker_cache.ReadReq_miss_latency::total    173869741                       # number of ReadReq miss cycles
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+system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker        41870                       # number of ReadReq accesses(hits+misses)
+system.cpu.itb_walker_cache.ReadReq_accesses::total        41870                       # number of ReadReq accesses(hits+misses)
 system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker            2                       # number of WriteReq accesses(hits+misses)
 system.cpu.itb_walker_cache.WriteReq_accesses::total            2                       # number of WriteReq accesses(hits+misses)
-system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker        29486                       # number of demand (read+write) accesses
-system.cpu.itb_walker_cache.demand_accesses::total        29486                       # number of demand (read+write) accesses
-system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker        29486                       # number of overall (read+write) accesses
-system.cpu.itb_walker_cache.overall_accesses::total        29486                       # number of overall (read+write) accesses
-system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker     0.330552                       # miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.ReadReq_miss_rate::total     0.330552                       # miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker     0.330530                       # miss rate for demand accesses
-system.cpu.itb_walker_cache.demand_miss_rate::total     0.330530                       # miss rate for demand accesses
-system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker     0.330530                       # miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_miss_rate::total     0.330530                       # miss rate for overall accesses
-system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 10870.690437                       # average ReadReq miss latency
-system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 10870.690437                       # average ReadReq miss latency
-system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 10870.690437                       # average overall miss latency
-system.cpu.itb_walker_cache.demand_avg_miss_latency::total 10870.690437                       # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 10870.690437                       # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_miss_latency::total 10870.690437                       # average overall miss latency
+system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker        41872                       # number of demand (read+write) accesses
+system.cpu.itb_walker_cache.demand_accesses::total        41872                       # number of demand (read+write) accesses
+system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker        41872                       # number of overall (read+write) accesses
+system.cpu.itb_walker_cache.overall_accesses::total        41872                       # number of overall (read+write) accesses
+system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker     0.366993                       # miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.ReadReq_miss_rate::total     0.366993                       # miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker     0.366976                       # miss rate for demand accesses
+system.cpu.itb_walker_cache.demand_miss_rate::total     0.366976                       # miss rate for demand accesses
+system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker     0.366976                       # miss rate for overall accesses
+system.cpu.itb_walker_cache.overall_miss_rate::total     0.366976                       # miss rate for overall accesses
+system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11315.224587                       # average ReadReq miss latency
+system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11315.224587                       # average ReadReq miss latency
+system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11315.224587                       # average overall miss latency
+system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11315.224587                       # average overall miss latency
+system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11315.224587                       # average overall miss latency
+system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11315.224587                       # average overall miss latency
 system.cpu.itb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.itb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.itb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
@@ -1047,85 +1040,85 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.itb_walker_cache.fast_writes             0                       # number of fast writes performed
 system.cpu.itb_walker_cache.cache_copies            0                       # number of cache copies performed
-system.cpu.itb_walker_cache.writebacks::writebacks         1636                       # number of writebacks
-system.cpu.itb_walker_cache.writebacks::total         1636                       # number of writebacks
-system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker         9746                       # number of ReadReq MSHR misses
-system.cpu.itb_walker_cache.ReadReq_mshr_misses::total         9746                       # number of ReadReq MSHR misses
-system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker         9746                       # number of demand (read+write) MSHR misses
-system.cpu.itb_walker_cache.demand_mshr_misses::total         9746                       # number of demand (read+write) MSHR misses
-system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker         9746                       # number of overall MSHR misses
-system.cpu.itb_walker_cache.overall_mshr_misses::total         9746                       # number of overall MSHR misses
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker     86450253                       # number of ReadReq MSHR miss cycles
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total     86450253                       # number of ReadReq MSHR miss cycles
-system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker     86450253                       # number of demand (read+write) MSHR miss cycles
-system.cpu.itb_walker_cache.demand_mshr_miss_latency::total     86450253                       # number of demand (read+write) MSHR miss cycles
-system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker     86450253                       # number of overall MSHR miss cycles
-system.cpu.itb_walker_cache.overall_mshr_miss_latency::total     86450253                       # number of overall MSHR miss cycles
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.330552                       # mshr miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total     0.330552                       # mshr miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker     0.330530                       # mshr miss rate for demand accesses
-system.cpu.itb_walker_cache.demand_mshr_miss_rate::total     0.330530                       # mshr miss rate for demand accesses
-system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker     0.330530                       # mshr miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_mshr_miss_rate::total     0.330530                       # mshr miss rate for overall accesses
-system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker  8870.331726                       # average ReadReq mshr miss latency
-system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total  8870.331726                       # average ReadReq mshr miss latency
-system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker  8870.331726                       # average overall mshr miss latency
-system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total  8870.331726                       # average overall mshr miss latency
-system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker  8870.331726                       # average overall mshr miss latency
-system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total  8870.331726                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.writebacks::writebacks         2963                       # number of writebacks
+system.cpu.itb_walker_cache.writebacks::total         2963                       # number of writebacks
+system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker        15366                       # number of ReadReq MSHR misses
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+system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker        15366                       # number of demand (read+write) MSHR misses
+system.cpu.itb_walker_cache.demand_mshr_misses::total        15366                       # number of demand (read+write) MSHR misses
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+system.cpu.itb_walker_cache.overall_mshr_misses::total        15366                       # number of overall MSHR misses
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker    143113289                       # number of ReadReq MSHR miss cycles
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total    143113289                       # number of ReadReq MSHR miss cycles
+system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker    143113289                       # number of demand (read+write) MSHR miss cycles
+system.cpu.itb_walker_cache.demand_mshr_miss_latency::total    143113289                       # number of demand (read+write) MSHR miss cycles
+system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker    143113289                       # number of overall MSHR miss cycles
+system.cpu.itb_walker_cache.overall_mshr_miss_latency::total    143113289                       # number of overall MSHR miss cycles
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.366993                       # mshr miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total     0.366993                       # mshr miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker     0.366976                       # mshr miss rate for demand accesses
+system.cpu.itb_walker_cache.demand_mshr_miss_rate::total     0.366976                       # mshr miss rate for demand accesses
+system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker     0.366976                       # mshr miss rate for overall accesses
+system.cpu.itb_walker_cache.overall_mshr_miss_rate::total     0.366976                       # mshr miss rate for overall accesses
+system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker  9313.633281                       # average ReadReq mshr miss latency
+system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total  9313.633281                       # average ReadReq mshr miss latency
+system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker  9313.633281                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total  9313.633281                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker  9313.633281                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total  9313.633281                       # average overall mshr miss latency
 system.cpu.itb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
-system.cpu.dtb_walker_cache.tags.replacements        70197                       # number of replacements
-system.cpu.dtb_walker_cache.tags.tagsinuse    14.820412                       # Cycle average of tags in use
-system.cpu.dtb_walker_cache.tags.total_refs        92434                       # Total number of references to valid blocks.
-system.cpu.dtb_walker_cache.tags.sampled_refs        70211                       # Sample count of references to valid blocks.
-system.cpu.dtb_walker_cache.tags.avg_refs     1.316517                       # Average number of references to valid blocks.
-system.cpu.dtb_walker_cache.tags.warmup_cycle 5101611575500                       # Cycle when the warmup percentage was hit.
-system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker    14.820412                       # Average occupied blocks per requestor
-system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker     0.926276                       # Average percentage of cache occupancy
-system.cpu.dtb_walker_cache.tags.occ_percent::total     0.926276                       # Average percentage of cache occupancy
-system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024           14                       # Occupied blocks per task id
-system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0            7                       # Occupied blocks per task id
-system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1            5                       # Occupied blocks per task id
+system.cpu.dtb_walker_cache.tags.replacements        73624                       # number of replacements
+system.cpu.dtb_walker_cache.tags.tagsinuse    15.198399                       # Cycle average of tags in use
+system.cpu.dtb_walker_cache.tags.total_refs       115934                       # Total number of references to valid blocks.
+system.cpu.dtb_walker_cache.tags.sampled_refs        73640                       # Sample count of references to valid blocks.
+system.cpu.dtb_walker_cache.tags.avg_refs     1.574335                       # Average number of references to valid blocks.
+system.cpu.dtb_walker_cache.tags.warmup_cycle 3233327929250                       # Cycle when the warmup percentage was hit.
+system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker    15.198399                       # Average occupied blocks per requestor
+system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker     0.949900                       # Average percentage of cache occupancy
+system.cpu.dtb_walker_cache.tags.occ_percent::total     0.949900                       # Average percentage of cache occupancy
+system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024           16                       # Occupied blocks per task id
+system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0            8                       # Occupied blocks per task id
+system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1            6                       # Occupied blocks per task id
 system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2            2                       # Occupied blocks per task id
-system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024     0.875000                       # Percentage of cache occupancy per task id
-system.cpu.dtb_walker_cache.tags.tag_accesses       398660                       # Number of tag accesses
-system.cpu.dtb_walker_cache.tags.data_accesses       398660                       # Number of data accesses
-system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker        92440                       # number of ReadReq hits
-system.cpu.dtb_walker_cache.ReadReq_hits::total        92440                       # number of ReadReq hits
-system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker        92440                       # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.demand_hits::total        92440                       # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker        92440                       # number of overall hits
-system.cpu.dtb_walker_cache.overall_hits::total        92440                       # number of overall hits
-system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker        71260                       # number of ReadReq misses
-system.cpu.dtb_walker_cache.ReadReq_misses::total        71260                       # number of ReadReq misses
-system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker        71260                       # number of demand (read+write) misses
-system.cpu.dtb_walker_cache.demand_misses::total        71260                       # number of demand (read+write) misses
-system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker        71260                       # number of overall misses
-system.cpu.dtb_walker_cache.overall_misses::total        71260                       # number of overall misses
-system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker    875246716                       # number of ReadReq miss cycles
-system.cpu.dtb_walker_cache.ReadReq_miss_latency::total    875246716                       # number of ReadReq miss cycles
-system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker    875246716                       # number of demand (read+write) miss cycles
-system.cpu.dtb_walker_cache.demand_miss_latency::total    875246716                       # number of demand (read+write) miss cycles
-system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker    875246716                       # number of overall miss cycles
-system.cpu.dtb_walker_cache.overall_miss_latency::total    875246716                       # number of overall miss cycles
-system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker       163700                       # number of ReadReq accesses(hits+misses)
-system.cpu.dtb_walker_cache.ReadReq_accesses::total       163700                       # number of ReadReq accesses(hits+misses)
-system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker       163700                       # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.demand_accesses::total       163700                       # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker       163700                       # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::total       163700                       # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker     0.435308                       # miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.ReadReq_miss_rate::total     0.435308                       # miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker     0.435308                       # miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::total     0.435308                       # miss rate for demand accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker     0.435308                       # miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::total     0.435308                       # miss rate for overall accesses
-system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12282.440584                       # average ReadReq miss latency
-system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12282.440584                       # average ReadReq miss latency
-system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12282.440584                       # average overall miss latency
-system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12282.440584                       # average overall miss latency
-system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12282.440584                       # average overall miss latency
-system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12282.440584                       # average overall miss latency
+system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.dtb_walker_cache.tags.tag_accesses       456046                       # Number of tag accesses
+system.cpu.dtb_walker_cache.tags.data_accesses       456046                       # Number of data accesses
+system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker       115934                       # number of ReadReq hits
+system.cpu.dtb_walker_cache.ReadReq_hits::total       115934                       # number of ReadReq hits
+system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker       115934                       # number of demand (read+write) hits
+system.cpu.dtb_walker_cache.demand_hits::total       115934                       # number of demand (read+write) hits
+system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker       115934                       # number of overall hits
+system.cpu.dtb_walker_cache.overall_hits::total       115934                       # number of overall hits
+system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker        74726                       # number of ReadReq misses
+system.cpu.dtb_walker_cache.ReadReq_misses::total        74726                       # number of ReadReq misses
+system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker        74726                       # number of demand (read+write) misses
+system.cpu.dtb_walker_cache.demand_misses::total        74726                       # number of demand (read+write) misses
+system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker        74726                       # number of overall misses
+system.cpu.dtb_walker_cache.overall_misses::total        74726                       # number of overall misses
+system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker    911611211                       # number of ReadReq miss cycles
+system.cpu.dtb_walker_cache.ReadReq_miss_latency::total    911611211                       # number of ReadReq miss cycles
+system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker    911611211                       # number of demand (read+write) miss cycles
+system.cpu.dtb_walker_cache.demand_miss_latency::total    911611211                       # number of demand (read+write) miss cycles
+system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker    911611211                       # number of overall miss cycles
+system.cpu.dtb_walker_cache.overall_miss_latency::total    911611211                       # number of overall miss cycles
+system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker       190660                       # number of ReadReq accesses(hits+misses)
+system.cpu.dtb_walker_cache.ReadReq_accesses::total       190660                       # number of ReadReq accesses(hits+misses)
+system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker       190660                       # number of demand (read+write) accesses
+system.cpu.dtb_walker_cache.demand_accesses::total       190660                       # number of demand (read+write) accesses
+system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker       190660                       # number of overall (read+write) accesses
+system.cpu.dtb_walker_cache.overall_accesses::total       190660                       # number of overall (read+write) accesses
+system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker     0.391933                       # miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.ReadReq_miss_rate::total     0.391933                       # miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker     0.391933                       # miss rate for demand accesses
+system.cpu.dtb_walker_cache.demand_miss_rate::total     0.391933                       # miss rate for demand accesses
+system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker     0.391933                       # miss rate for overall accesses
+system.cpu.dtb_walker_cache.overall_miss_rate::total     0.391933                       # miss rate for overall accesses
+system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12199.384565                       # average ReadReq miss latency
+system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12199.384565                       # average ReadReq miss latency
+system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12199.384565                       # average overall miss latency
+system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12199.384565                       # average overall miss latency
+system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12199.384565                       # average overall miss latency
+system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12199.384565                       # average overall miss latency
 system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dtb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dtb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
@@ -1134,153 +1127,169 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dtb_walker_cache.fast_writes             0                       # number of fast writes performed
 system.cpu.dtb_walker_cache.cache_copies            0                       # number of cache copies performed
-system.cpu.dtb_walker_cache.writebacks::writebacks        20047                       # number of writebacks
-system.cpu.dtb_walker_cache.writebacks::total        20047                       # number of writebacks
-system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker        71260                       # number of ReadReq MSHR misses
-system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total        71260                       # number of ReadReq MSHR misses
-system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker        71260                       # number of demand (read+write) MSHR misses
-system.cpu.dtb_walker_cache.demand_mshr_misses::total        71260                       # number of demand (read+write) MSHR misses
-system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker        71260                       # number of overall MSHR misses
-system.cpu.dtb_walker_cache.overall_mshr_misses::total        71260                       # number of overall MSHR misses
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker    732616430                       # number of ReadReq MSHR miss cycles
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total    732616430                       # number of ReadReq MSHR miss cycles
-system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker    732616430                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total    732616430                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker    732616430                       # number of overall MSHR miss cycles
-system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total    732616430                       # number of overall MSHR miss cycles
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.435308                       # mshr miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total     0.435308                       # mshr miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker     0.435308                       # mshr miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total     0.435308                       # mshr miss rate for demand accesses
-system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker     0.435308                       # mshr miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total     0.435308                       # mshr miss rate for overall accesses
-system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10280.892927                       # average ReadReq mshr miss latency
-system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10280.892927                       # average ReadReq mshr miss latency
-system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10280.892927                       # average overall mshr miss latency
-system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10280.892927                       # average overall mshr miss latency
-system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10280.892927                       # average overall mshr miss latency
-system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10280.892927                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.writebacks::writebacks        22207                       # number of writebacks
+system.cpu.dtb_walker_cache.writebacks::total        22207                       # number of writebacks
+system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker        74726                       # number of ReadReq MSHR misses
+system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total        74726                       # number of ReadReq MSHR misses
+system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker        74726                       # number of demand (read+write) MSHR misses
+system.cpu.dtb_walker_cache.demand_mshr_misses::total        74726                       # number of demand (read+write) MSHR misses
+system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker        74726                       # number of overall MSHR misses
+system.cpu.dtb_walker_cache.overall_mshr_misses::total        74726                       # number of overall MSHR misses
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker    762035957                       # number of ReadReq MSHR miss cycles
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total    762035957                       # number of ReadReq MSHR miss cycles
+system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker    762035957                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total    762035957                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker    762035957                       # number of overall MSHR miss cycles
+system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total    762035957                       # number of overall MSHR miss cycles
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.391933                       # mshr miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total     0.391933                       # mshr miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker     0.391933                       # mshr miss rate for demand accesses
+system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total     0.391933                       # mshr miss rate for demand accesses
+system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker     0.391933                       # mshr miss rate for overall accesses
+system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total     0.391933                       # mshr miss rate for overall accesses
+system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10197.735152                       # average ReadReq mshr miss latency
+system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10197.735152                       # average ReadReq mshr miss latency
+system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10197.735152                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10197.735152                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10197.735152                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10197.735152                       # average overall mshr miss latency
 system.cpu.dtb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements           1657713                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.996506                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            19009946                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           1658225                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             11.464033                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle          39778250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.996506                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999993                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999993                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements           1659582                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.996805                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            19130892                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           1660094                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             11.523981                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle          37454250                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.996805                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.999994                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999994                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          164                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          328                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          224                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          268                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::2           20                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          87793833                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         87793833                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     10909808                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        10909808                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      8097329                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        8097329                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data      19007137                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         19007137                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     19007137                       # number of overall hits
-system.cpu.dcache.overall_hits::total        19007137                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      2211100                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       2211100                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       315662                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       315662                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data      2526762                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        2526762                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      2526762                       # number of overall misses
-system.cpu.dcache.overall_misses::total       2526762                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  32878750930                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  32878750930                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  12078727781                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  12078727781                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  44957478711                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  44957478711                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  44957478711                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  44957478711                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     13120908                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     13120908                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data      8412991                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total      8412991                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     21533899                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     21533899                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     21533899                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     21533899                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.168517                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.168517                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.037521                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.037521                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.117339                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.117339                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.117339                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.117339                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14869.861576                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 14869.861576                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38264.750844                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 38264.750844                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 17792.526052                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 17792.526052                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 17792.526052                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 17792.526052                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs       428041                       # number of cycles access was blocked
+system.cpu.dcache.tags.tag_accesses          88336593                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         88336593                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     10981431                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        10981431                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      8081664                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        8081664                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data        65027                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total         65027                       # number of SoftPFReq hits
+system.cpu.dcache.demand_hits::cpu.data      19063095                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         19063095                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     19128122                       # number of overall hits
+system.cpu.dcache.overall_hits::total        19128122                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      1801191                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       1801191                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       333463                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       333463                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data       406345                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total       406345                       # number of SoftPFReq misses
+system.cpu.dcache.demand_misses::cpu.data      2134654                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        2134654                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      2540999                       # number of overall misses
+system.cpu.dcache.overall_misses::total       2540999                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  26558757753                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  26558757753                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  12819840878                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  12819840878                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  39378598631                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  39378598631                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  39378598631                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  39378598631                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     12782622                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     12782622                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data      8415127                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total      8415127                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data       471372                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total       471372                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     21197749                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     21197749                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     21669121                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     21669121                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.140909                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.140909                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.039627                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.039627                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.862047                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.862047                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.100702                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.100702                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.117264                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.117264                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14745.109071                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 14745.109071                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38444.567697                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 38444.567697                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 18447.298078                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 18447.298078                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 15497.290094                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 15497.290094                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs       378253                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs             36530                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs             40145                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    11.717520                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     9.422170                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      1559500                       # number of writebacks
-system.cpu.dcache.writebacks::total           1559500                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       840350                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       840350                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data        25845                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total        25845                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data       866195                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       866195                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data       866195                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       866195                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1370750                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      1370750                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       289817                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       289817                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      1660567                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      1660567                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      1660567                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      1660567                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  17852039460                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  17852039460                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  11191134624                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  11191134624                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  29043174084                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  29043174084                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  29043174084                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  29043174084                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data  97363185500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total  97363185500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2536205500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2536205500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  99899391000                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total  99899391000                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.104471                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.104471                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.034449                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.034449                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.077114                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.077114                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.077114                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.077114                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13023.556053                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13023.556053                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38614.486466                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38614.486466                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17489.914038                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 17489.914038                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17489.914038                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 17489.914038                       # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks      1560667                       # number of writebacks
+system.cpu.dcache.writebacks::total           1560667                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       830878                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       830878                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data        44317                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total        44317                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data       875195                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       875195                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data       875195                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       875195                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       970313                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       970313                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       289146                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       289146                       # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data       402890                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total       402890                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      1259459                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      1259459                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      1662349                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      1662349                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  12260897766                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  12260897766                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  11156657127                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  11156657127                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   5584385500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   5584385500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  23417554893                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  23417554893                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  29001940393                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  29001940393                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data  97364665000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total  97364665000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2539423000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2539423000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  99904088000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total  99904088000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.075909                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.075909                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.034360                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.034360                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.854718                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.854718                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.059415                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.059415                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.076715                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.076715                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12636.023392                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12636.023392                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38584.857224                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38584.857224                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13860.819330                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13860.819330                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18593.344359                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 18593.344359                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17446.360778                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 17446.360778                       # average overall mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
@@ -1288,150 +1297,150 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements           112318                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        64820.835708                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            3791752                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           176203                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            21.519225                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements           112856                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        64816.166677                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            3836348                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           176998                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            21.674527                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 50598.140423                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker    13.189472                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.125676                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  2974.923375                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 11234.456763                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.772066                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000201                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::writebacks 50391.724726                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker    14.855148                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.135532                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  3265.471036                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 11143.980235                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.768917                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000227                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000002                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.045394                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.171424                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.989087                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        63885                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           59                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          534                       # Occupied blocks per task id
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-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.974808                       # Percentage of cache occupancy per task id
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+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker        75550                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76645.758370                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79053.039986                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 78297.616300                       # average ReadReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11495.307908                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11495.307908                       # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69625.027864                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69625.027864                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker        78125                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker        75550                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76645.758370                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71623.306286                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 72068.980930                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker        78125                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker        75550                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76645.758370                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71623.306286                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 72068.980930                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1440,99 +1449,99 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks       102635                       # number of writebacks
-system.cpu.l2cache.writebacks::total           102635                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            3                       # number of ReadReq MSHR hits
+system.cpu.l2cache.writebacks::writebacks       103139                       # number of writebacks
+system.cpu.l2cache.writebacks::total           103139                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            1                       # number of ReadReq MSHR hits
 system.cpu.l2cache.ReadReq_mshr_hits::cpu.data            2                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total            5                       # number of ReadReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst            3                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total            3                       # number of ReadReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst            1                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.demand_mshr_hits::cpu.data            2                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total            5                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst            3                       # number of overall MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total            3                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst            1                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::cpu.data            2                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total            5                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker           59                       # number of ReadReq MSHR misses
+system.cpu.l2cache.overall_mshr_hits::total            3                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker           66                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker            5                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        16184                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        36110                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total        52358                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         1531                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total         1531                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       133713                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       133713                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker           59                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        16396                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        35886                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total        52353                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         1429                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total         1429                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       133434                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       133434                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker           66                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            5                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst        16184                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       169823                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       186071                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker           59                       # number of overall MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst        16396                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       169320                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       185787                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker           66                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            5                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst        16184                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       169823                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       186071                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker      4137750                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.overall_mshr_misses::cpu.inst        16396                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       169320                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       185787                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker      4346250                       # number of ReadReq MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker       315250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst   1022850261                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   2399724551                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total   3427027812                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     16292512                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     16292512                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   7636829333                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   7636829333                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker      4137750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst   1051024500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   2391844499                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total   3447530499                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     14329428                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     14329428                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   7615118032                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   7615118032                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker      4346250                       # number of demand (read+write) MSHR miss cycles
 system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       315250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   1022850261                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  10036553884                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  11063857145                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker      4137750                       # number of overall MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   1051024500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  10006962531                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  11062648531                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker      4346250                       # number of overall MSHR miss cycles
 system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       315250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   1022850261                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  10036553884                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  11063857145                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data  89250074000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total  89250074000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   2370675000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   2370675000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  91620749000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total  91620749000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000909                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000682                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.016788                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.026357                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.021759                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.825337                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.825337                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.464940                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.464940                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000909                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000682                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.016788                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.102450                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.069072                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000909                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000682                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.016788                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.102450                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.069072                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 70131.355932                       # average ReadReq mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   1051024500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  10006962531                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  11062648531                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data  89251423000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total  89251423000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   2373128500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   2373128500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  91624551500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total  91624551500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000980                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000406                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.016429                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.026148                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.021368                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.823631                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.823631                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.464896                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.464896                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000980                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000406                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.016429                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.102033                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.067878                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000980                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000406                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.016429                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.102033                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.067878                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 65852.272727                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker        63050                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63201.326063                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66455.955442                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 65453.757057                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10641.745265                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10641.745265                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57113.589053                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57113.589053                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 70131.355932                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64102.494511                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66651.187065                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 65851.632170                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10027.591323                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10027.591323                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57070.297166                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57070.297166                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 65852.272727                       # average overall mshr miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker        63050                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63201.326063                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59100.085878                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59460.405678                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 70131.355932                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64102.494511                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59100.889033                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59544.793398                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 65852.272727                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker        63050                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63201.326063                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59100.085878                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59460.405678                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64102.494511                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59100.889033                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59544.793398                       # average overall mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt
index 307acd090..f26bf1c54 100644
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt
@@ -1,159 +1,162 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  5.135764                       # Number of seconds simulated
-sim_ticks                                5135763847500                       # Number of ticks simulated
-final_tick                               5135763847500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  5.137881                       # Number of seconds simulated
+sim_ticks                                5137881357500                       # Number of ticks simulated
+final_tick                               5137881357500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 259782                       # Simulator instruction rate (inst/s)
-host_op_rate                                   516376                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             5470381356                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 959692                       # Number of bytes of host memory used
-host_seconds                                   938.83                       # Real time elapsed on the host
-sim_insts                                   243891279                       # Number of instructions simulated
-sim_ops                                     484789360                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 401147                       # Simulator instruction rate (inst/s)
+host_op_rate                                   797370                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             8430324111                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 944704                       # Number of bytes of host memory used
+host_seconds                                   609.45                       # Real time elapsed on the host
+sim_insts                                   244480058                       # Number of instructions simulated
+sim_ops                                     485958826                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::pc.south_bridge.ide      2442432                       # Number of bytes read from this memory
+system.physmem.bytes_read::pc.south_bridge.ide        28352                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.itb.walker          256                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst           470912                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data          6169536                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker           64                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           114240                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data          1582592                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.dtb.walker         2240                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.inst           379456                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.data          2632640                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             13794368                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       470912                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       114240                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu2.inst       379456                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          964608                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      9131520                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           9131520                       # Number of bytes written to this memory
-system.physmem.num_reads::pc.south_bridge.ide        38163                       # Number of read requests responded to by this memory
+system.physmem.bytes_read::cpu0.inst           396800                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data          5697984                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           149888                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data          1826880                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.dtb.walker         1984                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.itb.walker           64                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.inst           430976                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.data          2905472                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             11438656                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       396800                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       149888                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu2.inst       430976                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          977664                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      6187584                       # Number of bytes written to this memory
+system.physmem.bytes_written::pc.south_bridge.ide      2990080                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           9177664                       # Number of bytes written to this memory
+system.physmem.num_reads::pc.south_bridge.ide          443                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu0.itb.walker            4                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst              7358                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data             96399                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker            1                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              1785                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data             24728                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.dtb.walker           35                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.inst              5929                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.data             41135                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                215537                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          142680                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               142680                       # Number of write requests responded to by this memory
-system.physmem.bw_read::pc.south_bridge.ide       475573                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_reads::cpu0.inst              6200                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data             89031                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst              2342                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data             28545                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.dtb.walker           31                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.itb.walker            1                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.inst              6734                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.data             45398                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                178729                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           96681                       # Number of write requests responded to by this memory
+system.physmem.num_writes::pc.south_bridge.ide        46720                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               143401                       # Number of write requests responded to by this memory
+system.physmem.bw_read::pc.south_bridge.ide         5518                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu0.itb.walker            50                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst               91693                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data             1201289                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker            12                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               22244                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              308151                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.dtb.walker           436                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst               73885                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data              512609                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 2685943                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst          91693                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          22244                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst          73885                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             187822                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1778026                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1778026                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1778026                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::pc.south_bridge.ide       475573                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst               77230                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data             1109014                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               29173                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              355571                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.dtb.walker           386                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.itb.walker            12                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.inst               83882                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.data              565500                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 2226337                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst          77230                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          29173                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu2.inst          83882                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             190285                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1204307                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::pc.south_bridge.ide       581968                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                1786274                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1204307                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::pc.south_bridge.ide       587486                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.itb.walker           50                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst              91693                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data            1201289                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker           12                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              22244                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             308151                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.dtb.walker          436                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst              73885                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data             512609                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                4463968                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                         94056                       # Number of read requests accepted
-system.physmem.writeReqs                        72760                       # Number of write requests accepted
-system.physmem.readBursts                       94056                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                      72760                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                  6015488                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      4096                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   4656640                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                   6019584                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                4656640                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                       64                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bw_total::cpu0.inst              77230                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data            1109014                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              29173                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             355571                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.dtb.walker          386                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.itb.walker           12                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.inst              83882                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.data             565500                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                4012611                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                         83494                       # Number of read requests accepted
+system.physmem.writeReqs                        76163                       # Number of write requests accepted
+system.physmem.readBursts                       83494                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                      76163                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                  5331584                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     12032                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   4872768                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                   5343616                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                4874432                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      188                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs            766                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                5609                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                5668                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                5585                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                5594                       # Per bank write bursts
-system.physmem.perBankRdBursts::4                6037                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                6612                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                5733                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                5990                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                5523                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                5460                       # Per bank write bursts
-system.physmem.perBankRdBursts::10               5647                       # Per bank write bursts
-system.physmem.perBankRdBursts::11               6128                       # Per bank write bursts
-system.physmem.perBankRdBursts::12               6059                       # Per bank write bursts
-system.physmem.perBankRdBursts::13               6267                       # Per bank write bursts
-system.physmem.perBankRdBursts::14               6194                       # Per bank write bursts
-system.physmem.perBankRdBursts::15               5886                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                4545                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                4402                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                4127                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                4299                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                4675                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                5126                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                4327                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                4679                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                4360                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                4207                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               4528                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               4822                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               4836                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               4641                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               4944                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               4242                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs            873                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0                4736                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                4757                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                5051                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                5281                       # Per bank write bursts
+system.physmem.perBankRdBursts::4                5400                       # Per bank write bursts
+system.physmem.perBankRdBursts::5                4765                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                4961                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                5223                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                5069                       # Per bank write bursts
+system.physmem.perBankRdBursts::9                5177                       # Per bank write bursts
+system.physmem.perBankRdBursts::10               4953                       # Per bank write bursts
+system.physmem.perBankRdBursts::11               4660                       # Per bank write bursts
+system.physmem.perBankRdBursts::12               5195                       # Per bank write bursts
+system.physmem.perBankRdBursts::13               6216                       # Per bank write bursts
+system.physmem.perBankRdBursts::14               6082                       # Per bank write bursts
+system.physmem.perBankRdBursts::15               5780                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                4915                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                4846                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                4413                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                4685                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                5227                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                4409                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                4642                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                4533                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                4328                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                4737                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               4592                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               4470                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               4760                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               5234                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               5550                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               4796                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                           1                       # Number of times write queue was full causing retry
-system.physmem.totGap                    5131947184500                       # Total gap between requests
+system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
+system.physmem.totGap                    5136881165000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                   94056                       # Read request sizes (log2)
+system.physmem.readPktSize::6                   83494                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                  72760                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                     71094                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      4372                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                      2882                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                      1652                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                      1622                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                      1995                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                      1751                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                      1697                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                      1317                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                       996                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                      893                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                      759                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                      598                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                      528                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                      422                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                      379                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                      352                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                      273                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                      218                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                      184                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                        8                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                  76163                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                     78715                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      3589                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       535                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                       144                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                        41                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                        37                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                        34                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                        32                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                        28                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                        31                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                       29                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                       28                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                       26                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                       26                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                        8                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
@@ -165,474 +168,475 @@ system.physmem.rdQLenPdf::28                        0                       # Wh
 system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                       110                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1                        65                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                        63                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                        60                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                        57                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                        57                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                        55                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                        53                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                        53                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                        53                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10                       52                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                       52                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12                       52                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13                       53                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                       52                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     1038                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     1121                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     2990                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     3113                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     3162                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     3202                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     3262                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     3405                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     3645                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     3779                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     4031                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     4114                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::28                     4380                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::32                     4409                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::47                       64                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                       50                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::51                       42                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                       37                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                       38                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::55                       22                       # What write queue length does an incoming req see
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 system.physmem.wrQLenPdf::56                       16                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::58                        9                       # What write queue length does an incoming req see
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 system.physmem.wrQLenPdf::59                        7                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                        4                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                        6                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::61                        4                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        3                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                        3                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        35723                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      298.746690                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     173.799684                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     327.095227                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          14318     40.08%     40.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255         8282     23.18%     63.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         3507      9.82%     73.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         1954      5.47%     78.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         1307      3.66%     82.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767          922      2.58%     84.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895          623      1.74%     86.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          530      1.48%     88.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         4280     11.98%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          35723                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          3978                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        23.627954                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      119.433357                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-255            3969     99.77%     99.77% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::256-511             7      0.18%     99.95% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        38507                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      264.993274                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     160.426697                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     294.053955                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          15907     41.31%     41.31% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255         9655     25.07%     66.38% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         3981     10.34%     76.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         2127      5.52%     82.24% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         1469      3.81%     86.06% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1046      2.72%     88.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          664      1.72%     90.50% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          555      1.44%     91.94% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         3103      8.06%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          38507                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          3853                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        21.615365                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      121.265146                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-255            3842     99.71%     99.71% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::256-511             8      0.21%     99.92% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::512-767             1      0.03%     99.95% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::2560-2815            1      0.03%     99.97% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::6656-6911            1      0.03%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            3978                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          3978                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        18.290598                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       17.208175                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        6.685696                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::0-1                45      1.13%      1.13% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::2-3                 5      0.13%      1.26% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::4-5                 3      0.08%      1.33% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::6-7                 4      0.10%      1.43% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::10-11               1      0.03%      1.46% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::14-15               5      0.13%      1.58% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-17            2627     66.04%     67.62% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18-19             818     20.56%     88.19% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-21              28      0.70%     88.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22-23              32      0.80%     89.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-25              32      0.80%     90.50% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26-27              35      0.88%     91.38% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-29              65      1.63%     93.01% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::30-31              48      1.21%     94.22% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-33              35      0.88%     95.10% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::34-35              29      0.73%     95.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-37              29      0.73%     96.56% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::38-39              26      0.65%     97.21% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-41              31      0.78%     97.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::42-43              18      0.45%     98.44% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-45              10      0.25%     98.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::46-47              17      0.43%     99.12% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-49               8      0.20%     99.32% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::50-51               6      0.15%     99.47% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-53               2      0.05%     99.52% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::54-55               2      0.05%     99.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-57               7      0.18%     99.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::58-59               1      0.03%     99.77% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-61               3      0.08%     99.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::62-63               4      0.10%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::66-67               2      0.05%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            3978                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     2424873249                       # Total ticks spent queuing
-system.physmem.totMemAccLat                4187223249                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    469960000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       25798.72                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            3853                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          3853                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        19.760446                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       17.599143                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       12.462049                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::0-3                66      1.71%      1.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::4-7                 8      0.21%      1.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::12-15              10      0.26%      2.18% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            3269     84.84%     87.02% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23              44      1.14%     88.17% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27              26      0.67%     88.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31             135      3.50%     92.34% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35             114      2.96%     95.30% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39               3      0.08%     95.38% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43              14      0.36%     95.74% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47               8      0.21%     95.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51              13      0.34%     96.29% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55               2      0.05%     96.34% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59               2      0.05%     96.39% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63               1      0.03%     96.42% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67              96      2.49%     98.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71               1      0.03%     98.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79               5      0.13%     99.07% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83              13      0.34%     99.40% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99               4      0.10%     99.51% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             1      0.03%     99.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107             2      0.05%     99.58% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111             1      0.03%     99.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115             5      0.13%     99.74% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::116-119             2      0.05%     99.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-123             1      0.03%     99.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127             1      0.03%     99.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131             4      0.10%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143             2      0.05%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            3853                       # Writes before turning the bus around for reads
+system.physmem.totQLat                      942120750                       # Total ticks spent queuing
+system.physmem.totMemAccLat                2504108250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    416530000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       11309.16                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  44548.72                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           1.17                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           0.91                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        1.17                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        0.91                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  30059.16                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           1.04                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           0.95                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        1.04                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        0.95                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.02                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                         6.97                       # Average write queue length when enqueuing
-system.physmem.readRowHits                      76538                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     54491                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   81.43                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  74.89                       # Row buffer hit rate for writes
-system.physmem.avgGap                     30764118.46                       # Average gap between requests
-system.physmem.pageHitRate                      78.58                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE     4942425043001                       # Time in different power states
-system.physmem.memoryStateTime::REF      171494180000                       # Time in different power states
+system.physmem.avgRdQLen                         1.11                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                         7.45                       # Average write queue length when enqueuing
+system.physmem.readRowHits                      65566                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     55368                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   78.71                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  72.70                       # Row buffer hit rate for writes
+system.physmem.avgGap                     32174481.33                       # Average gap between requests
+system.physmem.pageHitRate                      75.84                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE     4942580735250                       # Time in different power states
+system.physmem.memoryStateTime::REF      171564900000                       # Time in different power states
 system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT       21844559499                       # Time in different power states
+system.physmem.memoryStateTime::ACT       23734191750                       # Time in different power states
 system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.membus.throughput                      6452408                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq              421921                       # Transaction distribution
-system.membus.trans_dist::ReadResp             421919                       # Transaction distribution
-system.membus.trans_dist::WriteReq               5915                       # Transaction distribution
-system.membus.trans_dist::WriteResp              5915                       # Transaction distribution
-system.membus.trans_dist::Writeback             72760                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq              778                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp             778                       # Transaction distribution
-system.membus.trans_dist::ReadExReq             75224                       # Transaction distribution
-system.membus.trans_dist::ReadExResp            75224                       # Transaction distribution
-system.membus.trans_dist::MessageReq              825                       # Transaction distribution
-system.membus.trans_dist::MessageResp             825                       # Transaction distribution
-system.membus.trans_dist::BadAddressError            2                       # Transaction distribution
-system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave         1650                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.apicbridge.master::total         1650                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       308134                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio       497586                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       196326                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio            4                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total      1002050                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        72232                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total        72232                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1075932                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave         3300                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.apicbridge.master::total         3300                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave       157715                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio       995169                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port      7734720                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::total      8887604                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port      2941504                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::total      2941504                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total            11832408                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus               32744958                       # Total data (bytes)
-system.membus.snoop_data_through_bus           393088                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy           161596500                       # Layer occupancy (ticks)
+system.membus.throughput                      5877722                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq              425622                       # Transaction distribution
+system.membus.trans_dist::ReadResp             425619                       # Transaction distribution
+system.membus.trans_dist::WriteReq               7303                       # Transaction distribution
+system.membus.trans_dist::WriteResp              7303                       # Transaction distribution
+system.membus.trans_dist::Writeback             54691                       # Transaction distribution
+system.membus.trans_dist::WriteInvalidateReq        21472                       # Transaction distribution
+system.membus.trans_dist::WriteInvalidateResp        21472                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq              873                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp             873                       # Transaction distribution
+system.membus.trans_dist::ReadExReq             56661                       # Transaction distribution
+system.membus.trans_dist::ReadExResp            56661                       # Transaction distribution
+system.membus.trans_dist::MessageReq             1005                       # Transaction distribution
+system.membus.trans_dist::MessageResp            1005                       # Transaction distribution
+system.membus.trans_dist::BadAddressError            3                       # Transaction distribution
+system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave         2010                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.apicbridge.master::total         2010                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       313168                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio       498446                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       222539                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio            6                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total      1034159                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        44112                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total        44112                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                1080281                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave         4020                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.apicbridge.master::total         4020                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave       160913                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio       996889                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port      8815488                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::total      9973290                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port      1402560                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.iocache.mem_side::total      1402560                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total            11379870                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus               30180989                       # Total data (bytes)
+system.membus.snoop_data_through_bus            18048                       # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy           165986000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy           315113000                       # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy           315728000                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             1650000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             2010000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer3.occupancy           794070497                       # Layer occupancy (ticks)
+system.membus.reqLayer3.occupancy           815495498                       # Layer occupancy (ticks)
 system.membus.reqLayer3.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer4.occupancy                2000                       # Layer occupancy (ticks)
+system.membus.reqLayer4.occupancy                3500                       # Layer occupancy (ticks)
 system.membus.reqLayer4.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer0.occupancy             825000                       # Layer occupancy (ticks)
+system.membus.respLayer0.occupancy            1005000                       # Layer occupancy (ticks)
 system.membus.respLayer0.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         1569908183                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         1662343876                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer4.occupancy          236956000                       # Layer occupancy (ticks)
+system.membus.respLayer4.occupancy           28017243                       # Layer occupancy (ticks)
 system.membus.respLayer4.utilization              0.0                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.l2c.tags.replacements                   104346                       # number of replacements
-system.l2c.tags.tagsinuse                64811.945905                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    3669840                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                   168730                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                    21.749778                       # Average number of references to valid blocks.
+system.l2c.tags.replacements                   105452                       # number of replacements
+system.l2c.tags.tagsinuse                64826.295665                       # Cycle average of tags in use
+system.l2c.tags.total_refs                    3690842                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                   169644                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                    21.756396                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   51276.768453                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker     0.121941                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     1221.298902                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     4234.138382                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.itb.walker     0.002961                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst      249.507225                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data     1581.676468                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.dtb.walker     7.253356                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.inst     1493.843089                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.data     4747.335130                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.782421                       # Average percentage of cache occupancy
+system.l2c.tags.occ_blocks::writebacks   50973.887089                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker     0.131156                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     1039.864675                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     3857.355286                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst      297.125354                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data     1525.078899                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.dtb.walker    11.736641                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.itb.walker     0.003210                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.inst     1792.530465                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.data     5328.582890                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.777800                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu0.itb.walker     0.000002                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.018636                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.064608                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.itb.walker     0.000000                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.003807                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.024134                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.dtb.walker     0.000111                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.inst       0.022794                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.data       0.072439                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.988952                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1024        64384                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0           76                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1          269                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         2861                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         7799                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        53379                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1024     0.982422                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                 33692585                       # Number of tag accesses
-system.l2c.tags.data_accesses                33692585                       # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.dtb.walker        19944                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker        10836                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.inst             348846                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data             522725                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker         9533                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker         5021                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst             144714                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data             221166                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.dtb.walker        56163                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.itb.walker        10079                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.inst             347465                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.data             563204                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                2259696                       # number of ReadReq hits
+system.l2c.tags.occ_percent::cpu0.inst       0.015867                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data       0.058859                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.004534                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data       0.023271                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.dtb.walker     0.000179                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.itb.walker     0.000000                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.inst       0.027352                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.data       0.081308                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.989171                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1024        64192                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0           36                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1          605                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2         3319                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3         7395                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        52837                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1024     0.979492                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                 33876235                       # Number of tag accesses
+system.l2c.tags.data_accesses                33876235                       # Number of data accesses
+system.l2c.ReadReq_hits::cpu0.dtb.walker        20790                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.itb.walker        10881                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.inst             323642                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.data             493790                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.dtb.walker        11848                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.itb.walker         6379                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.inst             159823                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.data             243124                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu2.dtb.walker        53625                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu2.itb.walker        12570                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu2.inst             372046                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu2.data             571492                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                2280010                       # number of ReadReq hits
 system.l2c.WriteReq_hits::cpu0.itb.walker            2                       # number of WriteReq hits
 system.l2c.WriteReq_hits::total                     2                       # number of WriteReq hits
-system.l2c.Writeback_hits::writebacks         1546042                       # number of Writeback hits
-system.l2c.Writeback_hits::total              1546042                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data             139                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data              47                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu2.data              73                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                 259                       # number of UpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data            69718                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data            41748                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu2.data            55006                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               166472                       # number of ReadExReq hits
-system.l2c.demand_hits::cpu0.dtb.walker         19944                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker         10838                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst              348846                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data              592443                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker          9533                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker          5021                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst              144714                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data              262914                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.dtb.walker         56163                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.itb.walker         10079                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.inst              347465                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.data              618210                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 2426170                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker        19944                       # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker        10838                       # number of overall hits
-system.l2c.overall_hits::cpu0.inst             348846                       # number of overall hits
-system.l2c.overall_hits::cpu0.data             592443                       # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker         9533                       # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker         5021                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst             144714                       # number of overall hits
-system.l2c.overall_hits::cpu1.data             262914                       # number of overall hits
-system.l2c.overall_hits::cpu2.dtb.walker        56163                       # number of overall hits
-system.l2c.overall_hits::cpu2.itb.walker        10079                       # number of overall hits
-system.l2c.overall_hits::cpu2.inst             347465                       # number of overall hits
-system.l2c.overall_hits::cpu2.data             618210                       # number of overall hits
-system.l2c.overall_hits::total                2426170                       # number of overall hits
+system.l2c.Writeback_hits::writebacks         1547750                       # number of Writeback hits
+system.l2c.Writeback_hits::total              1547750                       # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu0.data             119                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data              62                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu2.data              66                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                 247                       # number of UpgradeReq hits
+system.l2c.ReadExReq_hits::cpu0.data            66599                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data            37683                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu2.data            62729                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               167011                       # number of ReadExReq hits
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 system.l2c.WriteReq_accesses::cpu0.itb.walker            2                       # number of WriteReq accesses(hits+misses)
 system.l2c.WriteReq_accesses::total                 2                       # number of WriteReq accesses(hits+misses)
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-system.l2c.UpgradeReq_miss_rate::cpu2.data     0.827830                       # miss rate for UpgradeReq accesses
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+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.850602                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu2.data     0.835411                       # miss rate for UpgradeReq accesses
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 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -641,125 +645,134 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
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-system.l2c.demand_mshr_miss_rate::cpu1.data     0.086495                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker     0.000623                       # mshr miss rate for demand accesses
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-system.l2c.demand_mshr_miss_rate::cpu2.data     0.062840                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.028450                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.000199                       # mshr miss rate for overall accesses
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-system.l2c.overall_mshr_miss_rate::cpu1.data     0.086495                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker     0.000623                       # mshr miss rate for overall accesses
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-system.l2c.overall_mshr_miss_rate::cpu2.data     0.062840                       # mshr miss rate for overall accesses
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-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 63706.668391                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 65028.571429                       # average ReadReq mshr miss latency
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-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 63565.571043                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 63335.311332                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 12124.509653                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10171.934473                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 11000.978689                       # average UpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 56493.171737                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 58448.752790                       # average ReadExReq mshr miss latency
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-system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker        62500                       # average overall mshr miss latency
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-system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 65028.571429                       # average overall mshr miss latency
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-system.l2c.demand_avg_mshr_miss_latency::cpu2.data 59959.493595                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 59502.614100                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker        62500                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60735.994958                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 57725.267333                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 65028.571429                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 63366.377635                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.data 59959.493595                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 59502.614100                       # average overall mshr miss latency
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+system.l2c.ReadReq_mshr_uncacheable_latency::total  58725915000                       # number of ReadReq MSHR uncacheable cycles
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+system.l2c.overall_mshr_uncacheable_latency::total  60032458000                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.014442                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.017375                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker     0.000578                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2.itb.walker     0.000080                       # mshr miss rate for ReadReq accesses
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+system.l2c.ReadReq_mshr_miss_rate::cpu2.data     0.022218                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.011335                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.850602                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data     0.835411                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.412965                       # mshr miss rate for UpgradeReq accesses
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+system.l2c.ReadExReq_mshr_miss_rate::cpu2.data     0.341331                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.191288                       # mshr miss rate for ReadExReq accesses
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+system.l2c.demand_mshr_miss_rate::cpu1.data     0.092546                       # mshr miss rate for demand accesses
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+system.l2c.demand_mshr_miss_rate::cpu2.itb.walker     0.000080                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.inst     0.017778                       # mshr miss rate for demand accesses
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+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.014442                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.092546                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker     0.000578                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.itb.walker     0.000080                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.inst     0.017778                       # mshr miss rate for overall accesses
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+system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 77612.903226                       # average overall mshr miss latency
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+system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 65275.616276                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.data 60476.811663                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 59840.380543                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -770,106 +783,98 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average overall mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.iocache.tags.replacements                47573                       # number of replacements
-system.iocache.tags.tagsinuse                0.095086                       # Cycle average of tags in use
+system.iocache.tags.replacements                47572                       # number of replacements
+system.iocache.tags.tagsinuse                0.093953                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs                47589                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs                47588                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         5000199085509                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::pc.south_bridge.ide     0.095086                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::pc.south_bridge.ide     0.005943                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.005943                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         5000192642009                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::pc.south_bridge.ide     0.093953                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::pc.south_bridge.ide     0.005872                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.005872                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses               428652                       # Number of tag accesses
-system.iocache.tags.data_accesses              428652                       # Number of data accesses
-system.iocache.ReadReq_misses::pc.south_bridge.ide          908                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total              908                       # number of ReadReq misses
-system.iocache.WriteReq_misses::pc.south_bridge.ide        46720                       # number of WriteReq misses
-system.iocache.WriteReq_misses::total           46720                       # number of WriteReq misses
-system.iocache.demand_misses::pc.south_bridge.ide        47628                       # number of demand (read+write) misses
-system.iocache.demand_misses::total             47628                       # number of demand (read+write) misses
-system.iocache.overall_misses::pc.south_bridge.ide        47628                       # number of overall misses
-system.iocache.overall_misses::total            47628                       # number of overall misses
-system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    130701291                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total    130701291                       # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency::pc.south_bridge.ide   6017123258                       # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_latency::total   6017123258                       # number of WriteReq miss cycles
-system.iocache.demand_miss_latency::pc.south_bridge.ide   6147824549                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   6147824549                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::pc.south_bridge.ide   6147824549                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   6147824549                       # number of overall miss cycles
-system.iocache.ReadReq_accesses::pc.south_bridge.ide          908                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total            908                       # number of ReadReq accesses(hits+misses)
-system.iocache.WriteReq_accesses::pc.south_bridge.ide        46720                       # number of WriteReq accesses(hits+misses)
-system.iocache.WriteReq_accesses::total         46720                       # number of WriteReq accesses(hits+misses)
-system.iocache.demand_accesses::pc.south_bridge.ide        47628                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total           47628                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::pc.south_bridge.ide        47628                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total          47628                       # number of overall (read+write) accesses
+system.iocache.tags.tag_accesses               428643                       # Number of tag accesses
+system.iocache.tags.data_accesses              428643                       # Number of data accesses
+system.iocache.WriteInvalidateReq_hits::pc.south_bridge.ide        46720                       # number of WriteInvalidateReq hits
+system.iocache.WriteInvalidateReq_hits::total        46720                       # number of WriteInvalidateReq hits
+system.iocache.ReadReq_misses::pc.south_bridge.ide          907                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total              907                       # number of ReadReq misses
+system.iocache.demand_misses::pc.south_bridge.ide          907                       # number of demand (read+write) misses
+system.iocache.demand_misses::total               907                       # number of demand (read+write) misses
+system.iocache.overall_misses::pc.south_bridge.ide          907                       # number of overall misses
+system.iocache.overall_misses::total              907                       # number of overall misses
+system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    132008537                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total    132008537                       # number of ReadReq miss cycles
+system.iocache.demand_miss_latency::pc.south_bridge.ide    132008537                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total    132008537                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::pc.south_bridge.ide    132008537                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total    132008537                       # number of overall miss cycles
+system.iocache.ReadReq_accesses::pc.south_bridge.ide          907                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total            907                       # number of ReadReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide        46720                       # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::total        46720                       # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.demand_accesses::pc.south_bridge.ide          907                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total             907                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::pc.south_bridge.ide          907                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total            907                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
-system.iocache.WriteReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for WriteReq accesses
-system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
 system.iocache.demand_miss_rate::pc.south_bridge.ide            1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::pc.south_bridge.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 143944.153084                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 143944.153084                       # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 128791.165625                       # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total 128791.165625                       # average WriteReq miss latency
-system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 129080.048480                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 129080.048480                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 129080.048480                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 129080.048480                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs         86048                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 145544.142227                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 145544.142227                       # average ReadReq miss latency
+system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 145544.142227                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 145544.142227                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 145544.142227                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 145544.142227                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs           308                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                 7909                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                   26                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs    10.879757                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs    11.846154                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.fast_writes                          0                       # number of fast writes performed
+system.iocache.fast_writes                      46720                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.writebacks::writebacks           46667                       # number of writebacks
-system.iocache.writebacks::total                46667                       # number of writebacks
-system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          735                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total          735                       # number of ReadReq MSHR misses
-system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide        25536                       # number of WriteReq MSHR misses
-system.iocache.WriteReq_mshr_misses::total        25536                       # number of WriteReq MSHR misses
-system.iocache.demand_mshr_misses::pc.south_bridge.ide        26271                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total        26271                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::pc.south_bridge.ide        26271                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total        26271                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide     92456791                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     92456791                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide   4688241758                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::total   4688241758                       # number of WriteReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide   4780698549                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   4780698549                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide   4780698549                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   4780698549                       # number of overall MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide     0.809471                       # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::total     0.809471                       # mshr miss rate for ReadReq accesses
-system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide     0.546575                       # mshr miss rate for WriteReq accesses
-system.iocache.WriteReq_mshr_miss_rate::total     0.546575                       # mshr miss rate for WriteReq accesses
-system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide     0.551587                       # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total     0.551587                       # mshr miss rate for demand accesses
-system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide     0.551587                       # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total     0.551587                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 125791.552381                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 125791.552381                       # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 183593.427240                       # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total 183593.427240                       # average WriteReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 181976.268471                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 181976.268471                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 181976.268471                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 181976.268471                       # average overall mshr miss latency
+system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          725                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total          725                       # number of ReadReq MSHR misses
+system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide        21472                       # number of WriteInvalidateReq MSHR misses
+system.iocache.WriteInvalidateReq_mshr_misses::total        21472                       # number of WriteInvalidateReq MSHR misses
+system.iocache.demand_mshr_misses::pc.south_bridge.ide          725                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total          725                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::pc.south_bridge.ide          725                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total          725                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide     94282037                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     94282037                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide   1310743323                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::total   1310743323                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide     94282037                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total     94282037                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide     94282037                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total     94282037                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide     0.799338                       # mshr miss rate for ReadReq accesses
+system.iocache.ReadReq_mshr_miss_rate::total     0.799338                       # mshr miss rate for ReadReq accesses
+system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide     0.459589                       # mshr miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_mshr_miss_rate::total     0.459589                       # mshr miss rate for WriteInvalidateReq accesses
+system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide     0.799338                       # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::total     0.799338                       # mshr miss rate for demand accesses
+system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide     0.799338                       # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::total     0.799338                       # mshr miss rate for overall accesses
+system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 130044.188966                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 130044.188966                       # average ReadReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 61044.305281                       # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 61044.305281                       # average WriteInvalidateReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 130044.188966                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 130044.188966                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 130044.188966                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 130044.188966                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
 system.pc.south_bridge.ide.disks0.dma_read_bytes        34816                       # Number of bytes transfered via DMA reads (not PRD).
-system.pc.south_bridge.ide.disks0.dma_read_txs           31                       # Number of DMA read transactions (not PRD).
+system.pc.south_bridge.ide.disks0.dma_read_txs           32                       # Number of DMA read transactions (not PRD).
 system.pc.south_bridge.ide.disks0.dma_write_full_pages          693                       # Number of full page size DMA writes.
 system.pc.south_bridge.ide.disks0.dma_write_bytes      2985984                       # Number of bytes transfered via DMA writes.
 system.pc.south_bridge.ide.disks0.dma_write_txs          812                       # Number of DMA write transactions.
@@ -879,511 +884,555 @@ system.pc.south_bridge.ide.disks1.dma_read_txs            0
 system.pc.south_bridge.ide.disks1.dma_write_full_pages            1                       # Number of full page size DMA writes.
 system.pc.south_bridge.ide.disks1.dma_write_bytes         4096                       # Number of bytes transfered via DMA writes.
 system.pc.south_bridge.ide.disks1.dma_write_txs            1                       # Number of DMA write transactions.
-system.toL2Bus.throughput                    52407719                       # Throughput (bytes/s)
-system.toL2Bus.trans_dist::ReadReq            1793633                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           1793101                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq              5915                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp             5915                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback           899960                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq             730                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp            730                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           172146                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          146613                       # Transaction distribution
-system.toL2Bus.trans_dist::BadAddressError            2                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side       999818                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      3602290                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side        34349                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side       141650                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               4778107                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     31993152                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side    119401652                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side       120808                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side       525848                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size::total          152041460                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.data_through_bus             269011854                       # Total data (bytes)
-system.toL2Bus.snoop_data_through_bus          141816                       # Total snoop data (bytes)
-system.toL2Bus.reqLayer0.occupancy         5025953302                       # Layer occupancy (ticks)
+system.toL2Bus.throughput                    53202678                       # Throughput (bytes/s)
+system.toL2Bus.trans_dist::ReadReq            1873297                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp           1872762                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq              7303                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp             7303                       # Transaction distribution
+system.toL2Bus.trans_dist::Writeback           935388                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateReq        21472                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq             816                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp            816                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq           157258                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp          157258                       # Transaction distribution
+system.toL2Bus.trans_dist::BadAddressError            3                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      1081926                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      3727147                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side        42874                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side       142768                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total               4994715                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     34620672                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side    124341034                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side       151600                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side       524032                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size::total          159637338                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.data_through_bus             270199237                       # Total data (bytes)
+system.toL2Bus.snoop_data_through_bus         3149808                       # Total snoop data (bytes)
+system.toL2Bus.reqLayer0.occupancy         5231949371                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy           936000                       # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy           868500                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy        2251918114                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy        2437443949                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy        4677619434                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy        4869271823                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy          19272449                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy          23963155                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy          76057203                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy          77561882                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
-system.iobus.throughput                       1276582                       # Throughput (bytes/s)
-system.iobus.trans_dist::ReadReq               149714                       # Transaction distribution
-system.iobus.trans_dist::ReadResp              149714                       # Transaction distribution
-system.iobus.trans_dist::WriteReq               30624                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              30624                       # Transaction distribution
-system.iobus.trans_dist::MessageReq               825                       # Transaction distribution
-system.iobus.trans_dist::MessageResp              825                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio           36                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio            2                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio         4890                       # Packet count per connected master and slave (bytes)
+system.iobus.throughput                       1275815                       # Throughput (bytes/s)
+system.iobus.trans_dist::ReadReq               151004                       # Transaction distribution
+system.iobus.trans_dist::ReadResp              151004                       # Transaction distribution
+system.iobus.trans_dist::WriteReq               27777                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              27777                       # Transaction distribution
+system.iobus.trans_dist::MessageReq              1005                       # Transaction distribution
+system.iobus.trans_dist::MessageResp             1005                       # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio           44                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio            4                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio         5602                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf            2                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio          588                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio           30                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio           24                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio         1160                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio           50                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio           18                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio       287208                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio          156                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio           86                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio        13026                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio            4                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio         2064                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total       308134                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side        52542                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total        52542                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         1650                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total         1650                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  362326                       # Packet count per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio           18                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio            1                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio         2760                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio       287262                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio          594                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio          142                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio        16180                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio           12                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio           12                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio           12                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio           10                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio         2048                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total       313168                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side        44394                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total        44394                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         2010                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total         2010                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  359572                       # Packet count per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio           22                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio            2                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio         3164                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf            4                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio          294                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio           15                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio           12                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio          580                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio           25                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio            8                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio            9                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio       143604                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio          312                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.pc.i_dont_exist.pio           43                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.pc.com_1.pio         6513                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_floppy.pio            2                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio         4128                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::total       157715                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side      1670648                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total      1670648                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         3300                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total         3300                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::total              1831663                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.data_through_bus                 6556225                       # Total data (bytes)
-system.iobus.reqLayer0.occupancy              1987954                       # Layer occupancy (ticks)
+system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio       143631                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio         1188                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.pc.i_dont_exist.pio           71                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.pc.com_1.pio         8090                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_2.pio            6                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_3.pio            6                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_4.pio            6                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_floppy.pio            5                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio         4096                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::total       160913                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side      1410472                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total      1410472                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         4020                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total         4020                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::total              1575405                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.data_through_bus                 6554984                       # Total data (bytes)
+system.iobus.reqLayer0.occupancy              2375600                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy                28000                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy                34000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy                 2000                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy                 4000                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy              4046000                       # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy              4638000                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer4.occupancy                 1000                       # Layer occupancy (ticks)
 system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer5.occupancy               387000                       # Layer occupancy (ticks)
+system.iobus.reqLayer5.occupancy               758000                       # Layer occupancy (ticks)
 system.iobus.reqLayer5.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer6.occupancy                27000                       # Layer occupancy (ticks)
+system.iobus.reqLayer6.occupancy                42000                       # Layer occupancy (ticks)
 system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer7.occupancy                21000                       # Layer occupancy (ticks)
+system.iobus.reqLayer7.occupancy                15000                       # Layer occupancy (ticks)
 system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer8.occupancy                18000                       # Layer occupancy (ticks)
 system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer9.occupancy            143605000                       # Layer occupancy (ticks)
+system.iobus.reqLayer9.occupancy            143632000                       # Layer occupancy (ticks)
 system.iobus.reqLayer9.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer10.occupancy              124000                       # Layer occupancy (ticks)
+system.iobus.reqLayer10.occupancy              469000                       # Layer occupancy (ticks)
 system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer11.occupancy               86000                       # Layer occupancy (ticks)
+system.iobus.reqLayer11.occupancy              142000                       # Layer occupancy (ticks)
 system.iobus.reqLayer11.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer13.occupancy             9774000                       # Layer occupancy (ticks)
+system.iobus.reqLayer13.occupancy            12075000                       # Layer occupancy (ticks)
 system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer17.occupancy                4000                       # Layer occupancy (ticks)
+system.iobus.reqLayer14.occupancy                9000                       # Layer occupancy (ticks)
+system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer15.occupancy                9000                       # Layer occupancy (ticks)
+system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer16.occupancy                9000                       # Layer occupancy (ticks)
+system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer17.occupancy               10000                       # Layer occupancy (ticks)
 system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer18.occupancy           232428549                       # Layer occupancy (ticks)
+system.iobus.reqLayer18.occupancy           194319603                       # Layer occupancy (ticks)
 system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer19.occupancy             1032000                       # Layer occupancy (ticks)
+system.iobus.reqLayer19.occupancy             1024000                       # Layer occupancy (ticks)
 system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy           303046000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy           306863000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer1.occupancy            31488000                       # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy            26743757                       # Layer occupancy (ticks)
 system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer2.occupancy              825000                       # Layer occupancy (ticks)
+system.iobus.respLayer2.occupancy             1005000                       # Layer occupancy (ticks)
 system.iobus.respLayer2.utilization               0.0                       # Layer utilization (%)
 system.cpu0.apic_clk_domain.clock                8000                       # Clock period in ticks
-system.cpu0.numCycles                      1167096017                       # number of cpu cycles simulated
+system.cpu0.numCycles                      1069887436                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                   72932334                       # Number of instructions committed
-system.cpu0.committedOps                    148186849                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses            136173063                       # Number of integer alu accesses
+system.cpu0.committedInsts                   70857782                       # Number of instructions committed
+system.cpu0.committedOps                    144307609                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses            132405898                       # Number of integer alu accesses
 system.cpu0.num_fp_alu_accesses                     0                       # Number of float alu accesses
-system.cpu0.num_func_calls                    1014433                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts     14332221                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                   136173063                       # number of integer instructions
+system.cpu0.num_func_calls                     941314                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts     14024705                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                   132405898                       # number of integer instructions
 system.cpu0.num_fp_insts                            0                       # number of float instructions
-system.cpu0.num_int_register_reads          250637191                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes         116800630                       # number of times the integer registers were written
+system.cpu0.num_int_register_reads          243097330                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes         113712565                       # number of times the integer registers were written
 system.cpu0.num_fp_register_reads                   0                       # number of times the floating registers were read
 system.cpu0.num_fp_register_writes                  0                       # number of times the floating registers were written
-system.cpu0.num_cc_register_reads            84487712                       # number of times the CC registers were read
-system.cpu0.num_cc_register_writes           56367816                       # number of times the CC registers were written
-system.cpu0.num_mem_refs                     14369378                       # number of memory refs
-system.cpu0.num_load_insts                   10451844                       # Number of load instructions
-system.cpu0.num_store_insts                   3917534                       # Number of store instructions
-system.cpu0.num_idle_cycles              1108227141.183960                       # Number of idle cycles
-system.cpu0.num_busy_cycles              58868875.816040                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.050440                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.949560                       # Percentage of idle cycles
-system.cpu0.Branches                         15712912                       # Number of branches fetched
-system.cpu0.op_class::No_OpClass               100385      0.07%      0.07% # Class of executed instruction
-system.cpu0.op_class::IntAlu                133601927     90.16%     90.23% # Class of executed instruction
-system.cpu0.op_class::IntMult                   62763      0.04%     90.27% # Class of executed instruction
-system.cpu0.op_class::IntDiv                    53014      0.04%     90.30% # Class of executed instruction
-system.cpu0.op_class::FloatAdd                      0      0.00%     90.30% # Class of executed instruction
-system.cpu0.op_class::FloatCmp                      0      0.00%     90.30% # Class of executed instruction
-system.cpu0.op_class::FloatCvt                      0      0.00%     90.30% # Class of executed instruction
-system.cpu0.op_class::FloatMult                     0      0.00%     90.30% # Class of executed instruction
-system.cpu0.op_class::FloatDiv                      0      0.00%     90.30% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt                     0      0.00%     90.30% # Class of executed instruction
-system.cpu0.op_class::SimdAdd                       0      0.00%     90.30% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc                    0      0.00%     90.30% # Class of executed instruction
-system.cpu0.op_class::SimdAlu                       0      0.00%     90.30% # Class of executed instruction
-system.cpu0.op_class::SimdCmp                       0      0.00%     90.30% # Class of executed instruction
-system.cpu0.op_class::SimdCvt                       0      0.00%     90.30% # Class of executed instruction
-system.cpu0.op_class::SimdMisc                      0      0.00%     90.30% # Class of executed instruction
-system.cpu0.op_class::SimdMult                      0      0.00%     90.30% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc                   0      0.00%     90.30% # Class of executed instruction
-system.cpu0.op_class::SimdShift                     0      0.00%     90.30% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc                  0      0.00%     90.30% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt                      0      0.00%     90.30% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd                  0      0.00%     90.30% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu                  0      0.00%     90.30% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp                  0      0.00%     90.30% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt                  0      0.00%     90.30% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv                  0      0.00%     90.30% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc                 0      0.00%     90.30% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult                 0      0.00%     90.30% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     90.30% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     90.30% # Class of executed instruction
-system.cpu0.op_class::MemRead                10451844      7.05%     97.36% # Class of executed instruction
-system.cpu0.op_class::MemWrite                3917534      2.64%    100.00% # Class of executed instruction
+system.cpu0.num_cc_register_reads            82467233                       # number of times the CC registers were read
+system.cpu0.num_cc_register_writes           55021807                       # number of times the CC registers were written
+system.cpu0.num_mem_refs                     13631596                       # number of memory refs
+system.cpu0.num_load_insts                   10001277                       # Number of load instructions
+system.cpu0.num_store_insts                   3630319                       # Number of store instructions
+system.cpu0.num_idle_cycles              1016044794.752217                       # Number of idle cycles
+system.cpu0.num_busy_cycles              53842641.247783                       # Number of busy cycles
+system.cpu0.not_idle_fraction                0.050326                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                    0.949674                       # Percentage of idle cycles
+system.cpu0.Branches                         15304700                       # Number of branches fetched
+system.cpu0.op_class::No_OpClass                96295      0.07%      0.07% # Class of executed instruction
+system.cpu0.op_class::IntAlu                130472194     90.41%     90.48% # Class of executed instruction
+system.cpu0.op_class::IntMult                   58212      0.04%     90.52% # Class of executed instruction
+system.cpu0.op_class::IntDiv                    49897      0.03%     90.55% # Class of executed instruction
+system.cpu0.op_class::FloatAdd                      0      0.00%     90.55% # Class of executed instruction
+system.cpu0.op_class::FloatCmp                      0      0.00%     90.55% # Class of executed instruction
+system.cpu0.op_class::FloatCvt                      0      0.00%     90.55% # Class of executed instruction
+system.cpu0.op_class::FloatMult                     0      0.00%     90.55% # Class of executed instruction
+system.cpu0.op_class::FloatDiv                      0      0.00%     90.55% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt                     0      0.00%     90.55% # Class of executed instruction
+system.cpu0.op_class::SimdAdd                       0      0.00%     90.55% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc                    0      0.00%     90.55% # Class of executed instruction
+system.cpu0.op_class::SimdAlu                       0      0.00%     90.55% # Class of executed instruction
+system.cpu0.op_class::SimdCmp                       0      0.00%     90.55% # Class of executed instruction
+system.cpu0.op_class::SimdCvt                       0      0.00%     90.55% # Class of executed instruction
+system.cpu0.op_class::SimdMisc                      0      0.00%     90.55% # Class of executed instruction
+system.cpu0.op_class::SimdMult                      0      0.00%     90.55% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc                   0      0.00%     90.55% # Class of executed instruction
+system.cpu0.op_class::SimdShift                     0      0.00%     90.55% # Class of executed instruction
+system.cpu0.op_class::SimdShiftAcc                  0      0.00%     90.55% # Class of executed instruction
+system.cpu0.op_class::SimdSqrt                      0      0.00%     90.55% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAdd                  0      0.00%     90.55% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAlu                  0      0.00%     90.55% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCmp                  0      0.00%     90.55% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCvt                  0      0.00%     90.55% # Class of executed instruction
+system.cpu0.op_class::SimdFloatDiv                  0      0.00%     90.55% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc                 0      0.00%     90.55% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMult                 0      0.00%     90.55% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     90.55% # Class of executed instruction
+system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     90.55% # Class of executed instruction
+system.cpu0.op_class::MemRead                10001277      6.93%     97.48% # Class of executed instruction
+system.cpu0.op_class::MemWrite                3630319      2.52%    100.00% # Class of executed instruction
 system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
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-system.cpu0.icache.tags.warmup_cycle     147456803500                       # Cycle when the warmup percentage was hit.
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-system.cpu0.icache.tags.occ_blocks::cpu1.inst   131.510981                       # Average occupied blocks per requestor
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+system.cpu0.icache.demand_avg_miss_latency::total  8943.153684                       # average overall miss latency
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 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
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 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
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-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11819.352002                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12340.343894                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 12187.671411                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11819.352002                       # average overall mshr miss latency
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-system.cpu0.icache.overall_avg_mshr_miss_latency::total 12187.671411                       # average overall mshr miss latency
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+system.cpu0.icache.ReadReq_mshr_hits::total        23669                       # number of ReadReq MSHR hits
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+system.cpu0.icache.overall_mshr_hits::cpu2.inst        23669                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total        23669                       # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       162165                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst       378813                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total       540978                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu1.inst       162165                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu2.inst       378813                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total       540978                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu1.inst       162165                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu2.inst       378813                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total       540978                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst   1937521250                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst   4727163793                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total   6664685043                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst   1937521250                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst   4727163793                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total   6664685043                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst   1937521250                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst   4727163793                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total   6664685043                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.004064                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.110365                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.004165                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.004064                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst     0.110365                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.004165                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.004064                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst     0.110365                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.004165                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11947.838621                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12478.884814                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12319.696999                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11947.838621                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12478.884814                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 12319.696999                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11947.838621                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12478.884814                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 12319.696999                       # average overall mshr miss latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.dcache.tags.replacements          1636191                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          511.999281                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           19675203                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs          1636703                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            12.021242                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.replacements          1638145                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          511.999454                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs           19665757                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs          1638657                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            12.001143                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle          7549500                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   273.563820                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu1.data   233.097338                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu2.data     5.338124                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.534304                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu1.data     0.455268                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu2.data     0.010426                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   255.173145                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu1.data   234.203255                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu2.data    22.623054                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.498385                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu1.data     0.457428                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu2.data     0.044186                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_percent::total     0.999999                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0          210                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          278                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           24                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0          173                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          322                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           17                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses         88326830                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses        88326830                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data      5302140                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu1.data      2350453                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu2.data      3934991                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total       11587584                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data      3761995                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu1.data      1605612                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu2.data      2718349                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total       8085956                       # number of WriteReq hits
-system.cpu0.dcache.demand_hits::cpu0.data      9064135                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu1.data      3956065                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu2.data      6653340                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        19673540                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data      9064135                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu1.data      3956065                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu2.data      6653340                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       19673540                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data       539140                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu1.data       225418                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu2.data       918731                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total      1683289                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data       151041                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu1.data        62696                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu2.data       101955                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total       315692                       # number of WriteReq misses
-system.cpu0.dcache.demand_misses::cpu0.data       690181                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu1.data       288114                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu2.data      1020686                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       1998981                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data       690181                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu1.data       288114                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu2.data      1020686                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      1998981                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   3220560254                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::cpu2.data  14575132809                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total  17795693063                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   2058114299                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu2.data   3117330338                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total   5175444637                       # number of WriteReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu1.data   5278674553                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu2.data  17692463147                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total  22971137700                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu1.data   5278674553                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu2.data  17692463147                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total  22971137700                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data      5841280                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu1.data      2575871                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu2.data      4853722                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total     13270873                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data      3913036                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu1.data      1668308                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu2.data      2820304                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total      8401648                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data      9754316                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu1.data      4244179                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu2.data      7674026                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     21672521                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data      9754316                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu1.data      4244179                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu2.data      7674026                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     21672521                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.092298                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.087511                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu2.data     0.189284                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.126841                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.038599                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.037581                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu2.data     0.036150                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.037575                       # miss rate for WriteReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.070756                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu1.data     0.067885                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu2.data     0.133005                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.092236                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.070756                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu1.data     0.067885                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu2.data     0.133005                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.092236                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14287.058948                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 15864.418213                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 10571.977280                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 32826.883677                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 30575.551351                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 16393.968289                       # average WriteReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 18321.478835                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 17333.894211                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 11491.423730                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 18321.478835                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 17333.894211                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 11491.423730                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs        80099                       # number of cycles access was blocked
+system.cpu0.dcache.tags.tag_accesses         88359204                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses        88359204                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data      4868347                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu1.data      2652392                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu2.data      4007715                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total       11528454                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data      3486449                       # number of WriteReq hits
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+system.cpu0.dcache.WriteReq_hits::total       8074773                       # number of WriteReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu0.data        17966                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu1.data        11989                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu2.data        30798                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::total        60753                       # number of SoftPFReq hits
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+system.cpu0.dcache.demand_hits::total        19603227                       # number of demand (read+write) hits
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+system.cpu0.dcache.overall_hits::total       19663980                       # number of overall hits
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+system.cpu0.dcache.overall_miss_latency::total  20546602224                       # number of overall miss cycles
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+system.cpu0.dcache.overall_accesses::cpu1.data      4713906                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu2.data      7943100                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     21680133                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.069073                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.060818                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu2.data     0.157823                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.100216                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.038809                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.035569                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu2.data     0.041035                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.038902                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.891994                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.863358                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data     0.854704                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.869643                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.056678                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu1.data     0.050983                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu2.data     0.112922                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.075933                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.072078                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu1.data     0.066104                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu2.data     0.132717                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.092995                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 13789.942594                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 15926.913883                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 11160.492946                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 36804.709998                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 31623.977265                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 19019.649216                       # average WriteReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 20044.440194                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 18120.028891                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 12755.083151                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 15171.663710                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 15005.967453                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 10190.993553                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs       128848                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs            18060                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs            26365                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs     4.435161                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs     4.887085                       # average number of cycles each access was blocked
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks      1546042                       # number of writebacks
-system.cpu0.dcache.writebacks::total          1546042                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data       343252                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total       343252                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data        17347                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total        17347                       # number of WriteReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu2.data       360599                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total       360599                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu2.data       360599                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total       360599                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       225418                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data       575479                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       800897                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data        62696                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data        84608                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       147304                       # number of WriteReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu1.data       288114                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu2.data       660087                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total       948201                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu1.data       288114                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu2.data       660087                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total       948201                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   2768607746                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data   8066658535                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total  10835266281                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   1923226701                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data   2756691504                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total   4679918205                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   4691834447                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data  10823350039                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  15515184486                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   4691834447                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data  10823350039                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  15515184486                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data  30492689000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data  33165040000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total  63657729000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    394150500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data    725206000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   1119356500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data  30886839500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data  33890246000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total  64777085500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.087511                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.118564                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.060350                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.037581                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.030000                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.017533                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.067885                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.086016                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.043751                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.067885                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.086016                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.043751                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12282.105892                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14017.294350                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13528.913557                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 30675.429070                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 32581.924924                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31770.476056                       # average WriteReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 16284.645824                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 16396.853807                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16362.759042                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 16284.645824                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 16396.853807                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16362.759042                       # average overall mshr miss latency
+system.cpu0.dcache.writebacks::writebacks      1547750                       # number of writebacks
+system.cpu0.dcache.writebacks::total          1547750                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data           72                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data       345273                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total       345345                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data         1671                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data        26387                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total        28058                       # number of WriteReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu1.data         1743                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu2.data       371660                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total       373403                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu1.data         1743                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu2.data       371660                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total       373403                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       171687                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data       405767                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total       577454                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data        62425                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data        95586                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       158011                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data        75736                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data       178762                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total       254498                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu1.data       234112                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu2.data       501353                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total       735465                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu1.data       309848                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu2.data       680115                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total       989963                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   2023850750                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data   5632729880                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total   7656580630                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   2144841050                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data   3093501359                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total   5238342409                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    984108500                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data   2694382756                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   3678491256                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   4168691800                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data   8726231239                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  12894923039                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   5152800300                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data  11420613995                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  16573414295                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data  30657477000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data  33314384500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total  63971861500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    501111500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data    893222000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   1394333500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data  31158588500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data  34207606500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total  65366195000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.060792                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.085267                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.045070                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.034642                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.032158                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.018807                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.863187                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data     0.843348                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.546074                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.050606                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.064849                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.034669                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.065731                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.085623                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.045662                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11788.025593                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13881.685499                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13259.204421                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34358.687225                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 32363.540257                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33151.757846                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 12993.932872                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 15072.458106                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14453.910270                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 17806.399501                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 17405.363564                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17533.020659                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 16630.090561                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 16792.180727                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16741.448211                       # average overall mshr miss latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -1394,377 +1443,376 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf
 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average overall mshr uncacheable latency
 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.numCycles                      2604023259                       # number of cpu cycles simulated
+system.cpu1.numCycles                      2606024060                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                   34762499                       # Number of instructions committed
-system.cpu1.committedOps                     67606793                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses             62736553                       # Number of integer alu accesses
+system.cpu1.committedInsts                   35944624                       # Number of instructions committed
+system.cpu1.committedOps                     69816061                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses             64937038                       # Number of integer alu accesses
 system.cpu1.num_fp_alu_accesses                     0                       # Number of float alu accesses
-system.cpu1.num_func_calls                     437056                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts      6403696                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                    62736553                       # number of integer instructions
+system.cpu1.num_func_calls                     484528                       # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts      6597164                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                    64937038                       # number of integer instructions
 system.cpu1.num_fp_insts                            0                       # number of float instructions
-system.cpu1.num_int_register_reads          115724590                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes          54164636                       # number of times the integer registers were written
+system.cpu1.num_int_register_reads          120144832                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes          55989327                       # number of times the integer registers were written
 system.cpu1.num_fp_register_reads                   0                       # number of times the floating registers were read
 system.cpu1.num_fp_register_writes                  0                       # number of times the floating registers were written
-system.cpu1.num_cc_register_reads            35537675                       # number of times the CC registers were read
-system.cpu1.num_cc_register_writes           26584960                       # number of times the CC registers were written
-system.cpu1.num_mem_refs                      4433444                       # number of memory refs
-system.cpu1.num_load_insts                    2764122                       # Number of load instructions
-system.cpu1.num_store_insts                   1669322                       # Number of store instructions
-system.cpu1.num_idle_cycles              2476870816.288117                       # Number of idle cycles
-system.cpu1.num_busy_cycles              127152442.711883                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.048829                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.951171                       # Percentage of idle cycles
-system.cpu1.Branches                          7001569                       # Number of branches fetched
-system.cpu1.op_class::No_OpClass                28648      0.04%      0.04% # Class of executed instruction
-system.cpu1.op_class::IntAlu                 63095899     93.33%     93.37% # Class of executed instruction
-system.cpu1.op_class::IntMult                   28577      0.04%     93.41% # Class of executed instruction
-system.cpu1.op_class::IntDiv                    20525      0.03%     93.44% # Class of executed instruction
-system.cpu1.op_class::FloatAdd                      0      0.00%     93.44% # Class of executed instruction
-system.cpu1.op_class::FloatCmp                      0      0.00%     93.44% # Class of executed instruction
-system.cpu1.op_class::FloatCvt                      0      0.00%     93.44% # Class of executed instruction
-system.cpu1.op_class::FloatMult                     0      0.00%     93.44% # Class of executed instruction
-system.cpu1.op_class::FloatDiv                      0      0.00%     93.44% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt                     0      0.00%     93.44% # Class of executed instruction
-system.cpu1.op_class::SimdAdd                       0      0.00%     93.44% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc                    0      0.00%     93.44% # Class of executed instruction
-system.cpu1.op_class::SimdAlu                       0      0.00%     93.44% # Class of executed instruction
-system.cpu1.op_class::SimdCmp                       0      0.00%     93.44% # Class of executed instruction
-system.cpu1.op_class::SimdCvt                       0      0.00%     93.44% # Class of executed instruction
-system.cpu1.op_class::SimdMisc                      0      0.00%     93.44% # Class of executed instruction
-system.cpu1.op_class::SimdMult                      0      0.00%     93.44% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc                   0      0.00%     93.44% # Class of executed instruction
-system.cpu1.op_class::SimdShift                     0      0.00%     93.44% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc                  0      0.00%     93.44% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt                      0      0.00%     93.44% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd                  0      0.00%     93.44% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu                  0      0.00%     93.44% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp                  0      0.00%     93.44% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt                  0      0.00%     93.44% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv                  0      0.00%     93.44% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc                 0      0.00%     93.44% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult                 0      0.00%     93.44% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     93.44% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     93.44% # Class of executed instruction
-system.cpu1.op_class::MemRead                 2764122      4.09%     97.53% # Class of executed instruction
-system.cpu1.op_class::MemWrite                1669322      2.47%    100.00% # Class of executed instruction
+system.cpu1.num_cc_register_reads            36928761                       # number of times the CC registers were read
+system.cpu1.num_cc_register_writes           27400948                       # number of times the CC registers were written
+system.cpu1.num_mem_refs                      4904439                       # number of memory refs
+system.cpu1.num_load_insts                    3100845                       # Number of load instructions
+system.cpu1.num_store_insts                   1803594                       # Number of store instructions
+system.cpu1.num_idle_cycles              2475176569.081452                       # Number of idle cycles
+system.cpu1.num_busy_cycles              130847490.918548                       # Number of busy cycles
+system.cpu1.not_idle_fraction                0.050210                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                    0.949790                       # Percentage of idle cycles
+system.cpu1.Branches                          7263647                       # Number of branches fetched
+system.cpu1.op_class::No_OpClass                35052      0.05%      0.05% # Class of executed instruction
+system.cpu1.op_class::IntAlu                 64819822     92.84%     92.89% # Class of executed instruction
+system.cpu1.op_class::IntMult                   29822      0.04%     92.94% # Class of executed instruction
+system.cpu1.op_class::IntDiv                    27277      0.04%     92.98% # Class of executed instruction
+system.cpu1.op_class::FloatAdd                      0      0.00%     92.98% # Class of executed instruction
+system.cpu1.op_class::FloatCmp                      0      0.00%     92.98% # Class of executed instruction
+system.cpu1.op_class::FloatCvt                      0      0.00%     92.98% # Class of executed instruction
+system.cpu1.op_class::FloatMult                     0      0.00%     92.98% # Class of executed instruction
+system.cpu1.op_class::FloatDiv                      0      0.00%     92.98% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt                     0      0.00%     92.98% # Class of executed instruction
+system.cpu1.op_class::SimdAdd                       0      0.00%     92.98% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc                    0      0.00%     92.98% # Class of executed instruction
+system.cpu1.op_class::SimdAlu                       0      0.00%     92.98% # Class of executed instruction
+system.cpu1.op_class::SimdCmp                       0      0.00%     92.98% # Class of executed instruction
+system.cpu1.op_class::SimdCvt                       0      0.00%     92.98% # Class of executed instruction
+system.cpu1.op_class::SimdMisc                      0      0.00%     92.98% # Class of executed instruction
+system.cpu1.op_class::SimdMult                      0      0.00%     92.98% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc                   0      0.00%     92.98% # Class of executed instruction
+system.cpu1.op_class::SimdShift                     0      0.00%     92.98% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc                  0      0.00%     92.98% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt                      0      0.00%     92.98% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd                  0      0.00%     92.98% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu                  0      0.00%     92.98% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp                  0      0.00%     92.98% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt                  0      0.00%     92.98% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv                  0      0.00%     92.98% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc                 0      0.00%     92.98% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult                 0      0.00%     92.98% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     92.98% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     92.98% # Class of executed instruction
+system.cpu1.op_class::MemRead                 3100845      4.44%     97.42% # Class of executed instruction
+system.cpu1.op_class::MemWrite                1803594      2.58%    100.00% # Class of executed instruction
 system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu1.op_class::total                  67607093                       # Class of executed instruction
+system.cpu1.op_class::total                  69816412                       # Class of executed instruction
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
-system.cpu2.branchPred.lookups               28894520                       # Number of BP lookups
-system.cpu2.branchPred.condPredicted         28894520                       # Number of conditional branches predicted
-system.cpu2.branchPred.condIncorrect           314484                       # Number of conditional branches incorrect
-system.cpu2.branchPred.BTBLookups            26386768                       # Number of BTB lookups
-system.cpu2.branchPred.BTBHits               25807983                       # Number of BTB hits
+system.cpu2.branchPred.lookups               29512659                       # Number of BP lookups
+system.cpu2.branchPred.condPredicted         29512659                       # Number of conditional branches predicted
+system.cpu2.branchPred.condIncorrect           322904                       # Number of conditional branches incorrect
+system.cpu2.branchPred.BTBLookups            26886254                       # Number of BTB lookups
+system.cpu2.branchPred.BTBHits               26249300                       # Number of BTB hits
 system.cpu2.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu2.branchPred.BTBHitPct            97.806533                       # BTB Hit Percentage
-system.cpu2.branchPred.usedRAS                 541788                       # Number of times the RAS was used to get a target.
-system.cpu2.branchPred.RASInCorrect             61672                       # Number of incorrect RAS predictions.
-system.cpu2.numCycles                       154118891                       # number of cpu cycles simulated
+system.cpu2.branchPred.BTBHitPct            97.630931                       # BTB Hit Percentage
+system.cpu2.branchPred.usedRAS                 591365                       # Number of times the RAS was used to get a target.
+system.cpu2.branchPred.RASInCorrect             64668                       # Number of incorrect RAS predictions.
+system.cpu2.numCycles                       155365551                       # number of cpu cycles simulated
 system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu2.fetch.icacheStallCycles           9526926                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu2.fetch.Insts                     142222809                       # Number of instructions fetch has processed
-system.cpu2.fetch.Branches                   28894520                       # Number of branches that fetch encountered
-system.cpu2.fetch.predictedBranches          26349771                       # Number of branches that fetch has predicted taken
-system.cpu2.fetch.Cycles                     54464711                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu2.fetch.SquashCycles                1558370                       # Number of cycles fetch has spent squashing
-system.cpu2.fetch.TlbCycles                     64917                       # Number of cycles fetch has spent waiting for tlb
-system.cpu2.fetch.BlockedCycles              23183087                       # Number of cycles fetch has spent blocked
-system.cpu2.fetch.MiscStallCycles                4981                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu2.fetch.PendingDrainCycles             6096                       # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu2.fetch.PendingTrapStallCycles        25004                       # Number of stall cycles due to pending traps
-system.cpu2.fetch.IcacheWaitRetryStallCycles          241                       # Number of stall cycles due to full MSHR
-system.cpu2.fetch.CacheLines                  3179586                       # Number of cache lines fetched
-system.cpu2.fetch.IcacheSquashes               151181                       # Number of outstanding Icache misses that were squashed
-system.cpu2.fetch.ItlbSquashes                   1925                       # Number of outstanding ITLB misses that were squashed
-system.cpu2.fetch.rateDist::samples          88503258                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::mean             3.167922                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::stdev            3.413230                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.icacheStallCycles          10587640                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu2.fetch.Insts                     145508462                       # Number of instructions fetch has processed
+system.cpu2.fetch.Branches                   29512659                       # Number of branches that fetch encountered
+system.cpu2.fetch.predictedBranches          26840665                       # Number of branches that fetch has predicted taken
+system.cpu2.fetch.Cycles                    143230873                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu2.fetch.SquashCycles                 673912                       # Number of cycles fetch has spent squashing
+system.cpu2.fetch.TlbCycles                     95091                       # Number of cycles fetch has spent waiting for tlb
+system.cpu2.fetch.MiscStallCycles                7931                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu2.fetch.PendingDrainCycles             8903                       # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu2.fetch.PendingTrapStallCycles        52631                       # Number of stall cycles due to pending traps
+system.cpu2.fetch.PendingQuiesceStallCycles         2801                       # Number of stall cycles due to pending quiesce instructions
+system.cpu2.fetch.IcacheWaitRetryStallCycles          311                       # Number of stall cycles due to full MSHR
+system.cpu2.fetch.CacheLines                  3432374                       # Number of cache lines fetched
+system.cpu2.fetch.IcacheSquashes               167414                       # Number of outstanding Icache misses that were squashed
+system.cpu2.fetch.ItlbSquashes                   3341                       # Number of outstanding ITLB misses that were squashed
+system.cpu2.fetch.rateDist::samples         154322486                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::mean             1.857387                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::stdev            3.033367                       # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::0                34173678     38.61%     38.61% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::1                  596420      0.67%     39.29% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::2                23721602     26.80%     66.09% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::3                  320974      0.36%     66.45% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::4                  619988      0.70%     67.15% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::5                  815233      0.92%     68.07% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::6                  353145      0.40%     68.47% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::7                  523827      0.59%     69.07% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::8                27378391     30.93%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::0                98410042     63.77%     63.77% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::1                  833989      0.54%     64.31% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::2                24035117     15.57%     79.88% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::3                  597750      0.39%     80.27% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::4                  798628      0.52%     80.79% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::5                  859445      0.56%     81.35% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::6                  568143      0.37%     81.71% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::7                  716402      0.46%     82.18% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::8                27502970     17.82%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::total            88503258                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.branchRate                 0.187482                       # Number of branch fetches per cycle
-system.cpu2.fetch.rate                       0.922812                       # Number of inst fetches per cycle
-system.cpu2.decode.IdleCycles                10770329                       # Number of cycles decode is idle
-system.cpu2.decode.BlockedCycles             22316529                       # Number of cycles decode is blocked
-system.cpu2.decode.RunCycles                 33210052                       # Number of cycles decode is running
-system.cpu2.decode.UnblockCycles               993418                       # Number of cycles decode is unblocking
-system.cpu2.decode.SquashCycles               1230628                       # Number of cycles decode is squashing
-system.cpu2.decode.DecodedInsts             279539625                       # Number of instructions handled by decode
-system.cpu2.decode.SquashedInsts                   15                       # Number of squashed instructions handled by decode
-system.cpu2.rename.SquashCycles               1230628                       # Number of cycles rename is squashing
-system.cpu2.rename.IdleCycles                11632631                       # Number of cycles rename is idle
-system.cpu2.rename.BlockCycles               11620518                       # Number of cycles rename is blocking
-system.cpu2.rename.serializeStallCycles       4366536                       # count of cycles rename stalled for serializing inst
-system.cpu2.rename.RunCycles                 33251587                       # Number of cycles rename is running
-system.cpu2.rename.UnblockCycles              6419117                       # Number of cycles rename is unblocking
-system.cpu2.rename.RenamedInsts             278526444                       # Number of instructions processed by rename
-system.cpu2.rename.ROBFullEvents               145793                       # Number of times rename has blocked due to ROB full
-system.cpu2.rename.IQFullEvents               2942087                       # Number of times rename has blocked due to IQ full
-system.cpu2.rename.LQFullEvents                 39888                       # Number of times rename has blocked due to LQ full
-system.cpu2.rename.SQFullEvents               2722851                       # Number of times rename has blocked due to SQ full
-system.cpu2.rename.RenamedOperands          332982462                       # Number of destination operands rename has renamed
-system.cpu2.rename.RenameLookups            606515542                       # Number of register rename lookups that rename has made
-system.cpu2.rename.int_rename_lookups       372413837                       # Number of integer rename lookups
-system.cpu2.rename.fp_rename_lookups               42                       # Number of floating rename lookups
-system.cpu2.rename.CommittedMaps            321866415                       # Number of HB maps that are committed
-system.cpu2.rename.UndoneMaps                11116047                       # Number of HB maps that are undone due to squashing
-system.cpu2.rename.serializingInsts            145000                       # count of serializing insts renamed
-system.cpu2.rename.tempSerializingInsts        146469                       # count of temporary serializing insts renamed
-system.cpu2.rename.skidInsts                  9034946                       # count of insts added to the skid buffer
-system.cpu2.memDep0.insertedLoads             6263244                       # Number of loads inserted to the mem dependence unit.
-system.cpu2.memDep0.insertedStores            3375371                       # Number of stores inserted to the mem dependence unit.
-system.cpu2.memDep0.conflictingLoads           381006                       # Number of conflicting loads.
-system.cpu2.memDep0.conflictingStores          309187                       # Number of conflicting stores.
-system.cpu2.iq.iqInstsAdded                 276743563                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu2.iq.iqNonSpecInstsAdded             411647                       # Number of non-speculative instructions added to the IQ
-system.cpu2.iq.iqInstsIssued                274777165                       # Number of instructions issued
-system.cpu2.iq.iqSquashedInstsIssued            83308                       # Number of squashed instructions issued
-system.cpu2.iq.iqSquashedInstsExamined        7862427                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu2.iq.iqSquashedOperandsExamined     12385425                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu2.iq.iqSquashedNonSpecRemoved         57804                       # Number of squashed non-spec instructions that were removed
-system.cpu2.iq.issued_per_cycle::samples     88503258                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::mean        3.104712                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::stdev       2.400001                       # Number of insts issued each cycle
+system.cpu2.fetch.rateDist::total           154322486                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.branchRate                 0.189956                       # Number of branch fetches per cycle
+system.cpu2.fetch.rate                       0.936556                       # Number of inst fetches per cycle
+system.cpu2.decode.IdleCycles                10280285                       # Number of cycles decode is idle
+system.cpu2.decode.BlockedCycles             95091051                       # Number of cycles decode is blocked
+system.cpu2.decode.RunCycles                 22517334                       # Number of cycles decode is running
+system.cpu2.decode.UnblockCycles              5911995                       # Number of cycles decode is unblocking
+system.cpu2.decode.SquashCycles                337607                       # Number of cycles decode is squashing
+system.cpu2.decode.DecodedInsts             283677190                       # Number of instructions handled by decode
+system.cpu2.rename.SquashCycles                337607                       # Number of cycles rename is squashing
+system.cpu2.rename.IdleCycles                12887048                       # Number of cycles rename is idle
+system.cpu2.rename.BlockCycles               76613528                       # Number of cycles rename is blocking
+system.cpu2.rename.serializeStallCycles       4915145                       # count of cycles rename stalled for serializing inst
+system.cpu2.rename.RunCycles                 25582017                       # Number of cycles rename is running
+system.cpu2.rename.UnblockCycles             13802994                       # Number of cycles rename is unblocking
+system.cpu2.rename.RenamedInsts             282449598                       # Number of instructions processed by rename
+system.cpu2.rename.ROBFullEvents               208301                       # Number of times rename has blocked due to ROB full
+system.cpu2.rename.IQFullEvents               6363616                       # Number of times rename has blocked due to IQ full
+system.cpu2.rename.LQFullEvents                 49211                       # Number of times rename has blocked due to LQ full
+system.cpu2.rename.SQFullEvents               4861555                       # Number of times rename has blocked due to SQ full
+system.cpu2.rename.RenamedOperands          337331977                       # Number of destination operands rename has renamed
+system.cpu2.rename.RenameLookups            615247721                       # Number of register rename lookups that rename has made
+system.cpu2.rename.int_rename_lookups       378014471                       # Number of integer rename lookups
+system.cpu2.rename.fp_rename_lookups               38                       # Number of floating rename lookups
+system.cpu2.rename.CommittedMaps            325050122                       # Number of HB maps that are committed
+system.cpu2.rename.UndoneMaps                12281853                       # Number of HB maps that are undone due to squashing
+system.cpu2.rename.serializingInsts            158846                       # count of serializing insts renamed
+system.cpu2.rename.tempSerializingInsts        160455                       # count of temporary serializing insts renamed
+system.cpu2.rename.skidInsts                 28628976                       # count of insts added to the skid buffer
+system.cpu2.memDep0.insertedLoads             6469632                       # Number of loads inserted to the mem dependence unit.
+system.cpu2.memDep0.insertedStores            3638513                       # Number of stores inserted to the mem dependence unit.
+system.cpu2.memDep0.conflictingLoads           420201                       # Number of conflicting loads.
+system.cpu2.memDep0.conflictingStores          343826                       # Number of conflicting stores.
+system.cpu2.iq.iqInstsAdded                 280493266                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu2.iq.iqNonSpecInstsAdded             428842                       # Number of non-speculative instructions added to the IQ
+system.cpu2.iq.iqInstsIssued                278404006                       # Number of instructions issued
+system.cpu2.iq.iqSquashedInstsIssued           102314                       # Number of squashed instructions issued
+system.cpu2.iq.iqSquashedInstsExamined        8748691                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu2.iq.iqSquashedOperandsExamined     13528194                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu2.iq.iqSquashedNonSpecRemoved         64074                       # Number of squashed non-spec instructions that were removed
+system.cpu2.iq.issued_per_cycle::samples    154322486                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::mean        1.804040                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::stdev       2.401684                       # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::0           25772149     29.12%     29.12% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::1            5479119      6.19%     35.31% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::2            3780646      4.27%     39.58% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::3            2658058      3.00%     42.59% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::4           25098242     28.36%     70.94% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::5            1415095      1.60%     72.54% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::6           23897363     27.00%     99.55% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::7             310729      0.35%     99.90% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::8              91857      0.10%    100.00% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::0           91177599     59.08%     59.08% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::1            5361636      3.47%     62.56% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::2            3887403      2.52%     65.08% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::3            4108764      2.66%     67.74% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::4           21799190     14.13%     81.86% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::5            3056480      1.98%     83.84% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::6           24267786     15.73%     99.57% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::7             453628      0.29%     99.86% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::8             210000      0.14%    100.00% # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::total       88503258                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::total      154322486                       # Number of insts issued each cycle
 system.cpu2.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntAlu                 130084     34.74%     34.74% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntMult                     0      0.00%     34.74% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntDiv                    103      0.03%     34.77% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatAdd                    0      0.00%     34.77% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCmp                    0      0.00%     34.77% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCvt                    0      0.00%     34.77% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatMult                   0      0.00%     34.77% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatDiv                    0      0.00%     34.77% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%     34.77% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAdd                     0      0.00%     34.77% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%     34.77% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAlu                     0      0.00%     34.77% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCmp                     0      0.00%     34.77% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCvt                     0      0.00%     34.77% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMisc                    0      0.00%     34.77% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMult                    0      0.00%     34.77% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%     34.77% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShift                   0      0.00%     34.77% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%     34.77% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%     34.77% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%     34.77% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%     34.77% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%     34.77% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%     34.77% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%     34.77% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%     34.77% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%     34.77% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%     34.77% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%     34.77% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemRead                196279     52.42%     87.18% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemWrite                48005     12.82%    100.00% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntAlu                2321368     89.34%     89.34% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntMult                   246      0.01%     89.35% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntDiv                      0      0.00%     89.35% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatAdd                    0      0.00%     89.35% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCmp                    0      0.00%     89.35% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCvt                    0      0.00%     89.35% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatMult                   0      0.00%     89.35% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatDiv                    0      0.00%     89.35% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%     89.35% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAdd                     0      0.00%     89.35% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%     89.35% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAlu                     0      0.00%     89.35% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCmp                     0      0.00%     89.35% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCvt                     0      0.00%     89.35% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMisc                    0      0.00%     89.35% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMult                    0      0.00%     89.35% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%     89.35% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShift                   0      0.00%     89.35% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%     89.35% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%     89.35% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%     89.35% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%     89.35% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%     89.35% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%     89.35% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%     89.35% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%     89.35% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%     89.35% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%     89.35% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%     89.35% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemRead                217075      8.35%     97.70% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemWrite                59662      2.30%    100.00% # attempts to use FU when none available
 system.cpu2.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu2.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu2.iq.FU_type_0::No_OpClass            79957      0.03%      0.03% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntAlu            264964709     96.43%     96.46% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntMult               54296      0.02%     96.48% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntDiv                50937      0.02%     96.50% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatAdd                  0      0.00%     96.50% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     96.50% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCvt                  0      0.00%     96.50% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     96.50% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatDiv                  0      0.00%     96.50% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     96.50% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     96.50% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     96.50% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     96.50% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     96.50% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     96.50% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMisc                  0      0.00%     96.50% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     96.50% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     96.50% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     96.50% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     96.50% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     96.50% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     96.50% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     96.50% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     96.50% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     96.50% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     96.50% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMisc             0      0.00%     96.50% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     96.50% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     96.50% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     96.50% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemRead             6495012      2.36%     98.86% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemWrite            3132254      1.14%    100.00% # Type of FU issued
+system.cpu2.iq.FU_type_0::No_OpClass            72561      0.03%      0.03% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntAlu            268083598     96.29%     96.32% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntMult               57882      0.02%     96.34% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntDiv                47134      0.02%     96.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatAdd                  0      0.00%     96.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     96.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCvt                  0      0.00%     96.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     96.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatDiv                  0      0.00%     96.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     96.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     96.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     96.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     96.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     96.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     96.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMisc                  0      0.00%     96.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     96.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     96.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     96.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     96.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     96.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     96.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     96.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     96.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     96.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     96.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMisc             0      0.00%     96.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     96.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     96.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     96.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemRead             6794594      2.44%     98.80% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemWrite            3348237      1.20%    100.00% # Type of FU issued
 system.cpu2.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu2.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::total             274777165                       # Type of FU issued
-system.cpu2.iq.rate                          1.782891                       # Inst issue rate
-system.cpu2.iq.fu_busy_cnt                     374471                       # FU busy when requested
-system.cpu2.iq.fu_busy_rate                  0.001363                       # FU busy rate (busy events/executed inst)
-system.cpu2.iq.int_inst_queue_reads         638559252                       # Number of integer instruction queue reads
-system.cpu2.iq.int_inst_queue_writes        285021199                       # Number of integer instruction queue writes
-system.cpu2.iq.int_inst_queue_wakeup_accesses    273394851                       # Number of integer instruction queue wakeup accesses
-system.cpu2.iq.fp_inst_queue_reads                 45                       # Number of floating instruction queue reads
-system.cpu2.iq.fp_inst_queue_writes                74                       # Number of floating instruction queue writes
-system.cpu2.iq.fp_inst_queue_wakeup_accesses           14                       # Number of floating instruction queue wakeup accesses
-system.cpu2.iq.int_alu_accesses             275071659                       # Number of integer alu accesses
-system.cpu2.iq.fp_alu_accesses                     20                       # Number of floating point alu accesses
-system.cpu2.iew.lsq.thread0.forwLoads          655974                       # Number of loads that had data forwarded from stores
+system.cpu2.iq.FU_type_0::total             278404006                       # Type of FU issued
+system.cpu2.iq.rate                          1.791929                       # Inst issue rate
+system.cpu2.iq.fu_busy_cnt                    2598351                       # FU busy when requested
+system.cpu2.iq.fu_busy_rate                  0.009333                       # FU busy rate (busy events/executed inst)
+system.cpu2.iq.int_inst_queue_reads         713831099                       # Number of integer instruction queue reads
+system.cpu2.iq.int_inst_queue_writes        289675272                       # Number of integer instruction queue writes
+system.cpu2.iq.int_inst_queue_wakeup_accesses    276815941                       # Number of integer instruction queue wakeup accesses
+system.cpu2.iq.fp_inst_queue_reads                 63                       # Number of floating instruction queue reads
+system.cpu2.iq.fp_inst_queue_writes                70                       # Number of floating instruction queue writes
+system.cpu2.iq.fp_inst_queue_wakeup_accesses           18                       # Number of floating instruction queue wakeup accesses
+system.cpu2.iq.int_alu_accesses             280929766                       # Number of integer alu accesses
+system.cpu2.iq.fp_alu_accesses                     30                       # Number of floating point alu accesses
+system.cpu2.iew.lsq.thread0.forwLoads          708692                       # Number of loads that had data forwarded from stores
 system.cpu2.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu2.iew.lsq.thread0.squashedLoads      1102337                       # Number of loads squashed
-system.cpu2.iew.lsq.thread0.ignoredResponses         6308                       # Number of memory responses ignored because the instruction is squashed
-system.cpu2.iew.lsq.thread0.memOrderViolation         4079                       # Number of memory ordering violations
-system.cpu2.iew.lsq.thread0.squashedStores       550460                       # Number of stores squashed
+system.cpu2.iew.lsq.thread0.squashedLoads      1202973                       # Number of loads squashed
+system.cpu2.iew.lsq.thread0.ignoredResponses         6613                       # Number of memory responses ignored because the instruction is squashed
+system.cpu2.iew.lsq.thread0.memOrderViolation         5162                       # Number of memory ordering violations
+system.cpu2.iew.lsq.thread0.squashedStores       660777                       # Number of stores squashed
 system.cpu2.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu2.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu2.iew.lsq.thread0.rescheduledLoads       656385                       # Number of loads that were rescheduled
-system.cpu2.iew.lsq.thread0.cacheBlocked         7890                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu2.iew.lsq.thread0.rescheduledLoads       754641                       # Number of loads that were rescheduled
+system.cpu2.iew.lsq.thread0.cacheBlocked        21520                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu2.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu2.iew.iewSquashCycles               1230628                       # Number of cycles IEW is squashing
-system.cpu2.iew.iewBlockCycles                6003858                       # Number of cycles IEW is blocking
-system.cpu2.iew.iewUnblockCycles              2680102                       # Number of cycles IEW is unblocking
-system.cpu2.iew.iewDispatchedInsts          277155210                       # Number of instructions dispatched to IQ
-system.cpu2.iew.iewDispSquashedInsts            55656                       # Number of squashed instructions skipped by dispatch
-system.cpu2.iew.iewDispLoadInsts              6263266                       # Number of dispatched load instructions
-system.cpu2.iew.iewDispStoreInsts             3375371                       # Number of dispatched store instructions
-system.cpu2.iew.iewDispNonSpecInsts            233323                       # Number of dispatched non-speculative instructions
-system.cpu2.iew.iewIQFullEvents                631738                       # Number of times the IQ has become full, causing a stall
-system.cpu2.iew.iewLSQFullEvents              1840063                       # Number of times the LSQ has become full, causing a stall
-system.cpu2.iew.memOrderViolationEvents          4079                       # Number of memory order violations
-system.cpu2.iew.predictedTakenIncorrect        177700                       # Number of branches that were predicted taken incorrectly
-system.cpu2.iew.predictedNotTakenIncorrect       182074                       # Number of branches that were predicted not taken incorrectly
-system.cpu2.iew.branchMispredicts              359774                       # Number of branch mispredicts detected at execute
-system.cpu2.iew.iewExecutedInsts            274266101                       # Number of executed instructions
-system.cpu2.iew.iewExecLoadInsts              6377623                       # Number of load instructions executed
-system.cpu2.iew.iewExecSquashedInsts           511064                       # Number of squashed instructions skipped in execute
+system.cpu2.iew.iewSquashCycles                337607                       # Number of cycles IEW is squashing
+system.cpu2.iew.iewBlockCycles               71713264                       # Number of cycles IEW is blocking
+system.cpu2.iew.iewUnblockCycles              1590839                       # Number of cycles IEW is unblocking
+system.cpu2.iew.iewDispatchedInsts          280922108                       # Number of instructions dispatched to IQ
+system.cpu2.iew.iewDispSquashedInsts            41019                       # Number of squashed instructions skipped by dispatch
+system.cpu2.iew.iewDispLoadInsts              6469632                       # Number of dispatched load instructions
+system.cpu2.iew.iewDispStoreInsts             3638513                       # Number of dispatched store instructions
+system.cpu2.iew.iewDispNonSpecInsts            247100                       # Number of dispatched non-speculative instructions
+system.cpu2.iew.iewIQFullEvents                199459                       # Number of times the IQ has become full, causing a stall
+system.cpu2.iew.iewLSQFullEvents              1088059                       # Number of times the LSQ has become full, causing a stall
+system.cpu2.iew.memOrderViolationEvents          5162                       # Number of memory order violations
+system.cpu2.iew.predictedTakenIncorrect        186556                       # Number of branches that were predicted taken incorrectly
+system.cpu2.iew.predictedNotTakenIncorrect       187873                       # Number of branches that were predicted not taken incorrectly
+system.cpu2.iew.branchMispredicts              374429                       # Number of branch mispredicts detected at execute
+system.cpu2.iew.iewExecutedInsts            277824668                       # Number of executed instructions
+system.cpu2.iew.iewExecLoadInsts              6659327                       # Number of load instructions executed
+system.cpu2.iew.iewExecSquashedInsts           530499                       # Number of squashed instructions skipped in execute
 system.cpu2.iew.exec_swp                            0                       # number of swp insts executed
 system.cpu2.iew.exec_nop                            0                       # number of nop insts executed
-system.cpu2.iew.exec_refs                     9440682                       # number of memory reference insts executed
-system.cpu2.iew.exec_branches                27899539                       # Number of branches executed
-system.cpu2.iew.exec_stores                   3063059                       # Number of stores executed
-system.cpu2.iew.exec_rate                    1.779575                       # Inst execution rate
-system.cpu2.iew.wb_sent                     274107922                       # cumulative count of insts sent to commit
-system.cpu2.iew.wb_count                    273394865                       # cumulative count of insts written-back
-system.cpu2.iew.wb_producers                213810949                       # num instructions producing a value
-system.cpu2.iew.wb_consumers                349940477                       # num instructions consuming a value
+system.cpu2.iew.exec_refs                     9922055                       # number of memory reference insts executed
+system.cpu2.iew.exec_branches                28210243                       # Number of branches executed
+system.cpu2.iew.exec_stores                   3262728                       # Number of stores executed
+system.cpu2.iew.exec_rate                    1.788200                       # Inst execution rate
+system.cpu2.iew.wb_sent                     277637651                       # cumulative count of insts sent to commit
+system.cpu2.iew.wb_count                    276815959                       # cumulative count of insts written-back
+system.cpu2.iew.wb_producers                215923076                       # num instructions producing a value
+system.cpu2.iew.wb_consumers                354065892                       # num instructions consuming a value
 system.cpu2.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu2.iew.wb_rate                      1.773922                       # insts written-back per cycle
-system.cpu2.iew.wb_fanout                    0.610992                       # average fanout of values written-back
+system.cpu2.iew.wb_rate                      1.781707                       # insts written-back per cycle
+system.cpu2.iew.wb_fanout                    0.609839                       # average fanout of values written-back
 system.cpu2.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu2.commit.commitSquashedInsts        8157845                       # The number of squashed insts skipped by commit
-system.cpu2.commit.commitNonSpecStalls         353843                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu2.commit.branchMispredicts           317282                       # The number of times a branch was mispredicted
-system.cpu2.commit.committed_per_cycle::samples     87272630                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::mean     3.082246                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::stdev     2.874009                       # Number of insts commited each cycle
+system.cpu2.commit.commitSquashedInsts        9085200                       # The number of squashed insts skipped by commit
+system.cpu2.commit.commitNonSpecStalls         364768                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu2.commit.branchMispredicts           325355                       # The number of times a branch was mispredicted
+system.cpu2.commit.committed_per_cycle::samples    152966387                       # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::mean     1.777091                       # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::stdev     2.654040                       # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::0     30201439     34.61%     34.61% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::1      4017102      4.60%     39.21% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::2      1154677      1.32%     40.53% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::3     24628965     28.22%     68.75% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::4       905267      1.04%     69.79% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::5       589610      0.68%     70.47% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::6       344278      0.39%     70.86% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::7     23302755     26.70%     97.56% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::8      2128537      2.44%    100.00% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::0     95002675     62.11%     62.11% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::1      4175839      2.73%     64.84% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::2      1266091      0.83%     65.66% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::3     24954040     16.31%     81.98% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::4       981729      0.64%     82.62% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::5       650164      0.43%     83.04% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::6       435006      0.28%     83.33% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::7     23529501     15.38%     98.71% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::8      1971342      1.29%    100.00% # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::total     87272630                       # Number of insts commited each cycle
-system.cpu2.commit.committedInsts           136196446                       # Number of instructions committed
-system.cpu2.commit.committedOps             268995718                       # Number of ops (including micro ops) committed
+system.cpu2.commit.committed_per_cycle::total    152966387                       # Number of insts commited each cycle
+system.cpu2.commit.committedInsts           137677652                       # Number of instructions committed
+system.cpu2.commit.committedOps             271835156                       # Number of ops (including micro ops) committed
 system.cpu2.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu2.commit.refs                       7985840                       # Number of memory references committed
-system.cpu2.commit.loads                      5160929                       # Number of loads committed
-system.cpu2.commit.membars                     163767                       # Number of memory barriers committed
-system.cpu2.commit.branches                  27540439                       # Number of branches committed
+system.cpu2.commit.refs                       8244394                       # Number of memory references committed
+system.cpu2.commit.loads                      5266658                       # Number of loads committed
+system.cpu2.commit.membars                     166791                       # Number of memory barriers committed
+system.cpu2.commit.branches                  27802655                       # Number of branches committed
 system.cpu2.commit.fp_insts                         0                       # Number of committed floating point instructions.
-system.cpu2.commit.int_insts                245590309                       # Number of committed integer instructions.
-system.cpu2.commit.function_calls              428081                       # Number of function calls committed.
-system.cpu2.commit.op_class_0::No_OpClass        46387      0.02%      0.02% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntAlu       260861796     96.98%     96.99% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntMult          52266      0.02%     97.01% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntDiv           49429      0.02%     97.03% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatAdd             0      0.00%     97.03% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatCmp             0      0.00%     97.03% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatCvt             0      0.00%     97.03% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatMult            0      0.00%     97.03% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatDiv             0      0.00%     97.03% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatSqrt            0      0.00%     97.03% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAdd              0      0.00%     97.03% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAddAcc            0      0.00%     97.03% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAlu              0      0.00%     97.03% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdCmp              0      0.00%     97.03% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdCvt              0      0.00%     97.03% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMisc             0      0.00%     97.03% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMult             0      0.00%     97.03% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMultAcc            0      0.00%     97.03% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdShift            0      0.00%     97.03% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdShiftAcc            0      0.00%     97.03% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdSqrt             0      0.00%     97.03% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatAdd            0      0.00%     97.03% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatAlu            0      0.00%     97.03% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatCmp            0      0.00%     97.03% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatCvt            0      0.00%     97.03% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatDiv            0      0.00%     97.03% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMisc            0      0.00%     97.03% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMult            0      0.00%     97.03% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMultAcc            0      0.00%     97.03% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatSqrt            0      0.00%     97.03% # Class of committed instruction
-system.cpu2.commit.op_class_0::MemRead        5160929      1.92%     98.95% # Class of committed instruction
-system.cpu2.commit.op_class_0::MemWrite       2824911      1.05%    100.00% # Class of committed instruction
+system.cpu2.commit.int_insts                248203210                       # Number of committed integer instructions.
+system.cpu2.commit.function_calls              440588                       # Number of function calls committed.
+system.cpu2.commit.op_class_0::No_OpClass        43200      0.02%      0.02% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntAlu       263446464     96.91%     96.93% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntMult          55564      0.02%     96.95% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntDiv           45534      0.02%     96.97% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatAdd             0      0.00%     96.97% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatCmp             0      0.00%     96.97% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatCvt             0      0.00%     96.97% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatMult            0      0.00%     96.97% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatDiv             0      0.00%     96.97% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatSqrt            0      0.00%     96.97% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAdd              0      0.00%     96.97% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAddAcc            0      0.00%     96.97% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAlu              0      0.00%     96.97% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdCmp              0      0.00%     96.97% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdCvt              0      0.00%     96.97% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMisc             0      0.00%     96.97% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMult             0      0.00%     96.97% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMultAcc            0      0.00%     96.97% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdShift            0      0.00%     96.97% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdShiftAcc            0      0.00%     96.97% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdSqrt             0      0.00%     96.97% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatAdd            0      0.00%     96.97% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatAlu            0      0.00%     96.97% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatCmp            0      0.00%     96.97% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatCvt            0      0.00%     96.97% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatDiv            0      0.00%     96.97% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMisc            0      0.00%     96.97% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMult            0      0.00%     96.97% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMultAcc            0      0.00%     96.97% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatSqrt            0      0.00%     96.97% # Class of committed instruction
+system.cpu2.commit.op_class_0::MemRead        5266658      1.94%     98.90% # Class of committed instruction
+system.cpu2.commit.op_class_0::MemWrite       2977736      1.10%    100.00% # Class of committed instruction
 system.cpu2.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu2.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu2.commit.op_class_0::total        268995718                       # Class of committed instruction
-system.cpu2.commit.bw_lim_events              2128537                       # number cycles where commit BW limit reached
+system.cpu2.commit.op_class_0::total        271835156                       # Class of committed instruction
+system.cpu2.commit.bw_lim_events              1971342                       # number cycles where commit BW limit reached
 system.cpu2.commit.bw_limited                       0                       # number of insts not committed due to BW limits
-system.cpu2.rob.rob_reads                   362270810                       # The number of ROB reads
-system.cpu2.rob.rob_writes                  555542201                       # The number of ROB writes
-system.cpu2.timesIdled                         475518                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu2.idleCycles                       65615633                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu2.quiesceCycles                  4908375985                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu2.committedInsts                  136196446                       # Number of Instructions Simulated
-system.cpu2.committedOps                    268995718                       # Number of Ops (including micro ops) Simulated
-system.cpu2.cpi                              1.131593                       # CPI: Cycles Per Instruction
-system.cpu2.cpi_total                        1.131593                       # CPI: Total CPI of All Threads
-system.cpu2.ipc                              0.883710                       # IPC: Instructions Per Cycle
-system.cpu2.ipc_total                        0.883710                       # IPC: Total IPC of All Threads
-system.cpu2.int_regfile_reads               364616127                       # number of integer regfile reads
-system.cpu2.int_regfile_writes              219111496                       # number of integer regfile writes
-system.cpu2.fp_regfile_reads                    72926                       # number of floating regfile reads
-system.cpu2.fp_regfile_writes                   72912                       # number of floating regfile writes
-system.cpu2.cc_regfile_reads                139466740                       # number of cc regfile reads
-system.cpu2.cc_regfile_writes               107376389                       # number of cc regfile writes
-system.cpu2.misc_regfile_reads               88828545                       # number of misc regfile reads
-system.cpu2.misc_regfile_writes                129118                       # number of misc regfile writes
+system.cpu2.rob.rob_reads                   431889681                       # The number of ROB reads
+system.cpu2.rob.rob_writes                  563202973                       # The number of ROB writes
+system.cpu2.timesIdled                         114782                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu2.idleCycles                        1043065                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu2.quiesceCycles                  4908353341                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu2.committedInsts                  137677652                       # Number of Instructions Simulated
+system.cpu2.committedOps                    271835156                       # Number of Ops (including micro ops) Simulated
+system.cpu2.cpi                              1.128473                       # CPI: Cycles Per Instruction
+system.cpu2.cpi_total                        1.128473                       # CPI: Total CPI of All Threads
+system.cpu2.ipc                              0.886153                       # IPC: Instructions Per Cycle
+system.cpu2.ipc_total                        0.886153                       # IPC: Total IPC of All Threads
+system.cpu2.int_regfile_reads               369541594                       # number of integer regfile reads
+system.cpu2.int_regfile_writes              221773447                       # number of integer regfile writes
+system.cpu2.fp_regfile_reads                    72930                       # number of floating regfile reads
+system.cpu2.fp_regfile_writes                   72968                       # number of floating regfile writes
+system.cpu2.cc_regfile_reads                140769340                       # number of cc regfile reads
+system.cpu2.cc_regfile_writes               108468562                       # number of cc regfile writes
+system.cpu2.misc_regfile_reads               90221682                       # number of misc regfile reads
+system.cpu2.misc_regfile_writes                135530                       # number of misc regfile writes
 system.cpu2.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu2.kern.inst.quiesce                       0                       # number of quiesce instructions executed
 
diff --git a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt
index ec3cdc9eb..effbf44c1 100644
--- a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt
@@ -1,554 +1,56 @@
 
 ---------- Begin Simulation Statistics ----------
-final_tick                                61269894500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-host_inst_rate                                 246086                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 426904                       # Number of bytes of host memory used
-host_op_rate                                   247853                       # Simulator op (including micro ops) rate (op/s)
-host_seconds                                   368.18                       # Real time elapsed on the host
-host_tick_rate                              166415131                       # Simulator tick rate (ticks/s)
+sim_seconds                                  0.061144                       # Number of seconds simulated
+sim_ticks                                 61144411500                       # Number of ticks simulated
+final_tick                                61144411500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                 253751                       # Simulator instruction rate (inst/s)
+host_op_rate                                   255015                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              171247115                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 451144                       # Number of bytes of host memory used
+host_seconds                                   357.05                       # Real time elapsed on the host
 sim_insts                                    90602849                       # Number of instructions simulated
-sim_ops                                      91253402                       # Number of ops (including micro ops) simulated
-sim_seconds                                  0.061270                       # Number of seconds simulated
-sim_ticks                                 61269894500                       # Number of ticks simulated
+sim_ops                                      91054080                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             98.707356                       # BTB Hit Percentage
-system.cpu.branchPred.BTBHits                 8859613                       # Number of BTB hits
-system.cpu.branchPred.BTBLookups              8975636                       # Number of BTB lookups
-system.cpu.branchPred.RASInCorrect               1020                       # Number of incorrect RAS predictions.
-system.cpu.branchPred.condIncorrect            765388                       # Number of conditional branches incorrect
-system.cpu.branchPred.condPredicted          17116903                       # Number of conditional branches predicted
-system.cpu.branchPred.lookups                20794461                       # Number of BP lookups
-system.cpu.branchPred.usedRAS                   54785                       # Number of times the RAS was used to get a target.
-system.cpu.committedInsts                    90602849                       # Number of instructions committed
-system.cpu.committedOps                      91253402                       # Number of ops (including micro ops) committed
-system.cpu.cpi                               1.352494                       # CPI: cycles per instruction
-system.cpu.dcache.LoadLockedReq_accesses::cpu.inst         3887                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total         3887                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_hits::cpu.inst         3887                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total         3887                       # number of LoadLockedReq hits
-system.cpu.dcache.ReadReq_accesses::cpu.inst     22606743                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     22606743                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 13018.894340                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 13018.894340                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 11024.761855                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11024.761855                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits::cpu.inst     21691800                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        21691800                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency::cpu.inst  11911546244                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  11911546244                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate::cpu.inst     0.040472                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.040472                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses::cpu.inst       914943                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        914943                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits::cpu.inst        11527                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total        11527                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst   9959946256                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   9959946256                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst     0.039962                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.039962                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses::cpu.inst       903416                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       903416                       # number of ReadReq MSHR misses
-system.cpu.dcache.StoreCondReq_accesses::cpu.inst         3887                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total         3887                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_hits::cpu.inst         3887                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total         3887                       # number of StoreCondReq hits
-system.cpu.dcache.WriteReq_accesses::cpu.inst      4734981                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total      4734981                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 31690.074425                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 31690.074425                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 28535.254491                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28535.254491                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits::cpu.inst      4661081                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        4661081                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency::cpu.inst   2341896500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   2341896500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate::cpu.inst     0.015607                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.015607                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses::cpu.inst        73900                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total        73900                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits::cpu.inst        27140                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total        27140                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst   1334308500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   1334308500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst     0.009875                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.009875                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.inst        46760                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total        46760                       # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.demand_accesses::cpu.inst     27341724                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     27341724                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency::cpu.inst 14414.262673                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 14414.262673                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 11886.487089                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 11886.487089                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits::cpu.inst      26352881                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         26352881                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency::cpu.inst  14253442744                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  14253442744                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate::cpu.inst     0.036166                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.036166                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses::cpu.inst       988843                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total         988843                       # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits::cpu.inst        38667                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total        38667                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency::cpu.inst  11294254756                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  11294254756                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate::cpu.inst     0.034752                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.034752                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses::cpu.inst       950176                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       950176                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses::cpu.inst     27341724                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     27341724                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency::cpu.inst 14414.262673                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 14414.262673                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 11886.487089                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 11886.487089                       # average overall mshr miss latency
-system.cpu.dcache.overall_hits::cpu.inst     26352881                       # number of overall hits
-system.cpu.dcache.overall_hits::total        26352881                       # number of overall hits
-system.cpu.dcache.overall_miss_latency::cpu.inst  14253442744                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  14253442744                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate::cpu.inst     0.036166                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.036166                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses::cpu.inst       988843                       # number of overall misses
-system.cpu.dcache.overall_misses::total        988843                       # number of overall misses
-system.cpu.dcache.overall_mshr_hits::cpu.inst        38667                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total        38667                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency::cpu.inst  11294254756                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  11294254756                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate::cpu.inst     0.034752                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.034752                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses::cpu.inst       950176                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       950176                       # number of overall MSHR misses
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          247                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1         2200                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2         1649                       # Occupied blocks per task id
-system.cpu.dcache.tags.avg_refs             27.742918                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.data_accesses         55649172                       # Number of data accesses
-system.cpu.dcache.tags.occ_blocks::cpu.inst  3618.532737                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.inst     0.883431                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.883431                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.replacements            946080                       # number of replacements
-system.cpu.dcache.tags.sampled_refs            950176                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.tag_accesses          55649172                       # Number of tag accesses
-system.cpu.dcache.tags.tagsinuse          3618.532737                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            26360655                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle       20496262250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks::writebacks       943298                       # number of writebacks
-system.cpu.dcache.writebacks::total            943298                       # number of writebacks
-system.cpu.discardedOps                       2065378                       # Number of ops (including micro ops) which were discarded before commit
-system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
-system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
-system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
-system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
-system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
-system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
-system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
-system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
-system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
-system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
-system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
-system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
-system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
-system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
-system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
-system.cpu.dtb.accesses                             0                       # DTB accesses
-system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.hits                                 0                       # DTB hits
-system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.inst_hits                            0                       # ITB inst hits
-system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.misses                               0                       # DTB misses
-system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
-system.cpu.dtb.read_accesses                        0                       # DTB read accesses
-system.cpu.dtb.read_hits                            0                       # DTB read hits
-system.cpu.dtb.read_misses                          0                       # DTB read misses
-system.cpu.dtb.write_accesses                       0                       # DTB write accesses
-system.cpu.dtb.write_hits                           0                       # DTB write hits
-system.cpu.dtb.write_misses                         0                       # DTB write misses
-system.cpu.icache.ReadReq_accesses::cpu.inst     27818907                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     27818907                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68915.429630                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 68915.429630                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66500.619753                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66500.619753                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits::cpu.inst     27818097                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        27818097                       # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     55821498                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     55821498                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000029                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000029                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses::cpu.inst          810                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total           810                       # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     53865502                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     53865502                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000029                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000029                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst          810                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total          810                       # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.demand_accesses::cpu.inst     27818907                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     27818907                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 68915.429630                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 68915.429630                       # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66500.619753                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 66500.619753                       # average overall mshr miss latency
-system.cpu.icache.demand_hits::cpu.inst      27818097                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         27818097                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency::cpu.inst     55821498                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     55821498                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000029                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000029                       # miss rate for demand accesses
-system.cpu.icache.demand_misses::cpu.inst          810                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total            810                       # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     53865502                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     53865502                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000029                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.000029                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses::cpu.inst          810                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total          810                       # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses::cpu.inst     27818907                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     27818907                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 68915.429630                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 68915.429630                       # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66500.619753                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 66500.619753                       # average overall mshr miss latency
-system.cpu.icache.overall_hits::cpu.inst     27818097                       # number of overall hits
-system.cpu.icache.overall_hits::total        27818097                       # number of overall hits
-system.cpu.icache.overall_miss_latency::cpu.inst     55821498                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     55821498                       # number of overall miss cycles
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000029                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000029                       # miss rate for overall accesses
-system.cpu.icache.overall_misses::cpu.inst          810                       # number of overall misses
-system.cpu.icache.overall_misses::total           810                       # number of overall misses
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     53865502                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     53865502                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000029                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.000029                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses::cpu.inst          810                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total          810                       # number of overall MSHR misses
-system.cpu.icache.tags.age_task_id_blocks_1024::0           44                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2           13                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4          748                       # Occupied blocks per task id
-system.cpu.icache.tags.avg_refs          34343.329630                       # Average number of references to valid blocks.
-system.cpu.icache.tags.data_accesses         55638624                       # Number of data accesses
-system.cpu.icache.tags.occ_blocks::cpu.inst   696.774140                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.340222                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.340222                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024          805                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.393066                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.replacements                 5                       # number of replacements
-system.cpu.icache.tags.sampled_refs               810                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.tag_accesses          55638624                       # Number of tag accesses
-system.cpu.icache.tags.tagsinuse           696.774140                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            27818097                       # Total number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.idleCycles                        13105167                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.ipc                               0.739375                       # IPC: instructions per cycle
-system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
-system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
-system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
-system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
-system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
-system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
-system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
-system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
-system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
-system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
-system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
-system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
-system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
-system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
-system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
-system.cpu.itb.accesses                             0                       # DTB accesses
-system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
-system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.hits                                 0                       # DTB hits
-system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.itb.inst_hits                            0                       # ITB inst hits
-system.cpu.itb.inst_misses                          0                       # ITB inst misses
-system.cpu.itb.misses                               0                       # DTB misses
-system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
-system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
-system.cpu.itb.read_accesses                        0                       # DTB read accesses
-system.cpu.itb.read_hits                            0                       # DTB read hits
-system.cpu.itb.read_misses                          0                       # DTB read misses
-system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.write_hits                           0                       # DTB write hits
-system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.l2cache.ReadExReq_accesses::cpu.inst        46760                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total        46760                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 65946.757667                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65946.757667                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 53094.192683                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 53094.192683                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_hits::cpu.inst        32218                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total        32218                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst    958997750                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total    958997750                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst     0.310992                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.310992                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses::cpu.inst        14542                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total        14542                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst    772095750                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    772095750                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst     0.310992                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.310992                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst        14542                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total        14542                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses::cpu.inst       904226                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total       904226                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69821.699905                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 69821.699905                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57393.301435                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57393.301435                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits::cpu.inst       903173                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total         903173                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     73522250                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total     73522250                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.001165                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.001165                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses::cpu.inst         1053                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total         1053                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            8                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total            8                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     59976000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     59976000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.001156                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.001156                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         1045                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total         1045                       # number of ReadReq MSHR misses
-system.cpu.l2cache.Writeback_accesses::writebacks       943298                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total       943298                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits::writebacks       943298                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total       943298                       # number of Writeback hits
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.demand_accesses::cpu.inst       950986                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total       950986                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66208.400128                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 66208.400128                       # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53382.418041                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53382.418041                       # average overall mshr miss latency
-system.cpu.l2cache.demand_hits::cpu.inst       935391                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total          935391                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency::cpu.inst   1032520000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total   1032520000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.016399                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.016399                       # miss rate for demand accesses
-system.cpu.l2cache.demand_misses::cpu.inst        15595                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total         15595                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_mshr_hits::cpu.inst            8                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total            8                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    832071750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    832071750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.016390                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.016390                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst        15587                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total        15587                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses::cpu.inst       950986                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total       950986                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66208.400128                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 66208.400128                       # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53382.418041                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53382.418041                       # average overall mshr miss latency
-system.cpu.l2cache.overall_hits::cpu.inst       935391                       # number of overall hits
-system.cpu.l2cache.overall_hits::total         935391                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency::cpu.inst   1032520000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total   1032520000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.016399                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.016399                       # miss rate for overall accesses
-system.cpu.l2cache.overall_misses::cpu.inst        15595                       # number of overall misses
-system.cpu.l2cache.overall_misses::total        15595                       # number of overall misses
-system.cpu.l2cache.overall_mshr_hits::cpu.inst            8                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total            8                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    832071750                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    832071750                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.016390                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.016390                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst        15587                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total        15587                       # number of overall MSHR misses
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           49                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1           14                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          524                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         1094                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        13889                       # Occupied blocks per task id
-system.cpu.l2cache.tags.avg_refs           117.618626                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.data_accesses        15216602                       # Number of data accesses
-system.cpu.l2cache.tags.occ_blocks::writebacks  9366.525575                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   902.408366                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.285844                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.027539                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.313383                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        15570                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.475159                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.sampled_refs            15570                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.tag_accesses         15216602                       # Number of tag accesses
-system.cpu.l2cache.tags.tagsinuse        10268.933941                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            1831322                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.numCycles                        122539789                       # number of cpu cycles simulated
-system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.tickCycles                       109434622                       # Number of cycles that the CPU actually ticked
-system.cpu.toL2Bus.data_through_bus         121234176                       # Total data (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1620                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2843650                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           2845270                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy     1890440000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          3.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy       1382998                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    1428632744                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          2.3                       # Layer utilization (%)
-system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
-system.cpu.toL2Bus.throughput              1978690791                       # Throughput (bytes/s)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        51840                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    121182336                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total      121234176                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.trans_dist::ReadReq         904226                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp        904226                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback       943298                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq        46760                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp        46760                       # Transaction distribution
-system.cpu.workload.num_syscalls                  442                       # Number of system calls
-system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.membus.data_through_bus                 997568                       # Total data (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        31174                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                  31174                       # Packet count per connected master and slave (bytes)
-system.membus.reqLayer0.occupancy            21774500                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy          149672750                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
-system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.throughput                     16281536                       # Throughput (bytes/s)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       997568                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total              997568                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.trans_dist::ReadReq                1045                       # Transaction distribution
-system.membus.trans_dist::ReadResp               1045                       # Transaction distribution
-system.membus.trans_dist::ReadExReq             14542                       # Transaction distribution
-system.membus.trans_dist::ReadExResp            14542                       # Transaction distribution
-system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgGap                      3930827.39                       # Average gap between requests
-system.physmem.avgMemAccLat                  23360.33                       # Average memory access latency per DRAM burst
-system.physmem.avgQLat                        4610.33                       # Average queueing delay per DRAM burst
-system.physmem.avgRdBW                          16.28                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       16.28                       # Average system read bandwidth in MiByte/s
-system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
-system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.busUtil                           0.13                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       0.13                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.bw_inst_read::cpu.inst          816845                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             816845                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst             16281536                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                16281536                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst            16281536                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               16281536                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bytesPerActivate::samples         1547                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      643.557854                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     434.536592                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     403.240998                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127            258     16.68%     16.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255          197     12.73%     29.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383           72      4.65%     34.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511           57      3.68%     37.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639           69      4.46%     42.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767          102      6.59%     48.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895           43      2.78%     51.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023           57      3.68%     55.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151          692     44.73%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total           1547                       # Bytes accessed per row activation
-system.physmem.bytesReadDRAM                   997568                       # Total number of bytes read from DRAM
-system.physmem.bytesReadSys                    997568                       # Total read bytes from the system interface side
+system.physmem.bytes_read::cpu.inst            996736                       # Number of bytes read from this memory
+system.physmem.bytes_read::total               996736                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        49600                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           49600                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst              15574                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                 15574                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst             16301343                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                16301343                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          811194                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             811194                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst            16301343                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               16301343                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                         15574                       # Number of read requests accepted
+system.physmem.writeReqs                            0                       # Number of write requests accepted
+system.physmem.readBursts                       15574                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                   996736                       # Total number of bytes read from DRAM
 system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
 system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                    996736                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
-system.physmem.bytes_inst_read::cpu.inst        50048                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           50048                       # Number of instructions bytes read from this memory
-system.physmem.bytes_read::cpu.inst            997568                       # Number of bytes read from this memory
-system.physmem.bytes_read::total               997568                       # Number of bytes read from this memory
-system.physmem.memoryStateTime::IDLE      55978709750                       # Time in different power states
-system.physmem.memoryStateTime::REF        2045680000                       # Time in different power states
-system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT        3241107750                       # Time in different power states
-system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
+system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.num_reads::cpu.inst              15587                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                 15587                       # Number of read requests responded to by this memory
-system.physmem.pageHitRate                      90.01                       # Row buffer hit rate, read and write combined
-system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.perBankRdBursts::0                 994                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                 891                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                 951                       # Per bank write bursts
+system.physmem.perBankRdBursts::0                 993                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                 890                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                 950                       # Per bank write bursts
 system.physmem.perBankRdBursts::3                1028                       # Per bank write bursts
-system.physmem.perBankRdBursts::4                1052                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                1115                       # Per bank write bursts
+system.physmem.perBankRdBursts::4                1050                       # Per bank write bursts
+system.physmem.perBankRdBursts::5                1113                       # Per bank write bursts
 system.physmem.perBankRdBursts::6                1088                       # Per bank write bursts
 system.physmem.perBankRdBursts::7                1088                       # Per bank write bursts
 system.physmem.perBankRdBursts::8                1024                       # Per bank write bursts
 system.physmem.perBankRdBursts::9                 962                       # Per bank write bursts
-system.physmem.perBankRdBursts::10                941                       # Per bank write bursts
+system.physmem.perBankRdBursts::10                938                       # Per bank write bursts
 system.physmem.perBankRdBursts::11                899                       # Per bank write bursts
-system.physmem.perBankRdBursts::12                904                       # Per bank write bursts
-system.physmem.perBankRdBursts::13                869                       # Per bank write bursts
+system.physmem.perBankRdBursts::12                903                       # Per bank write bursts
+system.physmem.perBankRdBursts::13                867                       # Per bank write bursts
 system.physmem.perBankRdBursts::14                877                       # Per bank write bursts
 system.physmem.perBankRdBursts::15                904                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
@@ -567,8 +69,25 @@ system.physmem.perBankWrBursts::12                  0                       # Pe
 system.physmem.perBankWrBursts::13                  0                       # Per bank write bursts
 system.physmem.perBankWrBursts::14                  0                       # Per bank write bursts
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
-system.physmem.rdQLenPdf::0                     15468                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       110                       # What read queue length does an incoming req see
+system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
+system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
+system.physmem.totGap                     61144323500                       # Total gap between requests
+system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
+system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
+system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
+system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
+system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
+system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
+system.physmem.readPktSize::6                   15574                       # Read request sizes (log2)
+system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
+system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
+system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
+system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
+system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
+system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
+system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                     15451                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       114                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::2                         9                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
@@ -599,22 +118,6 @@ system.physmem.rdQLenPdf::28                        0                       # Wh
 system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.readBursts                       15587                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                   15587                       # Read request sizes (log2)
-system.physmem.readReqs                         15587                       # Number of read requests accepted
-system.physmem.readRowHitRate                   90.01                       # Row buffer hit rate for reads
-system.physmem.readRowHits                      14030                       # Number of row buffer hits during reads
-system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.totBusLat                     77935000                       # Total ticks spent in databus transfers
-system.physmem.totGap                     61269806500                       # Total gap between requests
-system.physmem.totMemAccLat                 364117500                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totQLat                       71861250                       # Total ticks spent queuing
 system.physmem.wrQLenPdf::0                         0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::1                         0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::2                         0                       # What write queue length does an incoming req see
@@ -679,17 +182,514 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.writeReqs                            0                       # Number of write requests accepted
-system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
+system.physmem.bytesPerActivate::samples         1531                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      649.865447                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     447.084914                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     397.724653                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127            242     15.81%     15.81% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255          164     10.71%     26.52% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383           94      6.14%     32.66% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511           77      5.03%     37.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639           65      4.25%     41.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767          106      6.92%     48.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895           51      3.33%     52.19% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023           28      1.83%     54.02% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151          704     45.98%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total           1531                       # Bytes accessed per row activation
+system.physmem.totQLat                       71444000                       # Total ticks spent queuing
+system.physmem.totMemAccLat                 363456500                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                     77870000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        4587.39                       # Average queueing delay per DRAM burst
+system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
+system.physmem.avgMemAccLat                  23337.39                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          16.30                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       16.30                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
+system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
+system.physmem.busUtil                           0.13                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       0.13                       # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
+system.physmem.readRowHits                      14033                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.physmem.readRowHitRate                   90.11                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
+system.physmem.avgGap                      3926051.34                       # Average gap between requests
+system.physmem.pageHitRate                      90.11                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE      55905599000                       # Time in different power states
+system.physmem.memoryStateTime::REF        2041520000                       # Time in different power states
+system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
+system.physmem.memoryStateTime::ACT        3193563500                       # Time in different power states
+system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
+system.membus.throughput                     16301343                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq                1030                       # Transaction distribution
+system.membus.trans_dist::ReadResp               1030                       # Transaction distribution
+system.membus.trans_dist::ReadExReq             14544                       # Transaction distribution
+system.membus.trans_dist::ReadExResp            14544                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        31148                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                  31148                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       996736                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total              996736                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus                 996736                       # Total data (bytes)
+system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy            21821000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
+system.membus.respLayer1.occupancy          149563500                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.cpu.branchPred.lookups                20748985                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          17053333                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            764055                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups              8969348                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                 8846034                       # Number of BTB hits
+system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.branchPred.BTBHitPct             98.625162                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                   62305                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect                 17                       # Number of incorrect RAS predictions.
+system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
+system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
+system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
+system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
+system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
+system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
+system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
+system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
+system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
+system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
+system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
+system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
+system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
+system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
+system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
+system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
+system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.dtb.inst_hits                            0                       # ITB inst hits
+system.cpu.dtb.inst_misses                          0                       # ITB inst misses
+system.cpu.dtb.read_hits                            0                       # DTB read hits
+system.cpu.dtb.read_misses                          0                       # DTB read misses
+system.cpu.dtb.write_hits                           0                       # DTB write hits
+system.cpu.dtb.write_misses                         0                       # DTB write misses
+system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                        0                       # DTB read accesses
+system.cpu.dtb.write_accesses                       0                       # DTB write accesses
+system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.dtb.hits                                 0                       # DTB hits
+system.cpu.dtb.misses                               0                       # DTB misses
+system.cpu.dtb.accesses                             0                       # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
+system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
+system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
+system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
+system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
+system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
+system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
+system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
+system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
+system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
+system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
+system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
+system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
+system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
+system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
+system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
+system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.itb.inst_hits                            0                       # ITB inst hits
+system.cpu.itb.inst_misses                          0                       # ITB inst misses
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
+system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.itb.hits                                 0                       # DTB hits
+system.cpu.itb.misses                               0                       # DTB misses
+system.cpu.itb.accesses                             0                       # DTB accesses
+system.cpu.workload.num_syscalls                  442                       # Number of system calls
+system.cpu.numCycles                        122288823                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.committedInsts                    90602849                       # Number of instructions committed
+system.cpu.committedOps                      91054080                       # Number of ops (including micro ops) committed
+system.cpu.discardedOps                       2027782                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
+system.cpu.cpi                               1.349724                       # CPI: cycles per instruction
+system.cpu.ipc                               0.740892                       # IPC: instructions per cycle
+system.cpu.tickCycles                       109176310                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                        13112513                       # Total number of cycles that the object has spent stopped
+system.cpu.icache.tags.replacements                 5                       # number of replacements
+system.cpu.icache.tags.tagsinuse           690.927528                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            27773576                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs               803                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          34587.267746                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   690.927528                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.337367                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.337367                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          798                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           42                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2           15                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4          741                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.389648                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses          55549561                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         55549561                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     27773576                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        27773576                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      27773576                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         27773576                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     27773576                       # number of overall hits
+system.cpu.icache.overall_hits::total        27773576                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          803                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           803                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          803                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            803                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          803                       # number of overall misses
+system.cpu.icache.overall_misses::total           803                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     55308998                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     55308998                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     55308998                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     55308998                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     55308998                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     55308998                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     27774379                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     27774379                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     27774379                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     27774379                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     27774379                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     27774379                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000029                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000029                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000029                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000029                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000029                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000029                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68877.955168                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 68877.955168                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 68877.955168                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 68877.955168                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 68877.955168                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 68877.955168                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          803                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          803                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          803                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          803                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          803                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total          803                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     53368002                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     53368002                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     53368002                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     53368002                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     53368002                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     53368002                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000029                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000029                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000029                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.000029                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000029                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.000029                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66460.774595                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66460.774595                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66460.774595                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 66460.774595                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66460.774595                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 66460.774595                       # average overall mshr miss latency
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.toL2Bus.throughput              1982677223                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq         904183                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp        904183                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback       943269                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq        46761                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp        46761                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1606                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2843551                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           2845157                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        51392                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    121178240                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total      121229632                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus         121229632                       # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy     1890375500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          3.1                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy       1371998                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy    1428578994                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization          2.3                       # Layer utilization (%)
+system.cpu.l2cache.tags.replacements                0                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        10264.635484                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            1831263                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs            15557                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs           117.713119                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks  9373.658869                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   890.976615                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.286061                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.027190                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.313252                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        15557                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           45                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1           14                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          526                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         1094                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        13878                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.474762                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         15216022                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        15216022                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.inst       903145                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total         903145                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks       943269                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total       943269                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.inst        32217                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total        32217                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst       935362                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total          935362                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst       935362                       # number of overall hits
+system.cpu.l2cache.overall_hits::total         935362                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst         1038                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total         1038                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.inst        14544                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total        14544                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst        15582                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total         15582                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst        15582                       # number of overall misses
+system.cpu.l2cache.overall_misses::total        15582                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     71727250                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total     71727250                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst    959621000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total    959621000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst   1031348250                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total   1031348250                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst   1031348250                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total   1031348250                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst       904183                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total       904183                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks       943269                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total       943269                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.inst        46761                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total        46761                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst       950944                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total       950944                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst       950944                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total       950944                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.001148                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.001148                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst     0.311028                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.311028                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.016386                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.016386                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.016386                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.016386                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69101.396917                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 69101.396917                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 65980.541804                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65980.541804                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66188.438583                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 66188.438583                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66188.438583                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 66188.438583                       # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
+system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            8                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total            8                       # number of ReadReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst            8                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total            8                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst            8                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total            8                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         1030                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total         1030                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst        14544                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total        14544                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst        15574                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total        15574                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst        15574                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total        15574                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     58365000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total     58365000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst    772683000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    772683000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    831048000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    831048000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    831048000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    831048000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.001139                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.001139                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst     0.311028                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.311028                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.016377                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.016377                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.016377                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.016377                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56665.048544                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56665.048544                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 53127.268977                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 53127.268977                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53361.243097                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53361.243097                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53361.243097                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53361.243097                       # average overall mshr miss latency
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu.dcache.tags.replacements            946045                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          3618.157159                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            26265609                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            950141                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             27.643907                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle       20427116250                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.inst  3618.157159                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.inst     0.883339                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.883339                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          261                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1         2250                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2         1585                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses          55458945                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         55458945                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.inst     21596750                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        21596750                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.inst      4661085                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        4661085                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.inst         3887                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total         3887                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.inst         3887                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total         3887                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.inst      26257835                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         26257835                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.inst     26257835                       # number of overall hits
+system.cpu.dcache.overall_hits::total        26257835                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.inst       914897                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        914897                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.inst        73896                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total        73896                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.inst       988793                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total         988793                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.inst       988793                       # number of overall misses
+system.cpu.dcache.overall_misses::total        988793                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.inst  11909486494                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  11909486494                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.inst   2342585500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   2342585500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.inst  14252071994                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  14252071994                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.inst  14252071994                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  14252071994                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.inst     22511647                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     22511647                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.inst      4734981                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total      4734981                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.inst         3887                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total         3887                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.inst         3887                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total         3887                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.inst     27246628                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     27246628                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.inst     27246628                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     27246628                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.inst     0.040641                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.040641                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.inst     0.015606                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.015606                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.inst     0.036290                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.036290                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.inst     0.036290                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.036290                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 13017.297569                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 13017.297569                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 31701.113727                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 31701.113727                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.inst 14413.605268                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 14413.605268                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.inst 14413.605268                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 14413.605268                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks       943269                       # number of writebacks
+system.cpu.dcache.writebacks::total            943269                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.inst        11517                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total        11517                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.inst        27135                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total        27135                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.inst        38652                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total        38652                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.inst        38652                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total        38652                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.inst       903380                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       903380                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.inst        46761                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total        46761                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.inst       950141                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       950141                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.inst       950141                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       950141                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst   9958325256                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   9958325256                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst   1334905750                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   1334905750                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.inst  11293231006                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  11293231006                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.inst  11293231006                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  11293231006                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst     0.040129                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.040129                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst     0.009876                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.009876                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.inst     0.034872                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.034872                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.inst     0.034872                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.034872                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 11023.406823                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11023.406823                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 28547.416651                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28547.416651                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 11885.847475                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 11885.847475                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 11885.847475                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 11885.847475                       # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
index b6a9feb5d..dd39737d4 100644
--- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
@@ -1,61 +1,61 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.026894                       # Number of seconds simulated
-sim_ticks                                 26894328500                       # Number of ticks simulated
-final_tick                                26894328500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.026367                       # Number of seconds simulated
+sim_ticks                                 26367385000                       # Number of ticks simulated
+final_tick                                26367385000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 165934                       # Simulator instruction rate (inst/s)
-host_op_rate                                   167125                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               49262466                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 394132                       # Number of bytes of host memory used
-host_seconds                                   545.94                       # Real time elapsed on the host
+host_inst_rate                                 125019                       # Simulator instruction rate (inst/s)
+host_op_rate                                   125641                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               36388385                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 387112                       # Number of bytes of host memory used
+host_seconds                                   724.61                       # Real time elapsed on the host
 sim_insts                                    90589798                       # Number of instructions simulated
-sim_ops                                      91240351                       # Number of ops (including micro ops) simulated
+sim_ops                                      91041029                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst             45184                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data            947456                       # Number of bytes read from this memory
-system.physmem.bytes_read::total               992640                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        45184                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           45184                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst                706                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data              14804                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                 15510                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst              1680057                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             35228840                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                36908897                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         1680057                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            1680057                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             1680057                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            35228840                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               36908897                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                         15510                       # Number of read requests accepted
+system.physmem.bytes_read::cpu.inst             44608                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data            947840                       # Number of bytes read from this memory
+system.physmem.bytes_read::total               992448                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        44608                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           44608                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst                697                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data              14810                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                 15507                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst              1691787                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             35947440                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                37639227                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         1691787                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            1691787                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             1691787                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            35947440                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               37639227                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                         15507                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
-system.physmem.readBursts                       15510                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                       15507                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                   992640                       # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM                   992448                       # Total number of bytes read from DRAM
 system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
 system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                    992640                       # Total read bytes from the system interface side
+system.physmem.bytesReadSys                    992448                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
 system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs              1                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                 987                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                 885                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                 942                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                1029                       # Per bank write bursts
-system.physmem.perBankRdBursts::4                1048                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs              3                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0                 989                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                 884                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                 939                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                1031                       # Per bank write bursts
+system.physmem.perBankRdBursts::4                1047                       # Per bank write bursts
 system.physmem.perBankRdBursts::5                1105                       # Per bank write bursts
 system.physmem.perBankRdBursts::6                1078                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                1080                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                1078                       # Per bank write bursts
 system.physmem.perBankRdBursts::8                1024                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                 957                       # Per bank write bursts
-system.physmem.perBankRdBursts::10                936                       # Per bank write bursts
+system.physmem.perBankRdBursts::9                 961                       # Per bank write bursts
+system.physmem.perBankRdBursts::10                931                       # Per bank write bursts
 system.physmem.perBankRdBursts::11                899                       # Per bank write bursts
-system.physmem.perBankRdBursts::12                905                       # Per bank write bursts
-system.physmem.perBankRdBursts::13                863                       # Per bank write bursts
-system.physmem.perBankRdBursts::14                876                       # Per bank write bursts
+system.physmem.perBankRdBursts::12                906                       # Per bank write bursts
+system.physmem.perBankRdBursts::13                864                       # Per bank write bursts
+system.physmem.perBankRdBursts::14                875                       # Per bank write bursts
 system.physmem.perBankRdBursts::15                896                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
 system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
@@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                     26894128500                       # Total gap between requests
+system.physmem.totGap                     26367229500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                   15510                       # Read request sizes (log2)
+system.physmem.readPktSize::6                   15507                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -90,12 +90,12 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                     10369                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      4857                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       264                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                        13                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                      9831                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      5064                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       594                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                        12                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         4                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                         3                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                         2                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
@@ -186,74 +186,74 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples         1366                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      726.489019                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     530.637647                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     387.552146                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127            153     11.20%     11.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255          146     10.69%     21.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383           54      3.95%     25.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511           65      4.76%     30.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639           57      4.17%     34.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767           41      3.00%     37.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895           35      2.56%     40.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023           33      2.42%     42.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151          782     57.25%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total           1366                       # Bytes accessed per row activation
-system.physmem.totQLat                       88775250                       # Total ticks spent queuing
-system.physmem.totMemAccLat                 379587750                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                     77550000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        5723.74                       # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples         1349                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      734.553002                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     545.014262                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     382.702300                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127            137     10.16%     10.16% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255          142     10.53%     20.68% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383           57      4.23%     24.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511           62      4.60%     29.50% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639           68      5.04%     34.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767           37      2.74%     37.29% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895           30      2.22%     39.51% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023           28      2.08%     41.59% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151          788     58.41%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total           1349                       # Bytes accessed per row activation
+system.physmem.totQLat                       76352250                       # Total ticks spent queuing
+system.physmem.totMemAccLat                 367108500                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                     77535000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        4923.73                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  24473.74                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          36.91                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  23673.73                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          37.64                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       36.91                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       37.64                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.29                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.29                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.03                       # Average read queue length when enqueuing
+system.physmem.avgRdQLen                         1.17                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                      14143                       # Number of row buffer hits during reads
+system.physmem.readRowHits                      14147                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   91.19                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   91.23                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                      1733986.36                       # Average gap between requests
-system.physmem.pageHitRate                      91.19                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE      24303280500                       # Time in different power states
-system.physmem.memoryStateTime::REF         898040000                       # Time in different power states
+system.physmem.avgGap                      1700343.68                       # Average gap between requests
+system.physmem.pageHitRate                      91.23                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE      23819655750                       # Time in different power states
+system.physmem.memoryStateTime::REF         880360000                       # Time in different power states
 system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT        1692660750                       # Time in different power states
+system.physmem.memoryStateTime::ACT        1664500500                       # Time in different power states
 system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.membus.throughput                     36908897                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq                 972                       # Transaction distribution
-system.membus.trans_dist::ReadResp                972                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq                1                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp               1                       # Transaction distribution
+system.membus.throughput                     37639227                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq                 969                       # Transaction distribution
+system.membus.trans_dist::ReadResp                969                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq                3                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp               3                       # Transaction distribution
 system.membus.trans_dist::ReadExReq             14538                       # Transaction distribution
 system.membus.trans_dist::ReadExResp            14538                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        31022                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                  31022                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       992640                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total              992640                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus                 992640                       # Total data (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        31020                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                  31020                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       992448                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total              992448                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus                 992448                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy            18401000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy            18431500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.1                       # Layer utilization (%)
-system.membus.respLayer1.occupancy          145166999                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy          144905497                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.5                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.branchPred.lookups                27364118                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          22575249                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            843312                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             11626081                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                11546341                       # Number of BTB hits
+system.cpu.branchPred.lookups                29708806                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          24486950                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            848073                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             12459505                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                12380967                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             99.314128                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                   70079                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect                187                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             99.369654                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                   77225                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect                105                       # Number of incorrect RAS predictions.
 system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -339,515 +339,517 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  442                       # Number of system calls
-system.cpu.numCycles                         53788658                       # number of cpu cycles simulated
+system.cpu.numCycles                         52734771                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           14474692                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      130915195                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    27364118                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           11616420                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      24576695                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 5106515                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles                9886759                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                  107                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles             8                       # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles           29                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                  14156505                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                349331                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples           53187301                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.478661                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.235073                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles           15504828                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      141696019                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    29708806                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           12458192                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      36323119                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 1712998                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles                   10                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles             5                       # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles           52                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                  15157439                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                317484                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples           52684513                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.702798                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.249702                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 28648969     53.86%     53.86% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  3469200      6.52%     60.39% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  2052434      3.86%     64.25% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  1567853      2.95%     67.19% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  1679873      3.16%     70.35% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  3021837      5.68%     76.03% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  1566641      2.95%     78.98% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  1116795      2.10%     81.08% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                 10063699     18.92%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 25447326     48.30%     48.30% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  3927834      7.46%     55.76% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  2643597      5.02%     60.77% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  1975703      3.75%     64.52% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  2124397      4.03%     68.56% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  2942984      5.59%     74.14% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  1825722      3.47%     77.61% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  1288988      2.45%     80.05% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 10507962     19.95%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total             53187301                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.508734                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        2.433881                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 16310855                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles               8657573                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  23455900                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles                522552                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                4240421                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved              4543490                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                  8671                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              129206748                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                 42514                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                4240421                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 17921369                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                 2850180                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles         191379                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  22351654                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles               5632298                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              126131712                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                   134                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                1889841                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                3251328                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                 563418                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.FullRegisterEvents             3246                       # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands           146876533                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             549573070                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        512042051                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups               826                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps             107414186                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 39462347                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts               4633                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts           4631                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                   9072079                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             30275485                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores             5599467                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           2184620                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          1363504                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  120806561                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                8485                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 105954089                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued             91175                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        29372689                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     73925597                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved            267                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples      53187301                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.992094                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.919550                       # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total             52684513                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.563363                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        2.686956                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 11541183                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              18148303                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  18363246                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               3783966                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                 847815                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              4787740                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                  8797                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              133953704                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                 39951                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                 847815                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 13130783                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                 7261973                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles         198650                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  20259912                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              10985380                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              130534992                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                  3194                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                4661957                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                5208173                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents                 864876                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands           151632066                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             568616751                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        140291234                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups               824                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps             107312919                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                 44319147                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts               4700                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts           4700                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  18678634                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             31297749                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores             5707560                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           2464961                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          1558957                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  125335435                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                8504                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 107771373                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued             19311                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        34045700                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     86545264                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved            286                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples      52684513                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         2.045599                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.948200                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            15526622     29.19%     29.19% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            10753574     20.22%     49.41% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2             8641028     16.25%     65.66% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3             6157106     11.58%     77.23% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4             5949684     11.19%     88.42% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             2742880      5.16%     93.58% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             2429206      4.57%     98.14% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7              538839      1.01%     99.16% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              448362      0.84%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            15278150     29.00%     29.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            10252049     19.46%     48.46% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2             8069131     15.32%     63.77% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3             6193349     11.76%     75.53% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             6619102     12.56%     88.09% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             3132844      5.95%     94.04% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             1926333      3.66%     97.70% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7              606051      1.15%     98.85% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              607504      1.15%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total        53187301                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total        52684513                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                   44574      8.99%      8.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                     27      0.01%      8.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      8.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      8.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      8.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      8.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      8.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      8.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      8.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      8.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      8.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      8.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      8.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      8.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      8.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      8.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      8.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      8.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      8.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      8.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      8.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      8.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      8.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      8.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      8.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      8.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      8.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      8.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      8.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                 174239     35.13%     44.13% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                277108     55.87%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  313366     33.84%     33.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                     27      0.00%     33.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     33.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     33.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     33.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     33.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     33.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     33.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     33.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     33.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     33.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     33.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     33.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     33.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     33.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     33.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     33.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     33.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     33.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     33.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     33.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     33.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     33.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     33.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     33.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     33.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     33.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     33.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     33.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                 287772     31.08%     64.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                324774     35.08%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu              75094311     70.87%     70.87% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                10550      0.01%     70.88% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     70.88% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     70.88% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     70.88% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     70.88% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     70.88% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     70.88% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     70.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     70.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     70.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     70.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     70.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     70.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     70.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     70.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     70.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     70.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     70.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     70.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     70.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     70.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               1      0.00%     70.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt             140      0.00%     70.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     70.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc            196      0.00%     70.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     70.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            4      0.00%     70.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     70.88% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             25720178     24.27%     95.16% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite             5128709      4.84%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu              76600270     71.08%     71.08% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                10764      0.01%     71.09% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     71.09% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     71.09% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     71.09% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     71.09% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     71.09% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     71.09% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     71.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     71.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     71.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     71.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     71.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     71.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     71.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     71.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     71.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     71.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     71.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     71.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     71.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     71.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               1      0.00%     71.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt             144      0.00%     71.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     71.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc            193      0.00%     71.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     71.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc           20      0.00%     71.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     71.09% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             25964378     24.09%     95.18% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite             5195603      4.82%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              105954089                       # Type of FU issued
-system.cpu.iq.rate                           1.969822                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                      495948                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.004681                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          265681854                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         150192687                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    103425723                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads                 748                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes               1061                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses          319                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              106449666                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                     371                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads           469381                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              107771373                       # Type of FU issued
+system.cpu.iq.rate                           2.043649                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                      925939                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.008592                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          269171739                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         159396970                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    104914190                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads                 770                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes               1077                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses          346                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              108696926                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                     386                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads           461125                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      7701519                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses         7870                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation         6982                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores       854623                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      8821838                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses         5647                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation         8949                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores       962716                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads            2                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked         30068                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads        15326                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked        231326                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                4240421                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                  731718                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                478226                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           120827778                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            309730                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              30275485                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts              5599467                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts               4597                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                  72415                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                359917                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents           6982                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         447833                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       447193                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts               895026                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             104954211                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              25387781                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts            999878                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                 847815                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 5127616                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                500104                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           125356607                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            320162                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts              31297749                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts              5707560                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts               4616                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                  66442                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                385113                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents           8949                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         454051                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       452935                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts               906986                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             106740965                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              25734173                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           1030408                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                         12732                       # number of nop insts executed
-system.cpu.iew.exec_refs                     30458601                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 21526378                       # Number of branches executed
-system.cpu.iew.exec_stores                    5070820                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.951233                       # Inst execution rate
-system.cpu.iew.wb_sent                      103717343                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     103426042                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                  62672484                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 105780863                       # num instructions consuming a value
+system.cpu.iew.exec_nop                         12668                       # number of nop insts executed
+system.cpu.iew.exec_refs                     30844738                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 21924000                       # Number of branches executed
+system.cpu.iew.exec_stores                    5110565                       # Number of stores executed
+system.cpu.iew.exec_rate                     2.024110                       # Inst execution rate
+system.cpu.iew.wb_sent                      105227967                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     104914536                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                  63175597                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 106448562                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.922823                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.592475                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.989476                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.593485                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts        29588025                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts        34317785                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls            8218                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            834722                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples     48946880                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.864326                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.553843                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts            839389                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples     47813008                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.904370                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.590937                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     19590544     40.02%     40.02% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     13003525     26.57%     66.59% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2      4154420      8.49%     75.08% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      3492472      7.14%     82.21% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      1473630      3.01%     85.22% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5       727145      1.49%     86.71% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6       923215      1.89%     88.60% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7       261788      0.53%     89.13% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      5320141     10.87%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     19048029     39.84%     39.84% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     12579538     26.31%     66.15% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      4065916      8.50%     74.65% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      3224325      6.74%     81.40% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      1531590      3.20%     84.60% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5       701376      1.47%     86.07% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      1004304      2.10%     88.17% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       253211      0.53%     88.70% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      5404719     11.30%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total     48946880                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total     47813008                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts             90602407                       # Number of instructions committed
-system.cpu.commit.committedOps               91252960                       # Number of ops (including micro ops) committed
+system.cpu.commit.committedOps               91053638                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                       27318810                       # Number of memory references committed
-system.cpu.commit.loads                      22573966                       # Number of loads committed
+system.cpu.commit.refs                       27220755                       # Number of memory references committed
+system.cpu.commit.loads                      22475911                       # Number of loads committed
 system.cpu.commit.membars                        3888                       # Number of memory barriers committed
 system.cpu.commit.branches                   18732304                       # Number of branches committed
 system.cpu.commit.fp_insts                         48                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                  72525674                       # Number of committed integer instructions.
+system.cpu.commit.int_insts                  72326352                       # Number of committed integer instructions.
 system.cpu.commit.function_calls                56148                       # Number of function calls committed.
 system.cpu.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu         63923653     70.05%     70.05% # Class of committed instruction
-system.cpu.commit.op_class_0::IntMult           10474      0.01%     70.06% # Class of committed instruction
-system.cpu.commit.op_class_0::IntDiv                0      0.00%     70.06% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatAdd              0      0.00%     70.06% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatCmp              0      0.00%     70.06% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatCvt              0      0.00%     70.06% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMult             0      0.00%     70.06% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatDiv              0      0.00%     70.06% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     70.06% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAdd               0      0.00%     70.06% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     70.06% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAlu               0      0.00%     70.06% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdCmp               0      0.00%     70.06% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdCvt               0      0.00%     70.06% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMisc              0      0.00%     70.06% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMult              0      0.00%     70.06% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     70.06% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdShift             0      0.00%     70.06% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     70.06% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     70.06% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     70.06% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     70.06% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     70.06% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatCvt            6      0.00%     70.06% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     70.06% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMisc           15      0.00%     70.06% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     70.06% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMultAcc            2      0.00%     70.06% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     70.06% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead        22573966     24.74%     94.80% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite        4744844      5.20%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu         63822386     70.09%     70.09% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult           10474      0.01%     70.10% # Class of committed instruction
+system.cpu.commit.op_class_0::IntDiv                0      0.00%     70.10% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatAdd              0      0.00%     70.10% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCmp              0      0.00%     70.10% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCvt              0      0.00%     70.10% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatMult             0      0.00%     70.10% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatDiv              0      0.00%     70.10% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     70.10% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAdd               0      0.00%     70.10% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     70.10% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAlu               0      0.00%     70.10% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCmp               0      0.00%     70.10% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCvt               0      0.00%     70.10% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMisc              0      0.00%     70.10% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMult              0      0.00%     70.10% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     70.10% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShift             0      0.00%     70.10% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     70.10% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     70.10% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     70.10% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     70.10% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     70.10% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCvt            6      0.00%     70.10% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     70.10% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMisc           15      0.00%     70.10% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     70.10% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMultAcc            2      0.00%     70.10% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     70.10% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead        22475911     24.68%     94.79% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite        4744844      5.21%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total          91252960                       # Class of committed instruction
-system.cpu.commit.bw_lim_events               5320141                       # number cycles where commit BW limit reached
+system.cpu.commit.op_class_0::total          91053638                       # Class of committed instruction
+system.cpu.commit.bw_lim_events               5404719                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                    164461990                       # The number of ROB reads
-system.cpu.rob.rob_writes                   245943119                       # The number of ROB writes
-system.cpu.timesIdled                           58216                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                          601357                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads                    167773978                       # The number of ROB reads
+system.cpu.rob.rob_writes                   255639290                       # The number of ROB writes
+system.cpu.timesIdled                             522                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           50258                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                    90589798                       # Number of Instructions Simulated
-system.cpu.committedOps                      91240351                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               0.593761                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.593761                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.684180                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.684180                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                499033245                       # number of integer regfile reads
-system.cpu.int_regfile_writes               121427335                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                       166                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                      402                       # number of floating regfile writes
-system.cpu.misc_regfile_reads                29301616                       # number of misc regfile reads
+system.cpu.committedOps                      91041029                       # Number of Ops (including micro ops) Simulated
+system.cpu.cpi                               0.582127                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.582127                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.717838                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.717838                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                115515398                       # number of integer regfile reads
+system.cpu.int_regfile_writes                62074294                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                       287                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                      460                       # number of floating regfile writes
+system.cpu.cc_regfile_reads                 391234324                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                 61185455                       # number of cc regfile writes
+system.cpu.misc_regfile_reads                29410043                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                   7784                       # number of misc regfile writes
-system.cpu.toL2Bus.throughput              4500548582                       # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq         907410                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp        907410                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback       942895                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq            1                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp            1                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq        40933                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp        40933                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1463                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2838119                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           2839582                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        46784                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    120992384                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total      121039168                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus         121039168                       # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus           64                       # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy     1888514500                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          7.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy       1215999                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.throughput              4590653188                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq         911002                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp        911001                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback       942911                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq            5                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp            5                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq        37393                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp        37393                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1448                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2838257                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           2839705                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        46144                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    120997056                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total      121043200                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus         121043200                       # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus          320                       # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy     1888566500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          7.2                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy       1205249                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    1424171240                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          5.3                       # Layer utilization (%)
-system.cpu.icache.tags.replacements                 3                       # number of replacements
-system.cpu.icache.tags.tagsinuse           631.006365                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            14155509                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs               731                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          19364.581395                       # Average number of references to valid blocks.
+system.cpu.toL2Bus.respLayer1.occupancy    1424155994                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization          5.4                       # Layer utilization (%)
+system.cpu.icache.tags.replacements                 2                       # number of replacements
+system.cpu.icache.tags.tagsinuse           624.324849                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            15156433                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs               721                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          21021.404993                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   631.006365                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.308109                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.308109                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024          728                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_blocks::cpu.inst   624.324849                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.304846                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.304846                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          719                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           36                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2           13                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2           11                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::3            6                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4          673                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.355469                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          28313740                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         28313740                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     14155509                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        14155509                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      14155509                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         14155509                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     14155509                       # number of overall hits
-system.cpu.icache.overall_hits::total        14155509                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst          995                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total           995                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst          995                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total            995                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst          995                       # number of overall misses
-system.cpu.icache.overall_misses::total           995                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     67178998                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     67178998                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     67178998                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     67178998                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     67178998                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     67178998                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     14156504                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     14156504                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     14156504                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     14156504                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     14156504                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     14156504                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000070                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000070                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000070                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000070                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000070                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000070                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67516.580905                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 67516.580905                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 67516.580905                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 67516.580905                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 67516.580905                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 67516.580905                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs          593                       # number of cycles access was blocked
+system.cpu.icache.tags.age_task_id_blocks_1024::4          666                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.351074                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses          30315604                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         30315604                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     15156433                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        15156433                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      15156433                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         15156433                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     15156433                       # number of overall hits
+system.cpu.icache.overall_hits::total        15156433                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         1006                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          1006                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         1006                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           1006                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         1006                       # number of overall misses
+system.cpu.icache.overall_misses::total          1006                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     68127998                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     68127998                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     68127998                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     68127998                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     68127998                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     68127998                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     15157439                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     15157439                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     15157439                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     15157439                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     15157439                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     15157439                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000066                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000066                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000066                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000066                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000066                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000066                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67721.667992                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 67721.667992                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 67721.667992                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 67721.667992                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 67721.667992                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 67721.667992                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs          475                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                10                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                11                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    59.300000                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    43.181818                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst          263                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total          263                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst          263                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total          263                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst          263                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total          263                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst          732                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total          732                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst          732                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total          732                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst          732                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total          732                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     50814250                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     50814250                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     50814250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     50814250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     50814250                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     50814250                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000052                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000052                       # mshr miss rate for ReadReq accesses
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-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000052                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.000052                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69418.374317                       # average ReadReq mshr miss latency
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-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69418.374317                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 69418.374317                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69418.374317                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 69418.374317                       # average overall mshr miss latency
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+system.cpu.icache.overall_avg_mshr_miss_latency::total 69398.211829                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        10751.524012                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            1834202                       # Total number of references to valid blocks.
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-system.cpu.l2cache.tags.avg_refs           118.381438                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.tagsinuse        10760.665120                       # Cycle average of tags in use
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 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks  9904.575959                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   617.996997                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   228.951056                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.302264                       # Average percentage of cache occupancy
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+system.cpu.l2cache.ReadReq_avg_miss_latency::total 71342.441267                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 66528.477095                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66528.477095                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70896.489971                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 66640.765234                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 66832.200168                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70896.489971                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 66640.765234                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 66832.200168                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -857,199 +859,215 @@ system.cpu.l2cache.avg_blocked_cycles::no_targets          nan
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            1                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           10                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total           11                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.data            9                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total           10                       # number of ReadReq MSHR hits
 system.cpu.l2cache.demand_mshr_hits::cpu.inst            1                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data           10                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total           11                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data            9                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total           10                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.overall_mshr_hits::cpu.inst            1                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data           10                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total           11                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          706                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          266                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total          972                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data            1                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total            1                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.overall_mshr_hits::cpu.data            9                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total           10                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          697                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          272                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total          969                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data            3                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total            3                       # number of UpgradeReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        14538                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total        14538                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst          706                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data        14804                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total        15510                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst          706                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data        14804                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total        15510                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     40933250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     17118000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     58051250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data        10001                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total        10001                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    795610750                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    795610750                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     40933250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    812728750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    853662000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     40933250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    812728750                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    853662000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.965800                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.000293                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.001071                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.355166                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.355166                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.965800                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.015622                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.016355                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.965800                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.015622                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.016355                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57979.107649                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64353.383459                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59723.508230                       # average ReadReq mshr miss latency
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          697                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data        14810                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total        15507                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          697                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data        14810                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total        15507                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     40695500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     16451000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total     57146500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data        30003                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total        30003                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    785057000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    785057000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     40695500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    801508000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    842203500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     40695500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    801508000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    842203500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.965374                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.000299                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.001064                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.600000                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.600000                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.388789                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.388789                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.965374                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.015628                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.016351                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.965374                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.015628                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.016351                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58386.657102                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60481.617647                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58974.716202                       # average ReadReq mshr miss latency
 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        10001                       # average UpgradeReq mshr miss latency
 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        10001                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54726.286284                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54726.286284                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57979.107649                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 54899.267090                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55039.458414                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57979.107649                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 54899.267090                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55039.458414                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54000.343926                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54000.343926                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58386.657102                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 54119.378798                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54311.182047                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58386.657102                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 54119.378798                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54311.182047                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements            943515                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          3673.207831                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            28229578                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs            947611                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             29.790260                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle        7976079250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  3673.207831                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.896779                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.896779                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements            943572                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          3673.474741                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            28380480                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            947668                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             29.947703                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle        7812548250                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  3673.474741                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.896844                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.896844                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          452                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1         3133                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2          511                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          478                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1         3177                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          441                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          60126081                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         60126081                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     23676805                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        23676805                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      4544974                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        4544974                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data         3910                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total         3910                       # number of LoadLockedReq hits
+system.cpu.dcache.tags.tag_accesses          60432712                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         60432712                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     23814120                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        23814120                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      4557910                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        4557910                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data          634                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total           634                       # number of SoftPFReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data         3911                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total         3911                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data         3887                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total         3887                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      28221779                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         28221779                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     28221779                       # number of overall hits
-system.cpu.dcache.overall_hits::total        28221779                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      1169644                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       1169644                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       190007                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       190007                       # number of WriteReq misses
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+system.cpu.dcache.demand_hits::total         28372030                       # number of demand (read+write) hits
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+system.cpu.dcache.WriteReq_misses::total       177071                       # number of WriteReq misses
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+system.cpu.dcache.SoftPFReq_misses::total           33                       # number of SoftPFReq misses
 system.cpu.dcache.LoadLockedReq_misses::cpu.data            8                       # number of LoadLockedReq misses
 system.cpu.dcache.LoadLockedReq_misses::total            8                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data      1359651                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        1359651                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      1359651                       # number of overall misses
-system.cpu.dcache.overall_misses::total       1359651                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  13867675477                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  13867675477                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   8610605390                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   8610605390                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       264500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total       264500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  22478280867                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  22478280867                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  22478280867                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  22478280867                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     24846449                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     24846449                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data      1362019                       # number of demand (read+write) misses
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+system.cpu.dcache.overall_misses::total       1362052                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  14093002232                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  14093002232                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   8425812922                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   8425812922                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       265500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total       265500                       # number of LoadLockedReq miss cycles
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+system.cpu.dcache.demand_miss_latency::total  22518815154                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  22518815154                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  22518815154                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     24999068                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     24999068                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data      4734981                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total      4734981                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data         3918                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total         3918                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data          667                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total          667                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data         3919                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total         3919                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data         3887                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total         3887                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     29581430                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     29581430                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     29581430                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     29581430                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.047075                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.047075                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.040128                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.040128                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.002042                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.002042                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.045963                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.045963                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.045963                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.045963                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11856.321647                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 11856.321647                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45317.306152                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 45317.306152                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 33062.500000                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 33062.500000                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 16532.390199                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 16532.390199                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 16532.390199                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 16532.390199                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs       136970                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs             24472                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     5.597009                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.demand_accesses::cpu.data     29734049                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     29734049                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     29734716                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     29734716                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.047400                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.047400                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.037396                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.037396                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.049475                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.049475                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.002041                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.002041                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.045807                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.045807                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.045807                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.045807                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11893.350790                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 11893.350790                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47584.375318                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 47584.375318                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 33187.500000                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 33187.500000                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 16533.407503                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 16533.407503                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 16533.006929                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 16533.006929                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs       231027                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets           25                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs             44986                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               1                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     5.135531                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets           25                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       942895                       # number of writebacks
-system.cpu.dcache.writebacks::total            942895                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       262958                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       262958                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       149081                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       149081                       # number of WriteReq MSHR hits
+system.cpu.dcache.writebacks::writebacks       942911                       # number of writebacks
+system.cpu.dcache.writebacks::total            942911                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       274687                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       274687                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       139679                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       139679                       # number of WriteReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            8                       # number of LoadLockedReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::total            8                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data       412039                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       412039                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data       412039                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       412039                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       906686                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       906686                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data        40926                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total        40926                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       947612                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       947612                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       947612                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       947612                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  10019308761                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  10019308761                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   1304642257                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   1304642257                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  11323951018                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  11323951018                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  11323951018                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  11323951018                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.036492                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.036492                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.008643                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.008643                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.032034                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.032034                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.032034                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.032034                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11050.472557                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11050.472557                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31878.078898                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31878.078898                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11949.986933                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 11949.986933                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11949.986933                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 11949.986933                       # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_hits::cpu.data       414366                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       414366                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data       414366                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       414366                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       910261                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       910261                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data        37392                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total        37392                       # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data           20                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total           20                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       947653                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       947653                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       947673                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       947673                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  10074295509                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  10074295509                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   1254962842                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   1254962842                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data      1219250                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total      1219250                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  11329258351                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  11329258351                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  11330477601                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  11330477601                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.036412                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.036412                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.007897                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.007897                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.029985                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.029985                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.031871                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.031871                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.031871                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.031871                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11067.480106                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11067.480106                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33562.335312                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33562.335312                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 60962.500000                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 60962.500000                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11955.070422                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 11955.070422                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11956.104691                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 11956.104691                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt
index 53bbc79f1..b4b101032 100644
--- a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt
@@ -1,16 +1,16 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.054241                       # Number of seconds simulated
-sim_ticks                                 54240661000                       # Number of ticks simulated
-final_tick                                54240661000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.054141                       # Number of seconds simulated
+sim_ticks                                 54141000000                       # Number of ticks simulated
+final_tick                                54141000000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1753346                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1765935                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1049669772                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 433744                       # Number of bytes of host memory used
-host_seconds                                    51.67                       # Real time elapsed on the host
+host_inst_rate                                1737374                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1746027                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1038196846                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 439336                       # Number of bytes of host memory used
+host_seconds                                    52.15                       # Real time elapsed on the host
 sim_insts                                    90602407                       # Number of instructions simulated
-sim_ops                                      91252960                       # Number of ops (including micro ops) simulated
+sim_ops                                      91053638                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst         431323080                       # Number of bytes read from this memory
@@ -21,21 +21,21 @@ system.physmem.bytes_inst_read::total       431323080                       # Nu
 system.physmem.bytes_written::cpu.data       18908138                       # Number of bytes written to this memory
 system.physmem.bytes_written::total          18908138                       # Number of bytes written to this memory
 system.physmem.num_reads::cpu.inst          107830770                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data           22553294                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total             130384064                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data           22461532                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total             130292302                       # Number of read requests responded to by this memory
 system.physmem.num_writes::cpu.data           4738868                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total              4738868                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst           7952024773                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data           1659577821                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              9611602595                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst      7952024773                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total         7952024773                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data           348597116                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total              348597116                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst          7952024773                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data          2008174937                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             9960199711                       # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput                   9960199711                       # Throughput (bytes/s)
+system.physmem.bw_read::cpu.inst           7966662603                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data           1662632718                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              9629295321                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst      7966662603                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total         7966662603                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data           349238802                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total              349238802                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst          7966662603                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data          2011871521                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             9978534124                       # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput                   9978534124                       # Throughput (bytes/s)
 system.membus.data_through_bus              540247816                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
@@ -124,63 +124,65 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  442                       # Number of system calls
-system.cpu.numCycles                        108481323                       # number of cpu cycles simulated
+system.cpu.numCycles                        108282001                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                    90602407                       # Number of instructions committed
-system.cpu.committedOps                      91252960                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses              72525674                       # Number of integer alu accesses
+system.cpu.committedOps                      91053638                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses              72326352                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                     48                       # Number of float alu accesses
 system.cpu.num_func_calls                      112245                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts     15549034                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                     72525674                       # number of integer instructions
+system.cpu.num_conditional_control_insts     15520157                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                     72326352                       # number of integer instructions
 system.cpu.num_fp_insts                            48                       # number of float instructions
-system.cpu.num_int_register_reads           396967282                       # number of times the integer registers were read
-system.cpu.num_int_register_writes          106840357                       # number of times the integer registers were written
+system.cpu.num_int_register_reads           124257699                       # number of times the integer registers were read
+system.cpu.num_int_register_writes           52782988                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                   54                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                  30                       # number of times the floating registers were written
-system.cpu.num_mem_refs                      27318810                       # number of memory refs
-system.cpu.num_load_insts                    22573966                       # Number of load instructions
+system.cpu.num_cc_register_reads            271814240                       # number of times the CC registers were read
+system.cpu.num_cc_register_writes            53956115                       # number of times the CC registers were written
+system.cpu.num_mem_refs                      27220755                       # number of memory refs
+system.cpu.num_load_insts                    22475911                       # Number of load instructions
 system.cpu.num_store_insts                    4744844                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                  108481323                       # Number of busy cycles
+system.cpu.num_busy_cycles                  108282001                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                          18732304                       # Number of branches fetched
 system.cpu.op_class::No_OpClass                     0      0.00%      0.00% # Class of executed instruction
-system.cpu.op_class::IntAlu                  63924095     70.05%     70.05% # Class of executed instruction
-system.cpu.op_class::IntMult                    10474      0.01%     70.06% # Class of executed instruction
-system.cpu.op_class::IntDiv                         0      0.00%     70.06% # Class of executed instruction
-system.cpu.op_class::FloatAdd                       0      0.00%     70.06% # Class of executed instruction
-system.cpu.op_class::FloatCmp                       0      0.00%     70.06% # Class of executed instruction
-system.cpu.op_class::FloatCvt                       0      0.00%     70.06% # Class of executed instruction
-system.cpu.op_class::FloatMult                      0      0.00%     70.06% # Class of executed instruction
-system.cpu.op_class::FloatDiv                       0      0.00%     70.06% # Class of executed instruction
-system.cpu.op_class::FloatSqrt                      0      0.00%     70.06% # Class of executed instruction
-system.cpu.op_class::SimdAdd                        0      0.00%     70.06% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc                     0      0.00%     70.06% # Class of executed instruction
-system.cpu.op_class::SimdAlu                        0      0.00%     70.06% # Class of executed instruction
-system.cpu.op_class::SimdCmp                        0      0.00%     70.06% # Class of executed instruction
-system.cpu.op_class::SimdCvt                        0      0.00%     70.06% # Class of executed instruction
-system.cpu.op_class::SimdMisc                       0      0.00%     70.06% # Class of executed instruction
-system.cpu.op_class::SimdMult                       0      0.00%     70.06% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc                    0      0.00%     70.06% # Class of executed instruction
-system.cpu.op_class::SimdShift                      0      0.00%     70.06% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc                   0      0.00%     70.06% # Class of executed instruction
-system.cpu.op_class::SimdSqrt                       0      0.00%     70.06% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd                   0      0.00%     70.06% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu                   0      0.00%     70.06% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp                   0      0.00%     70.06% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt                   6      0.00%     70.06% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv                   0      0.00%     70.06% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc                 15      0.00%     70.06% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult                  0      0.00%     70.06% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc               2      0.00%     70.06% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt                  0      0.00%     70.06% # Class of executed instruction
-system.cpu.op_class::MemRead                 22573966     24.74%     94.80% # Class of executed instruction
-system.cpu.op_class::MemWrite                 4744844      5.20%    100.00% # Class of executed instruction
+system.cpu.op_class::IntAlu                  63822828     70.09%     70.09% # Class of executed instruction
+system.cpu.op_class::IntMult                    10474      0.01%     70.10% # Class of executed instruction
+system.cpu.op_class::IntDiv                         0      0.00%     70.10% # Class of executed instruction
+system.cpu.op_class::FloatAdd                       0      0.00%     70.10% # Class of executed instruction
+system.cpu.op_class::FloatCmp                       0      0.00%     70.10% # Class of executed instruction
+system.cpu.op_class::FloatCvt                       0      0.00%     70.10% # Class of executed instruction
+system.cpu.op_class::FloatMult                      0      0.00%     70.10% # Class of executed instruction
+system.cpu.op_class::FloatDiv                       0      0.00%     70.10% # Class of executed instruction
+system.cpu.op_class::FloatSqrt                      0      0.00%     70.10% # Class of executed instruction
+system.cpu.op_class::SimdAdd                        0      0.00%     70.10% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc                     0      0.00%     70.10% # Class of executed instruction
+system.cpu.op_class::SimdAlu                        0      0.00%     70.10% # Class of executed instruction
+system.cpu.op_class::SimdCmp                        0      0.00%     70.10% # Class of executed instruction
+system.cpu.op_class::SimdCvt                        0      0.00%     70.10% # Class of executed instruction
+system.cpu.op_class::SimdMisc                       0      0.00%     70.10% # Class of executed instruction
+system.cpu.op_class::SimdMult                       0      0.00%     70.10% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc                    0      0.00%     70.10% # Class of executed instruction
+system.cpu.op_class::SimdShift                      0      0.00%     70.10% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc                   0      0.00%     70.10% # Class of executed instruction
+system.cpu.op_class::SimdSqrt                       0      0.00%     70.10% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd                   0      0.00%     70.10% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu                   0      0.00%     70.10% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp                   0      0.00%     70.10% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt                   6      0.00%     70.10% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv                   0      0.00%     70.10% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc                 15      0.00%     70.10% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult                  0      0.00%     70.10% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc               2      0.00%     70.10% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt                  0      0.00%     70.10% # Class of executed instruction
+system.cpu.op_class::MemRead                 22475911     24.68%     94.79% # Class of executed instruction
+system.cpu.op_class::MemWrite                 4744844      5.21%    100.00% # Class of executed instruction
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::total                   91253402                       # Class of executed instruction
+system.cpu.op_class::total                   91054080                       # Class of executed instruction
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt
index a84dd1567..1dc1749e2 100644
--- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt
@@ -1,16 +1,16 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.147136                       # Number of seconds simulated
-sim_ticks                                147135976000                       # Number of ticks simulated
-final_tick                               147135976000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.147041                       # Number of seconds simulated
+sim_ticks                                147041218000                       # Number of ticks simulated
+final_tick                               147041218000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 805246                       # Simulator instruction rate (inst/s)
-host_op_rate                                   811020                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1308067541                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 443480                       # Number of bytes of host memory used
-host_seconds                                   112.48                       # Real time elapsed on the host
+host_inst_rate                                1067718                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1073024                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1733318334                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 449084                       # Number of bytes of host memory used
+host_seconds                                    84.83                       # Real time elapsed on the host
 sim_insts                                    90576861                       # Number of instructions simulated
-sim_ops                                      91226312                       # Number of ops (including micro ops) simulated
+sim_ops                                      91026990                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst             36992                       # Number of bytes read from this memory
@@ -21,15 +21,15 @@ system.physmem.bytes_inst_read::total           36992                       # Nu
 system.physmem.num_reads::cpu.inst                578                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data              14762                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                 15340                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst               251414                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              6421054                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 6672467                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          251414                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             251414                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              251414                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             6421054                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                6672467                       # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput                      6672467                       # Throughput (bytes/s)
+system.physmem.bw_read::cpu.inst               251576                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              6425192                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 6676767                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          251576                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             251576                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              251576                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             6425192                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                6676767                       # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput                      6676767                       # Throughput (bytes/s)
 system.membus.trans_dist::ReadReq                 792                       # Transaction distribution
 system.membus.trans_dist::ReadResp                792                       # Transaction distribution
 system.membus.trans_dist::ReadExReq             14548                       # Transaction distribution
@@ -40,9 +40,9 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port
 system.membus.tot_pkt_size::total              981760                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.data_through_bus                 981760                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy            15340000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy            15603000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy          138060000                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy          138323000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
@@ -130,77 +130,79 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  442                       # Number of system calls
-system.cpu.numCycles                        294271952                       # number of cpu cycles simulated
+system.cpu.numCycles                        294082436                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                    90576861                       # Number of instructions committed
-system.cpu.committedOps                      91226312                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses              72525674                       # Number of integer alu accesses
+system.cpu.committedOps                      91026990                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses              72326352                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                     48                       # Number of float alu accesses
 system.cpu.num_func_calls                      112245                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts     15549034                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                     72525674                       # number of integer instructions
+system.cpu.num_conditional_control_insts     15520157                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                     72326352                       # number of integer instructions
 system.cpu.num_fp_insts                            48                       # number of float instructions
-system.cpu.num_int_register_reads           464618159                       # number of times the integer registers were read
-system.cpu.num_int_register_writes          106840357                       # number of times the integer registers were written
+system.cpu.num_int_register_reads           124237033                       # number of times the integer registers were read
+system.cpu.num_int_register_writes           52782988                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                   54                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                  30                       # number of times the floating registers were written
-system.cpu.num_mem_refs                      27318810                       # number of memory refs
-system.cpu.num_load_insts                    22573966                       # Number of load instructions
+system.cpu.num_cc_register_reads            339191618                       # number of times the CC registers were read
+system.cpu.num_cc_register_writes            53956115                       # number of times the CC registers were written
+system.cpu.num_mem_refs                      27220755                       # number of memory refs
+system.cpu.num_load_insts                    22475911                       # Number of load instructions
 system.cpu.num_store_insts                    4744844                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                  294271952                       # Number of busy cycles
+system.cpu.num_busy_cycles                  294082436                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                          18732304                       # Number of branches fetched
 system.cpu.op_class::No_OpClass                     0      0.00%      0.00% # Class of executed instruction
-system.cpu.op_class::IntAlu                  63924095     70.05%     70.05% # Class of executed instruction
-system.cpu.op_class::IntMult                    10474      0.01%     70.06% # Class of executed instruction
-system.cpu.op_class::IntDiv                         0      0.00%     70.06% # Class of executed instruction
-system.cpu.op_class::FloatAdd                       0      0.00%     70.06% # Class of executed instruction
-system.cpu.op_class::FloatCmp                       0      0.00%     70.06% # Class of executed instruction
-system.cpu.op_class::FloatCvt                       0      0.00%     70.06% # Class of executed instruction
-system.cpu.op_class::FloatMult                      0      0.00%     70.06% # Class of executed instruction
-system.cpu.op_class::FloatDiv                       0      0.00%     70.06% # Class of executed instruction
-system.cpu.op_class::FloatSqrt                      0      0.00%     70.06% # Class of executed instruction
-system.cpu.op_class::SimdAdd                        0      0.00%     70.06% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc                     0      0.00%     70.06% # Class of executed instruction
-system.cpu.op_class::SimdAlu                        0      0.00%     70.06% # Class of executed instruction
-system.cpu.op_class::SimdCmp                        0      0.00%     70.06% # Class of executed instruction
-system.cpu.op_class::SimdCvt                        0      0.00%     70.06% # Class of executed instruction
-system.cpu.op_class::SimdMisc                       0      0.00%     70.06% # Class of executed instruction
-system.cpu.op_class::SimdMult                       0      0.00%     70.06% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc                    0      0.00%     70.06% # Class of executed instruction
-system.cpu.op_class::SimdShift                      0      0.00%     70.06% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc                   0      0.00%     70.06% # Class of executed instruction
-system.cpu.op_class::SimdSqrt                       0      0.00%     70.06% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd                   0      0.00%     70.06% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu                   0      0.00%     70.06% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp                   0      0.00%     70.06% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt                   6      0.00%     70.06% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv                   0      0.00%     70.06% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc                 15      0.00%     70.06% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult                  0      0.00%     70.06% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc               2      0.00%     70.06% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt                  0      0.00%     70.06% # Class of executed instruction
-system.cpu.op_class::MemRead                 22573966     24.74%     94.80% # Class of executed instruction
-system.cpu.op_class::MemWrite                 4744844      5.20%    100.00% # Class of executed instruction
+system.cpu.op_class::IntAlu                  63822828     70.09%     70.09% # Class of executed instruction
+system.cpu.op_class::IntMult                    10474      0.01%     70.10% # Class of executed instruction
+system.cpu.op_class::IntDiv                         0      0.00%     70.10% # Class of executed instruction
+system.cpu.op_class::FloatAdd                       0      0.00%     70.10% # Class of executed instruction
+system.cpu.op_class::FloatCmp                       0      0.00%     70.10% # Class of executed instruction
+system.cpu.op_class::FloatCvt                       0      0.00%     70.10% # Class of executed instruction
+system.cpu.op_class::FloatMult                      0      0.00%     70.10% # Class of executed instruction
+system.cpu.op_class::FloatDiv                       0      0.00%     70.10% # Class of executed instruction
+system.cpu.op_class::FloatSqrt                      0      0.00%     70.10% # Class of executed instruction
+system.cpu.op_class::SimdAdd                        0      0.00%     70.10% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc                     0      0.00%     70.10% # Class of executed instruction
+system.cpu.op_class::SimdAlu                        0      0.00%     70.10% # Class of executed instruction
+system.cpu.op_class::SimdCmp                        0      0.00%     70.10% # Class of executed instruction
+system.cpu.op_class::SimdCvt                        0      0.00%     70.10% # Class of executed instruction
+system.cpu.op_class::SimdMisc                       0      0.00%     70.10% # Class of executed instruction
+system.cpu.op_class::SimdMult                       0      0.00%     70.10% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc                    0      0.00%     70.10% # Class of executed instruction
+system.cpu.op_class::SimdShift                      0      0.00%     70.10% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc                   0      0.00%     70.10% # Class of executed instruction
+system.cpu.op_class::SimdSqrt                       0      0.00%     70.10% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd                   0      0.00%     70.10% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu                   0      0.00%     70.10% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp                   0      0.00%     70.10% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt                   6      0.00%     70.10% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv                   0      0.00%     70.10% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc                 15      0.00%     70.10% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult                  0      0.00%     70.10% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc               2      0.00%     70.10% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt                  0      0.00%     70.10% # Class of executed instruction
+system.cpu.op_class::MemRead                 22475911     24.68%     94.79% # Class of executed instruction
+system.cpu.op_class::MemWrite                 4744844      5.21%    100.00% # Class of executed instruction
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::total                   91253402                       # Class of executed instruction
+system.cpu.op_class::total                   91054080                       # Class of executed instruction
 system.cpu.icache.tags.replacements                 2                       # number of replacements
-system.cpu.icache.tags.tagsinuse           510.071144                       # Cycle average of tags in use
+system.cpu.icache.tags.tagsinuse           510.120575                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs           107830172                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs               599                       # Sample count of references to valid blocks.
 system.cpu.icache.tags.avg_refs          180016.981636                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   510.071144                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.249058                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.249058                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst   510.120575                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.249082                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.249082                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          597                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           35                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2            1                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3            9                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2            6                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3            4                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::4          552                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.291504                       # Percentage of cache occupancy per task id
 system.cpu.icache.tags.tag_accesses         215662141                       # Number of tag accesses
@@ -217,12 +219,12 @@ system.cpu.icache.demand_misses::cpu.inst          599                       # n
 system.cpu.icache.demand_misses::total            599                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst          599                       # number of overall misses
 system.cpu.icache.overall_misses::total           599                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     32063000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     32063000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     32063000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     32063000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     32063000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     32063000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     32073500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     32073500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     32073500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     32073500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     32073500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     32073500                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst    107830771                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total    107830771                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst    107830771                       # number of demand (read+write) accesses
@@ -235,12 +237,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.000006
 system.cpu.icache.demand_miss_rate::total     0.000006                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000006                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000006                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53527.545910                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 53527.545910                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 53527.545910                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 53527.545910                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 53527.545910                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 53527.545910                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53545.075125                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 53545.075125                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 53545.075125                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 53545.075125                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 53545.075125                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 53545.075125                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -255,43 +257,43 @@ system.cpu.icache.demand_mshr_misses::cpu.inst          599
 system.cpu.icache.demand_mshr_misses::total          599                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          599                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          599                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     30865000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     30865000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     30865000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     30865000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     30865000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     30865000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     30875500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     30875500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     30875500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     30875500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     30875500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     30875500                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000006                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000006                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000006                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000006                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000006                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000006                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51527.545910                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51527.545910                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51527.545910                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 51527.545910                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51527.545910                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 51527.545910                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51545.075125                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51545.075125                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51545.075125                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 51545.075125                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51545.075125                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 51545.075125                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse         9565.271881                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse         9567.852615                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs            1827177                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs            15323                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs           119.244078                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks  8876.925013                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   495.124137                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   193.222731                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.270902                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.015110                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::writebacks  8879.446533                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   495.172981                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data   193.233101                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.270979                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.015111                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.005897                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.291909                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.291988                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024        15323                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0           42                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::1            4                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2           95                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         1478                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          105                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         1468                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::4        13704                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.467621                       # Percentage of cache occupancy per task id
 system.cpu.l2cache.tags.tag_accesses         15179780                       # Number of tag accesses
@@ -320,17 +322,17 @@ system.cpu.l2cache.demand_misses::total         15340                       # nu
 system.cpu.l2cache.overall_misses::cpu.inst          578                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data        14762                       # number of overall misses
 system.cpu.l2cache.overall_misses::total        15340                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     30056000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data     11128000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total     41184000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    756496000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total    756496000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     30056000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data    767624000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total    797680000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     30056000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data    767624000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total    797680000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     30066500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data     11130000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total     41196500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    756746500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total    756746500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     30066500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data    767876500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total    797943000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     30066500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data    767876500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    797943000                       # number of overall miss cycles
 system.cpu.l2cache.ReadReq_accesses::cpu.inst          599                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::cpu.data       900189                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::total       900788                       # number of ReadReq accesses(hits+misses)
@@ -355,17 +357,17 @@ system.cpu.l2cache.demand_miss_rate::total     0.016192                       #
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.964942                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.015591                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.016192                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst        52000                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data        52000                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total        52000                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        52000                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total        52000                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data        52000                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total        52000                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data        52000                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total        52000                       # average overall miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52018.166090                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52009.345794                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 52015.782828                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52017.218862                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52017.218862                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52018.166090                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52017.104728                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 52017.144720                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52018.166090                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52017.104728                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 52017.144720                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -420,78 +422,86 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40000
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total        40000                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.dcache.tags.replacements            942702                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          3565.217259                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            26345364                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse          3565.593965                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            26253601                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs            946798                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             27.825750                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle       54472394000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  3565.217259                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.870414                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.870414                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.avg_refs             27.728830                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle       54410413000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  3565.593965                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.870506                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.870506                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          128                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1         1322                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2         2583                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3           63                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          135                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1         1355                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2         2550                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3           56                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          55531122                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         55531122                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     21649218                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        21649218                       # number of ReadReq hits
+system.cpu.dcache.tags.tag_accesses          55347598                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         55347598                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     21556948                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        21556948                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data      4688372                       # number of WriteReq hits
 system.cpu.dcache.WriteReq_hits::total        4688372                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data          507                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total           507                       # number of SoftPFReq hits
 system.cpu.dcache.LoadLockedReq_hits::cpu.data         3887                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total         3887                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data         3887                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total         3887                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      26337590                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         26337590                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     26337590                       # number of overall hits
-system.cpu.dcache.overall_hits::total        26337590                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       900189                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        900189                       # number of ReadReq misses
+system.cpu.dcache.demand_hits::cpu.data      26245320                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         26245320                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     26245827                       # number of overall hits
+system.cpu.dcache.overall_hits::total        26245827                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       900187                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        900187                       # number of ReadReq misses
 system.cpu.dcache.WriteReq_misses::cpu.data        46609                       # number of WriteReq misses
 system.cpu.dcache.WriteReq_misses::total        46609                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data       946798                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total         946798                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data       946798                       # number of overall misses
-system.cpu.dcache.overall_misses::total        946798                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  11711445000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  11711445000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   1216933000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   1216933000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  12928378000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  12928378000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  12928378000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  12928378000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     22549407                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     22549407                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_misses::cpu.data            3                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total            3                       # number of SoftPFReq misses
+system.cpu.dcache.demand_misses::cpu.data       946796                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total         946796                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data       946799                       # number of overall misses
+system.cpu.dcache.overall_misses::total        946799                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  11711364000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  11711364000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   1217183500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   1217183500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  12928547500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  12928547500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  12928547500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  12928547500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     22457135                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     22457135                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data      4734981                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total      4734981                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data          510                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total          510                       # number of SoftPFReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::cpu.data         3887                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::total         3887                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data         3887                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total         3887                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     27284388                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     27284388                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     27284388                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     27284388                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.039921                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.039921                       # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data     27192116                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     27192116                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     27192626                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     27192626                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.040085                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.040085                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.009844                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_miss_rate::total     0.009844                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.034701                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.034701                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.034701                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.034701                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13009.984570                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 13009.984570                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26109.399472                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 26109.399472                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 13654.842955                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 13654.842955                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 13654.842955                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 13654.842955                       # average overall miss latency
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.005882                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.005882                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.034819                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.034819                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.034818                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.034818                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13009.923494                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 13009.923494                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26114.773971                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 26114.773971                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 13655.050824                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 13655.050824                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 13655.007557                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 13655.007557                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -502,40 +512,54 @@ system.cpu.dcache.fast_writes                       0                       # nu
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks       942334                       # number of writebacks
 system.cpu.dcache.writebacks::total            942334                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       900189                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       900189                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data            1                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total            1                       # number of ReadReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data            1                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total            1                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data            1                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total            1                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       900186                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       900186                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data        46609                       # number of WriteReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::total        46609                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       946798                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       946798                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data            3                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total            3                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       946795                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       946795                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data       946798                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total       946798                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   9911067000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   9911067000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   1123715000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   1123715000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  11034782000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  11034782000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  11034782000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  11034782000                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.039921                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.039921                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   9910952000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   9910952000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   1123965500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   1123965500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data       117000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total       117000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  11034917500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  11034917500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  11035034500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  11035034500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.040085                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.040085                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.009844                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.009844                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.034701                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.034701                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.034701                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.034701                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11009.984570                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11009.984570                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24109.399472                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24109.399472                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11654.842955                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 11654.842955                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11654.842955                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 11654.842955                       # average overall mshr miss latency
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.005882                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.005882                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.034819                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.034819                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.034818                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.034818                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11009.893511                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11009.893511                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24114.773971                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24114.773971                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data        39000                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total        39000                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11655.022999                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 11655.022999                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11655.109643                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 11655.109643                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.throughput               821979690                       # Throughput (bytes/s)
+system.cpu.toL2Bus.throughput               822509400                       # Throughput (bytes/s)
 system.cpu.toL2Bus.trans_dist::ReadReq         900788                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadResp        900788                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::Writeback       942334                       # Transaction distribution
diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
index 7987e137b..517ef5a2d 100644
--- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
@@ -1,74 +1,74 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.064361                       # Number of seconds simulated
-sim_ticks                                 64361067000                       # Number of ticks simulated
-final_tick                                64361067000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.061857                       # Number of seconds simulated
+sim_ticks                                 61857343500                       # Number of ticks simulated
+final_tick                                61857343500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 110006                       # Simulator instruction rate (inst/s)
-host_op_rate                                   193702                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               44813910                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 383472                       # Number of bytes of host memory used
-host_seconds                                  1436.19                       # Real time elapsed on the host
+host_inst_rate                                  85967                       # Simulator instruction rate (inst/s)
+host_op_rate                                   151374                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               33658728                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 393056                       # Number of bytes of host memory used
+host_seconds                                  1837.78                       # Real time elapsed on the host
 sim_insts                                   157988547                       # Number of instructions simulated
 sim_ops                                     278192464                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst             64000                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           1883008                       # Number of bytes read from this memory
-system.physmem.bytes_read::total              1947008                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        64000                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           64000                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks        10944                       # Number of bytes written to this memory
-system.physmem.bytes_written::total             10944                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               1000                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data              29422                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                 30422                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks             171                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total                  171                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               994390                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             29256942                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                30251332                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          994390                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             994390                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks            170041                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                 170041                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks            170041                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              994390                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            29256942                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               30421373                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                         30424                       # Number of read requests accepted
-system.physmem.writeReqs                          171                       # Number of write requests accepted
-system.physmem.readBursts                       30424                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                        171                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                  1942272                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      4864                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                      9152                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                   1947136                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                  10944                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                       76                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytes_read::cpu.inst             64640                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           1884928                       # Number of bytes read from this memory
+system.physmem.bytes_read::total              1949568                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        64640                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           64640                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks        12608                       # Number of bytes written to this memory
+system.physmem.bytes_written::total             12608                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               1010                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data              29452                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                 30462                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks             197                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                  197                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst              1044985                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             30472178                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                31517163                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         1044985                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            1044985                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks            203824                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                 203824                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks            203824                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             1044985                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            30472178                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               31720987                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                         30463                       # Number of read requests accepted
+system.physmem.writeReqs                          197                       # Number of write requests accepted
+system.physmem.readBursts                       30463                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                        197                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                  1943744                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      5888                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                     11328                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                   1949632                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                  12608                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                       92                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                1923                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                2059                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                2030                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                1927                       # Per bank write bursts
-system.physmem.perBankRdBursts::4                2025                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                1901                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                1962                       # Per bank write bursts
+system.physmem.perBankRdBursts::0                1927                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                2067                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                2027                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                1932                       # Per bank write bursts
+system.physmem.perBankRdBursts::4                2026                       # Per bank write bursts
+system.physmem.perBankRdBursts::5                1903                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                1964                       # Per bank write bursts
 system.physmem.perBankRdBursts::7                1863                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                1938                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                1933                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                1937                       # Per bank write bursts
+system.physmem.perBankRdBursts::9                1937                       # Per bank write bursts
 system.physmem.perBankRdBursts::10               1804                       # Per bank write bursts
 system.physmem.perBankRdBursts::11               1796                       # Per bank write bursts
 system.physmem.perBankRdBursts::12               1792                       # Per bank write bursts
 system.physmem.perBankRdBursts::13               1800                       # Per bank write bursts
-system.physmem.perBankRdBursts::14               1817                       # Per bank write bursts
+system.physmem.perBankRdBursts::14               1818                       # Per bank write bursts
 system.physmem.perBankRdBursts::15               1778                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                   9                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                  79                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                   8                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                  14                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                   6                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                  15                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                  94                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                  13                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                  21                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                   7                       # Per bank write bursts
 system.physmem.perBankWrBursts::5                   7                       # Per bank write bursts
 system.physmem.perBankWrBursts::6                  12                       # Per bank write bursts
 system.physmem.perBankWrBursts::7                   0                       # Per bank write bursts
@@ -82,27 +82,27 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                     64361050000                       # Total gap between requests
+system.physmem.totGap                     61857329000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                   30424                       # Read request sizes (log2)
+system.physmem.readPktSize::6                   30463                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                    171                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                     29879                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       374                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        75                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                        16                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                         3                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                    197                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                     29883                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       383                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        80                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                        20                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                         5                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
@@ -144,24 +144,24 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                        8                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                        8                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                        9                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                        9                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                        9                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                        9                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                        9                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                        9                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                        9                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                        9                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                        9                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                        9                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                        9                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                        9                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                        8                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                        8                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                        8                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                        8                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                        9                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                        9                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                       11                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                       11                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                       11                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                       10                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                       10                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                       10                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                       10                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                       10                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                       10                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                       10                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                       10                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                       11                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                       10                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                       10                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                       10                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                       10                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
@@ -193,322 +193,322 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples         2692                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      724.017831                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     522.534866                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     387.414799                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127            354     13.15%     13.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255          226      8.40%     21.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383          117      4.35%     25.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511          114      4.23%     30.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639          102      3.79%     33.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767           97      3.60%     37.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895          103      3.83%     41.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023           99      3.68%     45.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         1480     54.98%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total           2692                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples             8                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean      3785.250000                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::gmean       36.090663                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev    10663.878800                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023              7     87.50%     87.50% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::29696-30719            1     12.50%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total               8                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples             8                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        17.875000                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       17.857209                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        0.834523                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16                  1     12.50%     12.50% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18                  6     75.00%     87.50% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19                  1     12.50%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total               8                       # Writes before turning the bus around for reads
-system.physmem.totQLat                      124712250                       # Total ticks spent queuing
-system.physmem.totMemAccLat                 693737250                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    151740000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        4109.41                       # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples         2724                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      716.922173                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     515.538805                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     389.679049                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127            350     12.85%     12.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255          254      9.32%     22.17% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383          128      4.70%     26.87% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511          108      3.96%     30.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639          103      3.78%     34.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767          103      3.78%     38.40% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          111      4.07%     42.47% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023           70      2.57%     45.04% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         1497     54.96%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total           2724                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples            10                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean      3031.200000                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::gmean       22.218074                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev     9548.252985                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023              9     90.00%     90.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::29696-30719            1     10.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total              10                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples            10                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.700000                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       17.676249                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        0.948683                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16                  2     20.00%     20.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18                  7     70.00%     90.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19                  1     10.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total              10                       # Writes before turning the bus around for reads
+system.physmem.totQLat                      130872750                       # Total ticks spent queuing
+system.physmem.totMemAccLat                 700329000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    151855000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        4309.14                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  22859.41                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          30.18                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           0.14                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       30.25                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        0.17                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  23059.14                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          31.42                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           0.18                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       31.52                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        0.20                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           0.24                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       0.24                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                           0.25                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       0.25                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.01                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        19.95                       # Average write queue length when enqueuing
-system.physmem.readRowHits                      27697                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                        92                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   91.26                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  53.80                       # Row buffer hit rate for writes
-system.physmem.avgGap                      2103646.02                       # Average gap between requests
-system.physmem.pageHitRate                      91.05                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE      58016949500                       # Time in different power states
-system.physmem.memoryStateTime::REF        2148900000                       # Time in different power states
+system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        12.62                       # Average write queue length when enqueuing
+system.physmem.readRowHits                      27696                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                       119                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   91.19                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  60.41                       # Row buffer hit rate for writes
+system.physmem.avgGap                      2017525.41                       # Average gap between requests
+system.physmem.pageHitRate                      90.99                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE      55617527500                       # Time in different power states
+system.physmem.memoryStateTime::REF        2065440000                       # Time in different power states
 system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT        4191773500                       # Time in different power states
+system.physmem.memoryStateTime::ACT        4171276250                       # Time in different power states
 system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.membus.throughput                     30420378                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq                1422                       # Transaction distribution
-system.membus.trans_dist::ReadResp               1419                       # Transaction distribution
-system.membus.trans_dist::Writeback               171                       # Transaction distribution
-system.membus.trans_dist::ReadExReq             29002                       # Transaction distribution
-system.membus.trans_dist::ReadExResp            29002                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        61016                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total        61016                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                  61016                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port      1957888                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total      1957888                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total             1957888                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus                1957888                       # Total data (bytes)
+system.membus.throughput                     31718918                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq                1465                       # Transaction distribution
+system.membus.trans_dist::ReadResp               1462                       # Transaction distribution
+system.membus.trans_dist::Writeback               197                       # Transaction distribution
+system.membus.trans_dist::ReadExReq             28998                       # Transaction distribution
+system.membus.trans_dist::ReadExResp            28998                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        61120                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total        61120                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                  61120                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port      1962048                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total      1962048                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total             1962048                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus                1962048                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy            35504500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy            43500000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.1                       # Layer utilization (%)
-system.membus.respLayer1.occupancy          284722250                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              0.4                       # Layer utilization (%)
+system.membus.respLayer1.occupancy          291787250                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization              0.5                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.branchPred.lookups                34798086                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          34798086                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            784118                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             19722572                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                19623609                       # Number of BTB hits
+system.cpu.branchPred.lookups                37414357                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          37414357                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            797165                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             21409472                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                21302649                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             99.498225                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 5229209                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect               5537                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             99.501048                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 5521067                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect               5418                       # Number of incorrect RAS predictions.
 system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
 system.cpu.workload.num_syscalls                  444                       # Number of system calls
-system.cpu.numCycles                        128722137                       # number of cpu cycles simulated
+system.cpu.numCycles                        123714688                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           26886538                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      188337970                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    34798086                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           24852818                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      57142929                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 6497811                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles               38531317                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                   56                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles           400                       # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles            1                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                  26333180                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                202728                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          128229739                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.583672                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.351921                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles           28240184                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      201519425                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    37414357                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           26823716                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      94568947                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 1664994                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles                  796                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles         13919                       # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles           14                       # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles           16                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                  27849620                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                205824                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          123656373                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.872113                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.370891                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 73621715     57.41%     57.41% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  2024375      1.58%     58.99% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  3018246      2.35%     61.35% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  3935135      3.07%     64.42% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  7973611      6.22%     70.63% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  4963159      3.87%     74.50% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  2723923      2.12%     76.63% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  1373007      1.07%     77.70% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                 28596568     22.30%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 62738354     50.74%     50.74% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  3652838      2.95%     53.69% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  3508504      2.84%     56.53% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  5967471      4.83%     61.35% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  7654257      6.19%     67.54% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  5436238      4.40%     71.94% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  3366087      2.72%     74.66% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  2072932      1.68%     76.34% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 29259692     23.66%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            128229739                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.270335                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.463136                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 33273315                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              35123523                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  52275495                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               1888908                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                5668498                       # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts              328717141                       # Number of instructions handled by decode
-system.cpu.rename.SquashCycles                5668498                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 37218540                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                 3059312                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles          10022                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  50252159                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              32021208                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              323526783                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                  1441                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                 292036                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents               27143978                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                4136186                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands           325451198                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             859036392                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        529005653                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups               495                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total            123656373                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.302425                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.628905                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 13285380                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              63221157                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  36527318                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               9790021                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                 832497                       # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts              334996459                       # Number of instructions handled by decode
+system.cpu.rename.SquashCycles                 832497                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 18592313                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                 8932600                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles          16230                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  40801194                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              54481539                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              328650401                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                  2309                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                 768646                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents               48119118                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents                4597217                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands           330628900                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             873052183                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        537682976                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups               692                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps             279212747                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 46238451                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts                482                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts            480                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  38827180                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            104278858                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            35723148                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads          46025226                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          6660051                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  319586854                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                1670                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 304359156                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            192192                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        40795282                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     60346573                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved           1225                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     128229739                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         2.373546                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.813536                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                 51416153                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts                475                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts            476                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  66201491                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            106325920                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            36528653                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          49813174                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          8481864                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  325481116                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                2295                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 307976733                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued             54133                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        46686820                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     68916320                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved           1850                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     123656373                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         2.490585                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        2.124426                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            28989242     22.61%     22.61% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            17448953     13.61%     36.21% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            19181395     14.96%     51.17% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            24360940     19.00%     70.17% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            22567411     17.60%     87.77% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5            10236760      7.98%     95.75% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             4240558      3.31%     99.06% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7             1068039      0.83%     99.89% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              136441      0.11%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            30107103     24.35%     24.35% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            19550071     15.81%     40.16% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            16727631     13.53%     53.68% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            17064547     13.80%     67.48% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            16031842     12.96%     80.45% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            12684149     10.26%     90.71% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             5762402      4.66%     95.37% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             4173790      3.38%     98.74% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8             1554838      1.26%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       128229739                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       123656373                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                   85597      3.62%      3.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%      3.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      3.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      3.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      3.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      3.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      3.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      3.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      3.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      3.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      3.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      3.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      3.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      3.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      3.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      3.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      3.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      3.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      3.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      3.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      3.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      3.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      3.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      3.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      3.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      3.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      3.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      3.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      3.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                2173481     92.00%     95.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                103394      4.38%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  316998      7.53%      7.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      7.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      7.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      7.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      7.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      7.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      7.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      7.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      7.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      7.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      7.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      7.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      7.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      7.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      7.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      7.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      7.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      7.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      7.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      7.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      7.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      7.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      7.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      7.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      7.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      7.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      7.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      7.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      7.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                3711822     88.14%     95.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                182351      4.33%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass             33339      0.01%      0.01% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             172841480     56.79%     56.80% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                11196      0.00%     56.80% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                   333      0.00%     56.80% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                  41      0.00%     56.80% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     56.80% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     56.80% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     56.80% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     56.80% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     56.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     56.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     56.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     56.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     56.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     56.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     56.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     56.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     56.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     56.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     56.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     56.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     56.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     56.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     56.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     56.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     56.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     56.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     56.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     56.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     56.80% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             97881417     32.16%     88.96% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            33591350     11.04%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass             33338      0.01%      0.01% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             175394846     56.95%     56.96% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                11227      0.00%     56.97% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                   339      0.00%     56.97% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                  53      0.00%     56.97% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     56.97% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     56.97% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     56.97% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     56.97% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     56.97% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     56.97% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     56.97% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     56.97% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     56.97% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     56.97% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     56.97% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     56.97% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     56.97% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     56.97% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     56.97% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     56.97% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     56.97% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     56.97% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     56.97% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     56.97% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     56.97% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     56.97% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     56.97% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     56.97% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     56.97% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             98503391     31.98%     88.95% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            34033539     11.05%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              304359156                       # Type of FU issued
-system.cpu.iq.rate                           2.364466                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     2362472                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.007762                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          739502310                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         360419132                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    302118974                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads                 405                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes                682                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses          144                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              306688087                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                     202                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads         56122672                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              307976733                       # Type of FU issued
+system.cpu.iq.rate                           2.489411                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     4211171                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.013674                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          743874544                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         372209729                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    305990656                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads                 599                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes               1009                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses          208                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              312154273                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                     293                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads         58255906                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads     13499473                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        33923                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        36991                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      4283396                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads     15546535                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        56855                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        41794                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      5088901                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads         3583                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked         18172                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads         3643                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked        105171                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                5668498                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                   78601                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles               2898580                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           319588524                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts             72060                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             104278858                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             35723148                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts                467                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                   4947                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents               2697345                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          36991                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         397417                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       436010                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts               833427                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             302993807                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              97430054                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           1365349                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                 832497                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 5705091                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles               3134574                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           325483411                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            125197                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             106325920                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             36528653                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts                468                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                   2776                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents               3138754                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          41794                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         401755                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       445201                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts               846956                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             306897357                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              98135370                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           1079376                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                             0                       # number of nop insts executed
-system.cpu.iew.exec_refs                    130824453                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 31189297                       # Number of branches executed
-system.cpu.iew.exec_stores                   33394399                       # Number of stores executed
-system.cpu.iew.exec_rate                     2.353859                       # Inst execution rate
-system.cpu.iew.wb_sent                      302554101                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     302119118                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 223057856                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 305896063                       # num instructions consuming a value
+system.cpu.iew.exec_refs                    131959976                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 31536734                       # Number of branches executed
+system.cpu.iew.exec_stores                   33824606                       # Number of stores executed
+system.cpu.iew.exec_rate                     2.480687                       # Inst execution rate
+system.cpu.iew.wb_sent                      306320115                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     305990864                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 231632885                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 336126878                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       2.347064                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.729195                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       2.473359                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.689123                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts        41496946                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts        47392313                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls             445                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            784165                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    122561241                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     2.269824                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     3.033262                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts            797958                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    117208009                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     2.373494                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     3.089570                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     56600375     46.18%     46.18% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     17466589     14.25%     60.43% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     11063696      9.03%     69.46% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      8855238      7.23%     76.68% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      1990404      1.62%     78.31% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      1890723      1.54%     79.85% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      1087341      0.89%     80.74% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7       761508      0.62%     81.36% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     22845367     18.64%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     52857681     45.10%     45.10% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     15964987     13.62%     58.72% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     10970810      9.36%     68.08% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      8748486      7.46%     75.54% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      1925592      1.64%     77.19% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      1731777      1.48%     78.66% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6       850158      0.73%     79.39% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       689946      0.59%     79.98% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     23468572     20.02%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    122561241                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    117208009                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts            157988547                       # Number of instructions committed
 system.cpu.commit.committedOps              278192464                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -554,230 +554,230 @@ system.cpu.commit.op_class_0::MemWrite       31439752     11.30%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total         278192464                       # Class of committed instruction
-system.cpu.commit.bw_lim_events              22845367                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events              23468572                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                    419405284                       # The number of ROB reads
-system.cpu.rob.rob_writes                   645053666                       # The number of ROB writes
-system.cpu.timesIdled                          104925                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                          492398                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads                    419324214                       # The number of ROB reads
+system.cpu.rob.rob_writes                   657627212                       # The number of ROB writes
+system.cpu.timesIdled                             611                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           58315                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                   157988547                       # Number of Instructions Simulated
 system.cpu.committedOps                     278192464                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               0.814756                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.814756                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.227361                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.227361                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                488589645                       # number of integer regfile reads
-system.cpu.int_regfile_writes               237913555                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                       124                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                       93                       # number of floating regfile writes
-system.cpu.cc_regfile_reads                 107415229                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                 64109444                       # number of cc regfile writes
-system.cpu.misc_regfile_reads               194048137                       # number of misc regfile reads
+system.cpu.cpi                               0.783061                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.783061                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.277040                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.277040                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                493625450                       # number of integer regfile reads
+system.cpu.int_regfile_writes               240898259                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                       178                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                      135                       # number of floating regfile writes
+system.cpu.cc_regfile_reads                 107699117                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                 64568807                       # number of cc regfile writes
+system.cpu.misc_regfile_reads               196282104                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
-system.cpu.toL2Bus.throughput              4120563135                       # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq        1995370                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       1995367                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      2066178                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq        82265                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp        82265                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         2034                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      6219411                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           6221445                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        65088                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    265138752                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total      265203840                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus         265203840                       # Total data (bytes)
+system.cpu.toL2Bus.throughput              4287758914                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq        1995493                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       1995490                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback      2066654                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq        82065                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp        82065                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         2052                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      6219715                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           6221767                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        65664                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    265163712                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total      265229376                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus         265229376                       # Total data (bytes)
 system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy     4138084500                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          6.4                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy       1694000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.occupancy     4138760000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          6.7                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy       1710750                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    3121568749                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          4.9                       # Layer utilization (%)
-system.cpu.icache.tags.replacements                56                       # number of replacements
-system.cpu.icache.tags.tagsinuse           820.274669                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            26331871                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs              1017                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          25891.711898                       # Average number of references to valid blocks.
+system.cpu.toL2Bus.respLayer1.occupancy    3121417500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization          5.0                       # Layer utilization (%)
+system.cpu.icache.tags.replacements                62                       # number of replacements
+system.cpu.icache.tags.tagsinuse           827.714171                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            27848273                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs              1026                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          27142.566277                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   820.274669                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.400525                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.400525                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024          961                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           54                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2           31                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3            7                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4          869                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.469238                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          52667377                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         52667377                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     26331871                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        26331871                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      26331871                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         26331871                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     26331871                       # number of overall hits
-system.cpu.icache.overall_hits::total        26331871                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst         1309                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total          1309                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst         1309                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total           1309                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst         1309                       # number of overall misses
-system.cpu.icache.overall_misses::total          1309                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     89709250                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     89709250                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     89709250                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     89709250                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     89709250                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     89709250                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     26333180                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     26333180                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     26333180                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     26333180                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     26333180                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     26333180                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000050                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000050                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000050                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000050                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000050                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000050                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68532.658518                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 68532.658518                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 68532.658518                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 68532.658518                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 68532.658518                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 68532.658518                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs          117                       # number of cycles access was blocked
+system.cpu.icache.tags.occ_blocks::cpu.inst   827.714171                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.404157                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.404157                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          964                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           50                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2           20                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3           20                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4          874                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.470703                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses          55700266                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         55700266                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     27848273                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        27848273                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      27848273                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         27848273                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     27848273                       # number of overall hits
+system.cpu.icache.overall_hits::total        27848273                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         1347                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          1347                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         1347                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           1347                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         1347                       # number of overall misses
+system.cpu.icache.overall_misses::total          1347                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     92883749                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     92883749                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     92883749                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     92883749                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     92883749                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     92883749                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     27849620                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     27849620                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     27849620                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     27849620                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     27849620                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     27849620                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000048                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000048                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000048                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000048                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000048                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000048                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68956.012621                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 68956.012621                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 68956.012621                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 68956.012621                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 68956.012621                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 68956.012621                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs          850                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                 3                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 6                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs           39                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs   141.666667                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst          292                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total          292                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst          292                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total          292                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst          292                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total          292                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst         1017                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total         1017                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst         1017                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total         1017                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst         1017                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total         1017                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     70297000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     70297000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     70297000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     70297000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     70297000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     70297000                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000039                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000039                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000039                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.000039                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000039                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.000039                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69121.927237                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69121.927237                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69121.927237                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 69121.927237                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69121.927237                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 69121.927237                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst          321                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total          321                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst          321                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total          321                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst          321                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total          321                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst         1026                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total         1026                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst         1026                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total         1026                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst         1026                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total         1026                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     72336999                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     72336999                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     72336999                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     72336999                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     72336999                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     72336999                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000037                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000037                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000037                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.000037                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000037                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.000037                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70503.897661                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70503.897661                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70503.897661                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 70503.897661                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70503.897661                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 70503.897661                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements              489                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        20838.141939                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            4029004                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs            30405                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs           132.511232                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements              515                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        20693.420536                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            4029533                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs            30444                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs           132.358856                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 19919.361133                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   667.825750                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   250.955056                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.607891                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.020380                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.007659                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.635930                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        29916                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           56                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_blocks::writebacks 19762.319871                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   681.987127                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data   249.113538                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.603098                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.020813                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.007602                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.631513                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        29929                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           55                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::1           66                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          769                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         1376                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        27649                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.912964                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         33263174                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        33263174                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst           17                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data      1993931                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        1993948                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks      2066178                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      2066178                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data        53263                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total        53263                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst           17                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      2047194                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         2047211                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst           17                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      2047194                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        2047211                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst         1000                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data          422                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total         1422                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data        29002                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total        29002                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         1000                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data        29424                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total         30424                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         1000                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data        29424                       # number of overall misses
-system.cpu.l2cache.overall_misses::total        30424                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     69106000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data     29389750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total     98495750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   1891412500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   1891412500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     69106000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data   1920802250                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total   1989908250                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     69106000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data   1920802250                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total   1989908250                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst         1017                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data      1994353                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total      1995370                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks      2066178                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total      2066178                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data        82265                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total        82265                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst         1017                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      2076618                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      2077635                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst         1017                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      2076618                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      2077635                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.983284                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.000212                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.000713                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.352544                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.352544                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.983284                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.014169                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.014644                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.983284                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.014169                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.014644                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst        69106                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 69643.957346                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 69265.646976                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 65216.622992                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65216.622992                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst        69106                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 65280.119970                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 65405.872009                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst        69106                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 65280.119970                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 65405.872009                       # average overall miss latency
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          784                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         1397                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        27627                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.913361                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         33266205                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        33266205                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.inst           16                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data      1994012                       # number of ReadReq hits
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+system.cpu.l2cache.Writeback_hits::writebacks      2066654                       # number of Writeback hits
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+system.cpu.l2cache.overall_hits::cpu.data      2047079                       # number of overall hits
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+system.cpu.l2cache.ReadReq_miss_latency::cpu.data     31680000                       # number of ReadReq miss cycles
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+system.cpu.l2cache.ReadExReq_miss_latency::total   1901914500                       # number of ReadExReq miss cycles
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+system.cpu.l2cache.overall_miss_latency::cpu.data   1933594500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total   2004736250                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst         1026                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data      1994467                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total      1995493                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks      2066654                       # number of Writeback accesses(hits+misses)
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+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.984405                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.000228                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.000734                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.353354                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.353354                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.984405                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.014184                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.014663                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.984405                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.014184                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.014663                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70437.376238                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 69626.373626                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 70185.494881                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 65587.781916                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65587.781916                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70437.376238                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 65650.171460                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 65808.891114                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70437.376238                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 65650.171460                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 65808.891114                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -786,167 +786,167 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks          171                       # number of writebacks
-system.cpu.l2cache.writebacks::total              171                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         1000                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          422                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total         1422                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        29002                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total        29002                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         1000                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data        29424                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total        30424                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         1000                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data        29424                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total        30424                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     56577000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     24214250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     80791250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   1526186500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   1526186500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     56577000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   1550400750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total   1606977750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     56577000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   1550400750                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total   1606977750                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.983284                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.000212                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.000713                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.352544                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.352544                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.983284                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.014169                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.014644                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.983284                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.014169                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.014644                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst        56577                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 57379.739336                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56815.225035                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 52623.491483                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52623.491483                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst        56577                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 52691.705750                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 52819.410663                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst        56577                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 52691.705750                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 52819.410663                       # average overall mshr miss latency
+system.cpu.l2cache.writebacks::writebacks          197                       # number of writebacks
+system.cpu.l2cache.writebacks::total              197                       # number of writebacks
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+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          455                       # number of ReadReq MSHR misses
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+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     26096500                       # number of ReadReq MSHR miss cycles
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+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   1530042000                       # number of ReadExReq MSHR miss cycles
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+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.984405                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.000228                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.000734                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.353354                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.353354                       # mshr miss rate for ReadExReq accesses
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+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.014184                       # mshr miss rate for overall accesses
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+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57903.712871                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 57354.945055                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57733.276451                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 52763.707842                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52763.707842                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57903.712871                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 52834.634842                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53002.699997                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57903.712871                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 52834.634842                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53002.699997                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements           2072519                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4069.536250                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            69938402                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           2076615                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             33.679041                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle       20171577250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4069.536250                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.993539                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.993539                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements           2072433                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4068.938050                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            68459744                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           2076529                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             32.968354                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle       19695463250                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4068.938050                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.993393                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.993393                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          595                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1         3363                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2          138                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          636                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1         3333                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          127                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         147464213                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        147464213                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     38592969                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        38592969                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     31345433                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       31345433                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data      69938402                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         69938402                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     69938402                       # number of overall hits
-system.cpu.dcache.overall_hits::total        69938402                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      2661078                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       2661078                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data        94319                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total        94319                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data      2755397                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        2755397                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      2755397                       # number of overall misses
-system.cpu.dcache.overall_misses::total       2755397                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  31651251499                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  31651251499                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   2775683247                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   2775683247                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  34426934746                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  34426934746                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  34426934746                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  34426934746                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     41254047                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     41254047                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.tags.tag_accesses         144502463                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        144502463                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     37113881                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        37113881                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     31345863                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       31345863                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data      68459744                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         68459744                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     68459744                       # number of overall hits
+system.cpu.dcache.overall_hits::total        68459744                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      2659334                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       2659334                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data        93889                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total        93889                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data      2753223                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        2753223                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      2753223                       # number of overall misses
+system.cpu.dcache.overall_misses::total       2753223                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  31861058000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  31861058000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   2765155744                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   2765155744                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  34626213744                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  34626213744                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  34626213744                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  34626213744                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     39773215                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     39773215                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     31439752                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     31439752                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     72693799                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     72693799                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     72693799                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     72693799                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.064505                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.064505                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.003000                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.003000                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.037904                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.037904                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.037904                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.037904                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11894.146470                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 11894.146470                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29428.675527                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 29428.675527                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 12494.364604                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 12494.364604                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 12494.364604                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 12494.364604                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs        86474                       # number of cycles access was blocked
+system.cpu.dcache.demand_accesses::cpu.data     71212967                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     71212967                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     71212967                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     71212967                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.066862                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.066862                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.002986                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.002986                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.038662                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.038662                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.038662                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.038662                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11980.841068                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 11980.841068                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29451.328100                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 29451.328100                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 12576.610665                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 12576.610665                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 12576.610665                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 12576.610665                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs       182189                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs             16255                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs             39926                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     5.319840                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     4.563167                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      2066178                       # number of writebacks
-system.cpu.dcache.writebacks::total           2066178                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       666601                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       666601                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data        12178                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total        12178                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data       678779                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       678779                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data       678779                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       678779                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1994477                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      1994477                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data        82141                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total        82141                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      2076618                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      2076618                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      2076618                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      2076618                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  21991461751                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  21991461751                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   2506217997                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   2506217997                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  24497679748                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  24497679748                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  24497679748                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  24497679748                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.048346                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.048346                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.002613                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.002613                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.028567                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.028567                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.028567                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.028567                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11026.179671                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11026.179671                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30511.169781                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30511.169781                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11796.911973                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 11796.911973                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11796.911973                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 11796.911973                       # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks      2066654                       # number of writebacks
+system.cpu.dcache.writebacks::total           2066654                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       664835                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       664835                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data        11856                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total        11856                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data       676691                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       676691                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data       676691                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       676691                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1994499                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      1994499                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data        82033                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total        82033                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      2076532                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      2076532                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      2076532                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      2076532                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  22009130500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  22009130500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   2514972494                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   2514972494                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  24524102994                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  24524102994                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  24524102994                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  24524102994                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.050147                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.050147                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.002609                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.002609                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.029159                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.029159                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.029159                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.029159                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11034.916789                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11034.916789                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30658.058269                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30658.058269                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11810.125244                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 11810.125244                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11810.125244                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 11810.125244                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt
index d97d6a9aa..8a81dcd7c 100644
--- a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt
+++ b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt
@@ -1,100 +1,100 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.409306                       # Number of seconds simulated
-sim_ticks                                409306011500                       # Number of ticks simulated
-final_tick                               409306011500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.409289                       # Number of seconds simulated
+sim_ticks                                409289296500                       # Number of ticks simulated
+final_tick                               409289296500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 215743                       # Simulator instruction rate (inst/s)
-host_op_rate                                   215743                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              144312578                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 243356                       # Number of bytes of host memory used
-host_seconds                                  2836.25                       # Real time elapsed on the host
+host_inst_rate                                 309220                       # Simulator instruction rate (inst/s)
+host_op_rate                                   309220                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              206831646                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 269756                       # Number of bytes of host memory used
+host_seconds                                  1978.85                       # Real time elapsed on the host
 sim_insts                                   611901617                       # Number of instructions simulated
 sim_ops                                     611901617                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst          24320640                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             24320640                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       170752                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          170752                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     18724096                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          18724096                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst             380010                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                380010                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          292564                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               292564                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst             59419210                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                59419210                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          417174                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             417174                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          45745959                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               45745959                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          45745959                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst            59419210                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              105165169                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        380010                       # Number of read requests accepted
-system.physmem.writeReqs                       292564                       # Number of write requests accepted
-system.physmem.readBursts                      380010                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     292564                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 24298688                       # Total number of bytes read from DRAM
+system.physmem.bytes_read::cpu.inst          24320576                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             24320576                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       171008                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          171008                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     18723776                       # Number of bytes written to this memory
+system.physmem.bytes_written::total          18723776                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst             380009                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                380009                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          292559                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               292559                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst             59421481                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                59421481                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          417817                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             417817                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          45747045                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               45747045                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          45747045                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst            59421481                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              105168526                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        380009                       # Number of read requests accepted
+system.physmem.writeReqs                       292559                       # Number of write requests accepted
+system.physmem.readBursts                      380009                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     292559                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 24298624                       # Total number of bytes read from DRAM
 system.physmem.bytesReadWrQ                     21952                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  18722368                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  24320640                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               18724096                       # Total written bytes from the system interface side
+system.physmem.bytesWritten                  18721984                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  24320576                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               18723776                       # Total written bytes from the system interface side
 system.physmem.servicedByWrQ                      343                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
 system.physmem.perBankRdBursts::0               23736                       # Per bank write bursts
 system.physmem.perBankRdBursts::1               23211                       # Per bank write bursts
 system.physmem.perBankRdBursts::2               23514                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               24536                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               24530                       # Per bank write bursts
 system.physmem.perBankRdBursts::4               25475                       # Per bank write bursts
 system.physmem.perBankRdBursts::5               23585                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               23685                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               23974                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               23182                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               23686                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               23976                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               23181                       # Per bank write bursts
 system.physmem.perBankRdBursts::9               23951                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              24679                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              22748                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              23716                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              24414                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              22802                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              22459                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              24677                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              22749                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              23715                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              24413                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              22806                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              22461                       # Per bank write bursts
 system.physmem.perBankWrBursts::0               17754                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               17435                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               17434                       # Per bank write bursts
 system.physmem.perBankWrBursts::2               17902                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               18771                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               18770                       # Per bank write bursts
 system.physmem.perBankWrBursts::4               19442                       # Per bank write bursts
 system.physmem.perBankWrBursts::5               18539                       # Per bank write bursts
 system.physmem.perBankWrBursts::6               18677                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               18571                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               18354                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               18570                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               18353                       # Per bank write bursts
 system.physmem.perBankWrBursts::9               18833                       # Per bank write bursts
 system.physmem.perBankWrBursts::10              19131                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              17964                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              18221                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              18695                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              17147                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              17963                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              18220                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              18694                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              17148                       # Per bank write bursts
 system.physmem.perBankWrBursts::15              17101                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    409305930000                       # Total gap between requests
+system.physmem.totGap                    409289215500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  380010                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  380009                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 292564                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    378272                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      1380                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 292559                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    378276                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      1375                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::2                        15                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
@@ -140,29 +140,29 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     6975                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     7537                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    16938                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    17305                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    17384                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    17418                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    17392                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                    17374                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     6993                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     7538                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                    16933                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                    17310                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                    17382                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    17417                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    17401                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    17377                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::23                    17382                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    17390                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    17383                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    17383                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                    17565                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                    17454                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    17428                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                    17567                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                    17327                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                    17272                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    17387                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    17377                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    17385                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                    17562                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                    17443                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                    17429                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                    17559                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                    17324                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                    17269                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::33                       32                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::34                       13                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::35                       10                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::36                        6                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                        3                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::38                        3                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::39                        2                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::40                        1                       # What write queue length does an incoming req see
@@ -189,37 +189,37 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       141944                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      303.070281                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     179.645979                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     325.191162                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          50836     35.81%     35.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        38595     27.19%     63.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        13069      9.21%     72.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         8075      5.69%     77.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         5863      4.13%     82.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         3755      2.65%     84.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         3005      2.12%     86.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         2490      1.75%     88.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        16256     11.45%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         141944                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         17252                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        22.005912                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      228.974837                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023          17241     99.94%     99.94% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples       141842                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      303.284612                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     179.855968                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     325.125721                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          50699     35.74%     35.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        38599     27.21%     62.96% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        13098      9.23%     72.19% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         8031      5.66%     77.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         5875      4.14%     81.99% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         3794      2.67%     84.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         3041      2.14%     86.81% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         2492      1.76%     88.57% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        16213     11.43%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         141842                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         17249                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        22.009624                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      229.029888                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023          17238     99.94%     99.94% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::1024-2047            7      0.04%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::2048-3071            3      0.02%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::28672-29695            1      0.01%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           17252                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         17252                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        16.956701                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.885973                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        2.749936                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19           17057     98.87%     98.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23             150      0.87%     99.74% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              24      0.14%     99.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31               7      0.04%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35               1      0.01%     99.92% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total           17249                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         17249                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.959302                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.888033                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        2.754923                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19           17045     98.82%     98.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23             155      0.90%     99.72% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27              27      0.16%     99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31               7      0.04%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35               2      0.01%     99.92% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::36-39               1      0.01%     99.93% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::40-43               2      0.01%     99.94% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::44-47               2      0.01%     99.95% # Writes before turning the bus around for reads
@@ -230,13 +230,13 @@ system.physmem.wrPerTurnAround::100-103             1      0.01%     99.98% # Wr
 system.physmem.wrPerTurnAround::120-123             1      0.01%     99.99% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::208-211             1      0.01%     99.99% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::216-219             1      0.01%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           17252                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     4021715750                       # Total ticks spent queuing
-system.physmem.totMemAccLat               11140472000                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   1898335000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       10592.75                       # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::total           17249                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     4014686000                       # Total ticks spent queuing
+system.physmem.totMemAccLat               11133423500                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   1898330000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       10574.26                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  29342.75                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  29324.26                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                          59.37                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                          45.74                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                       59.42                       # Average system read bandwidth in MiByte/s
@@ -246,64 +246,64 @@ system.physmem.busUtil                           0.82                       # Da
 system.physmem.busUtilRead                       0.46                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.36                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        20.32                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     314877                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    215374                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   82.94                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  73.62                       # Row buffer hit rate for writes
-system.physmem.avgGap                       608566.39                       # Average gap between requests
-system.physmem.pageHitRate                      78.88                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE     274823723500                       # Time in different power states
-system.physmem.memoryStateTime::REF       13667420000                       # Time in different power states
+system.physmem.avgWrQLen                        20.36                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     314933                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    215412                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   82.95                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  73.63                       # Row buffer hit rate for writes
+system.physmem.avgGap                       608546.97                       # Average gap between requests
+system.physmem.pageHitRate                      78.89                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE     275084055500                       # Time in different power states
+system.physmem.memoryStateTime::REF       13666900000                       # Time in different power states
 system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT      120808954500                       # Time in different power states
+system.physmem.memoryStateTime::ACT      120533549500                       # Time in different power states
 system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.membus.throughput                    105165169                       # Throughput (bytes/s)
+system.membus.throughput                    105168526                       # Throughput (bytes/s)
 system.membus.trans_dist::ReadReq              173388                       # Transaction distribution
 system.membus.trans_dist::ReadResp             173388                       # Transaction distribution
-system.membus.trans_dist::Writeback            292564                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            206622                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           206622                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1052584                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1052584                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     43044736                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total            43044736                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus               43044736                       # Total data (bytes)
+system.membus.trans_dist::Writeback            292559                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            206621                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           206621                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1052577                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                1052577                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     43044352                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total            43044352                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus               43044352                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy          3204326000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy          3204296000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.8                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         3607344750                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         3607299000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.9                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.branchPred.lookups               123709142                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          87625206                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           6390886                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             71443290                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                67227338                       # Number of BTB hits
+system.cpu.branchPred.lookups               123707695                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          87624621                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           6388553                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             71411167                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                67224113                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             94.098883                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                14930671                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect            1120494                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             94.136696                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                14930801                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect            1120545                       # Number of incorrect RAS predictions.
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                    149298589                       # DTB read hits
-system.cpu.dtb.read_misses                     537604                       # DTB read misses
+system.cpu.dtb.read_hits                    149298209                       # DTB read hits
+system.cpu.dtb.read_misses                     537277                       # DTB read misses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                149836193                       # DTB read accesses
-system.cpu.dtb.write_hits                    57313863                       # DTB write hits
-system.cpu.dtb.write_misses                     67044                       # DTB write misses
+system.cpu.dtb.read_accesses                149835486                       # DTB read accesses
+system.cpu.dtb.write_hits                    57314081                       # DTB write hits
+system.cpu.dtb.write_misses                     66749                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses                57380907                       # DTB write accesses
-system.cpu.dtb.data_hits                    206612452                       # DTB hits
-system.cpu.dtb.data_misses                     604648                       # DTB misses
+system.cpu.dtb.write_accesses                57380830                       # DTB write accesses
+system.cpu.dtb.data_hits                    206612290                       # DTB hits
+system.cpu.dtb.data_misses                     604026                       # DTB misses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                207217100                       # DTB accesses
-system.cpu.itb.fetch_hits                   225745608                       # ITB hits
+system.cpu.dtb.data_accesses                207216316                       # DTB accesses
+system.cpu.itb.fetch_hits                   225738536                       # ITB hits
 system.cpu.itb.fetch_misses                        48                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses               225745656                       # ITB accesses
+system.cpu.itb.fetch_accesses               225738584                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -317,71 +317,71 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                  485                       # Number of system calls
-system.cpu.numCycles                        818612023                       # number of cpu cycles simulated
+system.cpu.numCycles                        818578593                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                   611901617                       # Number of instructions committed
 system.cpu.committedOps                     611901617                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                      13147093                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps                      13144034                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                               1.337816                       # CPI: cycles per instruction
-system.cpu.ipc                               0.747487                       # IPC: instructions per cycle
-system.cpu.tickCycles                       736852058                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                        81759965                       # Total number of cycles that the object has spent stopped
-system.cpu.icache.tags.replacements              3162                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1116.165991                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           225740617                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs              4991                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          45229.536566                       # Average number of references to valid blocks.
+system.cpu.cpi                               1.337762                       # CPI: cycles per instruction
+system.cpu.ipc                               0.747517                       # IPC: instructions per cycle
+system.cpu.tickCycles                       736835501                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                        81743092                       # Total number of cycles that the object has spent stopped
+system.cpu.icache.tags.replacements              3168                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1116.143798                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           225733539                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs              4997                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          45173.812087                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1116.165991                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.545003                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.545003                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst  1116.143798                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.544992                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.544992                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         1829                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           75                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1           72                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           77                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           70                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::2           16                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3           77                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4         1589                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3           76                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1590                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.893066                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         451496207                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        451496207                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    225740617                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       225740617                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     225740617                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        225740617                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    225740617                       # number of overall hits
-system.cpu.icache.overall_hits::total       225740617                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst         4991                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total          4991                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst         4991                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total           4991                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst         4991                       # number of overall misses
-system.cpu.icache.overall_misses::total          4991                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    227498000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    227498000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    227498000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    227498000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    227498000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    227498000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    225745608                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    225745608                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    225745608                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    225745608                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    225745608                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    225745608                       # number of overall (read+write) accesses
+system.cpu.icache.tags.tag_accesses         451482069                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        451482069                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    225733539                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       225733539                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     225733539                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        225733539                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    225733539                       # number of overall hits
+system.cpu.icache.overall_hits::total       225733539                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         4997                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          4997                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         4997                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           4997                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         4997                       # number of overall misses
+system.cpu.icache.overall_misses::total          4997                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    227649750                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    227649750                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    227649750                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    227649750                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    227649750                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    227649750                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    225738536                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    225738536                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    225738536                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    225738536                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    225738536                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    225738536                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000022                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000022                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000022                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000022                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000022                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000022                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 45581.646965                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 45581.646965                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 45581.646965                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 45581.646965                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 45581.646965                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 45581.646965                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 45557.284371                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 45557.284371                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 45557.284371                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 45557.284371                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 45557.284371                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 45557.284371                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -390,123 +390,123 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst         4991                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total         4991                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst         4991                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total         4991                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst         4991                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total         4991                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    216413000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    216413000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    216413000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    216413000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    216413000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    216413000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst         4997                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total         4997                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst         4997                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total         4997                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst         4997                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total         4997                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    216557250                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    216557250                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    216557250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    216557250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    216557250                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    216557250                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000022                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000022                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000022                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000022                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000022                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000022                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 43360.649169                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 43360.649169                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 43360.649169                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 43360.649169                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 43360.649169                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 43360.649169                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 43337.452471                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 43337.452471                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 43337.452471                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 43337.452471                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 43337.452471                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 43337.452471                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.throughput               763750366                       # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq        1766329                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       1766329                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      2340010                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       778155                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       778155                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         9982                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      7418996                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           7428978                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       319424                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    312288192                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total      312607616                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus         312607616                       # Total data (bytes)
+system.cpu.toL2Bus.throughput               763790001                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq        1766353                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       1766353                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback      2340032                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       778163                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       778163                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         9994                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      7419070                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           7429064                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       319808                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    312291264                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total      312611072                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus         312611072                       # Total data (bytes)
 system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy     4782257000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.occupancy     4782306000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          1.2                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy       8038000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy       8044750                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    3891565250                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    3891617250                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          1.0                       # Layer utilization (%)
-system.cpu.l2cache.tags.replacements           347300                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        29490.485605                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            3710989                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           379724                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             9.772859                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements           347298                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        29490.431668                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            3711042                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           379722                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             9.773050                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle     188606170000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 21413.748537                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  8076.737069                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.653496                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.246482                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.899978                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::writebacks 21413.910714                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  8076.520954                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.653501                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.246476                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.899977                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024        32424                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          133                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1           65                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          226                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3        13172                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        18828                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          137                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1           61                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          224                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3        13170                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        18832                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.989502                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         40233831                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        40233831                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst      1592941                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        1592941                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks      2340010                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      2340010                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.inst       571533                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       571533                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst      2164474                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         2164474                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst      2164474                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        2164474                       # number of overall hits
+system.cpu.l2cache.tags.tag_accesses         40234269                       # Number of tag accesses
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+system.cpu.l2cache.ReadReq_hits::cpu.inst      1592965                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total        1592965                       # number of ReadReq hits
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+system.cpu.l2cache.Writeback_hits::total      2340032                       # number of Writeback hits
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+system.cpu.l2cache.ReadExReq_hits::total       571542                       # number of ReadExReq hits
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+system.cpu.l2cache.overall_hits::total        2164507                       # number of overall hits
 system.cpu.l2cache.ReadReq_misses::cpu.inst       173388                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_misses::total       173388                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.inst       206622                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       206622                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst       380010                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        380010                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst       380010                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       380010                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst  12655083750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total  12655083750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst  14728692500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total  14728692500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst  27383776250                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  27383776250                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst  27383776250                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  27383776250                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst      1766329                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total      1766329                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks      2340010                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total      2340010                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.inst       778155                       # number of ReadExReq accesses(hits+misses)
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-system.cpu.l2cache.demand_accesses::total      2544484                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst      2544484                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      2544484                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.098163                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.098163                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst     0.265528                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.265528                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.149347                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.149347                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.149347                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.149347                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72987.079556                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 72987.079556                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 71283.273320                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71283.273320                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72060.672745                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 72060.672745                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72060.672745                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 72060.672745                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_misses::cpu.inst       206621                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       206621                       # number of ReadExReq misses
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+system.cpu.l2cache.overall_misses::total       380009                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst  12653023000                       # number of ReadReq miss cycles
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+system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst  14723654500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total  14723654500                       # number of ReadExReq miss cycles
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+system.cpu.l2cache.overall_miss_latency::total  27376677500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst      1766353                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total      1766353                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks      2340032                       # number of Writeback accesses(hits+misses)
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+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.098162                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.098162                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst     0.265524                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.265524                       # miss rate for ReadExReq accesses
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+system.cpu.l2cache.demand_miss_rate::total     0.149344                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.149344                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.149344                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72975.194362                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 72975.194362                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 71259.235508                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71259.235508                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72042.181896                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 72042.181896                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72042.181896                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 72042.181896                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -515,106 +515,106 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks       292564                       # number of writebacks
-system.cpu.l2cache.writebacks::total           292564                       # number of writebacks
+system.cpu.l2cache.writebacks::writebacks       292559                       # number of writebacks
+system.cpu.l2cache.writebacks::total           292559                       # number of writebacks
 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst       173388                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadReq_mshr_misses::total       173388                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst       206622                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       206622                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst       380010                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       380010                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst       380010                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       380010                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst  10443247750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total  10443247750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst  12110276500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  12110276500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst  22553524250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  22553524250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst  22553524250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  22553524250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.098163                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.098163                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst     0.265528                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.265528                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.149347                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.149347                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.149347                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.149347                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60230.510474                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60230.510474                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 58610.779588                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58610.779588                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59349.817768                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59349.817768                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59349.817768                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59349.817768                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst       206621                       # number of ReadExReq MSHR misses
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+system.cpu.l2cache.ReadReq_mshr_miss_latency::total  10441221500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst  12105242000                       # number of ReadExReq MSHR miss cycles
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+system.cpu.l2cache.overall_mshr_miss_latency::total  22546463500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.098162                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.098162                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst     0.265524                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.265524                       # mshr miss rate for ReadExReq accesses
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+system.cpu.l2cache.demand_mshr_miss_rate::total     0.149344                       # mshr miss rate for demand accesses
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+system.cpu.l2cache.overall_mshr_miss_rate::total     0.149344                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60218.824255                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60218.824255                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 58586.697383                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58586.697383                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59331.393467                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59331.393467                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59331.393467                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59331.393467                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements           2535397                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4087.756934                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           202541489                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           2539493                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             79.756664                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.replacements           2535423                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4087.756597                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           202541016                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           2539519                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             79.755661                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle        1608245250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.inst  4087.756934                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.inst     0.997988                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.997988                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.inst  4087.756597                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.inst     0.997987                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.997987                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           52                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1           70                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           53                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           69                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::2          829                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::3         3145                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         414526387                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        414526387                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.inst    146875295                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       146875295                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.inst     55666194                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       55666194                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.inst     202541489                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        202541489                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.inst    202541489                       # number of overall hits
-system.cpu.dcache.overall_hits::total       202541489                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.inst      1908118                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       1908118                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.inst      1543840                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      1543840                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.inst      3451958                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        3451958                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.inst      3451958                       # number of overall misses
-system.cpu.dcache.overall_misses::total       3451958                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.inst  36372214750                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  36372214750                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.inst  45066771500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  45066771500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.inst  81438986250                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  81438986250                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.inst  81438986250                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  81438986250                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.inst    148783413                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    148783413                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.tags.tag_accesses         414525597                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        414525597                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.inst    146874833                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       146874833                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.inst     55666183                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       55666183                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.inst     202541016                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        202541016                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.inst    202541016                       # number of overall hits
+system.cpu.dcache.overall_hits::total       202541016                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.inst      1908172                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       1908172                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.inst      1543851                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      1543851                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.inst      3452023                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        3452023                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.inst      3452023                       # number of overall misses
+system.cpu.dcache.overall_misses::total       3452023                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.inst  36370896250                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  36370896250                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.inst  45057234500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  45057234500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.inst  81428130750                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  81428130750                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.inst  81428130750                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  81428130750                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.inst    148783005                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    148783005                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.inst     57210034                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     57210034                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.inst    205993447                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    205993447                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.inst    205993447                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    205993447                       # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.inst    205993039                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    205993039                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.inst    205993039                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    205993039                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.inst     0.012825                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.012825                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.inst     0.026985                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.026985                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.inst     0.026986                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.026986                       # miss rate for WriteReq accesses
 system.cpu.dcache.demand_miss_rate::cpu.inst     0.016758                       # miss rate for demand accesses
 system.cpu.dcache.demand_miss_rate::total     0.016758                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.inst     0.016758                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.016758                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 19061.826758                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 19061.826758                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 29191.348521                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 29191.348521                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.inst 23592.113881                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 23592.113881                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.inst 23592.113881                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 23592.113881                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 19060.596346                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 19060.596346                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 29184.963121                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 29184.963121                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.inst 23588.524975                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 23588.524975                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.inst 23588.524975                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 23588.524975                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -623,32 +623,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      2340010                       # number of writebacks
-system.cpu.dcache.writebacks::total           2340010                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.inst       143436                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       143436                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.inst       769029                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       769029                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.inst       912465                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       912465                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.inst       912465                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       912465                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.inst      1764682                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      1764682                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.inst       774811                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       774811                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.inst      2539493                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      2539493                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.inst      2539493                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      2539493                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst  30204720750                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  30204720750                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst  21179013000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  21179013000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.inst  51383733750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  51383733750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.inst  51383733750                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  51383733750                       # number of overall MSHR miss cycles
+system.cpu.dcache.writebacks::writebacks      2340032                       # number of writebacks
+system.cpu.dcache.writebacks::total           2340032                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.inst       143471                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       143471                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.inst       769033                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       769033                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.inst       912504                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       912504                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.inst       912504                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       912504                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.inst      1764701                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      1764701                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.inst       774818                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       774818                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.inst      2539519                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      2539519                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.inst      2539519                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      2539519                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst  30202797250                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  30202797250                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst  21174067000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  21174067000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.inst  51376864250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  51376864250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.inst  51376864250                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  51376864250                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst     0.011861                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.011861                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst     0.013543                       # mshr miss rate for WriteReq accesses
@@ -657,14 +657,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.inst     0.012328
 system.cpu.dcache.demand_mshr_miss_rate::total     0.012328                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.inst     0.012328                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.012328                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 17116.240065                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17116.240065                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 27334.424782                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27334.424782                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 20233.855242                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 20233.855242                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 20233.855242                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 20233.855242                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 17114.965793                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17114.965793                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 27327.794398                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27327.794398                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 20230.943045                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 20230.943045                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 20230.943045                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 20230.943045                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt
index 8bc6ffa49..63d0e7cc1 100644
--- a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt
+++ b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt
@@ -1,594 +1,101 @@
 
 ---------- Begin Simulation Statistics ----------
-final_tick                               377848323500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-host_inst_rate                                 209721                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 298084                       # Number of bytes of host memory used
-host_op_rate                                   236376                       # Simulator op (including micro ops) rate (op/s)
-host_seconds                                  2415.51                       # Real time elapsed on the host
-host_tick_rate                              156426000                       # Simulator tick rate (ticks/s)
+sim_seconds                                  0.361826                       # Number of seconds simulated
+sim_ticks                                361826015500                       # Number of ticks simulated
+final_tick                               361826015500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                 231274                       # Simulator instruction rate (inst/s)
+host_op_rate                                   250500                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              165186980                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 321304                       # Number of bytes of host memory used
+host_seconds                                  2190.40                       # Real time elapsed on the host
 sim_insts                                   506582155                       # Number of instructions simulated
-sim_ops                                     570968717                       # Number of ops (including micro ops) simulated
-sim_seconds                                  0.377848                       # Number of seconds simulated
-sim_ticks                                377848323500                       # Number of ticks simulated
+sim_ops                                     548695378                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             88.099044                       # BTB Hit Percentage
-system.cpu.branchPred.BTBHits                66115419                       # Number of BTB hits
-system.cpu.branchPred.BTBLookups             75046693                       # Number of BTB lookups
-system.cpu.branchPred.RASInCorrect              20332                       # Number of incorrect RAS predictions.
-system.cpu.branchPred.condIncorrect           6724593                       # Number of conditional branches incorrect
-system.cpu.branchPred.condPredicted         104577278                       # Number of conditional branches predicted
-system.cpu.branchPred.lookups               137186083                       # Number of BP lookups
-system.cpu.branchPred.usedRAS                 8950727                       # Number of times the RAS was used to get a target.
-system.cpu.committedInsts                   506582155                       # Number of instructions committed
-system.cpu.committedOps                     570968717                       # Number of ops (including micro ops) committed
-system.cpu.cpi                               1.491755                       # CPI: cycles per instruction
-system.cpu.dcache.LoadLockedReq_accesses::cpu.inst      1488541                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total      1488541                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_hits::cpu.inst      1488541                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total      1488541                       # number of LoadLockedReq hits
-system.cpu.dcache.ReadReq_accesses::cpu.inst    123498792                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    123498792                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 16388.035885                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 16388.035885                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 14278.902943                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14278.902943                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits::cpu.inst    122622654                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       122622654                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency::cpu.inst  14358180984                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  14358180984                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate::cpu.inst     0.007094                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.007094                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses::cpu.inst       876138                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        876138                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits::cpu.inst        88069                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total        88069                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst  11252760763                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  11252760763                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst     0.006381                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.006381                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses::cpu.inst       788069                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       788069                       # number of ReadReq MSHR misses
-system.cpu.dcache.StoreCondReq_accesses::cpu.inst      1488541                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total      1488541                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_hits::cpu.inst      1488541                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total      1488541                       # number of StoreCondReq hits
-system.cpu.dcache.WriteReq_accesses::cpu.inst     54239306                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total     54239306                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 29400.581233                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 29400.581233                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 28261.554772                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28261.554772                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits::cpu.inst     53538382                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       53538382                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency::cpu.inst  20607573000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  20607573000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate::cpu.inst     0.012923                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.012923                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses::cpu.inst       700924                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       700924                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits::cpu.inst       344621                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       344621                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst  10069676750                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  10069676750                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst     0.006569                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.006569                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.inst       356303                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       356303                       # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.demand_accesses::cpu.inst    177738098                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    177738098                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency::cpu.inst 22171.451715                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 22171.451715                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 18632.435531                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 18632.435531                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits::cpu.inst     176161036                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        176161036                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency::cpu.inst  34965753984                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  34965753984                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate::cpu.inst     0.008873                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.008873                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses::cpu.inst      1577062                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        1577062                       # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits::cpu.inst       432690                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       432690                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency::cpu.inst  21322437513                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  21322437513                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate::cpu.inst     0.006439                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.006439                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses::cpu.inst      1144372                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      1144372                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses::cpu.inst    177738098                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    177738098                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency::cpu.inst 22171.451715                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 22171.451715                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 18632.435531                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 18632.435531                       # average overall mshr miss latency
-system.cpu.dcache.overall_hits::cpu.inst    176161036                       # number of overall hits
-system.cpu.dcache.overall_hits::total       176161036                       # number of overall hits
-system.cpu.dcache.overall_miss_latency::cpu.inst  34965753984                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  34965753984                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate::cpu.inst     0.008873                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.008873                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses::cpu.inst      1577062                       # number of overall misses
-system.cpu.dcache.overall_misses::total       1577062                       # number of overall misses
-system.cpu.dcache.overall_mshr_hits::cpu.inst       432690                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       432690                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency::cpu.inst  21322437513                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  21322437513                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate::cpu.inst     0.006439                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.006439                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses::cpu.inst      1144372                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      1144372                       # number of overall MSHR misses
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           29                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1           18                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2          541                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3         3508                       # Occupied blocks per task id
-system.cpu.dcache.tags.avg_refs            156.538362                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.data_accesses        362574732                       # Number of data accesses
-system.cpu.dcache.tags.occ_blocks::cpu.inst  4071.496497                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.inst     0.994018                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.994018                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.replacements           1140276                       # number of replacements
-system.cpu.dcache.tags.sampled_refs           1144372                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.tag_accesses         362574732                       # Number of tag accesses
-system.cpu.dcache.tags.tagsinuse          4071.496497                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           179138118                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle        4941909250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks::writebacks      1068741                       # number of writebacks
-system.cpu.dcache.writebacks::total           1068741                       # number of writebacks
-system.cpu.discardedOps                      18127434                       # Number of ops (including micro ops) which were discarded before commit
-system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
-system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
-system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
-system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
-system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
-system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
-system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
-system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
-system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
-system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
-system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
-system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
-system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
-system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
-system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
-system.cpu.dtb.accesses                             0                       # DTB accesses
-system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.hits                                 0                       # DTB hits
-system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.inst_hits                            0                       # ITB inst hits
-system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.misses                               0                       # DTB misses
-system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
-system.cpu.dtb.read_accesses                        0                       # DTB read accesses
-system.cpu.dtb.read_hits                            0                       # DTB read hits
-system.cpu.dtb.read_misses                          0                       # DTB read misses
-system.cpu.dtb.write_accesses                       0                       # DTB write accesses
-system.cpu.dtb.write_hits                           0                       # DTB write hits
-system.cpu.dtb.write_misses                         0                       # DTB write misses
-system.cpu.icache.ReadReq_accesses::cpu.inst    204480200                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    204480200                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23608.753898                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 23608.753898                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21540.715773                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21540.715773                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits::cpu.inst    204459741                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       204459741                       # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    483011496                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    483011496                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000100                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000100                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses::cpu.inst        20459                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total         20459                       # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    440701504                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    440701504                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000100                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000100                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst        20459                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total        20459                       # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.demand_accesses::cpu.inst    204480200                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    204480200                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 23608.753898                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 23608.753898                       # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21540.715773                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 21540.715773                       # average overall mshr miss latency
-system.cpu.icache.demand_hits::cpu.inst     204459741                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        204459741                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency::cpu.inst    483011496                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    483011496                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000100                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000100                       # miss rate for demand accesses
-system.cpu.icache.demand_misses::cpu.inst        20459                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total          20459                       # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    440701504                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    440701504                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000100                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.000100                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses::cpu.inst        20459                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total        20459                       # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses::cpu.inst    204480200                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    204480200                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 23608.753898                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 23608.753898                       # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21540.715773                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 21540.715773                       # average overall mshr miss latency
-system.cpu.icache.overall_hits::cpu.inst    204459741                       # number of overall hits
-system.cpu.icache.overall_hits::total       204459741                       # number of overall hits
-system.cpu.icache.overall_miss_latency::cpu.inst    483011496                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    483011496                       # number of overall miss cycles
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000100                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000100                       # miss rate for overall accesses
-system.cpu.icache.overall_misses::cpu.inst        20459                       # number of overall misses
-system.cpu.icache.overall_misses::total         20459                       # number of overall misses
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    440701504                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    440701504                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000100                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.000100                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses::cpu.inst        20459                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total        20459                       # number of overall MSHR misses
-system.cpu.icache.tags.age_task_id_blocks_1024::0           44                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1           68                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2           55                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3          315                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4         1399                       # Occupied blocks per task id
-system.cpu.icache.tags.avg_refs           9993.633169                       # Average number of references to valid blocks.
-system.cpu.icache.tags.data_accesses        408980859                       # Number of data accesses
-system.cpu.icache.tags.occ_blocks::cpu.inst  1204.301311                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.588038                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.588038                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024         1881                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.918457                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.replacements             18578                       # number of replacements
-system.cpu.icache.tags.sampled_refs             20459                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.tag_accesses         408980859                       # Number of tag accesses
-system.cpu.icache.tags.tagsinuse          1204.301311                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           204459741                       # Total number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.idleCycles                        36857312                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.ipc                               0.670351                       # IPC: instructions per cycle
-system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
-system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
-system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
-system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
-system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
-system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
-system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
-system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
-system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
-system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
-system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
-system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
-system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
-system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
-system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
-system.cpu.itb.accesses                             0                       # DTB accesses
-system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
-system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.hits                                 0                       # DTB hits
-system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.itb.inst_hits                            0                       # ITB inst hits
-system.cpu.itb.inst_misses                          0                       # ITB inst misses
-system.cpu.itb.misses                               0                       # DTB misses
-system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
-system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
-system.cpu.itb.read_accesses                        0                       # DTB read accesses
-system.cpu.itb.read_hits                            0                       # DTB read hits
-system.cpu.itb.read_misses                          0                       # DTB read misses
-system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.write_hits                           0                       # DTB write hits
-system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.l2cache.ReadExReq_accesses::cpu.inst       356556                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       356556                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 70944.376455                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70944.376455                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 58283.052569                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58283.052569                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_hits::cpu.inst       255641                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       255641                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst   7159351750                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   7159351750                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst     0.283027                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.283027                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses::cpu.inst       100915                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       100915                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst   5881634250                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   5881634250                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst     0.283027                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.283027                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst       100915                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       100915                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses::cpu.inst       808275                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total       808275                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74397.741148                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 74397.741148                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61739.381683                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61739.381683                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits::cpu.inst       764868                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total         764868                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst   3229382750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total   3229382750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.053703                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.053703                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses::cpu.inst        43407                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total        43407                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst           15                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total           15                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst   2678995250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total   2678995250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.053685                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.053685                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        43392                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total        43392                       # number of ReadReq MSHR misses
-system.cpu.l2cache.Writeback_accesses::writebacks      1068741                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total      1068741                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits::writebacks      1068741                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      1068741                       # number of Writeback hits
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.demand_accesses::cpu.inst      1164831                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      1164831                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71983.027536                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 71983.027536                       # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59322.344030                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59322.344030                       # average overall mshr miss latency
-system.cpu.l2cache.demand_hits::cpu.inst      1020509                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         1020509                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency::cpu.inst  10388734500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  10388734500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.123900                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.123900                       # miss rate for demand accesses
-system.cpu.l2cache.demand_misses::cpu.inst       144322                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        144322                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_mshr_hits::cpu.inst           15                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total           15                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   8560629500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total   8560629500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.123887                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.123887                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst       144307                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       144307                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses::cpu.inst      1164831                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      1164831                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71983.027536                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 71983.027536                       # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59322.344030                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59322.344030                       # average overall mshr miss latency
-system.cpu.l2cache.overall_hits::cpu.inst      1020509                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        1020509                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency::cpu.inst  10388734500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  10388734500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.123900                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.123900                       # miss rate for overall accesses
-system.cpu.l2cache.overall_misses::cpu.inst       144322                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       144322                       # number of overall misses
-system.cpu.l2cache.overall_mshr_hits::cpu.inst           15                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total           15                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   8560629500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total   8560629500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.123887                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.123887                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst       144307                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       144307                       # number of overall MSHR misses
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           70                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          321                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         4944                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        25858                       # Occupied blocks per task id
-system.cpu.l2cache.tags.avg_refs            11.811039                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.data_accesses        18367876                       # Number of data accesses
-system.cpu.l2cache.tags.occ_blocks::writebacks 23534.473696                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  4154.581244                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.718215                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.126788                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.845003                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        31193                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.951935                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.replacements           111551                       # number of replacements
-system.cpu.l2cache.tags.sampled_refs           142744                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.tag_accesses         18367876                       # Number of tag accesses
-system.cpu.l2cache.tags.tagsinuse        27689.054939                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            1685955                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle     168523988500                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks::writebacks        96655                       # number of writebacks
-system.cpu.l2cache.writebacks::total            96655                       # number of writebacks
-system.cpu.numCycles                        755696647                       # number of cpu cycles simulated
-system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.tickCycles                       718839335                       # Number of cycles that the CPU actually ticked
-system.cpu.toL2Bus.data_through_bus         142948608                       # Total data (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        40918                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      3357485                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           3398403                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy     2185527000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          0.6                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy      31384496                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    1745291987                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          0.5                       # Layer utilization (%)
-system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
-system.cpu.toL2Bus.throughput               378322727                       # Throughput (bytes/s)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1309376                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    141639232                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total      142948608                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.trans_dist::ReadReq         808275                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp        808275                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      1068741                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       356556                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       356556                       # Transaction distribution
-system.cpu.workload.num_syscalls                  548                       # Number of system calls
-system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.membus.data_through_bus               15421568                       # Total data (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       385269                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 385269                       # Packet count per connected master and slave (bytes)
-system.membus.reqLayer0.occupancy          1076098500                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               0.3                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         1364495500                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              0.4                       # Layer utilization (%)
-system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.throughput                     40814176                       # Throughput (bytes/s)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     15421568                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total            15421568                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.trans_dist::ReadReq               43392                       # Transaction distribution
-system.membus.trans_dist::ReadResp              43392                       # Transaction distribution
-system.membus.trans_dist::Writeback             96655                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            100915                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           100915                       # Transaction distribution
-system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgGap                      1568082.50                       # Average gap between requests
-system.physmem.avgMemAccLat                  29316.89                       # Average memory access latency per DRAM burst
-system.physmem.avgQLat                       10566.89                       # Average queueing delay per DRAM burst
-system.physmem.avgRdBW                          24.43                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       24.44                       # Average system read bandwidth in MiByte/s
-system.physmem.avgRdQLen                         1.03                       # Average read queue length when enqueuing
-system.physmem.avgWrBW                          16.37                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgWrBWSys                       16.37                       # Average system write bandwidth in MiByte/s
-system.physmem.avgWrQLen                        19.41                       # Average write queue length when enqueuing
-system.physmem.busUtil                           0.32                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       0.19                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.13                       # Data bus utilization in percentage for writes
-system.physmem.bw_inst_read::cpu.inst          599436                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             599436                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst             24442739                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                24442739                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          16371437                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst            24442739                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               40814176                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_write::writebacks          16371437                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               16371437                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bytesPerActivate::samples        65344                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      235.879530                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     156.532408                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     241.691059                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          24749     37.87%     37.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        18254     27.94%     65.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         7150     10.94%     76.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         7883     12.06%     88.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2042      3.12%     91.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1102      1.69%     93.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895          756      1.16%     94.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          612      0.94%     95.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         2796      4.28%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          65344                       # Bytes accessed per row activation
-system.physmem.bytesReadDRAM                  9229248                       # Total number of bytes read from DRAM
-system.physmem.bytesReadSys                   9235648                       # Total read bytes from the system interface side
-system.physmem.bytesReadWrQ                      6400                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   6184768                       # Total number of bytes written to DRAM
-system.physmem.bytesWrittenSys                6185920                       # Total written bytes from the system interface side
-system.physmem.bytes_inst_read::cpu.inst       226496                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          226496                       # Number of instructions bytes read from this memory
-system.physmem.bytes_read::cpu.inst           9235648                       # Number of bytes read from this memory
-system.physmem.bytes_read::total              9235648                       # Number of bytes read from this memory
-system.physmem.bytes_written::writebacks      6185920                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           6185920                       # Number of bytes written to this memory
-system.physmem.memoryStateTime::IDLE     265986637250                       # Time in different power states
-system.physmem.memoryStateTime::REF       12617020000                       # Time in different power states
-system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT       99239970250                       # Time in different power states
-system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
+system.physmem.bytes_read::cpu.inst           9220736                       # Number of bytes read from this memory
+system.physmem.bytes_read::total              9220736                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       221440                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          221440                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      6177024                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           6177024                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst             144074                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                144074                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           96516                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                96516                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst             25483894                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                25483894                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          612007                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             612007                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          17071807                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               17071807                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          17071807                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst            25483894                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               42555702                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        144074                       # Number of read requests accepted
+system.physmem.writeReqs                        96516                       # Number of write requests accepted
+system.physmem.readBursts                      144074                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                      96516                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                  9213952                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      6784                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   6175488                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                   9220736                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                6177024                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      106                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0                9331                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                8974                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                8995                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                8704                       # Per bank write bursts
+system.physmem.perBankRdBursts::4                9445                       # Per bank write bursts
+system.physmem.perBankRdBursts::5                9338                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                8941                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                8096                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                8562                       # Per bank write bursts
+system.physmem.perBankRdBursts::9                8674                       # Per bank write bursts
+system.physmem.perBankRdBursts::10               8773                       # Per bank write bursts
+system.physmem.perBankRdBursts::11               9481                       # Per bank write bursts
+system.physmem.perBankRdBursts::12               9368                       # Per bank write bursts
+system.physmem.perBankRdBursts::13               9509                       # Per bank write bursts
+system.physmem.perBankRdBursts::14               8709                       # Per bank write bursts
+system.physmem.perBankRdBursts::15               9068                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                6188                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                6094                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                6004                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                5817                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                6158                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                6168                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                6012                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                5489                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                5725                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                5819                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               5961                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               6448                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               6304                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               6266                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               5996                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               6043                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.num_reads::cpu.inst             144307                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                144307                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           96655                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total                96655                       # Number of write requests responded to by this memory
-system.physmem.pageHitRate                      72.86                       # Row buffer hit rate, read and write combined
-system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.perBankRdBursts::0                9328                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                8986                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                9010                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                8718                       # Per bank write bursts
-system.physmem.perBankRdBursts::4                9475                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                9358                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                8951                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                8100                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                8572                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                8669                       # Per bank write bursts
-system.physmem.perBankRdBursts::10               8784                       # Per bank write bursts
-system.physmem.perBankRdBursts::11               9499                       # Per bank write bursts
-system.physmem.perBankRdBursts::12               9376                       # Per bank write bursts
-system.physmem.perBankRdBursts::13               9538                       # Per bank write bursts
-system.physmem.perBankRdBursts::14               8741                       # Per bank write bursts
-system.physmem.perBankRdBursts::15               9102                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                6202                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                6099                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                6021                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                5821                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                6172                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                6184                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                6018                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                5493                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                5732                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                5815                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               5965                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               6456                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               6307                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               6282                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               6014                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               6056                       # Per bank write bursts
-system.physmem.rdPerTurnAround::samples          5563                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        25.922344                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      382.692234                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023           5559     99.93%     99.93% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-2047            3      0.05%     99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::27648-28671            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            5563                       # Reads before turning the bus around for writes
-system.physmem.rdQLenPdf::0                    143841                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       346                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        20                       # What read queue length does an incoming req see
+system.physmem.totGap                    361825986500                       # Total gap between requests
+system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
+system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
+system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
+system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
+system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
+system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  144074                       # Read request sizes (log2)
+system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
+system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
+system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
+system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
+system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
+system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
+system.physmem.writePktSize::6                  96516                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    143606                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       344                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        18                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
@@ -618,46 +125,6 @@ system.physmem.rdQLenPdf::28                        0                       # Wh
 system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.readBursts                      144307                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  144307                       # Read request sizes (log2)
-system.physmem.readReqs                        144307                       # Number of read requests accepted
-system.physmem.readRowHitRate                   76.88                       # Row buffer hit rate for reads
-system.physmem.readRowHits                     110862                       # Number of row buffer hits during reads
-system.physmem.servicedByWrQ                      100                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.totBusLat                    721035000                       # Total ticks spent in databus transfers
-system.physmem.totGap                    377848294500                       # Total gap between requests
-system.physmem.totMemAccLat                4227701250                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totQLat                     1523820000                       # Total ticks spent queuing
-system.physmem.wrPerTurnAround::samples          5563                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        17.371382                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       17.273622                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        2.337365                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-17            2499     44.92%     44.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18-19            2925     52.58%     97.50% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-21              45      0.81%     98.31% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22-23              18      0.32%     98.63% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-25              19      0.34%     98.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26-27              16      0.29%     99.26% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-29              12      0.22%     99.48% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::30-31               7      0.13%     99.60% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-33               2      0.04%     99.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::34-35               3      0.05%     99.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-37               1      0.02%     99.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::38-39               4      0.07%     99.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-41               4      0.07%     99.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::42-43               2      0.04%     99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::46-47               1      0.02%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-49               1      0.02%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-53               1      0.02%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::70-71               2      0.04%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-73               1      0.02%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            5563                       # Writes before turning the bus around for reads
 system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
@@ -673,36 +140,36 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     3052                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     3240                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     5530                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     5663                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     5670                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     5657                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     5657                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     5655                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     5664                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     5680                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     5671                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     5684                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     5707                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     5632                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     5620                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     5645                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     5589                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     5570                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                       16                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                        9                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                        4                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                        5                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     2930                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     3132                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     5541                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     5647                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     5676                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     5658                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     5671                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     5685                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     5655                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     5675                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     5648                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     5690                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     5726                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     5661                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     5642                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     5632                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     5590                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     5576                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                       13                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                       16                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                        7                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                        6                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::37                        6                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                        5                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                        6                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                        5                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::40                        2                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::41                        2                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::43                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
@@ -722,17 +189,551 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.writeBursts                      96655                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                  96655                       # Write request sizes (log2)
-system.physmem.writeReqs                        96655                       # Number of write requests accepted
-system.physmem.writeRowHitRate                  66.87                       # Row buffer hit rate for writes
-system.physmem.writeRowHits                     64630                       # Number of row buffer hits during writes
-system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.physmem.bytesPerActivate::samples        64715                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      237.790435                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     157.392081                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     243.201287                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          24444     37.77%     37.77% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        18161     28.06%     65.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         6768     10.46%     76.29% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         7845     12.12%     88.42% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2212      3.42%     91.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1114      1.72%     93.55% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          793      1.23%     94.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          596      0.92%     95.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         2782      4.30%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          64715                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          5568                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        25.855065                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      382.360630                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023           5564     99.93%     99.93% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-2047            3      0.05%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::27648-28671            1      0.02%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total            5568                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          5568                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.329741                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       17.226111                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        2.490816                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-17            2624     47.13%     47.13% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18-19            2801     50.31%     97.43% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-21              48      0.86%     98.29% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22-23              25      0.45%     98.74% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-25              21      0.38%     99.12% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26-27              12      0.22%     99.34% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-29               8      0.14%     99.48% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::30-31               6      0.11%     99.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-33               3      0.05%     99.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::34-35               4      0.07%     99.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-37               1      0.02%     99.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::38-39               5      0.09%     99.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-41               2      0.04%     99.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::50-51               1      0.02%     99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-53               1      0.02%     99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-57               1      0.02%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::58-59               1      0.02%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-69               2      0.04%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::70-71               1      0.02%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-81               1      0.02%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            5568                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     1536727500                       # Total ticks spent queuing
+system.physmem.totMemAccLat                4236127500                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    719840000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       10674.09                       # Average queueing delay per DRAM burst
+system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
+system.physmem.avgMemAccLat                  29424.09                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          25.47                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                          17.07                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       25.48                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                       17.07                       # Average system write bandwidth in MiByte/s
+system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
+system.physmem.busUtil                           0.33                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       0.20                       # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite                      0.13                       # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen                         1.03                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        19.41                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     111270                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     64468                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   77.29                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  66.80                       # Row buffer hit rate for writes
+system.physmem.avgGap                      1503911.16                       # Average gap between requests
+system.physmem.pageHitRate                      73.08                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE     254085865250                       # Time in different power states
+system.physmem.memoryStateTime::REF       12081940000                       # Time in different power states
+system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
+system.physmem.memoryStateTime::ACT       95653103250                       # Time in different power states
+system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
+system.membus.throughput                     42555702                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq               43212                       # Transaction distribution
+system.membus.trans_dist::ReadResp              43212                       # Transaction distribution
+system.membus.trans_dist::Writeback             96516                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            100862                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           100862                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       384664                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 384664                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     15397760                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total            15397760                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus               15397760                       # Total data (bytes)
+system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy          1075054000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               0.3                       # Layer utilization (%)
+system.membus.respLayer1.occupancy         1362559750                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization              0.4                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.cpu.branchPred.lookups               132256489                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          98266035                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           6550672                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             68852239                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                64692489                       # Number of BTB hits
+system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.branchPred.BTBHitPct             93.958439                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 9992276                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect              17882                       # Number of incorrect RAS predictions.
+system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
+system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
+system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
+system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
+system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
+system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
+system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
+system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
+system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
+system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
+system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
+system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
+system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
+system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
+system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
+system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
+system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.dtb.inst_hits                            0                       # ITB inst hits
+system.cpu.dtb.inst_misses                          0                       # ITB inst misses
+system.cpu.dtb.read_hits                            0                       # DTB read hits
+system.cpu.dtb.read_misses                          0                       # DTB read misses
+system.cpu.dtb.write_hits                           0                       # DTB write hits
+system.cpu.dtb.write_misses                         0                       # DTB write misses
+system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                        0                       # DTB read accesses
+system.cpu.dtb.write_accesses                       0                       # DTB write accesses
+system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.dtb.hits                                 0                       # DTB hits
+system.cpu.dtb.misses                               0                       # DTB misses
+system.cpu.dtb.accesses                             0                       # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
+system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
+system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
+system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
+system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
+system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
+system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
+system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
+system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
+system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
+system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
+system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
+system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
+system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
+system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
+system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
+system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.itb.inst_hits                            0                       # ITB inst hits
+system.cpu.itb.inst_misses                          0                       # ITB inst misses
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
+system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.itb.hits                                 0                       # DTB hits
+system.cpu.itb.misses                               0                       # DTB misses
+system.cpu.itb.accesses                             0                       # DTB accesses
+system.cpu.workload.num_syscalls                  548                       # Number of system calls
+system.cpu.numCycles                        723652031                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.committedInsts                   506582155                       # Number of instructions committed
+system.cpu.committedOps                     548695378                       # Number of ops (including micro ops) committed
+system.cpu.discardedOps                      14122871                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
+system.cpu.cpi                               1.428499                       # CPI: cycles per instruction
+system.cpu.ipc                               0.700036                       # IPC: instructions per cycle
+system.cpu.tickCycles                       687771211                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                        35880820                       # Total number of cycles that the object has spent stopped
+system.cpu.icache.tags.replacements             17660                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1187.686040                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           200323378                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs             19531                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          10256.688239                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst  1187.686040                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.579925                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.579925                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1871                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           41                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           63                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2           61                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3          302                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1404                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.913574                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses         400705349                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        400705349                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    200323378                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       200323378                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     200323378                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        200323378                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    200323378                       # number of overall hits
+system.cpu.icache.overall_hits::total       200323378                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst        19531                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total         19531                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst        19531                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total          19531                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst        19531                       # number of overall misses
+system.cpu.icache.overall_misses::total         19531                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    466485747                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    466485747                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    466485747                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    466485747                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    466485747                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    466485747                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    200342909                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    200342909                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    200342909                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    200342909                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    200342909                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    200342909                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000097                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000097                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000097                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000097                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000097                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000097                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23884.375966                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 23884.375966                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 23884.375966                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 23884.375966                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 23884.375966                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 23884.375966                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst        19531                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total        19531                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst        19531                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total        19531                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst        19531                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total        19531                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    426041253                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    426041253                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    426041253                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    426041253                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    426041253                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    426041253                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000097                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000097                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000097                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.000097                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000097                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.000097                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21813.591368                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21813.591368                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21813.591368                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 21813.591368                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21813.591368                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 21813.591368                       # average overall mshr miss latency
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.toL2Bus.throughput               394741942                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq         806872                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp        806872                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback      1068421                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       356393                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       356393                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        39062                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      3355889                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           3394951                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1249984                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    141577920                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total      142827904                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus         142827904                       # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy     2184264000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          0.6                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy      29987747                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy    1744465986                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization          0.5                       # Layer utilization (%)
+system.cpu.l2cache.tags.replacements           111319                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        27632.304905                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            1684536                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           142508                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            11.820642                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle     162493519500                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 23524.678269                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  4107.626636                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.717916                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.125355                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.843271                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        31189                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           67                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          325                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         4925                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        25872                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.951813                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         18352389                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        18352389                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.inst       763644                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total         763644                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks      1068421                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total      1068421                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.inst       255531                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       255531                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst      1019175                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         1019175                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst      1019175                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        1019175                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst        43228                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total        43228                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.inst       100862                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       100862                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst       144090                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        144090                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst       144090                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       144090                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst   3220977500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total   3220977500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst   7166346750                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   7166346750                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst  10387324250                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  10387324250                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst  10387324250                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  10387324250                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst       806872                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total       806872                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks      1068421                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total      1068421                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.inst       356393                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       356393                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst      1163265                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      1163265                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst      1163265                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      1163265                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.053575                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.053575                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst     0.283008                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.283008                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.123867                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.123867                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.123867                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.123867                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74511.369945                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 74511.369945                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 71051.007813                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71051.007813                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72089.140468                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 72089.140468                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72089.140468                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 72089.140468                       # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
+system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
+system.cpu.l2cache.writebacks::writebacks        96516                       # number of writebacks
+system.cpu.l2cache.writebacks::total            96516                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst           16                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total           16                       # number of ReadReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst           16                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total           16                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst           16                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total           16                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        43212                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total        43212                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst       100862                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       100862                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst       144074                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       144074                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst       144074                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       144074                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst   2672872000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total   2672872000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst   5889125250                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   5889125250                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   8561997250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total   8561997250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   8561997250                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total   8561997250                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.053555                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.053555                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst     0.283008                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.283008                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.123853                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.123853                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.123853                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.123853                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61854.855133                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61854.855133                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 58387.948385                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58387.948385                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59427.774963                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59427.774963                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59427.774963                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59427.774963                       # average overall mshr miss latency
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu.dcache.tags.replacements           1139638                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4071.125159                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           169305637                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           1143734                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs            148.028857                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle        4807181250                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.inst  4071.125159                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.inst     0.993927                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.993927                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           27                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           18                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          550                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3         3501                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses         342864800                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        342864800                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.inst    112789835                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       112789835                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.inst     53538720                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       53538720                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.inst      1488541                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total      1488541                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.inst      1488541                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total      1488541                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.inst     166328555                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        166328555                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.inst    166328555                       # number of overall hits
+system.cpu.dcache.overall_hits::total       166328555                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.inst       854310                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        854310                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.inst       700586                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       700586                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.inst      1554896                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        1554896                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.inst      1554896                       # number of overall misses
+system.cpu.dcache.overall_misses::total       1554896                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.inst  13696134233                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  13696134233                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.inst  20619900500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  20619900500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.inst  34316034733                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  34316034733                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.inst  34316034733                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  34316034733                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.inst    113644145                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    113644145                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.inst     54239306                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total     54239306                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.inst      1488541                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total      1488541                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.inst      1488541                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total      1488541                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.inst    167883451                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    167883451                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.inst    167883451                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    167883451                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.inst     0.007517                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.007517                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.inst     0.012917                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.012917                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.inst     0.009262                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.009262                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.inst     0.009262                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.009262                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 16031.808399                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 16031.808399                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 29432.361623                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 29432.361623                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.inst 22069.665581                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 22069.665581                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.inst 22069.665581                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 22069.665581                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks      1068421                       # number of writebacks
+system.cpu.dcache.writebacks::total           1068421                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.inst        66718                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total        66718                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.inst       344444                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       344444                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.inst       411162                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       411162                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.inst       411162                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       411162                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.inst       787592                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       787592                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.inst       356142                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       356142                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.inst      1143734                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      1143734                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.inst      1143734                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      1143734                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst  11245323264                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  11245323264                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst  10075452250                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  10075452250                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.inst  21320775514                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  21320775514                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.inst  21320775514                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  21320775514                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst     0.006930                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.006930                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst     0.006566                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.006566                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.inst     0.006813                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.006813                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.inst     0.006813                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.006813                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 14278.107528                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14278.107528                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 28290.547731                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28290.547731                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 18641.375979                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 18641.375979                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 18641.375979                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 18641.375979                       # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
index 522c4ee18..5c43314b3 100644
--- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
@@ -1,108 +1,108 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.201640                       # Number of seconds simulated
-sim_ticks                                201639641000                       # Number of ticks simulated
-final_tick                               201639641000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.195021                       # Number of seconds simulated
+sim_ticks                                195020773000                       # Number of ticks simulated
+final_tick                               195020773000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 135689                       # Simulator instruction rate (inst/s)
-host_op_rate                                   152980                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               54153116                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 265540                       # Number of bytes of host memory used
-host_seconds                                  3723.51                       # Real time elapsed on the host
+host_inst_rate                                 105873                       # Simulator instruction rate (inst/s)
+host_op_rate                                   114698                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               40866801                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 257276                       # Number of bytes of host memory used
+host_seconds                                  4772.11                       # Real time elapsed on the host
 sim_insts                                   505237723                       # Number of instructions simulated
-sim_ops                                     569624283                       # Number of ops (including micro ops) simulated
+sim_ops                                     547350944                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            217344                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           9271296                       # Number of bytes read from this memory
-system.physmem.bytes_read::total              9488640                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       217344                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          217344                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      6252864                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           6252864                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               3396                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             144864                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                148260                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           97701                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total                97701                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst              1077883                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             45979530                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                47057414                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         1077883                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            1077883                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          31010093                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               31010093                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          31010093                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             1077883                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            45979530                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               78067507                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        148261                       # Number of read requests accepted
-system.physmem.writeReqs                        97701                       # Number of write requests accepted
-system.physmem.readBursts                      148261                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                      97701                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                  9478784                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      9920                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   6251328                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                   9488704                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                6252864                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      155                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytes_read::cpu.inst            207936                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           9274560                       # Number of bytes read from this memory
+system.physmem.bytes_read::total              9482496                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       207936                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          207936                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      6243584                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           6243584                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               3249                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             144915                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                148164                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           97556                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                97556                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst              1066225                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             47556780                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                48623005                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         1066225                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            1066225                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          32014969                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               32014969                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          32014969                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             1066225                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            47556780                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               80637974                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        148164                       # Number of read requests accepted
+system.physmem.writeReqs                        97556                       # Number of write requests accepted
+system.physmem.readBursts                      148164                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                      97556                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                  9474176                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      8320                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   6241856                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                   9482496                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                6243584                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      130                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs              8                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                9600                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                9245                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                9272                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                9002                       # Per bank write bursts
-system.physmem.perBankRdBursts::4                9776                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                9633                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                9118                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                8324                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                8782                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                8907                       # Per bank write bursts
-system.physmem.perBankRdBursts::10               8927                       # Per bank write bursts
-system.physmem.perBankRdBursts::11               9740                       # Per bank write bursts
-system.physmem.perBankRdBursts::12               9612                       # Per bank write bursts
-system.physmem.perBankRdBursts::13               9774                       # Per bank write bursts
-system.physmem.perBankRdBursts::14               8952                       # Per bank write bursts
-system.physmem.perBankRdBursts::15               9442                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                6262                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                6157                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                6103                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                5900                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                6261                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                6280                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                6052                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                5550                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                5797                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                5910                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               5990                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               6523                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               6359                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               6344                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               6057                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               6132                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs              9                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0                9585                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                9250                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                9223                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                8986                       # Per bank write bursts
+system.physmem.perBankRdBursts::4                9777                       # Per bank write bursts
+system.physmem.perBankRdBursts::5                9541                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                9063                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                8318                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                8791                       # Per bank write bursts
+system.physmem.perBankRdBursts::9                8912                       # Per bank write bursts
+system.physmem.perBankRdBursts::10               8928                       # Per bank write bursts
+system.physmem.perBankRdBursts::11               9775                       # Per bank write bursts
+system.physmem.perBankRdBursts::12               9650                       # Per bank write bursts
+system.physmem.perBankRdBursts::13               9761                       # Per bank write bursts
+system.physmem.perBankRdBursts::14               8979                       # Per bank write bursts
+system.physmem.perBankRdBursts::15               9495                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                6258                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                6150                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                6073                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                5890                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                6255                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                6221                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                6024                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                5542                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                5802                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                5901                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               5976                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               6519                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               6371                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               6333                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               6062                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               6152                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    201639615000                       # Total gap between requests
+system.physmem.totGap                    195020664000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  148261                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  148164                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                  97701                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    138302                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      9255                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       486                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                        54                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                         7                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                         2                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                  97556                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    137840                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      9554                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       574                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                        60                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                         6                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
@@ -144,32 +144,32 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     2250                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     2402                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     5292                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     5790                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     5812                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     5837                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     5844                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     5837                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     5855                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     5847                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     5870                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     5853                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     5913                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     6010                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     5828                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     5851                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     5805                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     5732                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                       18                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                       11                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                        8                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                        7                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                        8                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                        3                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                        2                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     2105                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     2265                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     5298                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     5757                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     5823                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     5839                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     5855                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     5867                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     5891                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     5873                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     5884                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     5884                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     5906                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     5955                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     5832                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     5848                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     5868                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     5742                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                       21                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                       12                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                        6                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                        5                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
@@ -193,106 +193,105 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        65483                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      240.203045                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     153.557671                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     255.515687                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          26845     41.00%     41.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        17105     26.12%     67.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         6057      9.25%     76.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         6227      9.51%     85.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         3215      4.91%     90.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1344      2.05%     92.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895          866      1.32%     94.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          634      0.97%     95.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         3190      4.87%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          65483                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          5723                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        25.877861                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      376.772634                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023           5719     99.93%     99.93% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-2047            3      0.05%     99.98% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples        65254                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      240.825329                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     153.977579                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     256.120796                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          26634     40.82%     40.82% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        17090     26.19%     67.01% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         6012      9.21%     76.22% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         6427      9.85%     86.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         3020      4.63%     90.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1342      2.06%     92.75% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          838      1.28%     94.04% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          692      1.06%     95.10% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         3199      4.90%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          65254                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          5732                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        25.824669                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      376.283766                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023           5727     99.91%     99.91% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-2047            4      0.07%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::27648-28671            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            5723                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          5723                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        17.067447                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.968448                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        2.305335                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-17            3462     60.49%     60.49% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18-19            2077     36.29%     96.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-21              88      1.54%     98.32% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22-23              26      0.45%     98.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-25              19      0.33%     99.11% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26-27               9      0.16%     99.27% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-29              14      0.24%     99.51% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::30-31               5      0.09%     99.60% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-33               2      0.03%     99.63% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::34-35               1      0.02%     99.65% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-37               6      0.10%     99.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::38-39               2      0.03%     99.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-41               3      0.05%     99.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-45               2      0.03%     99.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::46-47               1      0.02%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-53               2      0.03%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::54-55               2      0.03%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-57               1      0.02%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-73               1      0.02%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            5723                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     1816896000                       # Total ticks spent queuing
-system.physmem.totMemAccLat                4593883500                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    740530000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       12267.54                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            5732                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          5732                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.014829                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.919448                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        2.243342                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-17            3608     62.94%     62.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18-19            1943     33.90%     96.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-21              77      1.34%     98.19% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22-23              32      0.56%     98.74% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-25              17      0.30%     99.04% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26-27              19      0.33%     99.37% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-29              11      0.19%     99.56% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::30-31               3      0.05%     99.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-33               2      0.03%     99.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::34-35               6      0.10%     99.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-37               2      0.03%     99.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::38-39               3      0.05%     99.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-41               2      0.03%     99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::42-43               1      0.02%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-49               1      0.02%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::50-51               3      0.05%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-61               1      0.02%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-77               1      0.02%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            5732                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     1847546250                       # Total ticks spent queuing
+system.physmem.totMemAccLat                4623183750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    740170000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       12480.55                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  31017.54                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          47.01                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                          31.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       47.06                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                       31.01                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  31230.55                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          48.58                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                          32.01                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       48.62                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                       32.01                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           0.61                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       0.37                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.24                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.05                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        19.04                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     116026                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     64266                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   78.34                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  65.78                       # Row buffer hit rate for writes
-system.physmem.avgGap                       819799.87                       # Average gap between requests
-system.physmem.pageHitRate                      73.35                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE     120286035750                       # Time in different power states
-system.physmem.memoryStateTime::REF        6732960000                       # Time in different power states
+system.physmem.busUtil                           0.63                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       0.38                       # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite                      0.25                       # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen                         1.06                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        19.21                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     116004                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     64298                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   78.36                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  65.91                       # Row buffer hit rate for writes
+system.physmem.avgGap                       793670.29                       # Average gap between requests
+system.physmem.pageHitRate                      73.42                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE     115260013250                       # Time in different power states
+system.physmem.memoryStateTime::REF        6511960000                       # Time in different power states
 system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT       74617456750                       # Time in different power states
+system.physmem.memoryStateTime::ACT       73245775250                       # Time in different power states
 system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.membus.throughput                     78067507                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq               46965                       # Transaction distribution
-system.membus.trans_dist::ReadResp              46964                       # Transaction distribution
-system.membus.trans_dist::Writeback             97701                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq                8                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp               8                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            101296                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           101296                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       394238                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 394238                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     15741504                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total            15741504                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus               15741504                       # Total data (bytes)
+system.membus.throughput                     80637974                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq               46897                       # Transaction distribution
+system.membus.trans_dist::ReadResp              46897                       # Transaction distribution
+system.membus.trans_dist::Writeback             97556                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq                9                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp               9                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            101267                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           101267                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       393902                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 393902                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     15726080                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total            15726080                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus               15726080                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy          1079764000                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               0.5                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         1396376742                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy          1079373000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               0.6                       # Layer utilization (%)
+system.membus.respLayer1.occupancy         1394503741                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.7                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.branchPred.lookups               185905498                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         145717903                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           7288959                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             95047377                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                88827374                       # Number of BTB hits
+system.cpu.branchPred.lookups               200189098                       # Number of BP lookups
+system.cpu.branchPred.condPredicted         149602484                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           7338467                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups            107397070                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                96034676                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             93.455892                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                12842646                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect             117058                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             89.420201                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                14381720                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect             112950                       # Number of incorrect RAS predictions.
 system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -378,517 +377,516 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  548                       # Number of system calls
-system.cpu.numCycles                        403279283                       # number of cpu cycles simulated
+system.cpu.numCycles                        390041547                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles          120682752                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      776131290                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                   185905498                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches          101670020                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     172998904                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                37503258                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles               68039482                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                   86                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles           481                       # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles           57                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                 115897812                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes               2525334                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          391132406                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.225985                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.009732                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles          129697358                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      835224616                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   200189098                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches          110416396                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     251952283                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                16305676                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles                   54                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles           725                       # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles           54                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                 125022986                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               2819221                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          389803312                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.324321                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.986703                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                218146201     55.77%     55.77% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 14394493      3.68%     59.45% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 23167694      5.92%     65.38% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 22933314      5.86%     71.24% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                 21066439      5.39%     76.63% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                 11728153      3.00%     79.62% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                 13552888      3.47%     83.09% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                 12244725      3.13%     86.22% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                 53898499     13.78%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                204497213     52.46%     52.46% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 16740879      4.29%     56.76% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 25096143      6.44%     63.19% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 25406235      6.52%     69.71% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                 22255484      5.71%     75.42% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                 19361790      4.97%     80.39% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                 11228649      2.88%     83.27% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                 12061789      3.09%     86.36% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 53155130     13.64%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            391132406                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.460984                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.924550                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                127941260                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              66012107                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 164309835                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               3533487                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles               29335717                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved             26533351                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                 77647                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              841607037                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                303900                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles               29335717                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                132935936                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                 7523486                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles       48032128                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 162776327                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              10528812                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              816179204                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                  4868                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                4457827                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                3314300                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                1212194                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.FullRegisterEvents             4787                       # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands           972434380                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            3587695415                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       3300630013                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups               432                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps             666252291                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                306182089                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts            2293511                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts        2293509                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  23291983                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            173719051                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            74905434                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads          30225729                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores         17207987                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  768522572                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded             3775769                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 668800812                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued           1727981                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined       200793138                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined    527082191                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved         798137                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     391132406                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.709909                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.765965                       # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total            389803312                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.513251                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        2.141373                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                103986680                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             118578898                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 144750042                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              14406980                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                8080712                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved             27470111                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                 74706                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              847095448                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                284101                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                8080712                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                110645607                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                38128402                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles       58728570                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 152416718                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              21803303                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              812473012                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                 12287                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                7169304                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                5481410                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents                7159011                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands           991790845                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            3569028243                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        858899446                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups               368                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps             654123751                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                337667094                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts            2298389                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts        3025745                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  46474458                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            165564895                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            77029612                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          33913346                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         24718127                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  764294822                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded             3785962                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 654447179                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            456586                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       218477687                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined    578622397                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved         808330                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     389803312                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.678916                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.824028                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           138616997     35.44%     35.44% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            67517265     17.26%     52.70% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            69869307     17.86%     70.57% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            51755005     13.23%     83.80% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            32440287      8.29%     92.09% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5            16135836      4.13%     96.22% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             9617335      2.46%     98.68% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7             3307412      0.85%     99.52% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8             1872962      0.48%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           146772690     37.65%     37.65% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            67318590     17.27%     54.92% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            64772838     16.62%     71.54% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            47064670     12.07%     83.61% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            29521584      7.57%     91.19% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            16702188      4.28%     95.47% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6            11171964      2.87%     98.34% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             4070461      1.04%     99.38% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8             2408327      0.62%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       391132406                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       389803312                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                  630442      6.26%      6.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%      6.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      6.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      6.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      6.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      6.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      6.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      6.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      6.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      6.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      6.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      6.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      6.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      6.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      6.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      6.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      6.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      6.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      6.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      6.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      6.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      6.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      6.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      6.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      6.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      6.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      6.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      6.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      6.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                6879641     68.30%     74.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite               2562211     25.44%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                 1532664     16.20%     16.20% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%     16.20% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     16.20% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     16.20% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     16.20% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     16.20% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     16.20% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     16.20% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     16.20% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     16.20% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     16.20% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     16.20% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     16.20% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     16.20% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     16.20% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     16.20% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     16.20% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     16.20% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     16.20% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     16.20% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     16.20% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     16.20% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     16.20% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     16.20% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     16.20% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     16.20% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     16.20% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     16.20% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     16.20% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                4929602     52.11%     68.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               2998000     31.69%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             449864838     67.26%     67.26% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult               383889      0.06%     67.32% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     67.32% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                 102      0.00%     67.32% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     67.32% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     67.32% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     67.32% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     67.32% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     67.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     67.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     67.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     67.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     67.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     67.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     67.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     67.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     67.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     67.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     67.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     67.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     67.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     67.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     67.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     67.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     67.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              3      0.00%     67.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.32% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            154509639     23.10%     90.42% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            64042341      9.58%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             441248731     67.42%     67.42% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult               435633      0.07%     67.49% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     67.49% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     67.49% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     67.49% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     67.49% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     67.49% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     67.49% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     67.49% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     67.49% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     67.49% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     67.49% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     67.49% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     67.49% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     67.49% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     67.49% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     67.49% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     67.49% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     67.49% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     67.49% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     67.49% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     67.49% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     67.49% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     67.49% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     67.49% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              3      0.00%     67.49% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.49% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.49% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.49% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            147725739     22.57%     90.06% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            65037073      9.94%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              668800812                       # Type of FU issued
-system.cpu.iq.rate                           1.658406                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                    10072294                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.015060                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         1740534066                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         973902079                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    649227410                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads                 239                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes                322                       # Number of floating instruction queue writes
+system.cpu.iq.FU_type_0::total              654447179                       # Type of FU issued
+system.cpu.iq.rate                           1.677891                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     9460266                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.014455                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         1708614343                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         987386046                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    633379143                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads                 179                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes                280                       # Number of floating instruction queue writes
 system.cpu.iq.fp_inst_queue_wakeup_accesses           16                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              678872985                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                     121                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads          9444118                       # Number of loads that had data forwarded from stores
+system.cpu.iq.int_alu_accesses              663907354                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                      91                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads          7666119                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads     47689496                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        34046                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation       814715                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores     18044957                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads     49680139                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        29913                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation       831675                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores     20169135                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads        19567                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked          5233                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads      1622994                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked          4397                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles               29335717                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                 3955691                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles               1178658                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           773883644                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts           1025688                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             173719051                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             74905434                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts            2287227                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                 242970                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                870100                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents         814715                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect        4363839                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect      4034750                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              8398589                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             659340001                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             151050186                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           9460811                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                8080712                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                32831376                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles               2550941                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           769700415                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            729466                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             165564895                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             77029612                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts            2297420                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                 241239                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents               2243400                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents         831675                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        4474207                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      4147009                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              8621216                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             645315428                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             144284542                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           9131751                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                       1585303                       # number of nop insts executed
-system.cpu.iew.exec_refs                    213740794                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                139088077                       # Number of branches executed
-system.cpu.iew.exec_stores                   62690608                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.634946                       # Inst execution rate
-system.cpu.iew.wb_sent                      654323635                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     649227426                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 378014910                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 657704988                       # num instructions consuming a value
+system.cpu.iew.exec_nop                       1619631                       # number of nop insts executed
+system.cpu.iew.exec_refs                    207974195                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                141482846                       # Number of branches executed
+system.cpu.iew.exec_stores                   63689653                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.654479                       # Inst execution rate
+system.cpu.iew.wb_sent                      638544011                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     633379159                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 371951295                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 631497340                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.609871                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.574748                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.623876                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.588999                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts       202955681                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts       221053017                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls         2977632                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts           7214032                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    361796689                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.578146                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.256071                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts           7266341                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    357986400                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.532725                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.266212                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    156712744     43.32%     43.32% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     96319147     26.62%     69.94% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     33326252      9.21%     79.15% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     17957546      4.96%     84.11% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     16748053      4.63%     88.74% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      7262749      2.01%     90.75% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      6923592      1.91%     92.66% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      3096479      0.86%     93.52% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     23450127      6.48%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    161840085     45.21%     45.21% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     93598872     26.15%     71.35% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     31669454      8.85%     80.20% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     16147172      4.51%     84.71% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     14656641      4.09%     88.81% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      6778711      1.89%     90.70% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      6277378      1.75%     92.45% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      3013551      0.84%     93.29% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     24004536      6.71%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    361796689                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    357986400                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts            506581607                       # Number of instructions committed
-system.cpu.commit.committedOps              570968167                       # Number of ops (including micro ops) committed
+system.cpu.commit.committedOps              548694828                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                      182890032                       # Number of memory references committed
-system.cpu.commit.loads                     126029555                       # Number of loads committed
+system.cpu.commit.refs                      172745233                       # Number of memory references committed
+system.cpu.commit.loads                     115884756                       # Number of loads committed
 system.cpu.commit.membars                     1488542                       # Number of memory barriers committed
 system.cpu.commit.branches                  121548301                       # Number of branches committed
 system.cpu.commit.fp_insts                         16                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                 470727693                       # Number of committed integer instructions.
+system.cpu.commit.int_insts                 448454354                       # Number of committed integer instructions.
 system.cpu.commit.function_calls              9757362                       # Number of function calls committed.
 system.cpu.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu        387738913     67.91%     67.91% # Class of committed instruction
-system.cpu.commit.op_class_0::IntMult          339219      0.06%     67.97% # Class of committed instruction
-system.cpu.commit.op_class_0::IntDiv                0      0.00%     67.97% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatAdd              0      0.00%     67.97% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatCmp              0      0.00%     67.97% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatCvt              0      0.00%     67.97% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMult             0      0.00%     67.97% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatDiv              0      0.00%     67.97% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     67.97% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAdd               0      0.00%     67.97% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     67.97% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAlu               0      0.00%     67.97% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdCmp               0      0.00%     67.97% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdCvt               0      0.00%     67.97% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMisc              0      0.00%     67.97% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMult              0      0.00%     67.97% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     67.97% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdShift             0      0.00%     67.97% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     67.97% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     67.97% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     67.97% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     67.97% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     67.97% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     67.97% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     67.97% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMisc            3      0.00%     67.97% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     67.97% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     67.97% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     67.97% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead       126029555     22.07%     90.04% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite       56860477      9.96%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu        375610373     68.46%     68.46% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult          339219      0.06%     68.52% # Class of committed instruction
+system.cpu.commit.op_class_0::IntDiv                0      0.00%     68.52% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatAdd              0      0.00%     68.52% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCmp              0      0.00%     68.52% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCvt              0      0.00%     68.52% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatMult             0      0.00%     68.52% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatDiv              0      0.00%     68.52% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     68.52% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAdd               0      0.00%     68.52% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     68.52% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAlu               0      0.00%     68.52% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCmp               0      0.00%     68.52% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCvt               0      0.00%     68.52% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMisc              0      0.00%     68.52% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMult              0      0.00%     68.52% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     68.52% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShift             0      0.00%     68.52% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     68.52% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     68.52% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     68.52% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     68.52% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     68.52% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     68.52% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     68.52% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMisc            3      0.00%     68.52% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     68.52% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     68.52% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     68.52% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead       115884756     21.12%     89.64% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite       56860477     10.36%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total         570968167                       # Class of committed instruction
-system.cpu.commit.bw_lim_events              23450127                       # number cycles where commit BW limit reached
+system.cpu.commit.op_class_0::total         548694828                       # Class of committed instruction
+system.cpu.commit.bw_lim_events              24004536                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                   1112263272                       # The number of ROB reads
-system.cpu.rob.rob_writes                  1577313182                       # The number of ROB writes
-system.cpu.timesIdled                          375340                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                        12146877                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads                   1103722571                       # The number of ROB reads
+system.cpu.rob.rob_writes                  1571491093                       # The number of ROB writes
+system.cpu.timesIdled                            5225                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                          238235                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                   505237723                       # Number of Instructions Simulated
-system.cpu.committedOps                     569624283                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               0.798197                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.798197                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.252823                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.252823                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               3074448522                       # number of integer regfile reads
-system.cpu.int_regfile_writes               755651134                       # number of integer regfile writes
+system.cpu.committedOps                     547350944                       # Number of Ops (including micro ops) Simulated
+system.cpu.cpi                               0.771996                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.771996                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.295343                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.295343                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                652860530                       # number of integer regfile reads
+system.cpu.int_regfile_writes               354600440                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                        16                       # number of floating regfile reads
-system.cpu.misc_regfile_reads               238959520                       # number of misc regfile reads
+system.cpu.cc_regfile_reads                2339325657                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                397666160                       # number of cc regfile writes
+system.cpu.misc_regfile_reads               231739115                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                2977084                       # number of misc regfile writes
-system.cpu.toL2Bus.throughput               738060588                       # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq         865494                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp        865493                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      1111057                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq           86                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp           86                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       348798                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       348798                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        34444                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      3505273                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           3539717                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1099136                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    147717056                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total      148816192                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus         148816192                       # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus         6080                       # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy     2273774999                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          1.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy      26477230                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.throughput               764614178                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq         866616                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp        866616                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback      1114497                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq           52                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp           52                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       348819                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       348819                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        30021                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      3515389                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           3545410                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       958720                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    148153024                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total      149111744                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus         149111744                       # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus         3904                       # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy     2279489000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          1.2                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy      23116485                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    1825044731                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    1829335495                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.9                       # Layer utilization (%)
-system.cpu.icache.tags.replacements             15336                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1096.367650                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           115876238                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs             17184                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs           6743.263385                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements             13145                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1062.088688                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           125003617                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs             14983                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs           8343.029901                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1096.367650                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.535336                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.535336                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024         1848                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           37                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1           57                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2           81                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3          301                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4         1372                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.902344                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         231812889                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        231812889                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    115876248                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       115876248                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     115876248                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        115876248                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    115876248                       # number of overall hits
-system.cpu.icache.overall_hits::total       115876248                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst        21562                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total         21562                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst        21562                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total          21562                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst        21562                       # number of overall misses
-system.cpu.icache.overall_misses::total         21562                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    560819979                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    560819979                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    560819979                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    560819979                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    560819979                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    560819979                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    115897810                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    115897810                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    115897810                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    115897810                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    115897810                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    115897810                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000186                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000186                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000186                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000186                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000186                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000186                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 26009.645627                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 26009.645627                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 26009.645627                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 26009.645627                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 26009.645627                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 26009.645627                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs         1208                       # number of cycles access was blocked
+system.cpu.icache.tags.occ_blocks::cpu.inst  1062.088688                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.518598                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.518598                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1838                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           32                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           49                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2           70                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3          297                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1390                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.897461                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses         250061011                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        250061011                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    125003619                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       125003619                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     125003619                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        125003619                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    125003619                       # number of overall hits
+system.cpu.icache.overall_hits::total       125003619                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst        19366                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total         19366                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst        19366                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total          19366                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst        19366                       # number of overall misses
+system.cpu.icache.overall_misses::total         19366                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    525397483                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    525397483                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    525397483                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    525397483                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    525397483                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    525397483                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    125022985                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    125022985                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    125022985                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    125022985                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    125022985                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    125022985                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000155                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000155                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000155                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000155                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000155                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000155                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27129.891717                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 27129.891717                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 27129.891717                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 27129.891717                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 27129.891717                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 27129.891717                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs         1332                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                16                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                15                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    75.500000                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    88.800000                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst         4292                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total         4292                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst         4292                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total         4292                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst         4292                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total         4292                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst        17270                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total        17270                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst        17270                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total        17270                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst        17270                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total        17270                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    408247770                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    408247770                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    408247770                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    408247770                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    408247770                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    408247770                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000149                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000149                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000149                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.000149                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000149                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.000149                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23639.129705                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 23639.129705                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23639.129705                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 23639.129705                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23639.129705                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 23639.129705                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         4325                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total         4325                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst         4325                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total         4325                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst         4325                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total         4325                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst        15041                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total        15041                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst        15041                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total        15041                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst        15041                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total        15041                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    373138014                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    373138014                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    373138014                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    373138014                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    373138014                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    373138014                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000120                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000120                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000120                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.000120                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000120                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.000120                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24808.058906                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24808.058906                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24808.058906                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 24808.058906                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24808.058906                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 24808.058906                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements           115515                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        27068.910861                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            1781873                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           146764                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            12.141077                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle      90165895500                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 22998.912938                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   364.941054                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  3705.056868                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.701871                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.011137                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.113069                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.826078                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        31249                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           64                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1            1                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2187                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         7697                       # Occupied blocks per task id
+system.cpu.l2cache.tags.replacements           115421                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        26962.800734                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            1786499                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           146666                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            12.180730                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle      88337540000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 22928.497316                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   342.512627                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  3691.790790                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.699722                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.010453                       # Average percentage of cache occupancy
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+system.cpu.l2cache.tags.occ_percent::total     0.822839                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        31245                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           63                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2223                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         7659                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::4        21300                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.953644                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         19098361                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        19098361                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst        13774                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data       804634                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total         818408                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks      1111057                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      1111057                       # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data           79                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total           79                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       247501                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       247501                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst        13774                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      1052135                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         1065909                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst        13774                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      1052135                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        1065909                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst         3401                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data        43590                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total        46991                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data            7                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total            7                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       101297                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       101297                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         3401                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       144887                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        148288                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         3401                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       144887                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       148288                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    252890250                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data   3330417250                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total   3583307500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   7356301749                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   7356301749                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    252890250                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  10686718999                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  10939609249                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    252890250                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  10686718999                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  10939609249                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst        17175                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data       848224                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total       865399                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks      1111057                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total      1111057                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data           86                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total           86                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       348798                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       348798                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst        17175                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      1197022                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      1214197                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst        17175                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      1197022                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      1214197                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.198020                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.051390                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.054300                       # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.081395                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.081395                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.290417                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.290417                       # miss rate for ReadExReq accesses
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 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -897,203 +895,219 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
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-system.cpu.l2cache.writebacks::total            97701                       # number of writebacks
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 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        10001                       # average UpgradeReq mshr miss latency
 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        10001                       # average UpgradeReq mshr miss latency
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+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60050.660630                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61414.050477                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61402.429010                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61402.683850                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61414.050477                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61402.429010                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61402.683850                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements           1192926                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4057.383105                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           190117545                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           1197022                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            158.825439                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle        4253859250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4057.383105                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.990572                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.990572                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements           1196298                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4055.671895                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           184137490                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           1200394                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs            153.397543                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle        4287130250                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4055.671895                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.990154                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.990154                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           30                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1           23                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           31                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           25                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::2         2354                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3         1689                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3         1686                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         391573870                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        391573870                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    136255144                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       136255144                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     50884737                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       50884737                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data      1488854                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total      1488854                       # number of LoadLockedReq hits
+system.cpu.dcache.tags.tag_accesses         379628218                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        379628218                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    130278206                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       130278206                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     50877875                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       50877875                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data         3872                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total          3872                       # number of SoftPFReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data      1488856                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total      1488856                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data      1488541                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total      1488541                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     187139881                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        187139881                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    187139881                       # number of overall hits
-system.cpu.dcache.overall_hits::total       187139881                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      1716538                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       1716538                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      3354569                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      3354569                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data           41                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total           41                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data      5071107                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        5071107                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      5071107                       # number of overall misses
-system.cpu.dcache.overall_misses::total       5071107                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  29658271464                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  29658271464                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  73164049214                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  73164049214                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       726000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total       726000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 102822320678                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 102822320678                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 102822320678                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 102822320678                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    137971682                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    137971682                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_hits::cpu.data     181156081                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        181156081                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    181159953                       # number of overall hits
+system.cpu.dcache.overall_hits::total       181159953                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      1715015                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       1715015                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      3361431                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      3361431                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data           76                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total           76                       # number of SoftPFReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data           40                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total           40                       # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data      5076446                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        5076446                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      5076522                       # number of overall misses
+system.cpu.dcache.overall_misses::total       5076522                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  29355008484                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  29355008484                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  73441852684                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  73441852684                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       636000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total       636000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 102796861168                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 102796861168                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 102796861168                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 102796861168                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    131993221                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    131993221                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     54239306                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     54239306                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data      1488895                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total      1488895                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data         3948                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total         3948                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data      1488896                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total      1488896                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data      1488541                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total      1488541                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    192210988                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    192210988                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    192210988                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    192210988                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.012441                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.012441                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.061848                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.061848                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.000028                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.000028                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.026383                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.026383                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.026383                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.026383                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17277.957997                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 17277.957997                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21810.268089                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 21810.268089                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 17707.317073                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 17707.317073                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 20276.109472                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 20276.109472                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 20276.109472                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 20276.109472                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs        17575                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets        53737                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs              1744                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets             663                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    10.077408                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets    81.051282                       # average number of cycles each access was blocked
+system.cpu.dcache.demand_accesses::cpu.data    186232527                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    186232527                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    186236475                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    186236475                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.012993                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.012993                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.061974                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.061974                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.019250                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.019250                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.000027                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.000027                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.027259                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.027259                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.027258                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.027258                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17116.473316                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 17116.473316                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21848.389178                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 21848.389178                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        15900                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        15900                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 20249.769458                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 20249.769458                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 20249.466302                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 20249.466302                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs        21467                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets        55050                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs              2269                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets             661                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     9.460996                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets    83.282905                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      1111057                       # number of writebacks
-system.cpu.dcache.writebacks::total           1111057                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       867776                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       867776                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data      3006223                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total      3006223                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data           41                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total           41                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      3873999                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      3873999                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      3873999                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      3873999                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       848762                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       848762                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       348346                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       348346                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      1197108                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      1197108                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      1197108                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      1197108                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  12264084776                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  12264084776                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  10175822989                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  10175822989                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  22439907765                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  22439907765                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  22439907765                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  22439907765                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.006152                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.006152                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.006422                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.006422                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.006228                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.006228                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.006228                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.006228                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14449.380128                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14449.380128                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29211.826715                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29211.826715                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18745.098826                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 18745.098826                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18745.098826                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 18745.098826                       # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks      1114497                       # number of writebacks
+system.cpu.dcache.writebacks::total           1114497                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       862982                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       862982                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data      3013069                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total      3013069                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data           40                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total           40                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      3876051                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      3876051                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      3876051                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      3876051                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       852033                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       852033                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       348362                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       348362                       # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data           51                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total           51                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      1200395                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      1200395                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      1200446                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      1200446                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  12334131763                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  12334131763                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  10183047234                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  10183047234                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data      2581000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total      2581000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  22517178997                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  22517178997                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  22519759997                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  22519759997                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.006455                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.006455                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.006423                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.006423                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.012918                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.012918                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.006446                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.006446                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.006446                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.006446                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14476.119778                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14476.119778                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29231.222791                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29231.222791                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 50607.843137                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 50607.843137                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18758.141276                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 18758.141276                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18759.494385                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 18759.494385                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt
index 2e9e4306a..5ec8e8e19 100644
--- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt
@@ -1,16 +1,16 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.290499                       # Number of seconds simulated
-sim_ticks                                290498967000                       # Number of ticks simulated
-final_tick                               290498967000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.279362                       # Number of seconds simulated
+sim_ticks                                279362297500                       # Number of ticks simulated
+final_tick                               279362297500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1775828                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2001536                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1018347697                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 304924                       # Number of bytes of host memory used
-host_seconds                                   285.27                       # Real time elapsed on the host
+host_inst_rate                                1833232                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1985632                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1010964168                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 309500                       # Number of bytes of host memory used
+host_seconds                                   276.33                       # Real time elapsed on the host
 sim_insts                                   506581607                       # Number of instructions simulated
-sim_ops                                     570968167                       # Number of ops (including micro ops) simulated
+sim_ops                                     548694828                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst        2066445500                       # Number of bytes read from this memory
@@ -21,21 +21,21 @@ system.physmem.bytes_inst_read::total      2066445500                       # Nu
 system.physmem.bytes_written::cpu.data      216067624                       # Number of bytes written to this memory
 system.physmem.bytes_written::total         216067624                       # Number of bytes written to this memory
 system.physmem.num_reads::cpu.inst          516611375                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data          125228857                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total             641840232                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data          115591527                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total             632202902                       # Number of read requests responded to by this memory
 system.physmem.num_writes::cpu.data          55727847                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total             55727847                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst           7113434933                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data           1455608278                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              8569043211                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst      7113434933                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total         7113434933                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data           743781041                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total              743781041                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst          7113434933                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data          2199389318                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             9312824252                       # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput                   9312824252                       # Throughput (bytes/s)
+system.physmem.bw_read::cpu.inst           7397009255                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data           1513635536                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              8910644791                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst      7397009255                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total         7397009255                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data           773431583                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total              773431583                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst          7397009255                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data          2287067119                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             9684076374                       # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput                   9684076374                       # Throughput (bytes/s)
 system.membus.data_through_bus             2705365825                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
@@ -124,63 +124,65 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  548                       # Number of system calls
-system.cpu.numCycles                        580997935                       # number of cpu cycles simulated
+system.cpu.numCycles                        558724596                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                   506581607                       # Number of instructions committed
-system.cpu.committedOps                     570968167                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses             470727695                       # Number of integer alu accesses
+system.cpu.committedOps                     548694828                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses             448454356                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                     16                       # Number of float alu accesses
 system.cpu.num_func_calls                    19311615                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts     94895872                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                    470727695                       # number of integer instructions
+system.cpu.num_conditional_control_insts     90667196                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                    448454356                       # number of integer instructions
 system.cpu.num_fp_insts                            16                       # number of float instructions
-system.cpu.num_int_register_reads          2482508148                       # number of times the integer registers were read
-system.cpu.num_int_register_writes          646169352                       # number of times the integer registers were written
+system.cpu.num_int_register_reads           749039746                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          290003067                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                   16                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
-system.cpu.num_mem_refs                     182890034                       # number of memory refs
-system.cpu.num_load_insts                   126029555                       # Number of load instructions
+system.cpu.num_cc_register_reads           1634230247                       # number of times the CC registers were read
+system.cpu.num_cc_register_writes           344080722                       # number of times the CC registers were written
+system.cpu.num_mem_refs                     172745235                       # number of memory refs
+system.cpu.num_load_insts                   115884756                       # Number of load instructions
 system.cpu.num_store_insts                   56860479                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                  580997935                       # Number of busy cycles
+system.cpu.num_busy_cycles                  558724596                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                         121548301                       # Number of branches fetched
 system.cpu.op_class::No_OpClass                     0      0.00%      0.00% # Class of executed instruction
-system.cpu.op_class::IntAlu                 387739461     67.91%     67.91% # Class of executed instruction
-system.cpu.op_class::IntMult                   339219      0.06%     67.97% # Class of executed instruction
-system.cpu.op_class::IntDiv                         0      0.00%     67.97% # Class of executed instruction
-system.cpu.op_class::FloatAdd                       0      0.00%     67.97% # Class of executed instruction
-system.cpu.op_class::FloatCmp                       0      0.00%     67.97% # Class of executed instruction
-system.cpu.op_class::FloatCvt                       0      0.00%     67.97% # Class of executed instruction
-system.cpu.op_class::FloatMult                      0      0.00%     67.97% # Class of executed instruction
-system.cpu.op_class::FloatDiv                       0      0.00%     67.97% # Class of executed instruction
-system.cpu.op_class::FloatSqrt                      0      0.00%     67.97% # Class of executed instruction
-system.cpu.op_class::SimdAdd                        0      0.00%     67.97% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc                     0      0.00%     67.97% # Class of executed instruction
-system.cpu.op_class::SimdAlu                        0      0.00%     67.97% # Class of executed instruction
-system.cpu.op_class::SimdCmp                        0      0.00%     67.97% # Class of executed instruction
-system.cpu.op_class::SimdCvt                        0      0.00%     67.97% # Class of executed instruction
-system.cpu.op_class::SimdMisc                       0      0.00%     67.97% # Class of executed instruction
-system.cpu.op_class::SimdMult                       0      0.00%     67.97% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc                    0      0.00%     67.97% # Class of executed instruction
-system.cpu.op_class::SimdShift                      0      0.00%     67.97% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc                   0      0.00%     67.97% # Class of executed instruction
-system.cpu.op_class::SimdSqrt                       0      0.00%     67.97% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd                   0      0.00%     67.97% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu                   0      0.00%     67.97% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp                   0      0.00%     67.97% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt                   0      0.00%     67.97% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv                   0      0.00%     67.97% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc                  3      0.00%     67.97% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult                  0      0.00%     67.97% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc               0      0.00%     67.97% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt                  0      0.00%     67.97% # Class of executed instruction
-system.cpu.op_class::MemRead                126029555     22.07%     90.04% # Class of executed instruction
-system.cpu.op_class::MemWrite                56860479      9.96%    100.00% # Class of executed instruction
+system.cpu.op_class::IntAlu                 375610921     68.46%     68.46% # Class of executed instruction
+system.cpu.op_class::IntMult                   339219      0.06%     68.52% # Class of executed instruction
+system.cpu.op_class::IntDiv                         0      0.00%     68.52% # Class of executed instruction
+system.cpu.op_class::FloatAdd                       0      0.00%     68.52% # Class of executed instruction
+system.cpu.op_class::FloatCmp                       0      0.00%     68.52% # Class of executed instruction
+system.cpu.op_class::FloatCvt                       0      0.00%     68.52% # Class of executed instruction
+system.cpu.op_class::FloatMult                      0      0.00%     68.52% # Class of executed instruction
+system.cpu.op_class::FloatDiv                       0      0.00%     68.52% # Class of executed instruction
+system.cpu.op_class::FloatSqrt                      0      0.00%     68.52% # Class of executed instruction
+system.cpu.op_class::SimdAdd                        0      0.00%     68.52% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc                     0      0.00%     68.52% # Class of executed instruction
+system.cpu.op_class::SimdAlu                        0      0.00%     68.52% # Class of executed instruction
+system.cpu.op_class::SimdCmp                        0      0.00%     68.52% # Class of executed instruction
+system.cpu.op_class::SimdCvt                        0      0.00%     68.52% # Class of executed instruction
+system.cpu.op_class::SimdMisc                       0      0.00%     68.52% # Class of executed instruction
+system.cpu.op_class::SimdMult                       0      0.00%     68.52% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc                    0      0.00%     68.52% # Class of executed instruction
+system.cpu.op_class::SimdShift                      0      0.00%     68.52% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc                   0      0.00%     68.52% # Class of executed instruction
+system.cpu.op_class::SimdSqrt                       0      0.00%     68.52% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd                   0      0.00%     68.52% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu                   0      0.00%     68.52% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp                   0      0.00%     68.52% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt                   0      0.00%     68.52% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv                   0      0.00%     68.52% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc                  3      0.00%     68.52% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult                  0      0.00%     68.52% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc               0      0.00%     68.52% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt                  0      0.00%     68.52% # Class of executed instruction
+system.cpu.op_class::MemRead                115884756     21.12%     89.64% # Class of executed instruction
+system.cpu.op_class::MemWrite                56860479     10.36%    100.00% # Class of executed instruction
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::total                  570968717                       # Class of executed instruction
+system.cpu.op_class::total                  548695378                       # Class of executed instruction
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt
index ef3fc2a0f..b06ae633b 100644
--- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt
@@ -1,16 +1,16 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.717366                       # Number of seconds simulated
-sim_ticks                                717366012000                       # Number of ticks simulated
-final_tick                               717366012000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.707539                       # Number of seconds simulated
+sim_ticks                                707539023000                       # Number of ticks simulated
+final_tick                               707539023000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 879063                       # Simulator instruction rate (inst/s)
-host_op_rate                                   990556                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1248765490                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 313636                       # Number of bytes of host memory used
-host_seconds                                   574.46                       # Real time elapsed on the host
+host_inst_rate                                1172742                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1270027                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1643133313                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 319240                       # Number of bytes of host memory used
+host_seconds                                   430.60                       # Real time elapsed on the host
 sim_insts                                   504986853                       # Number of instructions simulated
-sim_ops                                     569034839                       # Number of ops (including micro ops) simulated
+sim_ops                                     546878104                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst            177280                       # Number of bytes read from this memory
@@ -25,18 +25,18 @@ system.physmem.num_reads::cpu.data             139879                       # Nu
 system.physmem.num_reads::total                142649                       # Number of read requests responded to by this memory
 system.physmem.num_writes::writebacks           95953                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total                95953                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               247126                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             12479342                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                12726469                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          247126                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             247126                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           8560472                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                8560472                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           8560472                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              247126                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            12479342                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               21286941                       # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput                     21286941                       # Throughput (bytes/s)
+system.physmem.bw_read::cpu.inst               250559                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             12652667                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                12903226                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          250559                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             250559                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           8679369                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                8679369                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           8679369                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              250559                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            12652667                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               21582595                       # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput                     21582595                       # Throughput (bytes/s)
 system.membus.trans_dist::ReadReq               41855                       # Transaction distribution
 system.membus.trans_dist::ReadResp              41855                       # Transaction distribution
 system.membus.trans_dist::Writeback             95953                       # Transaction distribution
@@ -48,9 +48,9 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port
 system.membus.tot_pkt_size::total            15270528                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.data_through_bus               15270528                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy          1006226000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy          1018523828                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.1                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         1283841000                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         1290155000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
@@ -138,79 +138,81 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  548                       # Number of system calls
-system.cpu.numCycles                       1434732024                       # number of cpu cycles simulated
+system.cpu.numCycles                       1415078046                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                   504986853                       # Number of instructions committed
-system.cpu.committedOps                     569034839                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses             470727695                       # Number of integer alu accesses
+system.cpu.committedOps                     546878104                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses             448454356                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                     16                       # Number of float alu accesses
 system.cpu.num_func_calls                    19311615                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts     94895872                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                    470727695                       # number of integer instructions
+system.cpu.num_conditional_control_insts     90667196                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                    448454356                       # number of integer instructions
 system.cpu.num_fp_insts                            16                       # number of float instructions
-system.cpu.num_int_register_reads          2861859644                       # number of times the integer registers were read
-system.cpu.num_int_register_writes          646169352                       # number of times the integer registers were written
+system.cpu.num_int_register_reads           748355652                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          290003067                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                   16                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
-system.cpu.num_mem_refs                     182890034                       # number of memory refs
-system.cpu.num_load_insts                   126029555                       # Number of load instructions
+system.cpu.num_cc_register_reads           1984297856                       # number of times the CC registers were read
+system.cpu.num_cc_register_writes           344080722                       # number of times the CC registers were written
+system.cpu.num_mem_refs                     172745235                       # number of memory refs
+system.cpu.num_load_insts                   115884756                       # Number of load instructions
 system.cpu.num_store_insts                   56860479                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                 1434732024                       # Number of busy cycles
+system.cpu.num_busy_cycles                 1415078046                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                         121548301                       # Number of branches fetched
 system.cpu.op_class::No_OpClass                     0      0.00%      0.00% # Class of executed instruction
-system.cpu.op_class::IntAlu                 387739461     67.91%     67.91% # Class of executed instruction
-system.cpu.op_class::IntMult                   339219      0.06%     67.97% # Class of executed instruction
-system.cpu.op_class::IntDiv                         0      0.00%     67.97% # Class of executed instruction
-system.cpu.op_class::FloatAdd                       0      0.00%     67.97% # Class of executed instruction
-system.cpu.op_class::FloatCmp                       0      0.00%     67.97% # Class of executed instruction
-system.cpu.op_class::FloatCvt                       0      0.00%     67.97% # Class of executed instruction
-system.cpu.op_class::FloatMult                      0      0.00%     67.97% # Class of executed instruction
-system.cpu.op_class::FloatDiv                       0      0.00%     67.97% # Class of executed instruction
-system.cpu.op_class::FloatSqrt                      0      0.00%     67.97% # Class of executed instruction
-system.cpu.op_class::SimdAdd                        0      0.00%     67.97% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc                     0      0.00%     67.97% # Class of executed instruction
-system.cpu.op_class::SimdAlu                        0      0.00%     67.97% # Class of executed instruction
-system.cpu.op_class::SimdCmp                        0      0.00%     67.97% # Class of executed instruction
-system.cpu.op_class::SimdCvt                        0      0.00%     67.97% # Class of executed instruction
-system.cpu.op_class::SimdMisc                       0      0.00%     67.97% # Class of executed instruction
-system.cpu.op_class::SimdMult                       0      0.00%     67.97% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc                    0      0.00%     67.97% # Class of executed instruction
-system.cpu.op_class::SimdShift                      0      0.00%     67.97% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc                   0      0.00%     67.97% # Class of executed instruction
-system.cpu.op_class::SimdSqrt                       0      0.00%     67.97% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd                   0      0.00%     67.97% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu                   0      0.00%     67.97% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp                   0      0.00%     67.97% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt                   0      0.00%     67.97% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv                   0      0.00%     67.97% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc                  3      0.00%     67.97% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult                  0      0.00%     67.97% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc               0      0.00%     67.97% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt                  0      0.00%     67.97% # Class of executed instruction
-system.cpu.op_class::MemRead                126029555     22.07%     90.04% # Class of executed instruction
-system.cpu.op_class::MemWrite                56860479      9.96%    100.00% # Class of executed instruction
+system.cpu.op_class::IntAlu                 375610921     68.46%     68.46% # Class of executed instruction
+system.cpu.op_class::IntMult                   339219      0.06%     68.52% # Class of executed instruction
+system.cpu.op_class::IntDiv                         0      0.00%     68.52% # Class of executed instruction
+system.cpu.op_class::FloatAdd                       0      0.00%     68.52% # Class of executed instruction
+system.cpu.op_class::FloatCmp                       0      0.00%     68.52% # Class of executed instruction
+system.cpu.op_class::FloatCvt                       0      0.00%     68.52% # Class of executed instruction
+system.cpu.op_class::FloatMult                      0      0.00%     68.52% # Class of executed instruction
+system.cpu.op_class::FloatDiv                       0      0.00%     68.52% # Class of executed instruction
+system.cpu.op_class::FloatSqrt                      0      0.00%     68.52% # Class of executed instruction
+system.cpu.op_class::SimdAdd                        0      0.00%     68.52% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc                     0      0.00%     68.52% # Class of executed instruction
+system.cpu.op_class::SimdAlu                        0      0.00%     68.52% # Class of executed instruction
+system.cpu.op_class::SimdCmp                        0      0.00%     68.52% # Class of executed instruction
+system.cpu.op_class::SimdCvt                        0      0.00%     68.52% # Class of executed instruction
+system.cpu.op_class::SimdMisc                       0      0.00%     68.52% # Class of executed instruction
+system.cpu.op_class::SimdMult                       0      0.00%     68.52% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc                    0      0.00%     68.52% # Class of executed instruction
+system.cpu.op_class::SimdShift                      0      0.00%     68.52% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc                   0      0.00%     68.52% # Class of executed instruction
+system.cpu.op_class::SimdSqrt                       0      0.00%     68.52% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd                   0      0.00%     68.52% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu                   0      0.00%     68.52% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp                   0      0.00%     68.52% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt                   0      0.00%     68.52% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv                   0      0.00%     68.52% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc                  3      0.00%     68.52% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult                  0      0.00%     68.52% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc               0      0.00%     68.52% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt                  0      0.00%     68.52% # Class of executed instruction
+system.cpu.op_class::MemRead                115884756     21.12%     89.64% # Class of executed instruction
+system.cpu.op_class::MemWrite                56860479     10.36%    100.00% # Class of executed instruction
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::total                  570968717                       # Class of executed instruction
+system.cpu.op_class::total                  548695378                       # Class of executed instruction
 system.cpu.icache.tags.replacements              9788                       # number of replacements
-system.cpu.icache.tags.tagsinuse           982.663229                       # Cycle average of tags in use
+system.cpu.icache.tags.tagsinuse           983.372001                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs           516599855                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs             11521                       # Sample count of references to valid blocks.
 system.cpu.icache.tags.avg_refs          44839.845066                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   982.663229                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.479816                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.479816                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst   983.372001                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.480162                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.480162                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         1733                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           27                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1           24                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2           22                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3          257                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4         1403                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2           24                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3          256                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1402                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.846191                       # Percentage of cache occupancy per task id
 system.cpu.icache.tags.tag_accesses        1033234273                       # Number of tag accesses
 system.cpu.icache.tags.data_accesses       1033234273                       # Number of data accesses
@@ -226,12 +228,12 @@ system.cpu.icache.demand_misses::cpu.inst        11521                       # n
 system.cpu.icache.demand_misses::total          11521                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst        11521                       # number of overall misses
 system.cpu.icache.overall_misses::total         11521                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    266195000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    266195000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    266195000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    266195000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    266195000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    266195000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    266342000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    266342000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    266342000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    266342000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    266342000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    266342000                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst    516611376                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total    516611376                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst    516611376                       # number of demand (read+write) accesses
@@ -244,12 +246,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.000022
 system.cpu.icache.demand_miss_rate::total     0.000022                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000022                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000022                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23105.199201                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 23105.199201                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 23105.199201                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 23105.199201                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 23105.199201                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 23105.199201                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23117.958511                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 23117.958511                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 23117.958511                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 23117.958511                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 23117.958511                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 23117.958511                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -264,38 +266,38 @@ system.cpu.icache.demand_mshr_misses::cpu.inst        11521
 system.cpu.icache.demand_mshr_misses::total        11521                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst        11521                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total        11521                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    243153000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    243153000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    243153000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    243153000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    243153000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    243153000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    243300000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    243300000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    243300000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    243300000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    243300000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    243300000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000022                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000022                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000022                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000022                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000022                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000022                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21105.199201                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21105.199201                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21105.199201                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 21105.199201                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21105.199201                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 21105.199201                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21117.958511                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21117.958511                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21117.958511                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 21117.958511                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21117.958511                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 21117.958511                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements           109895                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        27243.192324                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse        27249.394273                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs            1668833                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs           141072                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs            11.829654                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle     343698539000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 23381.854289                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   287.865470                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  3573.472565                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.713558                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.008785                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.109054                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.831396                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.warmup_cycle     338494923500                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 23386.993586                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   287.904756                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  3574.495930                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.713714                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.008786                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.109085                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.831586                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024        31177                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0           57                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::2          283                       # Occupied blocks per task id
@@ -328,17 +330,17 @@ system.cpu.l2cache.demand_misses::total        142649                       # nu
 system.cpu.l2cache.overall_misses::cpu.inst         2770                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data       139879                       # number of overall misses
 system.cpu.l2cache.overall_misses::total       142649                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    144122000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data   2033729000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total   2177851000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   5241304000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   5241304000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    144122000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data   7275033000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total   7419155000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    144122000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data   7275033000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total   7419155000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    144269000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data   2035873000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total   2180142000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   5245341000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   5245341000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    144269000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data   7281214000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total   7425483000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    144269000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data   7281214000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total   7425483000                       # number of overall miss cycles
 system.cpu.l2cache.ReadReq_accesses::cpu.inst        11521                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::cpu.data       782658                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::total       794179                       # number of ReadReq accesses(hits+misses)
@@ -363,17 +365,17 @@ system.cpu.l2cache.demand_miss_rate::total     0.123995                       #
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.240431                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.122817                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.123995                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52029.602888                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52033.491109                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 52033.233783                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.158740                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.158740                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52029.602888                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52009.472473                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 52009.863371                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52029.602888                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52009.472473                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 52009.863371                       # average overall miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52082.671480                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52088.345913                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 52087.970374                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52040.210727                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52040.210727                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52082.671480                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52053.660664                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 52054.224004                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52082.671480                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52053.660664                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 52054.224004                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -395,17 +397,17 @@ system.cpu.l2cache.demand_mshr_misses::total       142649
 system.cpu.l2cache.overall_mshr_misses::cpu.inst         2770                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data       139879                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total       142649                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    110882000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   1564709000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1675591000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    110883500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   1564721500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1675605000                       # number of ReadReq MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   4031776000                       # number of ReadExReq MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   4031776000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    110882000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   5596485000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total   5707367000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    110882000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   5596485000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total   5707367000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    110883500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   5596497500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total   5707381000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    110883500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   5596497500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total   5707381000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.240431                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.049939                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.052702                       # mshr miss rate for ReadReq accesses
@@ -417,27 +419,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total     0.123995
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.240431                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.122817                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.123995                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40029.602888                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40033.491109                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40033.233783                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40030.144404                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40033.810925                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40033.568271                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000.158740                       # average ReadExReq mshr miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000.158740                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40029.602888                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40009.472473                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40009.863371                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40029.602888                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40009.472473                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40009.863371                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40030.144404                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40009.561836                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40009.961514                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40030.144404                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40009.561836                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40009.961514                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.dcache.tags.replacements           1134822                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4065.297446                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           179817786                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse          4065.318438                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           170180456                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs           1138918                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            157.884752                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle       11885124000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4065.297446                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.992504                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.992504                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.avg_refs            149.422922                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle       11716392000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4065.318438                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.992509                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.992509                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           23                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1           19                       # Occupied blocks per task id
@@ -445,64 +447,72 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2          343
 system.cpu.dcache.tags.age_task_id_blocks_1024::3         3546                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::4          165                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         363052326                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        363052326                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    122957658                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       122957658                       # number of ReadReq hits
+system.cpu.dcache.tags.tag_accesses         343777666                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        343777666                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    113317758                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       113317758                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data     53883046                       # number of WriteReq hits
 system.cpu.dcache.WriteReq_hits::total       53883046                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data         2570                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total          2570                       # number of SoftPFReq hits
 system.cpu.dcache.LoadLockedReq_hits::cpu.data      1488541                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total      1488541                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data      1488541                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total      1488541                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     176840704                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        176840704                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    176840704                       # number of overall hits
-system.cpu.dcache.overall_hits::total       176840704                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       782658                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        782658                       # number of ReadReq misses
+system.cpu.dcache.demand_hits::cpu.data     167200804                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        167200804                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    167203374                       # number of overall hits
+system.cpu.dcache.overall_hits::total       167203374                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       782657                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        782657                       # number of ReadReq misses
 system.cpu.dcache.WriteReq_misses::cpu.data       356260                       # number of WriteReq misses
 system.cpu.dcache.WriteReq_misses::total       356260                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data      1138918                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        1138918                       # number of demand (read+write) misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data            1                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total            1                       # number of SoftPFReq misses
+system.cpu.dcache.demand_misses::cpu.data      1138917                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        1138917                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data      1138918                       # number of overall misses
 system.cpu.dcache.overall_misses::total       1138918                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  11817433000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  11817433000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   8864744000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   8864744000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  20682177000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  20682177000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  20682177000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  20682177000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    123740316                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    123740316                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  11819576500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  11819576500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   8868781000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   8868781000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  20688357500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  20688357500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  20688357500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  20688357500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    114100415                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    114100415                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     54239306                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     54239306                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data         2571                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total         2571                       # number of SoftPFReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::cpu.data      1488541                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::total      1488541                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data      1488541                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total      1488541                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    177979622                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    177979622                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    177979622                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    177979622                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.006325                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.006325                       # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data    168339721                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    168339721                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    168342292                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    168342292                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.006859                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.006859                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.006568                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_miss_rate::total     0.006568                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.006399                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.006399                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.006399                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.006399                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15099.102034                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 15099.102034                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24882.793465                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 24882.793465                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 18159.496118                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 18159.496118                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 18159.496118                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 18159.496118                       # average overall miss latency
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.000389                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.000389                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.006766                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.006766                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.006765                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.006765                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15101.860074                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 15101.860074                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24894.125077                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 24894.125077                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 18164.938709                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 18164.938709                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 18164.922760                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 18164.922760                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -513,40 +523,48 @@ system.cpu.dcache.fast_writes                       0                       # nu
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks      1064905                       # number of writebacks
 system.cpu.dcache.writebacks::total           1064905                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       782658                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       782658                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       782657                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       782657                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data       356260                       # number of WriteReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::total       356260                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      1138918                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      1138918                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data            1                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total            1                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      1138917                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      1138917                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data      1138918                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total      1138918                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  10252117000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  10252117000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   8152224000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   8152224000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  18404341000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  18404341000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  18404341000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  18404341000                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.006325                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.006325                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  10254262500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  10254262500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   8156261000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   8156261000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data        53000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total        53000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  18410523500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  18410523500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  18410576500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  18410576500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.006859                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.006859                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.006568                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.006568                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.006399                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.006399                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.006399                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.006399                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13099.102034                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13099.102034                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22882.793465                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22882.793465                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16159.496118                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 16159.496118                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16159.496118                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 16159.496118                       # average overall mshr miss latency
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.000389                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.000389                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.006766                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.006766                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.006765                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.006765                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13101.860074                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13101.860074                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22894.125077                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22894.125077                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data        53000                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total        53000                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16164.938709                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 16164.938709                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16164.971051                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 16164.971051                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.throughput               197642506                       # Throughput (bytes/s)
+system.cpu.toL2Bus.throughput               200387557                       # Throughput (bytes/s)
 system.cpu.toL2Bus.trans_dist::ReadReq         794179                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadResp        794179                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::Writeback      1064905                       # Transaction distribution
diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt
index bc10d06da..71d3d27a1 100644
--- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt
@@ -1,108 +1,108 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.456433                       # Number of seconds simulated
-sim_ticks                                456433328000                       # Number of ticks simulated
-final_tick                               456433328000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.451995                       # Number of seconds simulated
+sim_ticks                                451994820000                       # Number of ticks simulated
+final_tick                               451994820000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  81383                       # Simulator instruction rate (inst/s)
-host_op_rate                                   150486                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               44923021                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 402504                       # Number of bytes of host memory used
-host_seconds                                 10160.34                       # Real time elapsed on the host
+host_inst_rate                                 140398                       # Simulator instruction rate (inst/s)
+host_op_rate                                   259611                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               76745378                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 366028                       # Number of bytes of host memory used
+host_seconds                                  5889.54                       # Real time elapsed on the host
 sim_insts                                   826877109                       # Number of instructions simulated
 sim_ops                                    1528988701                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            210304                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          24488448                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             24698752                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       210304                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          210304                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     18796480                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          18796480                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               3286                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             382632                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                385918                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          293695                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               293695                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               460755                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             53651753                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                54112508                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          460755                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             460755                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          41181217                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               41181217                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          41181217                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              460755                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            53651753                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               95293725                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        385918                       # Number of read requests accepted
-system.physmem.writeReqs                       293695                       # Number of write requests accepted
-system.physmem.readBursts                      385918                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     293695                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 24677440                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     21312                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  18795136                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  24698752                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               18796480                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      333                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytes_read::cpu.inst            225600                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          24537408                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             24763008                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       225600                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          225600                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     18819200                       # Number of bytes written to this memory
+system.physmem.bytes_written::total          18819200                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               3525                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             383397                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                386922                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          294050                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               294050                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst               499121                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             54286923                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                54786044                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          499121                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             499121                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          41635875                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               41635875                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          41635875                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              499121                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            54286923                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               96421919                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        386922                       # Number of read requests accepted
+system.physmem.writeReqs                       294050                       # Number of write requests accepted
+system.physmem.readBursts                      386922                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     294050                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 24741248                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     21760                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  18817856                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  24763008                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               18819200                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      340                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs         143951                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               24030                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               26462                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               24796                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               24548                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               23428                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               23679                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               24455                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               24282                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               23646                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               23871                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              24701                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              23965                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              23120                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              22899                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              23768                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              23935                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               18533                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               19857                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               18944                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               18929                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               18079                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               18409                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               18979                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               18957                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               18565                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               18141                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              18792                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              17687                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              17335                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              16957                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              17714                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              17796                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs         187441                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               24125                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               26507                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               24686                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               24623                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               23302                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               23746                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               24462                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               24273                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               23635                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               23973                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              24803                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              24077                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              23354                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              22972                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              24056                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              23988                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               18554                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               19852                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               18949                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               18947                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               18033                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               18442                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               18997                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               18979                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               18544                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               18172                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              18845                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              17739                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              17374                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              16976                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              17812                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              17814                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    456433277000                       # Total gap between requests
+system.physmem.totGap                    451994795000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  385918                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  386922                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 293695                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    380841                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      4378                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       326                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                        33                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                         6                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 294050                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    381621                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      4565                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       350                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                        36                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                         7                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                         3                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
@@ -144,43 +144,43 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     6284                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     6678                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    16870                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    17435                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    17552                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    17522                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    17553                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                    17543                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                    17585                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    17598                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    17605                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    17592                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                    17759                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                    17628                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    17575                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                    17808                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                    17489                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                    17442                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                       37                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                       20                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                       15                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                       14                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                       15                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                       12                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                       12                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                        9                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                        9                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                        5                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     6304                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     6696                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                    16856                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                    17449                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                    17548                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    17578                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    17578                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    17585                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    17629                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    17625                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    17630                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    17600                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                    17764                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                    17623                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                    17600                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                    17825                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                    17512                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                    17461                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                       42                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                       30                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                       22                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                       15                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                        6                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                        8                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                        6                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                        6                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                        5                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                        6                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::43                        4                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                        5                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                        2                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                        2                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                        4                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                        6                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                        4                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                        4                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
@@ -193,339 +193,343 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       146599                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      296.532446                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     174.978677                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     323.931077                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          54105     36.91%     36.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        40284     27.48%     64.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        13640      9.30%     73.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         7345      5.01%     78.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         5124      3.50%     82.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         3885      2.65%     84.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         3054      2.08%     86.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         2802      1.91%     88.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        16360     11.16%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         146599                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         17413                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        22.143169                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      209.002812                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023          17400     99.93%     99.93% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-2047            9      0.05%     99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2048-3071            2      0.01%     99.99% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples       147161                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      295.990160                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     174.516116                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     323.823787                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          54586     37.09%     37.09% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        40330     27.41%     64.50% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        13573      9.22%     73.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         7350      4.99%     78.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         5242      3.56%     82.28% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         3782      2.57%     84.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         3105      2.11%     86.96% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         2774      1.89%     88.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        16419     11.16%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         147161                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         17431                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        22.177500                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      209.580978                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023          17417     99.92%     99.92% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-2047            9      0.05%     99.97% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2048-3071            3      0.02%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::3072-4095            1      0.01%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::26624-27647            1      0.01%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           17413                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         17413                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        16.865216                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.791721                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        2.763276                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19           17216     98.87%     98.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23             134      0.77%     99.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              42      0.24%     99.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31               4      0.02%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35               3      0.02%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39               2      0.01%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47               1      0.01%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51               2      0.01%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59               1      0.01%     99.95% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total           17431                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         17431                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.868166                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.795967                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        2.664820                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19           17240     98.90%     98.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23             139      0.80%     99.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27              22      0.13%     99.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31               7      0.04%     99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35               7      0.04%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39               1      0.01%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43               2      0.01%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47               2      0.01%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55               1      0.01%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63               1      0.01%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67               1      0.01%     99.95% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::68-71               1      0.01%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75               1      0.01%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91               1      0.01%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111             1      0.01%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115             2      0.01%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131             1      0.01%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::244-247             1      0.01%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           17413                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     4238739250                       # Total ticks spent queuing
-system.physmem.totMemAccLat               11468458000                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   1927925000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       10993.01                       # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::72-75               2      0.01%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79               1      0.01%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83               1      0.01%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107             1      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127             1      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::248-251             1      0.01%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           17431                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     4215540250                       # Total ticks spent queuing
+system.physmem.totMemAccLat               11463952750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   1932910000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       10904.65                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  29743.01                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          54.07                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                          41.18                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       54.11                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                       41.18                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  29654.65                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          54.74                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                          41.63                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       54.79                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                       41.64                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           0.74                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       0.42                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.32                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.03                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        21.44                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     317362                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    215286                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   82.31                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  73.30                       # Row buffer hit rate for writes
-system.physmem.avgGap                       671607.63                       # Average gap between requests
-system.physmem.pageHitRate                      78.41                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE     317298172500                       # Time in different power states
-system.physmem.memoryStateTime::REF       15241200000                       # Time in different power states
+system.physmem.busUtil                           0.75                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       0.43                       # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite                      0.33                       # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen                         1.02                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        21.68                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     317951                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    215487                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   82.25                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  73.28                       # Row buffer hit rate for writes
+system.physmem.avgGap                       663749.46                       # Average gap between requests
+system.physmem.pageHitRate                      78.37                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE     313004335000                       # Time in different power states
+system.physmem.memoryStateTime::REF       15093000000                       # Time in different power states
 system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT      123890904750                       # Time in different power states
+system.physmem.memoryStateTime::ACT      123894751250                       # Time in different power states
 system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.membus.throughput                     95293725                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq              179074                       # Transaction distribution
-system.membus.trans_dist::ReadResp             179074                       # Transaction distribution
-system.membus.trans_dist::Writeback            293695                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq           143951                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp          143951                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            206844                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           206844                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1353433                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1353433                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1353433                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     43495232                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total     43495232                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total            43495232                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus               43495232                       # Total data (bytes)
+system.membus.throughput                     96421919                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq              179924                       # Transaction distribution
+system.membus.trans_dist::ReadResp             179924                       # Transaction distribution
+system.membus.trans_dist::Writeback            294050                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq           187441                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp          187441                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            206998                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           206998                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1442776                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1442776                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                1442776                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     43582208                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total     43582208                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total            43582208                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus               43582208                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy          3409046000                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               0.7                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         3919297073                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy          3478883000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               0.8                       # Layer utilization (%)
+system.membus.respLayer1.occupancy         4009907869                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.9                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.branchPred.lookups               214172576                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         214172576                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect          10017048                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups            122104582                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits               119561484                       # Number of BTB hits
+system.cpu.branchPred.lookups               231904597                       # Number of BP lookups
+system.cpu.branchPred.condPredicted         231904597                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           9750550                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups            132080719                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits               129337939                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             97.917279                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                25755339                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect            1811393                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             97.923406                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                28018771                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect            1471173                       # Number of incorrect RAS predictions.
 system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
 system.cpu.workload.num_syscalls                  551                       # Number of system calls
-system.cpu.numCycles                        913134033                       # number of cpu cycles simulated
+system.cpu.numCycles                        903989670                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles          172957677                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                     1180093576                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                   214172576                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches          145316823                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     366593738                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                80936667                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles              266990637                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                56859                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles        326654                       # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines                 167839999                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes               2941367                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          877562871                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.500418                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.366055                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles          186228043                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                     1278728730                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   231904597                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches          157356710                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     706545798                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                20232368                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles                       1261                       # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles                97161                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles        819145                       # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles         1413                       # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles           33                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                 180562981                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               2742944                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes                       6                       # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples          903809038                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.631393                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.340645                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                515232459     58.71%     58.71% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 24457756      2.79%     61.50% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 25984112      2.96%     64.46% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 28771124      3.28%     67.74% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                 18396810      2.10%     69.83% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                 23701764      2.70%     72.54% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                 30460841      3.47%     76.01% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                 27790154      3.17%     79.17% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                182767851     20.83%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                493137827     54.56%     54.56% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 34022388      3.76%     58.33% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 33226150      3.68%     62.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 33639943      3.72%     65.72% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                 27288864      3.02%     68.74% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                 27888530      3.09%     71.83% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                 37359921      4.13%     75.96% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                 33838464      3.74%     79.71% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                183406951     20.29%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            877562871                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.234547                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.292355                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                214899100                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             235918889                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 323832333                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              32275243                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles               70637306                       # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts             2159083489                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                    22                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles               70637306                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                235683125                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                99102790                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles          23033                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 334766565                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles             137350052                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts             2116178959                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                 79091                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents               86333515                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents               11675978                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents               34385645                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands          2221828274                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            5358350843                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       3404407883                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups             44462                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total            903809038                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.256535                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.414539                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                127644706                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             443195641                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 240140806                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              82711701                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles               10116184                       # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts             2234020290                       # Number of instructions handled by decode
+system.cpu.rename.SquashCycles               10116184                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                159943307                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles               227345077                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles          31762                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 285830207                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles             220542501                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts             2184066361                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                187446                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents              141210134                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents               24116907                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents               44409056                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands          2289283449                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            5527269614                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       3515022878                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups             52095                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps            1614040854                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                607787420                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts               1530                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts           1409                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                 224967788                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            514990281                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores           202517058                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads         220543258                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores         63035338                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                 2048951027                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded               18335                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                1800520380                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            873481                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined       514890445                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined    886881463                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved          17783                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     877562871                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         2.051728                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.961101                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                675242595                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts               2439                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts           2426                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                 427926698                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            530815140                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           210460978                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads         240742093                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         72507120                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                 2112837832                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded               25371                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                1829122546                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            418643                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       579202583                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined   1008004721                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved          24819                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     903809038                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         2.023793                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        2.068035                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           278621882     31.75%     31.75% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1           139650345     15.91%     47.66% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2           122145227     13.92%     61.58% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3           121221287     13.81%     75.40% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4           101661945     11.58%     86.98% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5            58080162      6.62%     93.60% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6            39790509      4.53%     98.13% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7            14008036      1.60%     99.73% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8             2383478      0.27%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           318787682     35.27%     35.27% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           130796714     14.47%     49.74% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2           120566882     13.34%     63.08% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3           111745228     12.36%     75.45% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            90951236     10.06%     85.51% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            61425555      6.80%     92.31% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6            43081513      4.77%     97.07% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7            19099237      2.11%     99.19% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8             7354991      0.81%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       877562871                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       903809038                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                 8996464     42.62%     42.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%     42.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     42.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     42.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     42.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     42.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     42.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     42.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     42.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     42.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     42.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     42.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     42.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     42.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     42.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     42.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     42.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     42.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     42.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     42.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     42.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     42.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     42.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     42.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     42.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     42.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     42.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     42.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     42.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                9189518     43.53%     86.15% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite               2923144     13.85%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                11301614     42.50%     42.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%     42.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     42.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     42.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     42.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     42.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     42.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     42.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     42.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     42.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     42.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     42.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     42.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     42.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     42.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     42.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     42.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     42.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     42.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     42.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     42.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     42.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     42.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     42.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     42.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     42.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     42.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     42.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     42.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead               12240522     46.03%     88.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               3051129     11.47%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass           2650510      0.15%      0.15% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu            1189351125     66.06%     66.20% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult               365099      0.02%     66.22% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv               3880777      0.22%     66.44% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                  57      0.00%     66.44% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     66.44% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     66.44% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     66.44% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     66.44% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     66.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     66.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     66.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     66.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     66.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     66.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     66.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     66.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     66.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     66.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     66.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     66.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     66.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     66.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     66.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     66.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     66.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     66.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     66.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     66.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     66.44% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            432328086     24.01%     90.45% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite           171944726      9.55%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass           2716130      0.15%      0.15% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu            1212914034     66.31%     66.46% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult               390088      0.02%     66.48% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv               3880828      0.21%     66.69% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                 131      0.00%     66.69% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     66.69% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     66.69% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     66.69% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     66.69% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     66.69% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     66.69% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     66.69% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     66.69% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     66.69% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     66.69% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     66.69% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     66.69% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     66.69% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     66.69% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     66.69% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     66.69% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     66.69% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     66.69% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     66.69% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     66.69% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     66.69% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     66.69% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     66.69% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     66.69% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     66.69% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            435498208     23.81%     90.50% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite           173723127      9.50%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total             1800520380                       # Type of FU issued
-system.cpu.iq.rate                           1.971803                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                    21109126                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.011724                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         4500567659                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes        2564101057                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses   1771520383                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads               18579                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes              42290                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses         4796                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses             1818970082                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                    8914                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads        181603573                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total             1829122546                       # Type of FU issued
+system.cpu.iq.rate                           2.023389                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    26593265                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.014539                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         4589034997                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes        2692332475                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses   1799432823                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads               31041                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes              65517                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses         6732                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses             1852985406                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                   14275                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads        184951720                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads    130889258                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses       280840                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation       356982                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores     53356872                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads    146715422                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses       214760                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation       386957                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores     61300792                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads        17048                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked           593                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads        19364                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked           985                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles               70637306                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                60567761                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles               9830463                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts          2048969362                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            565538                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             514991415                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts            202517058                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts               4133                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                4684109                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents               2987973                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents         356982                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect        5998592                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect      4475905                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts             10474497                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts            1780058647                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             427019742                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts          20461733                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles               10116184                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles               166422776                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles              10091675                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts          2112863203                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            400666                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             530817579                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts            210460978                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts               7795                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                4446284                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents               3513204                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents         386957                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        5751076                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      4630882                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts             10381958                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts            1808023539                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             429432372                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          21099007                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                             0                       # number of nop insts executed
-system.cpu.iew.exec_refs                    595482816                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                169731635                       # Number of branches executed
-system.cpu.iew.exec_stores                  168463074                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.949395                       # Inst execution rate
-system.cpu.iew.wb_sent                     1776808975                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                    1771525179                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                1358454852                       # num instructions producing a value
-system.cpu.iew.wb_consumers                2034017500                       # num instructions consuming a value
+system.cpu.iew.exec_refs                    599547125                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                171962867                       # Number of branches executed
+system.cpu.iew.exec_stores                  170114753                       # Number of stores executed
+system.cpu.iew.exec_rate                     2.000049                       # Inst execution rate
+system.cpu.iew.wb_sent                     1804768043                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                    1799439555                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                1369592486                       # num instructions producing a value
+system.cpu.iew.wb_consumers                2093220611                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.940049                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.667868                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.990553                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.654299                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts       520066569                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts       584100413                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls             552                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts          10054119                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    806925565                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.894832                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.501115                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts           9836004                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    824637269                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.854135                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.503267                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    332217224     41.17%     41.17% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1    181470930     22.49%     63.66% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     58010021      7.19%     70.85% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     87470883     10.84%     81.69% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     24768584      3.07%     84.76% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5     27525249      3.41%     88.17% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      9963607      1.23%     89.40% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7     11389679      1.41%     90.82% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     74109388      9.18%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    355822450     43.15%     43.15% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    175430054     21.27%     64.42% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     57247046      6.94%     71.36% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     86422444     10.48%     81.84% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     27139119      3.29%     85.14% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5     27033560      3.28%     88.41% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      9709039      1.18%     89.59% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      8849743      1.07%     90.66% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     76983814      9.34%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    806925565                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    824637269                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts            826877109                       # Number of instructions committed
 system.cpu.commit.committedOps             1528988701                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -571,245 +575,244 @@ system.cpu.commit.op_class_0::MemWrite      149160186      9.76%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total        1528988701                       # Class of committed instruction
-system.cpu.commit.bw_lim_events              74109388                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events              76983814                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                   2781871447                       # The number of ROB reads
-system.cpu.rob.rob_writes                  4168935238                       # The number of ROB writes
-system.cpu.timesIdled                         4004498                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                        35571162                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads                   2860742569                       # The number of ROB reads
+system.cpu.rob.rob_writes                  4305535749                       # The number of ROB writes
+system.cpu.timesIdled                            2688                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                          180632                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                   826877109                       # Number of Instructions Simulated
 system.cpu.committedOps                    1528988701                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               1.104316                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         1.104316                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.905537                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.905537                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               2740022491                       # number of integer regfile reads
-system.cpu.int_regfile_writes              1443498634                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                      4829                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                      113                       # number of floating regfile writes
-system.cpu.cc_regfile_reads                 599382503                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                407768692                       # number of cc regfile writes
-system.cpu.misc_regfile_reads               978269285                       # number of misc regfile reads
+system.cpu.cpi                               1.093258                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         1.093258                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.914698                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.914698                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               2763635866                       # number of integer regfile reads
+system.cpu.int_regfile_writes              1467536960                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                      6799                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                      207                       # number of floating regfile writes
+system.cpu.cc_regfile_reads                 600939716                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                409698109                       # number of cc regfile writes
+system.cpu.misc_regfile_reads               991748256                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
-system.cpu.toL2Bus.throughput               703796459                       # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq        1916652                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       1916650                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      2331152                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq       145500                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp       145500                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       771513                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       771513                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       160475                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      7692392                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           7852867                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       475520                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    311441408                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total      311916928                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus         311916928                       # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus      9319232                       # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy     4920349397                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.throughput               717782102                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq        1964869                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       1964868                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback      2332907                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq       189308                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp       189308                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       771503                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       771503                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       206675                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      7788165                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           7994840                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       551936                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    311758592                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total      312310528                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus         312310528                       # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus     12123264                       # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy     4978085168                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          1.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy     230044243                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy     297561992                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    3958184582                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    3985022632                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.9                       # Layer utilization (%)
-system.cpu.icache.tags.replacements              5899                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1053.974853                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           167683081                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs              7506                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          22339.872236                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements              6996                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1078.278361                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           180359326                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs              8602                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          20967.138572                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1053.974853                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.514636                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.514636                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024         1607                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           65                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1            7                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2           63                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3          269                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4         1203                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.784668                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         335833041                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        335833041                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    167684909                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       167684909                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     167684909                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        167684909                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    167684909                       # number of overall hits
-system.cpu.icache.overall_hits::total       167684909                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst       155090                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total        155090                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst       155090                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total         155090                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst       155090                       # number of overall misses
-system.cpu.icache.overall_misses::total        155090                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    984545992                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    984545992                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    984545992                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    984545992                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    984545992                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    984545992                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    167839999                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    167839999                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    167839999                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    167839999                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    167839999                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    167839999                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000924                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000924                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000924                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000924                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000924                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000924                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst  6348.223561                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total  6348.223561                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst  6348.223561                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total  6348.223561                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst  6348.223561                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total  6348.223561                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs          296                       # number of cycles access was blocked
+system.cpu.icache.tags.occ_blocks::cpu.inst  1078.278361                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.526503                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.526503                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1606                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           68                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1            8                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2           56                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3          301                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1173                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.784180                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses         361324012                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        361324012                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    180362453                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       180362453                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     180362453                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        180362453                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    180362453                       # number of overall hits
+system.cpu.icache.overall_hits::total       180362453                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst       200528                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total        200528                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst       200528                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total         200528                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst       200528                       # number of overall misses
+system.cpu.icache.overall_misses::total        200528                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst   1221704738                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total   1221704738                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst   1221704738                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total   1221704738                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst   1221704738                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total   1221704738                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    180562981                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    180562981                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    180562981                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    180562981                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    180562981                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    180562981                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.001111                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.001111                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.001111                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.001111                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.001111                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.001111                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst  6092.439649                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total  6092.439649                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst  6092.439649                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total  6092.439649                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst  6092.439649                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total  6092.439649                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs          899                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                 5                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                14                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    59.200000                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    64.214286                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst         2045                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total         2045                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst         2045                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total         2045                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst         2045                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total         2045                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst       153045                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total       153045                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst       153045                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total       153045                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst       153045                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total       153045                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    588350757                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    588350757                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    588350757                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    588350757                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    588350757                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    588350757                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000912                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000912                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000912                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.000912                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000912                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.000912                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  3844.299108                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total  3844.299108                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  3844.299108                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total  3844.299108                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  3844.299108                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total  3844.299108                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         2477                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total         2477                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst         2477                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total         2477                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst         2477                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total         2477                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst       198051                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total       198051                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst       198051                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total       198051                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst       198051                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total       198051                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    720791257                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    720791257                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    720791257                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    720791257                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    720791257                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    720791257                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.001097                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.001097                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.001097                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.001097                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.001097                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.001097                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  3639.422457                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total  3639.422457                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  3639.422457                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total  3639.422457                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  3639.422457                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total  3639.422457                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements           353238                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        29693.365830                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            3699378                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           385610                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             9.593574                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle     198448245500                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 21154.679974                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   231.567464                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  8307.118393                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.645590                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.007067                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.253513                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.906170                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        32372                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           85                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1            2                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          250                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3        11726                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        20309                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.987915                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         41312633                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        41312633                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst         4144                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data      1587819                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        1591963                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks      2331152                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      2331152                       # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data         1571                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total         1571                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       564647                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       564647                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst         4144                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      2152466                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         2156610                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst         4144                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      2152466                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        2156610                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst         3288                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data       175788                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total       179076                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data       143929                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total       143929                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       206866                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       206866                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         3288                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       382654                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        385942                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         3288                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       382654                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       385942                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    243230500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data  12860278959                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total  13103509459                       # number of ReadReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data      7140193                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total      7140193                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  14872236978                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total  14872236978                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    243230500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  27732515937                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  27975746437                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    243230500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  27732515937                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  27975746437                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst         7432                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data      1763607                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total      1771039                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks      2331152                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total      2331152                       # number of Writeback accesses(hits+misses)
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-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73157.888815                       # average ReadReq miss latency
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+system.cpu.l2cache.tags.tagsinuse        29686.826365                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            3703753                       # Total number of references to valid blocks.
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+system.cpu.l2cache.tags.avg_refs             9.580348                       # Average number of references to valid blocks.
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+system.cpu.l2cache.overall_avg_miss_latency::total 72409.335118                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -818,182 +821,182 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
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-system.cpu.l2cache.writebacks::total           293696                       # number of writebacks
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 system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            1                       # number of ReadReq MSHR hits
 system.cpu.l2cache.ReadReq_mshr_hits::total            1                       # number of ReadReq MSHR hits
 system.cpu.l2cache.demand_mshr_hits::cpu.inst            1                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.demand_mshr_hits::total            1                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.overall_mshr_hits::cpu.inst            1                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::total            1                       # number of overall MSHR hits
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+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total   1890449014                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  12223591032                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  12223591032                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    215844500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  22877151744                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  23092996244                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    215844500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  22877151744                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  23092996244                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.408812                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.099840                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.101341                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.989969                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.989969                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.268346                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.268346                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.408812                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.151056                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.151929                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.408812                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.151056                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.151929                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61215.116279                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60394.677475                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60410.755659                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10087.290440                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10087.290440                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59042.607506                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59042.607506                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61215.116279                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59664.636071                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59678.764311                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61215.116279                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59664.636071                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59678.764311                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements           2531024                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4088.627952                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           389841381                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           2535120                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            153.776303                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle        1681469250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4088.627952                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.998200                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.998200                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements           2534225                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4088.724937                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           389006458                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           2538321                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs            153.253453                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle        1658510250                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4088.724937                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.998224                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.998224                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           25                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1           20                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2          738                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3         3313                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           27                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           19                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          803                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3         3247                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         788808720                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        788808720                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    241135682                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       241135682                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    148226318                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      148226318                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data     389362000                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        389362000                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    389362000                       # number of overall hits
-system.cpu.dcache.overall_hits::total       389362000                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      2840916                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       2840916                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       933884                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       933884                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data      3774800                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        3774800                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      3774800                       # number of overall misses
-system.cpu.dcache.overall_misses::total       3774800                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  57099614849                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  57099614849                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  26803520330                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  26803520330                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  83903135179                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  83903135179                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  83903135179                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  83903135179                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    243976598                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    243976598                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.tags.tag_accesses         787132235                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        787132235                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    240408250                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       240408250                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    148181290                       # number of WriteReq hits
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+system.cpu.dcache.demand_hits::cpu.data     388589540                       # number of demand (read+write) hits
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+system.cpu.dcache.ReadReq_misses::cpu.data      2728505                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       2728505                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       978912                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       978912                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data      3707417                       # number of demand (read+write) misses
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+system.cpu.dcache.overall_misses::cpu.data      3707417                       # number of overall misses
+system.cpu.dcache.overall_misses::total       3707417                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  55514293617                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  55514293617                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  27913016377                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  27913016377                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  83427309994                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  83427309994                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  83427309994                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  83427309994                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    243136755                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    243136755                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data    149160202                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total    149160202                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    393136800                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    393136800                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    393136800                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    393136800                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.011644                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.011644                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.006261                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.006261                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.009602                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.009602                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.009602                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.009602                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20099.015546                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 20099.015546                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28701.123833                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 28701.123833                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 22227.173673                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 22227.173673                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 22227.173673                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 22227.173673                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs         6549                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs               751                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     8.720373                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.demand_accesses::cpu.data    392296957                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    392296957                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    392296957                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    392296957                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.011222                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.011222                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.006563                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.006563                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.009451                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.009451                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.009451                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.009451                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20346.047970                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 20346.047970                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28514.326494                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 28514.326494                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 22502.812603                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 22502.812603                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 22502.812603                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 22502.812603                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs         9167                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets          150                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs              1009                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               4                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     9.085233                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets    37.500000                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      2331152                       # number of writebacks
-system.cpu.dcache.writebacks::total           2331152                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data      1077049                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total      1077049                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data        17132                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total        17132                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      1094181                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      1094181                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      1094181                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      1094181                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1763867                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      1763867                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       916752                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       916752                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      2680619                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      2680619                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      2680619                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      2680619                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  30539375250                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  30539375250                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  24659789417                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  24659789417                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  55199164667                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  55199164667                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  55199164667                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  55199164667                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.007230                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.007230                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.006146                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.006146                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.006819                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.006819                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.006819                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.006819                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17313.876415                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17313.876415                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26899.084395                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26899.084395                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20591.947109                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 20591.947109                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20591.947109                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 20591.947109                       # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks      2332907                       # number of writebacks
+system.cpu.dcache.writebacks::total           2332907                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       961470                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       961470                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data        18318                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total        18318                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data       979788                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       979788                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data       979788                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       979788                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1767035                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      1767035                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       960594                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       960594                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      2727629                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      2727629                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      2727629                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      2727629                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  30608716000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  30608716000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  25669918867                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  25669918867                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  56278634867                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  56278634867                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  56278634867                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  56278634867                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.007268                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.007268                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.006440                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.006440                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.006953                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.006953                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.006953                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.006953                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17322.076812                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17322.076812                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26722.963986                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26722.963986                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20632.804119                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 20632.804119                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20632.804119                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 20632.804119                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt
index 0b41505d8..2ad80aa5a 100644
--- a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt
+++ b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.219644                       # Number of seconds simulated
-sim_ticks                                219644167500                       # Number of ticks simulated
-final_tick                               219644167500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.220941                       # Number of seconds simulated
+sim_ticks                                220941341500                       # Number of ticks simulated
+final_tick                               220941341500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 184210                       # Simulator instruction rate (inst/s)
-host_op_rate                                   184210                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              101490439                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 247040                       # Number of bytes of host memory used
-host_seconds                                  2164.19                       # Real time elapsed on the host
+host_inst_rate                                 303038                       # Simulator instruction rate (inst/s)
+host_op_rate                                   303038                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              167944827                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 273400                       # Number of bytes of host memory used
+host_seconds                                  1315.56                       # Real time elapsed on the host
 sim_insts                                   398664665                       # Number of instructions simulated
 sim_ops                                     398664665                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -19,12 +19,12 @@ system.physmem.bytes_inst_read::cpu.inst       249408                       # Nu
 system.physmem.bytes_inst_read::total          249408                       # Number of instructions bytes read from this memory
 system.physmem.num_reads::cpu.inst               7875                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                  7875                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst              2294620                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 2294620                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         1135509                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            1135509                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             2294620                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                2294620                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst              2281148                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 2281148                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         1128843                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            1128843                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             2281148                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                2281148                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.readReqs                          7875                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
 system.physmem.readBursts                        7875                       # Number of DRAM read bursts, including those serviced by the write queue
@@ -71,7 +71,7 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    219644086000                       # Total gap between requests
+system.physmem.totGap                    220941260000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
@@ -86,8 +86,8 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                      6822                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       970                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                      6820                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       972                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::2                        83                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
@@ -182,29 +182,29 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples         1515                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      331.828383                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     199.155331                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     333.926802                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127            511     33.73%     33.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255          341     22.51%     56.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383          189     12.48%     68.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511          107      7.06%     75.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639           50      3.30%     79.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767           60      3.96%     83.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895           36      2.38%     85.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023           30      1.98%     87.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151          191     12.61%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total           1515                       # Bytes accessed per row activation
-system.physmem.totQLat                       51832750                       # Total ticks spent queuing
-system.physmem.totMemAccLat                 199489000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.bytesPerActivate::samples         1518                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      330.160738                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     197.894458                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     332.998951                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127            519     34.19%     34.19% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255          336     22.13%     56.32% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383          186     12.25%     68.58% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511          110      7.25%     75.82% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639           56      3.69%     79.51% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767           56      3.69%     83.20% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895           37      2.44%     85.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023           28      1.84%     87.48% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151          190     12.52%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total           1518                       # Bytes accessed per row activation
+system.physmem.totQLat                       52730250                       # Total ticks spent queuing
+system.physmem.totMemAccLat                 200386500                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                     39375000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        6581.94                       # Average queueing delay per DRAM burst
+system.physmem.avgQLat                        6695.90                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  25331.94                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           2.29                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  25445.90                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           2.28                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        2.29                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        2.28                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.02                       # Data bus utilization in percentage
@@ -212,18 +212,18 @@ system.physmem.busUtilRead                       0.02                       # Da
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                       6354                       # Number of row buffer hits during reads
+system.physmem.readRowHits                       6348                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   80.69                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   80.61                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                     27891312.51                       # Average gap between requests
-system.physmem.pageHitRate                      80.69                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE     210595847500                       # Time in different power states
-system.physmem.memoryStateTime::REF        7334340000                       # Time in different power states
+system.physmem.avgGap                     28056033.02                       # Average gap between requests
+system.physmem.pageHitRate                      80.61                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE     211835989750                       # Time in different power states
+system.physmem.memoryStateTime::REF        7377500000                       # Time in different power states
 system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT        1712418250                       # Time in different power states
+system.physmem.memoryStateTime::ACT        1721627750                       # Time in different power states
 system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.membus.throughput                      2294620                       # Throughput (bytes/s)
+system.membus.throughput                      2281148                       # Throughput (bytes/s)
 system.membus.trans_dist::ReadReq                4737                       # Transaction distribution
 system.membus.trans_dist::ReadResp               4737                       # Transaction distribution
 system.membus.trans_dist::ReadExReq              3138                       # Transaction distribution
@@ -234,40 +234,40 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port
 system.membus.tot_pkt_size::total              504000                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.data_through_bus                 504000                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy             9401500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy             9511500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           73916250                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy           74010500                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.branchPred.lookups                46223200                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          26710359                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           1014875                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             25598344                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                21333887                       # Number of BTB hits
+system.cpu.branchPred.lookups                46221231                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          26710053                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           1012987                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             25408308                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                21330923                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             83.340887                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 8326899                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.BTBHitPct             83.952552                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 8326726                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect                323                       # Number of incorrect RAS predictions.
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                     95595217                       # DTB read hits
-system.cpu.dtb.read_misses                        114                       # DTB read misses
+system.cpu.dtb.read_hits                     95595776                       # DTB read hits
+system.cpu.dtb.read_misses                        118                       # DTB read misses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                 95595331                       # DTB read accesses
-system.cpu.dtb.write_hits                    73605959                       # DTB write hits
+system.cpu.dtb.read_accesses                 95595894                       # DTB read accesses
+system.cpu.dtb.write_hits                    73604420                       # DTB write hits
 system.cpu.dtb.write_misses                       858                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses                73606817                       # DTB write accesses
-system.cpu.dtb.data_hits                    169201176                       # DTB hits
-system.cpu.dtb.data_misses                        972                       # DTB misses
+system.cpu.dtb.write_accesses                73605278                       # DTB write accesses
+system.cpu.dtb.data_hits                    169200196                       # DTB hits
+system.cpu.dtb.data_misses                        976                       # DTB misses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                169202148                       # DTB accesses
-system.cpu.itb.fetch_hits                    98054052                       # ITB hits
-system.cpu.itb.fetch_misses                      1240                       # ITB misses
+system.cpu.dtb.data_accesses                169201172                       # DTB accesses
+system.cpu.itb.fetch_hits                    98242303                       # ITB hits
+system.cpu.itb.fetch_misses                      1225                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                98055292                       # ITB accesses
+system.cpu.itb.fetch_accesses                98243528                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -281,70 +281,70 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                  215                       # Number of system calls
-system.cpu.numCycles                        439288335                       # number of cpu cycles simulated
+system.cpu.numCycles                        441882683                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                   398664665                       # Number of instructions committed
 system.cpu.committedOps                     398664665                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                       4458110                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps                       4446127                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                               1.101899                       # CPI: cycles per instruction
-system.cpu.ipc                               0.907524                       # IPC: instructions per cycle
-system.cpu.tickCycles                       435056382                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                         4231953                       # Total number of cycles that the object has spent stopped
+system.cpu.cpi                               1.108407                       # CPI: cycles per instruction
+system.cpu.ipc                               0.902196                       # IPC: instructions per cycle
+system.cpu.tickCycles                       437732113                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                         4150570                       # Total number of cycles that the object has spent stopped
 system.cpu.icache.tags.replacements              3195                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1919.689869                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            98048879                       # Total number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse          1919.708567                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            98237130                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs              5173                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          18953.968490                       # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs          18990.359559                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1919.689869                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.937349                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.937349                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst  1919.708567                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.937358                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.937358                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         1978                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           98                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          200                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          100                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          198                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::2          398                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::4         1282                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.965820                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         196113277                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        196113277                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     98048879                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        98048879                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      98048879                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         98048879                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     98048879                       # number of overall hits
-system.cpu.icache.overall_hits::total        98048879                       # number of overall hits
+system.cpu.icache.tags.tag_accesses         196489779                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        196489779                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     98237130                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        98237130                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      98237130                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         98237130                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     98237130                       # number of overall hits
+system.cpu.icache.overall_hits::total        98237130                       # number of overall hits
 system.cpu.icache.ReadReq_misses::cpu.inst         5173                       # number of ReadReq misses
 system.cpu.icache.ReadReq_misses::total          5173                       # number of ReadReq misses
 system.cpu.icache.demand_misses::cpu.inst         5173                       # number of demand (read+write) misses
 system.cpu.icache.demand_misses::total           5173                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst         5173                       # number of overall misses
 system.cpu.icache.overall_misses::total          5173                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    293884750                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    293884750                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    293884750                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    293884750                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    293884750                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    293884750                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     98054052                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     98054052                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     98054052                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     98054052                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     98054052                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     98054052                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    293554750                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    293554750                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    293554750                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    293554750                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    293554750                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    293554750                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     98242303                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     98242303                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     98242303                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     98242303                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     98242303                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     98242303                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000053                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000053                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000053                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000053                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000053                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000053                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56811.279722                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 56811.279722                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 56811.279722                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 56811.279722                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 56811.279722                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 56811.279722                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56747.486951                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 56747.486951                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 56747.486951                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 56747.486951                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 56747.486951                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 56747.486951                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -359,26 +359,26 @@ system.cpu.icache.demand_mshr_misses::cpu.inst         5173
 system.cpu.icache.demand_mshr_misses::total         5173                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst         5173                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total         5173                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    281914250                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    281914250                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    281914250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    281914250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    281914250                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    281914250                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    281585250                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    281585250                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    281585250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    281585250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    281585250                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    281585250                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000053                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000053                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000053                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000053                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000053                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000053                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54497.245312                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54497.245312                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54497.245312                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 54497.245312                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54497.245312                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 54497.245312                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54433.645853                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54433.645853                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54433.645853                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 54433.645853                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54433.645853                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 54433.645853                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.throughput                 2911473                       # Throughput (bytes/s)
+system.cpu.toL2Bus.throughput                 2894379                       # Throughput (bytes/s)
 system.cpu.toL2Bus.trans_dist::ReadReq           6139                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadResp          6139                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::Writeback          654                       # Transaction distribution
@@ -394,24 +394,24 @@ system.cpu.toL2Bus.data_through_bus            639488                       # To
 system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
 system.cpu.toL2Bus.reqLayer0.occupancy        5650000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy       8571750                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy       8571250                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy       6975500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy       6974750                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse         4427.544414                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse         4427.627395                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs               1491                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs             5274                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs             0.282708                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks   373.069820                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  4054.474595                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.011385                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.123733                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.135118                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::writebacks   373.083919                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  4054.543476                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.011386                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.123735                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.135120                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024         5274                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           93                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          125                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           94                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          124                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::2          612                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::4         4444                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.160950                       # Percentage of cache occupancy per task id
@@ -435,14 +435,14 @@ system.cpu.l2cache.demand_misses::cpu.inst         7875                       #
 system.cpu.l2cache.demand_misses::total          7875                       # number of demand (read+write) misses
 system.cpu.l2cache.overall_misses::cpu.inst         7875                       # number of overall misses
 system.cpu.l2cache.overall_misses::total         7875                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    325631750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total    325631750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst    212036500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total    212036500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    537668250                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total    537668250                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    537668250                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total    537668250                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    325767500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total    325767500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst    212904500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total    212904500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    538672000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total    538672000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    538672000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    538672000                       # number of overall miss cycles
 system.cpu.l2cache.ReadReq_accesses::cpu.inst         6139                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::total         6139                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.Writeback_accesses::writebacks          654                       # number of Writeback accesses(hits+misses)
@@ -461,14 +461,14 @@ system.cpu.l2cache.demand_miss_rate::cpu.inst     0.843328
 system.cpu.l2cache.demand_miss_rate::total     0.843328                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.843328                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.843328                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68742.189149                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 68742.189149                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 67570.586361                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67570.586361                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68275.333333                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 68275.333333                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68275.333333                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 68275.333333                       # average overall miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68770.846527                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 68770.846527                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 67847.195666                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67847.195666                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68402.793651                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 68402.793651                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68402.793651                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 68402.793651                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -485,14 +485,14 @@ system.cpu.l2cache.demand_mshr_misses::cpu.inst         7875
 system.cpu.l2cache.demand_mshr_misses::total         7875                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.inst         7875                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total         7875                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    266250750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total    266250750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst    172336000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    172336000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    438586750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    438586750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    438586750                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    438586750                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    266387000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total    266387000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst    173110500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    173110500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    439497500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    439497500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    439497500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    439497500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.771624                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.771624                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst     0.980932                       # mshr miss rate for ReadExReq accesses
@@ -501,65 +501,65 @@ system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.843328
 system.cpu.l2cache.demand_mshr_miss_rate::total     0.843328                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.843328                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.843328                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56206.618113                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56206.618113                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 54919.056724                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54919.056724                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55693.555556                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55693.555556                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55693.555556                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55693.555556                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56235.381043                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56235.381043                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 55165.869981                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55165.869981                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55809.206349                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55809.206349                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55809.206349                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55809.206349                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.dcache.tags.replacements               771                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          3291.682067                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           168006905                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse          3291.748201                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           168007181                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs              4165                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs          40337.792317                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs          40337.858583                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.inst  3291.682067                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.inst     0.803633                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.803633                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.inst  3291.748201                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.inst     0.803649                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.803649                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         3394                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           37                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1           25                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           38                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           24                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::2          216                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::4         3114                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024     0.828613                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         336032209                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        336032209                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.inst     94492115                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        94492115                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.inst     73514790                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       73514790                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.inst     168006905                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        168006905                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.inst    168006905                       # number of overall hits
-system.cpu.dcache.overall_hits::total       168006905                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.inst         1177                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total          1177                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.inst         5940                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total         5940                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.inst         7117                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total           7117                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.inst         7117                       # number of overall misses
-system.cpu.dcache.overall_misses::total          7117                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.inst     80734750                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     80734750                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.inst    392862000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total    392862000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.inst    473596750                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total    473596750                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.inst    473596750                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total    473596750                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.inst     94493292                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     94493292                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.tags.tag_accesses         336032765                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        336032765                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.inst     94492394                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        94492394                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.inst     73514787                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       73514787                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.inst     168007181                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        168007181                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.inst    168007181                       # number of overall hits
+system.cpu.dcache.overall_hits::total       168007181                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.inst         1176                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total          1176                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.inst         5943                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total         5943                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.inst         7119                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total           7119                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.inst         7119                       # number of overall misses
+system.cpu.dcache.overall_misses::total          7119                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.inst     81035500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     81035500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.inst    393767750                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total    393767750                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.inst    474803250                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total    474803250                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.inst    474803250                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total    474803250                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.inst     94493570                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     94493570                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.inst     73520730                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     73520730                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.inst    168014022                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    168014022                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.inst    168014022                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    168014022                       # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.inst    168014300                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    168014300                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.inst    168014300                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    168014300                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.inst     0.000012                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.000012                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.inst     0.000081                       # miss rate for WriteReq accesses
@@ -568,14 +568,14 @@ system.cpu.dcache.demand_miss_rate::cpu.inst     0.000042
 system.cpu.dcache.demand_miss_rate::total     0.000042                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.inst     0.000042                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.000042                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 68593.670348                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 68593.670348                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 66138.383838                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 66138.383838                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66544.435858                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 66544.435858                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66544.435858                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 66544.435858                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 68907.738095                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 68907.738095                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 66257.403668                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 66257.403668                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66695.217025                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 66695.217025                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66695.217025                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 66695.217025                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -588,28 +588,28 @@ system.cpu.dcache.writebacks::writebacks          654                       # nu
 system.cpu.dcache.writebacks::total               654                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_hits::cpu.inst          208                       # number of ReadReq MSHR hits
 system.cpu.dcache.ReadReq_mshr_hits::total          208                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.inst         2744                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total         2744                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.inst         2952                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total         2952                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.inst         2952                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total         2952                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.inst          969                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total          969                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.inst         3196                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total         3196                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_hits::cpu.inst         2746                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total         2746                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.inst         2954                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total         2954                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.inst         2954                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total         2954                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.inst          968                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total          968                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.inst         3197                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total         3197                       # number of WriteReq MSHR misses
 system.cpu.dcache.demand_mshr_misses::cpu.inst         4165                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.demand_mshr_misses::total         4165                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.inst         4165                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total         4165                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst     64078250                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total     64078250                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst    215682250                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total    215682250                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.inst    279760500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total    279760500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.inst    279760500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total    279760500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst     64480250                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     64480250                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst    216613000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total    216613000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.inst    281093250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total    281093250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.inst    281093250                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total    281093250                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst     0.000010                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000010                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst     0.000043                       # mshr miss rate for WriteReq accesses
@@ -618,14 +618,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.inst     0.000025
 system.cpu.dcache.demand_mshr_miss_rate::total     0.000025                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.inst     0.000025                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.000025                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 66128.224974                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66128.224974                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 67485.059449                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67485.059449                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 67169.387755                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 67169.387755                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 67169.387755                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 67169.387755                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 66611.828512                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66611.828512                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 67755.082890                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67755.082890                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 67489.375750                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 67489.375750                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 67489.375750                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 67489.375750                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt
index 35136e25d..0f0c79704 100644
--- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,62 +1,62 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.072880                       # Number of seconds simulated
-sim_ticks                                 72880000500                       # Number of ticks simulated
-final_tick                                72880000500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.069652                       # Number of seconds simulated
+sim_ticks                                 69651704000                       # Number of ticks simulated
+final_tick                                69651704000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 219272                       # Simulator instruction rate (inst/s)
-host_op_rate                                   219272                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               42549566                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 229100                       # Number of bytes of host memory used
-host_seconds                                  1712.83                       # Real time elapsed on the host
+host_inst_rate                                 185769                       # Simulator instruction rate (inst/s)
+host_op_rate                                   185769                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               34451530                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 243176                       # Number of bytes of host memory used
+host_seconds                                  2021.73                       # Real time elapsed on the host
 sim_insts                                   375574808                       # Number of instructions simulated
 sim_ops                                     375574808                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            221696                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data            255296                       # Number of bytes read from this memory
-system.physmem.bytes_read::total               476992                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       221696                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          221696                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst               3464                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data               3989                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                  7453                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst              3041932                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              3502964                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 6544896                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         3041932                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            3041932                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             3041932                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             3502964                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                6544896                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                          7453                       # Number of read requests accepted
+system.physmem.bytes_read::cpu.inst            221568                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data            255744                       # Number of bytes read from this memory
+system.physmem.bytes_read::total               477312                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       221568                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          221568                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst               3462                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data               3996                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                  7458                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst              3181085                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              3671755                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 6852840                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         3181085                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            3181085                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             3181085                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             3671755                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                6852840                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                          7458                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
-system.physmem.readBursts                        7453                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                        7458                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                   476992                       # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM                   477312                       # Total number of bytes read from DRAM
 system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
 system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                    476992                       # Total read bytes from the system interface side
+system.physmem.bytesReadSys                    477312                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
 system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                 527                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                 653                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                 448                       # Per bank write bursts
+system.physmem.perBankRdBursts::0                 528                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                 655                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                 455                       # Per bank write bursts
 system.physmem.perBankRdBursts::3                 602                       # Per bank write bursts
-system.physmem.perBankRdBursts::4                 447                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                 455                       # Per bank write bursts
+system.physmem.perBankRdBursts::4                 446                       # Per bank write bursts
+system.physmem.perBankRdBursts::5                 454                       # Per bank write bursts
 system.physmem.perBankRdBursts::6                 515                       # Per bank write bursts
 system.physmem.perBankRdBursts::7                 524                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                 438                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                 405                       # Per bank write bursts
-system.physmem.perBankRdBursts::10                337                       # Per bank write bursts
-system.physmem.perBankRdBursts::11                306                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                 439                       # Per bank write bursts
+system.physmem.perBankRdBursts::9                 406                       # Per bank write bursts
+system.physmem.perBankRdBursts::10                340                       # Per bank write bursts
+system.physmem.perBankRdBursts::11                305                       # Per bank write bursts
 system.physmem.perBankRdBursts::12                414                       # Per bank write bursts
-system.physmem.perBankRdBursts::13                544                       # Per bank write bursts
-system.physmem.perBankRdBursts::14                457                       # Per bank write bursts
-system.physmem.perBankRdBursts::15                381                       # Per bank write bursts
+system.physmem.perBankRdBursts::13                542                       # Per bank write bursts
+system.physmem.perBankRdBursts::14                454                       # Per bank write bursts
+system.physmem.perBankRdBursts::15                379                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
 system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
 system.physmem.perBankWrBursts::2                   0                       # Per bank write bursts
@@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                     72879898500                       # Total gap between requests
+system.physmem.totGap                     69651614500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                    7453                       # Read request sizes (log2)
+system.physmem.readPktSize::6                    7458                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -90,11 +90,11 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                      4278                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      1960                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       858                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                       294                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                        61                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                      4229                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      1956                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       918                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                       291                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                        62                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         2                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
@@ -186,92 +186,92 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples         1352                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      352.520710                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     211.357899                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     348.521013                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127            414     30.62%     30.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255          333     24.63%     55.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383          156     11.54%     66.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511           86      6.36%     73.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639           58      4.29%     77.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767           36      2.66%     80.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895           33      2.44%     82.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023           35      2.59%     85.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151          201     14.87%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total           1352                       # Bytes accessed per row activation
-system.physmem.totQLat                       65605500                       # Total ticks spent queuing
-system.physmem.totMemAccLat                 205349250                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                     37265000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        8802.56                       # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples         1354                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      350.251108                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     208.626324                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     348.782669                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127            425     31.39%     31.39% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255          330     24.37%     55.76% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383          151     11.15%     66.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511           84      6.20%     73.12% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639           54      3.99%     77.10% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767           42      3.10%     80.21% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895           39      2.88%     83.09% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023           25      1.85%     84.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151          204     15.07%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total           1354                       # Bytes accessed per row activation
+system.physmem.totQLat                       65436750                       # Total ticks spent queuing
+system.physmem.totMemAccLat                 205274250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                     37290000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        8774.03                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  27552.56                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           6.54                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  27524.03                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           6.85                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        6.54                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        6.85                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.05                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.05                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.01                       # Average read queue length when enqueuing
+system.physmem.avgRdQLen                         1.03                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                       6099                       # Number of row buffer hits during reads
+system.physmem.readRowHits                       6095                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   81.83                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   81.72                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                      9778599.02                       # Average gap between requests
-system.physmem.pageHitRate                      81.83                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE      69326847500                       # Time in different power states
-system.physmem.memoryStateTime::REF        2433600000                       # Time in different power states
+system.physmem.avgGap                      9339181.35                       # Average gap between requests
+system.physmem.pageHitRate                      81.72                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE      66207100500                       # Time in different power states
+system.physmem.memoryStateTime::REF        2325700000                       # Time in different power states
 system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT        1119126250                       # Time in different power states
+system.physmem.memoryStateTime::ACT        1115479500                       # Time in different power states
 system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.membus.throughput                      6544896                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq                4323                       # Transaction distribution
-system.membus.trans_dist::ReadResp               4323                       # Transaction distribution
+system.membus.throughput                      6852840                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq                4328                       # Transaction distribution
+system.membus.trans_dist::ReadResp               4328                       # Transaction distribution
 system.membus.trans_dist::ReadExReq              3130                       # Transaction distribution
 system.membus.trans_dist::ReadExResp             3130                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        14906                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                  14906                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       476992                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total              476992                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus                 476992                       # Total data (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        14916                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                  14916                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       477312                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total              477312                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus                 477312                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy             9314500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy             9424500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           69584750                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy           69714000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.branchPred.lookups                50777064                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          29451932                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           1209851                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             26262147                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                23434234                       # Number of BTB hits
+system.cpu.branchPred.lookups                51167476                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          29641015                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           1213095                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             25804997                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                23600999                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             89.231981                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 9219036                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect               1140                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             91.459026                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 9351095                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect                307                       # Number of incorrect RAS predictions.
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                    102450301                       # DTB read hits
-system.cpu.dtb.read_misses                      84837                       # DTB read misses
-system.cpu.dtb.read_acv                         48604                       # DTB read access violations
-system.cpu.dtb.read_accesses                102535138                       # DTB read accesses
-system.cpu.dtb.write_hits                    78798145                       # DTB write hits
-system.cpu.dtb.write_misses                      1517                       # DTB write misses
+system.cpu.dtb.read_hits                    103696201                       # DTB read hits
+system.cpu.dtb.read_misses                      91462                       # DTB read misses
+system.cpu.dtb.read_acv                         49407                       # DTB read access violations
+system.cpu.dtb.read_accesses                103787663                       # DTB read accesses
+system.cpu.dtb.write_hits                    79414480                       # DTB write hits
+system.cpu.dtb.write_misses                      1579                       # DTB write misses
 system.cpu.dtb.write_acv                            2                       # DTB write access violations
-system.cpu.dtb.write_accesses                78799662                       # DTB write accesses
-system.cpu.dtb.data_hits                    181248446                       # DTB hits
-system.cpu.dtb.data_misses                      86354                       # DTB misses
-system.cpu.dtb.data_acv                         48606                       # DTB access violations
-system.cpu.dtb.data_accesses                181334800                       # DTB accesses
-system.cpu.itb.fetch_hits                    50876988                       # ITB hits
-system.cpu.itb.fetch_misses                       370                       # ITB misses
+system.cpu.dtb.write_accesses                79416059                       # DTB write accesses
+system.cpu.dtb.data_hits                    183110681                       # DTB hits
+system.cpu.dtb.data_misses                      93041                       # DTB misses
+system.cpu.dtb.data_acv                         49409                       # DTB access violations
+system.cpu.dtb.data_accesses                183203722                       # DTB accesses
+system.cpu.itb.fetch_hits                    51277823                       # ITB hits
+system.cpu.itb.fetch_misses                       422                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                50877358                       # ITB accesses
+system.cpu.itb.fetch_accesses                51278245                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -285,239 +285,239 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                  215                       # Number of system calls
-system.cpu.numCycles                        145760003                       # number of cpu cycles simulated
+system.cpu.numCycles                        139303411                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           51716425                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      453983948                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    50777064                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           32653270                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      79737605                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 6706722                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles                8534058                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                  183                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles         10415                       # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles           27                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                  50876988                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                470753                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          145449114                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              3.121256                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.346528                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles           52063836                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      457094552                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    51167476                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           32952094                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      85692293                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 2532764                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles                          4                       # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles                  174                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles         13783                       # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles           26                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                  51277823                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                545280                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          139036498                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              3.287587                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.344928                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 65711509     45.18%     45.18% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  4353129      2.99%     48.17% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  6951535      4.78%     52.95% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  5417508      3.72%     56.68% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                 11887137      8.17%     64.85% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  7943266      5.46%     70.31% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  5717445      3.93%     74.24% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  1835003      1.26%     75.50% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                 35632582     24.50%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 58307253     41.94%     41.94% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  4519217      3.25%     45.19% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  7280822      5.24%     50.42% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  5545601      3.99%     54.41% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                 11970287      8.61%     63.02% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  8019991      5.77%     68.79% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  5933035      4.27%     73.06% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  1884761      1.36%     74.41% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 35575531     25.59%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            145449114                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.348361                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        3.114599                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 53474843                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles               7565433                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  78027173                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles                935486                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                5446179                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved              9541832                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                  4276                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              449545046                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                 12399                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                5446179                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 54745977                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                  756567                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles         422703                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  77638167                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles               6439521                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              445569466                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                326953                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                1035803                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                1822362                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                2964059                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands           290831608                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             586091926                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        418076358                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups         168015567                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total            139036498                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.367310                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        3.281288                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 45112294                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              16348159                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  71786999                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               4526862                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                1262184                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              9563244                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                  4245                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              451283163                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                 14200                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                1262184                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 47010937                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                 5663540                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles         519055                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  74309214                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              10271568                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              447721649                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                439815                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                2540100                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                2926498                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents                3600584                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands           292278306                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             589607782                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        419965282                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups         169642499                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps             259532329                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 31299279                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts              36843                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts            279                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                   7560708                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            105663529                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            81235477                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads          11146516                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          7815881                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  412301107                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                 261                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 404056264                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued           1312815                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        35808008                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     18428665                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved             46                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     145449114                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         2.777991                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        2.042688                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                 32745977                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts              37893                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts            316                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  16173803                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            106306370                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            81667386                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          12470725                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          9729569                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  414594685                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                 306                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 406915916                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            484036                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        38878487                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     18208108                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved             91                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     139036498                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         2.926684                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        2.221929                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            25098996     17.26%     17.26% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            21117633     14.52%     31.78% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            22669138     15.59%     47.36% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            22701668     15.61%     62.97% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            23036562     15.84%     78.81% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5            15514820     10.67%     89.47% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             8774349      6.03%     95.51% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7             5158675      3.55%     99.05% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8             1377273      0.95%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            23891417     17.18%     17.18% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            19616673     14.11%     31.29% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            22677490     16.31%     47.60% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            18900240     13.59%     61.20% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            19609415     14.10%     75.30% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            14153869     10.18%     85.48% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             9626408      6.92%     92.40% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             6209798      4.47%     96.87% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8             4351188      3.13%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       145449114                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       139036498                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                  102079      0.82%      0.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%      0.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      0.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                 61666      0.50%      1.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                 48308      0.39%      1.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                  3198      0.03%      1.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult              1785372     14.39%     16.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv               1353790     10.91%     27.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     27.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     27.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     27.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     27.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     27.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     27.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     27.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     27.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     27.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     27.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     27.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     27.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     27.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     27.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     27.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     27.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     27.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     27.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     27.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     27.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     27.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                5374985     43.31%     70.34% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite               3681074     29.66%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  258477      1.29%      1.29% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      1      0.00%      1.29% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      1.29% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                145250      0.73%      2.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                 90218      0.45%      2.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                  2947      0.01%      2.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult              3497968     17.50%     19.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv               1676632      8.39%     28.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     28.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     28.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     28.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     28.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     28.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     28.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     28.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     28.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     28.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     28.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     28.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     28.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     28.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     28.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     28.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     28.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     28.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     28.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     28.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     28.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     28.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                9338598     46.73%     75.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               4976149     24.90%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass             33581      0.01%      0.01% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             156664975     38.77%     38.78% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult              2127225      0.53%     39.31% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     39.31% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd            32964847      8.16%     47.47% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp             7504684      1.86%     49.32% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt             2799878      0.69%     50.02% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult           16685729      4.13%     54.15% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv             1581715      0.39%     54.54% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     54.54% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     54.54% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     54.54% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     54.54% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     54.54% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     54.54% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     54.54% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     54.54% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     54.54% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     54.54% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     54.54% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     54.54% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     54.54% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     54.54% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     54.54% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     54.54% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     54.54% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     54.54% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     54.54% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     54.54% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     54.54% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            104147450     25.78%     80.31% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            79546180     19.69%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             153207489     37.65%     37.66% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult              2128182      0.52%     38.18% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     38.18% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd            37392506      9.19%     47.37% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp             7524499      1.85%     49.22% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt             2804822      0.69%     49.91% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult           16757586      4.12%     54.03% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv             1601657      0.39%     54.42% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     54.42% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     54.42% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     54.42% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     54.42% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     54.42% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     54.42% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     54.42% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     54.42% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     54.42% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     54.42% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     54.42% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     54.42% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     54.42% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     54.42% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     54.42% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     54.42% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     54.42% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     54.42% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     54.42% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     54.42% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     54.42% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            105367867     25.89%     80.32% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            80097727     19.68%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              404056264                       # Type of FU issued
-system.cpu.iq.rate                           2.772065                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                    12410472                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.030715                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          628197329                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         263376555                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    235877430                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads           339087600                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes          184792904                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses    162158669                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              243128966                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses               173304189                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads         17056087                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              406915916                       # Type of FU issued
+system.cpu.iq.rate                           2.921076                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    19986240                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.049116                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          625896967                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         265989715                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    237228630                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads           347441639                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes          187559752                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses    163339265                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              246150912                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses               180717663                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads         19936358                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads     10909042                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses       154314                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        60406                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      7714748                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads     11551883                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses       163597                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        76334                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      8146657                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads       360272                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked          4287                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads       381699                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked          4486                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                5446179                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                    1032                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                211342                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           437229791                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts             59050                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             105663529                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             81235477                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts                261                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                   4770                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                204982                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          60406                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         953368                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       408257                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              1361625                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             400360320                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             102583778                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           3695944                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                1262184                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 4471522                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                139226                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           439574480                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            145285                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             106306370                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             81667386                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts                306                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                   6690                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                131709                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          76334                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         976027                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       412585                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              1388612                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             403157734                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             103837101                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           3758182                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                      24928423                       # number of nop insts executed
-system.cpu.iew.exec_refs                    181383470                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 46799473                       # Number of branches executed
-system.cpu.iew.exec_stores                   78799692                       # Number of stores executed
-system.cpu.iew.exec_rate                     2.746709                       # Inst execution rate
-system.cpu.iew.wb_sent                      398772945                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     398036099                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 201124096                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 293988661                       # num instructions consuming a value
+system.cpu.iew.exec_nop                      24979489                       # number of nop insts executed
+system.cpu.iew.exec_refs                    183253197                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 46959988                       # Number of branches executed
+system.cpu.iew.exec_stores                   79416096                       # Number of stores executed
+system.cpu.iew.exec_rate                     2.894098                       # Inst execution rate
+system.cpu.iew.wb_sent                      401401506                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     400567895                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 198000447                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 283955601                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       2.730764                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.684122                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       2.875507                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.697294                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts        38564789                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts        40912072                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls             215                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts           1205629                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    140002935                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     2.847544                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     3.108853                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts           1208897                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    133310645                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     2.990493                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     3.213946                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     50426990     36.02%     36.02% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     20519996     14.66%     50.68% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     11173587      7.98%     58.66% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      9865184      7.05%     65.70% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      7560021      5.40%     71.10% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      4963241      3.55%     74.65% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      4885893      3.49%     78.14% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      3033970      2.17%     80.30% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     27574053     19.70%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     48555640     36.42%     36.42% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     18055919     13.54%     49.97% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      9630862      7.22%     57.19% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      8737321      6.55%     63.75% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      6426213      4.82%     68.57% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      4404757      3.30%     71.87% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      4988495      3.74%     75.61% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      2616134      1.96%     77.57% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     29895304     22.43%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    140002935                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    133310645                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts            398664583                       # Number of instructions committed
 system.cpu.commit.committedOps              398664583                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -529,10 +529,10 @@ system.cpu.commit.fp_insts                  155295106                       # Nu
 system.cpu.commit.int_insts                 316365839                       # Number of committed integer instructions.
 system.cpu.commit.function_calls              8007752                       # Number of function calls committed.
 system.cpu.commit.op_class_0::No_OpClass     23123356      5.80%      5.80% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu        145805186     36.57%     42.37% # Class of committed instruction
-system.cpu.commit.op_class_0::IntMult         2124322      0.53%     42.91% # Class of committed instruction
-system.cpu.commit.op_class_0::IntDiv                0      0.00%     42.91% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatAdd       31467419      7.89%     50.80% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu        141652545     35.53%     41.33% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult         2124322      0.53%     41.86% # Class of committed instruction
+system.cpu.commit.op_class_0::IntDiv                0      0.00%     41.86% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatAdd       35620060      8.93%     50.80% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatCmp        7072549      1.77%     52.57% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatCvt        2735231      0.69%     53.26% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatMult      16498021      4.14%     57.40% # Class of committed instruction
@@ -563,227 +563,227 @@ system.cpu.commit.op_class_0::MemWrite       73520729     18.44%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total         398664583                       # Class of committed instruction
-system.cpu.commit.bw_lim_events              27574053                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events              29895304                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                    549655277                       # The number of ROB reads
-system.cpu.rob.rob_writes                   879919465                       # The number of ROB writes
-system.cpu.timesIdled                            3916                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                          310889                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads                    542989019                       # The number of ROB reads
+system.cpu.rob.rob_writes                   884890973                       # The number of ROB writes
+system.cpu.timesIdled                            3471                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                          266913                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                   375574808                       # Number of Instructions Simulated
 system.cpu.committedOps                     375574808                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               0.388098                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.388098                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               2.576666                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         2.576666                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                400324799                       # number of integer regfile reads
-system.cpu.int_regfile_writes               170964393                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                 157088507                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                104631166                       # number of floating regfile writes
+system.cpu.cpi                               0.370907                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.370907                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               2.696092                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         2.696092                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                403240144                       # number of integer regfile reads
+system.cpu.int_regfile_writes               171897287                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                 157938395                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                105579710                       # number of floating regfile writes
 system.cpu.misc_regfile_reads                  350572                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
-system.cpu.toL2Bus.throughput                 7854226                       # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq           5074                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp          5074                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback          670                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq         3200                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp         3200                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         8166                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         9052                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total             17218                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       261312                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       311104                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total         572416                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus            572416                       # Total data (bytes)
+system.cpu.toL2Bus.throughput                 8238478                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq           5089                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp          5089                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback          674                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq         3203                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp         3203                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         8182                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         9076                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total             17258                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       261824                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       312000                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total         573824                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus            573824                       # Total data (bytes)
 system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy        5142000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.occupancy        5157000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy       6782500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy       6787250                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy       6677500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy       6699750                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu.icache.tags.replacements              2155                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1832.273556                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            50871213                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs              4083                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          12459.273328                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements              2164                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1832.364341                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            51272145                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs              4091                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          12532.912491                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1832.273556                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.894665                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.894665                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024         1928                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          120                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          137                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          333                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4         1338                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.941406                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         101758059                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        101758059                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     50871213                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        50871213                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      50871213                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         50871213                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     50871213                       # number of overall hits
-system.cpu.icache.overall_hits::total        50871213                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst         5775                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total          5775                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst         5775                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total           5775                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst         5775                       # number of overall misses
-system.cpu.icache.overall_misses::total          5775                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    343384000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    343384000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    343384000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    343384000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    343384000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    343384000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     50876988                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     50876988                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     50876988                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     50876988                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     50876988                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     50876988                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000114                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000114                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000114                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000114                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000114                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000114                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 59460.432900                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 59460.432900                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 59460.432900                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 59460.432900                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 59460.432900                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 59460.432900                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs          389                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets          400                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                 7                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               1                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    55.571429                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets          400                       # average number of cycles each access was blocked
+system.cpu.icache.tags.occ_blocks::cpu.inst  1832.364341                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.894709                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.894709                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1927                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          123                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          167                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          294                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1343                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.940918                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses         102559737                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        102559737                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     51272145                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        51272145                       # number of ReadReq hits
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+system.cpu.icache.overall_hits::total        51272145                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         5678                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          5678                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         5678                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           5678                       # number of demand (read+write) misses
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+system.cpu.icache.overall_misses::total          5678                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    339990499                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    339990499                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    339990499                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    339990499                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    339990499                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    339990499                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     51277823                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     51277823                       # number of ReadReq accesses(hits+misses)
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+system.cpu.icache.demand_accesses::total     51277823                       # number of demand (read+write) accesses
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+system.cpu.icache.overall_accesses::total     51277823                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000111                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000111                       # miss rate for ReadReq accesses
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+system.cpu.icache.demand_miss_rate::total     0.000111                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000111                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000111                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 59878.566221                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 59878.566221                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 59878.566221                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 59878.566221                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 59878.566221                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 59878.566221                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs          528                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 9                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    58.666667                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst         1692                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total         1692                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst         1692                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total         1692                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst         1692                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total         1692                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst         4083                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total         4083                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst         4083                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total         4083                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst         4083                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total         4083                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    250419500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    250419500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    250419500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    250419500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    250419500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    250419500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         1587                       # number of ReadReq MSHR hits
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+system.cpu.icache.ReadReq_mshr_misses::cpu.inst         4091                       # number of ReadReq MSHR misses
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+system.cpu.icache.overall_mshr_miss_latency::total    249912250                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000080                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000080                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000080                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000080                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000080                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000080                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61332.231203                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61332.231203                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61332.231203                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 61332.231203                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61332.231203                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 61332.231203                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61088.303593                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61088.303593                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61088.303593                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 61088.303593                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61088.303593                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 61088.303593                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse         4014.278169                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs                853                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs             4857                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             0.175623                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.tagsinuse         4021.632114                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs                866                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs             4864                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             0.178043                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks   371.130590                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  2983.232986                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   659.914592                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::writebacks   371.133815                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  2983.663024                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data   666.835276                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_percent::writebacks     0.011326                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.091041                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.020139                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.122506                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024         4857                       # Occupied blocks per task id
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-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          102                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          572                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4         4039                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.148224                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses            79609                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses           79609                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst          619                       # number of ReadReq hits
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.091054                       # Average percentage of cache occupancy
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+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.148438                       # Percentage of cache occupancy per task id
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 system.cpu.l2cache.ReadReq_hits::cpu.data          132                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total            751                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks          670                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total          670                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data           70                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total           70                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst          619                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data          202                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total             821                       # number of demand (read+write) hits
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-system.cpu.l2cache.overall_hits::cpu.data          202                       # number of overall hits
-system.cpu.l2cache.overall_hits::total            821                       # number of overall hits
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+system.cpu.l2cache.Writeback_hits::writebacks          674                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total          674                       # number of Writeback hits
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 system.cpu.l2cache.ReadExReq_misses::cpu.data         3130                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total         3130                       # number of ReadExReq misses
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-system.cpu.l2cache.overall_misses::cpu.data         3989                       # number of overall misses
-system.cpu.l2cache.overall_misses::total         7453                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    240129250                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data     65475000                       # number of ReadReq miss cycles
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-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    231013500                       # number of ReadExReq miss cycles
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-system.cpu.l2cache.overall_miss_latency::cpu.data    296488500                       # number of overall miss cycles
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-system.cpu.l2cache.ReadReq_accesses::cpu.data          991                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total         5074                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks          670                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total          670                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data         3200                       # number of ReadExReq accesses(hits+misses)
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-system.cpu.l2cache.demand_accesses::cpu.data         4191                       # number of demand (read+write) accesses
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-system.cpu.l2cache.overall_accesses::cpu.data         4191                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total         8274                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.848396                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.866801                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.851991                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.978125                       # miss rate for ReadExReq accesses
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-system.cpu.l2cache.demand_miss_rate::cpu.data     0.951801                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.900774                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.848396                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.951801                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.900774                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69321.377021                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76222.351572                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 70692.632431                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73806.230032                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73806.230032                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69321.377021                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74326.522938                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 72000.234805                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69321.377021                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74326.522938                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 72000.234805                       # average overall miss latency
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+system.cpu.l2cache.overall_misses::total         7458                       # number of overall misses
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+system.cpu.l2cache.ReadReq_miss_latency::cpu.data     65288250                       # number of ReadReq miss cycles
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+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    231991500                       # number of ReadExReq miss cycles
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+system.cpu.l2cache.overall_miss_latency::cpu.data    297279750                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    536800500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst         4091                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data          998                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total         5089                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks          674                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total          674                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data         3203                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total         3203                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst         4091                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data         4201                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total         8292                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst         4091                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data         4201                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total         8292                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.846248                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.867735                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.850462                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.977209                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.977209                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.846248                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.951202                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.899421                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.846248                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.951202                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.899421                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69185.658579                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75390.588915                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 70427.218115                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74118.690096                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74118.690096                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69185.658579                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74394.331832                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 71976.468222                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69185.658579                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74394.331832                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 71976.468222                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -792,171 +792,171 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3464                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          859                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total         4323                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3462                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          866                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total         4328                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         3130                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total         3130                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         3464                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data         3989                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total         7453                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         3464                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data         3989                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total         7453                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    196216750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     54882000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total    251098750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    192525500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    192525500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    196216750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    247407500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    443624250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    196216750                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    247407500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    443624250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.848396                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.866801                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.851991                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.978125                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.978125                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.848396                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.951801                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.900774                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.848396                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.951801                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.900774                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56644.558314                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63890.570431                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58084.374277                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61509.744409                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61509.744409                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56644.558314                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62022.436701                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59522.910237                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56644.558314                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62022.436701                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59522.910237                       # average overall mshr miss latency
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         3462                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data         3996                       # number of demand (read+write) MSHR misses
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+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    195634750                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     54618250                       # number of ReadReq MSHR miss cycles
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+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    193410500                       # number of ReadExReq MSHR miss cycles
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+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    248028750                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    443663500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.846248                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.867735                       # mshr miss rate for ReadReq accesses
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+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.977209                       # mshr miss rate for ReadExReq accesses
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+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.951202                       # mshr miss rate for overall accesses
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+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56509.170999                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63069.572748                       # average ReadReq mshr miss latency
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+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61792.492013                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61792.492013                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56509.170999                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62069.256757                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59488.267632                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56509.170999                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62069.256757                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59488.267632                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements               790                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          3294.829760                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           158529737                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs              4191                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs          37826.231687                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.replacements               798                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          3297.113069                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           156873476                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs              4201                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs          37341.936682                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  3294.829760                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.804402                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.804402                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024         3401                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           45                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1           17                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2          215                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_blocks::cpu.data  3297.113069                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.804959                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.804959                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         3403                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           47                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           21                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          212                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::3            7                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::4         3117                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024     0.830322                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         317106037                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        317106037                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     85028391                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        85028391                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     73501342                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       73501342                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data            4                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total            4                       # number of LoadLockedReq hits
-system.cpu.dcache.demand_hits::cpu.data     158529733                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        158529733                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    158529733                       # number of overall hits
-system.cpu.dcache.overall_hits::total       158529733                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data         1799                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total          1799                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data        19387                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total        19387                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data        21186                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total          21186                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data        21186                       # number of overall misses
-system.cpu.dcache.overall_misses::total         21186                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data    115077500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total    115077500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   1124516028                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   1124516028                       # number of WriteReq miss cycles
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-system.cpu.dcache.demand_miss_latency::total   1239593528                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data   1239593528                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total   1239593528                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     85030190                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     85030190                       # number of ReadReq accesses(hits+misses)
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+system.cpu.dcache.tags.occ_task_id_percent::1024     0.830811                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses         313794583                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        313794583                       # Number of data accesses
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+system.cpu.dcache.LoadLockedReq_hits::total            7                       # number of LoadLockedReq hits
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+system.cpu.dcache.overall_hits::total       156873469                       # number of overall hits
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+system.cpu.dcache.ReadReq_misses::total          1822                       # number of ReadReq misses
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+system.cpu.dcache.overall_misses::total         21715                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data    114614250                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total    114614250                       # number of ReadReq miss cycles
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+system.cpu.dcache.overall_miss_latency::total   1239819085                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     83374455                       # number of ReadReq accesses(hits+misses)
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 system.cpu.dcache.WriteReq_accesses::cpu.data     73520729                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     73520729                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data            4                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total            4                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    158550919                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    158550919                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    158550919                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    158550919                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000021                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.000021                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000264                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.000264                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.000134                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.000134                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.000134                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.000134                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63967.481934                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 63967.481934                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 58003.612111                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 58003.612111                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 58510.031530                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 58510.031530                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 58510.031530                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 58510.031530                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs        44616                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs               797                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    55.979925                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data            7                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total            7                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data    156895184                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    156895184                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    156895184                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    156895184                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000022                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.000022                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000271                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.000271                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.000138                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.000138                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.000138                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.000138                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62905.735456                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 62905.735456                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56562.853014                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 56562.853014                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 57095.053419                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 57095.053419                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 57095.053419                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 57095.053419                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs        46429                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets           61                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs               948                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               1                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    48.975738                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets           61                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks          670                       # number of writebacks
-system.cpu.dcache.writebacks::total               670                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data          808                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total          808                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data        16187                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total        16187                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data        16995                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total        16995                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data        16995                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total        16995                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data          991                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total          991                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data         3200                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total         3200                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data         4191                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total         4191                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data         4191                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total         4191                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     67828000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total     67828000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    235012500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total    235012500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data    302840500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total    302840500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data    302840500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total    302840500                       # number of overall MSHR miss cycles
+system.cpu.dcache.writebacks::writebacks          674                       # number of writebacks
+system.cpu.dcache.writebacks::total               674                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data          824                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total          824                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data        16690                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total        16690                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data        17514                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total        17514                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data        17514                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total        17514                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data          998                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total          998                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data         3203                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total         3203                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data         4201                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total         4201                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data         4201                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total         4201                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     67699250                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     67699250                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    236024500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total    236024500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data    303723750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total    303723750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data    303723750                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total    303723750                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000012                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000012                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000044                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000044                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000026                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.000026                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000026                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.000026                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 68443.995964                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 68443.995964                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73441.406250                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73441.406250                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72259.723216                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 72259.723216                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72259.723216                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 72259.723216                       # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000027                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.000027                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000027                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.000027                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67834.919840                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67834.919840                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73688.573213                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73688.573213                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72297.964770                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 72297.964770                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72297.964770                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 72297.964770                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt
index 4cd29aa5b..bde0ba631 100644
--- a/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.199332                       # Nu
 sim_ticks                                199332411500                       # Number of ticks simulated
 final_tick                               199332411500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                2589605                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2589605                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1294803220                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 262692                       # Number of bytes of host memory used
-host_seconds                                   153.95                       # Real time elapsed on the host
+host_inst_rate                                3159999                       # Simulator instruction rate (inst/s)
+host_op_rate                                  3159998                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1579999901                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 261616                       # Number of bytes of host memory used
+host_seconds                                   126.16                       # Real time elapsed on the host
 sim_insts                                   398664595                       # Number of instructions simulated
 sim_ops                                     398664595                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -96,10 +96,10 @@ system.cpu.not_idle_fraction                        1                       # Pe
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                          44587532                       # Number of branches fetched
 system.cpu.op_class::No_OpClass              23123356      5.80%      5.80% # Class of executed instruction
-system.cpu.op_class::IntAlu                 145805196     36.57%     42.37% # Class of executed instruction
-system.cpu.op_class::IntMult                  2124322      0.53%     42.91% # Class of executed instruction
-system.cpu.op_class::IntDiv                         0      0.00%     42.91% # Class of executed instruction
-system.cpu.op_class::FloatAdd                31467419      7.89%     50.80% # Class of executed instruction
+system.cpu.op_class::IntAlu                 141652555     35.53%     41.33% # Class of executed instruction
+system.cpu.op_class::IntMult                  2124322      0.53%     41.86% # Class of executed instruction
+system.cpu.op_class::IntDiv                         0      0.00%     41.86% # Class of executed instruction
+system.cpu.op_class::FloatAdd                35620060      8.93%     50.80% # Class of executed instruction
 system.cpu.op_class::FloatCmp                 7072549      1.77%     52.57% # Class of executed instruction
 system.cpu.op_class::FloatCvt                 2735231      0.69%     53.26% # Class of executed instruction
 system.cpu.op_class::FloatMult               16498021      4.14%     57.40% # Class of executed instruction
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt
index c52832ea0..f8ab96a0a 100644
--- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.567335                       # Nu
 sim_ticks                                567335093000                       # Number of ticks simulated
 final_tick                               567335093000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1080224                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1080224                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1537254294                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 271408                       # Number of bytes of host memory used
-host_seconds                                   369.06                       # Real time elapsed on the host
+host_inst_rate                                1556013                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1556013                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2214344764                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 270340                       # Number of bytes of host memory used
+host_seconds                                   256.21                       # Real time elapsed on the host
 sim_insts                                   398664609                       # Number of instructions simulated
 sim_ops                                     398664609                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -102,10 +102,10 @@ system.cpu.not_idle_fraction                        1                       # Pe
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                          44587535                       # Number of branches fetched
 system.cpu.op_class::No_OpClass              23123356      5.80%      5.80% # Class of executed instruction
-system.cpu.op_class::IntAlu                 145805208     36.57%     42.37% # Class of executed instruction
-system.cpu.op_class::IntMult                  2124322      0.53%     42.91% # Class of executed instruction
-system.cpu.op_class::IntDiv                         0      0.00%     42.91% # Class of executed instruction
-system.cpu.op_class::FloatAdd                31467419      7.89%     50.80% # Class of executed instruction
+system.cpu.op_class::IntAlu                 141652567     35.53%     41.33% # Class of executed instruction
+system.cpu.op_class::IntMult                  2124322      0.53%     41.86% # Class of executed instruction
+system.cpu.op_class::IntDiv                         0      0.00%     41.86% # Class of executed instruction
+system.cpu.op_class::FloatAdd                35620060      8.93%     50.80% # Class of executed instruction
 system.cpu.op_class::FloatCmp                 7072549      1.77%     52.57% # Class of executed instruction
 system.cpu.op_class::FloatCvt                 2735231      0.69%     53.26% # Class of executed instruction
 system.cpu.op_class::FloatMult               16498021      4.14%     57.40% # Class of executed instruction
diff --git a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt
index 0a05ac469..73979cce4 100644
--- a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt
+++ b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt
@@ -1,560 +1,58 @@
 
 ---------- Begin Simulation Statistics ----------
-final_tick                               227445516000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-host_inst_rate                                 153700                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 303376                       # Number of bytes of host memory used
-host_op_rate                                   196498                       # Simulator op (including micro ops) rate (op/s)
-host_seconds                                  1776.44                       # Real time elapsed on the host
-host_tick_rate                              128034740                       # Simulator tick rate (ticks/s)
+sim_seconds                                  0.212377                       # Number of seconds simulated
+sim_ticks                                212377413000                       # Number of ticks simulated
+final_tick                               212377413000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-sim_insts                                   273037854                       # Number of instructions simulated
-sim_ops                                     349065592                       # Number of ops (including micro ops) simulated
-sim_seconds                                  0.227446                       # Number of seconds simulated
-sim_ticks                                227445516000                       # Number of ticks simulated
+host_inst_rate                                 166098                       # Simulator instruction rate (inst/s)
+host_op_rate                                   199419                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              129195965                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 326468                       # Number of bytes of host memory used
+host_seconds                                  1643.84                       # Real time elapsed on the host
+sim_insts                                   273037856                       # Number of instructions simulated
+sim_ops                                     327812213                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             83.362247                       # BTB Hit Percentage
-system.cpu.branchPred.BTBHits                16723894                       # Number of BTB hits
-system.cpu.branchPred.BTBLookups             20061712                       # Number of BTB lookups
-system.cpu.branchPred.RASInCorrect                121                       # Number of incorrect RAS predictions.
-system.cpu.branchPred.condIncorrect           1671536                       # Number of conditional branches incorrect
-system.cpu.branchPred.condPredicted          21059526                       # Number of conditional branches predicted
-system.cpu.branchPred.lookups                35363260                       # Number of BP lookups
-system.cpu.branchPred.usedRAS                 6617396                       # Number of times the RAS was used to get a target.
-system.cpu.committedInsts                   273037854                       # Number of instructions committed
-system.cpu.committedOps                     349065592                       # Number of ops (including micro ops) committed
-system.cpu.cpi                               1.666037                       # CPI: cycles per instruction
-system.cpu.dcache.LoadLockedReq_accesses::cpu.inst        10895                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total        10895                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_hits::cpu.inst        10895                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total        10895                       # number of LoadLockedReq hits
-system.cpu.dcache.ReadReq_accesses::cpu.inst     95145110                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     95145110                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 61749.740048                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 61749.740048                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 61620.734497                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61620.734497                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits::cpu.inst     95143025                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        95143025                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency::cpu.inst    128748208                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total    128748208                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate::cpu.inst     0.000022                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.000022                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses::cpu.inst         2085                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total          2085                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits::cpu.inst          424                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total          424                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst    102352040                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total    102352040                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst     0.000017                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000017                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses::cpu.inst         1661                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total         1661                       # number of ReadReq MSHR misses
-system.cpu.dcache.StoreCondReq_accesses::cpu.inst        10895                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total        10895                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_hits::cpu.inst        10895                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total        10895                       # number of StoreCondReq hits
-system.cpu.dcache.WriteReq_accesses::cpu.inst     82052677                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total     82052677                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 68469.206380                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 68469.206380                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 68654.108392                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68654.108392                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits::cpu.inst     82047473                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       82047473                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency::cpu.inst    356313750                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total    356313750                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate::cpu.inst     0.000063                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.000063                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses::cpu.inst         5204                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total         5204                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits::cpu.inst         2344                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total         2344                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst    196350750                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total    196350750                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst     0.000035                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000035                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.inst         2860                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total         2860                       # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.demand_accesses::cpu.inst    177197787                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    177197787                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66547.120044                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 66547.120044                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 66070.070781                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 66070.070781                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits::cpu.inst     177190498                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        177190498                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency::cpu.inst    485061958                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total    485061958                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate::cpu.inst     0.000041                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.000041                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses::cpu.inst         7289                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total           7289                       # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits::cpu.inst         2768                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total         2768                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency::cpu.inst    298702790                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total    298702790                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate::cpu.inst     0.000026                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.000026                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses::cpu.inst         4521                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total         4521                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses::cpu.inst    177197787                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    177197787                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66547.120044                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 66547.120044                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 66070.070781                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 66070.070781                       # average overall mshr miss latency
-system.cpu.dcache.overall_hits::cpu.inst    177190498                       # number of overall hits
-system.cpu.dcache.overall_hits::total       177190498                       # number of overall hits
-system.cpu.dcache.overall_miss_latency::cpu.inst    485061958                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total    485061958                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate::cpu.inst     0.000041                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.000041                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses::cpu.inst         7289                       # number of overall misses
-system.cpu.dcache.overall_misses::total          7289                       # number of overall misses
-system.cpu.dcache.overall_mshr_hits::cpu.inst         2768                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total         2768                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency::cpu.inst    298702790                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total    298702790                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate::cpu.inst     0.000026                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.000026                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses::cpu.inst         4521                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total         4521                       # number of overall MSHR misses
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           17                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1           23                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2           11                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3          674                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::4         2436                       # Occupied blocks per task id
-system.cpu.dcache.tags.avg_refs          39197.586375                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.data_accesses        354443675                       # Number of data accesses
-system.cpu.dcache.tags.occ_blocks::cpu.inst  3089.554835                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.inst     0.754286                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.754286                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024         3161                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024     0.771729                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.replacements              1360                       # number of replacements
-system.cpu.dcache.tags.sampled_refs              4521                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.tag_accesses         354443675                       # Number of tag accesses
-system.cpu.dcache.tags.tagsinuse          3089.554835                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           177212288                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks::writebacks         1013                       # number of writebacks
-system.cpu.dcache.writebacks::total              1013                       # number of writebacks
-system.cpu.discardedOps                       6932970                       # Number of ops (including micro ops) which were discarded before commit
-system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
-system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
-system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
-system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
-system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
-system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
-system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
-system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
-system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
-system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
-system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
-system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
-system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
-system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
-system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
-system.cpu.dtb.accesses                             0                       # DTB accesses
-system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.hits                                 0                       # DTB hits
-system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.inst_hits                            0                       # ITB inst hits
-system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.misses                               0                       # DTB misses
-system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
-system.cpu.dtb.read_accesses                        0                       # DTB read accesses
-system.cpu.dtb.read_hits                            0                       # DTB read hits
-system.cpu.dtb.read_misses                          0                       # DTB read misses
-system.cpu.dtb.write_accesses                       0                       # DTB write accesses
-system.cpu.dtb.write_hits                           0                       # DTB write hits
-system.cpu.dtb.write_misses                         0                       # DTB write misses
-system.cpu.icache.ReadReq_accesses::cpu.inst     77471042                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     77471042                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17858.870336                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 17858.870336                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15825.006083                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15825.006083                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits::cpu.inst     77429612                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        77429612                       # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    739892998                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    739892998                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000535                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000535                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses::cpu.inst        41430                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total         41430                       # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    655630002                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    655630002                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000535                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000535                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst        41430                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total        41430                       # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.demand_accesses::cpu.inst     77471042                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     77471042                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 17858.870336                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 17858.870336                       # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15825.006083                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 15825.006083                       # average overall mshr miss latency
-system.cpu.icache.demand_hits::cpu.inst      77429612                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         77429612                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency::cpu.inst    739892998                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    739892998                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000535                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000535                       # miss rate for demand accesses
-system.cpu.icache.demand_misses::cpu.inst        41430                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total          41430                       # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    655630002                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    655630002                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000535                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.000535                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses::cpu.inst        41430                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total        41430                       # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses::cpu.inst     77471042                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     77471042                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 17858.870336                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 17858.870336                       # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15825.006083                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 15825.006083                       # average overall mshr miss latency
-system.cpu.icache.overall_hits::cpu.inst     77429612                       # number of overall hits
-system.cpu.icache.overall_hits::total        77429612                       # number of overall hits
-system.cpu.icache.overall_miss_latency::cpu.inst    739892998                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    739892998                       # number of overall miss cycles
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000535                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000535                       # miss rate for overall accesses
-system.cpu.icache.overall_misses::cpu.inst        41430                       # number of overall misses
-system.cpu.icache.overall_misses::total         41430                       # number of overall misses
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    655630002                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    655630002                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000535                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.000535                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses::cpu.inst        41430                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total        41430                       # number of overall MSHR misses
-system.cpu.icache.tags.age_task_id_blocks_1024::0           55                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1           87                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2           33                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3          288                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4         1478                       # Occupied blocks per task id
-system.cpu.icache.tags.avg_refs           1868.971300                       # Average number of references to valid blocks.
-system.cpu.icache.tags.data_accesses        154983513                       # Number of data accesses
-system.cpu.icache.tags.occ_blocks::cpu.inst  1927.026996                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.940931                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.940931                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024         1941                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.947754                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.replacements             39488                       # number of replacements
-system.cpu.icache.tags.sampled_refs             41429                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.tag_accesses         154983513                       # Number of tag accesses
-system.cpu.icache.tags.tagsinuse          1927.026996                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            77429612                       # Total number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.idleCycles                         4029946                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.ipc                               0.600227                       # IPC: instructions per cycle
-system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
-system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
-system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
-system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
-system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
-system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
-system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
-system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
-system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
-system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
-system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
-system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
-system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
-system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
-system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
-system.cpu.itb.accesses                             0                       # DTB accesses
-system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
-system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.hits                                 0                       # DTB hits
-system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.itb.inst_hits                            0                       # ITB inst hits
-system.cpu.itb.inst_misses                          0                       # ITB inst misses
-system.cpu.itb.misses                               0                       # DTB misses
-system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
-system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
-system.cpu.itb.read_accesses                        0                       # DTB read accesses
-system.cpu.itb.read_hits                            0                       # DTB read hits
-system.cpu.itb.read_misses                          0                       # DTB read misses
-system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.write_hits                           0                       # DTB write hits
-system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.l2cache.ReadExReq_accesses::cpu.inst         2860                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total         2860                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 67967.563291                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67967.563291                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 55399.173699                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55399.173699                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_hits::cpu.inst           16                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total           16                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst    193299750                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total    193299750                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst     0.994406                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.994406                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses::cpu.inst         2844                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total         2844                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst    157555250                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    157555250                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst     0.994406                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.994406                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst         2844                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total         2844                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses::cpu.inst        43091                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total        43091                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68852.642487                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 68852.642487                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56391.699770                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56391.699770                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits::cpu.inst        38266                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total          38266                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    332214000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total    332214000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.111972                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.111972                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses::cpu.inst         4825                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total         4825                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst           42                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total           42                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    269721500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total    269721500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.110998                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.110998                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         4783                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total         4783                       # number of ReadReq MSHR misses
-system.cpu.l2cache.Writeback_accesses::writebacks         1013                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total         1013                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits::writebacks         1013                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total         1013                       # number of Writeback hits
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.demand_accesses::cpu.inst        45951                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total        45951                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68524.416482                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 68524.416482                       # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56021.600892                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56021.600892                       # average overall mshr miss latency
-system.cpu.l2cache.demand_hits::cpu.inst        38282                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total           38282                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency::cpu.inst    525513750                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total    525513750                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.166895                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.166895                       # miss rate for demand accesses
-system.cpu.l2cache.demand_misses::cpu.inst         7669                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total          7669                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_mshr_hits::cpu.inst           42                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total           42                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    427276750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    427276750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.165981                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.165981                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         7627                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total         7627                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses::cpu.inst        45951                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total        45951                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68524.416482                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 68524.416482                       # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56021.600892                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56021.600892                       # average overall mshr miss latency
-system.cpu.l2cache.overall_hits::cpu.inst        38282                       # number of overall hits
-system.cpu.l2cache.overall_hits::total          38282                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency::cpu.inst    525513750                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total    525513750                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.166895                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.166895                       # miss rate for overall accesses
-system.cpu.l2cache.overall_misses::cpu.inst         7669                       # number of overall misses
-system.cpu.l2cache.overall_misses::total         7669                       # number of overall misses
-system.cpu.l2cache.overall_mshr_hits::cpu.inst           42                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total           42                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    427276750                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    427276750                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.165981                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.165981                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         7627                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total         7627                       # number of overall MSHR misses
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           50                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1           43                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2           40                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         1262                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4         4305                       # Occupied blocks per task id
-system.cpu.l2cache.tags.avg_refs             6.727368                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.data_accesses          384272                       # Number of data accesses
-system.cpu.l2cache.tags.occ_blocks::writebacks   356.812936                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  3883.048925                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.010889                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.118501                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.129390                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024         5700                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.173950                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.sampled_refs             5700                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.tag_accesses           384272                       # Number of tag accesses
-system.cpu.l2cache.tags.tagsinuse         4239.861860                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs              38346                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.numCycles                        454891032                       # number of cpu cycles simulated
-system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.tickCycles                       450861086                       # Number of cycles that the CPU actually ticked
-system.cpu.toL2Bus.data_through_bus           3005632                       # Total data (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        82859                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side        10055                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total             92914                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy       24495000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy      62845998                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy       7514710                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
-system.cpu.toL2Bus.throughput                13214734                       # Throughput (bytes/s)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2651456                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       354176                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total        3005632                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.trans_dist::ReadReq          43091                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp         43090                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback         1013                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq         2860                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp         2860                       # Transaction distribution
-system.cpu.workload.num_syscalls                  191                       # Number of system calls
-system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.membus.data_through_bus                 488128                       # Total data (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        15254                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                  15254                       # Packet count per connected master and slave (bytes)
-system.membus.reqLayer0.occupancy             8910000                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           71341750                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
-system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.throughput                      2146132                       # Throughput (bytes/s)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       488128                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total              488128                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.trans_dist::ReadReq                4783                       # Transaction distribution
-system.membus.trans_dist::ReadResp               4783                       # Transaction distribution
-system.membus.trans_dist::ReadExReq              2844                       # Transaction distribution
-system.membus.trans_dist::ReadExResp             2844                       # Transaction distribution
-system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgGap                     29821084.57                       # Average gap between requests
-system.physmem.avgMemAccLat                  25580.41                       # Average memory access latency per DRAM burst
-system.physmem.avgQLat                        6830.41                       # Average queueing delay per DRAM burst
-system.physmem.avgRdBW                           2.15                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        2.15                       # Average system read bandwidth in MiByte/s
-system.physmem.avgRdQLen                         1.05                       # Average read queue length when enqueuing
-system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
-system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.busUtil                           0.02                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       0.02                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.bw_inst_read::cpu.inst          974721                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             974721                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst              2146132                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 2146132                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             2146132                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                2146132                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bytesPerActivate::samples         1544                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      315.689119                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     184.950751                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     330.584238                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127            593     38.41%     38.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255          326     21.11%     59.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383          172     11.14%     70.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511           76      4.92%     75.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639           71      4.60%     80.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767           58      3.76%     83.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895           38      2.46%     86.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023           28      1.81%     88.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151          182     11.79%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total           1544                       # Bytes accessed per row activation
-system.physmem.bytesReadDRAM                   488128                       # Total number of bytes read from DRAM
-system.physmem.bytesReadSys                    488128                       # Total read bytes from the system interface side
+system.physmem.bytes_read::cpu.inst            485312                       # Number of bytes read from this memory
+system.physmem.bytes_read::total               485312                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       219008                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          219008                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst               7583                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                  7583                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst              2285139                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 2285139                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         1031221                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            1031221                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             2285139                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                2285139                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                          7583                       # Number of read requests accepted
+system.physmem.writeReqs                            0                       # Number of write requests accepted
+system.physmem.readBursts                        7583                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                   485312                       # Total number of bytes read from DRAM
 system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
 system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                    485312                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
-system.physmem.bytes_inst_read::cpu.inst       221696                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          221696                       # Number of instructions bytes read from this memory
-system.physmem.bytes_read::cpu.inst            488128                       # Number of bytes read from this memory
-system.physmem.bytes_read::total               488128                       # Number of bytes read from this memory
-system.physmem.memoryStateTime::IDLE     217468466000                       # Time in different power states
-system.physmem.memoryStateTime::REF        7594860000                       # Time in different power states
-system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT        2381096500                       # Time in different power states
-system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
+system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.num_reads::cpu.inst               7627                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                  7627                       # Number of read requests responded to by this memory
-system.physmem.pageHitRate                      79.70                       # Row buffer hit rate, read and write combined
-system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.perBankRdBursts::0                 637                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                 850                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                 633                       # Per bank write bursts
+system.physmem.perBankRdBursts::0                 630                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                 843                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                 628                       # Per bank write bursts
 system.physmem.perBankRdBursts::3                 541                       # Per bank write bursts
-system.physmem.perBankRdBursts::4                 470                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                 350                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                 175                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                 229                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                 210                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                 309                       # Per bank write bursts
-system.physmem.perBankRdBursts::10                346                       # Per bank write bursts
+system.physmem.perBankRdBursts::4                 466                       # Per bank write bursts
+system.physmem.perBankRdBursts::5                 349                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                 173                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                 228                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                 209                       # Per bank write bursts
+system.physmem.perBankRdBursts::9                 310                       # Per bank write bursts
+system.physmem.perBankRdBursts::10                342                       # Per bank write bursts
 system.physmem.perBankRdBursts::11                428                       # Per bank write bursts
-system.physmem.perBankRdBursts::12                552                       # Per bank write bursts
-system.physmem.perBankRdBursts::13                714                       # Per bank write bursts
-system.physmem.perBankRdBursts::14                639                       # Per bank write bursts
-system.physmem.perBankRdBursts::15                544                       # Per bank write bursts
+system.physmem.perBankRdBursts::12                554                       # Per bank write bursts
+system.physmem.perBankRdBursts::13                705                       # Per bank write bursts
+system.physmem.perBankRdBursts::14                637                       # Per bank write bursts
+system.physmem.perBankRdBursts::15                540                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
 system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
 system.physmem.perBankWrBursts::2                   0                       # Per bank write bursts
@@ -571,9 +69,26 @@ system.physmem.perBankWrBursts::12                  0                       # Pe
 system.physmem.perBankWrBursts::13                  0                       # Per bank write bursts
 system.physmem.perBankWrBursts::14                  0                       # Per bank write bursts
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
-system.physmem.rdQLenPdf::0                      6680                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       887                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        60                       # What read queue length does an incoming req see
+system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
+system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
+system.physmem.totGap                    212377186000                       # Total gap between requests
+system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
+system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
+system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
+system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
+system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
+system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
+system.physmem.readPktSize::6                    7583                       # Read request sizes (log2)
+system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
+system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
+system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
+system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
+system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
+system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
+system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                      6625                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       897                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        61                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
@@ -603,22 +118,6 @@ system.physmem.rdQLenPdf::28                        0                       # Wh
 system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.readBursts                        7627                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                    7627                       # Read request sizes (log2)
-system.physmem.readReqs                          7627                       # Number of read requests accepted
-system.physmem.readRowHitRate                   79.70                       # Row buffer hit rate for reads
-system.physmem.readRowHits                       6079                       # Number of row buffer hits during reads
-system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.totBusLat                     38135000                       # Total ticks spent in databus transfers
-system.physmem.totGap                    227445412000                       # Total gap between requests
-system.physmem.totMemAccLat                 195101750                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totQLat                       52095500                       # Total ticks spent queuing
 system.physmem.wrQLenPdf::0                         0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::1                         0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::2                         0                       # What write queue length does an incoming req see
@@ -683,17 +182,518 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.writeReqs                            0                       # Number of write requests accepted
-system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
+system.physmem.bytesPerActivate::samples         1498                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      322.691589                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     189.527839                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     333.553355                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127            554     36.98%     36.98% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255          333     22.23%     59.21% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383          160     10.68%     69.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511           67      4.47%     74.37% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639           72      4.81%     79.17% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767           61      4.07%     83.24% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895           43      2.87%     86.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023           33      2.20%     88.32% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151          175     11.68%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total           1498                       # Bytes accessed per row activation
+system.physmem.totQLat                       52122500                       # Total ticks spent queuing
+system.physmem.totMemAccLat                 194303750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                     37915000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        6873.60                       # Average queueing delay per DRAM burst
+system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
+system.physmem.avgMemAccLat                  25623.60                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           2.29                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        2.29                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
+system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
+system.physmem.busUtil                           0.02                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       0.02                       # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen                         1.05                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
+system.physmem.readRowHits                       6077                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.physmem.readRowHitRate                   80.14                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
+system.physmem.avgGap                     28007013.85                       # Average gap between requests
+system.physmem.pageHitRate                      80.14                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE     202838268250                       # Time in different power states
+system.physmem.memoryStateTime::REF        7091500000                       # Time in different power states
+system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
+system.physmem.memoryStateTime::ACT        2441586750                       # Time in different power states
+system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
+system.membus.throughput                      2285139                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq                4730                       # Transaction distribution
+system.membus.trans_dist::ReadResp               4730                       # Transaction distribution
+system.membus.trans_dist::ReadExReq              2853                       # Transaction distribution
+system.membus.trans_dist::ReadExResp             2853                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        15166                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                  15166                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       485312                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total              485312                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus                 485312                       # Total data (bytes)
+system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy             8812000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
+system.membus.respLayer1.occupancy           70869000                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.cpu.branchPred.lookups                33146135                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          17115100                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           1582628                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             18038083                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                15622031                       # Number of BTB hits
+system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.branchPred.BTBHitPct             86.605827                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 6627212                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect                  4                       # Number of incorrect RAS predictions.
+system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
+system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
+system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
+system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
+system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
+system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
+system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
+system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
+system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
+system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
+system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
+system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
+system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
+system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
+system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
+system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
+system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.dtb.inst_hits                            0                       # ITB inst hits
+system.cpu.dtb.inst_misses                          0                       # ITB inst misses
+system.cpu.dtb.read_hits                            0                       # DTB read hits
+system.cpu.dtb.read_misses                          0                       # DTB read misses
+system.cpu.dtb.write_hits                           0                       # DTB write hits
+system.cpu.dtb.write_misses                         0                       # DTB write misses
+system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                        0                       # DTB read accesses
+system.cpu.dtb.write_accesses                       0                       # DTB write accesses
+system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.dtb.hits                                 0                       # DTB hits
+system.cpu.dtb.misses                               0                       # DTB misses
+system.cpu.dtb.accesses                             0                       # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
+system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
+system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
+system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
+system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
+system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
+system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
+system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
+system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
+system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
+system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
+system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
+system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
+system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
+system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
+system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
+system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.itb.inst_hits                            0                       # ITB inst hits
+system.cpu.itb.inst_misses                          0                       # ITB inst misses
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
+system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.itb.hits                                 0                       # DTB hits
+system.cpu.itb.misses                               0                       # DTB misses
+system.cpu.itb.accesses                             0                       # DTB accesses
+system.cpu.workload.num_syscalls                  191                       # Number of system calls
+system.cpu.numCycles                        424754826                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.committedInsts                   273037856                       # Number of instructions committed
+system.cpu.committedOps                     327812213                       # Number of ops (including micro ops) committed
+system.cpu.discardedOps                       4318160                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
+system.cpu.cpi                               1.555663                       # CPI: cycles per instruction
+system.cpu.ipc                               0.642813                       # IPC: instructions per cycle
+system.cpu.tickCycles                       420995897                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                         3758929                       # Total number of cycles that the object has spent stopped
+system.cpu.icache.tags.replacements             36952                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1924.941242                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            73208047                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs             38889                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs           1882.487259                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst  1924.941242                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.939913                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.939913                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1937                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           58                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           83                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2           33                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3          275                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1488                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.945801                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses         146532763                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        146532763                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     73208047                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        73208047                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      73208047                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         73208047                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     73208047                       # number of overall hits
+system.cpu.icache.overall_hits::total        73208047                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst        38890                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total         38890                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst        38890                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total          38890                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst        38890                       # number of overall misses
+system.cpu.icache.overall_misses::total         38890                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    704978746                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    704978746                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    704978746                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    704978746                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    704978746                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    704978746                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     73246937                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     73246937                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     73246937                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     73246937                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     73246937                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     73246937                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000531                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000531                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000531                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000531                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000531                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000531                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18127.506968                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 18127.506968                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 18127.506968                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 18127.506968                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 18127.506968                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 18127.506968                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst        38890                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total        38890                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst        38890                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total        38890                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst        38890                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total        38890                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    625804254                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    625804254                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    625804254                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    625804254                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    625804254                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    625804254                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000531                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000531                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000531                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.000531                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000531                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.000531                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16091.649627                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16091.649627                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16091.649627                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 16091.649627                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16091.649627                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 16091.649627                       # average overall mshr miss latency
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.toL2Bus.throughput                13382365                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq          40531                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp         40530                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback         1009                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq         2869                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp         2869                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        77779                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side        10029                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total             87808                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2488896                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       353216                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total        2842112                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus           2842112                       # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy       23213500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy      59031746                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy       7495460                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
+system.cpu.l2cache.tags.replacements                0                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse         4198.136947                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs              35837                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs             5644                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             6.349575                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks   353.492029                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  3844.644919                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.010788                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.117329                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.128117                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024         5644                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           54                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1           38                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2           42                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         1251                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4         4259                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.172241                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses           363785                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses          363785                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.inst        35758                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total          35758                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks         1009                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total         1009                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.inst           16                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total           16                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst        35774                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total           35774                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst        35774                       # number of overall hits
+system.cpu.l2cache.overall_hits::total          35774                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst         4773                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total         4773                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.inst         2853                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total         2853                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         7626                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total          7626                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         7626                       # number of overall misses
+system.cpu.l2cache.overall_misses::total         7626                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    328392750                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total    328392750                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst    194194500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total    194194500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    522587250                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total    522587250                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    522587250                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    522587250                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst        40531                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total        40531                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks         1009                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total         1009                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.inst         2869                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total         2869                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst        43400                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total        43400                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst        43400                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total        43400                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.117762                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.117762                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst     0.994423                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.994423                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.175714                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.175714                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.175714                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.175714                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68802.168448                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 68802.168448                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 68066.771819                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68066.771819                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68527.045633                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 68527.045633                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68527.045633                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 68527.045633                       # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
+system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst           43                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total           43                       # number of ReadReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst           43                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total           43                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst           43                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total           43                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         4730                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total         4730                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst         2853                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total         2853                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         7583                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total         7583                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         7583                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total         7583                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    266719500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total    266719500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst    158382000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    158382000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    425101500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    425101500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    425101500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    425101500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.116701                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.116701                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst     0.994423                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.994423                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.174724                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.174724                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.174724                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.174724                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56388.900634                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56388.900634                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 55514.195584                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55514.195584                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56059.804827                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56059.804827                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56059.804827                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56059.804827                       # average overall mshr miss latency
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu.dcache.tags.replacements              1353                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          3085.890933                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           168774540                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs              4510                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs          37422.292683                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.inst  3085.890933                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.inst     0.753391                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.753391                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         3157                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           20                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           21                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           12                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3          671                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4         2433                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024     0.770752                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses         337568172                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        337568172                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.inst     86705299                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        86705299                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.inst     82047451                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       82047451                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.inst        10895                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total        10895                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.inst        10895                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total        10895                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.inst     168752750                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        168752750                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.inst    168752750                       # number of overall hits
+system.cpu.dcache.overall_hits::total       168752750                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.inst         2065                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total          2065                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.inst         5226                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total         5226                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.inst         7291                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total           7291                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.inst         7291                       # number of overall misses
+system.cpu.dcache.overall_misses::total          7291                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.inst    127204208                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total    127204208                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.inst    358851000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total    358851000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.inst    486055208                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total    486055208                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.inst    486055208                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total    486055208                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.inst     86707364                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     86707364                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.inst     82052677                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total     82052677                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.inst        10895                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total        10895                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.inst        10895                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total        10895                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.inst    168760041                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    168760041                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.inst    168760041                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    168760041                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.inst     0.000024                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.000024                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.inst     0.000064                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.000064                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.inst     0.000043                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.000043                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.inst     0.000043                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.000043                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 61600.100726                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 61600.100726                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 68666.475316                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 68666.475316                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66665.095049                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 66665.095049                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66665.095049                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 66665.095049                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks         1009                       # number of writebacks
+system.cpu.dcache.writebacks::total              1009                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.inst          424                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total          424                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.inst         2357                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total         2357                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.inst         2781                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total         2781                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.inst         2781                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total         2781                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.inst         1641                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total         1641                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.inst         2869                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total         2869                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.inst         4510                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total         4510                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.inst         4510                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total         4510                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst    100713040                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total    100713040                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst    197262500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total    197262500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.inst    297975540                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total    297975540                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.inst    297975540                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total    297975540                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst     0.000019                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000019                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst     0.000035                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000035                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.inst     0.000027                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.000027                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.inst     0.000027                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.000027                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 61372.967703                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61372.967703                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 68756.535378                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68756.535378                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 66069.964523                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 66069.964523                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 66069.964523                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 66069.964523                       # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt
index dff7f3d85..6d48708ce 100644
--- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt
@@ -1,61 +1,61 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.064767                       # Number of seconds simulated
-sim_ticks                                 64766858000                       # Number of ticks simulated
-final_tick                                64766858000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.058843                       # Number of seconds simulated
+sim_ticks                                 58842982000                       # Number of ticks simulated
+final_tick                                58842982000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 139181                       # Simulator instruction rate (inst/s)
-host_op_rate                                   177937                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               33015138                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 270440                       # Number of bytes of host memory used
-host_seconds                                  1961.73                       # Real time elapsed on the host
-sim_insts                                   273036725                       # Number of instructions simulated
-sim_ops                                     349064449                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 157851                       # Simulator instruction rate (inst/s)
+host_op_rate                                   189517                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               34018873                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 327492                       # Number of bytes of host memory used
+host_seconds                                  1729.72                       # Real time elapsed on the host
+sim_insts                                   273036656                       # Number of instructions simulated
+sim_ops                                     327810999                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            194688                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data            272960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total               467648                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       194688                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          194688                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst               3042                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data               4265                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                  7307                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst              3005982                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              4214501                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 7220483                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         3005982                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            3005982                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             3005982                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             4214501                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                7220483                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                          7307                       # Number of read requests accepted
+system.physmem.bytes_read::cpu.inst            189376                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data            272128                       # Number of bytes read from this memory
+system.physmem.bytes_read::total               461504                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       189376                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          189376                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst               2959                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data               4252                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                  7211                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst              3218328                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              4624647                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 7842974                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         3218328                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            3218328                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             3218328                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             4624647                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                7842974                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                          7211                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
-system.physmem.readBursts                        7307                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                        7211                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                   467648                       # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM                   461504                       # Total number of bytes read from DRAM
 system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
 system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                    467648                       # Total read bytes from the system interface side
+system.physmem.bytesReadSys                    461504                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
 system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs              3                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                 604                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                 805                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                 608                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                 526                       # Per bank write bursts
-system.physmem.perBankRdBursts::4                 446                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                 361                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                 162                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                 221                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs             11                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0                 592                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                 792                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                 603                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                 519                       # Per bank write bursts
+system.physmem.perBankRdBursts::4                 437                       # Per bank write bursts
+system.physmem.perBankRdBursts::5                 342                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                 159                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                 228                       # Per bank write bursts
 system.physmem.perBankRdBursts::8                 208                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                 290                       # Per bank write bursts
-system.physmem.perBankRdBursts::10                326                       # Per bank write bursts
-system.physmem.perBankRdBursts::11                415                       # Per bank write bursts
-system.physmem.perBankRdBursts::12                530                       # Per bank write bursts
-system.physmem.perBankRdBursts::13                688                       # Per bank write bursts
-system.physmem.perBankRdBursts::14                613                       # Per bank write bursts
+system.physmem.perBankRdBursts::9                 292                       # Per bank write bursts
+system.physmem.perBankRdBursts::10                317                       # Per bank write bursts
+system.physmem.perBankRdBursts::11                409                       # Per bank write bursts
+system.physmem.perBankRdBursts::12                526                       # Per bank write bursts
+system.physmem.perBankRdBursts::13                671                       # Per bank write bursts
+system.physmem.perBankRdBursts::14                612                       # Per bank write bursts
 system.physmem.perBankRdBursts::15                504                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
 system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
@@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                     64766656000                       # Total gap between requests
+system.physmem.totGap                     58842848000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                    7307                       # Read request sizes (log2)
+system.physmem.readPktSize::6                    7211                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -90,11 +90,11 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                      4265                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      2120                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       623                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                       229                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                        69                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                      4240                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      2012                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       646                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                       244                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                        68                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
@@ -186,29 +186,29 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples         1462                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      319.430917                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     186.825713                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     340.055999                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127            519     35.50%     35.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255          381     26.06%     61.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383          138      9.44%     71.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511           81      5.54%     76.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639           49      3.35%     79.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767           41      2.80%     82.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895           27      1.85%     84.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023           24      1.64%     86.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151          202     13.82%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total           1462                       # Bytes accessed per row activation
-system.physmem.totQLat                       61897500                       # Total ticks spent queuing
-system.physmem.totMemAccLat                 198903750                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                     36535000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        8470.99                       # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples         1405                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      327.288256                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     191.332764                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     342.731237                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127            492     35.02%     35.02% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255          350     24.91%     59.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383          132      9.40%     69.32% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511           82      5.84%     75.16% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639           53      3.77%     78.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767           47      3.35%     82.28% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895           27      1.92%     84.20% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023           22      1.57%     85.77% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151          200     14.23%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total           1405                       # Bytes accessed per row activation
+system.physmem.totQLat                       59614750                       # Total ticks spent queuing
+system.physmem.totMemAccLat                 194821000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                     36055000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        8267.20                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  27220.99                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           7.22                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  27017.20                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           7.84                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        7.22                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        7.84                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.06                       # Data bus utilization in percentage
@@ -216,44 +216,44 @@ system.physmem.busUtilRead                       0.06                       # Da
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.12                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                       5841                       # Number of row buffer hits during reads
+system.physmem.readRowHits                       5798                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   79.94                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   80.40                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                      8863645.27                       # Average gap between requests
-system.physmem.pageHitRate                      79.94                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE      60826618500                       # Time in different power states
-system.physmem.memoryStateTime::REF        2162680000                       # Time in different power states
+system.physmem.avgGap                      8160150.88                       # Average gap between requests
+system.physmem.pageHitRate                      80.40                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE      55121576750                       # Time in different power states
+system.physmem.memoryStateTime::REF        1964820000                       # Time in different power states
 system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT        1777002750                       # Time in different power states
+system.physmem.memoryStateTime::ACT        1754568250                       # Time in different power states
 system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.membus.throughput                      7220483                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq                4488                       # Transaction distribution
-system.membus.trans_dist::ReadResp               4488                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq                3                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp               3                       # Transaction distribution
-system.membus.trans_dist::ReadExReq              2819                       # Transaction distribution
-system.membus.trans_dist::ReadExResp             2819                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        14620                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                  14620                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       467648                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total              467648                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus                 467648                       # Total data (bytes)
+system.membus.throughput                      7842974                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq                4381                       # Transaction distribution
+system.membus.trans_dist::ReadResp               4381                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq               11                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp              11                       # Transaction distribution
+system.membus.trans_dist::ReadExReq              2830                       # Transaction distribution
+system.membus.trans_dist::ReadExResp             2830                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        14444                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                  14444                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       461504                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total              461504                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus                 461504                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy             8747000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy             8714000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           67869997                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy           67059990                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.branchPred.lookups                36489443                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          21873029                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           1677086                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             19094793                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                17269038                       # Number of BTB hits
+system.cpu.branchPred.lookups                36678579                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          19369962                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           1628976                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             19217639                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                17291098                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             90.438467                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 7051020                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect              13969                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             89.975142                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 7036393                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect               5252                       # Number of incorrect RAS predictions.
 system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -339,516 +339,519 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  191                       # Number of system calls
-system.cpu.numCycles                        129533717                       # number of cpu cycles simulated
+system.cpu.numCycles                        117685965                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           40065447                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      327212599                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    36489443                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           24320058                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      72959266                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 8220576                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles                9614052                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                   94                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles          1657                       # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles           76                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                  38688978                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                553522                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          129167933                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              3.246487                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.483221                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles           40172132                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      329927106                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    36678579                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           24327491                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      75600101                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 3327960                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles                  175                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles          2800                       # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles           41                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                  38768855                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                530996                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          117439229                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              3.389931                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.437439                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 56843632     44.01%     44.01% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  6961373      5.39%     49.40% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  5946764      4.60%     54.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  6307392      4.88%     58.88% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  5037669      3.90%     62.78% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  4117601      3.19%     65.97% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  3252291      2.52%     68.49% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  4297115      3.33%     71.82% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                 36404096     28.18%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 46731814     39.79%     39.79% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  7329854      6.24%     46.03% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  6574514      5.60%     51.63% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  6398088      5.45%     57.08% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  4252484      3.62%     60.70% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  5520861      4.70%     65.40% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  3987559      3.40%     68.80% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  3254311      2.77%     71.57% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 33389744     28.43%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            129167933                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.281698                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        2.526081                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 43040295                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles               8294549                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  70704377                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles                671384                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                6457328                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved              7532389                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                 70819                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              413867422                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                226829                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                6457328                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 45867800                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                  237018                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles         350499                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  68547941                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles               7707347                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              406294876                       # Number of instructions processed by rename
+system.cpu.fetch.rateDist::total            117439229                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.311665                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        2.803453                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 34271331                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              16148849                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  61039844                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               4384832                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                1594373                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              7530126                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                 70364                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              389722126                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                437543                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                1594373                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 37031203                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                 5569218                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles         387986                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  62601924                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              10254525                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              382340457                       # Number of instructions processed by rename
 system.cpu.rename.ROBFullEvents                    36                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                2372159                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                1808118                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                3023073                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.FullRegisterEvents            35743                       # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands           447044512                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            2837901709                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       1622364142                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups         210216215                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps             384566193                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 62478319                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts              12155                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts          12154                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  14556867                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            106022236                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            93881214                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           5184446                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          5926802                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  394612578                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded               23007                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 378124394                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued           2730874                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        45321613                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined    166213653                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved            887                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     129167933                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         2.927386                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        2.138502                       # Number of insts issued each cycle
+system.cpu.rename.IQFullEvents                4583661                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                2043172                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents                2989050                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.FullRegisterEvents            65700                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands           432935056                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            2729953830                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        376601971                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups         209126886                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps             372229219                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                 60705837                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts              14453                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts          15060                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  19856485                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             96101144                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            93882304                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           9920575                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         10878783                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  370378331                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded               25182                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 358744041                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued           1234352                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        42331510                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined    132428138                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved           3062                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     117439229                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         3.054721                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        2.223263                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            23289729     18.03%     18.03% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            17219322     13.33%     31.36% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            17000952     13.16%     44.52% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            16863081     13.06%     57.58% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            22471092     17.40%     74.98% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5            15547625     12.04%     87.01% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6            10749417      8.32%     95.33% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7             4018790      3.11%     98.45% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8             2007925      1.55%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            21274018     18.11%     18.11% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            14280801     12.16%     30.28% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            14869023     12.66%     42.94% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            13830819     11.78%     54.71% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            20620243     17.56%     72.27% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            15076681     12.84%     85.11% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6            10030176      8.54%     93.65% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             4472440      3.81%     97.46% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8             2985028      2.54%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       129167933                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       117439229                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                   70479      0.37%      0.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                   4864      0.03%      0.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      0.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      0.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      0.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      0.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      0.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      0.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      0.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      0.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      0.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      0.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      0.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      0.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      0.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      0.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      0.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      0.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      0.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      0.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd            116556      0.60%      1.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      1.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp             10208      0.05%      1.05% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt              2498      0.01%      1.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 3      0.00%      1.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc           192000      1.00%      2.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult             6622      0.03%      2.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc        104426      0.54%      2.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      2.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead               10354293     53.72%     56.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite               8412591     43.65%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                   30566      0.13%      0.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                   5035      0.02%      0.15% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      0.15% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      0.15% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      0.15% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      0.15% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      0.15% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      0.15% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      0.15% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      0.15% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      0.15% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      0.15% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      0.15% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      0.15% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      0.15% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      0.15% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      0.15% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      0.15% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      0.15% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      0.15% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd            218902      0.91%      1.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      1.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp            207576      0.86%      1.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt             15328      0.06%      1.98% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv              1824      0.01%      1.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc           338916      1.41%      3.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult            30886      0.13%      3.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc        130712      0.54%      4.07% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      4.07% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead               13684069     56.78%     60.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               9438097     39.16%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             127925021     33.83%     33.83% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult              2175908      0.58%     34.41% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     34.41% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     34.41% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     34.41% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     34.41% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     34.41% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     34.41% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     34.41% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     34.41% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     34.41% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     34.41% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    6      0.00%     34.41% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     34.41% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     34.41% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     34.41% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     34.41% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     34.41% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     34.41% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     34.41% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd         6792348      1.80%     36.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     36.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp         8524841      2.25%     38.46% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt         3465145      0.92%     39.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv         1600581      0.42%     39.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc       21035851      5.56%     45.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult        7175261      1.90%     47.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc      7134800      1.89%     49.15% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt         175287      0.05%     49.19% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            103072110     27.26%     76.45% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            89047235     23.55%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             114997382     32.06%     32.06% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult              2177572      0.61%     32.66% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     32.66% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     32.66% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     32.66% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     32.66% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     32.66% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     32.66% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     32.66% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     32.66% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     32.66% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     32.66% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     32.66% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     32.66% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     32.66% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     32.66% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     32.66% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     32.66% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     32.66% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     32.66% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd         6789188      1.89%     34.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     34.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp         8562613      2.39%     36.94% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt         3491505      0.97%     37.92% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv         1605361      0.45%     38.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc       21185799      5.91%     44.27% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult        7196318      2.01%     46.27% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc      7147739      1.99%     48.27% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt         183217      0.05%     48.32% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             95472748     26.61%     74.93% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            89934599     25.07%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              378124394                       # Type of FU issued
-system.cpu.iq.rate                           2.919119                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                    19274540                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.050974                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          653351237                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         300092831                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    252502629                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads           254070898                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes          139884609                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses    118704168                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              266903131                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses               130495803                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads         12681428                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              358744041                       # Type of FU issued
+system.cpu.iq.rate                           3.048316                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    24101911                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.067184                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          600140343                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         274631052                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    231134438                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads           260123231                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes          138160310                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses    119811956                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              246702850                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses               136143102                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads         13691987                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads     11373488                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        85866                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        20564                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores     11505631                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads     10368919                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses       114059                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        68397                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores     11506726                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads       299397                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked          2800                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads      1395971                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked           850                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                6457328                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                    4758                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                 17342                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           394637253                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            715920                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             106022236                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             93881214                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts              11972                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                    602                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                 17793                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          20564                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect        1298443                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       381522                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              1679965                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             373834206                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             101210545                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           4290188                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                1594373                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 4558099                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                129859                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           370404619                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts           1080086                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts              96101144                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             93882304                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts              14149                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                  21825                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                109033                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          68397                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        1241378                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       435662                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              1677040                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             354745077                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              94263609                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           3998964                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                          1668                       # number of nop insts executed
-system.cpu.iew.exec_refs                    189079864                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 32211788                       # Number of branches executed
-system.cpu.iew.exec_stores                   87869319                       # Number of stores executed
-system.cpu.iew.exec_rate                     2.885999                       # Inst execution rate
-system.cpu.iew.wb_sent                      372104883                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     371206797                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 194146455                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 400678068                       # num instructions consuming a value
+system.cpu.iew.exec_nop                          1106                       # number of nop insts executed
+system.cpu.iew.exec_refs                    182843438                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 32405794                       # Number of branches executed
+system.cpu.iew.exec_stores                   88579829                       # Number of stores executed
+system.cpu.iew.exec_rate                     3.014336                       # Inst execution rate
+system.cpu.iew.wb_sent                      352024494                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     350946394                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 175212964                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 355804607                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       2.865716                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.484545                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       2.982058                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.492442                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts        45577363                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts        42598489                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls           22120                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts           1607073                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    122710605                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     2.844620                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.797026                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts           1559369                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    111323846                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     2.944667                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.904010                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     31366686     25.56%     25.56% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     25118346     20.47%     46.03% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     12977285     10.58%     56.61% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     10004590      8.15%     64.76% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     11874018      9.68%     74.44% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      6164142      5.02%     79.46% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      4197962      3.42%     82.88% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      3586787      2.92%     85.80% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     17420789     14.20%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     29334492     26.35%     26.35% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     21002495     18.87%     45.22% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     12438899     11.17%     56.39% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      8843852      7.94%     64.33% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      8943359      8.03%     72.37% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      5286497      4.75%     77.12% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      3580965      3.22%     80.33% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      3438245      3.09%     83.42% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     18455042     16.58%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    122710605                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts            273037337                       # Number of instructions committed
-system.cpu.commit.committedOps              349065061                       # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total    111323846                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts            273037268                       # Number of instructions committed
+system.cpu.commit.committedOps              327811611                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                      177024331                       # Number of memory references committed
-system.cpu.commit.loads                      94648748                       # Number of loads committed
+system.cpu.commit.refs                      168107803                       # Number of memory references committed
+system.cpu.commit.loads                      85732225                       # Number of loads committed
 system.cpu.commit.membars                       11033                       # Number of memory barriers committed
-system.cpu.commit.branches                   30563497                       # Number of branches committed
+system.cpu.commit.branches                   30563485                       # Number of branches committed
 system.cpu.commit.fp_insts                  114216705                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                 279584611                       # Number of committed integer instructions.
+system.cpu.commit.int_insts                 258331174                       # Number of committed integer instructions.
 system.cpu.commit.function_calls              6225112                       # Number of function calls committed.
 system.cpu.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu        116648967     33.42%     33.42% # Class of committed instruction
-system.cpu.commit.op_class_0::IntMult         2145845      0.61%     34.03% # Class of committed instruction
-system.cpu.commit.op_class_0::IntDiv                0      0.00%     34.03% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatAdd              0      0.00%     34.03% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatCmp              0      0.00%     34.03% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatCvt              0      0.00%     34.03% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMult             0      0.00%     34.03% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatDiv              0      0.00%     34.03% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     34.03% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAdd               0      0.00%     34.03% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     34.03% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAlu               0      0.00%     34.03% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdCmp               0      0.00%     34.03% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdCvt               0      0.00%     34.03% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMisc              0      0.00%     34.03% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMult              0      0.00%     34.03% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     34.03% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdShift             0      0.00%     34.03% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     34.03% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     34.03% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatAdd      6594343      1.89%     35.92% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     35.92% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatCmp      7943502      2.28%     38.20% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatCvt      3118180      0.89%     39.09% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatDiv      1563217      0.45%     39.54% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMisc     19652356      5.63%     45.17% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMult      7136937      2.04%     47.21% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMultAcc      7062098      2.02%     49.24% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatSqrt       175285      0.05%     49.29% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead        94648748     27.11%     76.40% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite       82375583     23.60%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu        104312045     31.82%     31.82% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult         2145845      0.65%     32.48% # Class of committed instruction
+system.cpu.commit.op_class_0::IntDiv                0      0.00%     32.48% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatAdd              0      0.00%     32.48% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCmp              0      0.00%     32.48% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCvt              0      0.00%     32.48% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatMult             0      0.00%     32.48% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatDiv              0      0.00%     32.48% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     32.48% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAdd               0      0.00%     32.48% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     32.48% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAlu               0      0.00%     32.48% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCmp               0      0.00%     32.48% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCvt               0      0.00%     32.48% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMisc              0      0.00%     32.48% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMult              0      0.00%     32.48% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     32.48% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShift             0      0.00%     32.48% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     32.48% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     32.48% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAdd      6594343      2.01%     34.49% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     34.49% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCmp      7943502      2.42%     36.91% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCvt      3118180      0.95%     37.86% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatDiv      1563217      0.48%     38.34% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMisc     19652356      6.00%     44.33% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMult      7136937      2.18%     46.51% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMultAcc      7062098      2.15%     48.66% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatSqrt       175285      0.05%     48.72% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead        85732225     26.15%     74.87% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite       82375578     25.13%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total         349065061                       # Class of committed instruction
-system.cpu.commit.bw_lim_events              17420789                       # number cycles where commit BW limit reached
+system.cpu.commit.op_class_0::total         327811611                       # Class of committed instruction
+system.cpu.commit.bw_lim_events              18455042                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                    499929717                       # The number of ROB reads
-system.cpu.rob.rob_writes                   795751266                       # The number of ROB writes
-system.cpu.timesIdled                            6646                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                          365784                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts                   273036725                       # Number of Instructions Simulated
-system.cpu.committedOps                     349064449                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               0.474419                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.474419                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               2.107843                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         2.107843                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               1785673756                       # number of integer regfile reads
-system.cpu.int_regfile_writes               235086257                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                 188627632                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                133402932                       # number of floating regfile writes
-system.cpu.misc_regfile_reads              1210936846                       # number of misc regfile reads
+system.cpu.rob.rob_reads                    463276381                       # The number of ROB reads
+system.cpu.rob.rob_writes                   746948197                       # The number of ROB writes
+system.cpu.timesIdled                            5570                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                          246736                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts                   273036656                       # Number of Instructions Simulated
+system.cpu.committedOps                     327810999                       # Number of Ops (including micro ops) Simulated
+system.cpu.cpi                               0.431026                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.431026                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               2.320044                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         2.320044                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                344698387                       # number of integer regfile reads
+system.cpu.int_regfile_writes               141985623                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                 189510679                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                134618624                       # number of floating regfile writes
+system.cpu.cc_regfile_reads                1340695625                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                 80827327                       # number of cc regfile writes
+system.cpu.misc_regfile_reads              1216328122                       # number of misc regfile reads
 system.cpu.misc_regfile_writes               34421755                       # number of misc regfile writes
-system.cpu.toL2Bus.throughput                21331404                       # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq          17706                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp         17706                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback         1042                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq            3                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp            3                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq         2839                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp         2839                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        31825                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side        10310                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total             42135                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1018304                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       363072                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total        1381376                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus           1381376                       # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus          192                       # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy       11837000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.throughput                23209157                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq          17471                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp         17471                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback         1022                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq           12                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp           12                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq         2846                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp         2846                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        31432                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side        10234                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total             41666                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1005376                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       359424                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total        1364800                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus           1364800                       # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus          896                       # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy       11697999                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy      24407489                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy      24104992                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy       7420712                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy       7380470                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu.icache.tags.replacements             14019                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1852.281625                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            38671572                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs             15912                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs           2430.340121                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements             13841                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1830.861112                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            38751311                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs             15711                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs           2466.508243                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1852.281625                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.904434                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.904434                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024         1893                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           55                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_blocks::cpu.inst  1830.861112                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.893975                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.893975                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1870                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           53                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1           92                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          208                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3           12                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4         1526                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.924316                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          77393866                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         77393866                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     38671572                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        38671572                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      38671572                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         38671572                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     38671572                       # number of overall hits
-system.cpu.icache.overall_hits::total        38671572                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst        17404                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total         17404                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst        17404                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total          17404                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst        17404                       # number of overall misses
-system.cpu.icache.overall_misses::total         17404                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    452089736                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    452089736                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    452089736                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    452089736                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    452089736                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    452089736                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     38688976                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     38688976                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     38688976                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     38688976                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     38688976                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     38688976                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000450                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000450                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000450                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000450                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000450                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000450                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25976.197196                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 25976.197196                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 25976.197196                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 25976.197196                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 25976.197196                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 25976.197196                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs         1041                       # number of cycles access was blocked
+system.cpu.icache.tags.age_task_id_blocks_1024::2          194                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3            9                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1522                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.913086                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses          77553427                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         77553427                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     38751328                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        38751328                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      38751328                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         38751328                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     38751328                       # number of overall hits
+system.cpu.icache.overall_hits::total        38751328                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst        17524                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total         17524                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst        17524                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total          17524                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst        17524                       # number of overall misses
+system.cpu.icache.overall_misses::total         17524                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    439561740                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    439561740                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    439561740                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    439561740                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    439561740                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    439561740                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     38768852                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     38768852                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     38768852                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     38768852                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     38768852                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     38768852                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000452                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000452                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000452                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000452                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000452                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000452                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25083.413604                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 25083.413604                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 25083.413604                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 25083.413604                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 25083.413604                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 25083.413604                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs          684                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                22                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                12                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    47.318182                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs           57                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst         1490                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total         1490                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst         1490                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total         1490                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst         1490                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total         1490                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst        15914                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total        15914                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst        15914                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total        15914                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst        15914                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total        15914                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    359079759                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    359079759                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    359079759                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    359079759                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    359079759                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    359079759                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000411                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000411                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000411                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.000411                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000411                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.000411                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22563.765175                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22563.765175                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22563.765175                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 22563.765175                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22563.765175                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 22563.765175                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         1801                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total         1801                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst         1801                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total         1801                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst         1801                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total         1801                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst        15723                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total        15723                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst        15723                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total        15723                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst        15723                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total        15723                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    350218008                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    350218008                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    350218008                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    350218008                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    350218008                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    350218008                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000406                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000406                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000406                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.000406                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000406                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.000406                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22274.248426                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22274.248426                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22274.248426                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 22274.248426                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22274.248426                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 22274.248426                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse         3952.099762                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs              13258                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs             5413                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             2.449289                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.tagsinuse         3837.051468                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs              13121                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs             5294                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             2.478466                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks   379.383220                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  2782.580366                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   790.136176                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.011578                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.084918                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.024113                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.120609                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024         5413                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           60                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1           74                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         1243                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3           15                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4         4021                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.165192                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses           180948                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses          180948                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst        12858                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data          305                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total          13163                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks         1042                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total         1042                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data           20                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total           20                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst        12858                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data          325                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total           13183                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst        12858                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data          325                       # number of overall hits
-system.cpu.l2cache.overall_hits::total          13183                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst         3053                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data         1487                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total         4540                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data            3                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total            3                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data         2819                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total         2819                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         3053                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data         4306                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total          7359                       # number of demand (read+write) misses
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-system.cpu.l2cache.overall_misses::total         7359                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    214550000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data    110145250                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total    324695250                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    200330000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total    200330000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    214550000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data    310475250                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total    525025250                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    214550000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data    310475250                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total    525025250                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst        15911                       # number of ReadReq accesses(hits+misses)
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-system.cpu.l2cache.ReadReq_accesses::total        17703                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks         1042                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total         1042                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data            3                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total            3                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data         2839                       # number of ReadExReq accesses(hits+misses)
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-system.cpu.l2cache.overall_accesses::cpu.data         4631                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total        20542                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.191880                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.829799                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.256454                       # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data            1                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.992955                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.992955                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.191880                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.929821                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.358242                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.191880                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.929821                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.358242                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70275.139207                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74072.125084                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 71518.777533                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71064.207166                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71064.207166                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70275.139207                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72102.937761                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 71344.646012                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70275.139207                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72102.937761                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 71344.646012                       # average overall miss latency
+system.cpu.l2cache.tags.occ_blocks::writebacks   357.151307                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  2707.112582                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data   772.787579                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.010899                       # Average percentage of cache occupancy
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+system.cpu.l2cache.tags.occ_percent::total     0.117098                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024         5294                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           56                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1           69                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         1246                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3           12                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4         3911                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.161560                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses           178837                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses          178837                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.inst        12742                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data          286                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total          13028                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks         1022                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total         1022                       # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data            1                       # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total            1                       # number of UpgradeReq hits
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+system.cpu.l2cache.overall_hits::total          13044                       # number of overall hits
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+system.cpu.l2cache.ReadReq_misses::total         4429                       # number of ReadReq misses
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+system.cpu.l2cache.overall_miss_latency::cpu.data    309255000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    516287250                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst        15709                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data         1748                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total        17457                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks         1022                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total         1022                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data           12                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total           12                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data         2846                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total         2846                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst        15709                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data         4594                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total        20303                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst        15709                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data         4594                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total        20303                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.188873                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.836384                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.253709                       # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.916667                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total     0.916667                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.994378                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.994378                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.188873                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.934262                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.357533                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.188873                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.934262                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.357533                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69778.311426                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73076.436389                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 70867.012870                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71525.530035                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71525.530035                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69778.311426                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72053.821062                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 71123.742940                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69778.311426                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72053.821062                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 71123.742940                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -857,202 +860,218 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst           11                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           41                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total           52                       # number of ReadReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst           11                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data           41                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total           52                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst           11                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data           41                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total           52                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3042                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data         1446                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total         4488                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data            3                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total            3                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         2819                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total         2819                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         3042                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data         4265                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total         7307                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         3042                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data         4265                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total         7307                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    175689250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     89225250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total    264914500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data        30003                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total        30003                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    165556500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    165556500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    175689250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    254781750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    430471000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    175689250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    254781750                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    430471000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.191188                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.806920                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.253516                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.992955                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.992955                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.191188                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.920967                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.355710                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.191188                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.920967                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.355710                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57754.520053                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61704.875519                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59027.295009                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        10001                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        10001                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58728.804541                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58728.804541                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57754.520053                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59737.807737                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58912.139045                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57754.520053                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59737.807737                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58912.139045                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            8                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           40                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total           48                       # number of ReadReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst            8                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data           40                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total           48                       # number of demand (read+write) MSHR hits
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+system.cpu.l2cache.overall_mshr_hits::cpu.data           40                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total           48                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         2959                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data         1422                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total         4381                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data           11                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total           11                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         2830                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total         2830                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         2959                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data         4252                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total         7211                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         2959                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data         4252                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total         7211                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    169394250                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     86707000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total    256101250                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       112009                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       112009                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    167488250                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    167488250                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    169394250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    254195250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    423589500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    169394250                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    254195250                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    423589500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.188363                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.813501                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.250960                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.916667                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.916667                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.994378                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.994378                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.188363                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.925555                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.355169                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.188363                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.925555                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.355169                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57247.127408                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60975.386779                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58457.258617                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10182.636364                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10182.636364                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59183.127208                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59183.127208                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57247.127408                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59782.514111                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58742.130079                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57247.127408                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59782.514111                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58742.130079                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements              1426                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          3109.599416                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           170089338                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs              4631                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs          36728.425394                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.replacements              1384                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          3114.575432                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           161730326                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs              4594                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs          35204.685677                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  3109.599416                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.759180                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.759180                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024         3205                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_blocks::cpu.data  3114.575432                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.760394                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.760394                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         3210                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           23                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1           36                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2          688                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           27                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          686                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::3           12                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::4         2446                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024     0.782471                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         340235219                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        340235219                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     88036573                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        88036573                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     82030829                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       82030829                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data        11027                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total        11027                       # number of LoadLockedReq hits
+system.cpu.dcache.tags.age_task_id_blocks_1024::4         2462                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024     0.783691                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses         323517792                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        323517792                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     79590771                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        79590771                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     82030417                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       82030417                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data        87045                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total         87045                       # number of SoftPFReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data        11127                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total        11127                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data        10895                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total        10895                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     170067402                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        170067402                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    170067402                       # number of overall hits
-system.cpu.dcache.overall_hits::total       170067402                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data         4132                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total          4132                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data        21836                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total        21836                       # number of WriteReq misses
+system.cpu.dcache.demand_hits::cpu.data     161621188                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        161621188                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    161708233                       # number of overall hits
+system.cpu.dcache.overall_hits::total       161708233                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data         4059                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total          4059                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data        22243                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total        22243                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data           40                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total           40                       # number of SoftPFReq misses
 system.cpu.dcache.LoadLockedReq_misses::cpu.data            2                       # number of LoadLockedReq misses
 system.cpu.dcache.LoadLockedReq_misses::total            2                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data        25968                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total          25968                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data        25968                       # number of overall misses
-system.cpu.dcache.overall_misses::total         25968                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data    240617705                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total    240617705                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   1280155018                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   1280155018                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_misses::cpu.data        26302                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total          26302                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data        26342                       # number of overall misses
+system.cpu.dcache.overall_misses::total         26342                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data    234715222                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total    234715222                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   1291834537                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   1291834537                       # number of WriteReq miss cycles
 system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       170250                       # number of LoadLockedReq miss cycles
 system.cpu.dcache.LoadLockedReq_miss_latency::total       170250                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data   1520772723                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total   1520772723                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data   1520772723                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total   1520772723                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     88040705                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     88040705                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data     82052665                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total     82052665                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data        11029                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total        11029                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.demand_miss_latency::cpu.data   1526549759                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total   1526549759                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data   1526549759                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total   1526549759                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     79594830                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     79594830                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data     82052660                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total     82052660                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data        87085                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total        87085                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data        11129                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total        11129                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data        10895                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total        10895                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    170093370                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    170093370                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    170093370                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    170093370                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000047                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.000047                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000266                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.000266                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.000181                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.000181                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.000153                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.000153                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.000153                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.000153                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58232.745644                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 58232.745644                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 58625.893845                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 58625.893845                       # average WriteReq miss latency
+system.cpu.dcache.demand_accesses::cpu.data    161647490                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    161647490                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    161734575                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    161734575                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000051                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.000051                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000271                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.000271                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.000459                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.000459                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.000180                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.000180                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.000163                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.000163                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.000163                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.000163                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 57825.873861                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 57825.873861                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 58078.251000                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 58078.251000                       # average WriteReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        85125                       # average LoadLockedReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        85125                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 58563.336530                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 58563.336530                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 58563.336530                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 58563.336530                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs        30153                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets         1162                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs               553                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets              12                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    54.526221                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets    96.833333                       # average number of cycles each access was blocked
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 58039.303437                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 58039.303437                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 57951.171475                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 57951.171475                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs        32404                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets         1444                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs               548                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets              14                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    59.131387                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets   103.142857                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks         1042                       # number of writebacks
-system.cpu.dcache.writebacks::total              1042                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data         2339                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total         2339                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data        18995                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total        18995                       # number of WriteReq MSHR hits
+system.cpu.dcache.writebacks::writebacks         1022                       # number of writebacks
+system.cpu.dcache.writebacks::total              1022                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data         2332                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total         2332                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data        19388                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total        19388                       # number of WriteReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            2                       # number of LoadLockedReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::total            2                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data        21334                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total        21334                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data        21334                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total        21334                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data         1793                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total         1793                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data         2841                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total         2841                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data         4634                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total         4634                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data         4634                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total         4634                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data    115097041                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total    115097041                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    203424247                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total    203424247                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data    318521288                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total    318521288                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data    318521288                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total    318521288                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000020                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000020                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.demand_mshr_hits::cpu.data        21720                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total        21720                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data        21720                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total        21720                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data         1727                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total         1727                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data         2855                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total         2855                       # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data           24                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total           24                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data         4582                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total         4582                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data         4606                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total         4606                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data    109924790                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total    109924790                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    205574740                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total    205574740                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data      1745000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total      1745000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data    315499530                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total    315499530                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data    317244530                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total    317244530                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000022                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000022                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000035                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000035                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000027                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.000027                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000027                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.000027                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 64192.437814                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 64192.437814                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71603.043647                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71603.043647                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68735.711696                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 68735.711696                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68735.711696                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 68735.711696                       # average overall mshr miss latency
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.000276                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.000276                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000028                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.000028                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000028                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.000028                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 63650.718008                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 63650.718008                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72005.162872                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72005.162872                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 72708.333333                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 72708.333333                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68856.292012                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 68856.292012                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68876.363439                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 68876.363439                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt
index edb370512..d78fd5112 100644
--- a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt
@@ -1,42 +1,42 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.212344                       # Number of seconds simulated
-sim_ticks                                212344043000                       # Number of ticks simulated
-final_tick                               212344043000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.201717                       # Number of seconds simulated
+sim_ticks                                201717313500                       # Number of ticks simulated
+final_tick                               201717313500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1152169                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1472992                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              896053064                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 309060                       # Number of bytes of host memory used
-host_seconds                                   236.98                       # Real time elapsed on the host
-sim_insts                                   273037663                       # Number of instructions simulated
-sim_ops                                     349065399                       # Number of ops (including micro ops) simulated
+host_inst_rate                                1169681                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1404332                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              864148101                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 314684                       # Number of bytes of host memory used
+host_seconds                                   233.43                       # Real time elapsed on the host
+sim_insts                                   273037594                       # Number of instructions simulated
+sim_ops                                     327811949                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst        1394641404                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data         480709268                       # Number of bytes read from this memory
-system.physmem.bytes_read::total           1875350672                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst   1394641404                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total      1394641404                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::cpu.data      400047783                       # Number of bytes written to this memory
-system.physmem.bytes_written::total         400047783                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst          348660351                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data           94582505                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total             443242856                       # Number of read requests responded to by this memory
-system.physmem.num_writes::cpu.data          82063572                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total             82063572                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst           6567838609                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data           2263822715                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              8831661324                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst      6567838609                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total         6567838609                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data          1883960470                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total             1883960470                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst          6567838609                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data          4147783185                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total            10715621794                       # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput                  10715621794                       # Throughput (bytes/s)
-system.membus.data_through_bus             2275398455                       # Total data (bytes)
+system.physmem.bytes_read::cpu.inst        1394641092                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data         480709216                       # Number of bytes read from this memory
+system.physmem.bytes_read::total           1875350308                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst   1394641092                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total      1394641092                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::cpu.data      400047763                       # Number of bytes written to this memory
+system.physmem.bytes_written::total         400047763                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst          348660273                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data           86300511                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total             434960784                       # Number of read requests responded to by this memory
+system.physmem.num_writes::cpu.data          82063567                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total             82063567                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst           6913839312                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data           2383083572                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              9296922884                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst      6913839312                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total         6913839312                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data          1983209850                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total             1983209850                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst          6913839312                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data          4366293422                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total            11280132734                       # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput                  11280132734                       # Throughput (bytes/s)
+system.membus.data_through_bus             2275398071                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
@@ -124,63 +124,65 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  191                       # Number of system calls
-system.cpu.numCycles                        424688087                       # number of cpu cycles simulated
+system.cpu.numCycles                        403434628                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                   273037663                       # Number of instructions committed
-system.cpu.committedOps                     349065399                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses             279584918                       # Number of integer alu accesses
+system.cpu.committedInsts                   273037594                       # Number of instructions committed
+system.cpu.committedOps                     327811949                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses             258331481                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses              114216705                       # Number of float alu accesses
 system.cpu.num_func_calls                    12448615                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts     18105897                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                    279584918                       # number of integer instructions
+system.cpu.num_conditional_control_insts     15799338                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                    258331481                       # number of integer instructions
 system.cpu.num_fp_insts                     114216705                       # number of float instructions
-system.cpu.num_int_register_reads          2254222459                       # number of times the integer registers were read
-system.cpu.num_int_register_writes          251197905                       # number of times the integer registers were written
+system.cpu.num_int_register_reads          1174407516                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          162499657                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads            180262959                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes           126152315                       # number of times the floating registers were written
-system.cpu.num_mem_refs                     177024356                       # number of memory refs
-system.cpu.num_load_insts                    94648757                       # Number of load instructions
-system.cpu.num_store_insts                   82375599                       # Number of store instructions
+system.cpu.num_cc_register_reads            985884623                       # number of times the CC registers were read
+system.cpu.num_cc_register_writes            76361749                       # number of times the CC registers were written
+system.cpu.num_mem_refs                     168107829                       # number of memory refs
+system.cpu.num_load_insts                    85732235                       # Number of load instructions
+system.cpu.num_store_insts                   82375594                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                  424688087                       # Number of busy cycles
+system.cpu.num_busy_cycles                  403434628                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
-system.cpu.Branches                          30563502                       # Number of branches fetched
+system.cpu.Branches                          30563490                       # Number of branches fetched
 system.cpu.op_class::No_OpClass                     0      0.00%      0.00% # Class of executed instruction
-system.cpu.op_class::IntAlu                 116649415     33.42%     33.42% # Class of executed instruction
-system.cpu.op_class::IntMult                  2145905      0.61%     34.03% # Class of executed instruction
-system.cpu.op_class::IntDiv                         0      0.00%     34.03% # Class of executed instruction
-system.cpu.op_class::FloatAdd                       0      0.00%     34.03% # Class of executed instruction
-system.cpu.op_class::FloatCmp                       0      0.00%     34.03% # Class of executed instruction
-system.cpu.op_class::FloatCvt                       0      0.00%     34.03% # Class of executed instruction
-system.cpu.op_class::FloatMult                      0      0.00%     34.03% # Class of executed instruction
-system.cpu.op_class::FloatDiv                       0      0.00%     34.03% # Class of executed instruction
-system.cpu.op_class::FloatSqrt                      0      0.00%     34.03% # Class of executed instruction
-system.cpu.op_class::SimdAdd                        0      0.00%     34.03% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc                     0      0.00%     34.03% # Class of executed instruction
-system.cpu.op_class::SimdAlu                        0      0.00%     34.03% # Class of executed instruction
-system.cpu.op_class::SimdCmp                        0      0.00%     34.03% # Class of executed instruction
-system.cpu.op_class::SimdCvt                        0      0.00%     34.03% # Class of executed instruction
-system.cpu.op_class::SimdMisc                       0      0.00%     34.03% # Class of executed instruction
-system.cpu.op_class::SimdMult                       0      0.00%     34.03% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc                    0      0.00%     34.03% # Class of executed instruction
-system.cpu.op_class::SimdShift                      0      0.00%     34.03% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc                   0      0.00%     34.03% # Class of executed instruction
-system.cpu.op_class::SimdSqrt                       0      0.00%     34.03% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd             6594343      1.89%     35.92% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu                   0      0.00%     35.92% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp             7943502      2.28%     38.20% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt             3118180      0.89%     39.09% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv             1563217      0.45%     39.54% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc           19652356      5.63%     45.17% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult            7136937      2.04%     47.21% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc         7062098      2.02%     49.24% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt             175285      0.05%     49.29% # Class of executed instruction
-system.cpu.op_class::MemRead                 94648757     27.11%     76.40% # Class of executed instruction
-system.cpu.op_class::MemWrite                82375599     23.60%    100.00% # Class of executed instruction
+system.cpu.op_class::IntAlu                 104312492     31.82%     31.82% # Class of executed instruction
+system.cpu.op_class::IntMult                  2145905      0.65%     32.48% # Class of executed instruction
+system.cpu.op_class::IntDiv                         0      0.00%     32.48% # Class of executed instruction
+system.cpu.op_class::FloatAdd                       0      0.00%     32.48% # Class of executed instruction
+system.cpu.op_class::FloatCmp                       0      0.00%     32.48% # Class of executed instruction
+system.cpu.op_class::FloatCvt                       0      0.00%     32.48% # Class of executed instruction
+system.cpu.op_class::FloatMult                      0      0.00%     32.48% # Class of executed instruction
+system.cpu.op_class::FloatDiv                       0      0.00%     32.48% # Class of executed instruction
+system.cpu.op_class::FloatSqrt                      0      0.00%     32.48% # Class of executed instruction
+system.cpu.op_class::SimdAdd                        0      0.00%     32.48% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc                     0      0.00%     32.48% # Class of executed instruction
+system.cpu.op_class::SimdAlu                        0      0.00%     32.48% # Class of executed instruction
+system.cpu.op_class::SimdCmp                        0      0.00%     32.48% # Class of executed instruction
+system.cpu.op_class::SimdCvt                        0      0.00%     32.48% # Class of executed instruction
+system.cpu.op_class::SimdMisc                       0      0.00%     32.48% # Class of executed instruction
+system.cpu.op_class::SimdMult                       0      0.00%     32.48% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc                    0      0.00%     32.48% # Class of executed instruction
+system.cpu.op_class::SimdShift                      0      0.00%     32.48% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc                   0      0.00%     32.48% # Class of executed instruction
+system.cpu.op_class::SimdSqrt                       0      0.00%     32.48% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd             6594343      2.01%     34.49% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu                   0      0.00%     34.49% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp             7943502      2.42%     36.91% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt             3118180      0.95%     37.86% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv             1563217      0.48%     38.34% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc           19652356      6.00%     44.33% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult            7136937      2.18%     46.51% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc         7062098      2.15%     48.66% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt             175285      0.05%     48.72% # Class of executed instruction
+system.cpu.op_class::MemRead                 85732235     26.15%     74.87% # Class of executed instruction
+system.cpu.op_class::MemWrite                82375594     25.13%    100.00% # Class of executed instruction
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::total                  349065594                       # Class of executed instruction
+system.cpu.op_class::total                  327812144                       # Class of executed instruction
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt
index 23ba68f1d..57cca8ea4 100644
--- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt
@@ -1,16 +1,16 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.525834                       # Number of seconds simulated
-sim_ticks                                525834342000                       # Number of ticks simulated
-final_tick                               525834342000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.517235                       # Number of seconds simulated
+sim_ticks                                517235411000                       # Number of ticks simulated
+final_tick                               517235411000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 605985                       # Simulator instruction rate (inst/s)
-host_op_rate                                   774729                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1168322503                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 318808                       # Number of bytes of host memory used
-host_seconds                                   450.08                       # Real time elapsed on the host
-sim_insts                                   272739283                       # Number of instructions simulated
-sim_ops                                     348687122                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 749544                       # Simulator instruction rate (inst/s)
+host_op_rate                                   899855                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1421469107                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 324416                       # Number of bytes of host memory used
+host_seconds                                   363.87                       # Real time elapsed on the host
+sim_insts                                   272739285                       # Number of instructions simulated
+sim_ops                                     327433743                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst            166976                       # Number of bytes read from this memory
@@ -21,15 +21,15 @@ system.physmem.bytes_inst_read::total          166976                       # Nu
 system.physmem.num_reads::cpu.inst               2609                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data               4223                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                  6832                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst               317545                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data               513987                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                  831532                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          317545                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             317545                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              317545                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data              513987                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                 831532                       # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput                       831532                       # Throughput (bytes/s)
+system.physmem.bw_read::cpu.inst               322824                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data               522532                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                  845356                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          322824                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             322824                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              322824                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data              522532                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                 845356                       # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput                       845356                       # Throughput (bytes/s)
 system.membus.trans_dist::ReadReq                3976                       # Transaction distribution
 system.membus.trans_dist::ReadResp               3976                       # Transaction distribution
 system.membus.trans_dist::ReadExReq              2856                       # Transaction distribution
@@ -40,9 +40,9 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port
 system.membus.tot_pkt_size::total              437248                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.data_through_bus                 437248                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy             6832000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy             7260000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           61488000                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy           61915000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
@@ -130,73 +130,75 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  191                       # Number of system calls
-system.cpu.numCycles                       1051668684                       # number of cpu cycles simulated
+system.cpu.numCycles                       1034470822                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                   272739283                       # Number of instructions committed
-system.cpu.committedOps                     348687122                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses             279584917                       # Number of integer alu accesses
+system.cpu.committedInsts                   272739285                       # Number of instructions committed
+system.cpu.committedOps                     327433743                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses             258331537                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses              114216705                       # Number of float alu accesses
 system.cpu.num_func_calls                    12448615                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts     18105896                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                    279584917                       # number of integer instructions
+system.cpu.num_conditional_control_insts     15799349                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                    258331537                       # number of integer instructions
 system.cpu.num_fp_insts                     114216705                       # number of float instructions
-system.cpu.num_int_register_reads          2579483474                       # number of times the integer registers were read
-system.cpu.num_int_register_writes          251197902                       # number of times the integer registers were written
+system.cpu.num_int_register_reads          1215888421                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          162499693                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads            180262959                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes           126152315                       # number of times the floating registers were written
-system.cpu.num_mem_refs                     177024356                       # number of memory refs
-system.cpu.num_load_insts                    94648757                       # Number of load instructions
+system.cpu.num_cc_register_reads           1242915500                       # number of times the CC registers were read
+system.cpu.num_cc_register_writes            76361814                       # number of times the CC registers were written
+system.cpu.num_mem_refs                     168107847                       # number of memory refs
+system.cpu.num_load_insts                    85732248                       # Number of load instructions
 system.cpu.num_store_insts                   82375599                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                 1051668684                       # Number of busy cycles
+system.cpu.num_busy_cycles                 1034470822                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
-system.cpu.Branches                          30563501                       # Number of branches fetched
+system.cpu.Branches                          30563502                       # Number of branches fetched
 system.cpu.op_class::No_OpClass                     0      0.00%      0.00% # Class of executed instruction
-system.cpu.op_class::IntAlu                 116649413     33.42%     33.42% # Class of executed instruction
-system.cpu.op_class::IntMult                  2145905      0.61%     34.03% # Class of executed instruction
-system.cpu.op_class::IntDiv                         0      0.00%     34.03% # Class of executed instruction
-system.cpu.op_class::FloatAdd                       0      0.00%     34.03% # Class of executed instruction
-system.cpu.op_class::FloatCmp                       0      0.00%     34.03% # Class of executed instruction
-system.cpu.op_class::FloatCvt                       0      0.00%     34.03% # Class of executed instruction
-system.cpu.op_class::FloatMult                      0      0.00%     34.03% # Class of executed instruction
-system.cpu.op_class::FloatDiv                       0      0.00%     34.03% # Class of executed instruction
-system.cpu.op_class::FloatSqrt                      0      0.00%     34.03% # Class of executed instruction
-system.cpu.op_class::SimdAdd                        0      0.00%     34.03% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc                     0      0.00%     34.03% # Class of executed instruction
-system.cpu.op_class::SimdAlu                        0      0.00%     34.03% # Class of executed instruction
-system.cpu.op_class::SimdCmp                        0      0.00%     34.03% # Class of executed instruction
-system.cpu.op_class::SimdCvt                        0      0.00%     34.03% # Class of executed instruction
-system.cpu.op_class::SimdMisc                       0      0.00%     34.03% # Class of executed instruction
-system.cpu.op_class::SimdMult                       0      0.00%     34.03% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc                    0      0.00%     34.03% # Class of executed instruction
-system.cpu.op_class::SimdShift                      0      0.00%     34.03% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc                   0      0.00%     34.03% # Class of executed instruction
-system.cpu.op_class::SimdSqrt                       0      0.00%     34.03% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd             6594343      1.89%     35.92% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu                   0      0.00%     35.92% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp             7943502      2.28%     38.20% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt             3118180      0.89%     39.09% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv             1563217      0.45%     39.54% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc           19652356      5.63%     45.17% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult            7136937      2.04%     47.21% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc         7062098      2.02%     49.24% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt             175285      0.05%     49.29% # Class of executed instruction
-system.cpu.op_class::MemRead                 94648757     27.11%     76.40% # Class of executed instruction
-system.cpu.op_class::MemWrite                82375599     23.60%    100.00% # Class of executed instruction
+system.cpu.op_class::IntAlu                 104312543     31.82%     31.82% # Class of executed instruction
+system.cpu.op_class::IntMult                  2145905      0.65%     32.48% # Class of executed instruction
+system.cpu.op_class::IntDiv                         0      0.00%     32.48% # Class of executed instruction
+system.cpu.op_class::FloatAdd                       0      0.00%     32.48% # Class of executed instruction
+system.cpu.op_class::FloatCmp                       0      0.00%     32.48% # Class of executed instruction
+system.cpu.op_class::FloatCvt                       0      0.00%     32.48% # Class of executed instruction
+system.cpu.op_class::FloatMult                      0      0.00%     32.48% # Class of executed instruction
+system.cpu.op_class::FloatDiv                       0      0.00%     32.48% # Class of executed instruction
+system.cpu.op_class::FloatSqrt                      0      0.00%     32.48% # Class of executed instruction
+system.cpu.op_class::SimdAdd                        0      0.00%     32.48% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc                     0      0.00%     32.48% # Class of executed instruction
+system.cpu.op_class::SimdAlu                        0      0.00%     32.48% # Class of executed instruction
+system.cpu.op_class::SimdCmp                        0      0.00%     32.48% # Class of executed instruction
+system.cpu.op_class::SimdCvt                        0      0.00%     32.48% # Class of executed instruction
+system.cpu.op_class::SimdMisc                       0      0.00%     32.48% # Class of executed instruction
+system.cpu.op_class::SimdMult                       0      0.00%     32.48% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc                    0      0.00%     32.48% # Class of executed instruction
+system.cpu.op_class::SimdShift                      0      0.00%     32.48% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc                   0      0.00%     32.48% # Class of executed instruction
+system.cpu.op_class::SimdSqrt                       0      0.00%     32.48% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd             6594343      2.01%     34.49% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu                   0      0.00%     34.49% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp             7943502      2.42%     36.91% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt             3118180      0.95%     37.86% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv             1563217      0.48%     38.34% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc           19652356      6.00%     44.33% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult            7136937      2.18%     46.51% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc         7062098      2.15%     48.66% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt             175285      0.05%     48.72% # Class of executed instruction
+system.cpu.op_class::MemRead                 85732248     26.15%     74.87% # Class of executed instruction
+system.cpu.op_class::MemWrite                82375599     25.13%    100.00% # Class of executed instruction
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::total                  349065592                       # Class of executed instruction
+system.cpu.op_class::total                  327812213                       # Class of executed instruction
 system.cpu.icache.tags.replacements             13796                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1765.993223                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           348644747                       # Total number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse          1766.007645                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           348644749                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs             15603                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          22344.725181                       # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs          22344.725309                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1765.993223                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.862301                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.862301                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst  1766.007645                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.862308                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.862308                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         1807                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           30                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1           66                       # Occupied blocks per task id
@@ -204,44 +206,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2           26
 system.cpu.icache.tags.age_task_id_blocks_1024::3          161                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::4         1524                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.882324                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         697336303                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        697336303                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    348644747                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       348644747                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     348644747                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        348644747                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    348644747                       # number of overall hits
-system.cpu.icache.overall_hits::total       348644747                       # number of overall hits
+system.cpu.icache.tags.tag_accesses         697336307                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        697336307                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    348644749                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       348644749                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     348644749                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        348644749                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    348644749                       # number of overall hits
+system.cpu.icache.overall_hits::total       348644749                       # number of overall hits
 system.cpu.icache.ReadReq_misses::cpu.inst        15603                       # number of ReadReq misses
 system.cpu.icache.ReadReq_misses::total         15603                       # number of ReadReq misses
 system.cpu.icache.demand_misses::cpu.inst        15603                       # number of demand (read+write) misses
 system.cpu.icache.demand_misses::total          15603                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst        15603                       # number of overall misses
 system.cpu.icache.overall_misses::total         15603                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    312417000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    312417000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    312417000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    312417000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    312417000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    312417000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    348660350                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    348660350                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    348660350                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    348660350                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    348660350                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    348660350                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    312527500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    312527500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    312527500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    312527500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    312527500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    312527500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    348660352                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    348660352                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    348660352                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    348660352                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    348660352                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    348660352                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000045                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000045                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000045                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000045                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000045                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000045                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20022.880215                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 20022.880215                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 20022.880215                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 20022.880215                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 20022.880215                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 20022.880215                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20029.962187                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 20029.962187                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 20029.962187                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 20029.962187                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 20029.962187                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 20029.962187                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -256,38 +258,38 @@ system.cpu.icache.demand_mshr_misses::cpu.inst        15603
 system.cpu.icache.demand_mshr_misses::total        15603                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst        15603                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total        15603                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    281211000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    281211000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    281211000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    281211000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    281211000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    281211000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    281321500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    281321500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    281321500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    281321500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    281321500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    281321500                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000045                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000045                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000045                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000045                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000045                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000045                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18022.880215                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18022.880215                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18022.880215                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 18022.880215                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18022.880215                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 18022.880215                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18029.962187                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18029.962187                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18029.962187                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 18029.962187                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18029.962187                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 18029.962187                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse         3487.723791                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse         3487.764987                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs              13310                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs             4882                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs             2.726342                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks   341.616093                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  2408.399470                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   737.708228                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.010425                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::writebacks   341.623056                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  2408.427143                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data   737.714788                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.010426                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.073499                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.022513                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.106437                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.106438                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024         4882                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0           35                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::1           46                       # Occupied blocks per task id
@@ -321,17 +323,17 @@ system.cpu.l2cache.demand_misses::total          6832                       # nu
 system.cpu.l2cache.overall_misses::cpu.inst         2609                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data         4223                       # number of overall misses
 system.cpu.l2cache.overall_misses::total         6832                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    135668000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data     71084000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total    206752000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    148512000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total    148512000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    135668000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data    219596000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total    355264000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    135668000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data    219596000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total    355264000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    135778500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data     71271000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total    207049500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    148649500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total    148649500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    135778500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data    219920500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total    355699000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    135778500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data    219920500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    355699000                       # number of overall miss cycles
 system.cpu.l2cache.ReadReq_accesses::cpu.inst        15603                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::cpu.data         1606                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::total        17209                       # number of ReadReq accesses(hits+misses)
@@ -356,17 +358,17 @@ system.cpu.l2cache.demand_miss_rate::total     0.340222                       #
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.167211                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.943055                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.340222                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst        52000                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data        52000                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total        52000                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        52000                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total        52000                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data        52000                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total        52000                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data        52000                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total        52000                       # average overall miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52042.353392                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52136.795903                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 52074.823944                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52048.144258                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52048.144258                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52042.353392                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52076.841108                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 52063.670960                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52042.353392                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52076.841108                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 52063.670960                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -386,17 +388,17 @@ system.cpu.l2cache.demand_mshr_misses::total         6832
 system.cpu.l2cache.overall_mshr_misses::cpu.inst         2609                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data         4223                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total         6832                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    104360000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    104365000                       # number of ReadReq MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     54680000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total    159040000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    114240000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    114240000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    104360000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    168920000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    273280000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    104360000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    168920000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    273280000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total    159045000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    114243000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    114243000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    104365000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    168923000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    273288000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    104365000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    168923000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    273288000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.167211                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.851183                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.231042                       # mshr miss rate for ReadReq accesses
@@ -408,92 +410,100 @@ system.cpu.l2cache.demand_mshr_miss_rate::total     0.340222
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.167211                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.943055                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.340222                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40001.916443                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total        40000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total        40000                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total        40000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total        40000                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40001.257545                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40001.050420                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40001.050420                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40001.916443                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000.710395                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40001.170960                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40001.916443                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.710395                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40001.170960                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.dcache.tags.replacements              1332                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          3078.412981                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           176641599                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse          3078.445016                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           168359617                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs              4478                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs          39446.538410                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs          37597.056052                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  3078.412981                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.751566                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.751566                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data  3078.445016                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.751573                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.751573                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         3146                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           11                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1           19                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2           11                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           20                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           10                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::3          677                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::4         2428                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024     0.768066                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         353296632                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        353296632                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     94570004                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        94570004                       # number of ReadReq hits
+system.cpu.dcache.tags.tag_accesses         336732670                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        336732670                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     86233963                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        86233963                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data     82049805                       # number of WriteReq hits
 system.cpu.dcache.WriteReq_hits::total       82049805                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data        54059                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total         54059                       # number of SoftPFReq hits
 system.cpu.dcache.LoadLockedReq_hits::cpu.data        10895                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total        10895                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data        10895                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total        10895                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     176619809                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        176619809                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    176619809                       # number of overall hits
-system.cpu.dcache.overall_hits::total       176619809                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data         1606                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total          1606                       # number of ReadReq misses
+system.cpu.dcache.demand_hits::cpu.data     168283768                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        168283768                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    168337827                       # number of overall hits
+system.cpu.dcache.overall_hits::total       168337827                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data         1604                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total          1604                       # number of ReadReq misses
 system.cpu.dcache.WriteReq_misses::cpu.data         2872                       # number of WriteReq misses
 system.cpu.dcache.WriteReq_misses::total         2872                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data         4478                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total           4478                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data         4478                       # number of overall misses
-system.cpu.dcache.overall_misses::total          4478                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data     78292000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     78292000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data    157288000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total    157288000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data    235580000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total    235580000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data    235580000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total    235580000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     94571610                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     94571610                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_misses::cpu.data            3                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total            3                       # number of SoftPFReq misses
+system.cpu.dcache.demand_misses::cpu.data         4476                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total           4476                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data         4479                       # number of overall misses
+system.cpu.dcache.overall_misses::total          4479                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data     78354000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     78354000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data    157425500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total    157425500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data    235779500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total    235779500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data    235779500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total    235779500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     86235567                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     86235567                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     82052677                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     82052677                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data        54062                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total        54062                       # number of SoftPFReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::cpu.data        10895                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::total        10895                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data        10895                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total        10895                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    176624287                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    176624287                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    176624287                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    176624287                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000017                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.000017                       # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data    168288244                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    168288244                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    168342306                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    168342306                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000019                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.000019                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000035                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_miss_rate::total     0.000035                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.000025                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.000025                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.000025                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.000025                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48749.688667                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 48749.688667                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54766.016713                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 54766.016713                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 52608.307280                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 52608.307280                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 52608.307280                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 52608.307280                       # average overall miss latency
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.000055                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.000055                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.000027                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.000027                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.000027                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.000027                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48849.127182                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 48849.127182                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54813.892758                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 54813.892758                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 52676.385165                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 52676.385165                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 52641.102925                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 52641.102925                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -504,40 +514,54 @@ system.cpu.dcache.fast_writes                       0                       # nu
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks          998                       # number of writebacks
 system.cpu.dcache.writebacks::total               998                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data         1606                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total         1606                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data            1                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total            1                       # number of ReadReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data            1                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total            1                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data            1                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total            1                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data         1603                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total         1603                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data         2872                       # number of WriteReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::total         2872                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data         4478                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total         4478                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data            3                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total            3                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data         4475                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total         4475                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data         4478                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total         4478                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     75080000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total     75080000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    151544000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total    151544000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data    226624000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total    226624000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data    226624000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total    226624000                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000017                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000017                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     75108000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     75108000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    151681500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total    151681500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data       159000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total       159000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data    226789500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total    226789500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data    226948500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total    226948500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000019                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000019                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000035                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000035                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000025                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.000025                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000025                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.000025                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46749.688667                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46749.688667                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52766.016713                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52766.016713                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50608.307280                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 50608.307280                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50608.307280                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 50608.307280                       # average overall mshr miss latency
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.000055                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.000055                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000027                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.000027                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000027                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.000027                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46854.647536                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46854.647536                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52813.892758                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52813.892758                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data        53000                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total        53000                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50679.217877                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 50679.217877                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50680.772666                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 50680.772666                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.throughput                 2565553                       # Throughput (bytes/s)
+system.cpu.toL2Bus.throughput                 2608205                       # Throughput (bytes/s)
 system.cpu.toL2Bus.trans_dist::ReadReq          17209                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadResp         17209                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::Writeback          998                       # Transaction distribution
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt
index ef1860117..cf6f894cc 100644
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt
@@ -1,65 +1,65 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  1.190861                       # Number of seconds simulated
-sim_ticks                                1190860634000                       # Number of ticks simulated
-final_tick                               1190860634000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.555548                       # Number of seconds simulated
+sim_ticks                                555548307000                       # Number of ticks simulated
+final_tick                               555548307000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 304682                       # Simulator instruction rate (inst/s)
-host_op_rate                                   304682                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              180566626                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 250024                       # Number of bytes of host memory used
-host_seconds                                  6595.13                       # Real time elapsed on the host
-sim_insts                                  2009421070                       # Number of instructions simulated
-sim_ops                                    2009421070                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 201077                       # Simulator instruction rate (inst/s)
+host_op_rate                                   201077                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              120272803                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 246132                       # Number of bytes of host memory used
+host_seconds                                  4619.07                       # Real time elapsed on the host
+sim_insts                                   928789150                       # Number of instructions simulated
+sim_ops                                     928789150                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst          30476096                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             30476096                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       186816                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          186816                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      4282112                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           4282112                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst             476189                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                476189                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           66908                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total                66908                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst             25591656                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                25591656                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          156875                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             156875                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           3595813                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                3595813                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           3595813                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst            25591656                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               29187469                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        476189                       # Number of read requests accepted
-system.physmem.writeReqs                        66908                       # Number of write requests accepted
-system.physmem.readBursts                      476189                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                      66908                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 30458432                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     17664                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   4280448                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  30476096                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                4282112                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      276                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytes_read::cpu.inst          18657152                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             18657152                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       186688                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          186688                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      4267712                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           4267712                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst             291518                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                291518                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           66683                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                66683                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst             33583312                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                33583312                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          336043                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             336043                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           7681982                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                7681982                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           7681982                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst            33583312                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               41265294                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        291518                       # Number of read requests accepted
+system.physmem.writeReqs                        66683                       # Number of write requests accepted
+system.physmem.readBursts                      291518                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                      66683                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 18639168                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     17984                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   4266304                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  18657152                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                4267712                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      281                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               29463                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               29817                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               29839                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               29779                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               29691                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               29776                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               29845                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               29824                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               29755                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               29877                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              29842                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              29915                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              29785                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              29577                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              29501                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              29627                       # Per bank write bursts
+system.physmem.perBankRdBursts::0               17934                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               18286                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               18304                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               18252                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               18169                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               18242                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               18316                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               18295                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               18226                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               18227                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              18210                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              18385                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              18260                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              18048                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              17980                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              18103                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                4125                       # Per bank write bursts
 system.physmem.perBankWrBursts::1                4164                       # Per bank write bursts
 system.physmem.perBankWrBursts::2                4223                       # Per bank write bursts
@@ -69,8 +69,8 @@ system.physmem.perBankWrBursts::5                4099                       # Pe
 system.physmem.perBankWrBursts::6                4262                       # Per bank write bursts
 system.physmem.perBankWrBursts::7                4226                       # Per bank write bursts
 system.physmem.perBankWrBursts::8                4233                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                4334                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               4222                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                4185                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               4150                       # Per bank write bursts
 system.physmem.perBankWrBursts::11               4241                       # Per bank write bursts
 system.physmem.perBankWrBursts::12               4098                       # Per bank write bursts
 system.physmem.perBankWrBursts::13               4100                       # Per bank write bursts
@@ -78,23 +78,23 @@ system.physmem.perBankWrBursts::14               4096                       # Pe
 system.physmem.perBankWrBursts::15               4157                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    1190860558500                       # Total gap between requests
+system.physmem.totGap                    555548231500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  476189                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  291518                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                  66908                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    475413                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       474                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                  66683                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    290743                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       468                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::2                        26                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
@@ -140,24 +140,24 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                      994                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                      994                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     4057                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     4057                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     4057                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     4057                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     4057                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     4057                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     4057                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     4057                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     4057                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     4056                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     4056                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     4056                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     4056                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     4056                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     4056                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     4056                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                      970                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                      970                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     4046                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     4046                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     4046                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     4046                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     4046                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     4045                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     4045                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     4045                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     4045                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     4045                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     4048                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     4045                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     4045                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     4045                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     4045                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     4045                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
@@ -189,110 +189,111 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       196024                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      177.216831                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     127.562877                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     207.494740                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          75216     38.37%     38.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        90843     46.34%     84.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        17447      8.90%     93.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511          798      0.41%     94.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639          682      0.35%     94.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767          656      0.33%     94.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1172      0.60%     95.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1008      0.51%     95.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         8202      4.18%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         196024                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          4056                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean       115.321252                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::gmean       36.815163                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev     1129.679023                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047           4037     99.53%     99.53% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::12288-14335            7      0.17%     99.70% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::14336-16383            9      0.22%     99.93% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::16384-18431            2      0.05%     99.98% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples       104858                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      218.415915                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     140.780585                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     268.040689                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          39691     37.85%     37.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        43831     41.80%     79.65% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         8352      7.97%     87.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         1265      1.21%     88.82% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639          732      0.70%     89.52% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767          905      0.86%     90.39% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1060      1.01%     91.40% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          884      0.84%     92.24% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         8138      7.76%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         104858                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          4045                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        70.322621                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::gmean       36.136998                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      770.555291                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047           4038     99.83%     99.83% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::10240-12287            1      0.02%     99.85% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::12288-14335            1      0.02%     99.88% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::14336-16383            4      0.10%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::32768-34815            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            4056                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          4056                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        16.489645                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.468091                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        0.860070                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16               3063     75.52%     75.52% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18                993     24.48%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            4056                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     4642842500                       # Total ticks spent queuing
-system.physmem.totMemAccLat               13566211250                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   2379565000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        9755.65                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            4045                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          4045                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.479852                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.458537                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        0.855483                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               3076     76.04%     76.04% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18                966     23.88%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19                  3      0.07%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            4045                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     2434432250                       # Total ticks spent queuing
+system.physmem.totMemAccLat                7895126000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   1456185000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        8358.94                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  28505.65                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          25.58                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           3.59                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       25.59                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        3.60                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  27108.94                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          33.55                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           7.68                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       33.58                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        7.68                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           0.23                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       0.20                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
+system.physmem.busUtil                           0.32                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       0.26                       # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite                      0.06                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        24.34                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     296141                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     50629                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   62.23                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  75.67                       # Row buffer hit rate for writes
-system.physmem.avgGap                      2192721.67                       # Average gap between requests
-system.physmem.pageHitRate                      63.88                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE     589509971750                       # Time in different power states
-system.physmem.memoryStateTime::REF       39765440000                       # Time in different power states
+system.physmem.avgWrQLen                        24.31                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     202612                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     50417                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   69.57                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  75.61                       # Row buffer hit rate for writes
+system.physmem.avgGap                      1550939.92                       # Average gap between requests
+system.physmem.pageHitRate                      70.69                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE     275426566250                       # Time in different power states
+system.physmem.memoryStateTime::REF       18550740000                       # Time in different power states
 system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT      561585082000                       # Time in different power states
+system.physmem.memoryStateTime::ACT      261564123750                       # Time in different power states
 system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.membus.throughput                     29187469                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq              409320                       # Transaction distribution
-system.membus.trans_dist::ReadResp             409320                       # Transaction distribution
-system.membus.trans_dist::Writeback             66908                       # Transaction distribution
-system.membus.trans_dist::ReadExReq             66869                       # Transaction distribution
-system.membus.trans_dist::ReadExResp            66869                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1019286                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1019286                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     34758208                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total            34758208                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus               34758208                       # Total data (bytes)
+system.membus.throughput                     41265294                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq              224874                       # Transaction distribution
+system.membus.trans_dist::ReadResp             224874                       # Transaction distribution
+system.membus.trans_dist::Writeback             66683                       # Transaction distribution
+system.membus.trans_dist::ReadExReq             66644                       # Transaction distribution
+system.membus.trans_dist::ReadExResp            66644                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       649719                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 649719                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     22924864                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total            22924864                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus               22924864                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy          1283694000                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               0.1                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         4536921750                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              0.4                       # Layer utilization (%)
+system.membus.reqLayer0.occupancy           954576500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               0.2                       # Layer utilization (%)
+system.membus.respLayer1.occupancy         2724054750                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization              0.5                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.branchPred.lookups               271010035                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         174815111                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect          26224729                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups            223743631                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits               179636452                       # Number of BTB hits
+system.cpu.branchPred.lookups               125108663                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          80505378                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect          12157226                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups            103330872                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                82874855                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             80.286733                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                40316732                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect              27614                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             80.203383                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                18690214                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect               9442                       # Number of incorrect RAS predictions.
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                    511123125                       # DTB read hits
-system.cpu.dtb.read_misses                     428196                       # DTB read misses
+system.cpu.dtb.read_hits                    237537573                       # DTB read hits
+system.cpu.dtb.read_misses                     198412                       # DTB read misses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                511551321                       # DTB read accesses
-system.cpu.dtb.write_hits                   210802220                       # DTB write hits
-system.cpu.dtb.write_misses                     15121                       # DTB write misses
+system.cpu.dtb.read_accesses                237735985                       # DTB read accesses
+system.cpu.dtb.write_hits                    98305055                       # DTB write hits
+system.cpu.dtb.write_misses                      7206                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses               210817341                       # DTB write accesses
-system.cpu.dtb.data_hits                    721925345                       # DTB hits
-system.cpu.dtb.data_misses                     443317                       # DTB misses
+system.cpu.dtb.write_accesses                98312261                       # DTB write accesses
+system.cpu.dtb.data_hits                    335842628                       # DTB hits
+system.cpu.dtb.data_misses                     205618                       # DTB misses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                722368662                       # DTB accesses
-system.cpu.itb.fetch_hits                   682230205                       # ITB hits
+system.cpu.dtb.data_accesses                336048246                       # DTB accesses
+system.cpu.itb.fetch_hits                   315070348                       # ITB hits
 system.cpu.itb.fetch_misses                       120                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses               682230325                       # ITB accesses
+system.cpu.itb.fetch_accesses               315070468                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -305,71 +306,72 @@ system.cpu.itb.data_hits                            0                       # DT
 system.cpu.itb.data_misses                          0                       # DTB misses
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
-system.cpu.workload.num_syscalls                   39                       # Number of system calls
-system.cpu.numCycles                       2381721268                       # number of cpu cycles simulated
+system.cpu.workload.num_syscalls                   37                       # Number of system calls
+system.cpu.numCycles                       1111096614                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                  2009421070                       # Number of instructions committed
-system.cpu.committedOps                    2009421070                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                      51480727                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.committedInsts                   928789150                       # Number of instructions committed
+system.cpu.committedOps                     928789150                       # Number of ops (including micro ops) committed
+system.cpu.discardedOps                      23870770                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                               1.185277                       # CPI: cycles per instruction
-system.cpu.ipc                               0.843684                       # IPC: instructions per cycle
-system.cpu.tickCycles                      2275163827                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                       106557441                       # Total number of cycles that the object has spent stopped
-system.cpu.icache.tags.replacements             20821                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1689.662119                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           682207641                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs             22563                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          30235.679697                       # Average number of references to valid blocks.
+system.cpu.cpi                               1.196285                       # CPI: cycles per instruction
+system.cpu.ipc                               0.835921                       # IPC: instructions per cycle
+system.cpu.tickCycles                      1052548202                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                        58548412                       # Total number of cycles that the object has spent stopped
+system.cpu.icache.tags.replacements             10608                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1686.445112                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           315057997                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs             12350                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          25510.768988                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1689.662119                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.825030                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.825030                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst  1686.445112                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.823460                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.823460                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         1742                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           63                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1          103                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::2            2                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4         1574                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1572                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.850586                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses        1364482973                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses       1364482973                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    682207641                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       682207641                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     682207641                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        682207641                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    682207641                       # number of overall hits
-system.cpu.icache.overall_hits::total       682207641                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst        22564                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total         22564                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst        22564                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total          22564                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst        22564                       # number of overall misses
-system.cpu.icache.overall_misses::total         22564                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    467220750                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    467220750                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    467220750                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    467220750                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    467220750                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    467220750                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    682230205                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    682230205                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    682230205                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    682230205                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    682230205                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    682230205                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000033                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000033                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000033                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000033                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000033                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000033                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20706.468268                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 20706.468268                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 20706.468268                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 20706.468268                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 20706.468268                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 20706.468268                       # average overall miss latency
+system.cpu.icache.tags.tag_accesses         630153046                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        630153046                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    315057997                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       315057997                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     315057997                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        315057997                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    315057997                       # number of overall hits
+system.cpu.icache.overall_hits::total       315057997                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst        12351                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total         12351                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst        12351                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total          12351                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst        12351                       # number of overall misses
+system.cpu.icache.overall_misses::total         12351                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    334622500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    334622500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    334622500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    334622500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    334622500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    334622500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    315070348                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    315070348                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    315070348                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    315070348                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    315070348                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    315070348                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000039                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000039                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000039                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000039                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000039                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000039                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27092.745527                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 27092.745527                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 27092.745527                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 27092.745527                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 27092.745527                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 27092.745527                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -378,123 +380,123 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst        22564                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total        22564                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst        22564                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total        22564                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst        22564                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total        22564                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    420842250                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    420842250                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    420842250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    420842250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    420842250                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    420842250                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000033                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000033                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000033                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.000033                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000033                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.000033                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18651.048130                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18651.048130                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18651.048130                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 18651.048130                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18651.048130                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 18651.048130                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst        12351                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total        12351                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst        12351                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total        12351                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst        12351                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total        12351                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    308669500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    308669500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    308669500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    308669500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    308669500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    308669500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000039                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000039                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000039                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.000039                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000039                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.000039                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24991.458182                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24991.458182                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24991.458182                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 24991.458182                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24991.458182                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 24991.458182                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.throughput                88620923                       # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq        1481078                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       1481077                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback        95962                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq        71948                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp        71948                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        45127                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      3156886                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           3202013                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1444032                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    104091136                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total      105535168                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus         105535168                       # Total data (bytes)
+system.cpu.toL2Bus.throughput               101892158                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq         723971                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp        723970                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback        91489                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq        69010                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp        69010                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        24701                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      1652749                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           1677450                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       790400                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     55815616                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total       56606016                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus          56606016                       # Total data (bytes)
 system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy      920456000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.occupancy      533724000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy      34470750                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy      19151500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    2371437000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    1222065750                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.2                       # Layer utilization (%)
-system.cpu.l2cache.tags.replacements           443410                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        32681.250734                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            1100744                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           476144                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             2.311788                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements           258739                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        32601.591220                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs             523854                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           291475                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             1.797252                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks  1349.100172                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 31332.150562                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.041171                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.956181                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.997353                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        32734                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          122                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          209                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          274                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         2678                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        29451                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.998962                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         13739996                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        13739996                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst      1071757                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        1071757                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks        95962                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total        95962                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.inst         5079                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total         5079                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst      1076836                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         1076836                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst      1076836                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        1076836                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst       409321                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total       409321                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.inst        66869                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total        66869                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst       476190                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        476190                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst       476190                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       476190                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst  29485195750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total  29485195750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst   4407101000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   4407101000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst  33892296750                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  33892296750                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst  33892296750                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  33892296750                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst      1481078                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total      1481078                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks        95962                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total        95962                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.inst        71948                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total        71948                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst      1553026                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      1553026                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst      1553026                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      1553026                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.276367                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.276367                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst     0.929407                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.929407                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.306621                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.306621                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.306621                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.306621                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72034.407592                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 72034.407592                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 65906.488806                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65906.488806                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71173.894349                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 71173.894349                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71173.894349                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 71173.894349                       # average overall miss latency
+system.cpu.l2cache.tags.occ_blocks::writebacks  2866.071604                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 29735.519616                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.087466                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.907456                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.994922                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        32736                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          123                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          208                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          275                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         2681                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        29449                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.999023                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses          7436245                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses         7436245                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.inst       499096                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total         499096                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks        91489                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total        91489                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.inst         2366                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total         2366                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst       501462                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total          501462                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst       501462                       # number of overall hits
+system.cpu.l2cache.overall_hits::total         501462                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst       224875                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total       224875                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.inst        66644                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total        66644                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst       291519                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        291519                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst       291519                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       291519                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst  15957253750                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total  15957253750                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst   4332290500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   4332290500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst  20289544250                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  20289544250                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst  20289544250                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  20289544250                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst       723971                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total       723971                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks        91489                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total        91489                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.inst        69010                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total        69010                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst       792981                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total       792981                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst       792981                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total       792981                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.310613                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.310613                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst     0.965715                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.965715                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.367624                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.367624                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.367624                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.367624                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70960.550306                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 70960.550306                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 65006.459696                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65006.459696                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69599.388891                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 69599.388891                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69599.388891                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 69599.388891                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -503,107 +505,107 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        66908                       # number of writebacks
-system.cpu.l2cache.writebacks::total            66908                       # number of writebacks
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-system.cpu.l2cache.ReadReq_mshr_miss_latency::total  24307408750                       # number of ReadReq MSHR miss cycles
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-system.cpu.l2cache.demand_mshr_miss_latency::total  27850437750                       # number of demand (read+write) MSHR miss cycles
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-system.cpu.l2cache.overall_mshr_miss_latency::total  27850437750                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.276367                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.276367                       # mshr miss rate for ReadReq accesses
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-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.929407                       # mshr miss rate for ReadExReq accesses
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-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59384.709678                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59384.709678                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 52984.626658                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52984.626658                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58485.977761                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58485.977761                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58485.977761                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58485.977761                       # average overall mshr miss latency
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+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58434.217899                       # average ReadReq mshr miss latency
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+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57077.542973                       # average overall mshr miss latency
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+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57077.542973                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57077.542973                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements           1526366                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4094.558807                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           694159033                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           1530462                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            453.561757                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         828677250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.inst  4094.558807                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.inst     0.999648                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999648                       # Average percentage of cache occupancy
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+system.cpu.dcache.tags.total_refs           322859768                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            780630                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs            413.588727                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle         839965250                       # Cycle when the warmup percentage was hit.
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+system.cpu.dcache.tags.occ_percent::cpu.inst     0.999238                       # Average percentage of cache occupancy
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 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           60                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          211                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2          948                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3         1262                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::4         1615                       # Occupied blocks per task id
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 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses        1393051346                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses       1393051346                       # Number of data accesses
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-system.cpu.dcache.ReadReq_miss_latency::cpu.inst  44310462500                       # number of ReadReq miss cycles
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-system.cpu.dcache.overall_accesses::total    695760442                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.inst     0.003009                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.003009                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.inst     0.000675                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.000675                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.inst     0.002302                       # miss rate for demand accesses
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-system.cpu.dcache.overall_miss_rate::cpu.inst     0.002302                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.002302                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 30367.623626                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 30367.623626                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 64625.045686                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 64625.045686                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.inst 33411.156207                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 33411.156207                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.inst 33411.156207                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 33411.156207                       # average overall miss latency
+system.cpu.dcache.tags.tag_accesses         648198338                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        648198338                       # Number of data accesses
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+system.cpu.dcache.demand_miss_rate::total     0.002623                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.inst     0.002623                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.002623                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 32116.158051                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 32116.158051                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 65528.606738                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 65528.606738                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.inst 37513.276335                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 37513.276335                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.inst 37513.276335                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 37513.276335                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -612,48 +614,48 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks        95962                       # number of writebacks
-system.cpu.dcache.writebacks::total             95962                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.inst          621                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total          621                       # number of ReadReq MSHR hits
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-system.cpu.dcache.demand_mshr_hits::cpu.inst        70947                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total        70947                       # number of demand (read+write) MSHR hits
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-system.cpu.dcache.overall_mshr_hits::total        70947                       # number of overall MSHR hits
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-system.cpu.dcache.ReadReq_mshr_misses::total      1458514                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.inst        71948                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total        71948                       # number of WriteReq MSHR misses
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-system.cpu.dcache.overall_mshr_misses::total      1530462                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst  41263033500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  41263033500                       # number of ReadReq MSHR miss cycles
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-system.cpu.dcache.WriteReq_mshr_miss_latency::total   4529893000                       # number of WriteReq MSHR miss cycles
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-system.cpu.dcache.overall_mshr_miss_latency::total  45792926500                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst     0.003007                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.003007                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst     0.000341                       # mshr miss rate for WriteReq accesses
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-system.cpu.dcache.demand_mshr_miss_rate::cpu.inst     0.002200                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.002200                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.inst     0.002200                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.002200                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 28291.146674                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 28291.146674                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 62960.652138                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62960.652138                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 29920.982357                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 29920.982357                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 29920.982357                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 29920.982357                       # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks        91489                       # number of writebacks
+system.cpu.dcache.writebacks::total             91489                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.inst          313                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total          313                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.inst        68143                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total        68143                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.inst        68456                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total        68456                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.inst        68456                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total        68456                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.inst       711620                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       711620                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.inst        69010                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total        69010                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.inst       780630                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       780630                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.inst       780630                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       780630                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst  21363533750                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  21363533750                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst   4424989000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   4424989000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.inst  25788522750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  25788522750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.inst  25788522750                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  25788522750                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst     0.003157                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.003157                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst     0.000702                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000702                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.inst     0.002412                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.002412                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.inst     0.002412                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.002412                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 30020.985568                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30020.985568                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 64120.982466                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64120.982466                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 33035.526114                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 33035.526114                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 33035.526114                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 33035.526114                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
index c36f62fc3..9bdd841ee 100644
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,69 +1,69 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.635929                       # Number of seconds simulated
-sim_ticks                                635929494500                       # Number of ticks simulated
-final_tick                               635929494500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.278171                       # Number of seconds simulated
+sim_ticks                                278170874500                       # Number of ticks simulated
+final_tick                               278170874500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 181383                       # Simulator instruction rate (inst/s)
-host_op_rate                                   181383                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               63271586                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 229300                       # Number of bytes of host memory used
-host_seconds                                 10050.79                       # Real time elapsed on the host
-sim_insts                                  1823043370                       # Number of instructions simulated
-sim_ops                                    1823043370                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 125961                       # Simulator instruction rate (inst/s)
+host_op_rate                                   125961                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               41594749                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 247184                       # Number of bytes of host memory used
+host_seconds                                  6687.64                       # Real time elapsed on the host
+sim_insts                                   842382029                       # Number of instructions simulated
+sim_ops                                     842382029                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            176704                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          30295616                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             30472320                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       176704                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          176704                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      4282112                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           4282112                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               2761                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             473369                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                476130                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           66908                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total                66908                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               277867                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             47639898                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                47917765                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          277867                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             277867                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           6733627                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                6733627                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           6733627                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              277867                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            47639898                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               54651392                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        476130                       # Number of read requests accepted
-system.physmem.writeReqs                        66908                       # Number of write requests accepted
-system.physmem.readBursts                      476130                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                      66908                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 30454144                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     18176                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   4280960                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  30472320                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                4282112                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      284                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytes_read::cpu.inst            176000                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          18476352                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             18652352                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       176000                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          176000                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      4267712                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           4267712                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               2750                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             288693                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                291443                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           66683                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                66683                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst               632705                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             66420872                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                67053576                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          632705                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             632705                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          15342052                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               15342052                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          15342052                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              632705                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            66420872                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               82395628                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        291443                       # Number of read requests accepted
+system.physmem.writeReqs                        66683                       # Number of write requests accepted
+system.physmem.readBursts                      291443                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                      66683                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 18634688                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     17664                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   4265728                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  18652352                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                4267712                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      276                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               29443                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               29787                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               29841                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               29778                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               29678                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               29749                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               29855                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               29842                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               29764                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               29879                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              29841                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              29912                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              29773                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              29578                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              29495                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              29631                       # Per bank write bursts
+system.physmem.perBankRdBursts::0               17914                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               18261                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               18310                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               18245                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               18158                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               18234                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               18318                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               18307                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               18230                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               18222                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              18215                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              18386                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              18247                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              18053                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              17967                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              18100                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                4125                       # Per bank write bursts
 system.physmem.perBankWrBursts::1                4164                       # Per bank write bursts
 system.physmem.perBankWrBursts::2                4223                       # Per bank write bursts
@@ -73,8 +73,8 @@ system.physmem.perBankWrBursts::5                4099                       # Pe
 system.physmem.perBankWrBursts::6                4262                       # Per bank write bursts
 system.physmem.perBankWrBursts::7                4226                       # Per bank write bursts
 system.physmem.perBankWrBursts::8                4233                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                4334                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               4230                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                4179                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               4147                       # Per bank write bursts
 system.physmem.perBankWrBursts::11               4241                       # Per bank write bursts
 system.physmem.perBankWrBursts::12               4098                       # Per bank write bursts
 system.physmem.perBankWrBursts::13               4100                       # Per bank write bursts
@@ -82,27 +82,27 @@ system.physmem.perBankWrBursts::14               4096                       # Pe
 system.physmem.perBankWrBursts::15               4157                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    635929412000                       # Total gap between requests
+system.physmem.totGap                    278170791500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  476130                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  291443                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                  66908                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    408324                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     66857                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       507                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                       139                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                        17                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                         2                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                  66683                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    214189                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     46674                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     30117                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                       160                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                        24                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                         3                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
@@ -144,25 +144,25 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                      991                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     1175                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     2734                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     4071                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     4133                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     4105                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     5069                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     4046                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     4084                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     4071                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     4061                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     4059                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     4053                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     4051                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     4045                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     4045                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     4054                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     4045                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                      970                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                      972                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     2092                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     4176                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     4047                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     4046                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     4384                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     4068                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     4053                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     4075                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     4069                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     4380                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     4593                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     4103                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     4061                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     4256                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     4275                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     4044                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                        4                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
@@ -193,112 +193,111 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       185909                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      186.826200                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     134.409449                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     215.527814                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          65070     35.00%     35.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        87777     47.22%     82.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        21119     11.36%     93.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511          448      0.24%     93.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639          430      0.23%     94.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767          462      0.25%     94.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895          533      0.29%     94.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          575      0.31%     94.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         9495      5.11%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         185909                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::samples       100147                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      228.644373                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     146.919705                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     277.922323                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          35701     35.65%     35.65% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        41944     41.88%     77.53% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        10332     10.32%     87.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511          643      0.64%     88.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639          550      0.55%     89.04% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767          478      0.48%     89.52% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          606      0.61%     90.12% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1154      1.15%     91.27% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         8739      8.73%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         100147                       # Bytes accessed per row activation
 system.physmem.rdPerTurnAround::samples          4044                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean       117.004698                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::gmean       36.982691                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev     1132.774880                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047           4024     99.51%     99.51% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::4096-6143            1      0.02%     99.53% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::12288-14335            3      0.07%     99.60% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::14336-16383           15      0.37%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        68.435955                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::gmean       36.134261                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      746.811219                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047           4037     99.83%     99.83% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::4096-6143            1      0.02%     99.85% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::12288-14335            2      0.05%     99.90% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::14336-16383            3      0.07%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::32768-34815            1      0.02%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::total            4044                       # Reads before turning the bus around for writes
 system.physmem.wrPerTurnAround::samples          4044                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        16.540554                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.517518                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        0.888872                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16               2948     72.90%     72.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17                 11      0.27%     73.17% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18               1080     26.71%     99.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19                  5      0.12%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.481701                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.460271                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        0.857904                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               3073     75.99%     75.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18                965     23.86%     99.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19                  6      0.15%    100.00% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::total            4044                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     4824243250                       # Total ticks spent queuing
-system.physmem.totMemAccLat               13746355750                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   2379230000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       10138.24                       # Average queueing delay per DRAM burst
+system.physmem.totQLat                     3337058000                       # Total ticks spent queuing
+system.physmem.totMemAccLat                8796439250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   1455835000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       11460.98                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  28888.24                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          47.89                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           6.73                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       47.92                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        6.73                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  30210.98                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          66.99                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                          15.33                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       67.05                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                       15.34                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           0.43                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       0.37                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.05                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.01                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        24.41                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     306274                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     50544                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   64.36                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  75.54                       # Row buffer hit rate for writes
-system.physmem.avgGap                      1171058.77                       # Average gap between requests
-system.physmem.pageHitRate                      65.74                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE     176454220250                       # Time in different power states
-system.physmem.memoryStateTime::REF       21234980000                       # Time in different power states
+system.physmem.busUtil                           0.64                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       0.52                       # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite                      0.12                       # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen                         1.02                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        24.50                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     207319                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     50340                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   71.20                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  75.49                       # Row buffer hit rate for writes
+system.physmem.avgGap                       776740.01                       # Average gap between requests
+system.physmem.pageHitRate                      72.00                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE      73797472500                       # Time in different power states
+system.physmem.memoryStateTime::REF        9288500000                       # Time in different power states
 system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT      438237480500                       # Time in different power states
+system.physmem.memoryStateTime::ACT      195078106500                       # Time in different power states
 system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.membus.throughput                     54651392                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq              409276                       # Transaction distribution
-system.membus.trans_dist::ReadResp             409276                       # Transaction distribution
-system.membus.trans_dist::Writeback             66908                       # Transaction distribution
-system.membus.trans_dist::ReadExReq             66854                       # Transaction distribution
-system.membus.trans_dist::ReadExResp            66854                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1019168                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1019168                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     34754432                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total            34754432                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus               34754432                       # Total data (bytes)
+system.membus.throughput                     82395628                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq              224814                       # Transaction distribution
+system.membus.trans_dist::ReadResp             224814                       # Transaction distribution
+system.membus.trans_dist::Writeback             66683                       # Transaction distribution
+system.membus.trans_dist::ReadExReq             66629                       # Transaction distribution
+system.membus.trans_dist::ReadExResp            66629                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       649569                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 649569                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     22920064                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total            22920064                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus               22920064                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy          1134499000                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               0.2                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         4452935500                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              0.7                       # Layer utilization (%)
+system.membus.reqLayer0.occupancy           964230000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               0.3                       # Layer utilization (%)
+system.membus.respLayer1.occupancy         2710224500                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization              1.0                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.branchPred.lookups               402497188                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         262794086                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect          25809520                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups            329924346                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits               269779526                       # Number of BTB hits
+system.cpu.branchPred.lookups               192451615                       # Number of BP lookups
+system.cpu.branchPred.condPredicted         125635967                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect          11884604                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups            155866017                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits               126935891                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             81.770118                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                58338435                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect               6772                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             81.439106                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                28844958                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect                146                       # Number of incorrect RAS predictions.
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                    522325129                       # DTB read hits
-system.cpu.dtb.read_misses                     599769                       # DTB read misses
+system.cpu.dtb.read_hits                    244501349                       # DTB read hits
+system.cpu.dtb.read_misses                     309633                       # DTB read misses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                522924898                       # DTB read accesses
-system.cpu.dtb.write_hits                   290323928                       # DTB write hits
-system.cpu.dtb.write_misses                     50170                       # DTB write misses
+system.cpu.dtb.read_accesses                244810982                       # DTB read accesses
+system.cpu.dtb.write_hits                   135678395                       # DTB write hits
+system.cpu.dtb.write_misses                     31433                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses               290374098                       # DTB write accesses
-system.cpu.dtb.data_hits                    812649057                       # DTB hits
-system.cpu.dtb.data_misses                     649939                       # DTB misses
+system.cpu.dtb.write_accesses               135709828                       # DTB write accesses
+system.cpu.dtb.data_hits                    380179744                       # DTB hits
+system.cpu.dtb.data_misses                     341066                       # DTB misses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                813298996                       # DTB accesses
-system.cpu.itb.fetch_hits                   408884134                       # ITB hits
-system.cpu.itb.fetch_misses                       679                       # ITB misses
+system.cpu.dtb.data_accesses                380520810                       # DTB accesses
+system.cpu.itb.fetch_hits                   196843274                       # ITB hits
+system.cpu.itb.fetch_misses                       340                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses               408884813                       # ITB accesses
+system.cpu.itb.fetch_accesses               196843614                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -311,507 +310,508 @@ system.cpu.itb.data_hits                            0                       # DT
 system.cpu.itb.data_misses                          0                       # DTB misses
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
-system.cpu.workload.num_syscalls                   39                       # Number of system calls
-system.cpu.numCycles                       1271858990                       # number of cpu cycles simulated
+system.cpu.workload.num_syscalls                   37                       # Number of system calls
+system.cpu.numCycles                        556341750                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles          427176335                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                     3374139678                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                   402497188                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches          328117961                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     650903682                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles               174116050                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles               24391105                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                  137                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles          7638                       # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles           40                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                 408884134                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes               8158289                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples         1250296288                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.698672                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.147490                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles          202596472                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                     1648022555                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   192451615                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches          155780849                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     341400338                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                24237220                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles                         65                       # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles                  140                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles          6944                       # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles           24                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                 196843274                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               6474022                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          556122593                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.963416                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.176362                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                599392606     47.94%     47.94% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 59914511      4.79%     52.73% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 43339464      3.47%     56.20% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 76172685      6.09%     62.29% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                135820925     10.86%     73.15% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                 46245373      3.70%     76.85% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                 41570756      3.32%     80.18% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  7626661      0.61%     80.79% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                240213307     19.21%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                237070993     42.63%     42.63% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 30141188      5.42%     48.05% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 22117288      3.98%     52.03% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 36437929      6.55%     58.58% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                 67906358     12.21%     70.79% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                 21586506      3.88%     74.67% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                 19299171      3.47%     78.14% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  3525264      0.63%     78.77% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                118037896     21.23%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total           1250296288                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.316464                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        2.652920                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                437590524                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              25041136                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 638845250                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               1014076                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles              147805302                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved             33122555                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                 12366                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts             3318032791                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                 46593                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles              147805302                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                458553010                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                 7909851                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles          27396                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 618894367                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              17106362                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts             3208538957                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                  6484                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                  32278                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents               17594215                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                 887362                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands          2130246681                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            3706452753                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       3620701555                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups          85751197                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps            1384969070                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                745277611                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts               4240                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts            107                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  12056800                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            776684532                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores           361655801                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads          80427234                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores         13113632                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                 2720222433                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                  90                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                2182396478                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued          17917271                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined       897142134                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined    813907304                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved             51                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples    1250296288                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.745503                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.834496                       # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total            556122593                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.345923                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        2.962249                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                168349447                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              89068138                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 273848076                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              12745104                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles               12111828                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved             15365676                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                  7037                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts             1585434415                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                 25396                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles               12111828                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                176490492                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                62059786                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles          14189                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 278431125                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              27015173                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts             1538086365                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                  7791                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                2366498                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents               17905765                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents                6836076                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands          1026692475                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            1767991158                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       1728209753                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups          39781404                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps             638967158                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                387725317                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts               1423                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts            146                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                   9582425                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            372570647                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           175396988                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          40822996                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         11172222                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                 1305164678                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                 123                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                1015585029                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued           8790961                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       462756562                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined    428157425                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved             86                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     556122593                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.826189                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.898849                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           456063276     36.48%     36.48% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1           196937863     15.75%     52.23% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2           246215948     19.69%     71.92% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3           118632312      9.49%     81.41% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            96039549      7.68%     89.09% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5            85322198      6.82%     95.91% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6            31637786      2.53%     98.44% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7            19044967      1.52%     99.97% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              402389      0.03%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           196378723     35.31%     35.31% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            93218493     16.76%     52.07% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            92101634     16.56%     68.64% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            60001110     10.79%     79.42% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            56881652     10.23%     89.65% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            29459866      5.30%     94.95% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6            17057995      3.07%     98.02% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             7198930      1.29%     99.31% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8             3824190      0.69%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total      1250296288                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       556122593                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                 1147020      2.84%      2.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%      2.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      2.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      2.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      2.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      2.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      2.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      2.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      2.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      2.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      2.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      2.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      2.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      2.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      2.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      2.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      2.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      2.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      2.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      2.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      2.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      2.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      2.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      2.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      2.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      2.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      2.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      2.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      2.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead               25333961     62.75%     65.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite              13891524     34.41%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                 2464498     10.47%     10.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%     10.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     10.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     10.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     10.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     10.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     10.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     10.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     10.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     10.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     10.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     10.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     10.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     10.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     10.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     10.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     10.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     10.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     10.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     10.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     10.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     10.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     10.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     10.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     10.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     10.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     10.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     10.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     10.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead               15571985     66.15%     76.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               5503822     23.38%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass              2752      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu            1250439249     57.30%     57.30% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                17094      0.00%     57.30% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     57.30% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd            27851471      1.28%     58.57% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp             8254698      0.38%     58.95% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt             7204651      0.33%     59.28% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  4      0.00%     59.28% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     59.28% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     59.28% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     59.28% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     59.28% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     59.28% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     59.28% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     59.28% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     59.28% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     59.28% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     59.28% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     59.28% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     59.28% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     59.28% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     59.28% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     59.28% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     59.28% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     59.28% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     59.28% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     59.28% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     59.28% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     59.28% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     59.28% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            592678275     27.16%     86.44% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite           295948284     13.56%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass              1276      0.00%      0.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             579410115     57.05%     57.05% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                 7864      0.00%     57.05% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     57.05% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd            13181855      1.30%     58.35% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp             3826543      0.38%     58.73% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt             3339802      0.33%     59.06% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  4      0.00%     59.06% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     59.06% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     59.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     59.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     59.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     59.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     59.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     59.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     59.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     59.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     59.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     59.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     59.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     59.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     59.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     59.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     59.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     59.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     59.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     59.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     59.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     59.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     59.06% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            276884212     27.26%     86.32% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite           138933358     13.68%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total             2182396478                       # Type of FU issued
-system.cpu.iq.rate                           1.715911                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                    40372505                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.018499                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         5521594502                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes        3528574475                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses   2004997019                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads           151784518                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes           88865161                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses     73949462                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses             2144972289                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                77793942                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads         63261686                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total             1015585029                       # Type of FU issued
+system.cpu.iq.rate                           1.825470                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    23540305                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.023179                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         2548815722                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes        1726656461                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    939949010                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads            70808195                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes           41310105                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses     34425215                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses             1002762123                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                36361935                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads         50443717                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads    265614506                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        19945                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        77572                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores    150860905                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads    135060050                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses      1143240                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        45700                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores     77095788                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads         4433                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked          3083                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads         2279                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked          4366                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles              147805302                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                 7602167                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                279549                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts          3087695808                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts             56386                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             776684532                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts            361655801                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts                 90                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                 141634                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                 84137                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          77572                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect       25803318                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect        28659                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts             25831977                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts            2081430874                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             522925034                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts         100965604                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles               12111828                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                61105954                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                191244                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts          1479623370                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts             16690                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             372570647                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts            175396988                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts                121                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                  26783                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                176241                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          45700                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect       11878414                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect        16350                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts             11894764                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             976099064                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             244811165                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          39485965                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                     367473285                       # number of nop insts executed
-system.cpu.iew.exec_refs                    813299641                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                277669733                       # Number of branches executed
-system.cpu.iew.exec_stores                  290374607                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.636526                       # Inst execution rate
-system.cpu.iew.wb_sent                     2081298559                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                    2078946481                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                1190563677                       # num instructions producing a value
-system.cpu.iew.wb_consumers                1779120207                       # num instructions consuming a value
+system.cpu.iew.exec_nop                     174458569                       # number of nop insts executed
+system.cpu.iew.exec_refs                    380521398                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                129090215                       # Number of branches executed
+system.cpu.iew.exec_stores                  135710233                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.754495                       # Inst execution rate
+system.cpu.iew.wb_sent                      974894086                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     974374225                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 556362190                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 832682807                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.634573                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.669187                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.751395                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.668156                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts      1061256381                       # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls              39                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts          25797472                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples   1102490986                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.822226                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.529076                       # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts       543793882                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls              37                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts          11877823                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    483108609                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.922109                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.601347                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    487378417     44.21%     44.21% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1    227745323     20.66%     64.86% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2    117618714     10.67%     75.53% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     58023945      5.26%     80.80% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     49786654      4.52%     85.31% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5     22711490      2.06%     87.37% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6     18023785      1.63%     89.01% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7     18535022      1.68%     90.69% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8    102667636      9.31%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    205236337     42.48%     42.48% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    102049514     21.12%     63.61% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     51661331     10.69%     74.30% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     25803847      5.34%     79.64% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     21528421      4.46%     84.10% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      9152086      1.89%     85.99% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6     10413942      2.16%     88.15% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      6658903      1.38%     89.53% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     50604228     10.47%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total   1102490986                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts           2008987604                       # Number of instructions committed
-system.cpu.commit.committedOps             2008987604                       # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total    483108609                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts            928587628                       # Number of instructions committed
+system.cpu.commit.committedOps              928587628                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                      721864922                       # Number of memory references committed
-system.cpu.commit.loads                     511070026                       # Number of loads committed
+system.cpu.commit.refs                      335811797                       # Number of memory references committed
+system.cpu.commit.loads                     237510597                       # Number of loads committed
 system.cpu.commit.membars                           0                       # Number of memory barriers committed
-system.cpu.commit.branches                  266706457                       # Number of branches committed
-system.cpu.commit.fp_insts                   71824891                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                1778941351                       # Number of committed integer instructions.
-system.cpu.commit.function_calls             39955347                       # Number of function calls committed.
-system.cpu.commit.op_class_0::No_OpClass    185946986      9.26%      9.26% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu       1058512436     52.69%     61.94% # Class of committed instruction
-system.cpu.commit.op_class_0::IntMult           15158      0.00%     61.95% # Class of committed instruction
-system.cpu.commit.op_class_0::IntDiv                0      0.00%     61.95% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatAdd       27517120      1.37%     63.32% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatCmp        8254514      0.41%     63.73% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatCvt        6876464      0.34%     64.07% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMult             4      0.00%     64.07% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatDiv              0      0.00%     64.07% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     64.07% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAdd               0      0.00%     64.07% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     64.07% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAlu               0      0.00%     64.07% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdCmp               0      0.00%     64.07% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdCvt               0      0.00%     64.07% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMisc              0      0.00%     64.07% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMult              0      0.00%     64.07% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     64.07% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdShift             0      0.00%     64.07% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     64.07% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     64.07% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     64.07% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     64.07% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     64.07% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     64.07% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     64.07% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMisc            0      0.00%     64.07% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     64.07% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     64.07% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     64.07% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead       511070026     25.44%     89.51% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite      210794896     10.49%    100.00% # Class of committed instruction
+system.cpu.commit.branches                  123111018                       # Number of branches committed
+system.cpu.commit.fp_insts                   33436273                       # Number of committed floating point instructions.
+system.cpu.commit.int_insts                 821934723                       # Number of committed integer instructions.
+system.cpu.commit.function_calls             18524163                       # Number of function calls committed.
+system.cpu.commit.op_class_0::No_OpClass     86206875      9.28%      9.28% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu        486529510     52.39%     61.68% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult            7040      0.00%     61.68% # Class of committed instruction
+system.cpu.commit.op_class_0::IntDiv                0      0.00%     61.68% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatAdd       13018262      1.40%     63.08% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCmp        3826477      0.41%     63.49% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCvt        3187663      0.34%     63.84% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatMult             4      0.00%     63.84% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatDiv              0      0.00%     63.84% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     63.84% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAdd               0      0.00%     63.84% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     63.84% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAlu               0      0.00%     63.84% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCmp               0      0.00%     63.84% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCvt               0      0.00%     63.84% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMisc              0      0.00%     63.84% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMult              0      0.00%     63.84% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     63.84% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShift             0      0.00%     63.84% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     63.84% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     63.84% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     63.84% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     63.84% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     63.84% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     63.84% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     63.84% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMisc            0      0.00%     63.84% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     63.84% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     63.84% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     63.84% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead       237510597     25.58%     89.41% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite       98301200     10.59%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total        2008987604                       # Class of committed instruction
-system.cpu.commit.bw_lim_events             102667636                       # number cycles where commit BW limit reached
+system.cpu.commit.op_class_0::total         928587628                       # Class of committed instruction
+system.cpu.commit.bw_lim_events              50604228                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                   4064430925                       # The number of ROB reads
-system.cpu.rob.rob_writes                  6288295371                       # The number of ROB writes
-system.cpu.timesIdled                          345316                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                        21562702                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts                  1823043370                       # Number of Instructions Simulated
-system.cpu.committedOps                    1823043370                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               0.697657                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.697657                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.433369                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.433369                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               2650222630                       # number of integer regfile reads
-system.cpu.int_regfile_writes              1504597172                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                  79149378                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                 52661639                       # number of floating regfile writes
+system.cpu.rob.rob_reads                   1902264753                       # The number of ROB reads
+system.cpu.rob.rob_writes                  3017778261                       # The number of ROB writes
+system.cpu.timesIdled                            3284                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                          219157                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts                   842382029                       # Number of Instructions Simulated
+system.cpu.committedOps                     842382029                       # Number of Ops (including micro ops) Simulated
+system.cpu.cpi                               0.660439                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.660439                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.514145                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.514145                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               1237156032                       # number of integer regfile reads
+system.cpu.int_regfile_writes               705771856                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                  36691388                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                 24411317                       # number of floating regfile writes
 system.cpu.misc_regfile_reads                       1                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
-system.cpu.toL2Bus.throughput               164848262                       # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq        1470375                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       1470374                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback        95981                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq        71643                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp        71643                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        20103                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      3159913                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           3180016                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       643264                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    104188608                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total      104831872                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus         104831872                       # Total data (bytes)
+system.cpu.toL2Bus.throughput               202299828                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq         718925                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp        718924                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback        91520                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq        68836                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp        68836                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        12807                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      1654234                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           1667041                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       409792                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     55864128                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total       56273920                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus          56273920                       # Total data (bytes)
 system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy      914980500                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy      15576999                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.occupancy      531160500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          0.2                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy      10099250                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    2360120750                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    1208088500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.4                       # Layer utilization (%)
-system.cpu.icache.tags.replacements              8337                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1659.365799                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           408871331                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs             10051                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          40679.666799                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements              4693                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1650.457565                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           196834917                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs              6403                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          30741.045916                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1659.365799                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.810237                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.810237                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024         1714                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           79                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1           74                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_blocks::cpu.inst  1650.457565                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.805887                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.805887                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1710                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           80                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           84                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::2            1                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4         1560                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.836914                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         817778319                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        817778319                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    408871331                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       408871331                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     408871331                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        408871331                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    408871331                       # number of overall hits
-system.cpu.icache.overall_hits::total       408871331                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst        12803                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total         12803                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst        12803                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total          12803                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst        12803                       # number of overall misses
-system.cpu.icache.overall_misses::total         12803                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    381292998                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    381292998                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    381292998                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    381292998                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    381292998                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    381292998                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    408884134                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    408884134                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    408884134                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    408884134                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    408884134                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    408884134                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000031                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000031                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000031                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000031                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000031                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000031                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 29781.535421                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 29781.535421                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 29781.535421                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 29781.535421                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 29781.535421                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 29781.535421                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs          690                       # number of cycles access was blocked
+system.cpu.icache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1543                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.834961                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses         393692951                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        393692951                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    196834917                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       196834917                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     196834917                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        196834917                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    196834917                       # number of overall hits
+system.cpu.icache.overall_hits::total       196834917                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         8357                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          8357                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         8357                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           8357                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         8357                       # number of overall misses
+system.cpu.icache.overall_misses::total          8357                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    329567249                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    329567249                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    329567249                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    329567249                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    329567249                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    329567249                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    196843274                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    196843274                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    196843274                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    196843274                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    196843274                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    196843274                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000042                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000042                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000042                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000042                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000042                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000042                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 39436.071437                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 39436.071437                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 39436.071437                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 39436.071437                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 39436.071437                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 39436.071437                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs          515                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                12                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                11                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    57.500000                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    46.818182                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst         2751                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total         2751                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst         2751                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total         2751                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst         2751                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total         2751                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst        10052                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total        10052                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst        10052                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total        10052                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst        10052                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total        10052                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    281850750                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    281850750                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    281850750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    281850750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    281850750                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    281850750                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000025                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000025                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000025                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.000025                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000025                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.000025                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 28039.270792                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 28039.270792                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 28039.270792                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 28039.270792                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 28039.270792                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 28039.270792                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         1953                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total         1953                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst         1953                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total         1953                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst         1953                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total         1953                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst         6404                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total         6404                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst         6404                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total         6404                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst         6404                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total         6404                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    242038999                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    242038999                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    242038999                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    242038999                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    242038999                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    242038999                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000033                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000033                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000033                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.000033                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000033                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.000033                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37794.971736                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37794.971736                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37794.971736                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 37794.971736                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37794.971736                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 37794.971736                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements           443352                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        32689.433900                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            1090130                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           476087                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             2.289771                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements           258665                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        32635.252362                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs             518921                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           291402                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             1.780774                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks  1333.307331                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst    35.512650                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 31320.613920                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.040689                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.001084                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.955829                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.997602                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        32735                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          158                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          196                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          501                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         4985                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        26895                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.998993                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         13651722                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        13651722                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst         7290                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data      1053808                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        1061098                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks        95981                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total        95981                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data         4789                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total         4789                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst         7290                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      1058597                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         1065887                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst         7290                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      1058597                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        1065887                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst         2762                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data       406515                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total       409277                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data        66854                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total        66854                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         2762                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       473369                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        476131                       # number of demand (read+write) misses
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 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -820,173 +820,173 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
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+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64783.750319                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59748.636859                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61630.675146                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61612.910199                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59748.636859                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61630.675146                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61612.910199                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements           1527870                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4094.609891                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           666862520                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           1531966                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            435.298512                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         407274250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4094.609891                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999661                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999661                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements            777261                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4093.039148                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           289853249                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            781357                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs            370.961352                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle         354310000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4093.039148                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.999277                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999277                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           85                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          287                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           90                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          299                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::2          967                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3         2348                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::4          409                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3         2496                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4          244                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses        1341234178                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses       1341234178                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    457128371                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       457128371                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    209734126                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      209734126                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data           23                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total           23                       # number of LoadLockedReq hits
-system.cpu.dcache.demand_hits::cpu.data     666862497                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        666862497                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    666862497                       # number of overall hits
-system.cpu.dcache.overall_hits::total       666862497                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      1927816                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       1927816                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      1060770                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      1060770                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data      2988586                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        2988586                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      2988586                       # number of overall misses
-system.cpu.dcache.overall_misses::total       2988586                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  76893359750                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  76893359750                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  46482150765                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  46482150765                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 123375510515                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 123375510515                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 123375510515                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 123375510515                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    459056187                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    459056187                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data    210794896                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total    210794896                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data           23                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total           23                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    669851083                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    669851083                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    669851083                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    669851083                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.004200                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.004200                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.005032                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.005032                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.004462                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.004462                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.004462                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.004462                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 39886.254575                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 39886.254575                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43819.254659                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 43819.254659                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 41282.235316                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 41282.235316                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 41282.235316                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 41282.235316                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs        19699                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets          140                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs               433                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               1                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    45.494226                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets          140                       # average number of cycles each access was blocked
+system.cpu.dcache.tags.tag_accesses         585486507                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        585486507                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    192472293                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       192472293                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     97380937                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       97380937                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data           19                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total           19                       # number of LoadLockedReq hits
+system.cpu.dcache.demand_hits::cpu.data     289853230                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        289853230                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    289853230                       # number of overall hits
+system.cpu.dcache.overall_hits::total       289853230                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      1579063                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       1579063                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       920263                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       920263                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data      2499326                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        2499326                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      2499326                       # number of overall misses
+system.cpu.dcache.overall_misses::total       2499326                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  79789190750                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  79789190750                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  57377622714                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  57377622714                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 137166813464                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 137166813464                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 137166813464                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 137166813464                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    194051356                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    194051356                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data     98301200                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total     98301200                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data           19                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total           19                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data    292352556                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    292352556                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    292352556                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    292352556                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.008137                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.008137                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.009362                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.009362                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.008549                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.008549                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.008549                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.008549                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50529.453701                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 50529.453701                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62349.157484                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 62349.157484                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 54881.521444                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 54881.521444                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 54881.521444                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 54881.521444                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs        22462                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets        55443                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs               471                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets             516                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    47.690021                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets   107.447674                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks        95981                       # number of writebacks
-system.cpu.dcache.writebacks::total             95981                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       467493                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       467493                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       989127                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       989127                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      1456620                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      1456620                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      1456620                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      1456620                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1460323                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      1460323                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data        71643                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total        71643                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      1531966                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      1531966                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      1531966                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      1531966                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  40901282750                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  40901282750                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   5350796500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   5350796500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  46252079250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  46252079250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  46252079250                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  46252079250                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.003181                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.003181                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000340                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000340                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.002287                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.002287                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.002287                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.002287                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 28008.380851                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 28008.380851                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74686.940804                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74686.940804                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30191.322294                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 30191.322294                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30191.322294                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 30191.322294                       # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks        91520                       # number of writebacks
+system.cpu.dcache.writebacks::total             91520                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       866542                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       866542                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       851427                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       851427                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      1717969                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      1717969                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      1717969                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      1717969                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       712521                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       712521                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data        68836                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total        68836                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       781357                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       781357                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       781357                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       781357                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  21863154000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  21863154000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   5224164248                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   5224164248                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  27087318248                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  27087318248                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  27087318248                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  27087318248                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.003672                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.003672                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000700                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000700                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.002673                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.002673                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.002673                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.002673                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30684.224044                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30684.224044                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75892.908478                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75892.908478                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34667.019362                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 34667.019362                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34667.019362                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 34667.019362                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt
index 6bfc9d3ce..2d72b8ec8 100644
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt
@@ -1,64 +1,64 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  1.004711                       # Number of seconds simulated
-sim_ticks                                1004710587000                       # Number of ticks simulated
-final_tick                               1004710587000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.464395                       # Number of seconds simulated
+sim_ticks                                464394627000                       # Number of ticks simulated
+final_tick                               464394627000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                2670371                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2670371                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1335473702                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 265688                       # Number of bytes of host memory used
-host_seconds                                   752.33                       # Real time elapsed on the host
-sim_insts                                  2008987605                       # Number of instructions simulated
-sim_ops                                    2008987605                       # Number of ops (including micro ops) simulated
+host_inst_rate                                1843860                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1843860                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              922130037                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 234352                       # Number of bytes of host memory used
+host_seconds                                   503.61                       # Real time elapsed on the host
+sim_insts                                   928587629                       # Number of instructions simulated
+sim_ops                                     928587629                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst        8037684280                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data        3569416716                       # Number of bytes read from this memory
-system.physmem.bytes_read::total          11607100996                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst   8037684280                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total      8037684280                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::cpu.data     1586125963                       # Number of bytes written to this memory
-system.physmem.bytes_written::total        1586125963                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst         2009421070                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data          511070026                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total            2520491096                       # Number of read requests responded to by this memory
-system.physmem.num_writes::cpu.data         210794896                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total            210794896                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst           7999999586                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data           3552681501                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total             11552681087                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst      7999999586                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total         7999999586                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data          1578689409                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total             1578689409                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst          7999999586                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data          5131370910                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total            13131370496                       # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput                  13131370496                       # Throughput (bytes/s)
-system.membus.data_through_bus            13193226959                       # Total data (bytes)
+system.physmem.bytes_read::cpu.inst        3715156600                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data        1657129778                       # Number of bytes read from this memory
+system.physmem.bytes_read::total           5372286378                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst   3715156600                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total      3715156600                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::cpu.data      737675461                       # Number of bytes written to this memory
+system.physmem.bytes_written::total         737675461                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst          928789150                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data          237510597                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total            1166299747                       # Number of read requests responded to by this memory
+system.physmem.num_writes::cpu.data          98301200                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total             98301200                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst           7999999104                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data           3568365527                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total             11568364631                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst      7999999104                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total         7999999104                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data          1588466830                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total             1588466830                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst          7999999104                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data          5156832357                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total            13156831461                       # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput                  13156831461                       # Throughput (bytes/s)
+system.membus.data_through_bus             6109961839                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                    511070026                       # DTB read hits
-system.cpu.dtb.read_misses                     418884                       # DTB read misses
+system.cpu.dtb.read_hits                    237510597                       # DTB read hits
+system.cpu.dtb.read_misses                     194650                       # DTB read misses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                511488910                       # DTB read accesses
-system.cpu.dtb.write_hits                   210794896                       # DTB write hits
-system.cpu.dtb.write_misses                     14581                       # DTB write misses
+system.cpu.dtb.read_accesses                237705247                       # DTB read accesses
+system.cpu.dtb.write_hits                    98301200                       # DTB write hits
+system.cpu.dtb.write_misses                      6871                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses               210809477                       # DTB write accesses
-system.cpu.dtb.data_hits                    721864922                       # DTB hits
-system.cpu.dtb.data_misses                     433465                       # DTB misses
+system.cpu.dtb.write_accesses                98308071                       # DTB write accesses
+system.cpu.dtb.data_hits                    335811797                       # DTB hits
+system.cpu.dtb.data_misses                     201521                       # DTB misses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                722298387                       # DTB accesses
-system.cpu.itb.fetch_hits                  2009421070                       # ITB hits
+system.cpu.dtb.data_accesses                336013318                       # DTB accesses
+system.cpu.itb.fetch_hits                   928789150                       # ITB hits
 system.cpu.itb.fetch_misses                       105                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses              2009421175                       # ITB accesses
+system.cpu.itb.fetch_accesses               928789255                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -71,64 +71,64 @@ system.cpu.itb.data_hits                            0                       # DT
 system.cpu.itb.data_misses                          0                       # DTB misses
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
-system.cpu.workload.num_syscalls                   39                       # Number of system calls
-system.cpu.numCycles                       2009421175                       # number of cpu cycles simulated
+system.cpu.workload.num_syscalls                   37                       # Number of system calls
+system.cpu.numCycles                        928789255                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                  2008987605                       # Number of instructions committed
-system.cpu.committedOps                    2008987605                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses            1779374816                       # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses               71831671                       # Number of float alu accesses
-system.cpu.num_func_calls                    79910682                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts    172959296                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                   1779374816                       # number of integer instructions
-system.cpu.num_fp_insts                      71831671                       # number of float instructions
-system.cpu.num_int_register_reads          2314712013                       # number of times the integer registers were read
-system.cpu.num_int_register_writes         1332688300                       # number of times the integer registers were written
-system.cpu.num_fp_register_reads             77066699                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes            52280770                       # number of times the floating registers were written
-system.cpu.num_mem_refs                     722298387                       # number of memory refs
-system.cpu.num_load_insts                   511488910                       # Number of load instructions
-system.cpu.num_store_insts                  210809477                       # Number of store instructions
+system.cpu.committedInsts                   928587629                       # Number of instructions committed
+system.cpu.committedOps                     928587629                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses             822136244                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses               33439365                       # Number of float alu accesses
+system.cpu.num_func_calls                    37048314                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts     79645038                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                    822136244                       # number of integer instructions
+system.cpu.num_fp_insts                      33439365                       # number of float instructions
+system.cpu.num_int_register_reads          1066359180                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          614731604                       # number of times the integer registers were written
+system.cpu.num_fp_register_reads             35725528                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes            24235554                       # number of times the floating registers were written
+system.cpu.num_mem_refs                     336013318                       # number of memory refs
+system.cpu.num_load_insts                   237705247                       # Number of load instructions
+system.cpu.num_store_insts                   98308071                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                 2009421175                       # Number of busy cycles
+system.cpu.num_busy_cycles                  928789255                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
-system.cpu.Branches                         266706457                       # Number of branches fetched
-system.cpu.op_class::No_OpClass             185946986      9.25%      9.25% # Class of executed instruction
-system.cpu.op_class::IntAlu                1058512437     52.68%     61.93% # Class of executed instruction
-system.cpu.op_class::IntMult                    15158      0.00%     61.93% # Class of executed instruction
-system.cpu.op_class::IntDiv                         0      0.00%     61.93% # Class of executed instruction
-system.cpu.op_class::FloatAdd                27517120      1.37%     63.30% # Class of executed instruction
-system.cpu.op_class::FloatCmp                 8254514      0.41%     63.71% # Class of executed instruction
-system.cpu.op_class::FloatCvt                 6876464      0.34%     64.05% # Class of executed instruction
-system.cpu.op_class::FloatMult                      4      0.00%     64.05% # Class of executed instruction
-system.cpu.op_class::FloatDiv                       0      0.00%     64.05% # Class of executed instruction
-system.cpu.op_class::FloatSqrt                      0      0.00%     64.05% # Class of executed instruction
-system.cpu.op_class::SimdAdd                        0      0.00%     64.05% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc                     0      0.00%     64.05% # Class of executed instruction
-system.cpu.op_class::SimdAlu                        0      0.00%     64.05% # Class of executed instruction
-system.cpu.op_class::SimdCmp                        0      0.00%     64.05% # Class of executed instruction
-system.cpu.op_class::SimdCvt                        0      0.00%     64.05% # Class of executed instruction
-system.cpu.op_class::SimdMisc                       0      0.00%     64.05% # Class of executed instruction
-system.cpu.op_class::SimdMult                       0      0.00%     64.05% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc                    0      0.00%     64.05% # Class of executed instruction
-system.cpu.op_class::SimdShift                      0      0.00%     64.05% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc                   0      0.00%     64.05% # Class of executed instruction
-system.cpu.op_class::SimdSqrt                       0      0.00%     64.05% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd                   0      0.00%     64.05% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu                   0      0.00%     64.05% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp                   0      0.00%     64.05% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt                   0      0.00%     64.05% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv                   0      0.00%     64.05% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc                  0      0.00%     64.05% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult                  0      0.00%     64.05% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc               0      0.00%     64.05% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt                  0      0.00%     64.05% # Class of executed instruction
-system.cpu.op_class::MemRead                511488910     25.45%     89.51% # Class of executed instruction
-system.cpu.op_class::MemWrite               210809477     10.49%    100.00% # Class of executed instruction
+system.cpu.Branches                         123111018                       # Number of branches fetched
+system.cpu.op_class::No_OpClass              86206875      9.28%      9.28% # Class of executed instruction
+system.cpu.op_class::IntAlu                 486529511     52.38%     61.66% # Class of executed instruction
+system.cpu.op_class::IntMult                     7040      0.00%     61.67% # Class of executed instruction
+system.cpu.op_class::IntDiv                         0      0.00%     61.67% # Class of executed instruction
+system.cpu.op_class::FloatAdd                13018262      1.40%     63.07% # Class of executed instruction
+system.cpu.op_class::FloatCmp                 3826477      0.41%     63.48% # Class of executed instruction
+system.cpu.op_class::FloatCvt                 3187663      0.34%     63.82% # Class of executed instruction
+system.cpu.op_class::FloatMult                      4      0.00%     63.82% # Class of executed instruction
+system.cpu.op_class::FloatDiv                       0      0.00%     63.82% # Class of executed instruction
+system.cpu.op_class::FloatSqrt                      0      0.00%     63.82% # Class of executed instruction
+system.cpu.op_class::SimdAdd                        0      0.00%     63.82% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc                     0      0.00%     63.82% # Class of executed instruction
+system.cpu.op_class::SimdAlu                        0      0.00%     63.82% # Class of executed instruction
+system.cpu.op_class::SimdCmp                        0      0.00%     63.82% # Class of executed instruction
+system.cpu.op_class::SimdCvt                        0      0.00%     63.82% # Class of executed instruction
+system.cpu.op_class::SimdMisc                       0      0.00%     63.82% # Class of executed instruction
+system.cpu.op_class::SimdMult                       0      0.00%     63.82% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc                    0      0.00%     63.82% # Class of executed instruction
+system.cpu.op_class::SimdShift                      0      0.00%     63.82% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc                   0      0.00%     63.82% # Class of executed instruction
+system.cpu.op_class::SimdSqrt                       0      0.00%     63.82% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd                   0      0.00%     63.82% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu                   0      0.00%     63.82% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp                   0      0.00%     63.82% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt                   0      0.00%     63.82% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv                   0      0.00%     63.82% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc                  0      0.00%     63.82% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult                  0      0.00%     63.82% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc               0      0.00%     63.82% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt                  0      0.00%     63.82% # Class of executed instruction
+system.cpu.op_class::MemRead                237705247     25.59%     89.42% # Class of executed instruction
+system.cpu.op_class::MemWrite                98308071     10.58%    100.00% # Class of executed instruction
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::total                 2009421070                       # Class of executed instruction
+system.cpu.op_class::total                  928789150                       # Class of executed instruction
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt
index ef8e8a3ca..9f0d0f3c5 100644
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt
@@ -1,78 +1,78 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.769740                       # Number of seconds simulated
-sim_ticks                                2769739533000                       # Number of ticks simulated
-final_tick                               2769739533000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  1.286250                       # Number of seconds simulated
+sim_ticks                                1286249820000                       # Number of ticks simulated
+final_tick                               1286249820000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1094265                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1094265                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1508635104                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 274392                       # Number of bytes of host memory used
-host_seconds                                  1835.92                       # Real time elapsed on the host
-sim_insts                                  2008987605                       # Number of instructions simulated
-sim_ops                                    2008987605                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 839019                       # Simulator instruction rate (inst/s)
+host_op_rate                                   839019                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1162182391                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 244120                       # Number of bytes of host memory used
+host_seconds                                  1106.75                       # Real time elapsed on the host
+sim_insts                                   928587629                       # Number of instructions simulated
+sim_ops                                     928587629                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst            137792                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          30284544                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             30422336                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          18465664                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             18603456                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read::cpu.inst       137792                       # Number of instructions bytes read from this memory
 system.physmem.bytes_inst_read::total          137792                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      4282112                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           4282112                       # Number of bytes written to this memory
+system.physmem.bytes_written::writebacks      4267712                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           4267712                       # Number of bytes written to this memory
 system.physmem.num_reads::cpu.inst               2153                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             473196                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                475349                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           66908                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total                66908                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst                49749                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             10934077                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                10983826                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst           49749                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total              49749                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1546034                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1546034                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1546034                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst               49749                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            10934077                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               12529860                       # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput                     12529860                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq              408476                       # Transaction distribution
-system.membus.trans_dist::ReadResp             408476                       # Transaction distribution
-system.membus.trans_dist::Writeback             66908                       # Transaction distribution
-system.membus.trans_dist::ReadExReq             66873                       # Transaction distribution
-system.membus.trans_dist::ReadExResp            66873                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1017606                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1017606                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     34704448                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total            34704448                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus               34704448                       # Total data (bytes)
+system.physmem.num_reads::cpu.data             288526                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                290679                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           66683                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                66683                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst               107127                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             14356203                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                14463330                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          107127                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             107127                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           3317950                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                3317950                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           3317950                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              107127                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            14356203                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               17781280                       # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput                     17781280                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq              224031                       # Transaction distribution
+system.membus.trans_dist::ReadResp             224031                       # Transaction distribution
+system.membus.trans_dist::Writeback             66683                       # Transaction distribution
+system.membus.trans_dist::ReadExReq             66648                       # Transaction distribution
+system.membus.trans_dist::ReadExResp            66648                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       648041                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 648041                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     22871168                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total            22871168                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus               22871168                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy          1077521000                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         4278141000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy           890826000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               0.1                       # Layer utilization (%)
+system.membus.respLayer1.occupancy         2616111000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                    511070026                       # DTB read hits
-system.cpu.dtb.read_misses                     418884                       # DTB read misses
+system.cpu.dtb.read_hits                    237510597                       # DTB read hits
+system.cpu.dtb.read_misses                     194650                       # DTB read misses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                511488910                       # DTB read accesses
-system.cpu.dtb.write_hits                   210794896                       # DTB write hits
-system.cpu.dtb.write_misses                     14581                       # DTB write misses
+system.cpu.dtb.read_accesses                237705247                       # DTB read accesses
+system.cpu.dtb.write_hits                    98301200                       # DTB write hits
+system.cpu.dtb.write_misses                      6871                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses               210809477                       # DTB write accesses
-system.cpu.dtb.data_hits                    721864922                       # DTB hits
-system.cpu.dtb.data_misses                     433465                       # DTB misses
+system.cpu.dtb.write_accesses                98308071                       # DTB write accesses
+system.cpu.dtb.data_hits                    335811797                       # DTB hits
+system.cpu.dtb.data_misses                     201521                       # DTB misses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                722298387                       # DTB accesses
-system.cpu.itb.fetch_hits                  2009421071                       # ITB hits
+system.cpu.dtb.data_accesses                336013318                       # DTB accesses
+system.cpu.itb.fetch_hits                   928789151                       # ITB hits
 system.cpu.itb.fetch_misses                       105                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses              2009421176                       # ITB accesses
+system.cpu.itb.fetch_accesses               928789256                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -85,118 +85,118 @@ system.cpu.itb.data_hits                            0                       # DT
 system.cpu.itb.data_misses                          0                       # DTB misses
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
-system.cpu.workload.num_syscalls                   39                       # Number of system calls
-system.cpu.numCycles                       5539479066                       # number of cpu cycles simulated
+system.cpu.workload.num_syscalls                   37                       # Number of system calls
+system.cpu.numCycles                       2572499640                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                  2008987605                       # Number of instructions committed
-system.cpu.committedOps                    2008987605                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses            1779374816                       # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses               71831671                       # Number of float alu accesses
-system.cpu.num_func_calls                    79910682                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts    172959296                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                   1779374816                       # number of integer instructions
-system.cpu.num_fp_insts                      71831671                       # number of float instructions
-system.cpu.num_int_register_reads          2314712013                       # number of times the integer registers were read
-system.cpu.num_int_register_writes         1332688300                       # number of times the integer registers were written
-system.cpu.num_fp_register_reads             77066699                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes            52280770                       # number of times the floating registers were written
-system.cpu.num_mem_refs                     722298387                       # number of memory refs
-system.cpu.num_load_insts                   511488910                       # Number of load instructions
-system.cpu.num_store_insts                  210809477                       # Number of store instructions
+system.cpu.committedInsts                   928587629                       # Number of instructions committed
+system.cpu.committedOps                     928587629                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses             822136244                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses               33439365                       # Number of float alu accesses
+system.cpu.num_func_calls                    37048314                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts     79645038                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                    822136244                       # number of integer instructions
+system.cpu.num_fp_insts                      33439365                       # number of float instructions
+system.cpu.num_int_register_reads          1066359180                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          614731604                       # number of times the integer registers were written
+system.cpu.num_fp_register_reads             35725528                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes            24235554                       # number of times the floating registers were written
+system.cpu.num_mem_refs                     336013318                       # number of memory refs
+system.cpu.num_load_insts                   237705247                       # Number of load instructions
+system.cpu.num_store_insts                   98308071                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                 5539479066                       # Number of busy cycles
+system.cpu.num_busy_cycles                 2572499640                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
-system.cpu.Branches                         266706457                       # Number of branches fetched
-system.cpu.op_class::No_OpClass             185946986      9.25%      9.25% # Class of executed instruction
-system.cpu.op_class::IntAlu                1058512437     52.68%     61.93% # Class of executed instruction
-system.cpu.op_class::IntMult                    15158      0.00%     61.93% # Class of executed instruction
-system.cpu.op_class::IntDiv                         0      0.00%     61.93% # Class of executed instruction
-system.cpu.op_class::FloatAdd                27517120      1.37%     63.30% # Class of executed instruction
-system.cpu.op_class::FloatCmp                 8254514      0.41%     63.71% # Class of executed instruction
-system.cpu.op_class::FloatCvt                 6876464      0.34%     64.05% # Class of executed instruction
-system.cpu.op_class::FloatMult                      4      0.00%     64.05% # Class of executed instruction
-system.cpu.op_class::FloatDiv                       0      0.00%     64.05% # Class of executed instruction
-system.cpu.op_class::FloatSqrt                      0      0.00%     64.05% # Class of executed instruction
-system.cpu.op_class::SimdAdd                        0      0.00%     64.05% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc                     0      0.00%     64.05% # Class of executed instruction
-system.cpu.op_class::SimdAlu                        0      0.00%     64.05% # Class of executed instruction
-system.cpu.op_class::SimdCmp                        0      0.00%     64.05% # Class of executed instruction
-system.cpu.op_class::SimdCvt                        0      0.00%     64.05% # Class of executed instruction
-system.cpu.op_class::SimdMisc                       0      0.00%     64.05% # Class of executed instruction
-system.cpu.op_class::SimdMult                       0      0.00%     64.05% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc                    0      0.00%     64.05% # Class of executed instruction
-system.cpu.op_class::SimdShift                      0      0.00%     64.05% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc                   0      0.00%     64.05% # Class of executed instruction
-system.cpu.op_class::SimdSqrt                       0      0.00%     64.05% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd                   0      0.00%     64.05% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu                   0      0.00%     64.05% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp                   0      0.00%     64.05% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt                   0      0.00%     64.05% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv                   0      0.00%     64.05% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc                  0      0.00%     64.05% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult                  0      0.00%     64.05% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc               0      0.00%     64.05% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt                  0      0.00%     64.05% # Class of executed instruction
-system.cpu.op_class::MemRead                511488910     25.45%     89.51% # Class of executed instruction
-system.cpu.op_class::MemWrite               210809477     10.49%    100.00% # Class of executed instruction
+system.cpu.Branches                         123111018                       # Number of branches fetched
+system.cpu.op_class::No_OpClass              86206875      9.28%      9.28% # Class of executed instruction
+system.cpu.op_class::IntAlu                 486529511     52.38%     61.66% # Class of executed instruction
+system.cpu.op_class::IntMult                     7040      0.00%     61.67% # Class of executed instruction
+system.cpu.op_class::IntDiv                         0      0.00%     61.67% # Class of executed instruction
+system.cpu.op_class::FloatAdd                13018262      1.40%     63.07% # Class of executed instruction
+system.cpu.op_class::FloatCmp                 3826477      0.41%     63.48% # Class of executed instruction
+system.cpu.op_class::FloatCvt                 3187663      0.34%     63.82% # Class of executed instruction
+system.cpu.op_class::FloatMult                      4      0.00%     63.82% # Class of executed instruction
+system.cpu.op_class::FloatDiv                       0      0.00%     63.82% # Class of executed instruction
+system.cpu.op_class::FloatSqrt                      0      0.00%     63.82% # Class of executed instruction
+system.cpu.op_class::SimdAdd                        0      0.00%     63.82% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc                     0      0.00%     63.82% # Class of executed instruction
+system.cpu.op_class::SimdAlu                        0      0.00%     63.82% # Class of executed instruction
+system.cpu.op_class::SimdCmp                        0      0.00%     63.82% # Class of executed instruction
+system.cpu.op_class::SimdCvt                        0      0.00%     63.82% # Class of executed instruction
+system.cpu.op_class::SimdMisc                       0      0.00%     63.82% # Class of executed instruction
+system.cpu.op_class::SimdMult                       0      0.00%     63.82% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc                    0      0.00%     63.82% # Class of executed instruction
+system.cpu.op_class::SimdShift                      0      0.00%     63.82% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc                   0      0.00%     63.82% # Class of executed instruction
+system.cpu.op_class::SimdSqrt                       0      0.00%     63.82% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd                   0      0.00%     63.82% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu                   0      0.00%     63.82% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp                   0      0.00%     63.82% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt                   0      0.00%     63.82% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv                   0      0.00%     63.82% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc                  0      0.00%     63.82% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult                  0      0.00%     63.82% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc               0      0.00%     63.82% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt                  0      0.00%     63.82% # Class of executed instruction
+system.cpu.op_class::MemRead                237705247     25.59%     89.42% # Class of executed instruction
+system.cpu.op_class::MemWrite                98308071     10.58%    100.00% # Class of executed instruction
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::total                 2009421070                       # Class of executed instruction
-system.cpu.icache.tags.replacements              9046                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1478.418050                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs          2009410475                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs             10596                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          189638.587675                       # Average number of references to valid blocks.
+system.cpu.op_class::total                  928789150                       # Class of executed instruction
+system.cpu.icache.tags.replacements              4618                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1474.486239                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           928782983                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs              6168                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          150580.898671                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1478.418050                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.721884                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.721884                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst  1474.486239                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.719964                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.719964                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         1550                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           47                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1           72                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::3            3                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::4         1428                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.756836                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses        4018852738                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses       4018852738                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst   2009410475                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total      2009410475                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst    2009410475                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total       2009410475                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst   2009410475                       # number of overall hits
-system.cpu.icache.overall_hits::total      2009410475                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst        10596                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total         10596                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst        10596                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total          10596                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst        10596                       # number of overall misses
-system.cpu.icache.overall_misses::total         10596                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    228174000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    228174000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    228174000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    228174000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    228174000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    228174000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst   2009421071                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total   2009421071                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst   2009421071                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total   2009421071                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst   2009421071                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total   2009421071                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000005                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000005                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000005                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000005                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000005                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000005                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21533.975085                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 21533.975085                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 21533.975085                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 21533.975085                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 21533.975085                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 21533.975085                       # average overall miss latency
+system.cpu.icache.tags.tag_accesses        1857584470                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses       1857584470                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    928782983                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       928782983                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     928782983                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        928782983                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    928782983                       # number of overall hits
+system.cpu.icache.overall_hits::total       928782983                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         6168                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          6168                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         6168                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           6168                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         6168                       # number of overall misses
+system.cpu.icache.overall_misses::total          6168                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    170610000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    170610000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    170610000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    170610000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    170610000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    170610000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    928789151                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    928789151                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    928789151                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    928789151                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    928789151                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    928789151                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000007                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000007                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000007                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000007                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000007                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000007                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27660.505837                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 27660.505837                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 27660.505837                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 27660.505837                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 27660.505837                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 27660.505837                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -205,123 +205,123 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst        10596                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total        10596                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst        10596                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total        10596                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst        10596                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total        10596                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    206982000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    206982000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    206982000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    206982000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    206982000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    206982000                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000005                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000005                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000005                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.000005                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000005                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.000005                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19533.975085                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19533.975085                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19533.975085                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 19533.975085                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19533.975085                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 19533.975085                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst         6168                       # number of ReadReq MSHR misses
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+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    158274000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    158274000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    158274000                       # number of demand (read+write) MSHR miss cycles
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+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    158274000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    158274000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000007                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000007                       # mshr miss rate for ReadReq accesses
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+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000007                       # mshr miss rate for overall accesses
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+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 25660.505837                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 25660.505837                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 25660.505837                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 25660.505837                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 25660.505837                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 25660.505837                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements           442570                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        32706.854192                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            1089464                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           475302                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             2.292151                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements           257900                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        32657.894031                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs             518578                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           290634                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             1.784299                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks  1300.510334                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst    26.518402                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 31379.825456                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.039688                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.000809                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.957636                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.998134                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        32732                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          100                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_blocks::writebacks  2768.249737                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst    50.156527                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 29839.487767                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.084480                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.001531                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.910629                       # Average percentage of cache occupancy
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+system.cpu.l2cache.tags.occ_task_id_blocks::1024        32734                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          101                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::1          174                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          116                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         1143                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        31199                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.998901                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         13642206                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        13642206                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst         8443                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data      1051869                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        1060312                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks        96129                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total        96129                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data         5079                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total         5079                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst         8443                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      1056948                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         1065391                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst         8443                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      1056948                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        1065391                       # number of overall hits
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          117                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         1144                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        31198                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.998962                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses          7386496                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses         7386496                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.inst         4015                       # number of ReadReq hits
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+system.cpu.l2cache.Writeback_hits::writebacks        91660                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total        91660                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data         2366                       # number of ReadExReq hits
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 system.cpu.l2cache.ReadReq_misses::cpu.inst         2153                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data       406323                       # number of ReadReq misses
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-system.cpu.l2cache.ReadExReq_misses::cpu.data        66873                       # number of ReadExReq misses
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 system.cpu.l2cache.demand_misses::cpu.inst         2153                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       473196                       # number of demand (read+write) misses
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 system.cpu.l2cache.overall_misses::cpu.inst         2153                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       473196                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       475349                       # number of overall misses
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 system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    111956000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data  21128799000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total  21240755000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   3477396000                       # number of ReadExReq miss cycles
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 system.cpu.l2cache.demand_miss_latency::cpu.inst    111956000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  24606195000                       # number of demand (read+write) miss cycles
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 system.cpu.l2cache.overall_miss_latency::cpu.inst    111956000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  24606195000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  24718151000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst        10596                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data      1458192                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total      1468788                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks        96129                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total        96129                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data        71952                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total        71952                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst        10596                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      1530144                       # number of demand (read+write) accesses
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-system.cpu.l2cache.overall_accesses::cpu.data      1530144                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      1540740                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.203190                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.278648                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.278104                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.929411                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.929411                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.203190                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.309249                       # miss rate for demand accesses
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-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.203190                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.309249                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.308520                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_latency::cpu.data  15003355000                       # number of overall miss cycles
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+system.cpu.l2cache.ReadExReq_accesses::cpu.data        69014                       # number of ReadExReq accesses(hits+misses)
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+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.349060                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.311839                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.312159                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.965717                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.965717                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.349060                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.369655                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.369493                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.349060                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.369655                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.369493                       # miss rate for overall accesses
 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst        52000                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000.007383                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000.007344                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000.013521                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000.013391                       # average ReadReq miss latency
 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        52000                       # average ReadExReq miss latency
 system.cpu.l2cache.ReadExReq_avg_miss_latency::total        52000                       # average ReadExReq miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.006340                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 52000.006311                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.010398                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 52000.010321                       # average overall miss latency
 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.006340                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 52000.006311                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.010398                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 52000.010321                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -330,119 +330,119 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        66908                       # number of writebacks
-system.cpu.l2cache.writebacks::total            66908                       # number of writebacks
+system.cpu.l2cache.writebacks::writebacks        66683                       # number of writebacks
+system.cpu.l2cache.writebacks::total            66683                       # number of writebacks
 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         2153                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data       406323                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total       408476                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        66873                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total        66873                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data       221878                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total       224031                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        66648                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total        66648                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.inst         2153                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       473196                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       475349                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       288526                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       290679                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.inst         2153                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       473196                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       475349                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       288526                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       290679                       # number of overall MSHR misses
 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     86120000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  16252923000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total  16339043000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   2674920000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   2674920000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   8875123000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total   8961243000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   2665920000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   2665920000                       # number of ReadExReq MSHR miss cycles
 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     86120000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  18927843000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  19013963000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  11541043000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  11627163000                       # number of demand (read+write) MSHR miss cycles
 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     86120000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  18927843000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  19013963000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.203190                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.278648                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.278104                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.929411                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.929411                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.203190                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.309249                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.308520                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.203190                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.309249                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.308520                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  11541043000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  11627163000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.349060                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.311839                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.312159                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.965717                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.965717                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.349060                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.369655                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.369493                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.349060                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.369655                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.369493                       # mshr miss rate for overall accesses
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst        40000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000.007383                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000.007344                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000.013521                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000.013391                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadExReq mshr miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total        40000                       # average ReadExReq mshr miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000.006340                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000.006311                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000.010398                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000.010321                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.006340                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.006311                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.010398                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.010321                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements           1526048                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4095.197836                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           720334778                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           1530144                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            470.762737                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle        1041395000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4095.197836                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999804                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999804                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements            776432                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4094.261324                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           335031269                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            780528                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs            429.236708                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle        1046536000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4094.261324                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.999576                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999576                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           55                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          160                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2          466                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3          999                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::4         2416                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          153                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          468                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3          993                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4         2427                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses        1445259988                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses       1445259988                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    509611834                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       509611834                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    210722944                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      210722944                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data     720334778                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        720334778                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    720334778                       # number of overall hits
-system.cpu.dcache.overall_hits::total       720334778                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      1458192                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       1458192                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data        71952                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total        71952                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data      1530144                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        1530144                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      1530144                       # number of overall misses
-system.cpu.dcache.overall_misses::total       1530144                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  36022065000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  36022065000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   3744042000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   3744042000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  39766107000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  39766107000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  39766107000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  39766107000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    511070026                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    511070026                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data    210794896                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total    210794896                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    721864922                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    721864922                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    721864922                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    721864922                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.002853                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.002853                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000341                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.000341                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.002120                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.002120                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.002120                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.002120                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24703.238668                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 24703.238668                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52035.273516                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 52035.273516                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 25988.473634                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 25988.473634                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 25988.473634                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 25988.473634                       # average overall miss latency
+system.cpu.dcache.tags.tag_accesses         672404122                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        672404122                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    236799083                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       236799083                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     98232186                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       98232186                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data     335031269                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        335031269                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    335031269                       # number of overall hits
+system.cpu.dcache.overall_hits::total       335031269                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       711514                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        711514                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data        69014                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total        69014                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data       780528                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total         780528                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data       780528                       # number of overall misses
+system.cpu.dcache.overall_misses::total        780528                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  18568561000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  18568561000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   3696398000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   3696398000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  22264959000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  22264959000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  22264959000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  22264959000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    237510597                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    237510597                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data     98301200                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total     98301200                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data    335811797                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    335811797                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    335811797                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    335811797                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.002996                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.002996                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000702                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.000702                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.002324                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.002324                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.002324                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.002324                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26097.253181                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 26097.253181                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53560.118237                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 53560.118237                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 28525.509655                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 28525.509655                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 28525.509655                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 28525.509655                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -451,60 +451,60 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks        96129                       # number of writebacks
-system.cpu.dcache.writebacks::total             96129                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1458192                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      1458192                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data        71952                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total        71952                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      1530144                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      1530144                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      1530144                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      1530144                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  33105681000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  33105681000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   3600138000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   3600138000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  36705819000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  36705819000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  36705819000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  36705819000                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.002853                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.002853                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000341                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000341                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.002120                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.002120                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.002120                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.002120                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22703.238668                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22703.238668                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 50035.273516                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 50035.273516                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23988.473634                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 23988.473634                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23988.473634                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 23988.473634                       # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks        91660                       # number of writebacks
+system.cpu.dcache.writebacks::total             91660                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       711514                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       711514                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data        69014                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total        69014                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       780528                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       780528                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       780528                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       780528                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  17145533000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  17145533000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   3558370000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   3558370000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  20703903000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  20703903000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  20703903000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  20703903000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.002996                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.002996                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000702                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000702                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.002324                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.002324                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.002324                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.002324                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24097.253181                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24097.253181                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51560.118237                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51560.118237                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26525.509655                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 26525.509655                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26525.509655                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 26525.509655                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.throughput                37822912                       # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq        1468788                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       1468788                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback        96129                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq        71952                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp        71952                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        21192                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      3156417                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           3177609                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       678144                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    104081472                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total      104759616                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus         104759616                       # Total data (bytes)
+system.cpu.toL2Bus.throughput                43704406                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq         717682                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp        717682                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback        91660                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq        69014                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp        69014                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        12336                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      1652716                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           1665052                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       394752                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     55820032                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total       56214784                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus          56214784                       # Total data (bytes)
 system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy      914563500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.occupancy      530838000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy      15894000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy       9252000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    2295216000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    1170792000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt
index 3a1bb990b..dc7a25182 100644
--- a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt
@@ -1,597 +1,101 @@
 
 ---------- Begin Simulation Statistics ----------
-final_tick                               1252658454500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-host_inst_rate                                 126529                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 303852                       # Number of bytes of host memory used
-host_op_rate                                   172315                       # Simulator op (including micro ops) rate (op/s)
-host_seconds                                 10941.24                       # Real time elapsed on the host
-host_tick_rate                              114489637                       # Simulator tick rate (ticks/s)
+sim_seconds                                  0.537826                       # Number of seconds simulated
+sim_ticks                                537826498500                       # Number of ticks simulated
+final_tick                               537826498500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-sim_insts                                  1384383018                       # Number of instructions simulated
-sim_ops                                    1885337770                       # Number of ops (including micro ops) simulated
-sim_seconds                                  1.252658                       # Number of seconds simulated
-sim_ticks                                1252658454500                       # Number of ticks simulated
+host_inst_rate                                 114564                       # Simulator instruction rate (inst/s)
+host_op_rate                                   141043                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               96175687                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 263048                       # Number of bytes of host memory used
+host_seconds                                  5592.13                       # Real time elapsed on the host
+sim_insts                                   640655084                       # Number of instructions simulated
+sim_ops                                     788730743                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             92.275361                       # BTB Hit Percentage
-system.cpu.branchPred.BTBHits               183176705                       # Number of BTB hits
-system.cpu.branchPred.BTBLookups            198510960                       # Number of BTB lookups
-system.cpu.branchPred.RASInCorrect               2809                       # Number of incorrect RAS predictions.
-system.cpu.branchPred.condIncorrect          27775706                       # Number of conditional branches incorrect
-system.cpu.branchPred.condPredicted         271023918                       # Number of conditional branches predicted
-system.cpu.branchPred.lookups               347774230                       # Number of BP lookups
-system.cpu.branchPred.usedRAS                40383236                       # Number of times the RAS was used to get a target.
-system.cpu.committedInsts                  1384383018                       # Number of instructions committed
-system.cpu.committedOps                    1885337770                       # Number of ops (including micro ops) committed
-system.cpu.cpi                               1.809699                       # CPI: cycles per instruction
-system.cpu.dcache.LoadLockedReq_accesses::cpu.inst         9985                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total         9985                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_hits::cpu.inst         9985                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total         9985                       # number of LoadLockedReq hits
-system.cpu.dcache.ReadReq_accesses::cpu.inst    622157845                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    622157845                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 30504.122168                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 30504.122168                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 28441.732178                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 28441.732178                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits::cpu.inst    620694666                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       620694666                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency::cpu.inst  44632990969                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  44632990969                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate::cpu.inst     0.002352                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.002352                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses::cpu.inst      1463179                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       1463179                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits::cpu.inst         1721                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total         1721                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst  41566397026                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  41566397026                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst     0.002349                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.002349                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses::cpu.inst      1461458                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      1461458                       # number of ReadReq MSHR misses
-system.cpu.dcache.StoreCondReq_accesses::cpu.inst         9985                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total         9985                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_hits::cpu.inst         9985                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total         9985                       # number of StoreCondReq hits
-system.cpu.dcache.WriteReq_accesses::cpu.inst    276935678                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total    276935678                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 64418.412606                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 64418.412606                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 62661.295309                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62661.295309                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits::cpu.inst    276792059                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      276792059                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency::cpu.inst   9251708000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   9251708000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate::cpu.inst     0.000519                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.000519                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses::cpu.inst       143619                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       143619                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits::cpu.inst        70841                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total        70841                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst   4560363750                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   4560363750                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst     0.000263                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000263                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.inst        72778                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total        72778                       # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.demand_accesses::cpu.inst    899093523                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    899093523                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency::cpu.inst 33535.453099                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 33535.453099                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 30064.970954                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 30064.970954                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits::cpu.inst     897486725                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        897486725                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency::cpu.inst  53884698969                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  53884698969                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate::cpu.inst     0.001787                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.001787                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses::cpu.inst      1606798                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        1606798                       # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits::cpu.inst        72562                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total        72562                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency::cpu.inst  46126760776                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  46126760776                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate::cpu.inst     0.001706                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.001706                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses::cpu.inst      1534236                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      1534236                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses::cpu.inst    899093523                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    899093523                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency::cpu.inst 33535.453099                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 33535.453099                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 30064.970954                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 30064.970954                       # average overall mshr miss latency
-system.cpu.dcache.overall_hits::cpu.inst    897486725                       # number of overall hits
-system.cpu.dcache.overall_hits::total       897486725                       # number of overall hits
-system.cpu.dcache.overall_miss_latency::cpu.inst  53884698969                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  53884698969                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate::cpu.inst     0.001787                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.001787                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses::cpu.inst      1606798                       # number of overall misses
-system.cpu.dcache.overall_misses::total       1606798                       # number of overall misses
-system.cpu.dcache.overall_mshr_hits::cpu.inst        72562                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total        72562                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency::cpu.inst  46126760776                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  46126760776                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate::cpu.inst     0.001706                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.001706                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses::cpu.inst      1534236                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      1534236                       # number of overall MSHR misses
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           33                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          160                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2          964                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3         1240                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::4         1699                       # Occupied blocks per task id
-system.cpu.dcache.tags.avg_refs            584.986075                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.data_accesses       1799761222                       # Number of data accesses
-system.cpu.dcache.tags.occ_blocks::cpu.inst  4094.531713                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.inst     0.999642                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999642                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.replacements           1530140                       # number of replacements
-system.cpu.dcache.tags.sampled_refs           1534236                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.tag_accesses        1799761222                       # Number of tag accesses
-system.cpu.dcache.tags.tagsinuse          4094.531713                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           897506695                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         756574250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks::writebacks        96100                       # number of writebacks
-system.cpu.dcache.writebacks::total             96100                       # number of writebacks
-system.cpu.discardedOps                      58655042                       # Number of ops (including micro ops) which were discarded before commit
-system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
-system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
-system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
-system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
-system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
-system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
-system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
-system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
-system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
-system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
-system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
-system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
-system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
-system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
-system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
-system.cpu.dtb.accesses                             0                       # DTB accesses
-system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.hits                                 0                       # DTB hits
-system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.inst_hits                            0                       # ITB inst hits
-system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.misses                               0                       # DTB misses
-system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
-system.cpu.dtb.read_accesses                        0                       # DTB read accesses
-system.cpu.dtb.read_hits                            0                       # DTB read hits
-system.cpu.dtb.read_misses                          0                       # DTB read misses
-system.cpu.dtb.write_accesses                       0                       # DTB write accesses
-system.cpu.dtb.write_hits                           0                       # DTB write hits
-system.cpu.dtb.write_misses                         0                       # DTB write misses
-system.cpu.icache.ReadReq_accesses::cpu.inst    655834828                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    655834828                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15794.863845                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 15794.863845                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13774.677486                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13774.677486                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits::cpu.inst    655779494                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       655779494                       # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    873992996                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    873992996                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000084                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000084                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses::cpu.inst        55334                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total         55334                       # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    762208004                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    762208004                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000084                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000084                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst        55334                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total        55334                       # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.demand_accesses::cpu.inst    655834828                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    655834828                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 15794.863845                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 15794.863845                       # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13774.677486                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 13774.677486                       # average overall mshr miss latency
-system.cpu.icache.demand_hits::cpu.inst     655779494                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        655779494                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency::cpu.inst    873992996                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    873992996                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000084                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000084                       # miss rate for demand accesses
-system.cpu.icache.demand_misses::cpu.inst        55334                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total          55334                       # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    762208004                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    762208004                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000084                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.000084                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses::cpu.inst        55334                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total        55334                       # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses::cpu.inst    655834828                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    655834828                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 15794.863845                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 15794.863845                       # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13774.677486                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 13774.677486                       # average overall mshr miss latency
-system.cpu.icache.overall_hits::cpu.inst    655779494                       # number of overall hits
-system.cpu.icache.overall_hits::total       655779494                       # number of overall hits
-system.cpu.icache.overall_miss_latency::cpu.inst    873992996                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    873992996                       # number of overall miss cycles
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000084                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000084                       # miss rate for overall accesses
-system.cpu.icache.overall_misses::cpu.inst        55334                       # number of overall misses
-system.cpu.icache.overall_misses::total         55334                       # number of overall misses
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    762208004                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    762208004                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000084                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.000084                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses::cpu.inst        55334                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total        55334                       # number of overall MSHR misses
-system.cpu.icache.tags.age_task_id_blocks_1024::0           54                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1           95                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4         1615                       # Occupied blocks per task id
-system.cpu.icache.tags.avg_refs          11851.508033                       # Average number of references to valid blocks.
-system.cpu.icache.tags.data_accesses       1311724989                       # Number of data accesses
-system.cpu.icache.tags.occ_blocks::cpu.inst  1727.262157                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.843390                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.843390                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024         1765                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.861816                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.replacements             53568                       # number of replacements
-system.cpu.icache.tags.sampled_refs             55333                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.tag_accesses        1311724989                       # Number of tag accesses
-system.cpu.icache.tags.tagsinuse          1727.262157                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           655779494                       # Total number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.idleCycles                       103571975                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.ipc                               0.552578                       # IPC: instructions per cycle
-system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
-system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
-system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
-system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
-system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
-system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
-system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
-system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
-system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
-system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
-system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
-system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
-system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
-system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
-system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
-system.cpu.itb.accesses                             0                       # DTB accesses
-system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
-system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.hits                                 0                       # DTB hits
-system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.itb.inst_hits                            0                       # ITB inst hits
-system.cpu.itb.inst_misses                          0                       # ITB inst misses
-system.cpu.itb.misses                               0                       # DTB misses
-system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
-system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
-system.cpu.itb.read_accesses                        0                       # DTB read accesses
-system.cpu.itb.read_hits                            0                       # DTB read hits
-system.cpu.itb.read_misses                          0                       # DTB read misses
-system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.write_hits                           0                       # DTB write hits
-system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.l2cache.ReadExReq_accesses::cpu.inst        72778                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total        72778                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 66889.147375                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66889.147375                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 54354.270691                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54354.270691                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_hits::cpu.inst         6688                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total         6688                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst   4420703750                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   4420703750                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst     0.908104                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.908104                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses::cpu.inst        66090                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total        66090                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst   3592273750                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   3592273750                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst     0.908104                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.908104                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst        66090                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total        66090                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses::cpu.inst      1516792                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total      1516792                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72703.861690                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 72703.861690                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60134.219047                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60134.219047                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits::cpu.inst      1107826                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        1107826                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst  29733407500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total  29733407500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.269626                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.269626                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses::cpu.inst       408966                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total       408966                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst           30                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total           30                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst  24591047000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total  24591047000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.269606                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.269606                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst       408936                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total       408936                       # number of ReadReq MSHR misses
-system.cpu.l2cache.Writeback_accesses::writebacks        96100                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total        96100                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits::writebacks        96100                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total        96100                       # number of Writeback hits
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.demand_accesses::cpu.inst      1589570                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      1589570                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71894.916073                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 71894.916073                       # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59330.059302                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59330.059302                       # average overall mshr miss latency
-system.cpu.l2cache.demand_hits::cpu.inst      1114514                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         1114514                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency::cpu.inst  34154111250                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  34154111250                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.298858                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.298858                       # miss rate for demand accesses
-system.cpu.l2cache.demand_misses::cpu.inst       475056                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        475056                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_mshr_hits::cpu.inst           30                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total           30                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst  28183320750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  28183320750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.298839                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.298839                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst       475026                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       475026                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses::cpu.inst      1589570                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      1589570                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71894.916073                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 71894.916073                       # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59330.059302                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59330.059302                       # average overall mshr miss latency
-system.cpu.l2cache.overall_hits::cpu.inst      1114514                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        1114514                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency::cpu.inst  34154111250                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  34154111250                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.298858                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.298858                       # miss rate for overall accesses
-system.cpu.l2cache.overall_misses::cpu.inst       475056                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       475056                       # number of overall misses
-system.cpu.l2cache.overall_mshr_hits::cpu.inst           30                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total           30                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst  28183320750                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  28183320750                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.298839                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.298839                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst       475026                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       475026                       # number of overall MSHR misses
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           81                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          145                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          268                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         2580                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        29670                       # Occupied blocks per task id
-system.cpu.l2cache.tags.avg_refs             2.395162                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.data_accesses        14033128                       # Number of data accesses
-system.cpu.l2cache.tags.occ_blocks::writebacks  1330.818076                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 31344.832788                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.040613                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.956568                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.997182                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        32744                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.999268                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.replacements           442246                       # number of replacements
-system.cpu.l2cache.tags.sampled_refs           474990                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.tag_accesses         14033128                       # Number of tag accesses
-system.cpu.l2cache.tags.tagsinuse        32675.650864                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            1137678                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks::writebacks        66099                       # number of writebacks
-system.cpu.l2cache.writebacks::total            66099                       # number of writebacks
-system.cpu.numCycles                       2505316909                       # number of cpu cycles simulated
-system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.tickCycles                      2401744934                       # Number of cycles that the CPU actually ticked
-system.cpu.toL2Bus.data_through_bus         107882816                       # Total data (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       110667                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      3164572                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           3275239                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy      938935000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy      83558996                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    2375968224                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          0.2                       # Layer utilization (%)
-system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
-system.cpu.toL2Bus.throughput                86123089                       # Throughput (bytes/s)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      3541312                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    104341504                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total      107882816                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.trans_dist::ReadReq        1516792                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       1516791                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback        96100                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq        72778                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp        72778                       # Transaction distribution
-system.cpu.workload.num_syscalls                 1411                       # Number of system calls
-system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.membus.data_through_bus               34631936                       # Total data (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1016149                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1016149                       # Packet count per connected master and slave (bytes)
-system.membus.reqLayer0.occupancy          1205459500                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               0.1                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         4468586250                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              0.4                       # Layer utilization (%)
-system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.throughput                     27646751                       # Throughput (bytes/s)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     34631936                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total            34631936                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.trans_dist::ReadReq              408935                       # Transaction distribution
-system.membus.trans_dist::ReadResp             408935                       # Transaction distribution
-system.membus.trans_dist::Writeback             66099                       # Transaction distribution
-system.membus.trans_dist::ReadExReq             66090                       # Transaction distribution
-system.membus.trans_dist::ReadExResp            66090                       # Transaction distribution
-system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgGap                      2314919.25                       # Average gap between requests
-system.physmem.avgMemAccLat                  29362.18                       # Average memory access latency per DRAM burst
-system.physmem.avgQLat                       10612.18                       # Average queueing delay per DRAM burst
-system.physmem.avgRdBW                          24.25                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       24.27                       # Average system read bandwidth in MiByte/s
-system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrBW                           3.38                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        3.38                       # Average system write bandwidth in MiByte/s
-system.physmem.avgWrQLen                        26.46                       # Average write queue length when enqueuing
-system.physmem.busUtil                           0.22                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       0.19                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
-system.physmem.bw_inst_read::cpu.inst          133348                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             133348                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst             24269664                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                24269664                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           3377087                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst            24269664                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               27646751                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_write::writebacks           3377087                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                3377087                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bytesPerActivate::samples       204371                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      169.307779                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     122.893449                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     197.869772                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          84097     41.15%     41.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        91184     44.62%     85.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        16888      8.26%     94.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511          803      0.39%     94.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         1089      0.53%     94.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1331      0.65%     95.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895          576      0.28%     95.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          520      0.25%     96.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         7883      3.86%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         204371                       # Bytes accessed per row activation
-system.physmem.bytesReadDRAM                 30374976                       # Total number of bytes read from DRAM
-system.physmem.bytesReadSys                  30401600                       # Total read bytes from the system interface side
-system.physmem.bytesReadWrQ                     26624                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   4228608                       # Total number of bytes written to DRAM
-system.physmem.bytesWrittenSys                4230336                       # Total written bytes from the system interface side
-system.physmem.bytes_inst_read::cpu.inst       167040                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          167040                       # Number of instructions bytes read from this memory
-system.physmem.bytes_read::cpu.inst          30401600                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             30401600                       # Number of bytes read from this memory
-system.physmem.bytes_written::writebacks      4230336                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           4230336                       # Number of bytes written to this memory
-system.physmem.memoryStateTime::IDLE     639262116250                       # Time in different power states
-system.physmem.memoryStateTime::REF       41828800000                       # Time in different power states
-system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT      571561257500                       # Time in different power states
-system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
+system.physmem.bytes_read::cpu.inst          18593984                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             18593984                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       165056                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          165056                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      4230272                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           4230272                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst             290531                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                290531                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           66098                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                66098                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst             34572458                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                34572458                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          306895                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             306895                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           7865496                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                7865496                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           7865496                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst            34572458                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               42437954                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        290531                       # Number of read requests accepted
+system.physmem.writeReqs                        66098                       # Number of write requests accepted
+system.physmem.readBursts                      290531                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                      66098                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 18574336                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     19648                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   4229312                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  18593984                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                4230272                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      307                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.num_reads::cpu.inst             475025                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                475025                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           66099                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total                66099                       # Number of write requests responded to by this memory
-system.physmem.pageHitRate                      62.20                       # Row buffer hit rate, read and write combined
-system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.perBankRdBursts::0               29837                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               29647                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               29757                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               29702                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               29776                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               29847                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               29613                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               29430                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               29457                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               29488                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              29541                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              29643                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              29678                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              29796                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              29601                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              29796                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                4173                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                4100                       # Per bank write bursts
+system.physmem.perBankRdBursts::0               18283                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               18133                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               18223                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               18187                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               18258                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               18313                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               18090                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               17910                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               17943                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               17966                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              18023                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              18118                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              18159                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              18277                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              18081                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              18260                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                4174                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                4102                       # Per bank write bursts
 system.physmem.perBankWrBursts::2                4137                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                4146                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                4224                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                4147                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                4225                       # Per bank write bursts
 system.physmem.perBankWrBursts::5                4225                       # Per bank write bursts
 system.physmem.perBankWrBursts::6                4171                       # Per bank write bursts
 system.physmem.perBankWrBursts::7                4094                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                4094                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                4096                       # Per bank write bursts
 system.physmem.perBankWrBursts::9                4093                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               4093                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               4094                       # Per bank write bursts
 system.physmem.perBankWrBursts::11               4097                       # Per bank write bursts
 system.physmem.perBankWrBursts::12               4098                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               4095                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               4094                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               4096                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               4096                       # Per bank write bursts
 system.physmem.perBankWrBursts::15               4138                       # Per bank write bursts
-system.physmem.rdPerTurnAround::samples          4007                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        48.550786                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::gmean       36.067006                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      508.980201                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023           4004     99.93%     99.93% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-2047            1      0.02%     99.95% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2048-3071            1      0.02%     99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::31744-32767            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            4007                       # Reads before turning the bus around for writes
-system.physmem.rdQLenPdf::0                    474221                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       373                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        15                       # What read queue length does an incoming req see
+system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
+system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
+system.physmem.totGap                    537826410500                       # Total gap between requests
+system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
+system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
+system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
+system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
+system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
+system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  290531                       # Read request sizes (log2)
+system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
+system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
+system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
+system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
+system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
+system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
+system.physmem.writePktSize::6                  66098                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    289825                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       382                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        17                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
@@ -621,30 +125,6 @@ system.physmem.rdQLenPdf::28                        0                       # Wh
 system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.readBursts                      475025                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  475025                       # Read request sizes (log2)
-system.physmem.readReqs                        475025                       # Number of read requests accepted
-system.physmem.readRowHitRate                   60.31                       # Row buffer hit rate for reads
-system.physmem.readRowHits                     286253                       # Number of row buffer hits during reads
-system.physmem.servicedByWrQ                      416                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.totBusLat                   2373045000                       # Total ticks spent in databus transfers
-system.physmem.totGap                    1252658366500                       # Total gap between requests
-system.physmem.totMemAccLat               13935557250                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totQLat                     5036638500                       # Total ticks spent queuing
-system.physmem.wrPerTurnAround::samples          4007                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        16.489144                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.467620                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        0.859483                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16               3026     75.52%     75.52% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17                  2      0.05%     75.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18                979     24.43%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            4007                       # Writes before turning the bus around for reads
 system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
@@ -660,8 +140,8 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                      980                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                      982                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                      975                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                      978                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::17                     4008                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::18                     4008                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::19                     4008                       # What write queue length does an incoming req see
@@ -672,12 +152,12 @@ system.physmem.wrQLenPdf::23                     4008                       # Wh
 system.physmem.wrQLenPdf::24                     4008                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::25                     4008                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::26                     4008                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     4007                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     4007                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     4007                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     4007                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     4007                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     4007                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     4010                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     4008                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     4008                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     4008                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     4008                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     4008                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
@@ -709,17 +189,537 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.writeBursts                      66099                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                  66099                       # Write request sizes (log2)
-system.physmem.writeReqs                        66099                       # Number of write requests accepted
-system.physmem.writeRowHitRate                  75.71                       # Row buffer hit rate for writes
-system.physmem.writeRowHits                     50044                       # Number of row buffer hits during writes
-system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.physmem.bytesPerActivate::samples       111452                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      204.586154                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     132.570788                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     256.465119                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          47032     42.20%     42.20% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        43501     39.03%     81.23% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         8758      7.86%     89.09% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511          741      0.66%     89.75% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         1179      1.06%     90.81% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1268      1.14%     91.95% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          550      0.49%     92.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          543      0.49%     92.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         7880      7.07%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         111452                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          4008                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        48.655439                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::gmean       36.051521                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      507.704420                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023           4005     99.93%     99.93% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-2047            1      0.02%     99.95% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2048-3071            1      0.02%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::31744-32767            1      0.02%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total            4008                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          4008                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.487774                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.466259                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        0.859394                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               3030     75.60%     75.60% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17                  3      0.07%     75.67% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18                973     24.28%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19                  2      0.05%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            4008                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     3341298000                       # Total ticks spent queuing
+system.physmem.totMemAccLat                8782998000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   1451120000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       11512.82                       # Average queueing delay per DRAM burst
+system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
+system.physmem.avgMemAccLat                  30262.82                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          34.54                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           7.86                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       34.57                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        7.87                       # Average system write bandwidth in MiByte/s
+system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
+system.physmem.busUtil                           0.33                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       0.27                       # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite                      0.06                       # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        29.26                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     194846                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     49995                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   67.14                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  75.64                       # Row buffer hit rate for writes
+system.physmem.avgGap                      1508083.78                       # Average gap between requests
+system.physmem.pageHitRate                      68.71                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE     253517983250                       # Time in different power states
+system.physmem.memoryStateTime::REF       17958980000                       # Time in different power states
+system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
+system.physmem.memoryStateTime::ACT      266342956750                       # Time in different power states
+system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
+system.membus.throughput                     42437954                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq              224439                       # Transaction distribution
+system.membus.trans_dist::ReadResp             224439                       # Transaction distribution
+system.membus.trans_dist::Writeback             66098                       # Transaction distribution
+system.membus.trans_dist::ReadExReq             66092                       # Transaction distribution
+system.membus.trans_dist::ReadExResp            66092                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       647160                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 647160                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     22824256                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total            22824256                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus               22824256                       # Total data (bytes)
+system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy           974430000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               0.2                       # Layer utilization (%)
+system.membus.respLayer1.occupancy         2738631750                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization              0.5                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.cpu.branchPred.lookups               154837020                       # Number of BP lookups
+system.cpu.branchPred.condPredicted         104970668                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect          12892448                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups            106220966                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                82647169                       # Number of BTB hits
+system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.branchPred.BTBHitPct             77.806832                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                19441660                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect               1323                       # Number of incorrect RAS predictions.
+system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
+system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
+system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
+system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
+system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
+system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
+system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
+system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
+system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
+system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
+system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
+system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
+system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
+system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
+system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
+system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
+system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.dtb.inst_hits                            0                       # ITB inst hits
+system.cpu.dtb.inst_misses                          0                       # ITB inst misses
+system.cpu.dtb.read_hits                            0                       # DTB read hits
+system.cpu.dtb.read_misses                          0                       # DTB read misses
+system.cpu.dtb.write_hits                           0                       # DTB write hits
+system.cpu.dtb.write_misses                         0                       # DTB write misses
+system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                        0                       # DTB read accesses
+system.cpu.dtb.write_accesses                       0                       # DTB write accesses
+system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.dtb.hits                                 0                       # DTB hits
+system.cpu.dtb.misses                               0                       # DTB misses
+system.cpu.dtb.accesses                             0                       # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
+system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
+system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
+system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
+system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
+system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
+system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
+system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
+system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
+system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
+system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
+system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
+system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
+system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
+system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
+system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
+system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.itb.inst_hits                            0                       # ITB inst hits
+system.cpu.itb.inst_misses                          0                       # ITB inst misses
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
+system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.itb.hits                                 0                       # DTB hits
+system.cpu.itb.misses                               0                       # DTB misses
+system.cpu.itb.accesses                             0                       # DTB accesses
+system.cpu.workload.num_syscalls                  673                       # Number of system calls
+system.cpu.numCycles                       1075652997                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.committedInsts                   640655084                       # Number of instructions committed
+system.cpu.committedOps                     788730743                       # Number of ops (including micro ops) committed
+system.cpu.discardedOps                      25219021                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
+system.cpu.cpi                               1.678989                       # CPI: cycles per instruction
+system.cpu.ipc                               0.595596                       # IPC: instructions per cycle
+system.cpu.tickCycles                      1020176275                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                        55476722                       # Total number of cycles that the object has spent stopped
+system.cpu.icache.tags.replacements             23597                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1711.182078                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           289999264                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs             25347                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          11441.167160                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst  1711.182078                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.835538                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.835538                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1750                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           58                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           94                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1598                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.854492                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses         580074571                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        580074571                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    289999264                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       289999264                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     289999264                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        289999264                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    289999264                       # number of overall hits
+system.cpu.icache.overall_hits::total       289999264                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst        25348                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total         25348                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst        25348                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total          25348                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst        25348                       # number of overall misses
+system.cpu.icache.overall_misses::total         25348                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    480804246                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    480804246                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    480804246                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    480804246                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    480804246                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    480804246                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    290024612                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    290024612                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    290024612                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    290024612                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    290024612                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    290024612                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000087                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000087                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000087                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000087                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000087                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000087                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18968.133423                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 18968.133423                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 18968.133423                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 18968.133423                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 18968.133423                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 18968.133423                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst        25348                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total        25348                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst        25348                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total        25348                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst        25348                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total        25348                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    429006754                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    429006754                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    429006754                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    429006754                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    429006754                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    429006754                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000087                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000087                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000087                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.000087                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000087                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.000087                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16924.678633                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16924.678633                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16924.678633                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 16924.678633                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16924.678633                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 16924.678633                       # average overall mshr miss latency
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.toL2Bus.throughput               107000990                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq         738445                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp        738444                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback        91420                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq        69323                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp        69323                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        50695                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      1656260                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           1706955                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1622208                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     55925760                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total       57547968                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus          57547968                       # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy      541014000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy      38572246                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy    1224995475                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization          0.2                       # Layer utilization (%)
+system.cpu.l2cache.tags.replacements           257750                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        32582.970291                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs             539180                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           290494                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             1.856080                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks  2866.246405                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 29716.723886                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.087471                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.906882                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.994353                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        32744                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           82                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          150                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          292                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         2831                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        29389                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.999268                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses          7553321                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses         7553321                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.inst       513976                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total         513976                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks        91420                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total        91420                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.inst         3231                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total         3231                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst       517207                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total          517207                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst       517207                       # number of overall hits
+system.cpu.l2cache.overall_hits::total         517207                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst       224469                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total       224469                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.inst        66092                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total        66092                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst       290561                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        290561                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst       290561                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       290561                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst  16737523000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total  16737523000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst   4423362750                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   4423362750                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst  21160885750                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  21160885750                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst  21160885750                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  21160885750                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst       738445                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total       738445                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks        91420                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total        91420                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.inst        69323                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total        69323                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst       807768                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total       807768                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst       807768                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total       807768                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.303975                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.303975                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst     0.953392                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.953392                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.359708                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.359708                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.359708                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.359708                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74564.964427                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 74564.964427                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 66927.355051                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66927.355051                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72827.687646                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 72827.687646                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72827.687646                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 72827.687646                       # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
+system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
+system.cpu.l2cache.writebacks::writebacks        66098                       # number of writebacks
+system.cpu.l2cache.writebacks::total            66098                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst           29                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total           29                       # number of ReadReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst           29                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total           29                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst           29                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total           29                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst       224440                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total       224440                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst        66092                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total        66092                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst       290532                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       290532                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst       290532                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       290532                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst  13902147000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total  13902147000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst   3594959250                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   3594959250                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst  17497106250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  17497106250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst  17497106250                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  17497106250                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.303936                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.303936                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst     0.953392                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.953392                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.359673                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.359673                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.359673                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.359673                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61941.485475                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61941.485475                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 54393.258639                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54393.258639                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60224.368572                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60224.368572                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60224.368572                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60224.368572                       # average overall mshr miss latency
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu.dcache.tags.replacements            778324                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4092.650508                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           378453595                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            782420                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs            483.696218                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle         745524250                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.inst  4092.650508                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.inst     0.999182                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999182                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           30                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          172                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          963                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3         1354                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4         1577                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses         759392478                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        759392478                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.inst    249628224                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       249628224                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.inst    128813893                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      128813893                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.inst         5739                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total         5739                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.inst         5739                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total         5739                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.inst     378442117                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        378442117                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.inst    378442117                       # number of overall hits
+system.cpu.dcache.overall_hits::total       378442117                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.inst       713850                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        713850                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.inst       137584                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       137584                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.inst       851434                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total         851434                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.inst       851434                       # number of overall misses
+system.cpu.dcache.overall_misses::total        851434                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.inst  23698499970                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  23698499970                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.inst   9186329500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   9186329500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.inst  32884829470                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  32884829470                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.inst  32884829470                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  32884829470                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.inst    250342074                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    250342074                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.inst    128951477                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total    128951477                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.inst         5739                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total         5739                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.inst         5739                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total         5739                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.inst    379293551                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    379293551                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.inst    379293551                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    379293551                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.inst     0.002851                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.002851                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.inst     0.001067                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.001067                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.inst     0.002245                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.002245                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.inst     0.002245                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.002245                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 33198.150830                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 33198.150830                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 66768.879376                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 66768.879376                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.inst 38622.875608                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 38622.875608                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.inst 38622.875608                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 38622.875608                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks        91420                       # number of writebacks
+system.cpu.dcache.writebacks::total             91420                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.inst          753                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total          753                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.inst        68261                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total        68261                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.inst        69014                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total        69014                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.inst        69014                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total        69014                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.inst       713097                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       713097                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.inst        69323                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total        69323                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.inst       782420                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       782420                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.inst       782420                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       782420                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst  22186804275                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  22186804275                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst   4524997250                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   4524997250                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.inst  26711801525                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  26711801525                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.inst  26711801525                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  26711801525                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst     0.002848                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.002848                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst     0.000538                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000538                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.inst     0.002063                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.002063                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.inst     0.002063                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.002063                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 31113.304747                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31113.304747                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 65274.111767                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 65274.111767                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 34139.977921                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 34139.977921                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 34139.977921                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 34139.977921                       # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
index fbd52f02a..e42758d84 100644
--- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
@@ -1,95 +1,95 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.634728                       # Number of seconds simulated
-sim_ticks                                634728078000                       # Number of ticks simulated
-final_tick                               634728078000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.297198                       # Number of seconds simulated
+sim_ticks                                297198275500                       # Number of ticks simulated
+final_tick                               297198275500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  97161                       # Simulator instruction rate (inst/s)
-host_op_rate                                   132320                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               44547849                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 267228                       # Number of bytes of host memory used
-host_seconds                                 14248.23                       # Real time elapsed on the host
-sim_insts                                  1384370590                       # Number of instructions simulated
-sim_ops                                    1885325342                       # Number of ops (including micro ops) simulated
+host_inst_rate                                  98901                       # Simulator instruction rate (inst/s)
+host_op_rate                                   121761                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               45880544                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 261988                       # Number of bytes of host memory used
+host_seconds                                  6477.65                       # Real time elapsed on the host
+sim_insts                                   640649298                       # Number of instructions simulated
+sim_ops                                     788724957                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            156032                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          30243456                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             30399488                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       156032                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          156032                       # Number of instructions bytes read from this memory
+system.physmem.bytes_read::cpu.inst            150208                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          18436864                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             18587072                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       150208                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          150208                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written::writebacks      4230272                       # Number of bytes written to this memory
 system.physmem.bytes_written::total           4230272                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               2438                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             472554                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                474992                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst               2347                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             288076                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                290423                       # Number of read requests responded to by this memory
 system.physmem.num_writes::writebacks           66098                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total                66098                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               245825                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             47647894                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                47893719                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          245825                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             245825                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           6664700                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                6664700                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           6664700                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              245825                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            47647894                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               54558418                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        474992                       # Number of read requests accepted
+system.physmem.bw_read::cpu.inst               505413                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             62035569                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                62540982                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          505413                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             505413                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          14233838                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               14233838                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          14233838                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              505413                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            62035569                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               76774820                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        290424                       # Number of read requests accepted
 system.physmem.writeReqs                        66098                       # Number of write requests accepted
-system.physmem.readBursts                      474992                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                      290424                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                      66098                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 30375808                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     23680                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   4229120                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  30399488                       # Total read bytes from the system interface side
+system.physmem.bytesReadDRAM                 18565376                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     21760                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   4228224                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  18587136                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                4230272                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      370                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.servicedByWrQ                      340                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs           4530                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               29868                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               29664                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               29737                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               29712                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               29799                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               29810                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               29625                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               29426                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               29475                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               29463                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              29528                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              29636                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              29682                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              29788                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              29619                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              29790                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                4174                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                4102                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs           2334                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               18318                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               18131                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               18196                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               18163                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               18256                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               18279                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               18091                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               17906                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               17946                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               17953                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              18007                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              18104                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              18147                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              18252                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              18085                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              18250                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                4173                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                4100                       # Per bank write bursts
 system.physmem.perBankWrBursts::2                4137                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                4147                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                4225                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                4146                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                4224                       # Per bank write bursts
 system.physmem.perBankWrBursts::5                4224                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                4171                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                4170                       # Per bank write bursts
 system.physmem.perBankWrBursts::7                4094                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                4096                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                4090                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                4094                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                4091                       # Per bank write bursts
 system.physmem.perBankWrBursts::10               4093                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               4097                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               4098                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               4096                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               4095                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               4096                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               4094                       # Per bank write bursts
 system.physmem.perBankWrBursts::14               4096                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               4140                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               4139                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    634728009000                       # Total gap between requests
+system.physmem.totGap                    297198223500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  474992                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  290424                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -97,11 +97,11 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                  66098                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    407642                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     66616                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       276                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                        68                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                        17                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                    235690                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     49717                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                      4573                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                        81                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                        20                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         3                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
@@ -144,24 +144,24 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                      981                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                      983                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     3992                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     4008                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     4007                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     4009                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     4008                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     4007                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     4008                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     4014                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     4008                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     4008                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     4013                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     4007                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     4007                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     4008                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     4007                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     4008                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                      960                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                      960                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     2419                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     4037                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     4096                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     4031                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     4034                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     4057                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     4045                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     4603                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     4179                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     4050                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     4477                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     4017                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     4022                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     4018                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     4048                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     4030                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
@@ -193,93 +193,93 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       192766                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      179.514147                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     129.738688                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     208.062403                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          72454     37.59%     37.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        88147     45.73%     83.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        20712     10.74%     94.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511          450      0.23%     94.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639          454      0.24%     94.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767          512      0.27%     94.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895          512      0.27%     95.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          605      0.31%     95.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         8920      4.63%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         192766                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          4007                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        48.628151                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::gmean       36.096624                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      506.030557                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023           4004     99.93%     99.93% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples       106390                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      214.227653                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     137.234885                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     270.519636                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          42398     39.85%     39.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        42939     40.36%     80.21% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         9834      9.24%     89.45% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511          319      0.30%     89.75% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639          247      0.23%     89.99% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767          237      0.22%     90.21% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          324      0.30%     90.51% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1664      1.56%     92.08% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         8428      7.92%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         106390                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          4009                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        48.488651                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::gmean       36.041584                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      505.320352                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023           4006     99.93%     99.93% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::1024-2047            1      0.02%     99.95% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::2048-3071            1      0.02%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::31744-32767            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            4007                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          4007                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        16.491141                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.469437                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        0.863273                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16               3025     75.49%     75.49% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17                  2      0.05%     75.54% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18                974     24.31%     99.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19                  6      0.15%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            4007                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     4985394000                       # Total ticks spent queuing
-system.physmem.totMemAccLat               13884556500                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   2373110000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       10503.93                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            4009                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          4009                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.479421                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.458127                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        0.855088                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               3049     76.05%     76.05% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17                  1      0.02%     76.08% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18                956     23.85%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19                  3      0.07%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            4009                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     3531270750                       # Total ticks spent queuing
+system.physmem.totMemAccLat                8970345750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   1450420000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       12173.27                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  29253.93                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          47.86                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           6.66                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       47.89                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        6.66                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  30923.27                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          62.47                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                          14.23                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       62.54                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                       14.23                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           0.43                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       0.37                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.05                       # Data bus utilization in percentage for writes
+system.physmem.busUtil                           0.60                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       0.49                       # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite                      0.11                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.01                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        19.25                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     298015                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     49917                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   62.79                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  75.52                       # Row buffer hit rate for writes
-system.physmem.avgGap                      1173054.41                       # Average gap between requests
-system.physmem.pageHitRate                      64.35                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE     171675355500                       # Time in different power states
-system.physmem.memoryStateTime::REF       21194940000                       # Time in different power states
+system.physmem.avgWrQLen                        28.82                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     199840                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     49907                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   68.89                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  75.50                       # Row buffer hit rate for writes
+system.physmem.avgGap                       833604.16                       # Average gap between requests
+system.physmem.pageHitRate                      70.12                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE      84430805250                       # Time in different power states
+system.physmem.memoryStateTime::REF        9923940000                       # Time in different power states
 system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT      441857292000                       # Time in different power states
+system.physmem.memoryStateTime::ACT      202838904750                       # Time in different power states
 system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.membus.throughput                     54558418                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq              408916                       # Transaction distribution
-system.membus.trans_dist::ReadResp             408916                       # Transaction distribution
+system.membus.throughput                     76774820                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq              224345                       # Transaction distribution
+system.membus.trans_dist::ReadResp             224344                       # Transaction distribution
 system.membus.trans_dist::Writeback             66098                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             4530                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp            4530                       # Transaction distribution
-system.membus.trans_dist::ReadExReq             66076                       # Transaction distribution
-system.membus.trans_dist::ReadExResp            66076                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1025142                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1025142                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     34629760                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total            34629760                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus               34629760                       # Total data (bytes)
+system.membus.trans_dist::UpgradeReq             2334                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp            2334                       # Transaction distribution
+system.membus.trans_dist::ReadExReq             66079                       # Transaction distribution
+system.membus.trans_dist::ReadExResp            66079                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       651613                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 651613                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     22817344                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total            22817344                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus               22817344                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy          1216030000                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               0.2                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         4441818720                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              0.7                       # Layer utilization (%)
+system.membus.reqLayer0.occupancy          1003041500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               0.3                       # Layer utilization (%)
+system.membus.respLayer1.occupancy         2737822416                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization              0.9                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.branchPred.lookups               478607550                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         378292816                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect          30666231                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups            334166811                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits               254063804                       # Number of BTB hits
+system.cpu.branchPred.lookups               271863224                       # Number of BP lookups
+system.cpu.branchPred.condPredicted         178425431                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect          15415799                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups            186524109                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits               146250524                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             76.029036                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                60780885                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect            2806336                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             78.408376                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                34625446                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect            1929978                       # Number of incorrect RAS predictions.
 system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -364,519 +364,518 @@ system.cpu.itb.inst_accesses                        0                       # IT
 system.cpu.itb.hits                                 0                       # DTB hits
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
-system.cpu.workload.num_syscalls                 1411                       # Number of system calls
-system.cpu.numCycles                       1269456157                       # number of cpu cycles simulated
+system.cpu.workload.num_syscalls                  673                       # Number of system calls
+system.cpu.numCycles                        594396552                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles          382172768                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                     2398528075                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                   478607550                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches          314844689                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     646500630                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles               176126555                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles               55590458                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                  599                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles         12318                       # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles          120                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                 358033766                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes               6993732                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples         1229682095                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.711139                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.182068                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles          217387549                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                     1367579713                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   271863224                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches          180875970                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     338099313                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                30904558                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles               628206                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles       6076291                       # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles          107                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                 207850438                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               5507154                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          577643745                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.955013                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.177882                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                583226842     47.43%     47.43% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 47324489      3.85%     51.28% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                105202734      8.56%     59.83% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 59348034      4.83%     64.66% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                 82117278      6.68%     71.34% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                 49221552      4.00%     75.34% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                 36109976      2.94%     78.28% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                 30221135      2.46%     80.73% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                236910055     19.27%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                246926096     42.75%     42.75% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 22334065      3.87%     46.61% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 58641984     10.15%     56.77% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 13805206      2.39%     59.16% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                 49967679      8.65%     67.81% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                 26102781      4.52%     72.32% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                 32011884      5.54%     77.87% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                 19377139      3.35%     81.22% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                108476911     18.78%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total           1229682095                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.377018                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.889414                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                407354221                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              47938688                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 625726372                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               3270610                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles              145392204                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved             52977001                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                 97525                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts             3244658117                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                 31782                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles              145392204                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                431843071                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                21602754                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles         464275                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 603219561                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              27160230                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts             3179170609                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                   171                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                6664902                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents               18155043                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                  78588                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.FullRegisterEvents             2271                       # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands          3142601872                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups           15333387016                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups      13133730346                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups          83988681                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps            1993140090                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps               1149461782                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts              21762                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts          19092                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  48856011                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads           1039047790                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores           516447707                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads          54890431                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores         57377876                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                 2969017113                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded               28780                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                2494321710                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued          29655363                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined      1083496611                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined   2947742555                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved           7396                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples    1229682095                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         2.028428                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.901891                       # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total            577643745                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.457377                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        2.300787                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                170543616                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             112383913                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 256390493                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              22882666                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles               15443057                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved             30474424                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                  9349                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts             1602087744                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                 25664                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles               15443057                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                180102309                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                80879107                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles         304937                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 269061579                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              31852756                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts             1553633601                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                 27722                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                3084329                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents               23262068                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents                5400130                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands          1588085164                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            7592228001                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       1750427089                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups          56767331                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps             874778230                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                713306934                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts              13108                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts          10964                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  53001201                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            494421032                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           283375622                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          38186333                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         81232307                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                 1474584555                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded               16256                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                1149612413                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued           2320605                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       685767226                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined   1987453954                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved           4102                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     577643745                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.990175                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.969584                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           391713450     31.85%     31.85% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1           177167826     14.41%     46.26% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2           194208889     15.79%     62.06% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3           164750014     13.40%     75.45% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4           152000166     12.36%     87.81% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5            91333270      7.43%     95.24% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6            42323460      3.44%     98.68% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7            13601870      1.11%     99.79% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8             2583150      0.21%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           197611085     34.21%     34.21% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            85639840     14.83%     49.04% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            74707514     12.93%     61.97% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            82105787     14.21%     76.18% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            66954970     11.59%     87.77% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            40972938      7.09%     94.87% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6            18446421      3.19%     98.06% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             4764432      0.82%     98.88% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8             6440758      1.12%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total      1229682095                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       577643745                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                 1141867      1.24%      1.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                  24392      0.03%      1.27% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      1.27% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      1.27% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      1.27% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      1.27% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      1.27% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      1.27% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      1.27% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      1.27% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      1.27% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      1.27% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      1.27% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      1.27% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      1.27% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      1.27% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      1.27% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      1.27% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      1.27% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      1.27% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      1.27% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      1.27% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      1.27% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      1.27% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      1.27% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      1.27% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      1.27% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      1.27% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      1.27% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead               58632065     63.67%     64.94% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite              32290785     35.06%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  853039      1.90%      1.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                  10574      0.02%      1.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      1.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      1.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      1.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      1.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      1.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      1.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      1.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      1.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      1.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      1.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      1.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      1.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      1.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      1.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      1.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      1.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      1.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      1.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      1.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      1.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      1.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      1.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      1.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      1.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      1.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      1.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      1.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead               27015778     60.17%     62.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite              17022674     37.91%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu            1135683319     45.53%     45.53% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult             11247917      0.45%     45.98% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     45.98% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   3      0.00%     45.98% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     45.98% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     45.98% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     45.98% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     45.98% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     45.98% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     45.98% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     45.98% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     45.98% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     45.98% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     45.98% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     45.98% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     45.98% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     45.98% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     45.98% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     45.98% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     45.98% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd         1375289      0.06%     46.04% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     46.04% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp         6876475      0.28%     46.31% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt         5502263      0.22%     46.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     46.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc       23390431      0.94%     47.47% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     47.47% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     47.47% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     47.47% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            860090981     34.48%     81.95% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite           450155032     18.05%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             506618209     44.07%     44.07% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult              5850863      0.51%     44.58% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     44.58% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     44.58% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     44.58% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     44.58% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     44.58% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     44.58% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     44.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     44.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     44.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     44.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     44.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     44.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     44.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     44.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     44.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     44.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     44.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     44.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd         1274977      0.11%     44.69% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     44.69% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp         3188014      0.28%     44.97% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt         2550893      0.22%     45.19% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     45.19% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc       11539273      1.00%     46.19% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     46.19% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     46.19% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     46.19% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            402298542     34.99%     81.19% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite           216291642     18.81%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total             2494321710                       # Type of FU issued
-system.cpu.iq.rate                           1.964874                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                    92089109                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.036919                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         6216205899                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes        3969996640                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses   2305202146                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads           123864088                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes           82618605                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses     56425277                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses             2521728263                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                64682556                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads         98529432                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total             1149612413                       # Type of FU issued
+system.cpu.iq.rate                           1.934083                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    44902065                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.039058                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         2861318586                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes        2106127825                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses   1031796042                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads            62772655                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes           54292666                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses     30270248                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses             1162493023                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                32021455                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads         23570591                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads    407660609                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses      5276533                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation      2500816                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores    239452410                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads    242180094                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses         1210                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation       685580                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores    154395126                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads            6                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked           420                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads     29018041                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked           192                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles              145392204                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                15914893                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles               1611898                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts          2969058590                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts           2618613                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts            1039047790                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts            516447707                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts              18794                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                1555522                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                 56228                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents        2500816                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect       33181152                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect      1519240                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts             34700392                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts            2424200983                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             818208051                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts          70120727                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles               15443057                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                78194989                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles               1280631                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts          1475233939                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            214769                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             494421032                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts            283375622                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts              10516                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                 630754                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                 23941                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents         685580                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect       16670086                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       506202                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts             17176288                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts            1116354859                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             386341523                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          33257554                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                         12697                       # number of nop insts executed
-system.cpu.iew.exec_refs                   1248100004                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                329019811                       # Number of branches executed
-system.cpu.iew.exec_stores                  429891953                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.909637                       # Inst execution rate
-system.cpu.iew.wb_sent                     2388820620                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                    2361627423                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                1389701712                       # num instructions producing a value
-system.cpu.iew.wb_consumers                2644997142                       # num instructions consuming a value
+system.cpu.iew.exec_nop                        633128                       # number of nop insts executed
+system.cpu.iew.exec_refs                    593821006                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                162537737                       # Number of branches executed
+system.cpu.iew.exec_stores                  207479483                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.878131                       # Inst execution rate
+system.cpu.iew.wb_sent                     1074811517                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                    1062066290                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 606518919                       # num instructions producing a value
+system.cpu.iew.wb_consumers                1092664472                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.860346                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.525408                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.786798                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.555082                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts      1083730173                       # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls           21384                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts          30653233                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples   1084289891                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.738775                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.404247                       # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts       686508704                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls           12154                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts          15406577                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    485351634                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.625069                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.327523                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    445713482     41.11%     41.11% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1    287271007     26.49%     67.60% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     94862412      8.75%     76.35% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     69719327      6.43%     82.78% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     46233776      4.26%     87.04% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5     22314720      2.06%     89.10% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6     15854088      1.46%     90.56% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7     11019318      1.02%     91.58% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     91301761      8.42%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    210489753     43.37%     43.37% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    125850152     25.93%     69.30% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     47800480      9.85%     79.15% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     20690881      4.26%     83.41% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     22810841      4.70%     88.11% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      8150144      1.68%     89.79% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      8105919      1.67%     91.46% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      7050996      1.45%     92.91% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     34402468      7.09%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total   1084289891                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts           1384381606                       # Number of instructions committed
-system.cpu.commit.committedOps             1885336358                       # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total    485351634                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts            640654410                       # Number of instructions committed
+system.cpu.commit.committedOps              788730069                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                      908382478                       # Number of memory references committed
-system.cpu.commit.loads                     631387181                       # Number of loads committed
-system.cpu.commit.membars                        9986                       # Number of memory barriers committed
-system.cpu.commit.branches                  298259106                       # Number of branches committed
-system.cpu.commit.fp_insts                   52289415                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                1653698867                       # Number of committed integer instructions.
-system.cpu.commit.function_calls             41577833                       # Number of function calls committed.
+system.cpu.commit.refs                      381221434                       # Number of memory references committed
+system.cpu.commit.loads                     252240938                       # Number of loads committed
+system.cpu.commit.membars                        5740                       # Number of memory barriers committed
+system.cpu.commit.branches                  137364859                       # Number of branches committed
+system.cpu.commit.fp_insts                   24239771                       # Number of committed floating point instructions.
+system.cpu.commit.int_insts                 682251399                       # Number of committed integer instructions.
+system.cpu.commit.function_calls             19275340                       # Number of function calls committed.
 system.cpu.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu        930022484     49.33%     49.33% # Class of committed instruction
-system.cpu.commit.op_class_0::IntMult        11168279      0.59%     49.92% # Class of committed instruction
-system.cpu.commit.op_class_0::IntDiv                0      0.00%     49.92% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatAdd              0      0.00%     49.92% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatCmp              0      0.00%     49.92% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatCvt              0      0.00%     49.92% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMult             0      0.00%     49.92% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatDiv              0      0.00%     49.92% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     49.92% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAdd               0      0.00%     49.92% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     49.92% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAlu               0      0.00%     49.92% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdCmp               0      0.00%     49.92% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdCvt               0      0.00%     49.92% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMisc              0      0.00%     49.92% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMult              0      0.00%     49.92% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     49.92% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdShift             0      0.00%     49.92% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     49.92% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     49.92% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatAdd      1375288      0.07%     49.99% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     49.99% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatCmp      6876469      0.36%     50.36% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatCvt      5501172      0.29%     50.65% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     50.65% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMisc     22010188      1.17%     51.82% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     51.82% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     51.82% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     51.82% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead       631387181     33.49%     85.31% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite      276995297     14.69%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu        385756793     48.91%     48.91% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult         5173441      0.66%     49.56% # Class of committed instruction
+system.cpu.commit.op_class_0::IntDiv                0      0.00%     49.56% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatAdd              0      0.00%     49.56% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCmp              0      0.00%     49.56% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCvt              0      0.00%     49.56% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatMult             0      0.00%     49.56% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatDiv              0      0.00%     49.56% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     49.56% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAdd               0      0.00%     49.56% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     49.56% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAlu               0      0.00%     49.56% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCmp               0      0.00%     49.56% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCvt               0      0.00%     49.56% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMisc              0      0.00%     49.56% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMult              0      0.00%     49.56% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     49.56% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShift             0      0.00%     49.56% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     49.56% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     49.56% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAdd       637528      0.08%     49.65% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     49.65% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCmp      3187668      0.40%     50.05% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCvt      2550131      0.32%     50.37% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     50.37% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMisc     10203074      1.29%     51.67% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     51.67% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     51.67% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     51.67% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead       252240938     31.98%     83.65% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite      128980496     16.35%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total        1885336358                       # Class of committed instruction
-system.cpu.commit.bw_lim_events              91301761                       # number cycles where commit BW limit reached
+system.cpu.commit.op_class_0::total         788730069                       # Class of committed instruction
+system.cpu.commit.bw_lim_events              34402468                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                   3962036316                       # The number of ROB reads
-system.cpu.rob.rob_writes                  6083536675                       # The number of ROB writes
-system.cpu.timesIdled                          355726                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                        39774062                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts                  1384370590                       # Number of Instructions Simulated
-system.cpu.committedOps                    1885325342                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               0.916992                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.916992                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.090523                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.090523                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads              12060176633                       # number of integer regfile reads
-system.cpu.int_regfile_writes              2272688052                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                  68797676                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                 49536165                       # number of floating regfile writes
-system.cpu.misc_regfile_reads              1701422665                       # number of misc regfile reads
-system.cpu.misc_regfile_writes               13772902                       # number of misc regfile writes
-system.cpu.toL2Bus.throughput               167841675                       # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq        1495790                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       1495789                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback        96290                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq         4533                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp         4533                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq        72512                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp        72512                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        57900                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      3179527                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           3237427                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1707776                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    104536000                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total      106243776                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus         106243776                       # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus       290048                       # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy      930852999                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy      47253245                       # Layer occupancy (ticks)
+system.cpu.rob.rob_reads                   1926179188                       # The number of ROB reads
+system.cpu.rob.rob_writes                  3042778169                       # The number of ROB writes
+system.cpu.timesIdled                          159779                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                        16752807                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts                   640649298                       # Number of Instructions Simulated
+system.cpu.committedOps                     788724957                       # Number of Ops (including micro ops) Simulated
+system.cpu.cpi                               0.927803                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.927803                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.077815                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.077815                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               1132703521                       # number of integer regfile reads
+system.cpu.int_regfile_writes               646986163                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                  37276202                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                 27223952                       # number of floating regfile writes
+system.cpu.cc_regfile_reads                4371075707                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                413227106                       # number of cc regfile writes
+system.cpu.misc_regfile_reads               814254354                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                6386808                       # number of misc regfile writes
+system.cpu.toL2Bus.throughput               191669699                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq         729385                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp        729383                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback        91367                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq         2337                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp         2337                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq        69311                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp        69311                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        26757                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      1664338                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           1691095                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       781440                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     56032960                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total       56814400                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus          56814400                       # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus       149504                       # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy      537567000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          0.2                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy      22218748                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    2371526007                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    1220548813                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.4                       # Layer utilization (%)
-system.cpu.icache.tags.replacements             24993                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1647.783456                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           357995053                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs             26684                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          13416.094026                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements             10545                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1626.781544                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           207828971                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs             12209                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          17022.603899                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1647.783456                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.804582                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.804582                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024         1691                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           64                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1           70                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2            2                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3            4                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4         1551                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.825684                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         716098748                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        716098748                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    357999320                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       357999320                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     357999320                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        357999320                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    357999320                       # number of overall hits
-system.cpu.icache.overall_hits::total       357999320                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst        34446                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total         34446                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst        34446                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total          34446                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst        34446                       # number of overall misses
-system.cpu.icache.overall_misses::total         34446                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    570147243                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    570147243                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    570147243                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    570147243                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    570147243                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    570147243                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    358033766                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    358033766                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    358033766                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    358033766                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    358033766                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    358033766                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000096                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000096                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000096                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000096                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000096                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000096                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16551.914388                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 16551.914388                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 16551.914388                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 16551.914388                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 16551.914388                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 16551.914388                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs         1683                       # number of cycles access was blocked
+system.cpu.icache.tags.occ_blocks::cpu.inst  1626.781544                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.794327                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.794327                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1664                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           47                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           67                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2            1                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1549                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.812500                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses         415715422                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        415715422                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    207833630                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       207833630                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     207833630                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        207833630                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    207833630                       # number of overall hits
+system.cpu.icache.overall_hits::total       207833630                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst        16808                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total         16808                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst        16808                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total          16808                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst        16808                       # number of overall misses
+system.cpu.icache.overall_misses::total         16808                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    373718245                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    373718245                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    373718245                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    373718245                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    373718245                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    373718245                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    207850438                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    207850438                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    207850438                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    207850438                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    207850438                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    207850438                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000081                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000081                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000081                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000081                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000081                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000081                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22234.545752                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 22234.545752                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 22234.545752                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 22234.545752                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 22234.545752                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 22234.545752                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs         1690                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                28                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                26                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    60.107143                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs           65                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst         3230                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total         3230                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst         3230                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total         3230                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst         3230                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total         3230                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst        31216                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total        31216                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst        31216                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total        31216                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst        31216                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total        31216                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    454582253                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    454582253                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    454582253                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    454582253                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    454582253                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    454582253                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000087                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000087                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000087                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.000087                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000087                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.000087                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14562.476070                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14562.476070                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14562.476070                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 14562.476070                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14562.476070                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 14562.476070                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         2261                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total         2261                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst         2261                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total         2261                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst         2261                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total         2261                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst        14547                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total        14547                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst        14547                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total        14547                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst        14547                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total        14547                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    287782750                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    287782750                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    287782750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    287782750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    287782750                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    287782750                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000070                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000070                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000070                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.000070                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000070                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.000070                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19782.962123                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19782.962123                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19782.962123                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 19782.962123                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19782.962123                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 19782.962123                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements           442210                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        32678.682015                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            1111317                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           474958                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             2.339822                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements           257640                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        32630.586328                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs             527670                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           290385                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             1.817139                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks  1315.086004                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst    50.777344                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 31312.818667                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.040133                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.001550                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.955591                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.997274                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        32748                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           98                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          159                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          497                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         4974                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        27020                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.999390                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         13864217                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        13864217                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst        24244                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data      1058074                       # number of ReadReq hits
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 system.cpu.l2cache.UpgradeReq_hits::cpu.data            3                       # number of UpgradeReq hits
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 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -888,201 +887,217 @@ system.cpu.l2cache.cache_copies                     0                       # nu
 system.cpu.l2cache.writebacks::writebacks        66098                       # number of writebacks
 system.cpu.l2cache.writebacks::total            66098                       # number of writebacks
 system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            2                       # number of ReadReq MSHR hits
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 system.cpu.l2cache.demand_mshr_hits::cpu.inst            2                       # number of demand (read+write) MSHR hits
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 system.cpu.l2cache.overall_mshr_hits::cpu.inst            2                       # number of overall MSHR hits
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+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data       221998                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total       224345                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         2334                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total         2334                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        66079                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total        66079                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         2347                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       288077                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       290424                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         2347                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       288077                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       290424                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    142668750                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  13415878250                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total  13558547000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     23342334                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     23342334                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   4297620250                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   4297620250                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    142668750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  17713498500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  17856167250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    142668750                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  17713498500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  17856167250                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.192204                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.310557                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.308569                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.998716                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.998716                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.953370                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.953370                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.192204                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.367375                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.364689                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.192204                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.367375                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.364689                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60787.707712                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60432.428445                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60436.145223                       # average ReadReq mshr miss latency
 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        10001                       # average UpgradeReq mshr miss latency
 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        10001                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59380.766088                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59380.766088                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59708.675144                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59743.512911                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59743.334098                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59708.675144                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59743.512911                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59743.334098                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65037.610285                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65037.610285                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60787.707712                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61488.763421                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61483.097988                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60787.707712                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61488.763421                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61483.097988                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements           1532989                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4094.399228                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           981387634                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           1537085                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            638.473236                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         399634250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4094.399228                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999609                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999609                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements            780052                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4092.850454                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           456274938                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            784148                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs            581.873496                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle         340792000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4092.850454                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.999231                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999231                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           42                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          264                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2          980                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3         2382                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::4          428                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           47                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          258                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          976                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3         2364                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4          451                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses        1969885597                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses       1969885597                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    705264252                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       705264252                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    276089331                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      276089331                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data         9999                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total         9999                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data         9985                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total         9985                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     981353583                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        981353583                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    981353583                       # number of overall hits
-system.cpu.dcache.overall_hits::total       981353583                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      1954339                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       1954339                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       846347                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       846347                       # number of WriteReq misses
+system.cpu.dcache.tags.tag_accesses         918547346                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        918547346                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    328318489                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       328318489                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    127934774                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      127934774                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data         3905                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total          3905                       # number of SoftPFReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data         5745                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total         5745                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data         5739                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total         5739                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data     456253263                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        456253263                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    456257168                       # number of overall hits
+system.cpu.dcache.overall_hits::total       456257168                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      1596085                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       1596085                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      1016703                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      1016703                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data          156                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total          156                       # number of SoftPFReq misses
 system.cpu.dcache.LoadLockedReq_misses::cpu.data            3                       # number of LoadLockedReq misses
 system.cpu.dcache.LoadLockedReq_misses::total            3                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data      2800686                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        2800686                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      2800686                       # number of overall misses
-system.cpu.dcache.overall_misses::total       2800686                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  78948283141                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  78948283141                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  58782925343                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  58782925343                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       464000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total       464000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 137731208484                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 137731208484                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 137731208484                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 137731208484                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    707218591                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    707218591                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data    276935678                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total    276935678                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data        10002                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total        10002                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data         9985                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total         9985                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    984154269                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    984154269                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    984154269                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    984154269                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.002763                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.002763                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.003056                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.003056                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.000300                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.000300                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.002846                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.002846                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.002846                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.002846                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40396.411851                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 40396.411851                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69454.875297                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 69454.875297                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 154666.666667                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 154666.666667                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 49177.668787                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 49177.668787                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 49177.668787                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 49177.668787                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs         2986                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets          861                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                60                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets              79                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    49.766667                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets    10.898734                       # average number of cycles each access was blocked
+system.cpu.dcache.demand_misses::cpu.data      2612788                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        2612788                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      2612944                       # number of overall misses
+system.cpu.dcache.overall_misses::total       2612944                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  65672832321                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  65672832321                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  69021730126                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  69021730126                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       224500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total       224500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 134694562447                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 134694562447                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 134694562447                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 134694562447                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    329914574                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    329914574                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data    128951477                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total    128951477                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data         4061                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total         4061                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data         5748                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total         5748                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data         5739                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total         5739                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data    458866051                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    458866051                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    458870112                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    458870112                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.004838                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.004838                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.007884                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.007884                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.038414                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.038414                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.000522                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.000522                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.005694                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.005694                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.005694                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.005694                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41146.199808                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 41146.199808                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 67887.800199                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 67887.800199                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 74833.333333                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 74833.333333                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 51552.044195                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 51552.044195                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 51548.966395                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 51548.966395                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs         3326                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets          660                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                72                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               8                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    46.194444                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets    82.500000                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks        96290                       # number of writebacks
-system.cpu.dcache.writebacks::total             96290                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       489763                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       489763                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       769304                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       769304                       # number of WriteReq MSHR hits
+system.cpu.dcache.writebacks::writebacks        91367                       # number of writebacks
+system.cpu.dcache.writebacks::total             91367                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       881385                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       881385                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       945064                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       945064                       # number of WriteReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            3                       # number of LoadLockedReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::total            3                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      1259067                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      1259067                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      1259067                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      1259067                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1464576                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      1464576                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data        77043                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total        77043                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      1541619                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      1541619                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      1541619                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      1541619                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  41415183522                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  41415183522                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   4998292971                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   4998292971                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  46413476493                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  46413476493                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  46413476493                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  46413476493                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.002071                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.002071                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000278                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000278                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.001566                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.001566                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.001566                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.001566                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 28277.934038                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 28277.934038                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 64876.665901                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64876.665901                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30106.969681                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 30106.969681                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30106.969681                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 30106.969681                       # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_hits::cpu.data      1826449                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      1826449                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      1826449                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      1826449                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       714700                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       714700                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data        71639                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total        71639                       # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data          147                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total          147                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       786339                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       786339                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       786486                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       786486                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  21837733771                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  21837733771                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   5293200916                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   5293200916                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data      2189000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total      2189000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  27130934687                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  27130934687                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  27133123687                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  27133123687                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.002166                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.002166                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000556                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000556                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.036198                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.036198                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.001714                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.001714                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.001714                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.001714                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30555.105318                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30555.105318                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73887.141306                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73887.141306                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14891.156463                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14891.156463                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34502.847610                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 34502.847610                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34499.182041                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 34499.182041                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt
index 620dbb60e..a6a0dd3a8 100644
--- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt
@@ -1,42 +1,42 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.945613                       # Number of seconds simulated
-sim_ticks                                945613126000                       # Number of ticks simulated
-final_tick                               945613126000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.395727                       # Number of seconds simulated
+sim_ticks                                395726778000                       # Number of ticks simulated
+final_tick                               395726778000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1407956                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1917442                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              961716087                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 309672                       # Number of bytes of host memory used
-host_seconds                                   983.26                       # Real time elapsed on the host
-sim_insts                                  1384381606                       # Number of instructions simulated
-sim_ops                                    1885336358                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 935276                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1151448                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              577711928                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 250216                       # Number of bytes of host memory used
+host_seconds                                   684.99                       # Real time elapsed on the host
+sim_insts                                   640654410                       # Number of instructions simulated
+sim_ops                                     788730069                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst        5561086004                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data        2464405274                       # Number of bytes read from this memory
-system.physmem.bytes_read::total           8025491278                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst   5561086004                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total      5561086004                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::cpu.data     1123958396                       # Number of bytes written to this memory
-system.physmem.bytes_written::total        1123958396                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst         1390271501                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data          620345398                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total            2010616899                       # Number of read requests responded to by this memory
-system.physmem.num_writes::cpu.data         276945663                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total            276945663                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst           5880931484                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data           2606145374                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              8487076858                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst      5880931484                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total         5880931484                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data          1188602786                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total             1188602786                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst          5880931484                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data          3794748160                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             9675679644                       # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput                   9675679644                       # Throughput (bytes/s)
-system.membus.data_through_bus             9149449674                       # Total data (bytes)
+system.physmem.bytes_read::cpu.inst        2573511592                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data        1144718516                       # Number of bytes read from this memory
+system.physmem.bytes_read::total           3718230108                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst   2573511592                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total      2573511592                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::cpu.data      523317413                       # Number of bytes written to this memory
+system.physmem.bytes_written::total         523317413                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst          643377898                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data          250335238                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total             893713136                       # Number of read requests responded to by this memory
+system.physmem.num_writes::cpu.data         128957216                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total            128957216                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst           6503253596                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data           2892699154                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              9395952750                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst      6503253596                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total         6503253596                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data          1322421029                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total             1322421029                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst          6503253596                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data          4215120183                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total            10718373779                       # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput                  10718373779                       # Throughput (bytes/s)
+system.membus.data_through_bus             4241547521                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
@@ -123,64 +123,66 @@ system.cpu.itb.inst_accesses                        0                       # IT
 system.cpu.itb.hits                                 0                       # DTB hits
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
-system.cpu.workload.num_syscalls                 1411                       # Number of system calls
-system.cpu.numCycles                       1891226253                       # number of cpu cycles simulated
+system.cpu.workload.num_syscalls                  673                       # Number of system calls
+system.cpu.numCycles                        791453557                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                  1384381606                       # Number of instructions committed
-system.cpu.committedOps                    1885336358                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses            1653698868                       # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses               52289415                       # Number of float alu accesses
-system.cpu.num_func_calls                    80372855                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts    230619738                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                   1653698868                       # number of integer instructions
-system.cpu.num_fp_insts                      52289415                       # number of float instructions
-system.cpu.num_int_register_reads          8779152446                       # number of times the integer registers were read
-system.cpu.num_int_register_writes         1874331393                       # number of times the integer registers were written
-system.cpu.num_fp_register_reads             60540850                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes            46777010                       # number of times the floating registers were written
-system.cpu.num_mem_refs                     908382479                       # number of memory refs
-system.cpu.num_load_insts                   631387181                       # Number of load instructions
-system.cpu.num_store_insts                  276995298                       # Number of store instructions
+system.cpu.committedInsts                   640654410                       # Number of instructions committed
+system.cpu.committedOps                     788730069                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses             682251400                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses               24239771                       # Number of float alu accesses
+system.cpu.num_func_calls                    37261296                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts     91575866                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                    682251400                       # number of integer instructions
+system.cpu.num_fp_insts                      24239771                       # number of float instructions
+system.cpu.num_int_register_reads          1320162254                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          468423268                       # number of times the integer registers were written
+system.cpu.num_fp_register_reads             28064643                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes            21684311                       # number of times the floating registers were written
+system.cpu.num_cc_register_reads           2369173291                       # number of times the CC registers were read
+system.cpu.num_cc_register_writes           351919006                       # number of times the CC registers were written
+system.cpu.num_mem_refs                     381221435                       # number of memory refs
+system.cpu.num_load_insts                   252240938                       # Number of load instructions
+system.cpu.num_store_insts                  128980497                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                 1891226253                       # Number of busy cycles
+system.cpu.num_busy_cycles                  791453557                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
-system.cpu.Branches                         298259106                       # Number of branches fetched
+system.cpu.Branches                         137364859                       # Number of branches fetched
 system.cpu.op_class::No_OpClass                     0      0.00%      0.00% # Class of executed instruction
-system.cpu.op_class::IntAlu                 930023895     49.33%     49.33% # Class of executed instruction
-system.cpu.op_class::IntMult                 11168279      0.59%     49.92% # Class of executed instruction
-system.cpu.op_class::IntDiv                         0      0.00%     49.92% # Class of executed instruction
-system.cpu.op_class::FloatAdd                       0      0.00%     49.92% # Class of executed instruction
-system.cpu.op_class::FloatCmp                       0      0.00%     49.92% # Class of executed instruction
-system.cpu.op_class::FloatCvt                       0      0.00%     49.92% # Class of executed instruction
-system.cpu.op_class::FloatMult                      0      0.00%     49.92% # Class of executed instruction
-system.cpu.op_class::FloatDiv                       0      0.00%     49.92% # Class of executed instruction
-system.cpu.op_class::FloatSqrt                      0      0.00%     49.92% # Class of executed instruction
-system.cpu.op_class::SimdAdd                        0      0.00%     49.92% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc                     0      0.00%     49.92% # Class of executed instruction
-system.cpu.op_class::SimdAlu                        0      0.00%     49.92% # Class of executed instruction
-system.cpu.op_class::SimdCmp                        0      0.00%     49.92% # Class of executed instruction
-system.cpu.op_class::SimdCvt                        0      0.00%     49.92% # Class of executed instruction
-system.cpu.op_class::SimdMisc                       0      0.00%     49.92% # Class of executed instruction
-system.cpu.op_class::SimdMult                       0      0.00%     49.92% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc                    0      0.00%     49.92% # Class of executed instruction
-system.cpu.op_class::SimdShift                      0      0.00%     49.92% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc                   0      0.00%     49.92% # Class of executed instruction
-system.cpu.op_class::SimdSqrt                       0      0.00%     49.92% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd             1375288      0.07%     49.99% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu                   0      0.00%     49.99% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp             6876469      0.36%     50.36% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt             5501172      0.29%     50.65% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv                   0      0.00%     50.65% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc           22010188      1.17%     51.82% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult                  0      0.00%     51.82% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc               0      0.00%     51.82% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt                  0      0.00%     51.82% # Class of executed instruction
-system.cpu.op_class::MemRead                631387181     33.49%     85.31% # Class of executed instruction
-system.cpu.op_class::MemWrite               276995298     14.69%    100.00% # Class of executed instruction
+system.cpu.op_class::IntAlu                 385757466     48.91%     48.91% # Class of executed instruction
+system.cpu.op_class::IntMult                  5173441      0.66%     49.56% # Class of executed instruction
+system.cpu.op_class::IntDiv                         0      0.00%     49.56% # Class of executed instruction
+system.cpu.op_class::FloatAdd                       0      0.00%     49.56% # Class of executed instruction
+system.cpu.op_class::FloatCmp                       0      0.00%     49.56% # Class of executed instruction
+system.cpu.op_class::FloatCvt                       0      0.00%     49.56% # Class of executed instruction
+system.cpu.op_class::FloatMult                      0      0.00%     49.56% # Class of executed instruction
+system.cpu.op_class::FloatDiv                       0      0.00%     49.56% # Class of executed instruction
+system.cpu.op_class::FloatSqrt                      0      0.00%     49.56% # Class of executed instruction
+system.cpu.op_class::SimdAdd                        0      0.00%     49.56% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc                     0      0.00%     49.56% # Class of executed instruction
+system.cpu.op_class::SimdAlu                        0      0.00%     49.56% # Class of executed instruction
+system.cpu.op_class::SimdCmp                        0      0.00%     49.56% # Class of executed instruction
+system.cpu.op_class::SimdCvt                        0      0.00%     49.56% # Class of executed instruction
+system.cpu.op_class::SimdMisc                       0      0.00%     49.56% # Class of executed instruction
+system.cpu.op_class::SimdMult                       0      0.00%     49.56% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc                    0      0.00%     49.56% # Class of executed instruction
+system.cpu.op_class::SimdShift                      0      0.00%     49.56% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc                   0      0.00%     49.56% # Class of executed instruction
+system.cpu.op_class::SimdSqrt                       0      0.00%     49.56% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd              637528      0.08%     49.65% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu                   0      0.00%     49.65% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp             3187668      0.40%     50.05% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt             2550131      0.32%     50.37% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv                   0      0.00%     50.37% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc           10203074      1.29%     51.67% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult                  0      0.00%     51.67% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc               0      0.00%     51.67% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt                  0      0.00%     51.67% # Class of executed instruction
+system.cpu.op_class::MemRead                252240938     31.98%     83.65% # Class of executed instruction
+system.cpu.op_class::MemWrite               128980497     16.35%    100.00% # Class of executed instruction
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::total                 1885337770                       # Class of executed instruction
+system.cpu.op_class::total                  788730743                       # Class of executed instruction
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
index baba5d53b..d4c7242b6 100644
--- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
@@ -1,56 +1,56 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.326119                       # Number of seconds simulated
-sim_ticks                                2326118592000                       # Number of ticks simulated
-final_tick                               2326118592000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  1.043695                       # Number of seconds simulated
+sim_ticks                                1043695084000                       # Number of ticks simulated
+final_tick                               1043695084000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 706219                       # Simulator instruction rate (inst/s)
-host_op_rate                                   958037                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1189016431                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 318376                       # Number of bytes of host memory used
-host_seconds                                  1956.34                       # Real time elapsed on the host
-sim_insts                                  1381604339                       # Number of instructions simulated
-sim_ops                                    1874244941                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 520727                       # Simulator instruction rate (inst/s)
+host_op_rate                                   639745                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              850028397                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 259968                       # Number of bytes of host memory used
+host_seconds                                  1227.84                       # Real time elapsed on the host
+sim_insts                                   639366786                       # Number of instructions simulated
+sim_ops                                     785501034                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            113472                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          30232512                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             30345984                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       113472                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          113472                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      4230336                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           4230336                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               1773                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             472383                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                474156                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           66099                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total                66099                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst                48782                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             12996978                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                13045760                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst           48782                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total              48782                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1818624                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1818624                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1818624                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst               48782                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            12996978                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               14864384                       # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput                     14864384                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq              408063                       # Transaction distribution
-system.membus.trans_dist::ReadResp             408063                       # Transaction distribution
-system.membus.trans_dist::Writeback             66099                       # Transaction distribution
+system.physmem.bytes_read::cpu.inst            113280                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          18428288                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             18541568                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       113280                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          113280                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      4230272                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           4230272                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               1770                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             287942                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                289712                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           66098                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                66098                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst               108537                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             17656774                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                17765311                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          108537                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             108537                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           4053168                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                4053168                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           4053168                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              108537                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            17656774                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               21818480                       # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput                     21818480                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq              223619                       # Transaction distribution
+system.membus.trans_dist::ReadResp             223619                       # Transaction distribution
+system.membus.trans_dist::Writeback             66098                       # Transaction distribution
 system.membus.trans_dist::ReadExReq             66093                       # Transaction distribution
 system.membus.trans_dist::ReadExResp            66093                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1014411                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1014411                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     34576320                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total            34576320                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus               34576320                       # Total data (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       645522                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 645522                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     22771840                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total            22771840                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus               22771840                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy          1069047000                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         4267404000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy           884977500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               0.1                       # Layer utilization (%)
+system.membus.respLayer1.occupancy         2607766500                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
@@ -137,117 +137,119 @@ system.cpu.itb.inst_accesses                        0                       # IT
 system.cpu.itb.hits                                 0                       # DTB hits
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
-system.cpu.workload.num_syscalls                 1411                       # Number of system calls
-system.cpu.numCycles                       4652237184                       # number of cpu cycles simulated
+system.cpu.workload.num_syscalls                  673                       # Number of system calls
+system.cpu.numCycles                       2087390168                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                  1381604339                       # Number of instructions committed
-system.cpu.committedOps                    1874244941                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses            1653698868                       # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses               52289415                       # Number of float alu accesses
-system.cpu.num_func_calls                    80372855                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts    230619738                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                   1653698868                       # number of integer instructions
-system.cpu.num_fp_insts                      52289415                       # number of float instructions
-system.cpu.num_int_register_reads         10644316447                       # number of times the integer registers were read
-system.cpu.num_int_register_writes         1874331393                       # number of times the integer registers were written
-system.cpu.num_fp_register_reads             60540850                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes            46777010                       # number of times the floating registers were written
-system.cpu.num_mem_refs                     908382479                       # number of memory refs
-system.cpu.num_load_insts                   631387181                       # Number of load instructions
-system.cpu.num_store_insts                  276995298                       # Number of store instructions
+system.cpu.committedInsts                   639366786                       # Number of instructions committed
+system.cpu.committedOps                     785501034                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses             682251400                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses               24239771                       # Number of float alu accesses
+system.cpu.num_func_calls                    37261296                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts     91575866                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                    682251400                       # number of integer instructions
+system.cpu.num_fp_insts                      24239771                       # number of float instructions
+system.cpu.num_int_register_reads          1323974869                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          468423268                       # number of times the integer registers were written
+system.cpu.num_fp_register_reads             28064643                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes            21684311                       # number of times the floating registers were written
+system.cpu.num_cc_register_reads           3116296057                       # number of times the CC registers were read
+system.cpu.num_cc_register_writes           351919006                       # number of times the CC registers were written
+system.cpu.num_mem_refs                     381221435                       # number of memory refs
+system.cpu.num_load_insts                   252240938                       # Number of load instructions
+system.cpu.num_store_insts                  128980497                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                 4652237184                       # Number of busy cycles
+system.cpu.num_busy_cycles                 2087390168                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
-system.cpu.Branches                         298259106                       # Number of branches fetched
+system.cpu.Branches                         137364859                       # Number of branches fetched
 system.cpu.op_class::No_OpClass                     0      0.00%      0.00% # Class of executed instruction
-system.cpu.op_class::IntAlu                 930023895     49.33%     49.33% # Class of executed instruction
-system.cpu.op_class::IntMult                 11168279      0.59%     49.92% # Class of executed instruction
-system.cpu.op_class::IntDiv                         0      0.00%     49.92% # Class of executed instruction
-system.cpu.op_class::FloatAdd                       0      0.00%     49.92% # Class of executed instruction
-system.cpu.op_class::FloatCmp                       0      0.00%     49.92% # Class of executed instruction
-system.cpu.op_class::FloatCvt                       0      0.00%     49.92% # Class of executed instruction
-system.cpu.op_class::FloatMult                      0      0.00%     49.92% # Class of executed instruction
-system.cpu.op_class::FloatDiv                       0      0.00%     49.92% # Class of executed instruction
-system.cpu.op_class::FloatSqrt                      0      0.00%     49.92% # Class of executed instruction
-system.cpu.op_class::SimdAdd                        0      0.00%     49.92% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc                     0      0.00%     49.92% # Class of executed instruction
-system.cpu.op_class::SimdAlu                        0      0.00%     49.92% # Class of executed instruction
-system.cpu.op_class::SimdCmp                        0      0.00%     49.92% # Class of executed instruction
-system.cpu.op_class::SimdCvt                        0      0.00%     49.92% # Class of executed instruction
-system.cpu.op_class::SimdMisc                       0      0.00%     49.92% # Class of executed instruction
-system.cpu.op_class::SimdMult                       0      0.00%     49.92% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc                    0      0.00%     49.92% # Class of executed instruction
-system.cpu.op_class::SimdShift                      0      0.00%     49.92% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc                   0      0.00%     49.92% # Class of executed instruction
-system.cpu.op_class::SimdSqrt                       0      0.00%     49.92% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd             1375288      0.07%     49.99% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu                   0      0.00%     49.99% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp             6876469      0.36%     50.36% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt             5501172      0.29%     50.65% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv                   0      0.00%     50.65% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc           22010188      1.17%     51.82% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult                  0      0.00%     51.82% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc               0      0.00%     51.82% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt                  0      0.00%     51.82% # Class of executed instruction
-system.cpu.op_class::MemRead                631387181     33.49%     85.31% # Class of executed instruction
-system.cpu.op_class::MemWrite               276995298     14.69%    100.00% # Class of executed instruction
+system.cpu.op_class::IntAlu                 385757466     48.91%     48.91% # Class of executed instruction
+system.cpu.op_class::IntMult                  5173441      0.66%     49.56% # Class of executed instruction
+system.cpu.op_class::IntDiv                         0      0.00%     49.56% # Class of executed instruction
+system.cpu.op_class::FloatAdd                       0      0.00%     49.56% # Class of executed instruction
+system.cpu.op_class::FloatCmp                       0      0.00%     49.56% # Class of executed instruction
+system.cpu.op_class::FloatCvt                       0      0.00%     49.56% # Class of executed instruction
+system.cpu.op_class::FloatMult                      0      0.00%     49.56% # Class of executed instruction
+system.cpu.op_class::FloatDiv                       0      0.00%     49.56% # Class of executed instruction
+system.cpu.op_class::FloatSqrt                      0      0.00%     49.56% # Class of executed instruction
+system.cpu.op_class::SimdAdd                        0      0.00%     49.56% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc                     0      0.00%     49.56% # Class of executed instruction
+system.cpu.op_class::SimdAlu                        0      0.00%     49.56% # Class of executed instruction
+system.cpu.op_class::SimdCmp                        0      0.00%     49.56% # Class of executed instruction
+system.cpu.op_class::SimdCvt                        0      0.00%     49.56% # Class of executed instruction
+system.cpu.op_class::SimdMisc                       0      0.00%     49.56% # Class of executed instruction
+system.cpu.op_class::SimdMult                       0      0.00%     49.56% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc                    0      0.00%     49.56% # Class of executed instruction
+system.cpu.op_class::SimdShift                      0      0.00%     49.56% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc                   0      0.00%     49.56% # Class of executed instruction
+system.cpu.op_class::SimdSqrt                       0      0.00%     49.56% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd              637528      0.08%     49.65% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu                   0      0.00%     49.65% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp             3187668      0.40%     50.05% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt             2550131      0.32%     50.37% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv                   0      0.00%     50.37% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc           10203074      1.29%     51.67% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult                  0      0.00%     51.67% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc               0      0.00%     51.67% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt                  0      0.00%     51.67% # Class of executed instruction
+system.cpu.op_class::MemRead                252240938     31.98%     83.65% # Class of executed instruction
+system.cpu.op_class::MemWrite               128980497     16.35%    100.00% # Class of executed instruction
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::total                 1885337770                       # Class of executed instruction
-system.cpu.icache.tags.replacements             18364                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1392.317060                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs          1390251699                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs             19803                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          70204.095289                       # Average number of references to valid blocks.
+system.cpu.op_class::total                  788730743                       # Class of executed instruction
+system.cpu.icache.tags.replacements              8769                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1391.464499                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           643367691                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs             10208                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          63025.831799                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1392.317060                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.679842                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.679842                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst  1391.464499                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.679426                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.679426                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         1439                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           43                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1           57                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::4         1339                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.702637                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses        2780562807                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses       2780562807                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst   1390251699                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total      1390251699                       # number of ReadReq hits
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-system.cpu.icache.demand_hits::total       1390251699                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst   1390251699                       # number of overall hits
-system.cpu.icache.overall_hits::total      1390251699                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst        19803                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total         19803                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst        19803                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total          19803                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst        19803                       # number of overall misses
-system.cpu.icache.overall_misses::total         19803                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    331911000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    331911000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    331911000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    331911000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    331911000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    331911000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst   1390271502                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total   1390271502                       # number of ReadReq accesses(hits+misses)
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-system.cpu.icache.demand_accesses::total   1390271502                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst   1390271502                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total   1390271502                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000014                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000014                       # miss rate for ReadReq accesses
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-system.cpu.icache.demand_miss_rate::total     0.000014                       # miss rate for demand accesses
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-system.cpu.icache.overall_miss_rate::total     0.000014                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16760.642327                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 16760.642327                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 16760.642327                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 16760.642327                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 16760.642327                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 16760.642327                       # average overall miss latency
+system.cpu.icache.tags.tag_accesses        1286766006                       # Number of tag accesses
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+system.cpu.icache.ReadReq_miss_latency::cpu.inst    207122500                       # number of ReadReq miss cycles
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+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000016                       # miss rate for ReadReq accesses
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+system.cpu.icache.demand_avg_miss_latency::total 20290.213558                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 20290.213558                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 20290.213558                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -256,123 +258,123 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst        19803                       # number of ReadReq MSHR misses
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-system.cpu.icache.overall_mshr_misses::total        19803                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    292305000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    292305000                       # number of ReadReq MSHR miss cycles
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-system.cpu.icache.overall_mshr_miss_latency::total    292305000                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000014                       # mshr miss rate for ReadReq accesses
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+system.cpu.icache.overall_avg_mshr_miss_latency::total 18290.213558                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements           441378                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        32692.891822                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            1102614                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           474121                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             2.325596                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements           256932                       # number of replacements
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+system.cpu.l2cache.tags.avg_refs             1.811499                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks  1298.141733                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst    30.233408                       # Average occupied blocks per requestor
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-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           68                       # Occupied blocks per task id
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 system.cpu.l2cache.tags.age_task_id_blocks_1024::1          120                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          144                       # Occupied blocks per task id
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 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.999237                       # Percentage of cache occupancy per task id
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-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.089532                       # miss rate for ReadReq accesses
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-system.cpu.l2cache.demand_miss_rate::cpu.data     0.308012                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.305227                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.089532                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.308012                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.305227                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52003.384095                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data        52000                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000.014704                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        52000                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total        52000                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52003.384095                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data        52000                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 52000.012654                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52003.384095                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data        52000                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 52000.012654                       # average overall miss latency
+system.cpu.l2cache.demand_misses::cpu.inst         1770                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       287942                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        289712                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         1770                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data       287942                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       289712                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     92118500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data  11536392000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total  11628510500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   3436883000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   3436883000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     92118500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  14973275000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  15065393500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     92118500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  14973275000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  15065393500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst        10208                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data       712819                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total       723027                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks        91561                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total        91561                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data        69323                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total        69323                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst        10208                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data       782142                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total       792350                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst        10208                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data       782142                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total       792350                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.173393                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.311228                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.309282                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.953407                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.953407                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.173393                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.368145                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.365636                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.173393                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.368145                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.365636                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52044.350282                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52001.099847                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 52001.442185                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.711119                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.711119                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52044.350282                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52001.010620                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 52001.275405                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52044.350282                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52001.010620                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 52001.275405                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -381,127 +383,135 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        66099                       # number of writebacks
-system.cpu.l2cache.writebacks::total            66099                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         1773                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data       406290                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total       408063                       # number of ReadReq MSHR misses
+system.cpu.l2cache.writebacks::writebacks        66098                       # number of writebacks
+system.cpu.l2cache.writebacks::total            66098                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         1770                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data       221849                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total       223619                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        66093                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total        66093                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         1773                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       472383                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       474156                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         1773                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       472383                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       474156                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     70926000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  16251600000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total  16322526000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         1770                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       287942                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       289712                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         1770                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       287942                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       289712                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     70811000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   8873960000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total   8944771000                       # number of ReadReq MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   2643720000                       # number of ReadExReq MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   2643720000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     70926000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  18895320000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  18966246000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     70926000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  18895320000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  18966246000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.089532                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.278115                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.275592                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.908120                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.908120                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.089532                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.308012                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.305227                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.089532                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.308012                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.305227                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40003.384095                       # average ReadReq mshr miss latency
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     70811000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  11517680000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  11588491000                       # number of demand (read+write) MSHR miss cycles
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+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  11517680000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  11588491000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.173393                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.311228                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.309282                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.953407                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.953407                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.173393                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.368145                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.365636                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.173393                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.368145                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.365636                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40006.214689                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000.014704                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000.049191                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadExReq mshr miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total        40000                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40003.384095                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40006.214689                       # average overall mshr miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000.012654                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40003.384095                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000.037969                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40006.214689                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.012654                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.037969                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements           1529557                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4094.947189                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           895757408                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           1533653                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            584.067848                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         991199000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4094.947189                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999743                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999743                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements            778046                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4093.640576                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           378510311                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            782142                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs            483.940654                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle         996417000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4093.640576                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.999424                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999424                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           29                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          118                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2          568                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3         1040                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::4         2341                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           27                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          123                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          591                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3         1036                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4         2319                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses        1796115775                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses       1796115775                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    618874540                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       618874540                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    276862898                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      276862898                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data         9985                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total         9985                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data         9985                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total         9985                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     895737438                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        895737438                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    895737438                       # number of overall hits
-system.cpu.dcache.overall_hits::total       895737438                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      1460873                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       1460873                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data        72780                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total        72780                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data      1533653                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        1533653                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      1533653                       # number of overall misses
-system.cpu.dcache.overall_misses::total       1533653                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  36055529000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  36055529000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   3722046000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   3722046000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  39777575000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  39777575000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  39777575000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  39777575000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    620335413                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    620335413                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data    276935678                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total    276935678                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data         9985                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total         9985                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data         9985                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total         9985                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    897271091                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    897271091                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    897271091                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    897271091                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.002355                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.002355                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000263                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.000263                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.001709                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.001709                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.001709                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.001709                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24680.810036                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 24680.810036                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 51141.055235                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 51141.055235                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 25936.489545                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 25936.489545                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 25936.489545                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 25936.489545                       # average overall miss latency
+system.cpu.dcache.tags.tag_accesses         759367050                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        759367050                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    249613198                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       249613198                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    128882154                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      128882154                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data         3481                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total          3481                       # number of SoftPFReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data         5739                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total         5739                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data         5739                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total         5739                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data     378495352                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        378495352                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    378498833                       # number of overall hits
+system.cpu.dcache.overall_hits::total       378498833                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       712681                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        712681                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data        69323                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total        69323                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data          139                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total          139                       # number of SoftPFReq misses
+system.cpu.dcache.demand_misses::cpu.data       782004                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total         782004                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data       782143                       # number of overall misses
+system.cpu.dcache.overall_misses::total        782143                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  18582698000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  18582698000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   3677152000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   3677152000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  22259850000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  22259850000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  22259850000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  22259850000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    250325879                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    250325879                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data    128951477                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total    128951477                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data         3620                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total         3620                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data         5739                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total         5739                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data         5739                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total         5739                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data    379277356                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    379277356                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    379280976                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    379280976                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.002847                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.002847                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000538                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.000538                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.038398                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.038398                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.002062                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.002062                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.002062                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.002062                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26074.355848                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 26074.355848                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53043.751713                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 53043.751713                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 28465.135728                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 28465.135728                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 28460.076994                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 28460.076994                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -510,60 +520,74 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks        96257                       # number of writebacks
-system.cpu.dcache.writebacks::total             96257                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1460873                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      1460873                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data        72780                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total        72780                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      1533653                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      1533653                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      1533653                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      1533653                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  33133783000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  33133783000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   3576486000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   3576486000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  36710269000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  36710269000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  36710269000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  36710269000                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.002355                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.002355                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000263                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000263                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.001709                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.001709                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.001709                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.001709                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22680.810036                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22680.810036                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49141.055235                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49141.055235                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23936.489545                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 23936.489545                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23936.489545                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 23936.489545                       # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks        91561                       # number of writebacks
+system.cpu.dcache.writebacks::total             91561                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data            1                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total            1                       # number of ReadReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data            1                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total            1                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data            1                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total            1                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       712680                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       712680                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data        69323                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total        69323                       # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data          139                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total          139                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       782003                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       782003                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       782142                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       782142                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  17157298000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  17157298000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   3538506000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   3538506000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data      1613000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total      1613000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  20695804000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  20695804000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  20697417000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  20697417000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.002847                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.002847                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000538                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000538                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.038398                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.038398                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.002062                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.002062                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.002062                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.002062                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24074.336308                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24074.336308                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51043.751713                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51043.751713                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 11604.316547                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 11604.316547                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26465.120978                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 26465.120978                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26462.479959                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 26462.479959                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.throughput                45389617                       # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq        1480676                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       1480676                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback        96257                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq        72780                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp        72780                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        39606                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      3163563                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           3203169                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1267392                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    104314240                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total      105581632                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus         105581632                       # Total data (bytes)
+system.cpu.toL2Bus.throughput                54201945                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq         723027                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp        723027                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback        91561                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq        69323                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp        69323                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        20416                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      1655845                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           1676261                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       653312                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     55916992                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total       56570304                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus          56570304                       # Total data (bytes)
 system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy      921113500                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy      29704500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.occupancy      533516500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy      15312000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    2300479500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    1173213000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt
index 5d39af8d6..57d7475f8 100644
--- a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt
@@ -1,75 +1,75 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.058331                       # Number of seconds simulated
-sim_ticks                                 58330740000                       # Number of ticks simulated
-final_tick                                58330740000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.058327                       # Number of seconds simulated
+sim_ticks                                 58326668000                       # Number of ticks simulated
+final_tick                                58326668000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 186275                       # Simulator instruction rate (inst/s)
-host_op_rate                                   186275                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              122860334                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 249156                       # Number of bytes of host memory used
-host_seconds                                   474.77                       # Real time elapsed on the host
+host_inst_rate                                 319236                       # Simulator instruction rate (inst/s)
+host_op_rate                                   319236                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              210542764                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 275532                       # Number of bytes of host memory used
+host_seconds                                   277.03                       # Real time elapsed on the host
 sim_insts                                    88438073                       # Number of instructions simulated
 sim_ops                                      88438073                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst          10662976                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             10662976                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       515264                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          515264                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7299200                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7299200                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst             166609                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                166609                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          114050                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               114050                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst            182802001                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               182802001                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         8833490                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            8833490                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks         125134706                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total              125134706                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks         125134706                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           182802001                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              307936707                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        166609                       # Number of read requests accepted
-system.physmem.writeReqs                       114050                       # Number of write requests accepted
-system.physmem.readBursts                      166609                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     114050                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 10662464                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                       512                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   7297728                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  10662976                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                7299200                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                        8                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytes_read::cpu.inst          10663104                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             10663104                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       515520                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          515520                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      7299072                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7299072                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst             166611                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                166611                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          114048                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               114048                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst            182816958                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               182816958                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         8838496                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            8838496                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks         125141248                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total              125141248                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks         125141248                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           182816958                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              307958205                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        166611                       # Number of read requests accepted
+system.physmem.writeReqs                       114048                       # Number of write requests accepted
+system.physmem.readBursts                      166611                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     114048                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 10662720                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                       384                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   7297088                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  10663104                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                7299072                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                        6                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               10471                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               10513                       # Per bank write bursts
+system.physmem.perBankRdBursts::0               10470                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               10514                       # Per bank write bursts
 system.physmem.perBankRdBursts::2               10311                       # Per bank write bursts
 system.physmem.perBankRdBursts::3               10091                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               10430                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               10425                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               10432                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               10426                       # Per bank write bursts
 system.physmem.perBankRdBursts::6                9845                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               10301                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               10592                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               10642                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              10594                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               10300                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               10593                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               10643                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              10596                       # Per bank write bursts
 system.physmem.perBankRdBursts::11              10255                       # Per bank write bursts
 system.physmem.perBankRdBursts::12              10302                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              10654                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              10651                       # Per bank write bursts
 system.physmem.perBankRdBursts::14              10528                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              10647                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              10648                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                7087                       # Per bank write bursts
 system.physmem.perBankWrBursts::1                7261                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                7256                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                7255                       # Per bank write bursts
 system.physmem.perBankWrBursts::3                6999                       # Per bank write bursts
 system.physmem.perBankWrBursts::4                7126                       # Per bank write bursts
 system.physmem.perBankWrBursts::5                7177                       # Per bank write bursts
 system.physmem.perBankWrBursts::6                6771                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                7089                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                7224                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                6941                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                7084                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                7221                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                6940                       # Per bank write bursts
 system.physmem.perBankWrBursts::10               7095                       # Per bank write bursts
 system.physmem.perBankWrBursts::11               6991                       # Per bank write bursts
 system.physmem.perBankWrBursts::12               6965                       # Per bank write bursts
@@ -78,24 +78,24 @@ system.physmem.perBankWrBursts::14               7284                       # Pe
 system.physmem.perBankWrBursts::15               7472                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                     58330713500                       # Total gap between requests
+system.physmem.totGap                     58326641500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  166609                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  166611                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 114050                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    164962                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      1611                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        28                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 114048                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    164954                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      1625                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        26                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
@@ -140,27 +140,27 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                      736                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                      758                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     6203                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     6988                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     7033                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     7035                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     7030                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     7041                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     7036                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     7062                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     7079                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     7087                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     7241                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     7129                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     7115                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                      730                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                      752                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     6187                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     6989                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     7028                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     7045                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     7025                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     7044                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     7045                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     7061                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     7078                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     7102                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     7263                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     7119                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     7114                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::30                     7354                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     7080                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     7023                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                        5                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     7066                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     7021                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                        7                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
@@ -189,113 +189,115 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        54540                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      329.285515                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     195.168705                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     332.681094                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          19405     35.58%     35.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        11848     21.72%     57.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         5629     10.32%     67.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3624      6.64%     74.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2728      5.00%     79.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         2044      3.75%     83.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1598      2.93%     85.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1491      2.73%     88.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         6173     11.32%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          54540                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          7020                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        23.731339                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      347.912038                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023           7019     99.99%     99.99% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples        54563                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      329.133809                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     195.314569                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     332.108035                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          19364     35.49%     35.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        11887     21.79%     57.28% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         5658     10.37%     67.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3635      6.66%     74.31% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2734      5.01%     79.32% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         2059      3.77%     83.09% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1592      2.92%     86.01% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1526      2.80%     88.81% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         6108     11.19%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          54563                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          7019                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        23.733438                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      348.155819                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023           7017     99.97%     99.97% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-2047            1      0.01%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::28672-29695            1      0.01%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            7020                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          7020                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        16.243162                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.227940                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        0.737137                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16               6260     89.17%     89.17% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17                 15      0.21%     89.39% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18                596      8.49%     97.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19                118      1.68%     99.56% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                 21      0.30%     99.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21                  7      0.10%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22                  1      0.01%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26                  1      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total            7019                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          7019                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.244052                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.228462                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        0.746507                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               6270     89.33%     89.33% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17                 11      0.16%     89.49% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18                572      8.15%     97.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19                129      1.84%     99.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                 27      0.38%     99.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                  6      0.09%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22                  1      0.01%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23                  1      0.01%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25                  1      0.01%     99.99% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::27                  1      0.01%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            7020                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     1961331500                       # Total ticks spent queuing
-system.physmem.totMemAccLat                5085100250                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    833005000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       11772.63                       # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::total            7019                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     1962392500                       # Total ticks spent queuing
+system.physmem.totMemAccLat                5086236250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    833025000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       11778.71                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  30522.63                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         182.79                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  30528.71                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         182.81                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                         125.11                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                      182.80                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                      125.13                       # Average system write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                      182.82                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                      125.14                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           2.41                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       1.43                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.98                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.01                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        23.77                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     144790                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     81289                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   86.91                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  71.27                       # Row buffer hit rate for writes
-system.physmem.avgGap                       207834.82                       # Average gap between requests
-system.physmem.pageHitRate                      80.56                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE      31870385750                       # Time in different power states
-system.physmem.memoryStateTime::REF        1947660000                       # Time in different power states
+system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        23.89                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     144808                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     81240                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   86.92                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  71.23                       # Row buffer hit rate for writes
+system.physmem.avgGap                       207820.31                       # Average gap between requests
+system.physmem.pageHitRate                      80.54                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE      31774168500                       # Time in different power states
+system.physmem.memoryStateTime::REF        1947400000                       # Time in different power states
 system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT       24509026750                       # Time in different power states
+system.physmem.memoryStateTime::ACT       24597717750                       # Time in different power states
 system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.membus.throughput                    307936707                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq               35729                       # Transaction distribution
-system.membus.trans_dist::ReadResp              35729                       # Transaction distribution
-system.membus.trans_dist::Writeback            114050                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            130880                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           130880                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       447268                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 447268                       # Packet count per connected master and slave (bytes)
+system.membus.throughput                    307958205                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq               35730                       # Transaction distribution
+system.membus.trans_dist::ReadResp              35730                       # Transaction distribution
+system.membus.trans_dist::Writeback            114048                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            130881                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           130881                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       447270                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 447270                       # Packet count per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     17962176                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size::total            17962176                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.data_through_bus               17962176                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy          1302300000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy          1302233000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               2.2                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         1600619750                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         1600678750                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              2.7                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.branchPred.lookups                14594378                       # Number of BP lookups
-system.cpu.branchPred.condPredicted           9449120                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            378858                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             10404778                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                 6369492                       # Number of BTB hits
+system.cpu.branchPred.lookups                14594840                       # Number of BP lookups
+system.cpu.branchPred.condPredicted           9449166                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            378473                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             10265774                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                 6368296                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             61.216991                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 1700724                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect              73182                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             62.034251                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 1700711                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect              73330                       # Number of incorrect RAS predictions.
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                     20554057                       # DTB read hits
-system.cpu.dtb.read_misses                      96859                       # DTB read misses
+system.cpu.dtb.read_hits                     20553993                       # DTB read hits
+system.cpu.dtb.read_misses                      96885                       # DTB read misses
 system.cpu.dtb.read_acv                             9                       # DTB read access violations
-system.cpu.dtb.read_accesses                 20650916                       # DTB read accesses
-system.cpu.dtb.write_hits                    14665861                       # DTB write hits
-system.cpu.dtb.write_misses                      9387                       # DTB write misses
+system.cpu.dtb.read_accesses                 20650878                       # DTB read accesses
+system.cpu.dtb.write_hits                    14665827                       # DTB write hits
+system.cpu.dtb.write_misses                      9394                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses                14675248                       # DTB write accesses
-system.cpu.dtb.data_hits                     35219918                       # DTB hits
-system.cpu.dtb.data_misses                     106246                       # DTB misses
+system.cpu.dtb.write_accesses                14675221                       # DTB write accesses
+system.cpu.dtb.data_hits                     35219820                       # DTB hits
+system.cpu.dtb.data_misses                     106279                       # DTB misses
 system.cpu.dtb.data_acv                             9                       # DTB access violations
-system.cpu.dtb.data_accesses                 35326164                       # DTB accesses
-system.cpu.itb.fetch_hits                    25539378                       # ITB hits
-system.cpu.itb.fetch_misses                      5182                       # ITB misses
+system.cpu.dtb.data_accesses                 35326099                       # DTB accesses
+system.cpu.itb.fetch_hits                    25536643                       # ITB hits
+system.cpu.itb.fetch_misses                      5175                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                25544560                       # ITB accesses
+system.cpu.itb.fetch_accesses                25541818                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -309,70 +311,70 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                 4583                       # Number of system calls
-system.cpu.numCycles                        116661480                       # number of cpu cycles simulated
+system.cpu.numCycles                        116653336                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                    88438073                       # Number of instructions committed
 system.cpu.committedOps                      88438073                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                       1184669                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps                       1184863                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                               1.319132                       # CPI: cycles per instruction
-system.cpu.ipc                               0.758074                       # IPC: instructions per cycle
-system.cpu.tickCycles                        90786920                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                        25874560                       # Total number of cycles that the object has spent stopped
-system.cpu.icache.tags.replacements            152636                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1933.709390                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            25384693                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs            154684                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs            164.106779                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle       41485931250                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1933.709390                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.944194                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.944194                       # Average percentage of cache occupancy
+system.cpu.cpi                               1.319040                       # CPI: cycles per instruction
+system.cpu.ipc                               0.758127                       # IPC: instructions per cycle
+system.cpu.tickCycles                        90780036                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                        25873300                       # Total number of cycles that the object has spent stopped
+system.cpu.icache.tags.replacements            152673                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1933.703122                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            25381921                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs            154721                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs            164.049618                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle       41483619250                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst  1933.703122                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.944191                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.944191                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         2048                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           52                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          155                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3         1042                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4          799                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           55                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          152                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3         1044                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4          797                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          51233440                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         51233440                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     25384693                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        25384693                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      25384693                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         25384693                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     25384693                       # number of overall hits
-system.cpu.icache.overall_hits::total        25384693                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst       154685                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total        154685                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst       154685                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total         154685                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst       154685                       # number of overall misses
-system.cpu.icache.overall_misses::total        154685                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst   2511936746                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total   2511936746                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst   2511936746                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total   2511936746                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst   2511936746                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total   2511936746                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     25539378                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     25539378                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     25539378                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     25539378                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     25539378                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     25539378                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.006057                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.006057                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.006057                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.006057                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.006057                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.006057                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16239.045454                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 16239.045454                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 16239.045454                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 16239.045454                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 16239.045454                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 16239.045454                       # average overall miss latency
+system.cpu.icache.tags.tag_accesses          51228007                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         51228007                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     25381921                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        25381921                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      25381921                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         25381921                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     25381921                       # number of overall hits
+system.cpu.icache.overall_hits::total        25381921                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst       154722                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total        154722                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst       154722                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total         154722                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst       154722                       # number of overall misses
+system.cpu.icache.overall_misses::total        154722                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst   2515300997                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total   2515300997                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst   2515300997                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total   2515300997                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst   2515300997                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total   2515300997                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     25536643                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     25536643                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     25536643                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     25536643                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     25536643                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     25536643                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.006059                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.006059                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.006059                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.006059                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.006059                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.006059                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16256.905915                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 16256.905915                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 16256.905915                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 16256.905915                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 16256.905915                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 16256.905915                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -381,123 +383,123 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst       154685                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total       154685                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst       154685                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total       154685                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst       154685                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total       154685                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   2199492254                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total   2199492254                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst   2199492254                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total   2199492254                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst   2199492254                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total   2199492254                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.006057                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.006057                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.006057                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.006057                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.006057                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.006057                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14219.169629                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14219.169629                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14219.169629                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 14219.169629                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14219.169629                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 14219.169629                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst       154722                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total       154722                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst       154722                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total       154722                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst       154722                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total       154722                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   2202760003                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total   2202760003                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst   2202760003                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total   2202760003                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst   2202760003                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total   2202760003                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.006059                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.006059                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.006059                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.006059                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.006059                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.006059                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14236.889408                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14236.889408                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14236.889408                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 14236.889408                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14236.889408                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 14236.889408                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.throughput               579413736                       # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq         215991                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp        215990                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback       168535                       # Transaction distribution
+system.cpu.toL2Bus.throughput               579498078                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq         216032                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp        216031                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback       168534                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq       143563                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp       143563                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       309369                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       578273                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total            887642                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      9899776                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     23897856                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total       33797632                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus          33797632                       # Total data (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       309443                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       578280                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total            887723                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      9902144                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     23898048                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total       33800192                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus          33800192                       # Total data (bytes)
 system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy      432579500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.occupancy      432598500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.7                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy     233564246                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy     233630997                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.4                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy     343185250                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy     343195750                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.6                       # Layer utilization (%)
-system.cpu.l2cache.tags.replacements           132686                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        30472.865320                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs             219503                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           164761                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             1.332251                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements           132688                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        30472.596016                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs             219541                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           164763                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             1.332465                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 26247.009665                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  4225.855654                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.800995                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.128963                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.929958                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::writebacks 26246.298923                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  4226.297093                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.800973                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.128976                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.929950                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024        32075                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          125                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1         1028                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2        11972                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3        18837                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4          113                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          126                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1         1030                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2        11966                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3        18841                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4          112                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.978851                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses          4533036                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses         4533036                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst       180261                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total         180261                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks       168535                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total       168535                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.inst        12683                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total        12683                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst       192944                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total          192944                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst       192944                       # number of overall hits
-system.cpu.l2cache.overall_hits::total         192944                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst        35730                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total        35730                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.inst       130880                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       130880                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst       166610                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        166610                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst       166610                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       166610                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst   2607479500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total   2607479500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst   9666800250                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   9666800250                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst  12274279750                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  12274279750                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst  12274279750                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  12274279750                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst       215991                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total       215991                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks       168535                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total       168535                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.tags.tag_accesses          4533358                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses         4533358                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.inst       180301                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total         180301                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks       168534                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total       168534                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.inst        12682                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total        12682                       # number of ReadExReq hits
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+system.cpu.l2cache.overall_misses::total       166612                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst   2608847500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total   2608847500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst   9666752250                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   9666752250                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst  12275599750                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  12275599750                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst  12275599750                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  12275599750                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst       216032                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total       216032                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks       168534                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total       168534                       # number of Writeback accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.inst       143563                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total       143563                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst       359554                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total       359554                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst       359554                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total       359554                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.165424                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.165424                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst     0.911656                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.911656                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.463380                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.463380                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.463380                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.463380                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72977.315981                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 72977.315981                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 73860.026360                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73860.026360                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73670.726547                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 73670.726547                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73670.726547                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 73670.726547                       # average overall miss latency
+system.cpu.l2cache.demand_accesses::cpu.inst       359595                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total       359595                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst       359595                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total       359595                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.165397                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.165397                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst     0.911662                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.911662                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.463332                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.463332                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.463332                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.463332                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73013.559654                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 73013.559654                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 73859.095285                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73859.095285                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73677.764807                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 73677.764807                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73677.764807                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 73677.764807                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -506,105 +508,105 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks       114050                       # number of writebacks
-system.cpu.l2cache.writebacks::total           114050                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        35730                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total        35730                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst       130880                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       130880                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst       166610                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       166610                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst       166610                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       166610                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst   2154391500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total   2154391500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst   7982023250                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   7982023250                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst  10136414750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  10136414750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst  10136414750                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  10136414750                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.165424                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.165424                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst     0.911656                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.911656                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.463380                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.463380                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.463380                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.463380                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60296.431570                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60296.431570                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 60987.341458                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60987.341458                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60839.173819                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60839.173819                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60839.173819                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60839.173819                       # average overall mshr miss latency
+system.cpu.l2cache.writebacks::writebacks       114048                       # number of writebacks
+system.cpu.l2cache.writebacks::total           114048                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        35731                       # number of ReadReq MSHR misses
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+system.cpu.l2cache.ReadExReq_mshr_misses::total       130881                       # number of ReadExReq MSHR misses
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+system.cpu.l2cache.overall_mshr_misses::total       166612                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst   2155704000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total   2155704000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst   7981949750                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   7981949750                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst  10137653750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  10137653750                       # number of demand (read+write) MSHR miss cycles
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+system.cpu.l2cache.overall_mshr_miss_latency::total  10137653750                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.165397                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.165397                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst     0.911662                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.911662                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.463332                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.463332                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.463332                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.463332                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60331.476869                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60331.476869                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 60986.313903                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60986.313903                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60845.879949                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60845.879949                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60845.879949                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60845.879949                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements            200773                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4071.422788                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            34597432                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs            204869                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            168.875877                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.replacements            200777                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4071.421073                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            34597319                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            204873                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs            168.872028                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle         644670250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.inst  4071.422788                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.inst     0.994000                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.994000                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.inst  4071.421073                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.inst     0.993999                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.993999                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           52                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          752                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2         3292                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           53                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          754                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2         3289                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          70138775                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         70138775                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.inst     20264167                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        20264167                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.inst     14333265                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       14333265                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.inst      34597432                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         34597432                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.inst     34597432                       # number of overall hits
-system.cpu.dcache.overall_hits::total        34597432                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.inst        89409                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total         89409                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.inst       280112                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       280112                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.inst       369521                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total         369521                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.inst       369521                       # number of overall misses
-system.cpu.dcache.overall_misses::total        369521                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.inst   4415904250                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total   4415904250                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.inst  20008402750                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  20008402750                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.inst  24424307000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  24424307000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.inst  24424307000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  24424307000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.inst     20353576                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     20353576                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.tags.tag_accesses          70138517                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         70138517                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.inst     20264045                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        20264045                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.inst     14333274                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       14333274                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.inst      34597319                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         34597319                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.inst     34597319                       # number of overall hits
+system.cpu.dcache.overall_hits::total        34597319                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.inst        89400                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total         89400                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.inst       280103                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       280103                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.inst       369503                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total         369503                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.inst       369503                       # number of overall misses
+system.cpu.dcache.overall_misses::total        369503                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.inst   4413515000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total   4413515000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.inst  20003600250                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  20003600250                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.inst  24417115250                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  24417115250                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.inst  24417115250                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  24417115250                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.inst     20353445                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     20353445                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.inst     14613377                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     14613377                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.inst     34966953                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     34966953                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.inst     34966953                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     34966953                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.inst     0.004393                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.004393                       # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.inst     34966822                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     34966822                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.inst     34966822                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     34966822                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.inst     0.004392                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.004392                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.inst     0.019168                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_miss_rate::total     0.019168                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.inst     0.010568                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.010568                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.inst     0.010568                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.010568                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 49389.929985                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 49389.929985                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 71430.009246                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 71430.009246                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66097.209631                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 66097.209631                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66097.209631                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 66097.209631                       # average overall miss latency
+system.cpu.dcache.demand_miss_rate::cpu.inst     0.010567                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.010567                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.inst     0.010567                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.010567                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 49368.176734                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 49368.176734                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 71415.158888                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 71415.158888                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66080.966190                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 66080.966190                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66080.966190                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 66080.966190                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -613,32 +615,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       168535                       # number of writebacks
-system.cpu.dcache.writebacks::total            168535                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.inst        28102                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total        28102                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.inst       136550                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       136550                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.inst       164652                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       164652                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.inst       164652                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       164652                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.inst        61307                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total        61307                       # number of ReadReq MSHR misses
+system.cpu.dcache.writebacks::writebacks       168534                       # number of writebacks
+system.cpu.dcache.writebacks::total            168534                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.inst        28089                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total        28089                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.inst       136541                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       136541                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.inst       164630                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       164630                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.inst       164630                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       164630                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.inst        61311                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total        61311                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.inst       143562                       # number of WriteReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::total       143562                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.inst       204869                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       204869                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.inst       204869                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       204869                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst   2427134250                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   2427134250                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst   9937233500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   9937233500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.inst  12364367750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  12364367750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.inst  12364367750                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  12364367750                       # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_misses::cpu.inst       204873                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       204873                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.inst       204873                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       204873                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst   2425671500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   2425671500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst   9937173250                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   9937173250                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.inst  12362844750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  12362844750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.inst  12362844750                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  12362844750                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst     0.003012                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.003012                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst     0.009824                       # mshr miss rate for WriteReq accesses
@@ -647,14 +649,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.inst     0.005859
 system.cpu.dcache.demand_mshr_miss_rate::total     0.005859                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.inst     0.005859                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.005859                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 39589.838844                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 39589.838844                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 69219.107424                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69219.107424                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 60352.555780                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 60352.555780                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 60352.555780                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 60352.555780                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 39563.398085                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 39563.398085                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 69218.687745                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69218.687745                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 60343.943565                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 60343.943565                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 60343.943565                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 60343.943565                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
index 356c37c90..31507e486 100644
--- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,109 +1,109 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.024221                       # Number of seconds simulated
-sim_ticks                                 24220559500                       # Number of ticks simulated
-final_tick                                24220559500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.022262                       # Number of seconds simulated
+sim_ticks                                 22262172500                       # Number of ticks simulated
+final_tick                                22262172500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 196594                       # Simulator instruction rate (inst/s)
-host_op_rate                                   196594                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               59825545                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 231620                       # Number of bytes of host memory used
-host_seconds                                   404.85                       # Real time elapsed on the host
+host_inst_rate                                 164105                       # Simulator instruction rate (inst/s)
+host_op_rate                                   164105                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               45900767                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 245260                       # Number of bytes of host memory used
+host_seconds                                   485.01                       # Real time elapsed on the host
 sim_insts                                    79591756                       # Number of instructions simulated
 sim_ops                                      79591756                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            490880                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          10153984                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             10644864                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       490880                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          490880                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7297024                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7297024                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               7670                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             158656                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                166326                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          114016                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               114016                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst             20267079                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            419229952                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               439497031                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst        20267079                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total           20267079                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks         301273965                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total              301273965                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks         301273965                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst            20267079                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           419229952                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              740770997                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        166326                       # Number of read requests accepted
-system.physmem.writeReqs                       114016                       # Number of write requests accepted
-system.physmem.readBursts                      166326                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     114016                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 10644288                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                       576                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   7295168                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  10644864                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                7297024                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                        9                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytes_read::cpu.inst            487296                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          10152448                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             10639744                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       487296                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          487296                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      7297472                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7297472                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               7614                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             158632                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                166246                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          114023                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               114023                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst             21888969                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            456040308                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               477929277                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst        21888969                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total           21888969                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks         327796939                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total              327796939                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks         327796939                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst            21888969                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           456040308                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              805726216                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        166246                       # Number of read requests accepted
+system.physmem.writeReqs                       114023                       # Number of write requests accepted
+system.physmem.readBursts                      166246                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     114023                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 10639232                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                       512                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   7295808                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  10639744                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                7297472                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                        8                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               10433                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               10462                       # Per bank write bursts
+system.physmem.perBankRdBursts::0               10440                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               10463                       # Per bank write bursts
 system.physmem.perBankRdBursts::2               10311                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               10058                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               10424                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               10410                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                9846                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               10316                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               10611                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               10645                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              10555                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              10230                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              10281                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              10621                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              10488                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              10626                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               10061                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               10417                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               10395                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                9841                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               10308                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               10597                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               10638                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              10546                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              10227                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              10273                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              10619                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              10481                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              10621                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                7082                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                7257                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                7258                       # Per bank write bursts
 system.physmem.perBankWrBursts::2                7255                       # Per bank write bursts
 system.physmem.perBankWrBursts::3                6997                       # Per bank write bursts
 system.physmem.perBankWrBursts::4                7126                       # Per bank write bursts
 system.physmem.perBankWrBursts::5                7170                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                6772                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                7086                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                7220                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                6941                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               7083                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               6989                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               6964                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                6776                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                7085                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                7222                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                6942                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               7084                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               6990                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               6966                       # Per bank write bursts
 system.physmem.perBankWrBursts::13               7288                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               7285                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               7284                       # Per bank write bursts
 system.physmem.perBankWrBursts::15               7472                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                     24220526000                       # Total gap between requests
+system.physmem.totGap                     22262139000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  166326                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  166246                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 114016                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                     68881                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     45477                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     37755                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                     14195                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                         8                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 114023                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                     51670                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     53911                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     45458                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                     15180                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                        15                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                         3                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
@@ -144,33 +144,33 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                      846                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                      893                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     2119                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     3043                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     4983                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     6109                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     6450                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     6771                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     7076                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     7439                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     7786                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     8078                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     8708                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     9322                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     8469                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     8647                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     8533                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     7930                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      350                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      195                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      126                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                       96                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                       26                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                        3                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                      839                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                      879                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     1392                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     2489                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     4591                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     5919                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     6398                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     6763                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     7095                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     7509                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     7936                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     8302                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     8984                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     9696                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     8624                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     8779                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     8776                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     8045                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      453                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      263                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      156                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                       80                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                       34                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                        6                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
@@ -193,116 +193,115 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        52493                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      341.720229                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     200.667520                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     342.624937                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          18531     35.30%     35.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        10783     20.54%     55.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         5620     10.71%     66.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3233      6.16%     72.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2663      5.07%     77.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1771      3.37%     81.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1746      3.33%     84.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1279      2.44%     86.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         6867     13.08%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          52493                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          6963                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        23.883814                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      342.440327                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023           6961     99.97%     99.97% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-2047            1      0.01%     99.99% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples        52156                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      343.855817                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     201.745106                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     344.281593                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          18285     35.06%     35.06% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        10756     20.62%     55.68% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         5580     10.70%     66.38% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3146      6.03%     72.41% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2660      5.10%     77.51% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1727      3.31%     80.82% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1787      3.43%     84.25% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1244      2.39%     86.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         6971     13.37%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          52156                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          6968                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        23.856056                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      342.059287                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023           6967     99.99%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::27648-28671            1      0.01%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            6963                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          6963                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        16.370386                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.340039                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        1.063738                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16               6043     86.79%     86.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17                 33      0.47%     87.26% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18                485      6.97%     94.23% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19                209      3.00%     97.23% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                 93      1.34%     98.56% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21                 61      0.88%     99.44% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22                 21      0.30%     99.74% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23                  6      0.09%     99.83% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total            6968                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          6968                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.360075                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.330777                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        1.045922                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               6065     87.04%     87.04% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17                 29      0.42%     87.46% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18                476      6.83%     94.29% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19                227      3.26%     97.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                 92      1.32%     98.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                 39      0.56%     99.43% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22                 17      0.24%     99.67% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23                 11      0.16%     99.83% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::24                  8      0.11%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::25                  2      0.03%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::27                  2      0.03%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            6963                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     4923415500                       # Total ticks spent queuing
-system.physmem.totMemAccLat                8041859250                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    831585000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       29602.60                       # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::25                  3      0.04%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::30                  1      0.01%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            6968                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     5413019750                       # Total ticks spent queuing
+system.physmem.totMemAccLat                8529982250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    831190000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       32561.87                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  48352.60                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         439.47                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                         301.20                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                      439.50                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                      301.27                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  51311.87                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         477.91                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                         327.72                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                      477.93                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                      327.80                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           5.79                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       3.43                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      2.35                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.71                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        24.54                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     145967                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     81830                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   87.76                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  71.77                       # Row buffer hit rate for writes
-system.physmem.avgGap                        86396.35                       # Average gap between requests
-system.physmem.pageHitRate                      81.26                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE      10036891500                       # Time in different power states
-system.physmem.memoryStateTime::REF         808600000                       # Time in different power states
+system.physmem.busUtil                           6.29                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       3.73                       # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite                      2.56                       # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen                         1.80                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        24.52                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     146096                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     81976                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   87.88                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  71.89                       # Row buffer hit rate for writes
+system.physmem.avgGap                        79431.33                       # Average gap between requests
+system.physmem.pageHitRate                      81.38                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE       9551525000                       # Time in different power states
+system.physmem.memoryStateTime::REF         743340000                       # Time in different power states
 system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT       13370021250                       # Time in different power states
+system.physmem.memoryStateTime::ACT       11966317750                       # Time in different power states
 system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.membus.throughput                    740770997                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq               35544                       # Transaction distribution
-system.membus.trans_dist::ReadResp              35544                       # Transaction distribution
-system.membus.trans_dist::Writeback            114016                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            130782                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           130782                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       446668                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 446668                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     17941888                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total            17941888                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus               17941888                       # Total data (bytes)
+system.membus.throughput                    805726216                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq               35460                       # Transaction distribution
+system.membus.trans_dist::ReadResp              35460                       # Transaction distribution
+system.membus.trans_dist::Writeback            114023                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            130786                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           130786                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       446515                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 446515                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     17937216                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total            17937216                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus               17937216                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy          1251548500                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               5.2                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         1536730000                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              6.3                       # Layer utilization (%)
+system.membus.reqLayer0.occupancy          1235956000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               5.6                       # Layer utilization (%)
+system.membus.respLayer1.occupancy         1525146000                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization              6.9                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.branchPred.lookups                16751824                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          10815024                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            427504                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             12114862                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                 7449714                       # Number of BTB hits
+system.cpu.branchPred.lookups                16618538                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          10751969                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            360716                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             10752045                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                 7371197                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             61.492355                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 2011177                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect              42536                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             68.556233                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 1990414                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect               2895                       # Number of incorrect RAS predictions.
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                     22508658                       # DTB read hits
-system.cpu.dtb.read_misses                     223827                       # DTB read misses
-system.cpu.dtb.read_acv                            56                       # DTB read access violations
-system.cpu.dtb.read_accesses                 22732485                       # DTB read accesses
-system.cpu.dtb.write_hits                    15810202                       # DTB write hits
-system.cpu.dtb.write_misses                     43571                       # DTB write misses
-system.cpu.dtb.write_acv                            3                       # DTB write access violations
-system.cpu.dtb.write_accesses                15853773                       # DTB write accesses
-system.cpu.dtb.data_hits                     38318860                       # DTB hits
-system.cpu.dtb.data_misses                     267398                       # DTB misses
-system.cpu.dtb.data_acv                            59                       # DTB access violations
-system.cpu.dtb.data_accesses                 38586258                       # DTB accesses
-system.cpu.itb.fetch_hits                    14110575                       # ITB hits
-system.cpu.itb.fetch_misses                     33841                       # ITB misses
+system.cpu.dtb.read_hits                     22632838                       # DTB read hits
+system.cpu.dtb.read_misses                     226204                       # DTB read misses
+system.cpu.dtb.read_acv                            19                       # DTB read access violations
+system.cpu.dtb.read_accesses                 22859042                       # DTB read accesses
+system.cpu.dtb.write_hits                    15863725                       # DTB write hits
+system.cpu.dtb.write_misses                     44788                       # DTB write misses
+system.cpu.dtb.write_acv                            4                       # DTB write access violations
+system.cpu.dtb.write_accesses                15908513                       # DTB write accesses
+system.cpu.dtb.data_hits                     38496563                       # DTB hits
+system.cpu.dtb.data_misses                     270992                       # DTB misses
+system.cpu.dtb.data_acv                            23                       # DTB access violations
+system.cpu.dtb.data_accesses                 38767555                       # DTB accesses
+system.cpu.itb.fetch_hits                    13910081                       # ITB hits
+system.cpu.itb.fetch_misses                     31577                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                14144416                       # ITB accesses
+system.cpu.itb.fetch_accesses                13941658                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -316,239 +315,240 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                 4583                       # Number of system calls
-system.cpu.numCycles                         48441123                       # number of cpu cycles simulated
+system.cpu.numCycles                         44524349                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           15991541                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      106726758                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    16751824                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches            9460891                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      19798045                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 2119165                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles                5548537                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                 5780                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles        330003                       # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles           61                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                  14110575                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                235048                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples           43228418                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.468903                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.149982                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles           15777207                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      106088567                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    16618538                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches            9361611                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      27200271                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                  960062                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles                        179                       # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles                 5019                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles        332851                       # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles           57                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                  13910081                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                206082                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes                       1                       # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples           43795615                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.422356                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.133763                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 23430373     54.20%     54.20% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  1549768      3.59%     57.79% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  1389630      3.21%     61.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  1530327      3.54%     64.54% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  4182492      9.68%     74.22% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  1877886      4.34%     78.56% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                   686601      1.59%     80.15% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  1082983      2.51%     82.65% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                  7498358     17.35%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 24068312     54.96%     54.96% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  1538186      3.51%     58.47% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  1404705      3.21%     61.68% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  1522843      3.48%     65.15% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  4236021      9.67%     74.82% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  1845751      4.21%     79.04% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                   684777      1.56%     80.60% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  1069219      2.44%     83.04% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                  7425801     16.96%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total             43228418                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.345818                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        2.203226                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 16783976                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles               5410543                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  19277752                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles                307681                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                1448466                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved              3794458                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                108182                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              104881075                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                317541                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                1448466                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 17188880                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                 4589733                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles          87878                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  19270658                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles                642803                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              103574244                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                  2041                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                 123118                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                 133246                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                 383447                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands            62411257                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             124921798                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        124593189                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups            328608                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total             43795615                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.373246                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        2.382709                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 15090251                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles               9271065                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  18462331                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles                590423                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                 381545                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              3739004                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                100344                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              103984343                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                314766                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                 381545                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 15473555                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                 6415386                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles          96680                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  18647393                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles               2781056                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              102842787                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                  3945                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                 148156                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                 330502                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents                2246834                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands            61884966                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             124097859                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        123771677                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups            326181                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps              52546881                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                  9864376                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts               5611                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts           5609                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                   1424158                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             23418596                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            16455537                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           1234609                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores           506012                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                   91610357                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                5443                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                  89041530                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            152798                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        11549535                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined      5161371                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved            860                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples      43228418                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         2.059792                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        2.166400                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                  9338085                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts               5769                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts           5827                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                   2465534                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             23256981                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            16451468                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           1256796                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores           554193                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                   91273922                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                5644                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                  89085619                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued             78698                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        11197079                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined      4703509                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved           1061                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples      43795615                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         2.034122                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        2.247476                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            16020950     37.06%     37.06% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1             5899567     13.65%     50.71% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2             5167698     11.95%     62.66% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3             4624013     10.70%     73.36% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4             4881657     11.29%     84.65% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             2705075      6.26%     90.91% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             2091187      4.84%     95.75% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7             1370765      3.17%     98.92% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              467506      1.08%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            17182377     39.23%     39.23% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1             5792116     13.23%     52.46% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2             5098261     11.64%     64.10% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3             4417263     10.09%     74.19% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             4344645      9.92%     84.11% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             2649252      6.05%     90.15% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             1946446      4.44%     94.60% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             1380364      3.15%     97.75% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              984891      2.25%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total        43228418                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total        43795615                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                  122844      6.34%      6.34% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%      6.34% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      6.34% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      6.34% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      6.34% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      6.34% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      6.34% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      6.34% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      6.34% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      6.34% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      6.34% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      6.34% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      6.34% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      6.34% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      6.34% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      6.34% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      6.34% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      6.34% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      6.34% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      6.34% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      6.34% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      6.34% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      6.34% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      6.34% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      6.34% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      6.34% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      6.34% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      6.34% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      6.34% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                 826331     42.62%     48.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                989497     51.04%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  244209      9.65%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                1174646     46.40%     56.05% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               1112477     43.95%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu              49689736     55.81%     55.81% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                43878      0.05%     55.85% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     55.85% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd              121254      0.14%     55.99% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                  89      0.00%     55.99% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt              121079      0.14%     56.13% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                 57      0.00%     56.13% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv               38922      0.04%     56.17% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     56.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     56.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     56.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     56.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     56.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     56.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     56.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     56.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     56.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     56.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     56.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     56.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     56.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     56.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     56.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     56.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     56.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     56.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     56.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     56.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     56.17% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             22993595     25.82%     81.99% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            16032920     18.01%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu              49643458     55.73%     55.73% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                44096      0.05%     55.78% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     55.78% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd              121526      0.14%     55.91% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                  89      0.00%     55.91% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt              121394      0.14%     56.05% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                 58      0.00%     56.05% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv               39070      0.04%     56.09% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     56.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     56.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     56.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     56.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     56.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     56.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     56.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     56.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     56.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     56.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     56.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     56.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     56.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     56.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     56.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     56.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     56.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     56.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     56.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     56.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     56.09% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             23048961     25.87%     81.96% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            16066967     18.04%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total               89041530                       # Type of FU issued
-system.cpu.iq.rate                           1.838139                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     1938672                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.021773                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          222789760                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         102752204                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses     87020411                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads              613188                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes             432642                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses       299262                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses               90673556                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                  306646                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads          1613513                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total               89085619                       # Type of FU issued
+system.cpu.iq.rate                           2.000829                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     2531332                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.028415                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          223962824                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         102066580                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses     87151859                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads              614059                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes             431019                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses       300727                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses               91309756                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                  307195                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads          1661224                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      3141958                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses         5326                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        19773                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      1842160                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      2980343                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses         6431                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        21452                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      1838091                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads         3009                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked        163446                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads         2952                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked        325709                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                1448466                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                 3237152                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles               1283757                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           101157149                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            209803                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              23418596                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             16455537                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts               5443                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                  41968                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents               1233080                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          19773                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         207340                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       162214                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts               369554                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts              88099058                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              22735868                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts            942472                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                 381545                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 1215876                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles               4878836                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           100803158                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            157110                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts              23256981                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             16451468                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts               5576                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                   3364                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents               4856172                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          21452                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         149650                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       157694                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts               307344                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts              88311132                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              22859779                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts            774487                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                       9541349                       # number of nop insts executed
-system.cpu.iew.exec_refs                     38590030                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 15163094                       # Number of branches executed
-system.cpu.iew.exec_stores                   15854162                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.818683                       # Inst execution rate
-system.cpu.iew.wb_sent                       87723103                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                      87319673                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                  33922471                       # num instructions producing a value
-system.cpu.iew.wb_consumers                  44377340                       # num instructions consuming a value
+system.cpu.iew.exec_nop                       9523592                       # number of nop insts executed
+system.cpu.iew.exec_refs                     38768607                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 15170240                       # Number of branches executed
+system.cpu.iew.exec_stores                   15908828                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.983435                       # Inst execution rate
+system.cpu.iew.wb_sent                       87867079                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                      87452586                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                  33893139                       # num instructions producing a value
+system.cpu.iew.wb_consumers                  44339625                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.802594                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.764410                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.964152                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.764398                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts         9580594                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts         9260506                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls            4583                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            321519                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples     41779952                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     2.114427                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.873182                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts            262230                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples     42432313                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     2.081920                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.885099                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     19839464     47.49%     47.49% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1      6575552     15.74%     63.22% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2      3029914      7.25%     70.48% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      1889529      4.52%     75.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      1770667      4.24%     79.24% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      1150899      2.75%     81.99% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      1116698      2.67%     84.66% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7       758478      1.82%     86.48% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      5648751     13.52%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     20891279     49.23%     49.23% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1      6327574     14.91%     64.15% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      2939948      6.93%     71.08% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      1761291      4.15%     75.23% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      1656008      3.90%     79.13% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      1140180      2.69%     81.82% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      1204228      2.84%     84.65% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       795411      1.87%     86.53% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      5716394     13.47%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total     41779952                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total     42432313                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts             88340672                       # Number of instructions committed
 system.cpu.commit.committedOps               88340672                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -560,10 +560,10 @@ system.cpu.commit.fp_insts                     267754                       # Nu
 system.cpu.commit.int_insts                  77942044                       # Number of committed integer instructions.
 system.cpu.commit.function_calls              1661057                       # Number of function calls committed.
 system.cpu.commit.op_class_0::No_OpClass      8748916      9.90%      9.90% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu         44395413     50.25%     60.16% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu         44394798     50.25%     60.16% # Class of committed instruction
 system.cpu.commit.op_class_0::IntMult           41101      0.05%     60.20% # Class of committed instruction
 system.cpu.commit.op_class_0::IntDiv                0      0.00%     60.20% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatAdd         113689      0.13%     60.33% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatAdd         114304      0.13%     60.33% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatCmp             84      0.00%     60.33% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatCvt         113640      0.13%     60.46% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatMult            50      0.00%     60.46% # Class of committed instruction
@@ -594,229 +594,229 @@ system.cpu.commit.op_class_0::MemWrite       14613377     16.54%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total          88340672                       # Class of committed instruction
-system.cpu.commit.bw_lim_events               5648751                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events               5716394                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                    132735125                       # The number of ROB reads
-system.cpu.rob.rob_writes                   197294055                       # The number of ROB writes
-system.cpu.timesIdled                           86991                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                         5212705                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads                    132999755                       # The number of ROB reads
+system.cpu.rob.rob_writes                   196569210                       # The number of ROB writes
+system.cpu.timesIdled                           47704                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                          728734                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                    79591756                       # Number of Instructions Simulated
 system.cpu.committedOps                      79591756                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               0.608620                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.608620                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.643062                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.643062                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                116607971                       # number of integer regfile reads
-system.cpu.int_regfile_writes                57833573                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                    254535                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                   240366                       # number of floating regfile writes
-system.cpu.misc_regfile_reads                   38019                       # number of misc regfile reads
+system.cpu.cpi                               0.559409                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.559409                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.787601                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.787601                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                116880103                       # number of integer regfile reads
+system.cpu.int_regfile_writes                57914968                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                    255764                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                   241194                       # number of floating regfile writes
+system.cpu.misc_regfile_reads                   38207                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
-system.cpu.toL2Bus.throughput              1241063981                       # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq         157229                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp        157228                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback       169024                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       143424                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       143424                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       189945                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       580384                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total            770329                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      6078208                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     23981056                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total       30059264                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus          30059264                       # Total data (bytes)
+system.cpu.toL2Bus.throughput              1351038673                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq         157664                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp        157663                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback       168884                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       143407                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       143407                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       191277                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       579748                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total            771025                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      6120832                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     23956224                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total       30077056                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus          30077056                       # Total data (bytes)
 system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy      403862500                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          1.7                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy     143810707                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          0.6                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy     325706997                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          1.3                       # Layer utilization (%)
-system.cpu.icache.tags.replacements             92924                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1926.308876                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            14002846                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs             94972                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs            147.441835                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle       19458186000                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1926.308876                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.940581                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.940581                       # Average percentage of cache occupancy
+system.cpu.toL2Bus.reqLayer0.occupancy      403861500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          1.8                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy     144811965                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization          0.7                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy     321850746                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization          1.4                       # Layer utilization (%)
+system.cpu.icache.tags.replacements             93590                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1918.549362                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            13801419                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs             95638                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs            144.308946                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle       18781387250                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst  1918.549362                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.936792                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.936792                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         2048                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           76                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1           83                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2            1                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3         1533                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4          355                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           78                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           88                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2           26                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3         1479                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4          377                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          28316122                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         28316122                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     14002846                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        14002846                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      14002846                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         14002846                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     14002846                       # number of overall hits
-system.cpu.icache.overall_hits::total        14002846                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst       107729                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total        107729                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst       107729                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total         107729                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst       107729                       # number of overall misses
-system.cpu.icache.overall_misses::total        107729                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst   1994925704                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total   1994925704                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst   1994925704                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total   1994925704                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst   1994925704                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total   1994925704                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     14110575                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     14110575                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     14110575                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     14110575                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     14110575                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     14110575                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.007635                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.007635                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.007635                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.007635                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.007635                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.007635                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18518.000761                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 18518.000761                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 18518.000761                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 18518.000761                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 18518.000761                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 18518.000761                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs          484                       # number of cycles access was blocked
+system.cpu.icache.tags.tag_accesses          27915798                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         27915798                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     13801419                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        13801419                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      13801419                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         13801419                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     13801419                       # number of overall hits
+system.cpu.icache.overall_hits::total        13801419                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst       108661                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total        108661                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst       108661                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total         108661                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst       108661                       # number of overall misses
+system.cpu.icache.overall_misses::total        108661                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst   2007129462                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total   2007129462                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst   2007129462                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total   2007129462                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst   2007129462                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total   2007129462                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     13910080                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     13910080                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     13910080                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     13910080                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     13910080                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     13910080                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.007812                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.007812                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.007812                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.007812                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.007812                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.007812                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18471.479758                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 18471.479758                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 18471.479758                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 18471.479758                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 18471.479758                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 18471.479758                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs          421                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                21                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 8                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    23.047619                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    52.625000                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst        12756                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total        12756                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst        12756                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total        12756                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst        12756                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total        12756                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst        94973                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total        94973                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst        94973                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total        94973                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst        94973                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total        94973                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   1539030293                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total   1539030293                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst   1539030293                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total   1539030293                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst   1539030293                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total   1539030293                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.006731                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.006731                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.006731                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.006731                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.006731                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.006731                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16204.924484                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16204.924484                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16204.924484                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 16204.924484                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16204.924484                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 16204.924484                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst        13022                       # number of ReadReq MSHR hits
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+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.006876                       # mshr miss rate for ReadReq accesses
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+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16179.064346                       # average ReadReq mshr miss latency
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+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16179.064346                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 16179.064346                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements           132416                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        30678.676989                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs             161509                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           164481                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             0.981931                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements           132342                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        30650.396196                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs             161877                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           164409                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             0.984599                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 26301.675025                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  2114.771932                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  2262.230032                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.802663                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.064538                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.069038                       # Average percentage of cache occupancy
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-system.cpu.l2cache.tags.occ_task_id_blocks::1024        32065                       # Occupied blocks per task id
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-system.cpu.l2cache.tags.age_task_id_blocks_1024::1         1465                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2        18112                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3        12251                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4           62                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.978546                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses          4065321                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses         4065321                       # Number of data accesses
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-system.cpu.l2cache.ReadReq_hits::total         121684                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks       169024                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total       169024                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data        12642                       # number of ReadExReq hits
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-system.cpu.l2cache.Writeback_accesses::writebacks       169024                       # number of Writeback accesses(hits+misses)
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-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 99709.432491                       # average ReadExReq miss latency
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-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 95249.314555                       # average overall miss latency
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-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 95249.314555                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 94286.017904                       # average overall miss latency
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+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 94079.266322                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 89977.080455                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 99886.205328                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 99886.205328                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74976.493762                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 98866.864819                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 97772.558302                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74976.493762                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 98866.864819                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 97772.558302                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -825,171 +825,187 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks       114016                       # number of writebacks
-system.cpu.l2cache.writebacks::total           114016                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         7671                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        27874                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total        35545                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       130782                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       130782                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         7671                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       158656                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       166327                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         7671                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       158656                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       166327                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    473528250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   1715909250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total   2189437500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  11438645000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  11438645000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    473528250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  13154554250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  13628082500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    473528250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  13154554250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  13628082500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.080770                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.447732                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.226072                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.911856                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.911856                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.080770                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.771373                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.553219                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.080770                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.771373                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.553219                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61729.663668                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61559.490923                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61596.216064                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 87463.450628                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 87463.450628                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61729.663668                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 82912.428462                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 81935.479507                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61729.663668                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 82912.428462                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 81935.479507                       # average overall mshr miss latency
+system.cpu.l2cache.writebacks::writebacks       114023                       # number of writebacks
+system.cpu.l2cache.writebacks::total           114023                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         7615                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        27846                       # number of ReadReq MSHR misses
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+system.cpu.l2cache.ReadExReq_mshr_misses::total       130786                       # number of ReadExReq MSHR misses
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+system.cpu.l2cache.demand_mshr_misses::cpu.data       158632                       # number of demand (read+write) MSHR misses
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+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    474721500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   2276772250                       # number of ReadReq MSHR miss cycles
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+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  11463934250                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    474721500                       # number of demand (read+write) MSHR miss cycles
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+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.079622                       # mshr miss rate for ReadReq accesses
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+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.224915                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.911992                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.911992                       # mshr miss rate for ReadExReq accesses
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+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62340.315167                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 81762.991094                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 77592.108232                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 87654.139205                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 87654.139205                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62340.315167                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 86620.016768                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 85507.876834                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62340.315167                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 86620.016768                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 85507.876834                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements            201584                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4073.453777                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            34149208                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs            205680                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            166.030766                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         220256000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4073.453777                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.994496                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.994496                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements            201336                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4071.830097                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            34080339                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            205432                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs            165.895961                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle         215961000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4071.830097                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.994099                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.994099                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           77                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1         1087                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2         2932                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           76                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1         2800                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2         1220                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          71118094                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         71118094                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     20574856                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        20574856                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     13574283                       # number of WriteReq hits
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-system.cpu.dcache.LoadLockedReq_hits::cpu.data           69                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total           69                       # number of LoadLockedReq hits
-system.cpu.dcache.demand_hits::cpu.data      34149139                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         34149139                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     34149139                       # number of overall hits
-system.cpu.dcache.overall_hits::total        34149139                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       267905                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        267905                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      1039094                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      1039094                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data      1306999                       # number of demand (read+write) misses
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-system.cpu.dcache.overall_misses::total       1306999                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  16089401748                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  16089401748                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  84831675131                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  84831675131                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 100921076879                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 100921076879                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 100921076879                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 100921076879                       # number of overall miss cycles
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-system.cpu.dcache.ReadReq_accesses::total     20842761                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.tags.tag_accesses          71000880                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         71000880                       # Number of data accesses
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+system.cpu.dcache.ReadReq_hits::total        20516147                       # number of ReadReq hits
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+system.cpu.dcache.demand_miss_latency::total 102410388120                       # number of demand (read+write) miss cycles
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 system.cpu.dcache.WriteReq_accesses::cpu.data     14613377                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     14613377                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data           69                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total           69                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     35456138                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     35456138                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     35456138                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     35456138                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.012854                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.012854                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.071106                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.071106                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.036862                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.036862                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.036862                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.036862                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60056.369788                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 60056.369788                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 81640.039430                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 81640.039430                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 77215.879185                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 77215.879185                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 77215.879185                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 77215.879185                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs      5326980                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets          131                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs            116355                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               1                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    45.782132                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets          131                       # average number of cycles each access was blocked
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data           57                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total           57                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     35397667                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     35397667                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     35397667                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     35397667                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.012901                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.012901                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.071800                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.071800                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.017544                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.017544                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.037217                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.037217                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.037217                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.037217                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63140.520152                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 63140.520152                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 81468.127556                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 81468.127556                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        92750                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        92750                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 77737.689330                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 77737.689330                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 77737.689330                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 77737.689330                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs      6284356                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets          254                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs            146253                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               2                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    42.969074                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          127                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       169024                       # number of writebacks
-system.cpu.dcache.writebacks::total            169024                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       205645                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       205645                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       895674                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       895674                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      1101319                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      1101319                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      1101319                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      1101319                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data        62260                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total        62260                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       143420                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       143420                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       205680                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       205680                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       205680                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       205680                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   2479695502                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   2479695502                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  13310863495                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  13310863495                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  15790558997                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  15790558997                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  15790558997                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  15790558997                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.002987                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.002987                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.009814                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.009814                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.005801                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.005801                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.005801                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.005801                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 39828.067812                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 39828.067812                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 92810.371601                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 92810.371601                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76772.457201                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 76772.457201                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76772.457201                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 76772.457201                       # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks       168884                       # number of writebacks
+system.cpu.dcache.writebacks::total            168884                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       206118                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       206118                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       905835                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       905835                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      1111953                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      1111953                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      1111953                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      1111953                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data        62025                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total        62025                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       143406                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       143406                       # number of WriteReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data            1                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total            1                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       205431                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       205431                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       205431                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       205431                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   3026595754                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   3026595754                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  13337681700                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  13337681700                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data        90250                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total        90250                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  16364277454                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  16364277454                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  16364277454                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  16364277454                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.002984                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.002984                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.009813                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.009813                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.017544                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.017544                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.005804                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.005804                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.005804                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.005804                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48796.384587                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 48796.384587                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 93006.441153                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 93006.441153                       # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data        90250                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total        90250                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 79658.267029                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 79658.267029                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 79658.267029                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 79658.267029                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt
index 36b629088..c4c8f0d89 100644
--- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.044221                       # Nu
 sim_ticks                                 44221003000                       # Number of ticks simulated
 final_tick                                44221003000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                2624099                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2624098                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1313553455                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 264796                       # Number of bytes of host memory used
-host_seconds                                    33.67                       # Real time elapsed on the host
+host_inst_rate                                3162077                       # Simulator instruction rate (inst/s)
+host_op_rate                                  3162075                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1582850501                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 263736                       # Number of bytes of host memory used
+host_seconds                                    27.94                       # Real time elapsed on the host
 sim_insts                                    88340673                       # Number of instructions simulated
 sim_ops                                      88340673                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -96,10 +96,10 @@ system.cpu.not_idle_fraction                        1                       # Pe
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                          13754477                       # Number of branches fetched
 system.cpu.op_class::No_OpClass               8748916      9.89%      9.89% # Class of executed instruction
-system.cpu.op_class::IntAlu                  44395414     50.20%     60.09% # Class of executed instruction
+system.cpu.op_class::IntAlu                  44394799     50.20%     60.09% # Class of executed instruction
 system.cpu.op_class::IntMult                    41101      0.05%     60.14% # Class of executed instruction
 system.cpu.op_class::IntDiv                         0      0.00%     60.14% # Class of executed instruction
-system.cpu.op_class::FloatAdd                  113689      0.13%     60.27% # Class of executed instruction
+system.cpu.op_class::FloatAdd                  114304      0.13%     60.27% # Class of executed instruction
 system.cpu.op_class::FloatCmp                      84      0.00%     60.27% # Class of executed instruction
 system.cpu.op_class::FloatCvt                  113640      0.13%     60.40% # Class of executed instruction
 system.cpu.op_class::FloatMult                     50      0.00%     60.40% # Class of executed instruction
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
index 005dec492..beac32b45 100644
--- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.133635                       # Nu
 sim_ticks                                133634727000                       # Number of ticks simulated
 final_tick                               133634727000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1051168                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1051168                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1590122468                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 273520                       # Number of bytes of host memory used
-host_seconds                                    84.04                       # Real time elapsed on the host
+host_inst_rate                                1560477                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1560477                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2360564466                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 272464                       # Number of bytes of host memory used
+host_seconds                                    56.61                       # Real time elapsed on the host
 sim_insts                                    88340673                       # Number of instructions simulated
 sim_ops                                      88340673                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -110,10 +110,10 @@ system.cpu.not_idle_fraction                        1                       # Pe
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                          13754477                       # Number of branches fetched
 system.cpu.op_class::No_OpClass               8748916      9.89%      9.89% # Class of executed instruction
-system.cpu.op_class::IntAlu                  44395414     50.20%     60.09% # Class of executed instruction
+system.cpu.op_class::IntAlu                  44394799     50.20%     60.09% # Class of executed instruction
 system.cpu.op_class::IntMult                    41101      0.05%     60.14% # Class of executed instruction
 system.cpu.op_class::IntDiv                         0      0.00%     60.14% # Class of executed instruction
-system.cpu.op_class::FloatAdd                  113689      0.13%     60.27% # Class of executed instruction
+system.cpu.op_class::FloatAdd                  114304      0.13%     60.27% # Class of executed instruction
 system.cpu.op_class::FloatCmp                      84      0.00%     60.27% # Class of executed instruction
 system.cpu.op_class::FloatCvt                  113640      0.13%     60.40% # Class of executed instruction
 system.cpu.op_class::FloatMult                     50      0.00%     60.40% # Class of executed instruction
diff --git a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt
index a19ba8014..c63d403d5 100644
--- a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt
+++ b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt
@@ -1,100 +1,100 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.064367                       # Number of seconds simulated
-sim_ticks                                 64366581500                       # Number of ticks simulated
-final_tick                                64366581500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.056337                       # Number of seconds simulated
+sim_ticks                                 56337328500                       # Number of ticks simulated
+final_tick                                56337328500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  99170                       # Simulator instruction rate (inst/s)
-host_op_rate                                   140730                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               90012135                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 295432                       # Number of bytes of host memory used
-host_seconds                                   715.09                       # Real time elapsed on the host
+host_inst_rate                                 184341                       # Simulator instruction rate (inst/s)
+host_op_rate                                   235745                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              146446418                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 326872                       # Number of bytes of host memory used
+host_seconds                                   384.70                       # Real time elapsed on the host
 sim_insts                                    70915127                       # Number of instructions simulated
-sim_ops                                     100634375                       # Number of ops (including micro ops) simulated
+sim_ops                                      90690083                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst           8259328                       # Number of bytes read from this memory
-system.physmem.bytes_read::total              8259328                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       325696                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          325696                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      5373248                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           5373248                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst             129052                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                129052                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           83957                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total                83957                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst            128317021                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               128317021                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         5060017                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            5060017                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          83478847                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               83478847                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          83478847                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           128317021                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              211795868                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        129052                       # Number of read requests accepted
-system.physmem.writeReqs                        83957                       # Number of write requests accepted
-system.physmem.readBursts                      129052                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                      83957                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                  8258880                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                       448                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   5371584                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                   8259328                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                5373248                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                        7                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytes_read::cpu.inst           8247168                       # Number of bytes read from this memory
+system.physmem.bytes_read::total              8247168                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       323904                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          323904                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      5372864                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           5372864                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst             128862                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                128862                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           83951                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                83951                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst            146389050                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               146389050                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         5749367                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            5749367                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          95369520                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               95369520                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          95369520                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           146389050                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              241758570                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        128862                       # Number of read requests accepted
+system.physmem.writeReqs                        83951                       # Number of write requests accepted
+system.physmem.readBursts                      128862                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                      83951                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                  8246784                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                       384                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   5371008                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                   8247168                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                5372864                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                        6                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                8196                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                8381                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                8249                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                8185                       # Per bank write bursts
-system.physmem.perBankRdBursts::4                8327                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                8459                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                8094                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                7981                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                8076                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                7644                       # Per bank write bursts
-system.physmem.perBankRdBursts::10               7831                       # Per bank write bursts
-system.physmem.perBankRdBursts::11               7843                       # Per bank write bursts
-system.physmem.perBankRdBursts::12               7891                       # Per bank write bursts
-system.physmem.perBankRdBursts::13               7884                       # Per bank write bursts
-system.physmem.perBankRdBursts::14               7977                       # Per bank write bursts
-system.physmem.perBankRdBursts::15               8027                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                5181                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                5375                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                5284                       # Per bank write bursts
+system.physmem.perBankRdBursts::0                8164                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                8373                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                8238                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                8169                       # Per bank write bursts
+system.physmem.perBankRdBursts::4                8316                       # Per bank write bursts
+system.physmem.perBankRdBursts::5                8449                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                8089                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                7969                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                8071                       # Per bank write bursts
+system.physmem.perBankRdBursts::9                7635                       # Per bank write bursts
+system.physmem.perBankRdBursts::10               7816                       # Per bank write bursts
+system.physmem.perBankRdBursts::11               7830                       # Per bank write bursts
+system.physmem.perBankRdBursts::12               7881                       # Per bank write bursts
+system.physmem.perBankRdBursts::13               7876                       # Per bank write bursts
+system.physmem.perBankRdBursts::14               7976                       # Per bank write bursts
+system.physmem.perBankRdBursts::15               8004                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                5182                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                5376                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                5285                       # Per bank write bursts
 system.physmem.perBankWrBursts::3                5155                       # Per bank write bursts
 system.physmem.perBankWrBursts::4                5265                       # Per bank write bursts
 system.physmem.perBankWrBursts::5                5517                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                5201                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                5050                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                5034                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                5087                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               5251                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               5146                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               5344                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                5198                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                5049                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                5033                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                5086                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               5252                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               5143                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               5343                       # Per bank write bursts
 system.physmem.perBankWrBursts::13               5363                       # Per bank write bursts
 system.physmem.perBankWrBursts::14               5451                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               5227                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               5224                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                     64366550000                       # Total gap between requests
+system.physmem.totGap                     56337297000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  129052                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  128862                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                  83957                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    128466                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       557                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                  83951                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    126556                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      2278                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::2                        22                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
@@ -140,25 +140,25 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                      633                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                      644                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     4312                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     5147                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     5164                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     5167                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     5160                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     5162                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     5167                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     5183                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     5171                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     5182                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     5366                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     5212                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     5234                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     5667                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     5208                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     5156                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                        7                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                      610                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                      624                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     4267                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     5149                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     5165                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     5169                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     5164                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     5168                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     5166                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     5182                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     5177                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     5179                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     5351                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     5232                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     5236                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     5687                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     5245                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     5159                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                        6                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
@@ -189,96 +189,94 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        38820                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      351.055332                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     212.918314                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     334.655421                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          12445     32.06%     32.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255         8253     21.26%     53.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         4125     10.63%     63.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         2767      7.13%     71.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2567      6.61%     77.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1675      4.31%     82.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1312      3.38%     85.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1197      3.08%     88.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         4479     11.54%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          38820                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          5156                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        25.028123                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      359.400532                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023           5153     99.94%     99.94% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples        38348                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      355.034109                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     215.640084                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     336.462166                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          12103     31.56%     31.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255         8116     21.16%     52.73% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         4102     10.70%     63.42% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         2869      7.48%     70.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2471      6.44%     77.35% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1658      4.32%     81.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1256      3.28%     84.95% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1197      3.12%     88.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         4576     11.93%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          38348                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          5157                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        24.976149                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      361.694607                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023           5154     99.94%     99.94% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::1024-2047            1      0.02%     99.96% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2048-3071            1      0.02%     99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::24576-25599            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            5156                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          5155                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        16.280116                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.263015                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        0.779231                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16               4514     87.57%     87.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17                  7      0.14%     87.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18                501      9.72%     97.42% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19                114      2.21%     99.63% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                 12      0.23%     99.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21                  3      0.06%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22                  1      0.02%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23                  1      0.02%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24                  1      0.02%     99.98% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::3072-4095            1      0.02%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::25600-26623            1      0.02%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total            5157                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          5157                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.273415                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.256579                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        0.772702                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               4535     87.94%     87.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17                  9      0.17%     88.11% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18                476      9.23%     97.34% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19                113      2.19%     99.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                 16      0.31%     99.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                  5      0.10%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22                  2      0.04%     99.98% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::25                  1      0.02%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            5155                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     1458157250                       # Total ticks spent queuing
-system.physmem.totMemAccLat                3877751000                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    645225000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       11299.60                       # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::total            5157                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     1494390000                       # Total ticks spent queuing
+system.physmem.totMemAccLat                3910440000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    644280000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       11597.36                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  30049.60                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         128.31                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                          83.45                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                      128.32                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                       83.48                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  30347.36                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         146.38                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                          95.34                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                      146.39                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                       95.37                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           1.65                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       1.00                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.65                       # Data bus utilization in percentage for writes
+system.physmem.busUtil                           1.89                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       1.14                       # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite                      0.74                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.01                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        23.63                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     112129                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     62016                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   86.89                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  73.87                       # Row buffer hit rate for writes
-system.physmem.avgGap                       302177.61                       # Average gap between requests
-system.physmem.pageHitRate                      81.76                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE      37447706500                       # Time in different power states
-system.physmem.memoryStateTime::REF        2149160000                       # Time in different power states
+system.physmem.avgWrQLen                        23.43                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     112251                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     62167                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   87.11                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  74.05                       # Row buffer hit rate for writes
+system.physmem.avgGap                       264726.76                       # Average gap between requests
+system.physmem.pageHitRate                      81.96                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE      31175393250                       # Time in different power states
+system.physmem.memoryStateTime::REF        1881100000                       # Time in different power states
 system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT       24764549750                       # Time in different power states
+system.physmem.memoryStateTime::ACT       23277299250                       # Time in different power states
 system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.membus.throughput                    211795868                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq               26785                       # Transaction distribution
-system.membus.trans_dist::ReadResp              26785                       # Transaction distribution
-system.membus.trans_dist::Writeback             83957                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            102267                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           102267                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       342061                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 342061                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     13632576                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total            13632576                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus               13632576                       # Total data (bytes)
+system.membus.throughput                    241758570                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq               26583                       # Transaction distribution
+system.membus.trans_dist::ReadResp              26583                       # Transaction distribution
+system.membus.trans_dist::Writeback             83951                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            102279                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           102279                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       341675                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 341675                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     13620032                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total            13620032                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus               13620032                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy           975516500                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               1.5                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         1243562250                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              1.9                       # Layer utilization (%)
+system.membus.reqLayer0.occupancy           942262500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               1.7                       # Layer utilization (%)
+system.membus.respLayer1.occupancy         1221459500                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization              2.2                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.branchPred.lookups                16883830                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          12871662                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            417499                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             11152919                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                 7446252                       # Number of BTB hits
+system.cpu.branchPred.lookups                14808792                       # Number of BP lookups
+system.cpu.branchPred.condPredicted           9910132                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            393085                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups              9534896                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                 6736289                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             66.765050                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 1514690                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect                511                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             70.648794                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 1716012                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect                  3                       # Number of incorrect RAS predictions.
 system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -364,70 +362,70 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                 1946                       # Number of system calls
-system.cpu.numCycles                        128733163                       # number of cpu cycles simulated
+system.cpu.numCycles                        112674657                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                    70915127                       # Number of instructions committed
-system.cpu.committedOps                     100634375                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                       2952341                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.committedOps                      90690083                       # Number of ops (including micro ops) committed
+system.cpu.discardedOps                       1227274                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                               1.815313                       # CPI: cycles per instruction
-system.cpu.ipc                               0.550869                       # IPC: instructions per cycle
-system.cpu.tickCycles                       109168240                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                        19564923                       # Total number of cycles that the object has spent stopped
-system.cpu.icache.tags.replacements             43522                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1864.297124                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            27427302                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs             45564                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs            601.951146                       # Average number of references to valid blocks.
+system.cpu.cpi                               1.588866                       # CPI: cycles per instruction
+system.cpu.ipc                               0.629380                       # IPC: instructions per cycle
+system.cpu.tickCycles                        93712970                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                        18961687                       # Total number of cycles that the object has spent stopped
+system.cpu.icache.tags.replacements             42434                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1857.452171                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            24948252                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs             44476                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs            560.937404                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1864.297124                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.910301                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.910301                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst  1857.452171                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.906959                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.906959                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         2042                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           86                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1           35                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3          727                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4         1194                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           89                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           32                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3          846                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1075                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.997070                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          54991298                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         54991298                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     27427302                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        27427302                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      27427302                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         27427302                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     27427302                       # number of overall hits
-system.cpu.icache.overall_hits::total        27427302                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst        45565                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total         45565                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst        45565                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total          45565                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst        45565                       # number of overall misses
-system.cpu.icache.overall_misses::total         45565                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    909865240                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    909865240                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    909865240                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    909865240                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    909865240                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    909865240                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     27472867                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     27472867                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     27472867                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     27472867                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     27472867                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     27472867                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.001659                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.001659                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.001659                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.001659                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.001659                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.001659                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19968.511796                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 19968.511796                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 19968.511796                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 19968.511796                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 19968.511796                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 19968.511796                       # average overall miss latency
+system.cpu.icache.tags.tag_accesses          50029934                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         50029934                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     24948252                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        24948252                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      24948252                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         24948252                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     24948252                       # number of overall hits
+system.cpu.icache.overall_hits::total        24948252                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst        44477                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total         44477                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst        44477                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total          44477                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst        44477                       # number of overall misses
+system.cpu.icache.overall_misses::total         44477                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    894991489                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    894991489                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    894991489                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    894991489                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    894991489                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    894991489                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     24992729                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     24992729                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     24992729                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     24992729                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     24992729                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     24992729                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.001780                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.001780                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.001780                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.001780                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.001780                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.001780                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20122.568721                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 20122.568721                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 20122.568721                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 20122.568721                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 20122.568721                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 20122.568721                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -436,123 +434,123 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst        45565                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total        45565                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst        45565                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total        45565                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst        45565                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total        45565                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    816831760                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    816831760                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    816831760                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    816831760                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    816831760                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    816831760                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.001659                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.001659                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.001659                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.001659                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.001659                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.001659                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17926.736750                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17926.736750                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17926.736750                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 17926.736750                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17926.736750                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 17926.736750                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst        44477                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total        44477                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst        44477                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total        44477                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst        44477                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total        44477                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    804116511                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    804116511                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    804116511                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    804116511                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    804116511                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    804116511                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.001780                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.001780                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.001780                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.001780                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.001780                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.001780                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18079.378353                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18079.378353                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18079.378353                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 18079.378353                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18079.378353                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 18079.378353                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.throughput               333181591                       # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq          99493                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp         99492                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback       128565                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       107033                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       107033                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        91129                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       450487                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total            541616                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2916096                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     18529664                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total       21445760                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus          21445760                       # Total data (bytes)
+system.cpu.toL2Bus.throughput               378768688                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq          97959                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp         97958                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback       128423                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       107038                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       107038                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        88953                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       449463                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total            538416                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2846464                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     18492352                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total       21338816                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus          21338816                       # Total data (bytes)
 system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy      296110500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.occupancy      295133000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.5                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy      69298740                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy      67675489                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy     269478689                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          0.4                       # Layer utilization (%)
-system.cpu.l2cache.tags.replacements            95911                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        30027.975303                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs             100921                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           127032                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             0.794453                       # Average number of references to valid blocks.
+system.cpu.toL2Bus.respLayer1.occupancy     268454939                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization          0.5                       # Layer utilization (%)
+system.cpu.l2cache.tags.replacements            95725                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        29924.855625                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs              99436                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           126843                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             0.783930                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 26739.140336                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  3288.834967                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.816014                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.100367                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.916381                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        31121                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          129                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1         1012                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         9483                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3        19900                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4          597                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.949738                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses          2914793                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses         2914793                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst        72636                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total          72636                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks       128565                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total       128565                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.inst         4766                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total         4766                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst        77402                       # number of demand (read+write) hits
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-system.cpu.l2cache.overall_hits::cpu.inst        77402                       # number of overall hits
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-system.cpu.l2cache.ReadReq_misses::cpu.inst        26857                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total        26857                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.inst       102267                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       102267                       # number of ReadExReq misses
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-system.cpu.l2cache.overall_misses::cpu.inst       129124                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       129124                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst   1992283500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total   1992283500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst   7436939000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   7436939000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst   9429222500                       # number of demand (read+write) miss cycles
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-system.cpu.l2cache.ReadReq_accesses::cpu.inst        99493                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total        99493                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks       128565                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total       128565                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.inst       107033                       # number of ReadExReq accesses(hits+misses)
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-system.cpu.l2cache.demand_accesses::cpu.inst       206526                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total       206526                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst       206526                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total       206526                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.269939                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.269939                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst     0.955472                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.955472                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.625219                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.625219                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.625219                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.625219                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74181.163198                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 74181.163198                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 72720.809254                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72720.809254                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73024.553917                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 73024.553917                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73024.553917                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 73024.553917                       # average overall miss latency
+system.cpu.l2cache.tags.occ_blocks::writebacks 26686.795429                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  3238.060196                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.814416                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.098818                       # Average percentage of cache occupancy
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+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          133                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1         1148                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         9890                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3        19364                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4          583                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.949646                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses          2901241                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses         2901241                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.inst        71304                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total          71304                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks       128423                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total       128423                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.inst         4759                       # number of ReadExReq hits
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+system.cpu.l2cache.overall_misses::total       128934                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst   1978942750                       # number of ReadReq miss cycles
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+system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst   7452442750                       # number of ReadExReq miss cycles
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+system.cpu.l2cache.Writeback_accesses::total       128423                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.inst       107038                       # number of ReadExReq accesses(hits+misses)
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+system.cpu.l2cache.overall_accesses::total       204997                       # number of overall (read+write) accesses
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+system.cpu.l2cache.ReadReq_miss_rate::total     0.272104                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst     0.955539                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.955539                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.628956                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.628956                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.628956                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.628956                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74242.834365                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 74242.834365                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 72863.860128                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72863.860128                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73148.940543                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 73148.940543                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73148.940543                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 73148.940543                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -561,119 +559,119 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        83957                       # number of writebacks
-system.cpu.l2cache.writebacks::total            83957                       # number of writebacks
+system.cpu.l2cache.writebacks::writebacks        83951                       # number of writebacks
+system.cpu.l2cache.writebacks::total            83951                       # number of writebacks
 system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst           71                       # number of ReadReq MSHR hits
 system.cpu.l2cache.ReadReq_mshr_hits::total           71                       # number of ReadReq MSHR hits
 system.cpu.l2cache.demand_mshr_hits::cpu.inst           71                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.demand_mshr_hits::total           71                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.overall_mshr_hits::cpu.inst           71                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::total           71                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        26786                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total        26786                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst       102267                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       102267                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst       129053                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       129053                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst       129053                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       129053                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst   1646558250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1646558250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst   6118064000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   6118064000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   7764622250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total   7764622250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   7764622250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total   7764622250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.269225                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.269225                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst     0.955472                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.955472                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.624875                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.624875                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.624875                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.624875                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61470.852311                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61470.852311                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 59824.420390                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59824.420390                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60166.150729                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60166.150729                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60166.150729                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60166.150729                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        26584                       # number of ReadReq MSHR misses
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+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61546.936127                       # average ReadReq mshr miss latency
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+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60447.909796                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60447.909796                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements            156865                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4070.633737                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            47252087                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs            160961                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            293.562335                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         802561250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.inst  4070.633737                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.inst     0.993807                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.993807                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements            156424                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4068.182682                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            42664218                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            160520                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs            265.787553                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle         770315250                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.inst  4068.182682                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.inst     0.993209                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.993209                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           50                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          711                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2         3335                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          757                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2         3289                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          95193929                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         95193929                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.inst     27577955                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        27577955                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.inst     19642294                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       19642294                       # number of WriteReq hits
+system.cpu.dcache.tags.tag_accesses          86013120                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         86013120                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.inst     22988546                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        22988546                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.inst     19643834                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       19643834                       # number of WriteReq hits
 system.cpu.dcache.LoadLockedReq_hits::cpu.inst        15919                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total        15919                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.inst        15919                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total        15919                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.inst      47220249                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         47220249                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.inst     47220249                       # number of overall hits
-system.cpu.dcache.overall_hits::total        47220249                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.inst        56790                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total         56790                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.inst       207607                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       207607                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.inst       264397                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total         264397                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.inst       264397                       # number of overall misses
-system.cpu.dcache.overall_misses::total        264397                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.inst   2169299439                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total   2169299439                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.inst  15315314750                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  15315314750                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.inst  17484614189                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  17484614189                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.inst  17484614189                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  17484614189                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.inst     27634745                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     27634745                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_hits::cpu.inst      42632380                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         42632380                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.inst     42632380                       # number of overall hits
+system.cpu.dcache.overall_hits::total        42632380                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.inst        56015                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total         56015                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.inst       206067                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       206067                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.inst       262082                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total         262082                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.inst       262082                       # number of overall misses
+system.cpu.dcache.overall_misses::total        262082                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.inst   2143200689                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total   2143200689                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.inst  15189809250                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  15189809250                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.inst  17333009939                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  17333009939                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.inst  17333009939                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  17333009939                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.inst     23044561                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     23044561                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.inst     19849901                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     19849901                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::cpu.inst        15919                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::total        15919                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.inst        15919                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total        15919                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.inst     47484646                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     47484646                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.inst     47484646                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     47484646                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.inst     0.002055                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.002055                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.inst     0.010459                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.010459                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.inst     0.005568                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.005568                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.inst     0.005568                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.005568                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 38198.616640                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 38198.616640                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 73770.704986                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 73770.704986                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66130.153478                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 66130.153478                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66130.153478                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 66130.153478                       # average overall miss latency
+system.cpu.dcache.demand_accesses::cpu.inst     42894462                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     42894462                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.inst     42894462                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     42894462                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.inst     0.002431                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.002431                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.inst     0.010381                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.010381                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.inst     0.006110                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.006110                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.inst     0.006110                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.006110                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 38261.192341                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 38261.192341                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 73712.963502                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 73712.963502                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66135.827485                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 66135.827485                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66135.827485                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 66135.827485                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -682,48 +680,48 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       128565                       # number of writebacks
-system.cpu.dcache.writebacks::total            128565                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.inst         2862                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total         2862                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.inst       100574                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       100574                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.inst       103436                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       103436                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.inst       103436                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       103436                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.inst        53928                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total        53928                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.inst       107033                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       107033                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.inst       160961                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       160961                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.inst       160961                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       160961                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst   2001760311                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   2001760311                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst   7591657000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   7591657000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.inst   9593417311                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total   9593417311                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.inst   9593417311                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total   9593417311                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst     0.001951                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.001951                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.writebacks::writebacks       128423                       # number of writebacks
+system.cpu.dcache.writebacks::total            128423                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.inst         2533                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total         2533                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.inst        99029                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total        99029                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.inst       101562                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       101562                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.inst       101562                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       101562                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.inst        53482                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total        53482                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.inst       107038                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       107038                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.inst       160520                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       160520                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.inst       160520                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       160520                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst   1986266811                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   1986266811                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst   7607104750                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   7607104750                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.inst   9593371561                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total   9593371561                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.inst   9593371561                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total   9593371561                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst     0.002321                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.002321                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst     0.005392                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.005392                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.inst     0.003390                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.003390                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.inst     0.003390                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.003390                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 37119.127559                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 37119.127559                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 70928.190371                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70928.190371                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 59600.880406                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 59600.880406                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 59600.880406                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 59600.880406                       # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.inst     0.003742                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.003742                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.inst     0.003742                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.003742                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 37138.977806                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 37138.977806                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 71069.197388                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71069.197388                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 59764.338157                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 59764.338157                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 59764.338157                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 59764.338157                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt
index 8bf0c37c9..9e6dda47f 100644
--- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt
@@ -1,107 +1,107 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.025431                       # Number of seconds simulated
-sim_ticks                                 25431292500                       # Number of ticks simulated
-final_tick                                25431292500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.023896                       # Number of seconds simulated
+sim_ticks                                 23896420500                       # Number of ticks simulated
+final_tick                                23896420500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 123125                       # Simulator instruction rate (inst/s)
-host_op_rate                                   174730                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               44159257                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 270444                       # Number of bytes of host memory used
-host_seconds                                   575.90                       # Real time elapsed on the host
+host_inst_rate                                 105740                       # Simulator instruction rate (inst/s)
+host_op_rate                                   135229                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               35635051                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 262840                       # Number of bytes of host memory used
+host_seconds                                   670.59                       # Real time elapsed on the host
 sim_insts                                    70907629                       # Number of instructions simulated
-sim_ops                                     100626876                       # Number of ops (including micro ops) simulated
+sim_ops                                      90682584                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            300416                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           7942976                       # Number of bytes read from this memory
-system.physmem.bytes_read::total              8243392                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       300416                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          300416                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      5372352                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           5372352                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               4694                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             124109                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                128803                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           83943                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total                83943                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst             11812848                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            312330803                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               324143651                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst        11812848                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total           11812848                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks         211249664                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total              211249664                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks         211249664                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst            11812848                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           312330803                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              535393315                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        128804                       # Number of read requests accepted
-system.physmem.writeReqs                        83943                       # Number of write requests accepted
-system.physmem.readBursts                      128804                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                      83943                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                  8243072                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                       384                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   5371136                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                   8243456                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                5372352                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                        6                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytes_read::cpu.inst            299392                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           7936704                       # Number of bytes read from this memory
+system.physmem.bytes_read::total              8236096                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       299392                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          299392                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      5372800                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           5372800                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               4678                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             124011                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                128689                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           83950                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                83950                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst             12528738                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            332129408                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               344658147                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst        12528738                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total           12528738                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks         224837021                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total              224837021                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks         224837021                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst            12528738                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           332129408                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              569495168                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        128689                       # Number of read requests accepted
+system.physmem.writeReqs                        83950                       # Number of write requests accepted
+system.physmem.readBursts                      128689                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                      83950                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                  8235648                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                       448                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   5371072                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                   8236096                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                5372800                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                        7                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs            342                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                8140                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                8383                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                8248                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                8172                       # Per bank write bursts
-system.physmem.perBankRdBursts::4                8304                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                8450                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                8104                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                7960                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                8081                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                7608                       # Per bank write bursts
-system.physmem.perBankRdBursts::10               7787                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs            380                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0                8141                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                8384                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                8239                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                8150                       # Per bank write bursts
+system.physmem.perBankRdBursts::4                8295                       # Per bank write bursts
+system.physmem.perBankRdBursts::5                8428                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                8074                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                7958                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                8067                       # Per bank write bursts
+system.physmem.perBankRdBursts::9                7598                       # Per bank write bursts
+system.physmem.perBankRdBursts::10               7783                       # Per bank write bursts
 system.physmem.perBankRdBursts::11               7813                       # Per bank write bursts
-system.physmem.perBankRdBursts::12               7882                       # Per bank write bursts
-system.physmem.perBankRdBursts::13               7882                       # Per bank write bursts
-system.physmem.perBankRdBursts::14               7972                       # Per bank write bursts
-system.physmem.perBankRdBursts::15               8012                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                5177                       # Per bank write bursts
+system.physmem.perBankRdBursts::12               7877                       # Per bank write bursts
+system.physmem.perBankRdBursts::13               7881                       # Per bank write bursts
+system.physmem.perBankRdBursts::14               7983                       # Per bank write bursts
+system.physmem.perBankRdBursts::15               8011                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                5183                       # Per bank write bursts
 system.physmem.perBankWrBursts::1                5376                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                5291                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                5156                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                5265                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                5289                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                5157                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                5266                       # Per bank write bursts
 system.physmem.perBankWrBursts::5                5517                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                5200                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                5050                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                5030                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                5089                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               5251                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               5142                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                5198                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                5051                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                5029                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                5090                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               5246                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               5140                       # Per bank write bursts
 system.physmem.perBankWrBursts::12               5343                       # Per bank write bursts
 system.physmem.perBankWrBursts::13               5363                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               5451                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               5452                       # Per bank write bursts
 system.physmem.perBankWrBursts::15               5223                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                     25431274000                       # Total gap between requests
+system.physmem.totGap                     23896016500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  128804                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  128689                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                  83943                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                     74268                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     52779                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                      1686                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                        57                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                         7                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                  83950                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                     68784                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     50927                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                      6546                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                      2414                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                        10                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
@@ -144,29 +144,29 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                      634                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                      658                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     2213                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     3968                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     4721                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     5105                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     5202                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     5223                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     5297                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     5379                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     5443                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     5403                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     5565                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     5914                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     5677                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     6138                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     6027                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     5293                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                       56                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                       12                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                      628                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                      644                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     2057                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     3691                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     4468                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     4948                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     5100                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     5202                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     5301                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     5438                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     5521                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     5545                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     5656                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     6068                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     5800                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     6220                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     6095                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     5413                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                       91                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                       30                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                       13                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                        4                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                        2                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
@@ -193,97 +193,99 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        37764                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      360.466900                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     216.757090                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     343.203142                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          11986     31.74%     31.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255         7964     21.09%     52.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         3753      9.94%     62.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         2738      7.25%     70.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2422      6.41%     76.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1565      4.14%     80.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1215      3.22%     83.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1119      2.96%     86.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         5002     13.25%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          37764                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::samples        37607                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      361.810089                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     217.183531                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     344.455844                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          11970     31.83%     31.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255         7877     20.95%     52.77% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         3759     10.00%     62.77% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         2606      6.93%     69.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2473      6.58%     76.28% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1554      4.13%     80.41% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1216      3.23%     83.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1043      2.77%     86.41% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         5109     13.59%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          37607                       # Bytes accessed per row activation
 system.physmem.rdPerTurnAround::samples          5143                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        25.040249                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      360.430137                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023           5140     99.94%     99.94% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-2047            1      0.02%     99.96% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2048-3071            1      0.02%     99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::24576-25599            1      0.02%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        25.009139                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      391.762417                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023           5141     99.96%     99.96% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-2047            1      0.02%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::27648-28671            1      0.02%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::total            5143                       # Reads before turning the bus around for writes
 system.physmem.wrPerTurnAround::samples          5143                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        16.318102                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.295777                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        0.900493                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16               4492     87.34%     87.34% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17                  9      0.17%     87.52% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18                404      7.86%     95.37% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19                175      3.40%     98.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                 41      0.80%     99.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21                 14      0.27%     99.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22                  4      0.08%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23                  2      0.04%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::27                  2      0.04%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.317908                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.294258                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        0.943897                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               4493     87.36%     87.36% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17                 13      0.25%     87.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18                424      8.24%     95.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19                146      2.84%     98.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                 43      0.84%     99.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                 15      0.29%     99.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22                  3      0.06%     99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23                  1      0.02%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25                  1      0.02%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::27                  1      0.02%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28                  1      0.02%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32                  2      0.04%    100.00% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::total            5143                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     2477042500                       # Total ticks spent queuing
-system.physmem.totMemAccLat                4892005000                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    643990000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       19232.00                       # Average queueing delay per DRAM burst
+system.physmem.totQLat                     2744774250                       # Total ticks spent queuing
+system.physmem.totMemAccLat                5157561750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    643410000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       21329.90                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  37982.00                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         324.13                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                         211.20                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                      324.15                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                      211.25                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  40079.90                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         344.64                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                         224.76                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                      344.66                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                      224.84                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           4.18                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       2.53                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      1.65                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.36                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        23.78                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     112907                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     62042                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   87.66                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  73.91                       # Row buffer hit rate for writes
-system.physmem.avgGap                       119537.64                       # Average gap between requests
-system.physmem.pageHitRate                      82.24                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE      10352020250                       # Time in different power states
-system.physmem.memoryStateTime::REF         849160000                       # Time in different power states
+system.physmem.busUtil                           4.45                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       2.69                       # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite                      1.76                       # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen                         1.39                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        23.67                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     112874                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     62123                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   87.72                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  74.00                       # Row buffer hit rate for writes
+system.physmem.avgGap                       112378.33                       # Average gap between requests
+system.physmem.pageHitRate                      82.30                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE       9567571500                       # Time in different power states
+system.physmem.memoryStateTime::REF         797940000                       # Time in different power states
 system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT       14228986000                       # Time in different power states
+system.physmem.memoryStateTime::ACT       13530763500                       # Time in different power states
 system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.membus.throughput                    535393315                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq               26553                       # Transaction distribution
-system.membus.trans_dist::ReadResp              26552                       # Transaction distribution
-system.membus.trans_dist::Writeback             83943                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq              342                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp             342                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            102251                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           102251                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       342234                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 342234                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     13615744                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total            13615744                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus               13615744                       # Total data (bytes)
+system.membus.throughput                    569495168                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq               26431                       # Transaction distribution
+system.membus.trans_dist::ReadResp              26431                       # Transaction distribution
+system.membus.trans_dist::Writeback             83950                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq              380                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp             380                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            102258                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           102258                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       342088                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 342088                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     13608896                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total            13608896                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus               13608896                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy           901934500                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               3.5                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         1187807158                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              4.7                       # Layer utilization (%)
+system.membus.reqLayer0.occupancy           898146000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               3.8                       # Layer utilization (%)
+system.membus.respLayer1.occupancy         1183170872                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization              5.0                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.branchPred.lookups                17001662                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          13020210                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            614898                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             10708539                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                 7958691                       # Number of BTB hits
+system.cpu.branchPred.lookups                17877019                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          11927811                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            593439                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             11204319                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                 8313088                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             74.320979                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 1855518                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect             113838                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             74.195388                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 1978187                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect             104069                       # Number of incorrect RAS predictions.
 system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -369,521 +371,521 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                 1946                       # Number of system calls
-system.cpu.numCycles                         50862586                       # number of cpu cycles simulated
+system.cpu.numCycles                         47792842                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           12841579                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                       87379296                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    17001662                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches            9814209                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      21679126                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 2704202                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles                6435967                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                   67                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles           392                       # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles           76                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                  11938705                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                201875                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples           43012606                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.839331                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.389146                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles           13399730                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                       91818563                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    17877019                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           10291275                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      33374868                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 1293258                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles                  460                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles          3119                       # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles           70                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                  12485707                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                222370                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples           47424876                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.444936                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.221090                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 21356489     49.65%     49.65% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  2172665      5.05%     54.70% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  2009321      4.67%     59.37% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  2081413      4.84%     64.21% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  1500240      3.49%     67.70% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  1419840      3.30%     71.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                   985272      2.29%     73.29% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  1219233      2.83%     76.13% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                 10268133     23.87%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 25840907     54.49%     54.49% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  2398343      5.06%     59.55% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  2102611      4.43%     63.98% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  2392037      5.04%     69.02% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  1862029      3.93%     72.95% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  1496992      3.16%     76.11% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  1004992      2.12%     78.22% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  1407650      2.97%     81.19% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                  8919315     18.81%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total             43012606                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.334267                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.717948                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 13769056                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles               5959303                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  20895341                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles                441693                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                1947213                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved              3430949                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                110387                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              119589480                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                395300                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                1947213                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 14636498                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                  284865                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles        1020852                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  20468957                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles               4654221                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              117623188                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                   544                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                 181856                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                2734092                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                1628680                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.FullRegisterEvents             1673                       # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands           117928367                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             541896046                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        487330730                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups              3427                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps              99132672                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 18795695                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts              20563                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts          20550                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                   5392644                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             30100241                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            22927452                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           5590192                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          5698921                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  113818479                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded               36102                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 108240105                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            379531                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        13068972                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     32214297                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved           2316                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples      43012606                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         2.516474                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        2.084237                       # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total             47424876                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.374052                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.921178                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                  9991238                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              18372924                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  15962018                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               2553700                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                 544996                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              3514191                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                104008                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              110994138                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                375319                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                 544996                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 11354333                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                 2895918                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles        1063087                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  17104266                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              14462276                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              108881212                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                  1310                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                1983947                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                2643349                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents                9691184                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands           114456313                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             501643948                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        126478316                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups              2998                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps              93629226                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                 20827087                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts              24787                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts          25137                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  12915604                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             25719384                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            23405570                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           6651489                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          7812944                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  105238243                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded               38026                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                  99646497                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            159437                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        14433434                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     35646535                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved           4240                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples      47424876                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         2.101144                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        2.177334                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0             9996470     23.24%     23.24% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1             6251950     14.54%     37.78% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2             6474591     15.05%     52.83% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3             6613067     15.37%     68.20% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4             5424130     12.61%     80.81% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             4356381     10.13%     90.94% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             2112627      4.91%     95.85% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7             1221535      2.84%     98.69% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              561855      1.31%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            16924239     35.69%     35.69% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1             6535440     13.78%     49.47% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2             6148782     12.97%     62.43% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3             5092843     10.74%     73.17% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             5223877     11.02%     84.19% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             3271997      6.90%     91.09% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             2206801      4.65%     95.74% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             1128511      2.38%     98.12% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              892386      1.88%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total        43012606                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total        47424876                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                  131486      5.24%      5.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      1      0.00%      5.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      5.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      5.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      5.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      5.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      5.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      5.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      5.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      5.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      5.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      5.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      5.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      5.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      5.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      5.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      5.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      5.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      5.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      5.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      5.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      5.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      5.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      5.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      5.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      5.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      5.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      5.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      5.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                1416079     56.44%     61.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                961652     38.32%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  215167      9.06%      9.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      9.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      9.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      9.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      9.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      9.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      9.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      9.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      9.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      9.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      9.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      9.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      9.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      9.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      9.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      9.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      9.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      9.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      9.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      9.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      9.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      9.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      9.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      9.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      9.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      9.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      9.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      9.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      9.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                1190055     50.09%     59.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                970810     40.86%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu              57280619     52.92%     52.92% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                91502      0.08%     53.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     53.00% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                 249      0.00%     53.00% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     53.00% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     53.00% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     53.00% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     53.00% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     53.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     53.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     53.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     53.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     53.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     53.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     53.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     53.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     53.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     53.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     53.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     53.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     53.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     53.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     53.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     53.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     53.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              7      0.00%     53.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     53.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     53.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     53.00% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             29070055     26.86%     79.86% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            21797673     20.14%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu              51976863     52.16%     52.16% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                92995      0.09%     52.25% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     52.25% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                 147      0.00%     52.25% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     52.25% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     52.25% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     52.25% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     52.25% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     52.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     52.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     52.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     52.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     52.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     52.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     52.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     52.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     52.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     52.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     52.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     52.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     52.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     52.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     52.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     52.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     52.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              7      0.00%     52.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     52.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     52.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     52.25% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             25513927     25.60%     77.86% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            22062558     22.14%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              108240105                       # Type of FU issued
-system.cpu.iq.rate                           2.128089                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     2509218                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.023182                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          262380760                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         126960554                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    106504533                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads                 805                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes               1416                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses          198                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              110748938                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                     385                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads          2726538                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total               99646497                       # Type of FU issued
+system.cpu.iq.rate                           2.084967                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     2376032                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.023845                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          249252729                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         119771582                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses     97191472                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads                 610                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes                940                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses          210                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              102022220                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                     309                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads          2232705                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      2793133                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses         5994                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        39986                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      2371714                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      2853122                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses         4762                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        65666                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      2849832                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads           30                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked           777                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads       726205                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked         82286                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                1947213                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                   83242                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                154560                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           113864521                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            271261                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              30100241                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             22927452                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts              20182                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                  11127                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                139253                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          39986                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         397706                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       183440                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts               581146                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             107196907                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              28742416                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           1043198                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                 544996                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 1714516                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                834399                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           105286702                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            183365                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts              25719384                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             23405570                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts              22106                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                  17305                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                806226                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          65666                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         396732                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       182672                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts               579404                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts              98631248                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              25214590                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           1015249                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                          9940                       # number of nop insts executed
-system.cpu.iew.exec_refs                     50252614                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 14716112                       # Number of branches executed
-system.cpu.iew.exec_stores                   21510198                       # Number of stores executed
-system.cpu.iew.exec_rate                     2.107579                       # Inst execution rate
-system.cpu.iew.wb_sent                      106740577                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     106504731                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                  57038202                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 114479064                       # num instructions consuming a value
+system.cpu.iew.exec_nop                         10433                       # number of nop insts executed
+system.cpu.iew.exec_refs                     46968385                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 14905400                       # Number of branches executed
+system.cpu.iew.exec_stores                   21753795                       # Number of stores executed
+system.cpu.iew.exec_rate                     2.063724                       # Inst execution rate
+system.cpu.iew.wb_sent                       97441036                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                      97191682                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                  50912103                       # num instructions producing a value
+system.cpu.iew.wb_consumers                  98942269                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       2.093970                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.498241                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       2.033603                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.514564                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts        13236328                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts        14604340                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls           33786                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            506712                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples     41065393                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     2.450541                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.921831                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts            491808                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples     45293214                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     2.002246                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.787973                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     14078032     34.28%     34.28% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     10319124     25.13%     59.41% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2      2761047      6.72%     66.13% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      2619650      6.38%     72.51% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      1508272      3.67%     76.19% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      1822351      4.44%     80.62% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6       663911      1.62%     82.24% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7       540097      1.32%     83.56% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      6752909     16.44%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     20766641     45.85%     45.85% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1      9214809     20.34%     66.19% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      2670756      5.90%     72.09% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      2400198      5.30%     77.39% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      2023573      4.47%     81.86% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5       972100      2.15%     84.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6       768345      1.70%     85.70% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       447977      0.99%     86.69% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      6028815     13.31%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total     41065393                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total     45293214                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts             70913181                       # Number of instructions committed
-system.cpu.commit.committedOps              100632428                       # Number of ops (including micro ops) committed
+system.cpu.commit.committedOps               90688136                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                       47862846                       # Number of memory references committed
-system.cpu.commit.loads                      27307108                       # Number of loads committed
+system.cpu.commit.refs                       43422000                       # Number of memory references committed
+system.cpu.commit.loads                      22866262                       # Number of loads committed
 system.cpu.commit.membars                       15920                       # Number of memory barriers committed
 system.cpu.commit.branches                   13741485                       # Number of branches committed
 system.cpu.commit.fp_insts                         56                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                  91472779                       # Number of committed integer instructions.
+system.cpu.commit.int_insts                  81528487                       # Number of committed integer instructions.
 system.cpu.commit.function_calls              1679850                       # Number of function calls committed.
 system.cpu.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu         52689456     52.36%     52.36% # Class of committed instruction
-system.cpu.commit.op_class_0::IntMult           80119      0.08%     52.44% # Class of committed instruction
-system.cpu.commit.op_class_0::IntDiv                0      0.00%     52.44% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatAdd              0      0.00%     52.44% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatCmp              0      0.00%     52.44% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatCvt              0      0.00%     52.44% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMult             0      0.00%     52.44% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatDiv              0      0.00%     52.44% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     52.44% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAdd               0      0.00%     52.44% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     52.44% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAlu               0      0.00%     52.44% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdCmp               0      0.00%     52.44% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdCvt               0      0.00%     52.44% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMisc              0      0.00%     52.44% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMult              0      0.00%     52.44% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     52.44% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdShift             0      0.00%     52.44% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     52.44% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     52.44% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     52.44% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     52.44% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     52.44% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     52.44% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     52.44% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMisc            7      0.00%     52.44% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     52.44% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     52.44% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     52.44% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead        27307108     27.14%     79.57% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite       20555738     20.43%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu         47186010     52.03%     52.03% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult           80119      0.09%     52.12% # Class of committed instruction
+system.cpu.commit.op_class_0::IntDiv                0      0.00%     52.12% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatAdd              0      0.00%     52.12% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCmp              0      0.00%     52.12% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCvt              0      0.00%     52.12% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatMult             0      0.00%     52.12% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatDiv              0      0.00%     52.12% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     52.12% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAdd               0      0.00%     52.12% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     52.12% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAlu               0      0.00%     52.12% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCmp               0      0.00%     52.12% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCvt               0      0.00%     52.12% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMisc              0      0.00%     52.12% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMult              0      0.00%     52.12% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     52.12% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShift             0      0.00%     52.12% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     52.12% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     52.12% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     52.12% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     52.12% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     52.12% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     52.12% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     52.12% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMisc            7      0.00%     52.12% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     52.12% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     52.12% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     52.12% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead        22866262     25.21%     77.33% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite       20555738     22.67%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total         100632428                       # Class of committed instruction
-system.cpu.commit.bw_lim_events               6752909                       # number cycles where commit BW limit reached
+system.cpu.commit.op_class_0::total          90688136                       # Class of committed instruction
+system.cpu.commit.bw_lim_events               6028815                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                    148155941                       # The number of ROB reads
-system.cpu.rob.rob_writes                   229697127                       # The number of ROB writes
-system.cpu.timesIdled                           83826                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                         7849980                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads                    144531576                       # The number of ROB reads
+system.cpu.rob.rob_writes                   212728591                       # The number of ROB writes
+system.cpu.timesIdled                           10876                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                          367966                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                    70907629                       # Number of Instructions Simulated
-system.cpu.committedOps                     100626876                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               0.717308                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.717308                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.394102                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.394102                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                515806241                       # number of integer regfile reads
-system.cpu.int_regfile_writes               104262317                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                      1054                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                      938                       # number of floating regfile writes
-system.cpu.misc_regfile_reads                49641533                       # number of misc regfile reads
+system.cpu.committedOps                      90682584                       # Number of Ops (including micro ops) Simulated
+system.cpu.cpi                               0.674016                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.674016                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.483645                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.483645                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                106842718                       # number of integer regfile reads
+system.cpu.int_regfile_writes                59180200                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                      1084                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                      924                       # number of floating regfile writes
+system.cpu.cc_regfile_reads                 361896749                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                 40174850                       # number of cc regfile writes
+system.cpu.misc_regfile_reads                45647350                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                  31840                       # number of misc regfile writes
-system.cpu.toL2Bus.throughput               820945141                       # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq          90021                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp         90020                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback       129157                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq          357                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp          357                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       107037                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       107037                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        68737                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       454707                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total            523444                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2182208                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     18660800                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total       20843008                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus          20843008                       # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus        34688                       # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy      292444997                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          1.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy      52710982                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.throughput               869793867                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq          88682                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp         88681                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback       129104                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq          425                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp          425                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       106980                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       106980                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        66417                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       454340                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total            520757                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2108672                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     18643008                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total       20751680                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus          20751680                       # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus        33280                       # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy      291703993                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          1.2                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy      50946473                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.2                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy     261104274                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          1.0                       # Layer utilization (%)
-system.cpu.icache.tags.replacements             32259                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1808.767041                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            11900174                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs             34296                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs            346.984313                       # Average number of references to valid blocks.
+system.cpu.toL2Bus.respLayer1.occupancy     259533576                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization          1.1                       # Layer utilization (%)
+system.cpu.icache.tags.replacements             31122                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1801.454521                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            12448339                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs             33152                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs            375.492851                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1808.767041                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.883187                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.883187                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024         2037                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           84                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1           24                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_blocks::cpu.inst  1801.454521                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.879616                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.879616                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         2030                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           92                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           11                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::3         1255                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4          674                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.994629                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          23912047                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         23912047                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     11900181                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        11900181                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      11900181                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         11900181                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     11900181                       # number of overall hits
-system.cpu.icache.overall_hits::total        11900181                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst        38523                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total         38523                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst        38523                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total          38523                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst        38523                       # number of overall misses
-system.cpu.icache.overall_misses::total         38523                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    840683730                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    840683730                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    840683730                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    840683730                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    840683730                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    840683730                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     11938704                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     11938704                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     11938704                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     11938704                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     11938704                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     11938704                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.003227                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.003227                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.003227                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.003227                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.003227                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.003227                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21822.903979                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 21822.903979                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 21822.903979                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 21822.903979                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 21822.903979                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 21822.903979                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs         1168                       # number of cycles access was blocked
+system.cpu.icache.tags.age_task_id_blocks_1024::4          672                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.991211                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses          25004882                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         25004882                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     12448346                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        12448346                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      12448346                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         12448346                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     12448346                       # number of overall hits
+system.cpu.icache.overall_hits::total        12448346                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst        37361                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total         37361                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst        37361                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total          37361                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst        37361                       # number of overall misses
+system.cpu.icache.overall_misses::total         37361                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    833057215                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    833057215                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    833057215                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    833057215                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    833057215                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    833057215                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     12485707                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     12485707                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     12485707                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     12485707                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     12485707                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     12485707                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.002992                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.002992                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.002992                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.002992                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.002992                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.002992                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22297.508498                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 22297.508498                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 22297.508498                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 22297.508498                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 22297.508498                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 22297.508498                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs         1054                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                29                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                26                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    40.275862                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    40.538462                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst         3883                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total         3883                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst         3883                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total         3883                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst         3883                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total         3883                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst        34640                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total        34640                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst        34640                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total        34640                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst        34640                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total        34640                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    683348518                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    683348518                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    683348518                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    683348518                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    683348518                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    683348518                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.002901                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.002901                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.002901                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.002901                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.002901                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.002901                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19727.151212                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19727.151212                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19727.151212                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 19727.151212                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19727.151212                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 19727.151212                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         3892                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total         3892                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst         3892                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total         3892                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst         3892                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total         3892                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst        33469                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total        33469                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst        33469                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total        33469                       # number of demand (read+write) MSHR misses
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+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    671681027                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    671681027                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    671681027                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    671681027                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    671681027                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    671681027                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.002681                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.002681                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.002681                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.002681                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.002681                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.002681                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20068.750993                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20068.750993                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20068.750993                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 20068.750993                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20068.750993                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 20068.750993                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements            95674                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        29835.516778                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs              91740                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           126786                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             0.723581                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements            95567                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        29785.869326                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs              90467                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           126676                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             0.714161                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 26618.880266                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  1380.164406                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  1836.472106                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.812344                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.042119                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.056045                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.910508                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        31112                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          138                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1         1913                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2        20923                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         7751                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4          387                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.949463                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses          2842080                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses         2842080                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst        29388                       # number of ReadReq hits
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-system.cpu.l2cache.ReadReq_hits::total          62847                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks       129157                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total       129157                       # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data           15                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total           15                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data         4786                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total         4786                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst        29388                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data        38245                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total           67633                       # number of demand (read+write) hits
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-system.cpu.l2cache.overall_hits::total          67633                       # number of overall hits
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-system.cpu.l2cache.ReadReq_misses::cpu.data        21922                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total        26632                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data          342                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total          342                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       102251                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       102251                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         4710                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       124173                       # number of demand (read+write) misses
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-system.cpu.l2cache.overall_misses::cpu.data       124173                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       128883                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    353854250                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data   1815685750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total   2169540000                       # number of ReadReq miss cycles
+system.cpu.l2cache.tags.occ_blocks::writebacks 26681.247493                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  1364.251232                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  1740.370601                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.814247                       # Average percentage of cache occupancy
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+system.cpu.l2cache.tags.occ_percent::total     0.908993                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        31109                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          155                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1         2594                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2        24318                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         3666                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4          376                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.949371                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses          2831071                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses         2831071                       # Number of data accesses
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+system.cpu.l2cache.ReadReq_hits::total          61659                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks       129104                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total       129104                       # number of Writeback hits
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+system.cpu.l2cache.UpgradeReq_hits::total           45                       # number of UpgradeReq hits
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+system.cpu.l2cache.overall_hits::total          66381                       # number of overall hits
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+system.cpu.l2cache.overall_misses::cpu.data       124061                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       128761                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    354760000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data   2021590000                       # number of ReadReq miss cycles
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 system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data        46498                       # number of UpgradeReq miss cycles
 system.cpu.l2cache.UpgradeReq_miss_latency::total        46498                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   8365864000                       # number of ReadExReq miss cycles
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-system.cpu.l2cache.demand_miss_latency::cpu.data  10181549750                       # number of demand (read+write) miss cycles
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-system.cpu.l2cache.overall_miss_latency::cpu.inst    353854250                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  10181549750                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  10535404000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst        34098                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data        55381                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total        89479                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks       129157                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total       129157                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data          357                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total          357                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       107037                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       107037                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst        34098                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data       162418                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total       196516                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst        34098                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data       162418                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total       196516                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.138131                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.395840                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.297634                       # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.957983                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.957983                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.955286                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.955286                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.138131                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.764527                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.655840                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.138131                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.764527                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.655840                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 75128.290870                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 82824.822097                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 81463.652749                       # average ReadReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data   135.959064                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total   135.959064                       # average UpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81816.940666                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81816.940666                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75128.290870                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81994.876100                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 81743.938301                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75128.290870                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81994.876100                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 81743.938301                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   8476574750                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   8476574750                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    354760000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  10498164750                       # number of demand (read+write) miss cycles
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+system.cpu.l2cache.ReadReq_accesses::cpu.data        55213                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total        88162                       # number of ReadReq accesses(hits+misses)
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+system.cpu.l2cache.Writeback_accesses::total       129104                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data          425                       # number of UpgradeReq accesses(hits+misses)
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+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.142645                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.394889                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.300617                       # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.894118                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total     0.894118                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.955861                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.955861                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.142645                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.764897                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.659832                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.142645                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.764897                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.659832                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 75480.851064                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 92720.726506                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 89663.434328                       # average ReadReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data   122.363158                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total   122.363158                       # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82894.000958                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82894.000958                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75480.851064                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 84620.990884                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 84287.359915                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75480.851064                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 84620.990884                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 84287.359915                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -892,210 +894,218 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        83943                       # number of writebacks
-system.cpu.l2cache.writebacks::total            83943                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst           15                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           64                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total           79                       # number of ReadReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst           15                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data           64                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total           79                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst           15                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data           64                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total           79                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         4695                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        21858                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total        26553                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data          342                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total          342                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       102251                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       102251                       # number of ReadExReq MSHR misses
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-system.cpu.l2cache.overall_mshr_misses::cpu.inst         4695                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       124109                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       128804                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    294197750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   1539385750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1833583500                       # number of ReadReq MSHR miss cycles
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-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total      3432342                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   7104890000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   7104890000                       # number of ReadExReq MSHR miss cycles
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-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   8644275750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total   8938473500                       # number of demand (read+write) MSHR miss cycles
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-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   8644275750                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total   8938473500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.137691                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.394684                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.296751                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.957983                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.957983                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.955286                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.955286                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.137691                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.764133                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.655438                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.137691                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.764133                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.655438                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62661.927583                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70426.651569                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69053.722743                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10036.087719                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10036.087719                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69484.797215                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69484.797215                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62661.927583                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69650.676019                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69395.931027                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62661.927583                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69650.676019                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69395.931027                       # average overall mshr miss latency
+system.cpu.l2cache.writebacks::writebacks        83950                       # number of writebacks
+system.cpu.l2cache.writebacks::total            83950                       # number of writebacks
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+system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           50                       # number of ReadReq MSHR hits
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+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63014.159008                       # average ReadReq mshr miss latency
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+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 77403.980024                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10037.836842                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10037.836842                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70576.705490                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70576.705490                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63014.159008                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72317.225891                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71978.978553                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63014.159008                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72317.225891                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71978.978553                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements            158322                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4067.859586                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            43957323                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs            162418                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            270.643174                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         358577250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4067.859586                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.993130                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.993130                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements            158097                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4066.697393                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            40254845                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            162193                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs            248.191013                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle         349035000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4066.697393                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.992846                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.992846                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           65                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1         1830                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2         2201                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           75                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1         2487                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2         1534                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          91492426                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         91492426                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     25658218                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        25658218                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     18266460                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       18266460                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data        16005                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total        16005                       # number of LoadLockedReq hits
+system.cpu.dcache.tags.tag_accesses          84282165                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         84282165                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     21874674                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        21874674                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     18263658                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       18263658                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data        83481                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total         83481                       # number of SoftPFReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data        15983                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total        15983                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data        15919                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total        15919                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      43924678                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         43924678                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     43924678                       # number of overall hits
-system.cpu.dcache.overall_hits::total        43924678                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       124918                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        124918                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      1583441                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      1583441                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data           43                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total           43                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data      1708359                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        1708359                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      1708359                       # number of overall misses
-system.cpu.dcache.overall_misses::total       1708359                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data   5184955254                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total   5184955254                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 125206065525                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 125206065525                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       993000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total       993000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 130391020779                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 130391020779                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 130391020779                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 130391020779                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     25783136                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     25783136                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_hits::cpu.data      40138332                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         40138332                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     40221813                       # number of overall hits
+system.cpu.dcache.overall_hits::total        40221813                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       172724                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        172724                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      1586243                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      1586243                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data        47266                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total        47266                       # number of SoftPFReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data           38                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total           38                       # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data      1758967                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        1758967                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      1806233                       # number of overall misses
+system.cpu.dcache.overall_misses::total       1806233                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data   5001907368                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total   5001907368                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 128651444042                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 128651444042                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data      1064000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total      1064000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 133653351410                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 133653351410                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 133653351410                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 133653351410                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     22047398                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     22047398                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     19849901                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     19849901                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data        16048                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total        16048                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data       130747                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total       130747                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data        16021                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total        16021                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data        15919                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total        15919                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     45633037                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     45633037                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     45633037                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     45633037                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.004845                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.004845                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.079771                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.079771                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.002679                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.002679                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.037437                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.037437                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.037437                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.037437                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41506.870539                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 41506.870539                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 79072.138163                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 79072.138163                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 23093.023256                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 23093.023256                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 76325.304447                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 76325.304447                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 76325.304447                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 76325.304447                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs         4253                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets         1744                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs               139                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets              22                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    30.597122                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets    79.272727                       # average number of cycles each access was blocked
+system.cpu.dcache.demand_accesses::cpu.data     41897299                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     41897299                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     42028046                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     42028046                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.007834                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.007834                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.079912                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.079912                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.361507                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.361507                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.002372                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.002372                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.041983                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.041983                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.042977                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.042977                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28958.959774                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 28958.959774                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 81104.499148                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 81104.499148                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        28000                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        28000                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 75984.001638                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 75984.001638                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 73995.631466                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 73995.631466                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs       911565                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets         1622                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs             13218                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets              15                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    68.963913                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets   108.133333                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       129157                       # number of writebacks
-system.cpu.dcache.writebacks::total            129157                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data        69501                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total        69501                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1476084                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total      1476084                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data           42                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total           42                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      1545585                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      1545585                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      1545585                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      1545585                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data        55417                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total        55417                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       107357                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       107357                       # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data            1                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total            1                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       162774                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       162774                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       162774                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       162774                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   2210443817                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   2210443817                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   8528691900                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   8528691900                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data        11000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total        11000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  10739135717                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  10739135717                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  10739135717                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  10739135717                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.002149                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.002149                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.005408                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.005408                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.000062                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.000062                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.003567                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.003567                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.003567                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.003567                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 39887.468051                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 39887.468051                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79442.345632                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79442.345632                       # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data        11000                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total        11000                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65975.743774                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 65975.743774                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65975.743774                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 65975.743774                       # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks       129104                       # number of writebacks
+system.cpu.dcache.writebacks::total            129104                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       141550                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       141550                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1478910                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total      1478910                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data           38                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total           38                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      1620460                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      1620460                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      1620460                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      1620460                       # number of overall MSHR hits
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+system.cpu.dcache.ReadReq_mshr_misses::total        31174                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       107333                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       107333                       # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data        24111                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total        24111                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       138507                       # number of demand (read+write) MSHR misses
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+system.cpu.dcache.overall_mshr_misses::cpu.data       162618                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       162618                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data    566566801                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total    566566801                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   8639740111                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   8639740111                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   1848458500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   1848458500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data   9206306912                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total   9206306912                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  11054765412                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  11054765412                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.001414                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.001414                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.005407                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.005407                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.184410                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.184410                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.003306                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.003306                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.003869                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.003869                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18174.337621                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18174.337621                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80494.723067                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80494.723067                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 76664.530712                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 76664.530712                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66468.170648                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 66468.170648                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67979.961702                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 67979.961702                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt
index d5f8b245c..cf7a88b7a 100644
--- a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt
@@ -1,16 +1,16 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.053932                       # Number of seconds simulated
-sim_ticks                                 53932157000                       # Number of ticks simulated
-final_tick                                53932157000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.048960                       # Number of seconds simulated
+sim_ticks                                 48960011000                       # Number of ticks simulated
+final_tick                                48960011000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1371353                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1946078                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1042965622                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 308436                       # Number of bytes of host memory used
-host_seconds                                    51.71                       # Real time elapsed on the host
+host_inst_rate                                1457592                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1864058                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1006352889                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 314048                       # Number of bytes of host memory used
+host_seconds                                    48.65                       # Real time elapsed on the host
 sim_insts                                    70913181                       # Number of instructions simulated
-sim_ops                                     100632428                       # Number of ops (including micro ops) simulated
+sim_ops                                      90688136                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst         312580272                       # Number of bytes read from this memory
@@ -21,21 +21,21 @@ system.physmem.bytes_inst_read::total       312580272                       # Nu
 system.physmem.bytes_written::cpu.data       78660211                       # Number of bytes written to this memory
 system.physmem.bytes_written::total          78660211                       # Number of bytes written to this memory
 system.physmem.num_reads::cpu.inst           78145068                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data           27156252                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total             105301320                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data           22919730                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total             101064798                       # Number of read requests responded to by this memory
 system.physmem.num_writes::cpu.data          19865820                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total             19865820                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst           5795805126                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data           1976063093                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              7771868220                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst      5795805126                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total         5795805126                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data          1458502967                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total             1458502967                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst          5795805126                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data          3434566060                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             9230371187                       # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput                   9230371187                       # Throughput (bytes/s)
+system.physmem.bw_read::cpu.inst           6384399546                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data           2176742669                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              8561142215                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst      6384399546                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total         6384399546                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data          1606621596                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total             1606621596                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst          6384399546                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data          3783364264                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total            10167763810                       # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput                  10167763810                       # Throughput (bytes/s)
 system.membus.data_through_bus              497813828                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
@@ -124,63 +124,65 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                 1946                       # Number of system calls
-system.cpu.numCycles                        107864315                       # number of cpu cycles simulated
+system.cpu.numCycles                         97920023                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                    70913181                       # Number of instructions committed
-system.cpu.committedOps                     100632428                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses              91472780                       # Number of integer alu accesses
+system.cpu.committedOps                      90688136                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses              81528488                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                     56                       # Number of float alu accesses
 system.cpu.num_func_calls                     3311620                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts     10748863                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                     91472780                       # number of integer instructions
+system.cpu.num_conditional_control_insts      9253644                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                     81528488                       # number of integer instructions
 system.cpu.num_fp_insts                            56                       # number of float instructions
-system.cpu.num_int_register_reads           452305352                       # number of times the integer registers were read
-system.cpu.num_int_register_writes           96252285                       # number of times the integer registers were written
+system.cpu.num_int_register_reads           141479310                       # number of times the integer registers were read
+system.cpu.num_int_register_writes           53916283                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                   36                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                  20                       # number of times the floating registers were written
-system.cpu.num_mem_refs                      47862847                       # number of memory refs
-system.cpu.num_load_insts                    27307108                       # Number of load instructions
+system.cpu.num_cc_register_reads            266608028                       # number of times the CC registers were read
+system.cpu.num_cc_register_writes            36877020                       # number of times the CC registers were written
+system.cpu.num_mem_refs                      43422001                       # number of memory refs
+system.cpu.num_load_insts                    22866262                       # Number of load instructions
 system.cpu.num_store_insts                   20555739                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                  107864315                       # Number of busy cycles
+system.cpu.num_busy_cycles                   97920023                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                          13741485                       # Number of branches fetched
 system.cpu.op_class::No_OpClass                     0      0.00%      0.00% # Class of executed instruction
-system.cpu.op_class::IntAlu                  52691402     52.36%     52.36% # Class of executed instruction
-system.cpu.op_class::IntMult                    80119      0.08%     52.44% # Class of executed instruction
-system.cpu.op_class::IntDiv                         0      0.00%     52.44% # Class of executed instruction
-system.cpu.op_class::FloatAdd                       0      0.00%     52.44% # Class of executed instruction
-system.cpu.op_class::FloatCmp                       0      0.00%     52.44% # Class of executed instruction
-system.cpu.op_class::FloatCvt                       0      0.00%     52.44% # Class of executed instruction
-system.cpu.op_class::FloatMult                      0      0.00%     52.44% # Class of executed instruction
-system.cpu.op_class::FloatDiv                       0      0.00%     52.44% # Class of executed instruction
-system.cpu.op_class::FloatSqrt                      0      0.00%     52.44% # Class of executed instruction
-system.cpu.op_class::SimdAdd                        0      0.00%     52.44% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc                     0      0.00%     52.44% # Class of executed instruction
-system.cpu.op_class::SimdAlu                        0      0.00%     52.44% # Class of executed instruction
-system.cpu.op_class::SimdCmp                        0      0.00%     52.44% # Class of executed instruction
-system.cpu.op_class::SimdCvt                        0      0.00%     52.44% # Class of executed instruction
-system.cpu.op_class::SimdMisc                       0      0.00%     52.44% # Class of executed instruction
-system.cpu.op_class::SimdMult                       0      0.00%     52.44% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc                    0      0.00%     52.44% # Class of executed instruction
-system.cpu.op_class::SimdShift                      0      0.00%     52.44% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc                   0      0.00%     52.44% # Class of executed instruction
-system.cpu.op_class::SimdSqrt                       0      0.00%     52.44% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd                   0      0.00%     52.44% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu                   0      0.00%     52.44% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp                   0      0.00%     52.44% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt                   0      0.00%     52.44% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv                   0      0.00%     52.44% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc                  7      0.00%     52.44% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult                  0      0.00%     52.44% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc               0      0.00%     52.44% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt                  0      0.00%     52.44% # Class of executed instruction
-system.cpu.op_class::MemRead                 27307108     27.13%     79.57% # Class of executed instruction
-system.cpu.op_class::MemWrite                20555739     20.43%    100.00% # Class of executed instruction
+system.cpu.op_class::IntAlu                  47187956     52.03%     52.03% # Class of executed instruction
+system.cpu.op_class::IntMult                    80119      0.09%     52.12% # Class of executed instruction
+system.cpu.op_class::IntDiv                         0      0.00%     52.12% # Class of executed instruction
+system.cpu.op_class::FloatAdd                       0      0.00%     52.12% # Class of executed instruction
+system.cpu.op_class::FloatCmp                       0      0.00%     52.12% # Class of executed instruction
+system.cpu.op_class::FloatCvt                       0      0.00%     52.12% # Class of executed instruction
+system.cpu.op_class::FloatMult                      0      0.00%     52.12% # Class of executed instruction
+system.cpu.op_class::FloatDiv                       0      0.00%     52.12% # Class of executed instruction
+system.cpu.op_class::FloatSqrt                      0      0.00%     52.12% # Class of executed instruction
+system.cpu.op_class::SimdAdd                        0      0.00%     52.12% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc                     0      0.00%     52.12% # Class of executed instruction
+system.cpu.op_class::SimdAlu                        0      0.00%     52.12% # Class of executed instruction
+system.cpu.op_class::SimdCmp                        0      0.00%     52.12% # Class of executed instruction
+system.cpu.op_class::SimdCvt                        0      0.00%     52.12% # Class of executed instruction
+system.cpu.op_class::SimdMisc                       0      0.00%     52.12% # Class of executed instruction
+system.cpu.op_class::SimdMult                       0      0.00%     52.12% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc                    0      0.00%     52.12% # Class of executed instruction
+system.cpu.op_class::SimdShift                      0      0.00%     52.12% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc                   0      0.00%     52.12% # Class of executed instruction
+system.cpu.op_class::SimdSqrt                       0      0.00%     52.12% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd                   0      0.00%     52.12% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu                   0      0.00%     52.12% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp                   0      0.00%     52.12% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt                   0      0.00%     52.12% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv                   0      0.00%     52.12% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc                  7      0.00%     52.12% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult                  0      0.00%     52.12% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc               0      0.00%     52.12% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt                  0      0.00%     52.12% # Class of executed instruction
+system.cpu.op_class::MemRead                 22866262     25.21%     77.33% # Class of executed instruction
+system.cpu.op_class::MemWrite                20555739     22.67%    100.00% # Class of executed instruction
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::total                  100634375                       # Class of executed instruction
+system.cpu.op_class::total                   90690083                       # Class of executed instruction
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt
index 247ca051b..a71c9e67b 100644
--- a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt
@@ -1,16 +1,16 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.132689                       # Number of seconds simulated
-sim_ticks                                132689045000                       # Number of ticks simulated
-final_tick                               132689045000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.127294                       # Number of seconds simulated
+sim_ticks                                127293983000                       # Number of ticks simulated
+final_tick                               127293983000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 682193                       # Simulator instruction rate (inst/s)
-host_op_rate                                   967367                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1286269606                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 318200                       # Number of bytes of host memory used
-host_seconds                                   103.16                       # Real time elapsed on the host
+host_inst_rate                                 875914                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1118296                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1584379759                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 323804                       # Number of bytes of host memory used
+host_seconds                                    80.34                       # Real time elapsed on the host
 sim_insts                                    70373628                       # Number of instructions simulated
-sim_ops                                      99791654                       # Number of ops (including micro ops) simulated
+sim_ops                                      89847362                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst            255488                       # Number of bytes read from this memory
@@ -25,18 +25,18 @@ system.physmem.num_reads::cpu.data             123820                       # Nu
 system.physmem.num_reads::total                127812                       # Number of read requests responded to by this memory
 system.physmem.num_writes::writebacks           83909                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total                83909                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst              1925464                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             59722187                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                61647651                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         1925464                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            1925464                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          40471887                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               40471887                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          40471887                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             1925464                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            59722187                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              102119538                       # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput                    102119538                       # Throughput (bytes/s)
+system.physmem.bw_read::cpu.inst              2007071                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             62253375                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                64260445                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         2007071                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            2007071                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          42187194                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               42187194                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          42187194                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             2007071                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            62253375                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              106447639                       # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput                    106447639                       # Throughput (bytes/s)
 system.membus.trans_dist::ReadReq               25532                       # Transaction distribution
 system.membus.trans_dist::ReadResp              25532                       # Transaction distribution
 system.membus.trans_dist::Writeback             83909                       # Transaction distribution
@@ -48,9 +48,9 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port
 system.membus.tot_pkt_size::total            13550144                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.data_through_bus               13550144                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy           882993000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy           895030780                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.7                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         1150308000                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         1156019000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.9                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
@@ -138,78 +138,80 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                 1946                       # Number of system calls
-system.cpu.numCycles                        265378090                       # number of cpu cycles simulated
+system.cpu.numCycles                        254587966                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                    70373628                       # Number of instructions committed
-system.cpu.committedOps                      99791654                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses              91472780                       # Number of integer alu accesses
+system.cpu.committedOps                      89847362                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses              81528488                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                     56                       # Number of float alu accesses
 system.cpu.num_func_calls                     3311620                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts     10748863                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                     91472780                       # number of integer instructions
+system.cpu.num_conditional_control_insts      9253644                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                     81528488                       # number of integer instructions
 system.cpu.num_fp_insts                            56                       # number of float instructions
-system.cpu.num_int_register_reads           533671029                       # number of times the integer registers were read
-system.cpu.num_int_register_writes           96252285                       # number of times the integer registers were written
+system.cpu.num_int_register_reads           141328474                       # number of times the integer registers were read
+system.cpu.num_int_register_writes           53916283                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                   36                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                  20                       # number of times the floating registers were written
-system.cpu.num_mem_refs                      47862847                       # number of memory refs
-system.cpu.num_load_insts                    27307108                       # Number of load instructions
+system.cpu.num_cc_register_reads            334802003                       # number of times the CC registers were read
+system.cpu.num_cc_register_writes            36877020                       # number of times the CC registers were written
+system.cpu.num_mem_refs                      43422001                       # number of memory refs
+system.cpu.num_load_insts                    22866262                       # Number of load instructions
 system.cpu.num_store_insts                   20555739                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                  265378090                       # Number of busy cycles
+system.cpu.num_busy_cycles                  254587966                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                          13741485                       # Number of branches fetched
 system.cpu.op_class::No_OpClass                     0      0.00%      0.00% # Class of executed instruction
-system.cpu.op_class::IntAlu                  52691402     52.36%     52.36% # Class of executed instruction
-system.cpu.op_class::IntMult                    80119      0.08%     52.44% # Class of executed instruction
-system.cpu.op_class::IntDiv                         0      0.00%     52.44% # Class of executed instruction
-system.cpu.op_class::FloatAdd                       0      0.00%     52.44% # Class of executed instruction
-system.cpu.op_class::FloatCmp                       0      0.00%     52.44% # Class of executed instruction
-system.cpu.op_class::FloatCvt                       0      0.00%     52.44% # Class of executed instruction
-system.cpu.op_class::FloatMult                      0      0.00%     52.44% # Class of executed instruction
-system.cpu.op_class::FloatDiv                       0      0.00%     52.44% # Class of executed instruction
-system.cpu.op_class::FloatSqrt                      0      0.00%     52.44% # Class of executed instruction
-system.cpu.op_class::SimdAdd                        0      0.00%     52.44% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc                     0      0.00%     52.44% # Class of executed instruction
-system.cpu.op_class::SimdAlu                        0      0.00%     52.44% # Class of executed instruction
-system.cpu.op_class::SimdCmp                        0      0.00%     52.44% # Class of executed instruction
-system.cpu.op_class::SimdCvt                        0      0.00%     52.44% # Class of executed instruction
-system.cpu.op_class::SimdMisc                       0      0.00%     52.44% # Class of executed instruction
-system.cpu.op_class::SimdMult                       0      0.00%     52.44% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc                    0      0.00%     52.44% # Class of executed instruction
-system.cpu.op_class::SimdShift                      0      0.00%     52.44% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc                   0      0.00%     52.44% # Class of executed instruction
-system.cpu.op_class::SimdSqrt                       0      0.00%     52.44% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd                   0      0.00%     52.44% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu                   0      0.00%     52.44% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp                   0      0.00%     52.44% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt                   0      0.00%     52.44% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv                   0      0.00%     52.44% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc                  7      0.00%     52.44% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult                  0      0.00%     52.44% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc               0      0.00%     52.44% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt                  0      0.00%     52.44% # Class of executed instruction
-system.cpu.op_class::MemRead                 27307108     27.13%     79.57% # Class of executed instruction
-system.cpu.op_class::MemWrite                20555739     20.43%    100.00% # Class of executed instruction
+system.cpu.op_class::IntAlu                  47187956     52.03%     52.03% # Class of executed instruction
+system.cpu.op_class::IntMult                    80119      0.09%     52.12% # Class of executed instruction
+system.cpu.op_class::IntDiv                         0      0.00%     52.12% # Class of executed instruction
+system.cpu.op_class::FloatAdd                       0      0.00%     52.12% # Class of executed instruction
+system.cpu.op_class::FloatCmp                       0      0.00%     52.12% # Class of executed instruction
+system.cpu.op_class::FloatCvt                       0      0.00%     52.12% # Class of executed instruction
+system.cpu.op_class::FloatMult                      0      0.00%     52.12% # Class of executed instruction
+system.cpu.op_class::FloatDiv                       0      0.00%     52.12% # Class of executed instruction
+system.cpu.op_class::FloatSqrt                      0      0.00%     52.12% # Class of executed instruction
+system.cpu.op_class::SimdAdd                        0      0.00%     52.12% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc                     0      0.00%     52.12% # Class of executed instruction
+system.cpu.op_class::SimdAlu                        0      0.00%     52.12% # Class of executed instruction
+system.cpu.op_class::SimdCmp                        0      0.00%     52.12% # Class of executed instruction
+system.cpu.op_class::SimdCvt                        0      0.00%     52.12% # Class of executed instruction
+system.cpu.op_class::SimdMisc                       0      0.00%     52.12% # Class of executed instruction
+system.cpu.op_class::SimdMult                       0      0.00%     52.12% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc                    0      0.00%     52.12% # Class of executed instruction
+system.cpu.op_class::SimdShift                      0      0.00%     52.12% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc                   0      0.00%     52.12% # Class of executed instruction
+system.cpu.op_class::SimdSqrt                       0      0.00%     52.12% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd                   0      0.00%     52.12% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu                   0      0.00%     52.12% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp                   0      0.00%     52.12% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt                   0      0.00%     52.12% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv                   0      0.00%     52.12% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc                  7      0.00%     52.12% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult                  0      0.00%     52.12% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc               0      0.00%     52.12% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt                  0      0.00%     52.12% # Class of executed instruction
+system.cpu.op_class::MemRead                 22866262     25.21%     77.33% # Class of executed instruction
+system.cpu.op_class::MemWrite                20555739     22.67%    100.00% # Class of executed instruction
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::total                  100634375                       # Class of executed instruction
+system.cpu.op_class::total                   90690083                       # Class of executed instruction
 system.cpu.icache.tags.replacements             16890                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1736.497265                       # Cycle average of tags in use
+system.cpu.icache.tags.tagsinuse          1733.675052                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs            78126161                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs             18908                       # Sample count of references to valid blocks.
 system.cpu.icache.tags.avg_refs           4131.910355                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1736.497265                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.847899                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.847899                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst  1733.675052                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.846521                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.846521                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         2018                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           62                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1           17                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3          184                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4         1755                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           64                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           15                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3          294                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1645                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.985352                       # Percentage of cache occupancy per task id
 system.cpu.icache.tags.tag_accesses         156309046                       # Number of tag accesses
 system.cpu.icache.tags.data_accesses        156309046                       # Number of data accesses
@@ -225,12 +227,12 @@ system.cpu.icache.demand_misses::cpu.inst        18908                       # n
 system.cpu.icache.demand_misses::total          18908                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst        18908                       # number of overall misses
 system.cpu.icache.overall_misses::total         18908                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    413722000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    413722000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    413722000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    413722000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    413722000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    413722000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    414091500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    414091500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    414091500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    414091500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    414091500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    414091500                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst     78145069                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total     78145069                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst     78145069                       # number of demand (read+write) accesses
@@ -243,12 +245,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.000242
 system.cpu.icache.demand_miss_rate::total     0.000242                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000242                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000242                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21880.791199                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 21880.791199                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 21880.791199                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 21880.791199                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 21880.791199                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 21880.791199                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21900.333192                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 21900.333192                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 21900.333192                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 21900.333192                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 21900.333192                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 21900.333192                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -263,44 +265,44 @@ system.cpu.icache.demand_mshr_misses::cpu.inst        18908
 system.cpu.icache.demand_mshr_misses::total        18908                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst        18908                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total        18908                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    375906000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    375906000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    375906000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    375906000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    375906000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    375906000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    376275500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    376275500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    376275500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    376275500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    376275500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    376275500                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000242                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000242                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000242                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000242                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000242                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000242                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19880.791199                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19880.791199                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19880.791199                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 19880.791199                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19880.791199                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 19880.791199                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19900.333192                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19900.333192                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19900.333192                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 19900.333192                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19900.333192                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 19900.333192                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements            94693                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        30368.194893                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse        30351.010864                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs              74295                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs           125788                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs             0.590637                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 27745.868937                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  1154.037281                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  1468.288674                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.846737                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.035218                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.044809                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.926764                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::writebacks 27796.806295                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  1151.765897                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  1402.438673                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.848291                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.035149                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.042799                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.926239                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024        31095                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          107                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          428                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2        10156                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3        19788                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4          616                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          109                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1         1359                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2        15086                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3        13934                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4          607                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.948944                       # Percentage of cache occupancy per task id
 system.cpu.l2cache.tags.tag_accesses          2689980                       # Number of tag accesses
 system.cpu.l2cache.tags.data_accesses         2689980                       # Number of data accesses
@@ -328,17 +330,17 @@ system.cpu.l2cache.demand_misses::total        127812                       # nu
 system.cpu.l2cache.overall_misses::cpu.inst         3992                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data       123820                       # number of overall misses
 system.cpu.l2cache.overall_misses::total       127812                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    207838000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data   1126741000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total   1334579000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   5318574000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   5318574000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    207838000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data   6445315000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total   6653153000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    207838000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data   6445315000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total   6653153000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    208207500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data   1130236000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total   1338443500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   5321243500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   5321243500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    208207500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data   6451479500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total   6659687000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    208207500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data   6451479500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total   6659687000                       # number of overall miss cycles
 system.cpu.l2cache.ReadReq_accesses::cpu.inst        18908                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::cpu.data        52966                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::total        71874                       # number of ReadReq accesses(hits+misses)
@@ -363,17 +365,17 @@ system.cpu.l2cache.demand_miss_rate::total     0.714409                       #
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.211128                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.773885                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.714409                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52063.627255                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52309.238626                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 52270.836597                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.136879                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.136879                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52063.627255                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52053.908900                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 52054.212437                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52063.627255                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52053.908900                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 52054.212437                       # average overall miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52156.187375                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52471.494893                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 52422.195676                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52026.236801                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52026.236801                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52156.187375                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52103.694880                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 52105.334397                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52156.187375                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52103.694880                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 52105.334397                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -395,17 +397,17 @@ system.cpu.l2cache.demand_mshr_misses::total       127812
 system.cpu.l2cache.overall_mshr_misses::cpu.inst         3992                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data       123820                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total       127812                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    159934000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data    868261000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1028195000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   4091214000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   4091214000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    159934000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   4959475000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total   5119409000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    159934000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   4959475000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total   5119409000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    159943500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data    868345500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1028289000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   4091943000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   4091943000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    159943500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   4960288500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total   5120232000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    159943500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   4960288500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total   5120232000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.211128                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.406676                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.355233                       # mshr miss rate for ReadReq accesses
@@ -417,90 +419,98 @@ system.cpu.l2cache.demand_mshr_miss_rate::total     0.714409
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.211128                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.773885                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.714409                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40063.627255                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40309.238626                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40270.836597                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000.136879                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000.136879                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40063.627255                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40053.908900                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40054.212437                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40063.627255                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40053.908900                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40054.212437                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40066.007014                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40313.161560                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40274.518252                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40007.264372                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40007.264372                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40066.007014                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40060.478921                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40060.651582                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40066.007014                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40060.478921                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40060.651582                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.dcache.tags.replacements            155902                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4076.954355                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            46862074                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse          4076.389354                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            42608166                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs            159998                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            292.891624                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle        1072595000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4076.954355                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.995350                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.995350                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.avg_refs            266.304366                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle        1061073000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4076.389354                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.995212                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.995212                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           49                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          443                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2         3604                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          856                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2         3191                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          94204142                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         94204142                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     27087367                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        27087367                       # number of ReadReq hits
+system.cpu.dcache.tags.tag_accesses          85731098                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         85731098                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     22749836                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        22749836                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data     19742869                       # number of WriteReq hits
 system.cpu.dcache.WriteReq_hits::total       19742869                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data        83623                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total         83623                       # number of SoftPFReq hits
 system.cpu.dcache.LoadLockedReq_hits::cpu.data        15919                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total        15919                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data        15919                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total        15919                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      46830236                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         46830236                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     46830236                       # number of overall hits
-system.cpu.dcache.overall_hits::total        46830236                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data        52966                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total         52966                       # number of ReadReq misses
+system.cpu.dcache.demand_hits::cpu.data      42492705                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         42492705                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     42576328                       # number of overall hits
+system.cpu.dcache.overall_hits::total        42576328                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data        30231                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total         30231                       # number of ReadReq misses
 system.cpu.dcache.WriteReq_misses::cpu.data       107032                       # number of WriteReq misses
 system.cpu.dcache.WriteReq_misses::total       107032                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data       159998                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total         159998                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data       159998                       # number of overall misses
-system.cpu.dcache.overall_misses::total        159998                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data   1599899000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total   1599899000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   5687190000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   5687190000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data   7287089000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total   7287089000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data   7287089000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total   7287089000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     27140333                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     27140333                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_misses::cpu.data        40121                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total        40121                       # number of SoftPFReq misses
+system.cpu.dcache.demand_misses::cpu.data       137263                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total         137263                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data       177384                       # number of overall misses
+system.cpu.dcache.overall_misses::total        177384                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data    516746500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total    516746500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   5689859500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   5689859500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data   6206606000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total   6206606000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data   6206606000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total   6206606000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     22780067                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     22780067                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     19849901                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     19849901                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data       123744                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total       123744                       # number of SoftPFReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::cpu.data        15919                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::total        15919                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data        15919                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total        15919                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     46990234                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     46990234                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     46990234                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     46990234                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.001952                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.001952                       # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data     42629968                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     42629968                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     42753712                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     42753712                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.001327                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.001327                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.005392                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_miss_rate::total     0.005392                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.003405                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.003405                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.003405                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.003405                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30206.151116                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 30206.151116                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53135.417445                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 53135.417445                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 45544.875561                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 45544.875561                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 45544.875561                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 45544.875561                       # average overall miss latency
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.324226                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.324226                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.003220                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.003220                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.004149                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.004149                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17093.265191                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 17093.265191                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53160.358584                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 53160.358584                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 45216.890203                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 45216.890203                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 34989.660849                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 34989.660849                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -511,40 +521,54 @@ system.cpu.dcache.fast_writes                       0                       # nu
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks       128239                       # number of writebacks
 system.cpu.dcache.writebacks::total            128239                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data        52966                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total        52966                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data         1123                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total         1123                       # number of ReadReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data         1123                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total         1123                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data         1123                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total         1123                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data        29108                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total        29108                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data       107032                       # number of WriteReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::total       107032                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       159998                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       159998                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data        23858                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total        23858                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       136140                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       136140                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data       159998                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total       159998                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   1493967000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   1493967000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   5473126000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   5473126000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data   6967093000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total   6967093000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data   6967093000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total   6967093000                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.001952                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.001952                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data    443576500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total    443576500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   5475795500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   5475795500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   1053888500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   1053888500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data   5919372000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total   5919372000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data   6973260500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total   6973260500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.001278                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.001278                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.005392                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.005392                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.003405                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.003405                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.003405                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.003405                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 28206.151116                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 28206.151116                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51135.417445                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51135.417445                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 43544.875561                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 43544.875561                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 43544.875561                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 43544.875561                       # average overall mshr miss latency
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.192801                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.192801                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.003194                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.003194                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.003742                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.003742                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15238.989281                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15238.989281                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51160.358584                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51160.358584                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 44173.379998                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 44173.379998                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 43480.035258                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 43480.035258                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 43583.422918                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 43583.422918                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.throughput               148145463                       # Throughput (bytes/s)
+system.cpu.toL2Bus.throughput               154424267                       # Throughput (bytes/s)
 system.cpu.toL2Bus.trans_dist::ReadReq          71874                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadResp         71874                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::Writeback       128239                       # Transaction distribution
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt
index fd5fa200e..8e313893e 100644
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt
@@ -1,100 +1,100 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  1.181828                       # Number of seconds simulated
-sim_ticks                                1181828044500                       # Number of ticks simulated
-final_tick                               1181828044500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  1.181972                       # Number of seconds simulated
+sim_ticks                                1181971516500                       # Number of ticks simulated
+final_tick                               1181971516500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 296156                       # Simulator instruction rate (inst/s)
-host_op_rate                                   296156                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              191639126                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 241048                       # Number of bytes of host memory used
-host_seconds                                  6166.95                       # Real time elapsed on the host
+host_inst_rate                                 316302                       # Simulator instruction rate (inst/s)
+host_op_rate                                   316302                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              204699977                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 267460                       # Number of bytes of host memory used
+host_seconds                                  5774.17                       # Real time elapsed on the host
 sim_insts                                  1826378509                       # Number of instructions simulated
 sim_ops                                    1826378509                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst         125507328                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            125507328                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        61248                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           61248                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     65168512                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          65168512                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst            1961052                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1961052                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1018258                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1018258                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst            106197622                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               106197622                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst           51825                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total              51825                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          55142127                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               55142127                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          55142127                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           106197622                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              161339749                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                       1961052                       # Number of read requests accepted
-system.physmem.writeReqs                      1018258                       # Number of write requests accepted
-system.physmem.readBursts                     1961052                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                    1018258                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                125425344                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     81984                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  65166912                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                 125507328                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               65168512                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                     1281                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytes_read::cpu.inst         125504768                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            125504768                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        61312                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           61312                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     65167040                       # Number of bytes written to this memory
+system.physmem.bytes_written::total          65167040                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst            1961012                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               1961012                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1018235                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total              1018235                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst            106182566                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               106182566                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst           51873                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total              51873                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          55134188                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               55134188                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          55134188                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           106182566                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              161316754                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                       1961012                       # Number of read requests accepted
+system.physmem.writeReqs                      1018235                       # Number of write requests accepted
+system.physmem.readBursts                     1961012                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                    1018235                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                125424512                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     80256                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  65165696                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                 125504768                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               65167040                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                     1254                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0              118745                       # Per bank write bursts
-system.physmem.perBankRdBursts::1              114099                       # Per bank write bursts
-system.physmem.perBankRdBursts::2              116228                       # Per bank write bursts
-system.physmem.perBankRdBursts::3              117773                       # Per bank write bursts
-system.physmem.perBankRdBursts::4              117823                       # Per bank write bursts
-system.physmem.perBankRdBursts::5              117515                       # Per bank write bursts
+system.physmem.perBankRdBursts::0              118750                       # Per bank write bursts
+system.physmem.perBankRdBursts::1              114103                       # Per bank write bursts
+system.physmem.perBankRdBursts::2              116233                       # Per bank write bursts
+system.physmem.perBankRdBursts::3              117780                       # Per bank write bursts
+system.physmem.perBankRdBursts::4              117833                       # Per bank write bursts
+system.physmem.perBankRdBursts::5              117521                       # Per bank write bursts
 system.physmem.perBankRdBursts::6              119886                       # Per bank write bursts
-system.physmem.perBankRdBursts::7              124512                       # Per bank write bursts
-system.physmem.perBankRdBursts::8              126980                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              130096                       # Per bank write bursts
-system.physmem.perBankRdBursts::10             128651                       # Per bank write bursts
-system.physmem.perBankRdBursts::11             130358                       # Per bank write bursts
-system.physmem.perBankRdBursts::12             126070                       # Per bank write bursts
-system.physmem.perBankRdBursts::13             125261                       # Per bank write bursts
-system.physmem.perBankRdBursts::14             122591                       # Per bank write bursts
-system.physmem.perBankRdBursts::15             123183                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               61220                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               61482                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               60570                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               61238                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               61663                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               63102                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               64153                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               65613                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               65334                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               65779                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              65298                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              65646                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              64168                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              64213                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              64569                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              64185                       # Per bank write bursts
+system.physmem.perBankRdBursts::7              124520                       # Per bank write bursts
+system.physmem.perBankRdBursts::8              126974                       # Per bank write bursts
+system.physmem.perBankRdBursts::9              130087                       # Per bank write bursts
+system.physmem.perBankRdBursts::10             128649                       # Per bank write bursts
+system.physmem.perBankRdBursts::11             130350                       # Per bank write bursts
+system.physmem.perBankRdBursts::12             126060                       # Per bank write bursts
+system.physmem.perBankRdBursts::13             125237                       # Per bank write bursts
+system.physmem.perBankRdBursts::14             122580                       # Per bank write bursts
+system.physmem.perBankRdBursts::15             123195                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               61223                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               61486                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               60566                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               61239                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               61662                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               63100                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               64151                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               65612                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               65333                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               65776                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              65296                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              65642                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              64167                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              64207                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              64568                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              64186                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    1181827934500                       # Total gap between requests
+system.physmem.totGap                    1181971406500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                 1961052                       # Read request sizes (log2)
+system.physmem.readPktSize::6                 1961012                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                1018258                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                   1833401                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    126352                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                1018235                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                   1833489                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    126251                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::2                        18                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
@@ -140,28 +140,28 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                    31610                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                    33151                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    55452                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    59144                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    59934                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    59814                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    59766                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                    59740                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                    59781                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    59810                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    59797                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    59814                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                    60785                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                    60213                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    59934                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                    60699                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                    59435                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                    59248                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                       95                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                       17                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                        4                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                    31694                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                    33227                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                    55449                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                    59149                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                    59888                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    59833                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    59765                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    59757                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    59786                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    59783                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    59794                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    59834                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                    60768                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                    60180                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                    59898                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                    60650                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                    59424                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                    59239                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                       86                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                       10                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                        5                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
@@ -189,27 +189,27 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples      1832736                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      103.991479                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean      81.204587                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     130.379474                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127        1452314     79.24%     79.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255       263429     14.37%     93.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        49355      2.69%     96.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        20877      1.14%     97.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639        12925      0.71%     98.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         7130      0.39%     98.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         5386      0.29%     98.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         4144      0.23%     99.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        17176      0.94%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total        1832736                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         59244                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        33.077763                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      162.502392                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023          59205     99.93%     99.93% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-2047           11      0.02%     99.95% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2048-3071           12      0.02%     99.97% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::3072-4095            6      0.01%     99.98% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples      1832879                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      103.982912                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean      81.202772                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     130.375131                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127        1452262     79.23%     79.23% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255       263657     14.38%     93.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        49315      2.69%     96.31% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511        20815      1.14%     97.45% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639        12975      0.71%     98.15% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         7226      0.39%     98.55% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         5262      0.29%     98.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         4170      0.23%     99.06% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        17197      0.94%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total        1832879                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         59235                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        33.083110                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      163.258366                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023          59198     99.94%     99.94% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-2047           10      0.02%     99.95% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2048-3071           10      0.02%     99.97% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::3072-4095            7      0.01%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::4096-5119            3      0.01%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::5120-6143            1      0.00%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::6144-7167            1      0.00%     99.99% # Reads before turning the bus around for writes
@@ -217,96 +217,94 @@ system.physmem.rdPerTurnAround::8192-9215            1      0.00%     99.99% # R
 system.physmem.rdPerTurnAround::12288-13311            2      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::16384-17407            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::19456-20479            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           59244                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         59244                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        17.187108                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       17.151334                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        1.111623                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16              26003     43.89%     43.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17               1351      2.28%     46.17% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18              27334     46.14%     92.31% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19               4039      6.82%     99.13% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                439      0.74%     99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21                 54      0.09%     99.96% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total           59235                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         59235                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.189398                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       17.153834                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        1.107502                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16              25894     43.71%     43.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17               1328      2.24%     45.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18              27547     46.50%     92.46% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19               3948      6.66%     99.13% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                431      0.73%     99.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                 64      0.11%     99.96% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::22                 18      0.03%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23                  1      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24                  3      0.01%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::29                  1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::31                  1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           59244                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    36544904000                       # Total ticks spent queuing
-system.physmem.totMemAccLat               73290610250                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   9798855000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       18647.54                       # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::23                  4      0.01%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24                  1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           59235                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    36544529000                       # Total ticks spent queuing
+system.physmem.totMemAccLat               73289991500                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   9798790000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       18647.47                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  37397.54                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         106.13                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                          55.14                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                      106.20                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                       55.14                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  37397.47                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         106.11                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                          55.13                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                      106.18                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                       55.13                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           1.26                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.83                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.43                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.02                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        24.90                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     730029                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    415229                       # Number of row buffer hits during writes
+system.physmem.avgWrQLen                        24.78                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     729927                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    415160                       # Number of row buffer hits during writes
 system.physmem.readRowHitRate                   37.25                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  40.78                       # Row buffer hit rate for writes
-system.physmem.avgGap                       396678.40                       # Average gap between requests
-system.physmem.pageHitRate                      38.46                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE     386610550250                       # Time in different power states
-system.physmem.memoryStateTime::REF       39463580000                       # Time in different power states
+system.physmem.writeRowHitRate                  40.77                       # Row buffer hit rate for writes
+system.physmem.avgGap                       396734.95                       # Average gap between requests
+system.physmem.pageHitRate                      38.45                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE     385912942500                       # Time in different power states
+system.physmem.memoryStateTime::REF       39468520000                       # Time in different power states
 system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT      755746527250                       # Time in different power states
+system.physmem.memoryStateTime::ACT      756587133750                       # Time in different power states
 system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.membus.throughput                    161339749                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq             1181614                       # Transaction distribution
-system.membus.trans_dist::ReadResp            1181614                       # Transaction distribution
-system.membus.trans_dist::Writeback           1018258                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            779438                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           779438                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      4940362                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                4940362                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    190675840                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total           190675840                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus              190675840                       # Total data (bytes)
+system.membus.throughput                    161316754                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq             1181581                       # Transaction distribution
+system.membus.trans_dist::ReadResp            1181581                       # Transaction distribution
+system.membus.trans_dist::Writeback           1018235                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            779431                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           779431                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      4940259                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                4940259                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    190671808                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total           190671808                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus              190671808                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy         11933572000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy         11933364500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               1.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy        18494807500                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy        18494109500                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              1.6                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.branchPred.lookups               244429252                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         184894637                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect          15662499                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups            166226175                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits               163968290                       # Number of BTB hits
+system.cpu.branchPred.lookups               244428250                       # Number of BP lookups
+system.cpu.branchPred.condPredicted         184893435                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect          15662948                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups            166307436                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits               163975175                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             98.641679                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                18313425                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect              99980                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             98.597621                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                18313183                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect              99860                       # Number of incorrect RAS predictions.
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                    452571491                       # DTB read hits
-system.cpu.dtb.read_misses                    4982965                       # DTB read misses
+system.cpu.dtb.read_hits                    452570396                       # DTB read hits
+system.cpu.dtb.read_misses                    4982513                       # DTB read misses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                457554456                       # DTB read accesses
-system.cpu.dtb.write_hits                   161354418                       # DTB write hits
-system.cpu.dtb.write_misses                   1708765                       # DTB write misses
+system.cpu.dtb.read_accesses                457552909                       # DTB read accesses
+system.cpu.dtb.write_hits                   161353452                       # DTB write hits
+system.cpu.dtb.write_misses                   1708793                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses               163063183                       # DTB write accesses
-system.cpu.dtb.data_hits                    613925909                       # DTB hits
-system.cpu.dtb.data_misses                    6691730                       # DTB misses
+system.cpu.dtb.write_accesses               163062245                       # DTB write accesses
+system.cpu.dtb.data_hits                    613923848                       # DTB hits
+system.cpu.dtb.data_misses                    6691306                       # DTB misses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                620617639                       # DTB accesses
-system.cpu.itb.fetch_hits                   591482700                       # ITB hits
+system.cpu.dtb.data_accesses                620615154                       # DTB accesses
+system.cpu.itb.fetch_hits                   591487986                       # ITB hits
 system.cpu.itb.fetch_misses                        19                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses               591482719                       # ITB accesses
+system.cpu.itb.fetch_accesses               591488005                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -320,68 +318,68 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                   29                       # Number of system calls
-system.cpu.numCycles                       2363656089                       # number of cpu cycles simulated
+system.cpu.numCycles                       2363943033                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                  1826378509                       # Number of instructions committed
 system.cpu.committedOps                    1826378509                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                      49661954                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps                      49642925                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                               1.294176                       # CPI: cycles per instruction
-system.cpu.ipc                               0.772692                       # IPC: instructions per cycle
-system.cpu.tickCycles                      2043068356                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                       320587733                       # Total number of cycles that the object has spent stopped
+system.cpu.cpi                               1.294334                       # CPI: cycles per instruction
+system.cpu.ipc                               0.772598                       # IPC: instructions per cycle
+system.cpu.tickCycles                      2043545366                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                       320397667                       # Total number of cycles that the object has spent stopped
 system.cpu.icache.tags.replacements                 3                       # number of replacements
-system.cpu.icache.tags.tagsinuse           750.459785                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           591481743                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs               957                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          618058.247649                       # Average number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse           750.580892                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           591487028                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs               958                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          617418.609603                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   750.459785                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.366435                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.366435                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024          954                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_blocks::cpu.inst   750.580892                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.366495                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.366495                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          955                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           81                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4          873                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.465820                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses        1182966357                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses       1182966357                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    591481743                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       591481743                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     591481743                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        591481743                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    591481743                       # number of overall hits
-system.cpu.icache.overall_hits::total       591481743                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst          957                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total           957                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst          957                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total            957                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst          957                       # number of overall misses
-system.cpu.icache.overall_misses::total           957                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     70550250                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     70550250                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     70550250                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     70550250                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     70550250                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     70550250                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    591482700                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    591482700                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    591482700                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    591482700                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    591482700                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    591482700                       # number of overall (read+write) accesses
+system.cpu.icache.tags.age_task_id_blocks_1024::4          874                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.466309                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses        1182976930                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses       1182976930                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    591487028                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       591487028                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     591487028                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        591487028                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    591487028                       # number of overall hits
+system.cpu.icache.overall_hits::total       591487028                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          958                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           958                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          958                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            958                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          958                       # number of overall misses
+system.cpu.icache.overall_misses::total           958                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     69768750                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     69768750                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     69768750                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     69768750                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     69768750                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     69768750                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    591487986                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    591487986                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    591487986                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    591487986                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    591487986                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    591487986                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000002                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000002                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000002                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000002                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000002                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000002                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 73720.219436                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 73720.219436                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 73720.219436                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 73720.219436                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 73720.219436                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 73720.219436                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72827.505219                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 72827.505219                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 72827.505219                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 72827.505219                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 72827.505219                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 72827.505219                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -390,62 +388,62 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst          957                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total          957                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst          957                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total          957                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst          957                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total          957                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     68248750                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     68248750                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     68248750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     68248750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     68248750                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     68248750                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          958                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          958                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          958                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          958                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          958                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total          958                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     67467250                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     67467250                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     67467250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     67467250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     67467250                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     67467250                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000002                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000002                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000002                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71315.308255                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71315.308255                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71315.308255                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 71315.308255                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71315.308255                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 71315.308255                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70425.104384                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70425.104384                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70425.104384                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 70425.104384                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70425.104384                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 70425.104384                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.throughput               694662629                       # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq        7239687                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       7239687                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      3700672                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq      1887325                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp      1887325                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1914                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     21952782                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total          21954696                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        61248                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    820910528                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total      820971776                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus         820971776                       # Total data (bytes)
+system.cpu.toL2Bus.throughput               694575222                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq        7239698                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       7239698                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback      3700613                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq      1887316                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp      1887316                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1916                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     21952725                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total          21954641                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        61312                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    820906816                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total      820968128                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus         820968128                       # Total data (bytes)
 system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy    10114514000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.occupancy    10114426500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.9                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy       1629250                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy       1629750                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy   14012964250                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy   14012910250                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          1.2                       # Layer utilization (%)
-system.cpu.l2cache.tags.replacements          1928316                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        30739.409036                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            8981710                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs          1958121                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             4.586902                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements          1928276                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        30739.606267                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            8981702                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs          1958081                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             4.586992                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle      88667368250                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 14930.422883                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 15808.986154                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.455640                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.482452                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.938092                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::writebacks 14931.057799                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 15808.548467                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.455660                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.482439                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.938098                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024        29805                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0          167                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::1           21                       # Occupied blocks per task id
@@ -453,60 +451,60 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2         1232
 system.cpu.l2cache.tags.age_task_id_blocks_1024::3        12869                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::4        15516                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.909576                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses        106466918                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses       106466918                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst      6058073                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        6058073                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks      3700672                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      3700672                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.inst      1107887                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total      1107887                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst      7165960                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         7165960                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst      7165960                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        7165960                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst      1181614                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total      1181614                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.inst       779438                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       779438                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst      1961052                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total       1961052                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst      1961052                       # number of overall misses
-system.cpu.l2cache.overall_misses::total      1961052                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst  94264990000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total  94264990000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst  62866370000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total  62866370000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 157131360000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 157131360000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 157131360000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 157131360000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst      7239687                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total      7239687                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks      3700672                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total      3700672                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.inst      1887325                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total      1887325                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst      9127012                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      9127012                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst      9127012                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      9127012                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.163213                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.163213                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst     0.412986                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.412986                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.214862                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.214862                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.214862                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.214862                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 79776.466765                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 79776.466765                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 80656.023956                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80656.023956                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80126.054791                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 80126.054791                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80126.054791                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 80126.054791                       # average overall miss latency
+system.cpu.l2cache.tags.tag_accesses        106466413                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses       106466413                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.inst      6058117                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total        6058117                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks      3700613                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total      3700613                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.inst      1107885                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total      1107885                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst      7166002                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         7166002                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst      7166002                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        7166002                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst      1181581                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total      1181581                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.inst       779431                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       779431                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst      1961012                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total       1961012                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst      1961012                       # number of overall misses
+system.cpu.l2cache.overall_misses::total      1961012                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst  94257909250                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total  94257909250                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst  62870670250                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total  62870670250                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 157128579500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 157128579500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 157128579500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 157128579500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst      7239698                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total      7239698                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks      3700613                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total      3700613                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.inst      1887316                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total      1887316                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst      9127014                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      9127014                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst      9127014                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      9127014                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.163209                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.163209                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst     0.412984                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.412984                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.214858                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.214858                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.214858                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.214858                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 79772.702210                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 79772.702210                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 80662.265486                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80662.265486                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80126.271282                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 80126.271282                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80126.271282                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 80126.271282                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -515,90 +513,90 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks      1018258                       # number of writebacks
-system.cpu.l2cache.writebacks::total          1018258                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst      1181614                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total      1181614                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst       779438                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       779438                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst      1961052                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total      1961052                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst      1961052                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total      1961052                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst  79403793000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total  79403793000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst  53024408000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  53024408000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 132428201000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 132428201000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 132428201000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 132428201000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.163213                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.163213                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst     0.412986                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.412986                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.214862                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.214862                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.214862                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.214862                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67199.434841                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67199.434841                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 68029.026042                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68029.026042                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67529.163429                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67529.163429                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67529.163429                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67529.163429                       # average overall mshr miss latency
+system.cpu.l2cache.writebacks::writebacks      1018235                       # number of writebacks
+system.cpu.l2cache.writebacks::total          1018235                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst      1181581                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total      1181581                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst       779431                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       779431                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst      1961012                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total      1961012                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst      1961012                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total      1961012                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst  79397427250                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total  79397427250                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst  53028861750                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  53028861750                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 132426289000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 132426289000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 132426289000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 132426289000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.163209                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.163209                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst     0.412984                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.412984                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.214858                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.214858                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.214858                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.214858                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67195.924147                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67195.924147                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 68035.351109                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68035.351109                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67529.565857                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67529.565857                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67529.565857                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67529.565857                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements           9121959                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4080.549274                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           599881153                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           9126055                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             65.732801                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.replacements           9121960                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4080.551150                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           599880175                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           9126056                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             65.732686                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle       16715078000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.inst  4080.549274                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_blocks::cpu.inst  4080.551150                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.inst     0.996228                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.996228                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0          103                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1         1621                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2         2308                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1         1617                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2         2312                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::3           64                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses        1227943655                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses       1227943655                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.inst    441390753                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       441390753                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.inst    158490400                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      158490400                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.inst     599881153                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        599881153                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.inst    599881153                       # number of overall hits
-system.cpu.dcache.overall_hits::total       599881153                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.inst      7289545                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       7289545                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.inst      2238102                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      2238102                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.inst      9527647                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        9527647                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.inst      9527647                       # number of overall misses
-system.cpu.dcache.overall_misses::total       9527647                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.inst 177999429500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 177999429500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.inst 100859304250                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 100859304250                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.inst 278858733750                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 278858733750                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.inst 278858733750                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 278858733750                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.inst    448680298                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    448680298                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.tags.tag_accesses        1227941810                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses       1227941810                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.inst    441389836                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       441389836                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.inst    158490339                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      158490339                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.inst     599880175                       # number of demand (read+write) hits
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+system.cpu.dcache.overall_hits::total       599880175                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.inst      7289539                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       7289539                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.inst      2238163                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      2238163                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.inst      9527702                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        9527702                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.inst      9527702                       # number of overall misses
+system.cpu.dcache.overall_misses::total       9527702                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.inst 177992802750                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 177992802750                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.inst 100871241750                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 100871241750                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.inst 278864044500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 278864044500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.inst 278864044500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 278864044500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.inst    448679375                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    448679375                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.inst    160728502                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total    160728502                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.inst    609408800                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    609408800                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.inst    609408800                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    609408800                       # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.inst    609407877                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    609407877                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.inst    609407877                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    609407877                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.inst     0.016247                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.016247                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.inst     0.013925                       # miss rate for WriteReq accesses
@@ -607,14 +605,14 @@ system.cpu.dcache.demand_miss_rate::cpu.inst     0.015634
 system.cpu.dcache.demand_miss_rate::total     0.015634                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.inst     0.015634                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.015634                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 24418.455404                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 24418.455404                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 45064.659363                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 45064.659363                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.inst 29268.373792                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 29268.373792                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.inst 29268.373792                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 29268.373792                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 24417.566426                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 24417.566426                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 45068.764764                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 45068.764764                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.inst 29268.762237                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 29268.762237                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.inst 29268.762237                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 29268.762237                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -623,32 +621,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      3700672                       # number of writebacks
-system.cpu.dcache.writebacks::total           3700672                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.inst        50815                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total        50815                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.inst       350777                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       350777                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.inst       401592                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       401592                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.inst       401592                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       401592                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.inst      7238730                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      7238730                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.inst      1887325                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total      1887325                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.inst      9126055                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      9126055                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.inst      9126055                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      9126055                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 162033829750                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 162033829750                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst  75893768500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  75893768500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 237927598250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 237927598250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 237927598250                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 237927598250                       # number of overall MSHR miss cycles
+system.cpu.dcache.writebacks::writebacks      3700613                       # number of writebacks
+system.cpu.dcache.writebacks::total           3700613                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.inst        50799                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total        50799                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.inst       350847                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       350847                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.inst       401646                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       401646                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.inst       401646                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       401646                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.inst      7238740                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      7238740                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.inst      1887316                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total      1887316                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.inst      9126056                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      9126056                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.inst      9126056                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      9126056                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 162027926000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 162027926000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst  75898088250                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  75898088250                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 237926014250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 237926014250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 237926014250                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 237926014250                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst     0.016133                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.016133                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst     0.011742                       # mshr miss rate for WriteReq accesses
@@ -657,14 +655,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.inst     0.014975
 system.cpu.dcache.demand_mshr_miss_rate::total     0.014975                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.inst     0.014975                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.014975                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 22384.289751                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22384.289751                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 40212.347370                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40212.347370                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 26071.243078                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 26071.243078                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 26071.243078                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 26071.243078                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 22383.443251                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22383.443251                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 40214.827962                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40214.827962                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 26071.066652                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 26071.066652                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 26071.066652                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 26071.066652                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
index a090e3fd8..87bb9f534 100644
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,108 +1,108 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.679350                       # Number of seconds simulated
-sim_ticks                                679349778000                       # Number of ticks simulated
-final_tick                               679349778000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.661836                       # Number of seconds simulated
+sim_ticks                                661835607000                       # Number of ticks simulated
+final_tick                               661835607000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 176355                       # Simulator instruction rate (inst/s)
-host_op_rate                                   176355                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               69011357                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 223060                       # Number of bytes of host memory used
-host_seconds                                  9844.03                       # Real time elapsed on the host
+host_inst_rate                                 129941                       # Simulator instruction rate (inst/s)
+host_op_rate                                   129941                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               49537566                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 237180                       # Number of bytes of host memory used
+host_seconds                                 13360.28                       # Real time elapsed on the host
 sim_insts                                  1736043781                       # Number of instructions simulated
 sim_ops                                    1736043781                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst             61824                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data         125814720                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            125876544                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        61824                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           61824                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     65265856                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          65265856                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst                966                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data            1965855                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1966821                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1019779                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1019779                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst                91005                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            185198736                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               185289740                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst           91005                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total              91005                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          96071064                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               96071064                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          96071064                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst               91005                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           185198736                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              281360804                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                       1966821                       # Number of read requests accepted
-system.physmem.writeReqs                      1019779                       # Number of write requests accepted
-system.physmem.readBursts                     1966821                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                    1019779                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                125795136                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     81408                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  65264000                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                 125876544                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               65265856                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                     1272                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytes_read::cpu.inst             61952                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data         125980800                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            126042752                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        61952                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           61952                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     65306880                       # Number of bytes written to this memory
+system.physmem.bytes_written::total          65306880                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst                968                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data            1968450                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               1969418                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1020420                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total              1020420                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst                93606                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            190350593                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               190444199                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst           93606                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total              93606                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          98675380                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               98675380                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          98675380                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst               93606                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           190350593                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              289119579                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                       1969418                       # Number of read requests accepted
+system.physmem.writeReqs                      1020420                       # Number of write requests accepted
+system.physmem.readBursts                     1969418                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                    1020420                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                125960256                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     82496                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  65304896                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                 126042752                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               65306880                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                     1289                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0              118990                       # Per bank write bursts
-system.physmem.perBankRdBursts::1              114401                       # Per bank write bursts
-system.physmem.perBankRdBursts::2              116526                       # Per bank write bursts
-system.physmem.perBankRdBursts::3              118038                       # Per bank write bursts
-system.physmem.perBankRdBursts::4              118100                       # Per bank write bursts
-system.physmem.perBankRdBursts::5              117781                       # Per bank write bursts
-system.physmem.perBankRdBursts::6              120191                       # Per bank write bursts
-system.physmem.perBankRdBursts::7              124916                       # Per bank write bursts
-system.physmem.perBankRdBursts::8              127523                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              130444                       # Per bank write bursts
-system.physmem.perBankRdBursts::10             129055                       # Per bank write bursts
-system.physmem.perBankRdBursts::11             130769                       # Per bank write bursts
-system.physmem.perBankRdBursts::12             126629                       # Per bank write bursts
-system.physmem.perBankRdBursts::13             125625                       # Per bank write bursts
-system.physmem.perBankRdBursts::14             122929                       # Per bank write bursts
-system.physmem.perBankRdBursts::15             123632                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               61276                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               61573                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               60655                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               61329                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               61751                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               63183                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               64216                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               65714                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               65484                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               65866                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              65407                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              65735                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              64310                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              64307                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              64646                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              64298                       # Per bank write bursts
+system.physmem.perBankRdBursts::0              119133                       # Per bank write bursts
+system.physmem.perBankRdBursts::1              114512                       # Per bank write bursts
+system.physmem.perBankRdBursts::2              116620                       # Per bank write bursts
+system.physmem.perBankRdBursts::3              118156                       # Per bank write bursts
+system.physmem.perBankRdBursts::4              118267                       # Per bank write bursts
+system.physmem.perBankRdBursts::5              117901                       # Per bank write bursts
+system.physmem.perBankRdBursts::6              120342                       # Per bank write bursts
+system.physmem.perBankRdBursts::7              125056                       # Per bank write bursts
+system.physmem.perBankRdBursts::8              127675                       # Per bank write bursts
+system.physmem.perBankRdBursts::9              130585                       # Per bank write bursts
+system.physmem.perBankRdBursts::10             129305                       # Per bank write bursts
+system.physmem.perBankRdBursts::11             130922                       # Per bank write bursts
+system.physmem.perBankRdBursts::12             126863                       # Per bank write bursts
+system.physmem.perBankRdBursts::13             125867                       # Per bank write bursts
+system.physmem.perBankRdBursts::14             123079                       # Per bank write bursts
+system.physmem.perBankRdBursts::15             123846                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               61299                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               61588                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               60677                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               61353                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               61807                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               63207                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               64256                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               65745                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               65527                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               65905                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              65467                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              65774                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              64405                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              64356                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              64678                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              64345                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    679349688500                       # Total gap between requests
+system.physmem.totGap                    661835517500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                 1966821                       # Read request sizes (log2)
+system.physmem.readPktSize::6                 1969418                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                1019779                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                   1643770                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    225726                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     72200                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                     23834                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                        17                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                         2                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                1020420                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                   1619695                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    248396                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     75753                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                     24266                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                        18                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
@@ -144,39 +144,39 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                    28029                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                    29643                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    50000                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    56258                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    59169                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    60158                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    60388                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                    60609                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                    60716                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    61035                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    61226                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    61677                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                    63137                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                    63948                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    61422                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                    62019                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                    60448                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                    59666                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      135                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                       37                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                       15                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                    27847                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                    29428                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                    49632                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                    56164                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                    59203                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    60208                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    60474                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    60709                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    60907                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    61095                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    61301                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    61745                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                    63276                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                    64246                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                    61504                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                    62091                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                    60589                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                    59740                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      161                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                       48                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                       18                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::36                        6                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::37                        4                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                        4                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                        3                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                        2                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                        3                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::43                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
@@ -193,125 +193,132 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples      1771721                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      107.836103                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean      82.953832                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     137.029832                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127        1375665     77.65%     77.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255       272762     15.40%     93.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        53440      3.02%     96.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        21316      1.20%     97.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639        12827      0.72%     97.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         6576      0.37%     98.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         5044      0.28%     98.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         3861      0.22%     98.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        20230      1.14%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total        1771721                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         59588                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        32.942421                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      164.012858                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023          59550     99.94%     99.94% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-2047           12      0.02%     99.96% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2048-3071           13      0.02%     99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::3072-4095            4      0.01%     99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::4096-5119            2      0.00%     99.99% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples      1772142                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      107.926701                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean      82.988600                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     137.225720                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127        1375537     77.62%     77.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255       272696     15.39%     93.01% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        53852      3.04%     96.05% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511        21473      1.21%     97.26% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639        12850      0.73%     97.98% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         6581      0.37%     98.35% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         4855      0.27%     98.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         3761      0.21%     98.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        20537      1.16%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total        1772142                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         59644                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        32.954195                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      163.722438                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023          59607     99.94%     99.94% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-2047           13      0.02%     99.96% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2048-3071            6      0.01%     99.97% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::3072-4095            8      0.01%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::4096-5119            3      0.01%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::5120-6143            1      0.00%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::6144-7167            1      0.00%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::10240-11263            1      0.00%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::12288-13311            2      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::16384-17407            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::19456-20479            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           59588                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         59588                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        17.113345                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       17.071670                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        1.230173                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-17           30977     51.99%     51.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18-19           27509     46.17%     98.15% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-21            1030      1.73%     99.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22-23              43      0.07%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-25               8      0.01%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26-27               4      0.01%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-29               2      0.00%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::30-31              11      0.02%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-33               1      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::34-35               1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::42-43               1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-77               1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           59588                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    40014194750                       # Total ticks spent queuing
-system.physmem.totMemAccLat               76868238500                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   9827745000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       20357.77                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total           59644                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         59644                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.107991                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       17.066184                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        1.220335                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16              29768     49.91%     49.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17               1416      2.37%     52.28% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18              22411     37.57%     89.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19               4939      8.28%     98.14% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                872      1.46%     99.60% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                162      0.27%     99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22                 31      0.05%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23                 10      0.02%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24                  7      0.01%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26                  1      0.00%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::27                  3      0.01%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28                  1      0.00%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::29                  1      0.00%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::30                  2      0.00%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::31                 10      0.02%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32                  4      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::33                  2      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::34                  3      0.01%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::38                  1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           59644                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    40394853000                       # Total ticks spent queuing
+system.physmem.totMemAccLat               77297271750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   9840645000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       20524.49                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  39107.77                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         185.17                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                          96.07                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                      185.29                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                       96.07                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  39274.49                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         190.32                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                          98.67                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                      190.44                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                       98.68                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           2.20                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       1.45                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.75                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.09                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        25.15                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     795833                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    417735                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   40.49                       # Row buffer hit rate for reads
+system.physmem.busUtil                           2.26                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       1.49                       # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite                      0.77                       # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen                         1.10                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        24.96                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     798370                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    417997                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   40.56                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                  40.96                       # Row buffer hit rate for writes
-system.physmem.avgGap                       227465.91                       # Average gap between requests
-system.physmem.pageHitRate                      40.65                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE     134374460000                       # Time in different power states
-system.physmem.memoryStateTime::REF       22684740000                       # Time in different power states
+system.physmem.avgGap                       221361.66                       # Average gap between requests
+system.physmem.pageHitRate                      40.70                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE     126237669000                       # Time in different power states
+system.physmem.memoryStateTime::REF       22100000000                       # Time in different power states
 system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT      522286376500                       # Time in different power states
+system.physmem.memoryStateTime::ACT      513493900500                       # Time in different power states
 system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.membus.throughput                    281360804                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq             1191893                       # Transaction distribution
-system.membus.trans_dist::ReadResp            1191893                       # Transaction distribution
-system.membus.trans_dist::Writeback           1019779                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            774928                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           774928                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      4953421                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                4953421                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    191142400                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total           191142400                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus              191142400                       # Total data (bytes)
+system.membus.throughput                    289119579                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq             1198182                       # Transaction distribution
+system.membus.trans_dist::ReadResp            1198182                       # Transaction distribution
+system.membus.trans_dist::Writeback           1020420                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            771236                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           771236                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      4959256                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                4959256                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    191349632                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total           191349632                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus              191349632                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy         11809306000                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               1.7                       # Layer utilization (%)
-system.membus.respLayer1.occupancy        18437139750                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              2.7                       # Layer utilization (%)
+system.membus.reqLayer0.occupancy         11823202500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               1.8                       # Layer utilization (%)
+system.membus.respLayer1.occupancy        18425039000                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization              2.8                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.branchPred.lookups               390516660                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         303583970                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect          16113462                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups            268537122                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits               266026822                       # Number of BTB hits
+system.cpu.branchPred.lookups               410520712                       # Number of BP lookups
+system.cpu.branchPred.condPredicted         318849760                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect          16265290                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups            282927738                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits               279343276                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             99.065194                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                25282995                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect               3069                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             98.733082                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                26370791                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect                 17                       # Number of incorrect RAS predictions.
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                    621222786                       # DTB read hits
-system.cpu.dtb.read_misses                   11503040                       # DTB read misses
+system.cpu.dtb.read_hits                    646139057                       # DTB read hits
+system.cpu.dtb.read_misses                   12159875                       # DTB read misses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                632725826                       # DTB read accesses
-system.cpu.dtb.write_hits                   213831979                       # DTB write hits
-system.cpu.dtb.write_misses                   7254265                       # DTB write misses
+system.cpu.dtb.read_accesses                658298932                       # DTB read accesses
+system.cpu.dtb.write_hits                   218185834                       # DTB write hits
+system.cpu.dtb.write_misses                   7515423                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses               221086244                       # DTB write accesses
-system.cpu.dtb.data_hits                    835054765                       # DTB hits
-system.cpu.dtb.data_misses                   18757305                       # DTB misses
+system.cpu.dtb.write_accesses               225701257                       # DTB write accesses
+system.cpu.dtb.data_hits                    864324891                       # DTB hits
+system.cpu.dtb.data_misses                   19675298                       # DTB misses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                853812070                       # DTB accesses
-system.cpu.itb.fetch_hits                   400046189                       # ITB hits
+system.cpu.dtb.data_accesses                884000189                       # DTB accesses
+system.cpu.itb.fetch_hits                   422443679                       # ITB hits
 system.cpu.itb.fetch_misses                        44                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses               400046233                       # ITB accesses
+system.cpu.itb.fetch_accesses               422443723                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -325,239 +332,238 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                   29                       # Number of system calls
-system.cpu.numCycles                       1358699557                       # number of cpu cycles simulated
+system.cpu.numCycles                       1323671215                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles          410929991                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                     3243314345                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                   390516660                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches          291309817                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     589336372                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles               147340013                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles              133548447                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                  141                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles          1456                       # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles           18                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                 400046189                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes               9025513                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples         1257254668                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.579680                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.173136                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles          433730630                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                     3419498139                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   410520712                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches          305714067                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     866879802                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                45990094                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles                   88                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles          1786                       # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles           51                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                 422443679                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               8426079                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples         1323607404                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.583469                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.158025                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                667918296     53.13%     53.13% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 44267394      3.52%     56.65% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 22207289      1.77%     58.41% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 40636739      3.23%     61.64% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                131869370     10.49%     72.13% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                 62966774      5.01%     77.14% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                 40227274      3.20%     80.34% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                 28245094      2.25%     82.59% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                218916438     17.41%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                696600974     52.63%     52.63% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 48023746      3.63%     56.26% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 24394821      1.84%     58.10% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 45250405      3.42%     61.52% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                142990505     10.80%     72.32% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                 66206181      5.00%     77.32% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                 43787822      3.31%     80.63% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                 29609921      2.24%     82.87% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                226743029     17.13%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total           1257254668                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.287419                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        2.387072                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                430550615                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             129659255                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 568815009                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               4792365                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles              123437424                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved             59500767                       # Number of times decode resolved a branch
+system.cpu.fetch.rateDist::total           1323607404                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.310138                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        2.583344                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                355560821                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             384357689                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 525784970                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              34909729                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles               22994195                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved             62281773                       # Number of times decode resolved a branch
 system.cpu.decode.BranchMispred                   917                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts             3153748807                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                  2128                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles              123437424                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                446386402                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                61779163                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles           6860                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 557518816                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              68126003                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts             3069486898                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents               1505727                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                6123879                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents               54202488                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                8466199                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands          2295837862                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            3983545178                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       3983398130                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups            147047                       # Number of floating rename lookups
+system.cpu.decode.DecodedInsts             3264096854                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                  2212                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles               22994195                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                373922324                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles               204910686                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles           7734                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 538718918                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles             183053547                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts             3181111000                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents               1787853                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents               18972686                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents              140245391                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents               27858899                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands          2377395421                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            4126748897                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       4126578364                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups            170532                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps            1376202963                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                919634899                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts                203                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts            202                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  44876150                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            692163471                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores           260495859                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads          73383628                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores         38808502                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                 2780183806                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                 184                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                2536585762                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued           4364880                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined      1034533664                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined    460650584                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved            155                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples    1257254668                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         2.017559                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        2.009997                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps               1001192458                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts                212                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts            209                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  99259627                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            719210617                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           272896274                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          90779805                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         59022559                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                 2889836484                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                 194                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                2624050349                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued           1575226                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined      1139401909                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined    505657216                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved            165                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples    1323607404                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.982499                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        2.151238                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           428157011     34.05%     34.05% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1           188380197     14.98%     49.04% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2           177998596     14.16%     63.20% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3           153960413     12.25%     75.44% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4           135215337     10.75%     86.20% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5            80818226      6.43%     92.62% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6            69593138      5.54%     98.16% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7            17238172      1.37%     99.53% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8             5893578      0.47%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           519394281     39.24%     39.24% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           169344121     12.79%     52.03% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2           158328435     11.96%     64.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3           149155945     11.27%     75.27% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4           126186051      9.53%     84.80% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            84451720      6.38%     91.18% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6            68205907      5.15%     96.33% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7            33984275      2.57%     98.90% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8            14556669      1.10%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total      1257254668                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total      1323607404                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                 2760636     13.79%     13.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%     13.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     13.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     13.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     13.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     13.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     13.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     13.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     13.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     13.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     13.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     13.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     13.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     13.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     13.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     13.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     13.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     13.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     13.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     13.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     13.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     13.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     13.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     13.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     13.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     13.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     13.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     13.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     13.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead               12853797     64.19%     77.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite               4410220     22.02%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                13175247     35.70%     35.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%     35.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     35.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     35.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     35.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     35.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     35.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     35.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     35.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     35.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     35.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     35.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     35.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     35.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     35.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     35.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     35.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     35.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     35.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     35.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     35.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     35.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     35.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     35.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     35.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     35.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     35.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     35.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     35.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead               19116655     51.79%     87.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               4618094     12.51%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu            1663143410     65.57%     65.57% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                   98      0.00%     65.57% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     65.57% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                 259      0.00%     65.57% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                  15      0.00%     65.57% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                 165      0.00%     65.57% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                 21      0.00%     65.57% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                  24      0.00%     65.57% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     65.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     65.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     65.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     65.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     65.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     65.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     65.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     65.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     65.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     65.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     65.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     65.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     65.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     65.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     65.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     65.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     65.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     65.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     65.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     65.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     65.57% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            647516942     25.53%     91.09% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite           225924828      8.91%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu            1719340504     65.52%     65.52% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                  109      0.00%     65.52% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     65.52% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd              896937      0.03%     65.56% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                  19      0.00%     65.56% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                 170      0.00%     65.56% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                 34      0.00%     65.56% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                  25      0.00%     65.56% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     65.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     65.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     65.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     65.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     65.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     65.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     65.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     65.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     65.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     65.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     65.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     65.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     65.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     65.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     65.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     65.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     65.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     65.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     65.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     65.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     65.56% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            672950109     25.65%     91.20% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite           230862442      8.80%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total             2536585762                       # Type of FU issued
-system.cpu.iq.rate                           1.866922                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                    20024653                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.007894                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         6352883505                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes        3813585390                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses   2440929650                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads             1932220                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes            1252073                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses       864209                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses             2555655812                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                  954603                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads         64558247                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total             2624050349                       # Type of FU issued
+system.cpu.iq.rate                           1.982403                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    36909996                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.014066                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         6608212970                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes        4028086926                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses   2521962769                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads             1980354                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes            1298007                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses       893087                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses             2659977012                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                  983333                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads         69535121                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads    247567808                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses       343004                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation       121628                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores     99767357                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads    274614954                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses       379465                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation       148696                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores    112167772                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads          225                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked       1607198                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads          269                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked       6022963                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles              123437424                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                22713536                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles               8297734                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts          2923674181                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts           8955846                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             692163471                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts            260495859                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts                184                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                 449856                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents               8304684                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents         121628                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect       10428435                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect      8597760                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts             19026195                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts            2492121408                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             632726353                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts          44464354                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles               22994195                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles               147722049                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles              18412868                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts          3041056525                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts           6683505                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             719210617                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts            272896274                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts                194                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                 821771                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents              17859213                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents         148696                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect       10896298                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      8844115                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts             19740413                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts            2578377980                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             658298938                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          45672369                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                     143490191                       # number of nop insts executed
-system.cpu.iew.exec_refs                    853812632                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                304222027                       # Number of branches executed
-system.cpu.iew.exec_stores                  221086279                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.834196                       # Inst execution rate
-system.cpu.iew.wb_sent                     2470047897                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                    2441793859                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                1422096892                       # num instructions producing a value
-system.cpu.iew.wb_consumers                1830175974                       # num instructions consuming a value
+system.cpu.iew.exec_nop                     151219847                       # number of nop insts executed
+system.cpu.iew.exec_refs                    884000267                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                315975248                       # Number of branches executed
+system.cpu.iew.exec_stores                  225701329                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.947899                       # Inst execution rate
+system.cpu.iew.wb_sent                     2552852780                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                    2522855856                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                1489309006                       # num instructions producing a value
+system.cpu.iew.wb_consumers                1920624303                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.797155                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.777027                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.905954                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.775430                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts       873443731                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts      1005196168                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls              29                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts          16112643                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples   1133817244                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.605003                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.541695                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts          16264438                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples   1184721059                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.536041                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.558766                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    625261340     55.15%     55.15% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1    171314027     15.11%     70.26% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     86268180      7.61%     77.86% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     54871559      4.84%     82.70% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     31288205      2.76%     85.46% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5     20767631      1.83%     87.30% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6     23576751      2.08%     89.37% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7     22892827      2.02%     91.39% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     97576724      8.61%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    695617998     58.72%     58.72% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    159800446     13.49%     72.20% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     79745623      6.73%     78.94% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     52150996      4.40%     83.34% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     28466079      2.40%     85.74% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5     19402088      1.64%     87.38% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6     20010452      1.69%     89.07% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7     23121038      1.95%     91.02% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8    106406339      8.98%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total   1133817244                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total   1184721059                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts           1819780126                       # Number of instructions committed
 system.cpu.commit.committedOps             1819780126                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -569,10 +575,10 @@ system.cpu.commit.fp_insts                     805525                       # Nu
 system.cpu.commit.int_insts                1718967519                       # Number of committed integer instructions.
 system.cpu.commit.function_calls             16767440                       # Number of function calls committed.
 system.cpu.commit.op_class_0::No_OpClass     83736345      4.60%      4.60% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu       1130719227     62.13%     66.74% # Class of committed instruction
-system.cpu.commit.op_class_0::IntMult              75      0.00%     66.74% # Class of committed instruction
-system.cpu.commit.op_class_0::IntDiv                0      0.00%     66.74% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatAdd            166      0.00%     66.74% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu       1129914149     62.09%     66.69% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult              75      0.00%     66.69% # Class of committed instruction
+system.cpu.commit.op_class_0::IntDiv                0      0.00%     66.69% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatAdd         805244      0.04%     66.74% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatCmp             13      0.00%     66.74% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatCvt            100      0.00%     66.74% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatMult            11      0.00%     66.74% # Class of committed instruction
@@ -603,224 +609,225 @@ system.cpu.commit.op_class_0::MemWrite      160728502      8.83%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total        1819780126                       # Class of committed instruction
-system.cpu.commit.bw_lim_events              97576724                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events             106406339                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                   3643685177                       # The number of ROB reads
-system.cpu.rob.rob_writes                  5509997541                       # The number of ROB writes
-system.cpu.timesIdled                         1119552                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                       101444889                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads                   3817511814                       # The number of ROB reads
+system.cpu.rob.rob_writes                  5788973646                       # The number of ROB writes
+system.cpu.timesIdled                             715                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           63811                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                  1736043781                       # Number of Instructions Simulated
 system.cpu.committedOps                    1736043781                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               0.782641                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.782641                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.277725                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.277725                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               3354502670                       # number of integer regfile reads
-system.cpu.int_regfile_writes              1955490145                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                     31250                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                      519                       # number of floating regfile writes
+system.cpu.cpi                               0.762464                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.762464                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.311537                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.311537                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               3467668910                       # number of integer regfile reads
+system.cpu.int_regfile_writes              2022324472                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                     45289                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                      607                       # number of floating regfile writes
 system.cpu.misc_regfile_reads                      25                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
-system.cpu.toL2Bus.throughput              1216162152                       # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq        7299986                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       7299986                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      3725797                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq      1883584                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp      1883584                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1932                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     22091005                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total          22092937                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        61824                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    826137664                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total      826199488                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus         826199488                       # Total data (bytes)
+system.cpu.toL2Bus.throughput              1252958492                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq        7335196                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       7335196                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback      3742782                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq      1879093                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp      1879093                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1936                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     22169424                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total          22171360                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        61952                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    829190592                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total      829252544                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus         829252544                       # Total data (bytes)
 system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy    10180553427                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.occupancy    10221470348                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          1.5                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy       1609000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy       1613250                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy   14076007750                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy   14118250749                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          2.1                       # Layer utilization (%)
 system.cpu.icache.tags.replacements                 1                       # number of replacements
-system.cpu.icache.tags.tagsinuse           775.530288                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           400044658                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs               966                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          414124.904762                       # Average number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse           769.518205                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           422442162                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs               968                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          436407.192149                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   775.530288                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.378677                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.378677                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024          965                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           52                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_blocks::cpu.inst   769.518205                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.375741                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.375741                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          967                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           65                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1            1                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4          912                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.471191                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         800093342                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        800093342                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    400044658                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       400044658                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     400044658                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        400044658                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    400044658                       # number of overall hits
-system.cpu.icache.overall_hits::total       400044658                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst         1530                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total          1530                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst         1530                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total           1530                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst         1530                       # number of overall misses
-system.cpu.icache.overall_misses::total          1530                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    107584749                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    107584749                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    107584749                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    107584749                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    107584749                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    107584749                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    400046188                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    400046188                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    400046188                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    400046188                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    400046188                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    400046188                       # number of overall (read+write) accesses
+system.cpu.icache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4          900                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.472168                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses         844888324                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        844888324                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    422442162                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       422442162                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     422442162                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        422442162                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    422442162                       # number of overall hits
+system.cpu.icache.overall_hits::total       422442162                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         1516                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          1516                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         1516                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           1516                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         1516                       # number of overall misses
+system.cpu.icache.overall_misses::total          1516                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    105797750                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    105797750                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    105797750                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    105797750                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    105797750                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    105797750                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    422443678                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    422443678                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    422443678                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    422443678                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    422443678                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    422443678                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000004                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000004                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000004                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000004                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000004                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000004                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70316.829412                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 70316.829412                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 70316.829412                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 70316.829412                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 70316.829412                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 70316.829412                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs          293                       # number of cycles access was blocked
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69787.434037                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 69787.434037                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 69787.434037                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 69787.434037                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 69787.434037                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 69787.434037                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs          455                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                 6                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 7                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    48.833333                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs           65                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst          564                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total          564                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst          564                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total          564                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst          564                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total          564                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst          966                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total          966                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst          966                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total          966                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst          966                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total          966                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     73366499                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     73366499                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     73366499                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     73366499                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     73366499                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     73366499                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst          548                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total          548                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst          548                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total          548                       # number of demand (read+write) MSHR hits
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+system.cpu.icache.overall_mshr_hits::total          548                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          968                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          968                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          968                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          968                       # number of demand (read+write) MSHR misses
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+system.cpu.icache.overall_mshr_misses::total          968                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     72550750                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     72550750                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     72550750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     72550750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     72550750                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     72550750                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000002                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000002                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000002                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75948.756729                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75948.756729                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75948.756729                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 75948.756729                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75948.756729                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 75948.756729                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74949.121901                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74949.121901                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74949.121901                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 74949.121901                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74949.121901                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 74949.121901                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements          1934120                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        31423.856311                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            9061358                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs          1963896                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             4.613970                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle      28109033750                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 14558.709173                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst    26.630498                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 16838.516639                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.444297                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.000813                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.513871                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.958980                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        29776                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          153                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          973                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          595                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3        17352                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        10703                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.908691                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses        107122416                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses       107122416                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.data      6108093                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        6108093                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks      3725797                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      3725797                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data      1108656                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total      1108656                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.data      7216749                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         7216749                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.data      7216749                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        7216749                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst          966                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data      1190927                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total      1191893                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       774928                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       774928                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst          966                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data      1965855                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total       1966821                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst          966                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data      1965855                       # number of overall misses
-system.cpu.l2cache.overall_misses::total      1966821                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     72391000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data  97891621750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total  97964012750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  63926223998                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total  63926223998                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     72391000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 161817845748                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 161890236748                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     72391000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 161817845748                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 161890236748                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst          966                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data      7299020                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total      7299986                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks      3725797                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total      3725797                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data      1883584                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total      1883584                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst          966                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      9182604                       # number of demand (read+write) accesses
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+system.cpu.l2cache.tags.tagsinuse        31406.356645                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            9110956                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs          1966492                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             4.633101                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle      27876219500                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 14556.001230                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst    26.874303                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 16823.481112                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.444214                       # Average percentage of cache occupancy
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+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        10379                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.909058                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses        107502153                       # Number of tag accesses
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+system.cpu.l2cache.Writeback_hits::writebacks      3742782                       # number of Writeback hits
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 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst            1                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.163163                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.163273                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.411411                       # miss rate for ReadExReq accesses
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 system.cpu.l2cache.demand_miss_rate::cpu.inst            1                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.214085                       # miss rate for demand accesses
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 system.cpu.l2cache.overall_miss_rate::cpu.inst            1                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.214085                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.214167                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74938.923395                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 82197.835594                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 82191.952424                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82493.114196                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82493.114196                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74938.923395                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82314.232610                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 82310.610243                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74938.923395                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82314.232610                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 82310.610243                       # average overall miss latency
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.213653                       # miss rate for overall accesses
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+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73938.791322                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 82506.368744                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 82499.447079                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82461.789258                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82461.789258                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73938.791322                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82488.902563                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 82484.700048                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73938.791322                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82488.902563                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 82484.700048                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -829,188 +836,188 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks      1019779                       # number of writebacks
-system.cpu.l2cache.writebacks::total          1019779                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          966                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data      1190927                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total      1191893                       # number of ReadReq MSHR misses
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-system.cpu.l2cache.ReadExReq_mshr_misses::total       774928                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst          966                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data      1965855                       # number of demand (read+write) MSHR misses
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-system.cpu.l2cache.overall_mshr_misses::cpu.data      1965855                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total      1966821                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     60233500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  82944620750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total  83004854250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  54243912498                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  54243912498                       # number of ReadExReq MSHR miss cycles
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-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 137188533248                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 137248766748                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     60233500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 137188533248                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 137248766748                       # number of overall MSHR miss cycles
+system.cpu.l2cache.writebacks::writebacks      1020420                       # number of writebacks
+system.cpu.l2cache.writebacks::total          1020420                       # number of writebacks
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+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  83779780750                       # number of ReadReq MSHR miss cycles
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+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  53974282000                       # number of ReadExReq MSHR miss cycles
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+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 137754062750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 137813448500                       # number of demand (read+write) MSHR miss cycles
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+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 137754062750                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 137813448500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.163163                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.163273                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.411411                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.411411                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.163237                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.163347                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.410430                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.410430                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.214085                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.214167                       # mshr miss rate for demand accesses
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 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.214085                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.214167                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62353.519669                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 69647.107463                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69641.196190                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69998.648259                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69998.648259                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62353.519669                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69785.682692                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69782.032401                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62353.519669                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69785.682692                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69782.032401                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.213653                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.213735                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61348.915289                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 69978.951758                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69971.979632                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69984.131965                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69984.131965                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61348.915289                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69980.981356                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69976.738559                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61348.915289                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69980.981356                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69976.738559                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements           9178508                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4087.552800                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           699314315                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           9182604                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             76.156427                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle        5143328250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4087.552800                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.997938                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.997938                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements           9209225                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4087.405523                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           713868953                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           9213321                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             77.482262                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle        5101114000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4087.405523                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.997902                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.997902                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          755                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1         2929                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          735                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1         2949                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::2          408                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::3            4                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses        1441348176                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses       1441348176                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    543788004                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       543788004                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    155526308                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      155526308                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data            3                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total            3                       # number of LoadLockedReq hits
-system.cpu.dcache.demand_hits::cpu.data     699314312                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        699314312                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    699314312                       # number of overall hits
-system.cpu.dcache.overall_hits::total       699314312                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data     11566276                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total      11566276                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      5202194                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      5202194                       # number of WriteReq misses
+system.cpu.dcache.tags.tag_accesses        1472872785                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses       1472872785                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    558354793                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       558354793                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    155514155                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      155514155                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data            5                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total            5                       # number of LoadLockedReq hits
+system.cpu.dcache.demand_hits::cpu.data     713868948                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        713868948                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    713868948                       # number of overall hits
+system.cpu.dcache.overall_hits::total       713868948                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data     12746431                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total      12746431                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      5214347                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      5214347                       # number of WriteReq misses
 system.cpu.dcache.LoadLockedReq_misses::cpu.data            1                       # number of LoadLockedReq misses
 system.cpu.dcache.LoadLockedReq_misses::total            1                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data     16768470                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total       16768470                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data     16768470                       # number of overall misses
-system.cpu.dcache.overall_misses::total      16768470                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 334833749250                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 334833749250                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 287624135124                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 287624135124                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data        69500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total        69500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 622457884374                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 622457884374                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 622457884374                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 622457884374                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    555354280                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    555354280                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data     17960778                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total       17960778                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data     17960778                       # number of overall misses
+system.cpu.dcache.overall_misses::total      17960778                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 384137632000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 384137632000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 288800427104                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 288800427104                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data        70500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total        70500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 672938059104                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 672938059104                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 672938059104                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 672938059104                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    571101224                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    571101224                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data    160728502                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total    160728502                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data            4                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total            4                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    716082782                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    716082782                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    716082782                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    716082782                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.020827                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.020827                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.032366                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.032366                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.250000                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.250000                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.023417                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.023417                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.023417                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.023417                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28949.140523                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 28949.140523                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55289.005970                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 55289.005970                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        69500                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        69500                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 37120.732206                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 37120.732206                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 37120.732206                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 37120.732206                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs     11998793                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets      8384809                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs            779484                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets           65137                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    15.393251                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets   128.725747                       # average number of cycles each access was blocked
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data            6                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total            6                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data    731829726                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    731829726                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    731829726                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    731829726                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.022319                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.022319                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.032442                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.032442                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.166667                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.166667                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.024542                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.024542                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.024542                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.024542                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30136.877688                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 30136.877688                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55385.732308                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 55385.732308                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        70500                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        70500                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 37467.088514                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 37467.088514                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 37467.088514                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 37467.088514                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs     14080620                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets      8619116                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs           1054999                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets           67267                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    13.346572                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets   128.132903                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      3725797                       # number of writebacks
-system.cpu.dcache.writebacks::total           3725797                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data      4267247                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total      4267247                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data      3318620                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total      3318620                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      7585867                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      7585867                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      7585867                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      7585867                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      7299029                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      7299029                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data      1883574                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total      1883574                       # number of WriteReq MSHR misses
+system.cpu.dcache.writebacks::writebacks      3742782                       # number of writebacks
+system.cpu.dcache.writebacks::total           3742782                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data      5412183                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total      5412183                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data      3335275                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total      3335275                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      8747458                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      8747458                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      8747458                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      8747458                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      7334248                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      7334248                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data      1879072                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total      1879072                       # number of WriteReq MSHR misses
 system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data            1                       # number of LoadLockedReq MSHR misses
 system.cpu.dcache.LoadLockedReq_mshr_misses::total            1                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      9182603                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      9182603                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      9182603                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      9182603                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 167129067750                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 167129067750                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  77336919371                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  77336919371                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data        67500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total        67500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 244465987121                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 244465987121                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 244465987121                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 244465987121                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.013143                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.013143                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.011719                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.011719                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.250000                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.250000                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.012823                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.012823                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.012823                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.012823                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22897.438515                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22897.438515                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41058.604213                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41058.604213                       # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data        67500                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total        67500                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26622.732914                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 26622.732914                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26622.732914                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 26622.732914                       # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_misses::cpu.data      9213320                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      9213320                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      9213320                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      9213320                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 168546702500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 168546702500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  77098541067                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  77098541067                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data        68500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total        68500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 245645243567                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 245645243567                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 245645243567                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 245645243567                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.012842                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.012842                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.011691                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.011691                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.166667                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.166667                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.012589                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.012589                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.012589                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.012589                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22980.774921                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22980.774921                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41030.115433                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41030.115433                       # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data        68500                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total        68500                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26661.968060                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 26661.968060                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26661.968060                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 26661.968060                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt
index f3e627477..f3667e9fd 100644
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.913189                       # Nu
 sim_ticks                                913189263000                       # Number of ticks simulated
 final_tick                               913189263000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                2693565                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2693565                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1351665756                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 256712                       # Number of bytes of host memory used
-host_seconds                                   675.60                       # Real time elapsed on the host
+host_inst_rate                                3321406                       # Simulator instruction rate (inst/s)
+host_op_rate                                  3321406                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1666724755                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 255644                       # Number of bytes of host memory used
+host_seconds                                   547.89                       # Real time elapsed on the host
 sim_insts                                  1819780127                       # Number of instructions simulated
 sim_ops                                    1819780127                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -96,10 +96,10 @@ system.cpu.not_idle_fraction                        1                       # Pe
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                         214632552                       # Number of branches fetched
 system.cpu.op_class::No_OpClass              83736345      4.58%      4.58% # Class of executed instruction
-system.cpu.op_class::IntAlu                1130719228     61.91%     66.50% # Class of executed instruction
-system.cpu.op_class::IntMult                       75      0.00%     66.50% # Class of executed instruction
-system.cpu.op_class::IntDiv                         0      0.00%     66.50% # Class of executed instruction
-system.cpu.op_class::FloatAdd                     166      0.00%     66.50% # Class of executed instruction
+system.cpu.op_class::IntAlu                1129914150     61.87%     66.45% # Class of executed instruction
+system.cpu.op_class::IntMult                       75      0.00%     66.45% # Class of executed instruction
+system.cpu.op_class::IntDiv                         0      0.00%     66.45% # Class of executed instruction
+system.cpu.op_class::FloatAdd                  805244      0.04%     66.50% # Class of executed instruction
 system.cpu.op_class::FloatCmp                      13      0.00%     66.50% # Class of executed instruction
 system.cpu.op_class::FloatCvt                     100      0.00%     66.50% # Class of executed instruction
 system.cpu.op_class::FloatMult                     11      0.00%     66.50% # Class of executed instruction
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt
index 2ba96be4b..07eca3cb9 100644
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  2.623386                       # Nu
 sim_ticks                                2623386226000                       # Number of ticks simulated
 final_tick                               2623386226000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1099630                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1099630                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1585220760                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 265440                       # Number of bytes of host memory used
-host_seconds                                  1654.90                       # Real time elapsed on the host
+host_inst_rate                                1619868                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1619868                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2335193556                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 265412                       # Number of bytes of host memory used
+host_seconds                                  1123.41                       # Real time elapsed on the host
 sim_insts                                  1819780127                       # Number of instructions simulated
 sim_ops                                    1819780127                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -110,10 +110,10 @@ system.cpu.not_idle_fraction                        1                       # Pe
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                         214632552                       # Number of branches fetched
 system.cpu.op_class::No_OpClass              83736345      4.58%      4.58% # Class of executed instruction
-system.cpu.op_class::IntAlu                1130719228     61.91%     66.50% # Class of executed instruction
-system.cpu.op_class::IntMult                       75      0.00%     66.50% # Class of executed instruction
-system.cpu.op_class::IntDiv                         0      0.00%     66.50% # Class of executed instruction
-system.cpu.op_class::FloatAdd                     166      0.00%     66.50% # Class of executed instruction
+system.cpu.op_class::IntAlu                1129914150     61.87%     66.45% # Class of executed instruction
+system.cpu.op_class::IntMult                       75      0.00%     66.45% # Class of executed instruction
+system.cpu.op_class::IntDiv                         0      0.00%     66.45% # Class of executed instruction
+system.cpu.op_class::FloatAdd                  805244      0.04%     66.50% # Class of executed instruction
 system.cpu.op_class::FloatCmp                      13      0.00%     66.50% # Class of executed instruction
 system.cpu.op_class::FloatCvt                     100      0.00%     66.50% # Class of executed instruction
 system.cpu.op_class::FloatMult                     11      0.00%     66.50% # Class of executed instruction
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt
index 7b16ef532..d103f16e9 100644
--- a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt
@@ -1,599 +1,101 @@
 
 ---------- Begin Simulation Statistics ----------
-final_tick                               1134079016500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-host_inst_rate                                 227824                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 293824                       # Number of bytes of host memory used
-host_op_rate                                   254155                       # Simulator op (including micro ops) rate (op/s)
-host_seconds                                  6779.62                       # Real time elapsed on the host
-host_tick_rate                              167277674                       # Simulator tick rate (ticks/s)
+sim_seconds                                  1.095875                       # Number of seconds simulated
+sim_ticks                                1095875470500                       # Number of ticks simulated
+final_tick                               1095875470500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                 232088                       # Simulator instruction rate (inst/s)
+host_op_rate                                   250040                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              164667871                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 318056                       # Number of bytes of host memory used
+host_seconds                                  6655.07                       # Real time elapsed on the host
 sim_insts                                  1544563087                       # Number of instructions simulated
-sim_ops                                    1723073900                       # Number of ops (including micro ops) simulated
-sim_seconds                                  1.134079                       # Number of seconds simulated
-sim_ticks                                1134079016500                       # Number of ticks simulated
+sim_ops                                    1664032480                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             87.938151                       # BTB Hit Percentage
-system.cpu.branchPred.BTBHits               122192107                       # Number of BTB hits
-system.cpu.branchPred.BTBLookups            138952327                       # Number of BTB lookups
-system.cpu.branchPred.RASInCorrect                 15                       # Number of incorrect RAS predictions.
-system.cpu.branchPred.condIncorrect          14597136                       # Number of conditional branches incorrect
-system.cpu.branchPred.condPredicted         197361074                       # Number of conditional branches predicted
-system.cpu.branchPred.lookups               250285818                       # Number of BP lookups
-system.cpu.branchPred.usedRAS                13226889                       # Number of times the RAS was used to get a target.
-system.cpu.committedInsts                  1544563087                       # Number of instructions committed
-system.cpu.committedOps                    1723073900                       # Number of ops (including micro ops) committed
-system.cpu.cpi                               1.468479                       # CPI: cycles per instruction
-system.cpu.dcache.LoadLockedReq_accesses::cpu.inst           61                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total           61                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_hits::cpu.inst           61                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total           61                       # number of LoadLockedReq hits
-system.cpu.dcache.ReadReq_accesses::cpu.inst    485955700                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    485955700                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 24973.063686                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 24973.063686                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 22917.493937                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22917.493937                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits::cpu.inst    478618690                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       478618690                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency::cpu.inst 183227617996                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 183227617996                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate::cpu.inst     0.015098                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.015098                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses::cpu.inst      7337010                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       7337010                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits::cpu.inst          222                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total          222                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 168140794504                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 168140794504                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst     0.015098                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.015098                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses::cpu.inst      7336788                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      7336788                       # number of ReadReq MSHR misses
-system.cpu.dcache.StoreCondReq_accesses::cpu.inst           61                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total           61                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_hits::cpu.inst           61                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total           61                       # number of StoreCondReq hits
-system.cpu.dcache.WriteReq_accesses::cpu.inst    172586047                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total    172586047                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 45215.138055                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 45215.138055                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 40855.687627                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40855.687627                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits::cpu.inst    170348428                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      170348428                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency::cpu.inst 101174252000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 101174252000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate::cpu.inst     0.012965                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.012965                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses::cpu.inst      2237619                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      2237619                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits::cpu.inst       346681                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       346681                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst  77255572250                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  77255572250                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst     0.010956                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.010956                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.inst      1890938                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total      1890938                       # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.demand_accesses::cpu.inst    658541747                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    658541747                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency::cpu.inst 29703.696091                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 29703.696091                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 26593.373790                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 26593.373790                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits::cpu.inst     648967118                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        648967118                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency::cpu.inst 284401869996                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 284401869996                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate::cpu.inst     0.014539                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.014539                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses::cpu.inst      9574629                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        9574629                       # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits::cpu.inst       346903                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       346903                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 245396366754                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 245396366754                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate::cpu.inst     0.014012                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.014012                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses::cpu.inst      9227726                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      9227726                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses::cpu.inst    658541747                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    658541747                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency::cpu.inst 29703.696091                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 29703.696091                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 26593.373790                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 26593.373790                       # average overall mshr miss latency
-system.cpu.dcache.overall_hits::cpu.inst    648967118                       # number of overall hits
-system.cpu.dcache.overall_hits::total       648967118                       # number of overall hits
-system.cpu.dcache.overall_miss_latency::cpu.inst 284401869996                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 284401869996                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate::cpu.inst     0.014539                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.014539                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses::cpu.inst      9574629                       # number of overall misses
-system.cpu.dcache.overall_misses::total       9574629                       # number of overall misses
-system.cpu.dcache.overall_mshr_hits::cpu.inst       346903                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       346903                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 245396366754                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 245396366754                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate::cpu.inst     0.014012                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.014012                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses::cpu.inst      9227726                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      9227726                       # number of overall MSHR misses
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          257                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1         1280                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2         2489                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3           70                       # Occupied blocks per task id
-system.cpu.dcache.tags.avg_refs             70.327970                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.data_accesses       1326311464                       # Number of data accesses
-system.cpu.dcache.tags.occ_blocks::cpu.inst  4085.294010                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.inst     0.997386                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.997386                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.replacements           9223630                       # number of replacements
-system.cpu.dcache.tags.sampled_refs           9227726                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.tag_accesses        1326311464                       # Number of tag accesses
-system.cpu.dcache.tags.tagsinuse          4085.294010                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           648967240                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle       10338720250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks::writebacks      3700800                       # number of writebacks
-system.cpu.dcache.writebacks::total           3700800                       # number of writebacks
-system.cpu.discardedOps                      51251418                       # Number of ops (including micro ops) which were discarded before commit
-system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
-system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
-system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
-system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
-system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
-system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
-system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
-system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
-system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
-system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
-system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
-system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
-system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
-system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
-system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
-system.cpu.dtb.accesses                             0                       # DTB accesses
-system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.hits                                 0                       # DTB hits
-system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.inst_hits                            0                       # ITB inst hits
-system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.misses                               0                       # DTB misses
-system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
-system.cpu.dtb.read_accesses                        0                       # DTB read accesses
-system.cpu.dtb.read_hits                            0                       # DTB read hits
-system.cpu.dtb.read_misses                          0                       # DTB read misses
-system.cpu.dtb.write_accesses                       0                       # DTB write accesses
-system.cpu.dtb.write_hits                           0                       # DTB write hits
-system.cpu.dtb.write_misses                         0                       # DTB write misses
-system.cpu.icache.ReadReq_accesses::cpu.inst    468616075                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    468616075                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 71218.824455                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 71218.824455                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68823.548426                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68823.548426                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits::cpu.inst    468615249                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       468615249                       # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     58826749                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     58826749                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000002                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000002                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses::cpu.inst          826                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total           826                       # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     56848251                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     56848251                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000002                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst          826                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total          826                       # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.demand_accesses::cpu.inst    468616075                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    468616075                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 71218.824455                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 71218.824455                       # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68823.548426                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 68823.548426                       # average overall mshr miss latency
-system.cpu.icache.demand_hits::cpu.inst     468615249                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        468615249                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency::cpu.inst     58826749                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     58826749                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000002                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000002                       # miss rate for demand accesses
-system.cpu.icache.demand_misses::cpu.inst          826                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total            826                       # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     56848251                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     56848251                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.000002                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses::cpu.inst          826                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total          826                       # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses::cpu.inst    468616075                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    468616075                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 71218.824455                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 71218.824455                       # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68823.548426                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 68823.548426                       # average overall mshr miss latency
-system.cpu.icache.overall_hits::cpu.inst    468615249                       # number of overall hits
-system.cpu.icache.overall_hits::total       468615249                       # number of overall hits
-system.cpu.icache.overall_miss_latency::cpu.inst     58826749                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     58826749                       # number of overall miss cycles
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000002                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000002                       # miss rate for overall accesses
-system.cpu.icache.overall_misses::cpu.inst          826                       # number of overall misses
-system.cpu.icache.overall_misses::total           826                       # number of overall misses
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     56848251                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     56848251                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.000002                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses::cpu.inst          826                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total          826                       # number of overall MSHR misses
-system.cpu.icache.tags.age_task_id_blocks_1024::0           32                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2            5                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4          760                       # Occupied blocks per task id
-system.cpu.icache.tags.avg_refs          567330.809927                       # Average number of references to valid blocks.
-system.cpu.icache.tags.data_accesses        937232976                       # Number of data accesses
-system.cpu.icache.tags.occ_blocks::cpu.inst   667.306532                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.325833                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.325833                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024          797                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.389160                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.replacements                29                       # number of replacements
-system.cpu.icache.tags.sampled_refs               826                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.tag_accesses         937232976                       # Number of tag accesses
-system.cpu.icache.tags.tagsinuse           667.306532                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           468615249                       # Total number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.idleCycles                       378561103                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.ipc                               0.680977                       # IPC: instructions per cycle
-system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
-system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
-system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
-system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
-system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
-system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
-system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
-system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
-system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
-system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
-system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
-system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
-system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
-system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
-system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
-system.cpu.itb.accesses                             0                       # DTB accesses
-system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
-system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.hits                                 0                       # DTB hits
-system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.itb.inst_hits                            0                       # ITB inst hits
-system.cpu.itb.inst_misses                          0                       # ITB inst misses
-system.cpu.itb.misses                               0                       # DTB misses
-system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
-system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
-system.cpu.itb.read_accesses                        0                       # DTB read accesses
-system.cpu.itb.read_hits                            0                       # DTB read hits
-system.cpu.itb.read_misses                          0                       # DTB read misses
-system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.write_hits                           0                       # DTB write hits
-system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.l2cache.ReadExReq_accesses::cpu.inst      1890938                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total      1890938                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 80530.523230                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80530.523230                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 67904.363586                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67904.363586                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_hits::cpu.inst      1090908                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total      1090908                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst  64426834500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total  64426834500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst     0.423086                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.423086                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses::cpu.inst       800030                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       800030                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst  54325528000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  54325528000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst     0.423086                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.423086                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst       800030                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       800030                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses::cpu.inst      7337614                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total      7337614                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 79650.729800                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 79650.729800                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67079.515524                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67079.515524                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits::cpu.inst      6081653                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        6081653                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 100038210250                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 100038210250                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.171167                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.171167                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses::cpu.inst      1255961                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total      1255961                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            5                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total            5                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst  84248920000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total  84248920000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.171167                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.171167                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst      1255956                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total      1255956                       # number of ReadReq MSHR misses
-system.cpu.l2cache.Writeback_accesses::writebacks      3700800                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total      3700800                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits::writebacks      3700800                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      3700800                       # number of Writeback hits
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.demand_accesses::cpu.inst      9228552                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      9228552                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79993.076210                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 79993.076210                       # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67400.482299                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67400.482299                       # average overall mshr miss latency
-system.cpu.l2cache.demand_hits::cpu.inst      7172561                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         7172561                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency::cpu.inst 164465044750                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 164465044750                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.222786                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.222786                       # miss rate for demand accesses
-system.cpu.l2cache.demand_misses::cpu.inst      2055991                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total       2055991                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_mshr_hits::cpu.inst            5                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total            5                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 138574448000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 138574448000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.222785                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.222785                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst      2055986                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total      2055986                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses::cpu.inst      9228552                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      9228552                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79993.076210                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 79993.076210                       # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67400.482299                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67400.482299                       # average overall mshr miss latency
-system.cpu.l2cache.overall_hits::cpu.inst      7172561                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        7172561                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency::cpu.inst 164465044750                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 164465044750                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.222786                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.222786                       # miss rate for overall accesses
-system.cpu.l2cache.overall_misses::cpu.inst      2055991                       # number of overall misses
-system.cpu.l2cache.overall_misses::total      2055991                       # number of overall misses
-system.cpu.l2cache.overall_mshr_hits::cpu.inst            5                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total            5                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 138574448000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 138574448000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.222785                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.222785                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst      2055986                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total      2055986                       # number of overall MSHR misses
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           92                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1           31                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         1208                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3        12891                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        15554                       # Occupied blocks per task id
-system.cpu.l2cache.tags.avg_refs             4.376215                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.data_accesses       107378812                       # Number of data accesses
-system.cpu.l2cache.tags.occ_blocks::writebacks 14921.737919                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 16303.939645                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.455375                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.497557                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.952932                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        29776                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.908691                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.replacements          2023282                       # number of replacements
-system.cpu.l2cache.tags.sampled_refs          2053058                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.tag_accesses        107378812                       # Number of tag accesses
-system.cpu.l2cache.tags.tagsinuse        31225.677564                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            8984623                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle      62285743250                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks::writebacks      1046478                       # number of writebacks
-system.cpu.l2cache.writebacks::total          1046478                       # number of writebacks
-system.cpu.numCycles                       2268158033                       # number of cpu cycles simulated
-system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.tickCycles                      1889596930                       # Number of cycles that the CPU actually ticked
-system.cpu.toL2Bus.data_through_bus         827478528                       # Total data (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1652                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     22156252                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total          22157904                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy    10165476000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          0.9                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy       1402249                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy   14183973746                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          1.3                       # Layer utilization (%)
-system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
-system.cpu.toL2Bus.throughput               729648037                       # Throughput (bytes/s)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        52864                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    827425664                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total      827478528                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.trans_dist::ReadReq        7337614                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       7337614                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      3700800                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq      1890938                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp      1890938                       # Transaction distribution
-system.cpu.workload.num_syscalls                   46                       # Number of system calls
-system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.membus.data_through_bus              198557696                       # Total data (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      5158450                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                5158450                       # Packet count per connected master and slave (bytes)
-system.membus.reqLayer0.occupancy         12256366000                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               1.1                       # Layer utilization (%)
-system.membus.respLayer1.occupancy        19378736500                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              1.7                       # Layer utilization (%)
-system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.throughput                    175082770                       # Throughput (bytes/s)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    198557696                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total           198557696                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.trans_dist::ReadReq             1255956                       # Transaction distribution
-system.membus.trans_dist::ReadResp            1255956                       # Transaction distribution
-system.membus.trans_dist::Writeback           1046478                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            800030                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           800030                       # Transaction distribution
-system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgGap                       365541.37                       # Average gap between requests
-system.physmem.avgMemAccLat                  37274.24                       # Average memory access latency per DRAM burst
-system.physmem.avgQLat                       18524.24                       # Average queueing delay per DRAM burst
-system.physmem.avgRdBW                         115.95                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgRdBWSys                      116.03                       # Average system read bandwidth in MiByte/s
-system.physmem.avgRdQLen                         1.02                       # Average read queue length when enqueuing
-system.physmem.avgWrBW                          59.05                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgWrBWSys                       59.06                       # Average system write bandwidth in MiByte/s
-system.physmem.avgWrQLen                        24.80                       # Average write queue length when enqueuing
-system.physmem.busUtil                           1.37                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       0.91                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.46                       # Data bus utilization in percentage for writes
-system.physmem.bw_inst_read::cpu.inst           44808                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total              44808                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst            116026399                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               116026399                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          59056372                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           116026399                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              175082770                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_write::writebacks          59056372                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               59056372                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bytesPerActivate::samples      1917061                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      103.528140                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean      81.739842                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     125.452866                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127        1492586     77.86%     77.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255       305285     15.92%     93.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        52052      2.72%     96.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        21496      1.12%     97.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639        13307      0.69%     98.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         7031      0.37%     98.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         5522      0.29%     98.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         4121      0.21%     99.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        15661      0.82%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total        1917061                       # Bytes accessed per row activation
-system.physmem.bytesReadDRAM                131498944                       # Total number of bytes read from DRAM
-system.physmem.bytesReadSys                 131583104                       # Total read bytes from the system interface side
-system.physmem.bytesReadWrQ                     84160                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  66972672                       # Total number of bytes written to DRAM
-system.physmem.bytesWrittenSys               66974592                       # Total written bytes from the system interface side
-system.physmem.bytes_inst_read::cpu.inst        50816                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           50816                       # Number of instructions bytes read from this memory
-system.physmem.bytes_read::cpu.inst         131583104                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            131583104                       # Number of bytes read from this memory
-system.physmem.bytes_written::writebacks     66974592                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          66974592                       # Number of bytes written to this memory
-system.physmem.memoryStateTime::IDLE     321867794250                       # Time in different power states
-system.physmem.memoryStateTime::REF       37869260000                       # Time in different power states
-system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT      774338779750                       # Time in different power states
-system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
+system.physmem.bytes_read::cpu.inst         131539072                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            131539072                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        50432                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           50432                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     66963456                       # Number of bytes written to this memory
+system.physmem.bytes_written::total          66963456                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst            2055298                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               2055298                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1046304                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total              1046304                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst            120031040                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               120031040                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst           46020                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total              46020                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          61104987                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               61104987                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          61104987                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           120031040                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              181136026                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                       2055298                       # Number of read requests accepted
+system.physmem.writeReqs                      1046304                       # Number of write requests accepted
+system.physmem.readBursts                     2055298                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                    1046304                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                131453056                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     86016                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  66961856                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                 131539072                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               66963456                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                     1344                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0              127944                       # Per bank write bursts
+system.physmem.perBankRdBursts::1              125151                       # Per bank write bursts
+system.physmem.perBankRdBursts::2              122313                       # Per bank write bursts
+system.physmem.perBankRdBursts::3              124176                       # Per bank write bursts
+system.physmem.perBankRdBursts::4              123203                       # Per bank write bursts
+system.physmem.perBankRdBursts::5              123365                       # Per bank write bursts
+system.physmem.perBankRdBursts::6              123797                       # Per bank write bursts
+system.physmem.perBankRdBursts::7              124247                       # Per bank write bursts
+system.physmem.perBankRdBursts::8              131879                       # Per bank write bursts
+system.physmem.perBankRdBursts::9              134089                       # Per bank write bursts
+system.physmem.perBankRdBursts::10             132451                       # Per bank write bursts
+system.physmem.perBankRdBursts::11             133680                       # Per bank write bursts
+system.physmem.perBankRdBursts::12             133764                       # Per bank write bursts
+system.physmem.perBankRdBursts::13             133810                       # Per bank write bursts
+system.physmem.perBankRdBursts::14             129795                       # Per bank write bursts
+system.physmem.perBankRdBursts::15             130290                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               65788                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               64108                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               62418                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               62855                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               62808                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               62982                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               64271                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               65268                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               67081                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               67609                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              67274                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              67626                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              67000                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              67431                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              66125                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              65635                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.num_reads::cpu.inst            2055986                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               2055986                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1046478                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1046478                       # Number of write requests responded to by this memory
-system.physmem.pageHitRate                      38.18                       # Row buffer hit rate, read and write combined
-system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.perBankRdBursts::0              127958                       # Per bank write bursts
-system.physmem.perBankRdBursts::1              125105                       # Per bank write bursts
-system.physmem.perBankRdBursts::2              122165                       # Per bank write bursts
-system.physmem.perBankRdBursts::3              124186                       # Per bank write bursts
-system.physmem.perBankRdBursts::4              123280                       # Per bank write bursts
-system.physmem.perBankRdBursts::5              123449                       # Per bank write bursts
-system.physmem.perBankRdBursts::6              123880                       # Per bank write bursts
-system.physmem.perBankRdBursts::7              124388                       # Per bank write bursts
-system.physmem.perBankRdBursts::8              131994                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              133987                       # Per bank write bursts
-system.physmem.perBankRdBursts::10             132463                       # Per bank write bursts
-system.physmem.perBankRdBursts::11             133769                       # Per bank write bursts
-system.physmem.perBankRdBursts::12             133910                       # Per bank write bursts
-system.physmem.perBankRdBursts::13             133839                       # Per bank write bursts
-system.physmem.perBankRdBursts::14             129945                       # Per bank write bursts
-system.physmem.perBankRdBursts::15             130353                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               65810                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               64091                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               62337                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               62824                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               62831                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               62991                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               64303                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               65302                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               67082                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               67591                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              67285                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              67661                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              67090                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              67416                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              66182                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              65652                       # Per bank write bursts
-system.physmem.rdPerTurnAround::samples         60782                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        33.755668                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      161.633297                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023          60741     99.93%     99.93% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-2047           17      0.03%     99.96% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2048-3071           11      0.02%     99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::3072-4095            5      0.01%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::4096-5119            3      0.00%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::10240-11263            1      0.00%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::12288-13311            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::13312-14335            2      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::22528-23551            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           60782                       # Reads before turning the bus around for writes
-system.physmem.rdQLenPdf::0                   1924013                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    130641                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        17                       # What read queue length does an incoming req see
+system.physmem.totGap                    1095875382500                       # Total gap between requests
+system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
+system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
+system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
+system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
+system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
+system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
+system.physmem.readPktSize::6                 2055298                       # Read request sizes (log2)
+system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
+system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
+system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
+system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
+system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
+system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
+system.physmem.writePktSize::6                1046304                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                   1922424                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    131512                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        18                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
@@ -623,36 +125,6 @@ system.physmem.rdQLenPdf::28                        0                       # Wh
 system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.readBursts                     2055986                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                 2055986                       # Read request sizes (log2)
-system.physmem.readReqs                       2055986                       # Number of read requests accepted
-system.physmem.readRowHitRate                   37.77                       # Row buffer hit rate for reads
-system.physmem.readRowHits                     776076                       # Number of row buffer hits during reads
-system.physmem.servicedByWrQ                     1315                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.totBusLat                  10273355000                       # Total ticks spent in databus transfers
-system.physmem.totGap                    1134078928500                       # Total gap between requests
-system.physmem.totMemAccLat               76586290250                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totQLat                    38061209000                       # Total ticks spent queuing
-system.physmem.wrPerTurnAround::samples         60782                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        17.216413                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       17.182090                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        1.086488                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16              25426     41.83%     41.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17               1488      2.45%     44.28% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18              29643     48.77%     93.05% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19               3806      6.26%     99.31% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                363      0.60%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21                 50      0.08%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22                  4      0.01%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23                  1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::27                  1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           60782                       # Writes before turning the bus around for reads
 system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
@@ -668,30 +140,30 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                    33627                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                    35200                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    57222                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    60715                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    61437                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    61279                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    61254                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                    61244                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                    61236                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    61317                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    61255                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    61292                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                    62303                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                    61692                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    61407                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                    62182                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                    60930                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                    60785                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                       71                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                        8                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                        4                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                    33528                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                    34841                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                    57203                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                    60757                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                    61403                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    61327                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    61251                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    61258                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    61259                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    61367                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    61289                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    61334                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                    62306                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                    61683                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                    61440                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                    62194                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                    60945                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                    60798                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                       90                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                       13                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                        3                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
@@ -717,17 +189,544 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.writeBursts                    1046478                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                1046478                       # Write request sizes (log2)
-system.physmem.writeReqs                      1046478                       # Number of write requests accepted
-system.physmem.writeRowHitRate                  38.99                       # Row buffer hit rate for writes
-system.physmem.writeRowHits                    407972                       # Number of row buffer hits during writes
-system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.physmem.bytesPerActivate::samples      1911965                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      103.774418                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean      81.877172                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     125.825249                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127        1485376     77.69%     77.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255       306998     16.06%     93.75% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        52789      2.76%     96.51% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511        21060      1.10%     97.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639        13283      0.69%     98.30% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         6873      0.36%     98.66% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         5659      0.30%     98.96% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         4134      0.22%     99.17% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        15793      0.83%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total        1911965                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         60795                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        33.737117                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      161.571664                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023          60754     99.93%     99.93% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-2047           14      0.02%     99.96% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2048-3071           14      0.02%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::3072-4095            5      0.01%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::4096-5119            3      0.00%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::9216-10239            1      0.00%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::12288-13311            2      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::14336-15359            1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::22528-23551            1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total           60795                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         60795                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.209951                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       17.175292                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        1.091996                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16              25805     42.45%     42.45% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17               1192      1.96%     44.41% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18              29551     48.61%     93.01% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19               3811      6.27%     99.28% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                363      0.60%     99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                 60      0.10%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22                 11      0.02%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23                  2      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           60795                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    38124649000                       # Total ticks spent queuing
+system.physmem.totMemAccLat               76636286500                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                  10269770000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       18561.59                       # Average queueing delay per DRAM burst
+system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
+system.physmem.avgMemAccLat                  37311.59                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         119.95                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                          61.10                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                      120.03                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                       61.10                       # Average system write bandwidth in MiByte/s
+system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
+system.physmem.busUtil                           1.41                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       0.94                       # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite                      0.48                       # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen                         1.02                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        24.69                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     779774                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    408484                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   37.96                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  39.04                       # Row buffer hit rate for writes
+system.physmem.avgGap                       353325.60                       # Average gap between requests
+system.physmem.pageHitRate                      38.33                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE     306310282500                       # Time in different power states
+system.physmem.memoryStateTime::REF       36593440000                       # Time in different power states
+system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
+system.physmem.memoryStateTime::ACT      752968660500                       # Time in different power states
+system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
+system.membus.throughput                    181136026                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq             1255348                       # Transaction distribution
+system.membus.trans_dist::ReadResp            1255348                       # Transaction distribution
+system.membus.trans_dist::Writeback           1046304                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            799950                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           799950                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      5156900                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                5156900                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    198502528                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total           198502528                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus              198502528                       # Total data (bytes)
+system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy         12227667000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               1.1                       # Layer utilization (%)
+system.membus.respLayer1.occupancy        19360882250                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization              1.8                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.cpu.branchPred.lookups               239641872                       # Number of BP lookups
+system.cpu.branchPred.condPredicted         186303374                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect          14594643                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups            130836287                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits               121989290                       # Number of BTB hits
+system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.branchPred.BTBHitPct             93.238117                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                15653729                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect                 15                       # Number of incorrect RAS predictions.
+system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
+system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
+system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
+system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
+system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
+system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
+system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
+system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
+system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
+system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
+system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
+system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
+system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
+system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
+system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
+system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
+system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.dtb.inst_hits                            0                       # ITB inst hits
+system.cpu.dtb.inst_misses                          0                       # ITB inst misses
+system.cpu.dtb.read_hits                            0                       # DTB read hits
+system.cpu.dtb.read_misses                          0                       # DTB read misses
+system.cpu.dtb.write_hits                           0                       # DTB write hits
+system.cpu.dtb.write_misses                         0                       # DTB write misses
+system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                        0                       # DTB read accesses
+system.cpu.dtb.write_accesses                       0                       # DTB write accesses
+system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.dtb.hits                                 0                       # DTB hits
+system.cpu.dtb.misses                               0                       # DTB misses
+system.cpu.dtb.accesses                             0                       # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
+system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
+system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
+system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
+system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
+system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
+system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
+system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
+system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
+system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
+system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
+system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
+system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
+system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
+system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
+system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
+system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.itb.inst_hits                            0                       # ITB inst hits
+system.cpu.itb.inst_misses                          0                       # ITB inst misses
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
+system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.itb.hits                                 0                       # DTB hits
+system.cpu.itb.misses                               0                       # DTB misses
+system.cpu.itb.accesses                             0                       # DTB accesses
+system.cpu.workload.num_syscalls                   46                       # Number of system calls
+system.cpu.numCycles                       2191750941                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.committedInsts                  1544563087                       # Number of instructions committed
+system.cpu.committedOps                    1664032480                       # Number of ops (including micro ops) committed
+system.cpu.discardedOps                      42066132                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
+system.cpu.cpi                               1.419010                       # CPI: cycles per instruction
+system.cpu.ipc                               0.704717                       # IPC: instructions per cycle
+system.cpu.tickCycles                      1808188284                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                       383562657                       # Total number of cycles that the object has spent stopped
+system.cpu.icache.tags.replacements                29                       # number of replacements
+system.cpu.icache.tags.tagsinuse           661.141376                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           464847257                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs               820                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          566886.898780                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   661.141376                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.322823                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.322823                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          791                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           32                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2            5                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4          754                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.386230                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses         929696974                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        929696974                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    464847257                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       464847257                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     464847257                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        464847257                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    464847257                       # number of overall hits
+system.cpu.icache.overall_hits::total       464847257                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          820                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           820                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          820                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            820                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          820                       # number of overall misses
+system.cpu.icache.overall_misses::total           820                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     58324499                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     58324499                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     58324499                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     58324499                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     58324499                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     58324499                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    464848077                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    464848077                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    464848077                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    464848077                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    464848077                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    464848077                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000002                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000002                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000002                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000002                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000002                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000002                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 71127.437805                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 71127.437805                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 71127.437805                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 71127.437805                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 71127.437805                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 71127.437805                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          820                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          820                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          820                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          820                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          820                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total          820                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     56360501                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     56360501                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     56360501                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     56360501                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     56360501                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     56360501                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000002                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.000002                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.000002                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68732.318293                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68732.318293                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68732.318293                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 68732.318293                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68732.318293                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 68732.318293                       # average overall mshr miss latency
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.toL2Bus.throughput               755014954                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq        7336391                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       7336391                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback      3700895                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq      1890876                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp      1890876                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1640                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     22153789                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total          22155429                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        52480                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    827349888                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total      827402368                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus         827402368                       # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy    10164976000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          0.9                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy       1391999                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy   14185372245                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization          1.3                       # Layer utilization (%)
+system.cpu.l2cache.tags.replacements          2022594                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        31252.258926                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            8984184                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs          2052369                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             4.377470                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle      58953869250                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 14968.183746                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 16284.075180                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.456793                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.496951                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.953743                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        29775                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           91                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1           31                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         1248                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3        12849                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        15556                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.908661                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses        107368541                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses       107368541                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.inst      6081037                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total        6081037                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks      3700895                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total      3700895                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.inst      1090926                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total      1090926                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst      7171963                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         7171963                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst      7171963                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        7171963                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst      1255354                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total      1255354                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.inst       799950                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       799950                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst      2055304                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total       2055304                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst      2055304                       # number of overall misses
+system.cpu.l2cache.overall_misses::total      2055304                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 100122250500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 100122250500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst  64358555750                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total  64358555750                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 164480806250                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 164480806250                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 164480806250                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 164480806250                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst      7336391                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total      7336391                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks      3700895                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total      3700895                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.inst      1890876                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total      1890876                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst      9227267                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      9227267                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst      9227267                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      9227267                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.171113                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.171113                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst     0.423058                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.423058                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.222742                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.222742                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.222742                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.222742                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 79756.188693                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 79756.188693                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 80453.223014                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80453.223014                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80027.483161                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 80027.483161                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80027.483161                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 80027.483161                       # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
+system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
+system.cpu.l2cache.writebacks::writebacks      1046304                       # number of writebacks
+system.cpu.l2cache.writebacks::total          1046304                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            6                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total            6                       # number of ReadReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst            6                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total            6                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst            6                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total            6                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst      1255348                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total      1255348                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst       799950                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       799950                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst      2055298                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total      2055298                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst      2055298                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total      2055298                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst  84333554000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total  84333554000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst  54273221250                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  54273221250                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 138606775250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 138606775250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 138606775250                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 138606775250                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.171112                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.171112                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst     0.423058                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.423058                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.222742                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.222742                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.222742                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.222742                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67179.422758                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67179.422758                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 67845.766923                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67845.766923                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67438.772991                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67438.772991                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67438.772991                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67438.772991                       # average overall mshr miss latency
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu.dcache.tags.replacements           9222351                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4085.559894                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           624001258                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           9226447                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             67.631804                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle        9703664000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.inst  4085.559894                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.inst     0.997451                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.997451                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          283                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1         1314                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2         2438                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3           61                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses        1276381727                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses       1276381727                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.inst    453655688                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       453655688                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.inst    170345448                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      170345448                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.inst           61                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total           61                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.inst           61                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total           61                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.inst     624001136                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        624001136                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.inst    624001136                       # number of overall hits
+system.cpu.dcache.overall_hits::total       624001136                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.inst      7335783                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       7335783                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.inst      2240599                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      2240599                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.inst      9576382                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        9576382                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.inst      9576382                       # number of overall misses
+system.cpu.dcache.overall_misses::total       9576382                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.inst 183307188995                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 183307188995                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.inst 101248592250                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 101248592250                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.inst 284555781245                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 284555781245                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.inst 284555781245                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 284555781245                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.inst    460991471                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    460991471                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.inst    172586047                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total    172586047                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.inst           61                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total           61                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.inst           61                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total           61                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.inst    633577518                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    633577518                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.inst    633577518                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    633577518                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.inst     0.015913                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.015913                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.inst     0.012983                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.012983                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.inst     0.015115                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.015115                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.inst     0.015115                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.015115                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 24988.087706                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 24988.087706                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 45188.180594                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 45188.180594                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.inst 29714.330657                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 29714.330657                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.inst 29714.330657                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 29714.330657                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks      3700895                       # number of writebacks
+system.cpu.dcache.writebacks::total           3700895                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.inst          212                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total          212                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.inst       349723                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       349723                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.inst       349935                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       349935                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.inst       349935                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       349935                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.inst      7335571                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      7335571                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.inst      1890876                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total      1890876                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.inst      9226447                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      9226447                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.inst      9226447                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      9226447                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 168217924005                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 168217924005                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst  77187221250                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  77187221250                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 245405145255                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 245405145255                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 245405145255                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 245405145255                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst     0.015913                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.015913                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst     0.010956                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.010956                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.inst     0.014562                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.014562                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.inst     0.014562                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.014562                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 22931.810490                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22931.810490                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 40820.879450                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40820.879450                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 26598.011700                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 26598.011700                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 26598.011700                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 26598.011700                       # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt
index 80d2ee221..a0b5e888a 100644
--- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt
@@ -1,108 +1,108 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.523064                       # Number of seconds simulated
-sim_ticks                                523063504500                       # Number of ticks simulated
-final_tick                               523063504500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.506591                       # Number of seconds simulated
+sim_ticks                                506591420000                       # Number of ticks simulated
+final_tick                               506591420000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 149016                       # Simulator instruction rate (inst/s)
-host_op_rate                                   166238                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               50463882                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 261252                       # Number of bytes of host memory used
-host_seconds                                 10365.11                       # Real time elapsed on the host
+host_inst_rate                                 188296                       # Simulator instruction rate (inst/s)
+host_op_rate                                   202861                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               61758141                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 254008                       # Number of bytes of host memory used
+host_seconds                                  8202.83                       # Real time elapsed on the host
 sim_insts                                  1544563023                       # Number of instructions simulated
-sim_ops                                    1723073835                       # Number of ops (including micro ops) simulated
+sim_ops                                    1664032415                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst             48064                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data         143764288                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            143812352                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        48064                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           48064                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     70447616                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          70447616                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst                751                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data            2246317                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               2247068                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1100744                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1100744                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst                91889                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            274850543                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               274942432                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst           91889                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total              91889                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks         134682721                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total              134682721                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks         134682721                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst               91889                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           274850543                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              409625153                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                       2247068                       # Number of read requests accepted
-system.physmem.writeReqs                      1100744                       # Number of write requests accepted
-system.physmem.readBursts                     2247068                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                    1100744                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                143722368                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     89984                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  70445760                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                 143812352                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               70447616                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                     1406                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytes_read::cpu.inst             46336                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data         143772736                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            143819072                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        46336                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           46336                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     70460288                       # Number of bytes written to this memory
+system.physmem.bytes_written::total          70460288                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst                724                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data            2246449                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               2247173                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1100942                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total              1100942                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst                91466                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            283804128                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               283895594                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst           91466                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total              91466                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks         139087014                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total              139087014                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks         139087014                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst               91466                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           283804128                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              422982608                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                       2247174                       # Number of read requests accepted
+system.physmem.writeReqs                      1100942                       # Number of write requests accepted
+system.physmem.readBursts                     2247174                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                    1100942                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                143725504                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     93632                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  70458432                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                 143819136                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               70460288                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                     1463                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0              139750                       # Per bank write bursts
-system.physmem.perBankRdBursts::1              136144                       # Per bank write bursts
-system.physmem.perBankRdBursts::2              133842                       # Per bank write bursts
-system.physmem.perBankRdBursts::3              136111                       # Per bank write bursts
-system.physmem.perBankRdBursts::4              134906                       # Per bank write bursts
-system.physmem.perBankRdBursts::5              135203                       # Per bank write bursts
-system.physmem.perBankRdBursts::6              136131                       # Per bank write bursts
-system.physmem.perBankRdBursts::7              136315                       # Per bank write bursts
-system.physmem.perBankRdBursts::8              143809                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              146590                       # Per bank write bursts
-system.physmem.perBankRdBursts::10             144423                       # Per bank write bursts
-system.physmem.perBankRdBursts::11             146169                       # Per bank write bursts
-system.physmem.perBankRdBursts::12             145711                       # Per bank write bursts
-system.physmem.perBankRdBursts::13             146127                       # Per bank write bursts
-system.physmem.perBankRdBursts::14             142010                       # Per bank write bursts
-system.physmem.perBankRdBursts::15             142421                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               69157                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               67395                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               65690                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               66283                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               66211                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               66391                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               67933                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               68845                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               70389                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               71029                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              70577                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              70974                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              70326                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              70796                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              69605                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              69114                       # Per bank write bursts
+system.physmem.perBankRdBursts::0              139870                       # Per bank write bursts
+system.physmem.perBankRdBursts::1              136313                       # Per bank write bursts
+system.physmem.perBankRdBursts::2              133717                       # Per bank write bursts
+system.physmem.perBankRdBursts::3              136218                       # Per bank write bursts
+system.physmem.perBankRdBursts::4              134833                       # Per bank write bursts
+system.physmem.perBankRdBursts::5              135331                       # Per bank write bursts
+system.physmem.perBankRdBursts::6              136159                       # Per bank write bursts
+system.physmem.perBankRdBursts::7              136113                       # Per bank write bursts
+system.physmem.perBankRdBursts::8              143820                       # Per bank write bursts
+system.physmem.perBankRdBursts::9              146459                       # Per bank write bursts
+system.physmem.perBankRdBursts::10             144333                       # Per bank write bursts
+system.physmem.perBankRdBursts::11             146068                       # Per bank write bursts
+system.physmem.perBankRdBursts::12             145787                       # Per bank write bursts
+system.physmem.perBankRdBursts::13             145950                       # Per bank write bursts
+system.physmem.perBankRdBursts::14             142167                       # Per bank write bursts
+system.physmem.perBankRdBursts::15             142573                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               69256                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               67490                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               65701                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               66292                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               66182                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               66456                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               67905                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               68814                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               70409                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               70980                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              70565                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              70894                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              70329                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              70807                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              69706                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              69127                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    523063435500                       # Total gap between requests
+system.physmem.totGap                    506591366500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                 2247068                       # Read request sizes (log2)
+system.physmem.readPktSize::6                 2247174                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                1100744                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                   1615066                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    449330                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                    137330                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                     43923                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                        12                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                1100942                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                   1574104                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    476401                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                    148213                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                     46974                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                        16                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                         3                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
@@ -144,160 +144,152 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                    23358                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                    24975                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    49534                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    60519                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    65129                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    66570                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    66892                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                    67087                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                    67169                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    67424                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    67533                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    67827                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                    68851                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                    70296                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    67618                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                    68033                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                    66306                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                    65326                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      193                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                       44                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                       13                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                        7                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                        4                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                        2                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                        2                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                        2                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                        2                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                    22580                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                    24088                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                    48460                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                    60043                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                    65003                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    66811                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    67201                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::23                    67460                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    67663                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    67777                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    68170                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                    69182                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                    70669                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                    67984                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                    68233                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                    66514                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                    65455                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      246                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                       63                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                       18                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                        8                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                        5                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                        4                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                        3                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                        4                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                        3                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                        3                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                        3                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                        6                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                        4                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                        4                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                        4                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                        6                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                        3                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                        3                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                        3                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                        3                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples      2025915                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      105.713545                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean      82.619710                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     129.565498                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127        1567130     77.35%     77.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255       318929     15.74%     93.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        67085      3.31%     96.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        23530      1.16%     97.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639        13977      0.69%     98.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         6837      0.34%     98.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         5148      0.25%     98.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         3637      0.18%     99.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        19642      0.97%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total        2025915                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         65189                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        34.403642                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      148.850371                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023          65147     99.94%     99.94% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-2047           15      0.02%     99.96% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2048-3071           11      0.02%     99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::3072-4095            8      0.01%     99.99% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples      2025013                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      105.768407                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean      82.613194                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     129.925028                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127        1567130     77.39%     77.39% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255       318117     15.71%     93.10% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        66732      3.30%     96.39% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511        23886      1.18%     97.57% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639        14001      0.69%     98.26% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         6496      0.32%     98.59% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         4833      0.24%     98.82% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         3896      0.19%     99.02% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        19922      0.98%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total        2025013                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         65320                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        34.335441                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      154.678788                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023          65282     99.94%     99.94% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-2047           11      0.02%     99.96% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2048-3071           14      0.02%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::3072-4095            5      0.01%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::4096-5119            3      0.00%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::8192-9215            1      0.00%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::9216-10239            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::10240-11263            1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::10240-11263            1      0.00%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::12288-13311            2      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::13312-14335            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::22528-23551            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           65189                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         65189                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        16.884981                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.844479                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        1.202215                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16              39520     60.62%     60.62% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17               1483      2.27%     62.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18              18196     27.91%     90.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19               4786      7.34%     98.15% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                898      1.38%     99.53% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21                207      0.32%     99.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22                 54      0.08%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23                 11      0.02%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24                  9      0.01%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::25                  1      0.00%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26                  2      0.00%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::27                  1      0.00%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28                  2      0.00%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::29                  1      0.00%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::30                  3      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::31                 10      0.02%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32                  3      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::33                  1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40                  1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           65189                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    50228413500                       # Total ticks spent queuing
-system.physmem.totMemAccLat               92334576000                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                  11228310000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       22366.86                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total           65320                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         65320                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.854149                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.813582                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        1.224401                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-17           41990     64.28%     64.28% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18-19           22168     33.94%     98.22% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-21            1073      1.64%     99.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22-23              57      0.09%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-25               8      0.01%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26-27               3      0.00%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-29               2      0.00%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::30-31              14      0.02%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-33               2      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::34-35               1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-45               1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-85               1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           65320                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    50678676000                       # Total ticks spent queuing
+system.physmem.totMemAccLat               92785757250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                  11228555000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       22566.87                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  41116.86                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         274.77                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                         134.68                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                      274.94                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                      134.68                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  41316.87                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         283.71                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                         139.08                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                      283.90                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                      139.09                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           3.20                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       2.15                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      1.05                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.18                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        24.83                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     905849                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    414601                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   40.34                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  37.67                       # Row buffer hit rate for writes
-system.physmem.avgGap                       156240.38                       # Average gap between requests
-system.physmem.pageHitRate                      39.46                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE      94741058000                       # Time in different power states
-system.physmem.memoryStateTime::REF       17466020000                       # Time in different power states
+system.physmem.busUtil                           3.30                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       2.22                       # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite                      1.09                       # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen                         1.19                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        25.41                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     906473                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    415128                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   40.36                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  37.71                       # Row buffer hit rate for writes
+system.physmem.avgGap                       151306.40                       # Average gap between requests
+system.physmem.pageHitRate                      39.49                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE      89126966500                       # Time in different power states
+system.physmem.memoryStateTime::REF       16916120000                       # Time in different power states
 system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT      410854630500                       # Time in different power states
+system.physmem.memoryStateTime::ACT      400546526000                       # Time in different power states
 system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.membus.throughput                    409625031                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq             1419612                       # Transaction distribution
-system.membus.trans_dist::ReadResp            1419611                       # Transaction distribution
-system.membus.trans_dist::Writeback           1100744                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            827456                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           827456                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      5594879                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                5594879                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    214259904                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total           214259904                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus              214259904                       # Total data (bytes)
+system.membus.throughput                    422982608                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq             1419539                       # Transaction distribution
+system.membus.trans_dist::ReadResp            1419538                       # Transaction distribution
+system.membus.trans_dist::Writeback           1100942                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            827635                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           827635                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      5595289                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                5595289                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    214279360                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total           214279360                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus              214279360                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy         12872956000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy         12858312000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               2.5                       # Layer utilization (%)
-system.membus.respLayer1.occupancy        21034966500                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              4.0                       # Layer utilization (%)
+system.membus.respLayer1.occupancy        21011522750                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization              4.1                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.branchPred.lookups               310041872                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         254951905                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect          15242132                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups            177250182                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits               164623168                       # Number of BTB hits
+system.cpu.branchPred.lookups               322479068                       # Number of BP lookups
+system.cpu.branchPred.condPredicted         251697336                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect          15342173                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups            182789015                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits               169211218                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             92.876163                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                17905906                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect                206                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             92.571875                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                19180311                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect                 62                       # Number of incorrect RAS predictions.
 system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -383,380 +375,377 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                   46                       # Number of system calls
-system.cpu.numCycles                       1046127010                       # number of cpu cycles simulated
+system.cpu.numCycles                       1013182841                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles          304406506                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                     2237155990                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                   310041872                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches          182529074                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     444747763                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                93800973                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles              104367517                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                    3                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles            63                       # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles           14                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                 295060555                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes               6266924                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          929205544                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.663579                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.245143                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles          309137299                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                     2319640214                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   322479068                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches          188391529                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     688452374                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                31084694                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.CacheLines                 300792002                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               5498702                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples         1013132020                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.455758                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.154346                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                484458019     52.14%     52.14% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 25667204      2.76%     54.90% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 39962445      4.30%     59.20% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 49351933      5.31%     64.51% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                 44527866      4.79%     69.30% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                 47023403      5.06%     74.36% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                 39036338      4.20%     78.56% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                 19508250      2.10%     80.66% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                179670086     19.34%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                555222202     54.80%     54.80% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 28050197      2.77%     57.57% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 43308558      4.27%     61.85% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 56959165      5.62%     67.47% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                 42292761      4.17%     71.64% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                 51207543      5.05%     76.70% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                 41019007      4.05%     80.75% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                 29441196      2.91%     83.65% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                165631391     16.35%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            929205544                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.296371                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        2.138513                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                323230837                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              95973570                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 424273226                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              10044892                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles               75683019                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved             46957126                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                   712                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts             2419092576                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                  2470                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles               75683019                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                338590369                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                36235131                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles          20070                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 418478079                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              60198876                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts             2357219159                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                486871                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents               10439342                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents               39865193                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                9487400                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.FullRegisterEvents              108                       # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands          2332621614                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups           10887738442                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       9980989966                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups               478                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps            1706319930                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                626301684                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts               1665                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts           1662                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  62763220                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            637377073                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores           224726985                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads          97022139                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores         86012676                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                 2244793752                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                1629                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                2031991177                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued           6410093                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined       517307509                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined   1273036014                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved           1459                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     929205544                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         2.186805                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.944442                       # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total           1013132020                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.318283                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        2.289459                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                248682792                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             345622952                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 359459924                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              43824601                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles               15541751                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved             49856372                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                   610                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts             2395697302                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                  2189                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles               15541751                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                269479595                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles               192381996                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles          17471                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 380094168                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles             155617039                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts             2338847400                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                939227                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents               43524152                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents               85831703                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents               28336004                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands          2341659219                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups           10827293229                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       2896191361                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups               924                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps            1674898945                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                666760274                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts                297                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts            295                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                 177584133                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            623787680                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           234474986                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads         103326529                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores        119861826                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                 2235979798                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                 279                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                2042453270                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued           1123672                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       568282292                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined   1410742018                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved            109                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples    1013132020                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         2.015979                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        2.060962                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           266904218     28.72%     28.72% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1           128322549     13.81%     42.53% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2           158977129     17.11%     59.64% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3           117185502     12.61%     72.25% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4           128428514     13.82%     86.08% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5            72785870      7.83%     93.91% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6            42669642      4.59%     98.50% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7            10960354      1.18%     99.68% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8             2971766      0.32%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           369509753     36.47%     36.47% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           122144381     12.06%     48.53% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2           148105848     14.62%     63.15% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3           116397380     11.49%     74.64% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4           120158766     11.86%     86.50% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            67734855      6.69%     93.18% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6            38716090      3.82%     97.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7            19620402      1.94%     98.94% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8            10744545      1.06%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       929205544                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total      1013132020                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                 1285844      5.85%      5.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                   5675      0.03%      5.88% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      5.88% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      5.88% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      5.88% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      5.88% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      5.88% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      5.88% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      5.88% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      5.88% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      5.88% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      5.88% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      5.88% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      5.88% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      5.88% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      5.88% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      5.88% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      5.88% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      5.88% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      5.88% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      5.88% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      5.88% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      5.88% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      5.88% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      5.88% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      5.88% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      5.88% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      5.88% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      5.88% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead               18368199     83.62%     89.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite               2306433     10.50%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                 3650692     18.70%     18.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                    890      0.00%     18.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     18.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     18.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     18.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     18.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     18.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     18.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     18.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     18.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     18.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     18.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     18.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     18.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     18.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     18.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     18.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     18.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     18.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     18.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     18.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     18.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     18.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     18.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     18.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     18.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     18.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     18.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     18.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead               15434151     79.07%     97.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                434530      2.23%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu            1245462856     61.29%     61.29% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult               947392      0.05%     61.34% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     61.34% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   2      0.00%     61.34% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     61.34% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     61.34% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     61.34% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     61.34% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     61.34% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     61.34% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     61.34% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     61.34% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     61.34% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     61.34% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     61.34% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     61.34% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     61.34% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     61.34% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     61.34% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     61.34% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     61.34% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     61.34% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     61.34% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt              51      0.00%     61.34% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               1      0.00%     61.34% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc             21      0.00%     61.34% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              9      0.00%     61.34% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     61.34% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     61.34% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            592199391     29.14%     90.48% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite           193381454      9.52%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu            1227555044     60.10%     60.10% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult               999501      0.05%     60.15% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     60.15% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     60.15% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     60.15% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     60.15% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     60.15% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     60.15% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     60.15% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     60.15% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     60.15% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     60.15% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     60.15% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     60.15% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     60.15% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     60.15% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     60.15% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     60.15% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     60.15% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     60.15% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     60.15% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     60.15% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     60.15% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt              75      0.00%     60.15% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               3      0.00%     60.15% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc             36      0.00%     60.15% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult             18      0.00%     60.15% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     60.15% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     60.15% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            618802083     30.30%     90.45% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite           195096510      9.55%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total             2031991177                       # Type of FU issued
-system.cpu.iq.rate                           1.942394                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                    21966151                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.010810                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         5021563817                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes        2762296727                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses   1969035141                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads                 325                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes                660                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses          139                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses             2053957167                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                     161                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads         66315008                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total             2042453270                       # Type of FU issued
+system.cpu.iq.rate                           2.015878                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    19520263                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.009557                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         5118681932                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes        2804481694                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses   1937195401                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads                 563                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes                772                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses          222                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses             2061973250                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                     283                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads         29620868                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads    151450304                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses       182572                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation       197144                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores     49879940                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads    165481346                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses       152761                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation       223174                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores     59627941                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads            4                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked       4648682                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads     27365932                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked      20554693                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles               75683019                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                13889446                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles              17402817                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts          2244795480                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts           7970371                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             637377073                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts            224726985                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts               1567                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                 551835                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents              16641279                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents         197144                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect        8164855                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect      9718586                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts             17883441                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts            2000301565                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             577561658                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts          31689612                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles               15541751                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                99594513                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles              79709192                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts          2235980127                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts           3715851                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             623787680                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts            234474986                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts                217                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                 887425                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents              78519079                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents         223174                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        8257753                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect     10408115                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts             18665868                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts            2014561503                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             604829298                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          27891767                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                            99                       # number of nop insts executed
-system.cpu.iew.exec_refs                    768256899                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                239583236                       # Number of branches executed
-system.cpu.iew.exec_stores                  190695241                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.912102                       # Inst execution rate
-system.cpu.iew.wb_sent                     1977910575                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                    1969035280                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                1321133911                       # num instructions producing a value
-system.cpu.iew.wb_consumers                2129107129                       # num instructions consuming a value
+system.cpu.iew.exec_nop                            50                       # number of nop insts executed
+system.cpu.iew.exec_refs                    796810326                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                245407289                       # Number of branches executed
+system.cpu.iew.exec_stores                  191981028                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.988349                       # Inst execution rate
+system.cpu.iew.wb_sent                     1947397166                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                    1937195623                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                1312629106                       # num instructions producing a value
+system.cpu.iew.wb_consumers                2061058840                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.882214                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.620511                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.911990                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.636871                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts       522107871                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts       572342091                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls             170                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts          15241473                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    853522525                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     2.018780                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.777115                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts          15341577                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    933174586                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.783195                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.675212                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    375117315     43.95%     43.95% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1    185477330     21.73%     65.68% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     70116011      8.21%     73.90% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     33059312      3.87%     77.77% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     18836055      2.21%     79.98% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5     30683416      3.59%     83.57% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6     20461939      2.40%     85.97% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7     11515545      1.35%     87.32% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8    108255602     12.68%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    468896979     50.25%     50.25% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    178641910     19.14%     69.39% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     68227019      7.31%     76.70% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     32102473      3.44%     80.14% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     24397966      2.61%     82.76% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5     27603302      2.96%     85.71% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6     17322198      1.86%     87.57% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7     14774408      1.58%     89.15% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8    101208331     10.85%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    853522525                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    933174586                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts           1544563041                       # Number of instructions committed
-system.cpu.commit.committedOps             1723073853                       # Number of ops (including micro ops) committed
+system.cpu.commit.committedOps             1664032433                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                      660773814                       # Number of memory references committed
-system.cpu.commit.loads                     485926769                       # Number of loads committed
+system.cpu.commit.refs                      633153379                       # Number of memory references committed
+system.cpu.commit.loads                     458306334                       # Number of loads committed
 system.cpu.commit.membars                          62                       # Number of memory barriers committed
 system.cpu.commit.branches                  213462426                       # Number of branches committed
 system.cpu.commit.fp_insts                         36                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                1536941841                       # Number of committed integer instructions.
+system.cpu.commit.int_insts                1477900421                       # Number of committed integer instructions.
 system.cpu.commit.function_calls             13665177                       # Number of function calls committed.
 system.cpu.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu       1061599714     61.61%     61.61% # Class of committed instruction
-system.cpu.commit.op_class_0::IntMult          700322      0.04%     61.65% # Class of committed instruction
-system.cpu.commit.op_class_0::IntDiv                0      0.00%     61.65% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatAdd              0      0.00%     61.65% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatCmp              0      0.00%     61.65% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatCvt              0      0.00%     61.65% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMult             0      0.00%     61.65% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatDiv              0      0.00%     61.65% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     61.65% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAdd               0      0.00%     61.65% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     61.65% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAlu               0      0.00%     61.65% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdCmp               0      0.00%     61.65% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdCvt               0      0.00%     61.65% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMisc              0      0.00%     61.65% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMult              0      0.00%     61.65% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     61.65% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdShift             0      0.00%     61.65% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     61.65% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     61.65% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     61.65% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     61.65% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     61.65% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     61.65% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     61.65% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMisc            3      0.00%     61.65% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     61.65% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     61.65% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     61.65% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead       485926769     28.20%     89.85% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite      174847045     10.15%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu       1030178729     61.91%     61.91% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult          700322      0.04%     61.95% # Class of committed instruction
+system.cpu.commit.op_class_0::IntDiv                0      0.00%     61.95% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatAdd              0      0.00%     61.95% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCmp              0      0.00%     61.95% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCvt              0      0.00%     61.95% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatMult             0      0.00%     61.95% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatDiv              0      0.00%     61.95% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     61.95% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAdd               0      0.00%     61.95% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     61.95% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAlu               0      0.00%     61.95% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCmp               0      0.00%     61.95% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCvt               0      0.00%     61.95% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMisc              0      0.00%     61.95% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMult              0      0.00%     61.95% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     61.95% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShift             0      0.00%     61.95% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     61.95% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     61.95% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     61.95% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     61.95% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     61.95% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     61.95% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     61.95% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMisc            3      0.00%     61.95% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     61.95% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     61.95% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     61.95% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead       458306334     27.54%     89.49% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite      174847045     10.51%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total        1723073853                       # Class of committed instruction
-system.cpu.commit.bw_lim_events             108255602                       # number cycles where commit BW limit reached
+system.cpu.commit.op_class_0::total        1664032433                       # Class of committed instruction
+system.cpu.commit.bw_lim_events             101208331                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                   2990448048                       # The number of ROB reads
-system.cpu.rob.rob_writes                  4566229463                       # The number of ROB writes
-system.cpu.timesIdled                         1335234                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                       116921466                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads                   3068340180                       # The number of ROB reads
+system.cpu.rob.rob_writes                  4552875899                       # The number of ROB writes
+system.cpu.timesIdled                             556                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           50821                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                  1544563023                       # Number of Instructions Simulated
-system.cpu.committedOps                    1723073835                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               0.677296                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.677296                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.476458                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.476458                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads              10016037678                       # number of integer regfile reads
-system.cpu.int_regfile_writes              1949973157                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                       144                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                      144                       # number of floating regfile writes
-system.cpu.misc_regfile_reads               741547581                       # number of misc regfile reads
+system.cpu.committedOps                    1664032415                       # Number of Ops (including micro ops) Simulated
+system.cpu.cpi                               0.655967                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.655967                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.524466                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.524466                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               2376547647                       # number of integer regfile reads
+system.cpu.int_regfile_writes              1366493054                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                       209                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                      233                       # number of floating regfile writes
+system.cpu.cc_regfile_reads                7643535318                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                583887345                       # number of cc regfile writes
+system.cpu.misc_regfile_reads               725285725                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                    124                       # number of misc regfile writes
-system.cpu.toL2Bus.throughput              1637500473                       # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq        7708273                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       7708272                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      3780671                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq      1894131                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp      1894131                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1564                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     22983914                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total          22985478                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        50048                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    856466688                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total      856516736                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus         856516736                       # Total data (bytes)
+system.cpu.toL2Bus.throughput              1691907313                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq        7714547                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       7714546                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback      3783532                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq      1894199                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp      1894199                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1502                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     22999521                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total          23001023                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        48064                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    857057664                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total      857105728                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus         857105728                       # Total data (bytes)
 system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy    10472370339                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          2.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy       1301749                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.occupancy    10479902270                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          2.1                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy       1252249                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy   14750464244                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          2.8                       # Layer utilization (%)
-system.cpu.icache.tags.replacements                21                       # number of replacements
-system.cpu.icache.tags.tagsinuse           633.135504                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           295059337                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs               782                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          377313.730179                       # Average number of references to valid blocks.
+system.cpu.toL2Bus.respLayer1.occupancy   14758141993                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization          2.9                       # Layer utilization (%)
+system.cpu.icache.tags.replacements                15                       # number of replacements
+system.cpu.icache.tags.tagsinuse           614.894819                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           300790815                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs               751                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          400520.392810                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   633.135504                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.309148                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.309148                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024          761                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           25                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2            4                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4          732                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.371582                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         590121892                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        590121892                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    295059337                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       295059337                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     295059337                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        295059337                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    295059337                       # number of overall hits
-system.cpu.icache.overall_hits::total       295059337                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst         1218                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total          1218                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst         1218                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total           1218                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst         1218                       # number of overall misses
-system.cpu.icache.overall_misses::total          1218                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     82722999                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     82722999                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     82722999                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     82722999                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     82722999                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     82722999                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    295060555                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    295060555                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    295060555                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    295060555                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    295060555                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    295060555                       # number of overall (read+write) accesses
+system.cpu.icache.tags.occ_blocks::cpu.inst   614.894819                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.300242                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.300242                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          736                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           24                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2            3                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4          709                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.359375                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses         601584755                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        601584755                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    300790815                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       300790815                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     300790815                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        300790815                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    300790815                       # number of overall hits
+system.cpu.icache.overall_hits::total       300790815                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         1187                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          1187                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         1187                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           1187                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         1187                       # number of overall misses
+system.cpu.icache.overall_misses::total          1187                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     83295499                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     83295499                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     83295499                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     83295499                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     83295499                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     83295499                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    300792002                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    300792002                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    300792002                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    300792002                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    300792002                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    300792002                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000004                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000004                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000004                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000004                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000004                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000004                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67917.076355                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 67917.076355                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 67917.076355                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 67917.076355                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 67917.076355                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 67917.076355                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs          292                       # number of cycles access was blocked
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70173.124684                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 70173.124684                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 70173.124684                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 70173.124684                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 70173.124684                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 70173.124684                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs           65                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                 6                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 1                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    48.666667                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs           65                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
@@ -766,123 +755,123 @@ system.cpu.icache.demand_mshr_hits::cpu.inst          436
 system.cpu.icache.demand_mshr_hits::total          436                       # number of demand (read+write) MSHR hits
 system.cpu.icache.overall_mshr_hits::cpu.inst          436                       # number of overall MSHR hits
 system.cpu.icache.overall_mshr_hits::total          436                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst          782                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total          782                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst          782                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total          782                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst          782                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total          782                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     55396751                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     55396751                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     55396751                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     55396751                       # number of demand (read+write) MSHR miss cycles
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 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
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+system.cpu.l2cache.overall_avg_miss_latency::total 84869.092824                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -891,195 +880,211 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
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 system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            1                       # number of ReadReq MSHR hits
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 system.cpu.l2cache.demand_mshr_hits::cpu.inst            1                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data            6                       # number of demand (read+write) MSHR hits
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+system.cpu.l2cache.demand_mshr_hits::cpu.data            7                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total            8                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.overall_mshr_hits::cpu.inst            1                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data            6                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total            7                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          751                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data      1418861                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total      1419612                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       827456                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       827456                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst          751                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data      2246317                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total      2247068                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst          751                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data      2246317                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total      2247068                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     44796750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 101386052500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 101430849250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  60631607750                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  60631607750                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     44796750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 162017660250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 162062457000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     44796750                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 162017660250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 162062457000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.960358                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.184089                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.184167                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.436853                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.436853                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.960358                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.233952                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.234011                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.960358                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.233952                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.234011                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59649.467377                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 71455.944240                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 71449.698404                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 73274.721254                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 73274.721254                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59649.467377                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72125.911102                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72121.741309                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59649.467377                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72125.911102                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72121.741309                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_hits::cpu.data            7                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total            8                       # number of overall MSHR hits
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+system.cpu.l2cache.ReadExReq_mshr_misses::total       827635                       # number of ReadExReq MSHR misses
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+system.cpu.l2cache.overall_mshr_misses::cpu.data      2246450                       # number of overall MSHR misses
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+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 101708549750                       # number of ReadReq MSHR miss cycles
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+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72362.686534                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements           9597525                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4087.935639                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           657806876                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           9601621                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             68.509981                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle        3523864250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4087.935639                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.998031                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.998031                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements           9603898                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4087.677378                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           678741158                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           9607994                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             70.643379                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle        3511642250                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4087.677378                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.997968                       # Average percentage of cache occupancy
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 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          660                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1         2418                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          657                       # Occupied blocks per task id
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 system.cpu.dcache.tags.age_task_id_blocks_1024::2         1017                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses        1359744661                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses       1359744661                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    490891096                       # number of ReadReq hits
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-system.cpu.dcache.LoadLockedReq_hits::cpu.data           62                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total           62                       # number of LoadLockedReq hits
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+system.cpu.dcache.tags.data_accesses       1403558154                       # Number of data accesses
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 system.cpu.dcache.StoreCondReq_hits::cpu.data           61                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total           61                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     657806753                       # number of demand (read+write) hits
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 system.cpu.dcache.LoadLockedReq_misses::cpu.data            3                       # number of LoadLockedReq misses
 system.cpu.dcache.LoadLockedReq_misses::total            3                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data     17264641                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total       17264641                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data     17264641                       # number of overall misses
-system.cpu.dcache.overall_misses::total      17264641                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 353287122740                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 353287122740                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 298200381062                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 298200381062                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       243250                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total       243250                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 651487503802                       # number of demand (read+write) miss cycles
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-system.cpu.dcache.overall_miss_latency::cpu.data 651487503802                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 651487503802                       # number of overall miss cycles
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+system.cpu.dcache.overall_miss_latency::total 686148162890                       # number of overall miss cycles
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 system.cpu.dcache.WriteReq_accesses::cpu.data    172586047                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total    172586047                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data           65                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total           65                       # number of LoadLockedReq accesses(hits+misses)
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+system.cpu.dcache.SoftPFReq_accesses::total            4                       # number of SoftPFReq accesses(hits+misses)
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 system.cpu.dcache.StoreCondReq_accesses::cpu.data           61                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total           61                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    675071394                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    675071394                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    675071394                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    675071394                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.023074                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.023074                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.032855                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.032855                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.046154                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.046154                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.025575                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.025575                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.025575                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.025575                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30470.887920                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 30470.887920                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52589.042564                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 52589.042564                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 81083.333333                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 81083.333333                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 37735.363498                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 37735.363498                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 37735.363498                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 37735.363498                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs     22798709                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets      4000734                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs           1307566                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets           65131                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    17.435991                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets    61.425957                       # average number of cycles each access was blocked
+system.cpu.dcache.demand_accesses::cpu.data    696974949                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    696974949                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    696974953                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    696974953                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.023933                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.023933                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.032933                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.032933                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.500000                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.500000                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.045455                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.045455                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.026162                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.026162                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.026162                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.026162                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30193.153449                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 30193.153449                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54051.901302                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 54051.901302                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        76000                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        76000                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 37630.321718                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 37630.321718                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 37630.317591                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 37630.317591                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs     28822616                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets      4626055                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs           1847693                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets           65151                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    15.599245                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets    71.005127                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      3780671                       # number of writebacks
-system.cpu.dcache.writebacks::total           3780671                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data      3886759                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total      3886759                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data      3776260                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total      3776260                       # number of WriteReq MSHR hits
+system.cpu.dcache.writebacks::writebacks      3783532                       # number of writebacks
+system.cpu.dcache.writebacks::total           3783532                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data      4836306                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total      4836306                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data      3789617                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total      3789617                       # number of WriteReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            3                       # number of LoadLockedReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::total            3                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      7663019                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      7663019                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      7663019                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      7663019                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      7707492                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      7707492                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data      1894130                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total      1894130                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      9601622                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      9601622                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      9601622                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      9601622                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 191674058756                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 191674058756                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  84036609462                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  84036609462                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 275710668218                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 275710668218                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 275710668218                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 275710668218                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.015339                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.015339                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.demand_mshr_hits::cpu.data      8625923                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      8625923                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      8625923                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      8625923                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      7713796                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      7713796                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data      1894198                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total      1894198                       # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data            1                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total            1                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      9607994                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      9607994                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      9607995                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      9607995                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 192253948507                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 192253948507                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  84881076130                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  84881076130                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data        69500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total        69500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 277135024637                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 277135024637                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 277135094137                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 277135094137                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.014710                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.014710                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.010975                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.010975                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.014223                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.014223                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.014223                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.014223                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24868.538139                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24868.538139                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44366.864715                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44366.864715                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28715.009633                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 28715.009633                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28715.009633                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 28715.009633                       # average overall mshr miss latency
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.250000                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.250000                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.013785                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.013785                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.013785                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.013785                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24923.390314                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24923.390314                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44811.089511                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44811.089511                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data        69500                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total        69500                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28844.212917                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 28844.212917                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28844.217148                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 28844.217148                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt
index 38623e444..4decc9d3b 100644
--- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt
@@ -1,16 +1,16 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.861538                       # Number of seconds simulated
-sim_ticks                                861538200000                       # Number of ticks simulated
-final_tick                               861538200000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.832017                       # Number of seconds simulated
+sim_ticks                                832017490000                       # Number of ticks simulated
+final_tick                               832017490000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1785934                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1992340                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              996171702                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 301680                       # Number of bytes of host memory used
-host_seconds                                   864.85                       # Real time elapsed on the host
+host_inst_rate                                1782051                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1919890                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              959946236                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 306272                       # Number of bytes of host memory used
+host_seconds                                   866.73                       # Real time elapsed on the host
 sim_insts                                  1544563041                       # Number of instructions simulated
-sim_ops                                    1723073853                       # Number of ops (including micro ops) simulated
+sim_ops                                    1664032433                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst        6178262356                       # Number of bytes read from this memory
@@ -21,21 +21,21 @@ system.physmem.bytes_inst_read::total      6178262356                       # Nu
 system.physmem.bytes_written::cpu.data      624158392                       # Number of bytes written to this memory
 system.physmem.bytes_written::total         624158392                       # Number of bytes written to this memory
 system.physmem.num_reads::cpu.inst         1544565589                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data          482384187                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total            2026949776                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data          454909197                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total            1999474786                       # Number of read requests responded to by this memory
 system.physmem.num_writes::cpu.data         172586108                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total            172586108                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst           7171199554                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data           1835539818                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              9006739373                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst      7171199554                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total         7171199554                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data           724469782                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total              724469782                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst          7171199554                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data          2560009600                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             9731209155                       # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput                   9731209155                       # Throughput (bytes/s)
+system.physmem.bw_read::cpu.inst           7425640002                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data           1900666380                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              9326306382                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst      7425640002                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total         7425640002                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data           750174605                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total              750174605                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst          7425640002                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data          2650840985                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total            10076480987                       # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput                  10076480987                       # Throughput (bytes/s)
 system.membus.data_through_bus             8383808419                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
@@ -124,63 +124,65 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                   46                       # Number of system calls
-system.cpu.numCycles                       1723076401                       # number of cpu cycles simulated
+system.cpu.numCycles                       1664034981                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                  1544563041                       # Number of instructions committed
-system.cpu.committedOps                    1723073853                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses            1536941842                       # Number of integer alu accesses
+system.cpu.committedOps                    1664032433                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses            1477900422                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                     36                       # Number of float alu accesses
 system.cpu.num_func_calls                    27330256                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts    177498328                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                   1536941842                       # number of integer instructions
+system.cpu.num_conditional_control_insts    167612489                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                   1477900422                       # number of integer instructions
 system.cpu.num_fp_insts                            36                       # number of float instructions
-system.cpu.num_int_register_reads          7861285293                       # number of times the integer registers were read
-system.cpu.num_int_register_writes         1675132405                       # number of times the integer registers were written
+system.cpu.num_int_register_reads          2605402942                       # number of times the integer registers were read
+system.cpu.num_int_register_writes         1125475224                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                   24                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                  16                       # number of times the floating registers were written
-system.cpu.num_mem_refs                     660773815                       # number of memory refs
-system.cpu.num_load_insts                   485926769                       # Number of load instructions
+system.cpu.num_cc_register_reads           4992096236                       # number of times the CC registers were read
+system.cpu.num_cc_register_writes           518236214                       # number of times the CC registers were written
+system.cpu.num_mem_refs                     633153380                       # number of memory refs
+system.cpu.num_load_insts                   458306334                       # Number of load instructions
 system.cpu.num_store_insts                  174847046                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                 1723076401                       # Number of busy cycles
+system.cpu.num_busy_cycles                 1664034981                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                         213462426                       # Number of branches fetched
 system.cpu.op_class::No_OpClass                     0      0.00%      0.00% # Class of executed instruction
-system.cpu.op_class::IntAlu                1061599760     61.61%     61.61% # Class of executed instruction
-system.cpu.op_class::IntMult                   700322      0.04%     61.65% # Class of executed instruction
-system.cpu.op_class::IntDiv                         0      0.00%     61.65% # Class of executed instruction
-system.cpu.op_class::FloatAdd                       0      0.00%     61.65% # Class of executed instruction
-system.cpu.op_class::FloatCmp                       0      0.00%     61.65% # Class of executed instruction
-system.cpu.op_class::FloatCvt                       0      0.00%     61.65% # Class of executed instruction
-system.cpu.op_class::FloatMult                      0      0.00%     61.65% # Class of executed instruction
-system.cpu.op_class::FloatDiv                       0      0.00%     61.65% # Class of executed instruction
-system.cpu.op_class::FloatSqrt                      0      0.00%     61.65% # Class of executed instruction
-system.cpu.op_class::SimdAdd                        0      0.00%     61.65% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc                     0      0.00%     61.65% # Class of executed instruction
-system.cpu.op_class::SimdAlu                        0      0.00%     61.65% # Class of executed instruction
-system.cpu.op_class::SimdCmp                        0      0.00%     61.65% # Class of executed instruction
-system.cpu.op_class::SimdCvt                        0      0.00%     61.65% # Class of executed instruction
-system.cpu.op_class::SimdMisc                       0      0.00%     61.65% # Class of executed instruction
-system.cpu.op_class::SimdMult                       0      0.00%     61.65% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc                    0      0.00%     61.65% # Class of executed instruction
-system.cpu.op_class::SimdShift                      0      0.00%     61.65% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc                   0      0.00%     61.65% # Class of executed instruction
-system.cpu.op_class::SimdSqrt                       0      0.00%     61.65% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd                   0      0.00%     61.65% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu                   0      0.00%     61.65% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp                   0      0.00%     61.65% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt                   0      0.00%     61.65% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv                   0      0.00%     61.65% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc                  3      0.00%     61.65% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult                  0      0.00%     61.65% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc               0      0.00%     61.65% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt                  0      0.00%     61.65% # Class of executed instruction
-system.cpu.op_class::MemRead                485926769     28.20%     89.85% # Class of executed instruction
-system.cpu.op_class::MemWrite               174847046     10.15%    100.00% # Class of executed instruction
+system.cpu.op_class::IntAlu                1030178775     61.91%     61.91% # Class of executed instruction
+system.cpu.op_class::IntMult                   700322      0.04%     61.95% # Class of executed instruction
+system.cpu.op_class::IntDiv                         0      0.00%     61.95% # Class of executed instruction
+system.cpu.op_class::FloatAdd                       0      0.00%     61.95% # Class of executed instruction
+system.cpu.op_class::FloatCmp                       0      0.00%     61.95% # Class of executed instruction
+system.cpu.op_class::FloatCvt                       0      0.00%     61.95% # Class of executed instruction
+system.cpu.op_class::FloatMult                      0      0.00%     61.95% # Class of executed instruction
+system.cpu.op_class::FloatDiv                       0      0.00%     61.95% # Class of executed instruction
+system.cpu.op_class::FloatSqrt                      0      0.00%     61.95% # Class of executed instruction
+system.cpu.op_class::SimdAdd                        0      0.00%     61.95% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc                     0      0.00%     61.95% # Class of executed instruction
+system.cpu.op_class::SimdAlu                        0      0.00%     61.95% # Class of executed instruction
+system.cpu.op_class::SimdCmp                        0      0.00%     61.95% # Class of executed instruction
+system.cpu.op_class::SimdCvt                        0      0.00%     61.95% # Class of executed instruction
+system.cpu.op_class::SimdMisc                       0      0.00%     61.95% # Class of executed instruction
+system.cpu.op_class::SimdMult                       0      0.00%     61.95% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc                    0      0.00%     61.95% # Class of executed instruction
+system.cpu.op_class::SimdShift                      0      0.00%     61.95% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc                   0      0.00%     61.95% # Class of executed instruction
+system.cpu.op_class::SimdSqrt                       0      0.00%     61.95% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd                   0      0.00%     61.95% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu                   0      0.00%     61.95% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp                   0      0.00%     61.95% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt                   0      0.00%     61.95% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv                   0      0.00%     61.95% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc                  3      0.00%     61.95% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult                  0      0.00%     61.95% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc               0      0.00%     61.95% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt                  0      0.00%     61.95% # Class of executed instruction
+system.cpu.op_class::MemRead                458306334     27.54%     89.49% # Class of executed instruction
+system.cpu.op_class::MemWrite               174847046     10.51%    100.00% # Class of executed instruction
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::total                 1723073900                       # Class of executed instruction
+system.cpu.op_class::total                 1664032480                       # Class of executed instruction
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt
index de9b22f80..8e22dfda9 100644
--- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt
@@ -1,16 +1,16 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.391205                       # Number of seconds simulated
-sim_ticks                                2391205115000                       # Number of ticks simulated
-final_tick                               2391205115000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.363671                       # Number of seconds simulated
+sim_ticks                                2363670998000                       # Number of ticks simulated
+final_tick                               2363670998000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 867002                       # Simulator instruction rate (inst/s)
-host_op_rate                                   967582                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1347305237                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 310408                       # Number of bytes of host memory used
-host_seconds                                  1774.81                       # Real time elapsed on the host
+host_inst_rate                                1066052                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1148821                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1637550718                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 316024                       # Number of bytes of host memory used
+host_seconds                                  1443.42                       # Real time elapsed on the host
 sim_insts                                  1538759601                       # Number of instructions simulated
-sim_ops                                    1717270334                       # Number of ops (including micro ops) simulated
+sim_ops                                    1658228914                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst             39424                       # Number of bytes read from this memory
@@ -25,18 +25,18 @@ system.physmem.num_reads::cpu.data            1958158                       # Nu
 system.physmem.num_reads::total               1958774                       # Number of read requests responded to by this memory
 system.physmem.num_writes::writebacks         1017198                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total              1017198                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst                16487                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             52409604                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                52426091                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst           16487                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total              16487                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          27225047                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               27225047                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          27225047                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst               16487                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            52409604                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               79651138                       # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput                     79651138                       # Throughput (bytes/s)
+system.physmem.bw_read::cpu.inst                16679                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             53020117                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                53036796                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst           16679                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total              16679                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          27542188                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               27542188                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          27542188                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst               16679                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            53020117                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               80578984                       # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput                     80578984                       # Throughput (bytes/s)
 system.membus.trans_dist::ReadReq             1177898                       # Transaction distribution
 system.membus.trans_dist::ReadResp            1177898                       # Transaction distribution
 system.membus.trans_dist::Writeback           1017198                       # Transaction distribution
@@ -48,9 +48,9 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    1
 system.membus.tot_pkt_size::total           190462208                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.data_through_bus              190462208                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy         11113556000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy         11138507500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.5                       # Layer utilization (%)
-system.membus.respLayer1.occupancy        17628966000                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy        17642613000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.7                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
@@ -138,73 +138,75 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                   46                       # Number of system calls
-system.cpu.numCycles                       4782410230                       # number of cpu cycles simulated
+system.cpu.numCycles                       4727341996                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                  1538759601                       # Number of instructions committed
-system.cpu.committedOps                    1717270334                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses            1536941842                       # Number of integer alu accesses
+system.cpu.committedOps                    1658228914                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses            1477900422                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                     36                       # Number of float alu accesses
 system.cpu.num_func_calls                    27330256                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts    177498328                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                   1536941842                       # number of integer instructions
+system.cpu.num_conditional_control_insts    167612489                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                   1477900422                       # number of integer instructions
 system.cpu.num_fp_insts                            36                       # number of float instructions
-system.cpu.num_int_register_reads          9304895467                       # number of times the integer registers were read
-system.cpu.num_int_register_writes         1675132405                       # number of times the integer registers were written
+system.cpu.num_int_register_reads          2601860372                       # number of times the integer registers were read
+system.cpu.num_int_register_writes         1125475224                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                   24                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                  16                       # number of times the floating registers were written
-system.cpu.num_mem_refs                     660773815                       # number of memory refs
-system.cpu.num_load_insts                   485926769                       # Number of load instructions
+system.cpu.num_cc_register_reads           6356387675                       # number of times the CC registers were read
+system.cpu.num_cc_register_writes           518236214                       # number of times the CC registers were written
+system.cpu.num_mem_refs                     633153380                       # number of memory refs
+system.cpu.num_load_insts                   458306334                       # Number of load instructions
 system.cpu.num_store_insts                  174847046                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                 4782410230                       # Number of busy cycles
+system.cpu.num_busy_cycles                 4727341996                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                         213462426                       # Number of branches fetched
 system.cpu.op_class::No_OpClass                     0      0.00%      0.00% # Class of executed instruction
-system.cpu.op_class::IntAlu                1061599760     61.61%     61.61% # Class of executed instruction
-system.cpu.op_class::IntMult                   700322      0.04%     61.65% # Class of executed instruction
-system.cpu.op_class::IntDiv                         0      0.00%     61.65% # Class of executed instruction
-system.cpu.op_class::FloatAdd                       0      0.00%     61.65% # Class of executed instruction
-system.cpu.op_class::FloatCmp                       0      0.00%     61.65% # Class of executed instruction
-system.cpu.op_class::FloatCvt                       0      0.00%     61.65% # Class of executed instruction
-system.cpu.op_class::FloatMult                      0      0.00%     61.65% # Class of executed instruction
-system.cpu.op_class::FloatDiv                       0      0.00%     61.65% # Class of executed instruction
-system.cpu.op_class::FloatSqrt                      0      0.00%     61.65% # Class of executed instruction
-system.cpu.op_class::SimdAdd                        0      0.00%     61.65% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc                     0      0.00%     61.65% # Class of executed instruction
-system.cpu.op_class::SimdAlu                        0      0.00%     61.65% # Class of executed instruction
-system.cpu.op_class::SimdCmp                        0      0.00%     61.65% # Class of executed instruction
-system.cpu.op_class::SimdCvt                        0      0.00%     61.65% # Class of executed instruction
-system.cpu.op_class::SimdMisc                       0      0.00%     61.65% # Class of executed instruction
-system.cpu.op_class::SimdMult                       0      0.00%     61.65% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc                    0      0.00%     61.65% # Class of executed instruction
-system.cpu.op_class::SimdShift                      0      0.00%     61.65% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc                   0      0.00%     61.65% # Class of executed instruction
-system.cpu.op_class::SimdSqrt                       0      0.00%     61.65% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd                   0      0.00%     61.65% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu                   0      0.00%     61.65% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp                   0      0.00%     61.65% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt                   0      0.00%     61.65% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv                   0      0.00%     61.65% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc                  3      0.00%     61.65% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult                  0      0.00%     61.65% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc               0      0.00%     61.65% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt                  0      0.00%     61.65% # Class of executed instruction
-system.cpu.op_class::MemRead                485926769     28.20%     89.85% # Class of executed instruction
-system.cpu.op_class::MemWrite               174847046     10.15%    100.00% # Class of executed instruction
+system.cpu.op_class::IntAlu                1030178775     61.91%     61.91% # Class of executed instruction
+system.cpu.op_class::IntMult                   700322      0.04%     61.95% # Class of executed instruction
+system.cpu.op_class::IntDiv                         0      0.00%     61.95% # Class of executed instruction
+system.cpu.op_class::FloatAdd                       0      0.00%     61.95% # Class of executed instruction
+system.cpu.op_class::FloatCmp                       0      0.00%     61.95% # Class of executed instruction
+system.cpu.op_class::FloatCvt                       0      0.00%     61.95% # Class of executed instruction
+system.cpu.op_class::FloatMult                      0      0.00%     61.95% # Class of executed instruction
+system.cpu.op_class::FloatDiv                       0      0.00%     61.95% # Class of executed instruction
+system.cpu.op_class::FloatSqrt                      0      0.00%     61.95% # Class of executed instruction
+system.cpu.op_class::SimdAdd                        0      0.00%     61.95% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc                     0      0.00%     61.95% # Class of executed instruction
+system.cpu.op_class::SimdAlu                        0      0.00%     61.95% # Class of executed instruction
+system.cpu.op_class::SimdCmp                        0      0.00%     61.95% # Class of executed instruction
+system.cpu.op_class::SimdCvt                        0      0.00%     61.95% # Class of executed instruction
+system.cpu.op_class::SimdMisc                       0      0.00%     61.95% # Class of executed instruction
+system.cpu.op_class::SimdMult                       0      0.00%     61.95% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc                    0      0.00%     61.95% # Class of executed instruction
+system.cpu.op_class::SimdShift                      0      0.00%     61.95% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc                   0      0.00%     61.95% # Class of executed instruction
+system.cpu.op_class::SimdSqrt                       0      0.00%     61.95% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd                   0      0.00%     61.95% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu                   0      0.00%     61.95% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp                   0      0.00%     61.95% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt                   0      0.00%     61.95% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv                   0      0.00%     61.95% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc                  3      0.00%     61.95% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult                  0      0.00%     61.95% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc               0      0.00%     61.95% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt                  0      0.00%     61.95% # Class of executed instruction
+system.cpu.op_class::MemRead                458306334     27.54%     89.49% # Class of executed instruction
+system.cpu.op_class::MemWrite               174847046     10.51%    100.00% # Class of executed instruction
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::total                 1723073900                       # Class of executed instruction
+system.cpu.op_class::total                 1664032480                       # Class of executed instruction
 system.cpu.icache.tags.replacements                 7                       # number of replacements
-system.cpu.icache.tags.tagsinuse           514.976015                       # Cycle average of tags in use
+system.cpu.icache.tags.tagsinuse           515.012865                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs          1544564952                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs               638                       # Sample count of references to valid blocks.
 system.cpu.icache.tags.avg_refs          2420948.200627                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   514.976015                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.251453                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.251453                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst   515.012865                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.251471                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.251471                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          631                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           24                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::2            1                       # Occupied blocks per task id
@@ -224,12 +226,12 @@ system.cpu.icache.demand_misses::cpu.inst          638                       # n
 system.cpu.icache.demand_misses::total            638                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst          638                       # number of overall misses
 system.cpu.icache.overall_misses::total           638                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     34233000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     34233000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     34233000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     34233000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     34233000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     34233000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     34244500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     34244500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     34244500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     34244500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     34244500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     34244500                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst   1544565590                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total   1544565590                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst   1544565590                       # number of demand (read+write) accesses
@@ -242,12 +244,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.000000
 system.cpu.icache.demand_miss_rate::total     0.000000                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000000                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000000                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53656.739812                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 53656.739812                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 53656.739812                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 53656.739812                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 53656.739812                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 53656.739812                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53674.764890                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 53674.764890                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 53674.764890                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 53674.764890                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 53674.764890                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 53674.764890                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -262,44 +264,44 @@ system.cpu.icache.demand_mshr_misses::cpu.inst          638
 system.cpu.icache.demand_mshr_misses::total          638                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          638                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          638                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     32957000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     32957000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     32957000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     32957000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     32957000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     32957000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     32968500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     32968500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     32968500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     32968500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     32968500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     32968500                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000000                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000000                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000000                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000000                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000000                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000000                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51656.739812                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51656.739812                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51656.739812                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 51656.739812                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51656.739812                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 51656.739812                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51674.764890                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51674.764890                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51674.764890                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 51674.764890                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51674.764890                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 51674.764890                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements          1926075                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        30987.094489                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse        31008.537310                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs            8967572                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs          1955843                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs             4.585016                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle     154026636000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 15648.493745                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst    24.153175                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 15314.447570                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.477554                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.000737                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.467360                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.945651                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.warmup_cycle     150067859000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 15658.172881                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst    23.876038                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 15326.488392                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.477850                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.000729                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.467727                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.946305                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024        29768                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0           83                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::1           30                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::2         1082                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         1693                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        26880                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         1732                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        26841                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.908447                       # Percentage of cache occupancy per task id
 system.cpu.l2cache.tags.tag_accesses        106351328                       # Number of tag accesses
 system.cpu.l2cache.tags.data_accesses       106351328                       # Number of data accesses
@@ -327,17 +329,17 @@ system.cpu.l2cache.demand_misses::total       1958774                       # nu
 system.cpu.l2cache.overall_misses::cpu.inst          616                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data      1958158                       # number of overall misses
 system.cpu.l2cache.overall_misses::total      1958774                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     32099000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data  61225555000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total  61257654000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  40608829000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total  40608829000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     32099000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 101834384000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 101866483000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     32099000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 101834384000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 101866483000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     32110500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data  61239144500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total  61271255000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  40608894000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total  40608894000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     32110500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 101848038500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 101880149000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     32110500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 101848038500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 101880149000                       # number of overall miss cycles
 system.cpu.l2cache.ReadReq_accesses::cpu.inst          638                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::cpu.data      7226087                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::total      7226725                       # number of ReadReq accesses(hits+misses)
@@ -362,17 +364,17 @@ system.cpu.l2cache.demand_miss_rate::total     0.214875                       #
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.965517                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.214823                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.214875                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52108.766234                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52005.853313                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 52005.907133                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52004.196569                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52004.196569                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52108.766234                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52005.192635                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 52005.225207                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52108.766234                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52005.192635                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 52005.225207                       # average overall miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52127.435065                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52017.396427                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 52017.453973                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52004.279809                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52004.279809                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52127.435065                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52012.165770                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 52012.202020                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52127.435065                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52012.165770                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 52012.202020                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -394,17 +396,17 @@ system.cpu.l2cache.demand_mshr_misses::total      1958774
 system.cpu.l2cache.overall_mshr_misses::cpu.inst          616                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data      1958158                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total      1958774                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     24707000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  47098171000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total  47122878000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     24708000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  47098189000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total  47122897000                       # number of ReadReq MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  31238317000                       # number of ReadExReq MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  31238317000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     24707000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  78336488000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  78361195000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     24707000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  78336488000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  78361195000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     24708000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  78336506000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  78361214000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     24708000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  78336506000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  78361214000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.965517                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.162921                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.162992                       # mshr miss rate for ReadReq accesses
@@ -416,92 +418,98 @@ system.cpu.l2cache.demand_mshr_miss_rate::total     0.214875
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.965517                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.214823                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.214875                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40108.766234                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40005.853313                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40005.907133                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40110.389610                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40005.868602                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40005.923263                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40004.196569                       # average ReadExReq mshr miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40004.196569                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40108.766234                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40005.192635                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40005.225207                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40108.766234                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40005.192635                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40005.225207                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40110.389610                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40005.201827                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40005.234907                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40110.389610                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40005.201827                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40005.234907                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.dcache.tags.replacements           9111140                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4083.522356                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           645855059                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse          4083.733705                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           618380069                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs           9115236                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             70.854453                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle       25914401000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4083.522356                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.996954                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.996954                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.avg_refs             67.840270                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle       25164666000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4083.733705                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.997005                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.997005                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          157                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1         1214                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          158                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1         1213                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::2         2578                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::3          146                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::4            1                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses        1319055826                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses       1319055826                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    475158039                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       475158039                       # number of ReadReq hits
+system.cpu.dcache.tags.tag_accesses        1264105846                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses       1264105846                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    447683049                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       447683049                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data    170696898                       # number of WriteReq hits
 system.cpu.dcache.WriteReq_hits::total      170696898                       # number of WriteReq hits
 system.cpu.dcache.LoadLockedReq_hits::cpu.data           61                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total           61                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data           61                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total           61                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     645854937                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        645854937                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    645854937                       # number of overall hits
-system.cpu.dcache.overall_hits::total       645854937                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      7226087                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       7226087                       # number of ReadReq misses
+system.cpu.dcache.demand_hits::cpu.data     618379947                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        618379947                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    618379947                       # number of overall hits
+system.cpu.dcache.overall_hits::total       618379947                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      7226086                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       7226086                       # number of ReadReq misses
 system.cpu.dcache.WriteReq_misses::cpu.data      1889149                       # number of WriteReq misses
 system.cpu.dcache.WriteReq_misses::total      1889149                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data      9115236                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        9115236                       # number of demand (read+write) misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data            1                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total            1                       # number of SoftPFReq misses
+system.cpu.dcache.demand_misses::cpu.data      9115235                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        9115235                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data      9115236                       # number of overall misses
 system.cpu.dcache.overall_misses::total       9115236                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 143391866000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 143391866000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  57359006000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  57359006000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 200750872000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 200750872000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 200750872000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 200750872000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    482384126                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    482384126                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 143405400500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 143405400500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  57359071000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  57359071000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 200764471500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 200764471500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 200764471500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 200764471500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    454909135                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    454909135                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data    172586047                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total    172586047                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data            1                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total            1                       # number of SoftPFReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::cpu.data           61                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::total           61                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data           61                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total           61                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    654970173                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    654970173                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    654970173                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    654970173                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.014980                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.014980                       # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data    627495182                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    627495182                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    627495183                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    627495183                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.015885                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.015885                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.010946                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_miss_rate::total     0.010946                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.013917                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.013917                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.013917                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.013917                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19843.639580                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 19843.639580                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30362.351514                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 30362.351514                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 22023.661483                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 22023.661483                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 22023.661483                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 22023.661483                       # average overall miss latency
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data            1                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total            1                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.014526                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.014526                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.014526                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.014526                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19845.515332                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 19845.515332                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30362.385921                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 30362.385921                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 22025.155852                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 22025.155852                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 22025.153435                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 22025.153435                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -512,40 +520,48 @@ system.cpu.dcache.fast_writes                       0                       # nu
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks      3697418                       # number of writebacks
 system.cpu.dcache.writebacks::total           3697418                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      7226087                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      7226087                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      7226086                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      7226086                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data      1889149                       # number of WriteReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::total      1889149                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      9115236                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      9115236                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data            1                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total            1                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      9115235                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      9115235                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data      9115236                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total      9115236                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 128939692000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 128939692000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  53580708000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  53580708000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 182520400000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 182520400000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 182520400000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 182520400000                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.014980                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.014980                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 128953228500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 128953228500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  53580773000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  53580773000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data        53000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total        53000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 182534001500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 182534001500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 182534054500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 182534054500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.015885                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.015885                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.010946                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.010946                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.013917                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.013917                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.013917                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.013917                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17843.639580                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17843.639580                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28362.351514                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28362.351514                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20023.661483                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 20023.661483                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20023.661483                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 20023.661483                       # average overall mshr miss latency
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total            1                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.014526                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.014526                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.014526                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.014526                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17845.515332                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17845.515332                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28362.385921                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28362.385921                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data        53000                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total        53000                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20025.155852                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 20025.155852                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20025.159469                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 20025.159469                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.throughput               342944519                       # Throughput (bytes/s)
+system.cpu.toL2Bus.throughput               346939438                       # Throughput (bytes/s)
 system.cpu.toL2Bus.trans_dist::ReadReq        7226725                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadResp       7226725                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::Writeback      3697418                       # Transaction distribution
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt
index 2c6817645..478ad3d97 100644
--- a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.051523                       # Nu
 sim_ticks                                 51522973500                       # Number of ticks simulated
 final_tick                                51522973500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 192794                       # Simulator instruction rate (inst/s)
-host_op_rate                                   192794                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              108084557                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 244692                       # Number of bytes of host memory used
-host_seconds                                   476.69                       # Real time elapsed on the host
+host_inst_rate                                 335661                       # Simulator instruction rate (inst/s)
+host_op_rate                                   335661                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              188179142                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 271092                       # Number of bytes of host memory used
+host_seconds                                   273.80                       # Real time elapsed on the host
 sim_insts                                    91903089                       # Number of instructions simulated
 sim_ops                                      91903089                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -196,12 +196,12 @@ system.physmem.bytesPerActivate::768-895           30      3.09%     85.57% # By
 system.physmem.bytesPerActivate::896-1023           24      2.47%     88.04% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::1024-1151          116     11.96%    100.00% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::total            970                       # Bytes accessed per row activation
-system.physmem.totQLat                       35128750                       # Total ticks spent queuing
-system.physmem.totMemAccLat                 134766250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totQLat                       35079750                       # Total ticks spent queuing
+system.physmem.totMemAccLat                 134717250                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                     26570000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        6610.60                       # Average queueing delay per DRAM burst
+system.physmem.avgQLat                        6601.38                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  25360.60                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  25351.38                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                           6.60                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                        6.60                       # Average system read bandwidth in MiByte/s
@@ -218,10 +218,10 @@ system.physmem.readRowHitRate                   81.65                       # Ro
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
 system.physmem.avgGap                      9695689.12                       # Average gap between requests
 system.physmem.pageHitRate                      81.65                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE      48460398500                       # Time in different power states
+system.physmem.memoryStateTime::IDLE      48460480000                       # Time in different power states
 system.physmem.memoryStateTime::REF        1720420000                       # Time in different power states
 system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT        1341071500                       # Time in different power states
+system.physmem.memoryStateTime::ACT        1340990000                       # Time in different power states
 system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
 system.membus.throughput                      6600861                       # Throughput (bytes/s)
 system.membus.trans_dist::ReadReq                3595                       # Transaction distribution
@@ -234,40 +234,40 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port
 system.membus.tot_pkt_size::total              340096                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.data_through_bus                 340096                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy             6106000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy             6107000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           49717250                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy           49715750                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.branchPred.lookups                11407310                       # Number of BP lookups
-system.cpu.branchPred.condPredicted           8177170                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            788660                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups              6672659                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                 5348436                       # Number of BTB hits
+system.cpu.branchPred.lookups                11407320                       # Number of BP lookups
+system.cpu.branchPred.condPredicted           8177175                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            788662                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups              6672694                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                 5348459                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             80.154493                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 1172954                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.BTBHitPct             80.154417                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 1172953                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect                216                       # Number of incorrect RAS predictions.
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                     20390002                       # DTB read hits
+system.cpu.dtb.read_hits                     20390003                       # DTB read hits
 system.cpu.dtb.read_misses                      46972                       # DTB read misses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                 20436974                       # DTB read accesses
-system.cpu.dtb.write_hits                     6579989                       # DTB write hits
+system.cpu.dtb.read_accesses                 20436975                       # DTB read accesses
+system.cpu.dtb.write_hits                     6579991                       # DTB write hits
 system.cpu.dtb.write_misses                       273                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses                 6580262                       # DTB write accesses
-system.cpu.dtb.data_hits                     26969991                       # DTB hits
+system.cpu.dtb.write_accesses                 6580264                       # DTB write accesses
+system.cpu.dtb.data_hits                     26969994                       # DTB hits
 system.cpu.dtb.data_misses                      47245                       # DTB misses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                 27017236                       # DTB accesses
-system.cpu.itb.fetch_hits                    22956123                       # ITB hits
+system.cpu.dtb.data_accesses                 27017239                       # DTB accesses
+system.cpu.itb.fetch_hits                    22956162                       # ITB hits
 system.cpu.itb.fetch_misses                        88                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                22956211                       # ITB accesses
+system.cpu.itb.fetch_accesses                22956250                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -286,19 +286,19 @@ system.cpu.numWorkItemsStarted                      0                       # nu
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                    91903089                       # Number of instructions committed
 system.cpu.committedOps                      91903089                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                       2250201                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps                       2250216                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
 system.cpu.cpi                               1.121246                       # CPI: cycles per instruction
 system.cpu.ipc                               0.891865                       # IPC: instructions per cycle
-system.cpu.tickCycles                       100852498                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                         2193449                       # Total number of cycles that the object has spent stopped
+system.cpu.tickCycles                       100852685                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                         2193262                       # Total number of cycles that the object has spent stopped
 system.cpu.icache.tags.replacements             13697                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1640.300459                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            22940462                       # Total number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse          1640.300457                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            22940501                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs             15661                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs           1464.814635                       # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs           1464.817125                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1640.300459                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_blocks::cpu.inst  1640.300457                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.800928                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.800928                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         1964                       # Occupied blocks per task id
@@ -308,44 +308,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2          670
 system.cpu.icache.tags.age_task_id_blocks_1024::3          149                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::4          947                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.958984                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          45927907                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         45927907                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     22940462                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        22940462                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      22940462                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         22940462                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     22940462                       # number of overall hits
-system.cpu.icache.overall_hits::total        22940462                       # number of overall hits
+system.cpu.icache.tags.tag_accesses          45927985                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         45927985                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     22940501                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        22940501                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      22940501                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         22940501                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     22940501                       # number of overall hits
+system.cpu.icache.overall_hits::total        22940501                       # number of overall hits
 system.cpu.icache.ReadReq_misses::cpu.inst        15661                       # number of ReadReq misses
 system.cpu.icache.ReadReq_misses::total         15661                       # number of ReadReq misses
 system.cpu.icache.demand_misses::cpu.inst        15661                       # number of demand (read+write) misses
 system.cpu.icache.demand_misses::total          15661                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst        15661                       # number of overall misses
 system.cpu.icache.overall_misses::total         15661                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    385817000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    385817000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    385817000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    385817000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    385817000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    385817000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     22956123                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     22956123                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     22956123                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     22956123                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     22956123                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     22956123                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    385791500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    385791500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    385791500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    385791500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    385791500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    385791500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     22956162                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     22956162                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     22956162                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     22956162                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     22956162                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     22956162                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000682                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000682                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000682                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000682                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000682                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000682                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24635.527744                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 24635.527744                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 24635.527744                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 24635.527744                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 24635.527744                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 24635.527744                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24633.899496                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 24633.899496                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 24633.899496                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 24633.899496                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 24633.899496                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 24633.899496                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -360,24 +360,24 @@ system.cpu.icache.demand_mshr_misses::cpu.inst        15661
 system.cpu.icache.demand_mshr_misses::total        15661                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst        15661                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total        15661                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    353131000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    353131000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    353131000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    353131000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    353131000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    353131000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    353105500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    353105500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    353105500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    353105500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    353105500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    353105500                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000682                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000682                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000682                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000682                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000682                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000682                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22548.432412                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22548.432412                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22548.432412                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 22548.432412                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22548.432412                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 22548.432412                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22546.804163                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22546.804163                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22546.804163                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 22546.804163                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22546.804163                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 22546.804163                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.throughput                22356474                       # Throughput (bytes/s)
 system.cpu.toL2Bus.trans_dist::ReadReq          16146                       # Transaction distribution
@@ -400,13 +400,13 @@ system.cpu.toL2Bus.respLayer0.utilization          0.0                       # L
 system.cpu.toL2Bus.respLayer1.occupancy       3734250                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse         2477.580709                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse         2477.580697                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs              12565                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs             3661                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs             3.432122                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks    17.790278                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  2459.790431                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::writebacks    17.790277                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  2459.790419                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_percent::writebacks     0.000543                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.075067                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.075610                       # Average percentage of cache occupancy
@@ -437,14 +437,14 @@ system.cpu.l2cache.demand_misses::cpu.inst         5314                       #
 system.cpu.l2cache.demand_misses::total          5314                       # number of demand (read+write) misses
 system.cpu.l2cache.overall_misses::cpu.inst         5314                       # number of overall misses
 system.cpu.l2cache.overall_misses::total         5314                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    245039250                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total    245039250                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst    117228000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total    117228000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    362267250                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total    362267250                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    362267250                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total    362267250                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    245013750                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total    245013750                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst    117202000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total    117202000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    362215750                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total    362215750                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    362215750                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    362215750                       # number of overall miss cycles
 system.cpu.l2cache.ReadReq_accesses::cpu.inst        16146                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::total        16146                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.Writeback_accesses::writebacks          107                       # number of Writeback accesses(hits+misses)
@@ -463,14 +463,14 @@ system.cpu.l2cache.demand_miss_rate::cpu.inst     0.297021
 system.cpu.l2cache.demand_miss_rate::total     0.297021                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.297021                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.297021                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68161.126565                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 68161.126565                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 68195.462478                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68195.462478                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68172.233722                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 68172.233722                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68172.233722                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 68172.233722                       # average overall miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68154.033380                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 68154.033380                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 68180.337405                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68180.337405                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68162.542341                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 68162.542341                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68162.542341                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 68162.542341                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -487,14 +487,14 @@ system.cpu.l2cache.demand_mshr_misses::cpu.inst         5314
 system.cpu.l2cache.demand_mshr_misses::total         5314                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.inst         5314                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total         5314                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    199861250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total    199861250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst     95675500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     95675500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    295536750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    295536750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    295536750                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    295536750                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    199838750                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total    199838750                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst     95648000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     95648000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    295486750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    295486750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    295486750                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    295486750                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.222656                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.222656                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst     0.985100                       # mshr miss rate for ReadExReq accesses
@@ -503,22 +503,22 @@ system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.297021
 system.cpu.l2cache.demand_mshr_miss_rate::total     0.297021                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.297021                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.297021                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55594.228095                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55594.228095                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 55657.649796                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55657.649796                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55614.744072                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55614.744072                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55614.744072                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55614.744072                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55587.969402                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55587.969402                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 55641.652123                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55641.652123                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55605.334964                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55605.334964                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55605.334964                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55605.334964                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.dcache.tags.replacements               157                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          1448.553123                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            26545427                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse          1448.553115                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            26545428                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs              2230                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs          11903.778924                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs          11903.779372                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.inst  1448.553123                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_blocks::cpu.inst  1448.553115                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.inst     0.353651                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.353651                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         2073                       # Occupied blocks per task id
@@ -528,16 +528,16 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2          226
 system.cpu.dcache.tags.age_task_id_blocks_1024::3          405                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::4         1380                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024     0.506104                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          53099944                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         53099944                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.inst     20047235                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        20047235                       # number of ReadReq hits
+system.cpu.dcache.tags.tag_accesses          53099946                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         53099946                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.inst     20047236                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        20047236                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.inst      6498192                       # number of WriteReq hits
 system.cpu.dcache.WriteReq_hits::total        6498192                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.inst      26545427                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         26545427                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.inst     26545427                       # number of overall hits
-system.cpu.dcache.overall_hits::total        26545427                       # number of overall hits
+system.cpu.dcache.demand_hits::cpu.inst      26545428                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         26545428                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.inst     26545428                       # number of overall hits
+system.cpu.dcache.overall_hits::total        26545428                       # number of overall hits
 system.cpu.dcache.ReadReq_misses::cpu.inst          519                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_misses::total           519                       # number of ReadReq misses
 system.cpu.dcache.WriteReq_misses::cpu.inst         2911                       # number of WriteReq misses
@@ -548,20 +548,20 @@ system.cpu.dcache.overall_misses::cpu.inst         3430                       #
 system.cpu.dcache.overall_misses::total          3430                       # number of overall misses
 system.cpu.dcache.ReadReq_miss_latency::cpu.inst     36876750                       # number of ReadReq miss cycles
 system.cpu.dcache.ReadReq_miss_latency::total     36876750                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.inst    198662500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total    198662500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.inst    235539250                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total    235539250                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.inst    235539250                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total    235539250                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.inst     20047754                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     20047754                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_miss_latency::cpu.inst    198611000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total    198611000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.inst    235487750                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total    235487750                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.inst    235487750                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total    235487750                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.inst     20047755                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     20047755                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.inst      6501103                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total      6501103                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.inst     26548857                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     26548857                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.inst     26548857                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     26548857                       # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.inst     26548858                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     26548858                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.inst     26548858                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     26548858                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.inst     0.000026                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.000026                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.inst     0.000448                       # miss rate for WriteReq accesses
@@ -572,12 +572,12 @@ system.cpu.dcache.overall_miss_rate::cpu.inst     0.000129
 system.cpu.dcache.overall_miss_rate::total     0.000129                       # miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 71053.468208                       # average ReadReq miss latency
 system.cpu.dcache.ReadReq_avg_miss_latency::total 71053.468208                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 68245.448300                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 68245.448300                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.inst 68670.335277                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 68670.335277                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.inst 68670.335277                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 68670.335277                       # average overall miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 68227.756785                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 68227.756785                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.inst 68655.320700                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 68655.320700                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.inst 68655.320700                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 68655.320700                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -606,12 +606,12 @@ system.cpu.dcache.overall_mshr_misses::cpu.inst         2230
 system.cpu.dcache.overall_mshr_misses::total         2230                       # number of overall MSHR misses
 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst     33572250                       # number of ReadReq MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_latency::total     33572250                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst    119233500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total    119233500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.inst    152805750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total    152805750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.inst    152805750                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total    152805750                       # number of overall MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst    119207500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total    119207500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.inst    152779750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total    152779750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.inst    152779750                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total    152779750                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst     0.000024                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000024                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst     0.000268                       # mshr miss rate for WriteReq accesses
@@ -622,12 +622,12 @@ system.cpu.dcache.overall_mshr_miss_rate::cpu.inst     0.000084
 system.cpu.dcache.overall_mshr_miss_rate::total     0.000084                       # mshr miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 69221.134021                       # average ReadReq mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 69221.134021                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 68328.653295                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68328.653295                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 68522.757848                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 68522.757848                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 68522.757848                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 68522.757848                       # average overall mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 68313.753582                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68313.753582                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 68511.098655                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 68511.098655                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 68511.098655                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 68511.098655                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
index 35ce90696..5c7163ec8 100644
--- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,34 +1,34 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.023058                       # Number of seconds simulated
-sim_ticks                                 23058360500                       # Number of ticks simulated
-final_tick                                23058360500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.022159                       # Number of seconds simulated
+sim_ticks                                 22159411000                       # Number of ticks simulated
+final_tick                                22159411000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 185744                       # Simulator instruction rate (inst/s)
-host_op_rate                                   185744                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               50878767                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 227216                       # Number of bytes of host memory used
-host_seconds                                   453.20                       # Real time elapsed on the host
+host_inst_rate                                 150496                       # Simulator instruction rate (inst/s)
+host_op_rate                                   150496                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               39616568                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 240828                       # Number of bytes of host memory used
+host_seconds                                   559.35                       # Real time elapsed on the host
 sim_insts                                    84179709                       # Number of instructions simulated
 sim_ops                                      84179709                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            196416                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data            138432                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst            196160                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data            138688                       # Number of bytes read from this memory
 system.physmem.bytes_read::total               334848                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       196416                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          196416                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst               3069                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data               2163                       # Number of read requests responded to by this memory
+system.physmem.bytes_inst_read::cpu.inst       196160                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          196160                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst               3065                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data               2167                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                  5232                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst              8518212                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              6003549                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                14521761                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         8518212                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            8518212                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             8518212                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             6003549                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               14521761                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst              8852221                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              6258650                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                15110871                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         8852221                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            8852221                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             8852221                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             6258650                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               15110871                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.readReqs                          5232                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
 system.physmem.readBursts                        5232                       # Number of DRAM read bursts, including those serviced by the write queue
@@ -42,20 +42,20 @@ system.physmem.servicedByWrQ                        0                       # Nu
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
 system.physmem.perBankRdBursts::0                 471                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                 291                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                 289                       # Per bank write bursts
 system.physmem.perBankRdBursts::2                 302                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                 524                       # Per bank write bursts
-system.physmem.perBankRdBursts::4                 220                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                 225                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                 219                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                 286                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                 240                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                 278                       # Per bank write bursts
-system.physmem.perBankRdBursts::10                248                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                 527                       # Per bank write bursts
+system.physmem.perBankRdBursts::4                 218                       # Per bank write bursts
+system.physmem.perBankRdBursts::5                 224                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                 217                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                 287                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                 239                       # Per bank write bursts
+system.physmem.perBankRdBursts::9                 281                       # Per bank write bursts
+system.physmem.perBankRdBursts::10                249                       # Per bank write bursts
 system.physmem.perBankRdBursts::11                253                       # Per bank write bursts
-system.physmem.perBankRdBursts::12                398                       # Per bank write bursts
+system.physmem.perBankRdBursts::12                396                       # Per bank write bursts
 system.physmem.perBankRdBursts::13                338                       # Per bank write bursts
-system.physmem.perBankRdBursts::14                491                       # Per bank write bursts
+system.physmem.perBankRdBursts::14                493                       # Per bank write bursts
 system.physmem.perBankRdBursts::15                448                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
 system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
@@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                     23058233500                       # Total gap between requests
+system.physmem.totGap                     22159321500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
@@ -90,12 +90,12 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                      3262                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      1223                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       633                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                       105                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                         8                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                      3250                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      1221                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       631                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                       112                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                        15                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                         3                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
@@ -186,92 +186,92 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples          871                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      381.722158                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     229.044875                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     356.837953                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127            257     29.51%     29.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255          194     22.27%     51.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383           84      9.64%     61.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511           65      7.46%     68.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639           35      4.02%     72.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767           36      4.13%     77.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895           31      3.56%     80.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023           43      4.94%     85.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151          126     14.47%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total            871                       # Bytes accessed per row activation
-system.physmem.totQLat                       38517250                       # Total ticks spent queuing
-system.physmem.totMemAccLat                 136617250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.bytesPerActivate::samples          866                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      383.630485                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     228.084782                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     358.284844                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127            269     31.06%     31.06% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255          171     19.75%     50.81% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383           88     10.16%     60.97% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511           63      7.27%     68.24% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639           38      4.39%     72.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767           33      3.81%     76.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895           35      4.04%     80.48% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023           46      5.31%     85.80% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151          123     14.20%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total            866                       # Bytes accessed per row activation
+system.physmem.totQLat                       40678250                       # Total ticks spent queuing
+system.physmem.totMemAccLat                 138778250                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                     26160000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        7361.86                       # Average queueing delay per DRAM burst
+system.physmem.avgQLat                        7774.89                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  26111.86                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          14.52                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  26524.89                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          15.11                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       14.52                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       15.11                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           0.11                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       0.11                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                           0.12                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       0.12                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.03                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                       4353                       # Number of row buffer hits during reads
+system.physmem.readRowHits                       4354                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   83.20                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   83.22                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                      4407154.72                       # Average gap between requests
-system.physmem.pageHitRate                      83.20                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE      21416461750                       # Time in different power states
-system.physmem.memoryStateTime::REF         769860000                       # Time in different power states
+system.physmem.avgGap                      4235344.32                       # Average gap between requests
+system.physmem.pageHitRate                      83.22                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE      20544029500                       # Time in different power states
+system.physmem.memoryStateTime::REF         739700000                       # Time in different power states
 system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT         869038750                       # Time in different power states
+system.physmem.memoryStateTime::ACT         868593500                       # Time in different power states
 system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.membus.throughput                     14521761                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq                3525                       # Transaction distribution
-system.membus.trans_dist::ReadResp               3525                       # Transaction distribution
-system.membus.trans_dist::ReadExReq              1707                       # Transaction distribution
-system.membus.trans_dist::ReadExResp             1707                       # Transaction distribution
+system.membus.throughput                     15110871                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq                3523                       # Transaction distribution
+system.membus.trans_dist::ReadResp               3523                       # Transaction distribution
+system.membus.trans_dist::ReadExReq              1709                       # Transaction distribution
+system.membus.trans_dist::ReadExResp             1709                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        10464                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count::total                  10464                       # Packet count per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       334848                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size::total              334848                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.data_through_bus                 334848                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy             6496500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy             6531000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           48985000                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy           48922250                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.branchPred.lookups                15361032                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          11166301                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            940671                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups              8650721                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                 7195754                       # Number of BTB hits
+system.cpu.branchPred.lookups                16298030                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          11843884                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            974423                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups              8872850                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                 7618799                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             83.180974                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 1505004                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect               3205                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             85.866424                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 1608574                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect                439                       # Number of incorrect RAS predictions.
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                     23573955                       # DTB read hits
-system.cpu.dtb.read_misses                     207074                       # DTB read misses
-system.cpu.dtb.read_acv                             4                       # DTB read access violations
-system.cpu.dtb.read_accesses                 23781029                       # DTB read accesses
-system.cpu.dtb.write_hits                     7120317                       # DTB write hits
-system.cpu.dtb.write_misses                      1134                       # DTB write misses
-system.cpu.dtb.write_acv                            4                       # DTB write access violations
-system.cpu.dtb.write_accesses                 7121451                       # DTB write accesses
-system.cpu.dtb.data_hits                     30694272                       # DTB hits
-system.cpu.dtb.data_misses                     208208                       # DTB misses
-system.cpu.dtb.data_acv                             8                       # DTB access violations
-system.cpu.dtb.data_accesses                 30902480                       # DTB accesses
-system.cpu.itb.fetch_hits                    15234213                       # ITB hits
-system.cpu.itb.fetch_misses                       102                       # ITB misses
+system.cpu.dtb.read_hits                     24142171                       # DTB read hits
+system.cpu.dtb.read_misses                     235539                       # DTB read misses
+system.cpu.dtb.read_acv                             2                       # DTB read access violations
+system.cpu.dtb.read_accesses                 24377710                       # DTB read accesses
+system.cpu.dtb.write_hits                     7161357                       # DTB write hits
+system.cpu.dtb.write_misses                      1208                       # DTB write misses
+system.cpu.dtb.write_acv                            1                       # DTB write access violations
+system.cpu.dtb.write_accesses                 7162565                       # DTB write accesses
+system.cpu.dtb.data_hits                     31303528                       # DTB hits
+system.cpu.dtb.data_misses                     236747                       # DTB misses
+system.cpu.dtb.data_acv                             3                       # DTB access violations
+system.cpu.dtb.data_accesses                 31540275                       # DTB accesses
+system.cpu.itb.fetch_hits                    16127186                       # ITB hits
+system.cpu.itb.fetch_misses                        86                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                15234315                       # ITB accesses
+system.cpu.itb.fetch_accesses                16127272                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -285,239 +285,238 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                  389                       # Number of system calls
-system.cpu.numCycles                         46116722                       # number of cpu cycles simulated
+system.cpu.numCycles                         44318823                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           15940932                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      131589057                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    15361032                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches            8700758                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      22892353                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 5007718                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles                2994752                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                   90                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles          2134                       # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles            8                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                  15234213                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                364576                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples           45860852                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.869311                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.407633                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles           16859425                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      139373095                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    16298030                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches            9227373                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      26218432                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 2029202                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles                  113                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles          2359                       # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles           29                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                  16127186                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                380559                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples           44094959                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              3.160749                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.432020                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 22968499     50.08%     50.08% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  2435887      5.31%     55.39% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  1214898      2.65%     58.04% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  1783514      3.89%     61.93% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  2844070      6.20%     68.13% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  1193047      2.60%     70.74% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  1264346      2.76%     73.49% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                   807487      1.76%     75.25% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                 11349104     24.75%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 19653194     44.57%     44.57% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  2660337      6.03%     50.60% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  1339868      3.04%     53.64% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  1948475      4.42%     58.06% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  3047157      6.91%     64.97% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  1303414      2.96%     67.93% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  1381873      3.13%     71.06% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                   894467      2.03%     73.09% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 11866174     26.91%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total             45860852                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.333090                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        2.853391                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 16942268                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles               2554020                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  21969696                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles                376134                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                4018734                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved              2597948                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                 12434                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              128314772                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                 36360                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                4018734                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 17696753                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                  830389                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles           7936                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  21575239                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles               1731801                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              125347310                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                  9609                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                 982853                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                 675750                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                  22720                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands            92019426                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             162776933                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        155390791                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups           7386141                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total             44094959                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.367745                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        3.144783                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 13063421                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles               8246941                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  19674377                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               2107337                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                1002883                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              2678530                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                 12053                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              133445502                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                 49010                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                1002883                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 14206611                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                 4728529                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles           8933                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  20521133                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles               3626870                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              129917938                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                 71936                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                1987853                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                1348485                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents                  46116                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands            95420653                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             168813407                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        161260201                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups           7553205                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps              68427361                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 23592065                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts                733                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts            723                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                   3333773                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             26203423                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores             8541215                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           2901793                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          1268500                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  108868755                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                1841                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                  97966771                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            305092                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        24205687                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     18927840                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved           1452                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples      45860852                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         2.136174                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.932064                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                 26993292                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts                764                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts            773                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                   8204907                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             27105677                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores             8747640                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           3541499                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          1618929                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  112639456                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                1940                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 100102495                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            120259                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        27967887                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     21886195                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved           1551                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples      44094959                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         2.270157                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        2.096378                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            12004778     26.18%     26.18% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1             8735781     19.05%     45.22% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2             7795942     17.00%     62.22% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3             6187579     13.49%     75.72% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4             4939987     10.77%     86.49% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             3238381      7.06%     93.55% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             1831298      3.99%     97.54% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7              880120      1.92%     99.46% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              246986      0.54%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            11535003     26.16%     26.16% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1             7754472     17.59%     43.75% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2             7555417     17.13%     60.88% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3             5737107     13.01%     73.89% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             4489381     10.18%     84.07% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             2977390      6.75%     90.82% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             2013843      4.57%     95.39% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             1160432      2.63%     98.02% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              871914      1.98%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total        45860852                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total        44094959                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                  202355     11.05%     11.05% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%     11.05% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     11.05% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                   107      0.01%     11.05% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     11.05% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                  8618      0.47%     11.52% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                 9498      0.52%     12.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                955023     52.14%     64.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     64.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     64.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     64.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     64.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     64.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     64.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     64.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     64.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     64.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     64.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     64.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     64.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     64.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     64.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     64.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     64.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     64.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     64.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     64.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     64.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     64.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                 532552     29.07%     93.25% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                123630      6.75%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  479018     20.14%     20.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%     20.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     20.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                   443      0.02%     20.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     20.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                 33638      1.41%     21.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                11723      0.49%     22.07% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv               1006429     42.32%     64.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     64.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     64.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     64.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     64.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     64.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     64.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     64.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     64.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     64.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     64.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     64.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     64.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     64.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     64.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     64.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     64.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     64.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     64.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     64.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     64.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     64.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                 686405     28.86%     93.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                160330      6.74%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 7      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu              59518834     60.75%     60.75% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult               484423      0.49%     61.25% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     61.25% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd             2816502      2.87%     64.12% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp              115449      0.12%     64.24% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt             2407923      2.46%     66.70% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult             312382      0.32%     67.02% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv              763359      0.78%     67.80% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                319      0.00%     67.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     67.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     67.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     67.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     67.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     67.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     67.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     67.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     67.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     67.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     67.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     67.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     67.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     67.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     67.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     67.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     67.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     67.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.80% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             24335343     24.84%     92.64% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite             7212230      7.36%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu              60895265     60.83%     60.83% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult               491428      0.49%     61.32% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     61.32% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd             2836761      2.83%     64.16% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp              115534      0.12%     64.27% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt             2437739      2.44%     66.71% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult             313998      0.31%     67.02% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv              765483      0.76%     67.79% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                319      0.00%     67.79% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     67.79% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     67.79% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     67.79% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     67.79% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     67.79% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     67.79% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     67.79% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     67.79% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     67.79% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     67.79% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     67.79% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     67.79% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     67.79% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     67.79% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     67.79% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     67.79% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     67.79% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.79% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.79% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.79% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             24980976     24.96%     92.74% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite             7264985      7.26%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total               97966771                       # Type of FU issued
-system.cpu.iq.rate                           2.124322                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     1831783                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.018698                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          228533724                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         123769088                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses     88239146                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads            15397545                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes            9344200                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses      7119957                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses               91612691                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                 8185856                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads          1667830                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              100102495                       # Type of FU issued
+system.cpu.iq.rate                           2.258690                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     2377986                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.023756                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          231175572                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         131029945                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses     90008845                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads            15622622                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes            9621224                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses      7166740                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses               94135365                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                 8345109                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads          1908745                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      6207225                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        16318                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        37199                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      2040112                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      7109479                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        10719                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        42241                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      2246537                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads        40236                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked          2728                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads        42761                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked          2468                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                4018734                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                   14986                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                580703                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           119442937                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            327587                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              26203423                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts              8541215                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts               1841                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                  22416                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                558101                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          37199                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         549687                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       504581                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              1054268                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts              96742235                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              23781507                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           1224536                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                1002883                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 3707628                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                461880                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           123638491                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            278104                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts              27105677                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts              8747640                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts               1940                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                  39979                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                414958                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          42241                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         554445                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       525545                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              1079990                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts              98729732                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              24378234                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           1372763                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                      10572341                       # number of nop insts executed
-system.cpu.iew.exec_refs                     30903185                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 12219901                       # Number of branches executed
-system.cpu.iew.exec_stores                    7121678                       # Number of stores executed
-system.cpu.iew.exec_rate                     2.097769                       # Inst execution rate
-system.cpu.iew.wb_sent                       95961828                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                      95359103                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                  65705546                       # num instructions producing a value
-system.cpu.iew.wb_consumers                  92226364                       # num instructions consuming a value
+system.cpu.iew.exec_nop                      10997095                       # number of nop insts executed
+system.cpu.iew.exec_refs                     31540837                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 12532490                       # Number of branches executed
+system.cpu.iew.exec_stores                    7162603                       # Number of stores executed
+system.cpu.iew.exec_rate                     2.227716                       # Inst execution rate
+system.cpu.iew.wb_sent                       97918366                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                      97175585                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                  67088116                       # num instructions producing a value
+system.cpu.iew.wb_consumers                  95122373                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       2.067777                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.712438                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       2.192648                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.705282                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts        27540320                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts        31736961                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls             389                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            928822                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples     41842118                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     2.196425                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.812600                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts            962705                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples     39466883                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     2.328612                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.908948                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     16239554     38.81%     38.81% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1      9401519     22.47%     61.28% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2      4137637      9.89%     71.17% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      2136234      5.11%     76.27% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      1534088      3.67%     79.94% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      1088589      2.60%     82.54% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6       699410      1.67%     84.21% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7       798893      1.91%     86.12% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      5806194     13.88%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     14969501     37.93%     37.93% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1      8597580     21.78%     59.71% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      3898486      9.88%     69.59% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      1956471      4.96%     74.55% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      1378247      3.49%     78.04% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      1028776      2.61%     80.65% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6       694004      1.76%     82.41% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       732346      1.86%     84.26% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      6211472     15.74%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total     41842118                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total     39466883                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts             91903055                       # Number of instructions committed
 system.cpu.commit.committedOps               91903055                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -529,10 +528,10 @@ system.cpu.commit.fp_insts                    6862061                       # Nu
 system.cpu.commit.int_insts                  79581076                       # Number of committed integer instructions.
 system.cpu.commit.function_calls              1029620                       # Number of function calls committed.
 system.cpu.commit.op_class_0::No_OpClass      7723353      8.40%      8.40% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu         51001542     55.49%     63.90% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu         51001453     55.49%     63.90% # Class of committed instruction
 system.cpu.commit.op_class_0::IntMult          458252      0.50%     64.40% # Class of committed instruction
 system.cpu.commit.op_class_0::IntDiv                0      0.00%     64.40% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatAdd        2732464      2.97%     67.37% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatAdd        2732553      2.97%     67.37% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatCmp         104605      0.11%     67.48% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatCvt        2333953      2.54%     70.02% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatMult        296445      0.32%     70.35% # Class of committed instruction
@@ -563,229 +562,229 @@ system.cpu.commit.op_class_0::MemWrite        6501103      7.07%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total          91903055                       # Class of committed instruction
-system.cpu.commit.bw_lim_events               5806194                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events               6211472                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                    155478259                       # The number of ROB reads
-system.cpu.rob.rob_writes                   242937786                       # The number of ROB writes
-system.cpu.timesIdled                            5286                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                          255870                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads                    156894387                       # The number of ROB reads
+system.cpu.rob.rob_writes                   251967276                       # The number of ROB writes
+system.cpu.timesIdled                            4538                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                          223864                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                    84179709                       # Number of Instructions Simulated
 system.cpu.committedOps                      84179709                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               0.547837                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.547837                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.825362                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.825362                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                130779466                       # number of integer regfile reads
-system.cpu.int_regfile_writes                71543363                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                   6233836                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                  6101151                       # number of floating regfile writes
-system.cpu.misc_regfile_reads                  718857                       # number of misc regfile reads
+system.cpu.cpi                               0.526479                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.526479                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.899412                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.899412                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                133358099                       # number of integer regfile reads
+system.cpu.int_regfile_writes                73122879                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                   6250590                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                  6153622                       # number of floating regfile writes
+system.cpu.misc_regfile_reads                  718773                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
-system.cpu.toL2Bus.throughput                37986395                       # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq          11847                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp         11847                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback          107                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq         1732                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp         1732                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        22674                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         4591                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total             27265                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       725568                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       150336                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total         875904                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus            875904                       # Total data (bytes)
+system.cpu.toL2Bus.throughput                40079044                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq          12032                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp         12032                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback          110                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq         1735                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp         1735                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        23038                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         4606                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total             27644                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       737216                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       150912                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total         888128                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus            888128                       # Total data (bytes)
 system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy        6950000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.occupancy        7048500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy      17583000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy      17856750                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy       3542750                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy       3547750                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu.icache.tags.replacements              9401                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1598.407560                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            15220036                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs             11337                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs           1342.510011                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements              9583                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1600.631079                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            16112652                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs             11519                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs           1398.789131                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1598.407560                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.780472                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.780472                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst  1600.631079                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.781558                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.781558                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         1936                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           62                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          179                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          757                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3            7                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4          931                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           57                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          178                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          763                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3            8                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4          930                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.945312                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          30479761                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         30479761                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     15220036                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        15220036                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      15220036                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         15220036                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     15220036                       # number of overall hits
-system.cpu.icache.overall_hits::total        15220036                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst        14176                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total         14176                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst        14176                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total          14176                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst        14176                       # number of overall misses
-system.cpu.icache.overall_misses::total         14176                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    411369250                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    411369250                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    411369250                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    411369250                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    411369250                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    411369250                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     15234212                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     15234212                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     15234212                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     15234212                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     15234212                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     15234212                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000931                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000931                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000931                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000931                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000931                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000931                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 29018.711202                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 29018.711202                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 29018.711202                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 29018.711202                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 29018.711202                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 29018.711202                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs          201                       # number of cycles access was blocked
+system.cpu.icache.tags.tag_accesses          32265889                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         32265889                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     16112652                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        16112652                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      16112652                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         16112652                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     16112652                       # number of overall hits
+system.cpu.icache.overall_hits::total        16112652                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst        14533                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total         14533                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst        14533                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total          14533                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst        14533                       # number of overall misses
+system.cpu.icache.overall_misses::total         14533                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    419582750                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    419582750                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    419582750                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    419582750                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    419582750                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    419582750                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     16127185                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     16127185                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     16127185                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     16127185                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     16127185                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     16127185                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000901                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000901                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000901                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000901                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000901                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000901                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28871.034886                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 28871.034886                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 28871.034886                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 28871.034886                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 28871.034886                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 28871.034886                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs          196                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 5                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    40.200000                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    39.200000                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst         2839                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total         2839                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst         2839                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total         2839                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst         2839                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total         2839                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst        11337                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total        11337                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst        11337                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total        11337                       # number of demand (read+write) MSHR misses
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-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26696.877481                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26696.877481                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 26696.877481                       # average overall mshr miss latency
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+system.cpu.icache.overall_avg_mshr_miss_latency::total 26612.835316                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse         2409.556828                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs               8337                       # Total number of references to valid blocks.
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 system.cpu.l2cache.tags.sampled_refs             3591                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             2.321637                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             2.373712                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks    17.688406                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  2013.956930                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   377.911492                       # Average occupied blocks per requestor
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 system.cpu.l2cache.tags.occ_percent::writebacks     0.000540                       # Average percentage of cache occupancy
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 system.cpu.l2cache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
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 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.109589                       # Percentage of cache occupancy per task id
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-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73213.476653                       # average overall miss latency
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+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76675.764192                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 69714.447914                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72339.233470                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72339.233470                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68674.225122                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73255.768343                       # average overall miss latency
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+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68674.225122                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73255.768343                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 70571.817661                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -794,186 +793,186 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3069                       # number of ReadReq MSHR misses
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-system.cpu.l2cache.ReadExReq_mshr_misses::total         1707                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         3069                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data         2163                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3065                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          458                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total         3523                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         1709                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total         1709                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         3065                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data         2167                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::total         5232                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         3069                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data         2163                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         3065                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data         2167                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total         5232                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    169758750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     29825000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total    199583750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    101974750                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    101974750                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    169758750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    131799750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    301558500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    169758750                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    131799750                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    301558500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.270707                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.894118                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.297544                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.985566                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.985566                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.270707                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.964764                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.385301                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.270707                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.964764                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.385301                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55314.027370                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65405.701754                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56619.503546                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59739.162273                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59739.162273                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55314.027370                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60933.772538                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57637.327982                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55314.027370                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60933.772538                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57637.327982                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    171659000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     29432500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total    201091500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    102767750                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    102767750                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    171659000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    132200250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    303859250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    171659000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    132200250                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    303859250                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.266082                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.892788                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.292803                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.985014                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.985014                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.266082                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.963968                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.380039                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.266082                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.963968                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.380039                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56006.199021                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64263.100437                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57079.619642                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60133.265067                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60133.265067                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56006.199021                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61006.114444                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58077.073777                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56006.199021                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61006.114444                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58077.073777                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements               157                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          1456.621503                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            28355724                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs              2242                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs          12647.512935                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.replacements               160                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          1457.564736                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            28680752                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs              2248                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs          12758.341637                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  1456.621503                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.355620                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.355620                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024         2085                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           23                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          129                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2          545                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_blocks::cpu.data  1457.564736                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.355851                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.355851                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         2088                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           27                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          131                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          542                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::4         1388                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024     0.509033                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          56732342                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         56732342                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     21862715                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        21862715                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      6492763                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        6492763                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data          246                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total          246                       # number of LoadLockedReq hits
-system.cpu.dcache.demand_hits::cpu.data      28355478                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         28355478                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     28355478                       # number of overall hits
-system.cpu.dcache.overall_hits::total        28355478                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data          985                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total           985                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data         8340                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total         8340                       # number of WriteReq misses
+system.cpu.dcache.tags.occ_task_id_percent::1024     0.509766                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses          57382574                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         57382574                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     22187756                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        22187756                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      6492734                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        6492734                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data          262                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total          262                       # number of LoadLockedReq hits
+system.cpu.dcache.demand_hits::cpu.data      28680490                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         28680490                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     28680490                       # number of overall hits
+system.cpu.dcache.overall_hits::total        28680490                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data         1041                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total          1041                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data         8369                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total         8369                       # number of WriteReq misses
 system.cpu.dcache.LoadLockedReq_misses::cpu.data            1                       # number of LoadLockedReq misses
 system.cpu.dcache.LoadLockedReq_misses::total            1                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data         9325                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total           9325                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data         9325                       # number of overall misses
-system.cpu.dcache.overall_misses::total          9325                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data     61174750                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     61174750                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data    507348010                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total    507348010                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_misses::cpu.data         9410                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total           9410                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data         9410                       # number of overall misses
+system.cpu.dcache.overall_misses::total          9410                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data     65428750                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     65428750                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data    523784968                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total    523784968                       # number of WriteReq miss cycles
 system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data        92750                       # number of LoadLockedReq miss cycles
 system.cpu.dcache.LoadLockedReq_miss_latency::total        92750                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data    568522760                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total    568522760                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data    568522760                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total    568522760                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     21863700                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     21863700                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_miss_latency::cpu.data    589213718                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total    589213718                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data    589213718                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total    589213718                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     22188797                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     22188797                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data      6501103                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total      6501103                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data          247                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total          247                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     28364803                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     28364803                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     28364803                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     28364803                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000045                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.000045                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.001283                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.001283                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.004049                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.004049                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.000329                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.000329                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.000329                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.000329                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62106.345178                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 62106.345178                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60833.094724                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 60833.094724                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data          263                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total          263                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     28689900                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     28689900                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     28689900                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     28689900                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000047                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.000047                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.001287                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.001287                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.003802                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.003802                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.000328                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.000328                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.000328                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.000328                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62851.825168                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 62851.825168                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62586.326682                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 62586.326682                       # average WriteReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        92750                       # average LoadLockedReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        92750                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 60967.588204                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 60967.588204                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 60967.588204                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 60967.588204                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs        27950                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs               875                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    31.942857                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 62615.697981                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 62615.697981                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 62615.697981                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 62615.697981                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs        29209                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets          416                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs               894                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               2                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    32.672260                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          208                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks          107                       # number of writebacks
-system.cpu.dcache.writebacks::total               107                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data          476                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total          476                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data         6608                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total         6608                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data         7084                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total         7084                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data         7084                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total         7084                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data          509                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total          509                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data         1732                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total         1732                       # number of WriteReq MSHR misses
+system.cpu.dcache.writebacks::writebacks          110                       # number of writebacks
+system.cpu.dcache.writebacks::total               110                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data          528                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total          528                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data         6635                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total         6635                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data         7163                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total         7163                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data         7163                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total         7163                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data          513                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total          513                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data         1734                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total         1734                       # number of WriteReq MSHR misses
 system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data            1                       # number of LoadLockedReq MSHR misses
 system.cpu.dcache.LoadLockedReq_mshr_misses::total            1                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data         2241                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total         2241                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data         2241                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total         2241                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     36463750                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total     36463750                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    124994997                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total    124994997                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_misses::cpu.data         2247                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total         2247                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data         2247                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total         2247                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     36170500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     36170500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    125701245                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total    125701245                       # number of WriteReq MSHR miss cycles
 system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data        90250                       # number of LoadLockedReq MSHR miss cycles
 system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total        90250                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data    161458747                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total    161458747                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data    161458747                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total    161458747                       # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data    161871745                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total    161871745                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data    161871745                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total    161871745                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000023                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000023                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000266                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000266                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.004049                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.004049                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000079                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.000079                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000079                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.000079                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 71638.015717                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 71638.015717                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72168.012125                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72168.012125                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000267                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000267                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.003802                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.003802                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000078                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.000078                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000078                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.000078                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 70507.797271                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70507.797271                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72492.067474                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72492.067474                       # average WriteReq mshr miss latency
 system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data        90250                       # average LoadLockedReq mshr miss latency
 system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total        90250                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72047.633646                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 72047.633646                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72047.633646                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 72047.633646                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72039.049844                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 72039.049844                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72039.049844                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 72039.049844                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt
index 5bf6c1d3d..e6477bb91 100644
--- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.045952                       # Nu
 sim_ticks                                 45951567500                       # Number of ticks simulated
 final_tick                                45951567500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                2663178                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2663177                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1331588953                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 260384                       # Number of bytes of host memory used
-host_seconds                                    34.51                       # Real time elapsed on the host
+host_inst_rate                                3319618                       # Simulator instruction rate (inst/s)
+host_op_rate                                  3319616                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1659808736                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 259284                       # Number of bytes of host memory used
+host_seconds                                    27.68                       # Real time elapsed on the host
 sim_insts                                    91903056                       # Number of instructions simulated
 sim_ops                                      91903056                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -96,10 +96,10 @@ system.cpu.not_idle_fraction                        1                       # Pe
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                          10240685                       # Number of branches fetched
 system.cpu.op_class::No_OpClass               7723353      8.40%      8.40% # Class of executed instruction
-system.cpu.op_class::IntAlu                  51001543     55.49%     63.90% # Class of executed instruction
+system.cpu.op_class::IntAlu                  51001454     55.49%     63.90% # Class of executed instruction
 system.cpu.op_class::IntMult                   458252      0.50%     64.40% # Class of executed instruction
 system.cpu.op_class::IntDiv                         0      0.00%     64.40% # Class of executed instruction
-system.cpu.op_class::FloatAdd                 2732464      2.97%     67.37% # Class of executed instruction
+system.cpu.op_class::FloatAdd                 2732553      2.97%     67.37% # Class of executed instruction
 system.cpu.op_class::FloatCmp                  104605      0.11%     67.48% # Class of executed instruction
 system.cpu.op_class::FloatCvt                 2333953      2.54%     70.02% # Class of executed instruction
 system.cpu.op_class::FloatMult                 296445      0.32%     70.35% # Class of executed instruction
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt
index 88e7e1e1c..640d2653d 100644
--- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.118729                       # Nu
 sim_ticks                                118729316000                       # Number of ticks simulated
 final_tick                               118729316000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1199929                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1199929                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1550185026                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 269088                       # Number of bytes of host memory used
-host_seconds                                    76.59                       # Real time elapsed on the host
+host_inst_rate                                1742639                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1742639                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2251309988                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 268020                       # Number of bytes of host memory used
+host_seconds                                    52.74                       # Real time elapsed on the host
 sim_insts                                    91903056                       # Number of instructions simulated
 sim_ops                                      91903056                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -102,10 +102,10 @@ system.cpu.not_idle_fraction                        1                       # Pe
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                          10240685                       # Number of branches fetched
 system.cpu.op_class::No_OpClass               7723353      8.40%      8.40% # Class of executed instruction
-system.cpu.op_class::IntAlu                  51001543     55.49%     63.90% # Class of executed instruction
+system.cpu.op_class::IntAlu                  51001454     55.49%     63.90% # Class of executed instruction
 system.cpu.op_class::IntMult                   458252      0.50%     64.40% # Class of executed instruction
 system.cpu.op_class::IntDiv                         0      0.00%     64.40% # Class of executed instruction
-system.cpu.op_class::FloatAdd                 2732464      2.97%     67.37% # Class of executed instruction
+system.cpu.op_class::FloatAdd                 2732553      2.97%     67.37% # Class of executed instruction
 system.cpu.op_class::FloatCmp                  104605      0.11%     67.48% # Class of executed instruction
 system.cpu.op_class::FloatCvt                 2333953      2.54%     70.02% # Class of executed instruction
 system.cpu.op_class::FloatMult                 296445      0.32%     70.35% # Class of executed instruction
diff --git a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt
index 6b1426f89..414b5b5a9 100644
--- a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt
@@ -1,560 +1,58 @@
 
 ---------- Begin Simulation Statistics ----------
-final_tick                               133576129500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-host_inst_rate                                 174502                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 298144                       # Number of bytes of host memory used
-host_op_rate                                   191062                       # Simulator op (including micro ops) rate (op/s)
-host_seconds                                   987.48                       # Real time elapsed on the host
-host_tick_rate                              135269038                       # Simulator tick rate (ticks/s)
+sim_seconds                                  0.131652                       # Number of seconds simulated
+sim_ticks                                131652469500                       # Number of ticks simulated
+final_tick                               131652469500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                 235317                       # Simulator instruction rate (inst/s)
+host_op_rate                                   248063                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              179784828                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 321352                       # Number of bytes of host memory used
+host_seconds                                   732.28                       # Real time elapsed on the host
 sim_insts                                   172317809                       # Number of instructions simulated
-sim_ops                                     188671292                       # Number of ops (including micro ops) simulated
-sim_seconds                                  0.133576                       # Number of seconds simulated
-sim_ticks                                133576129500                       # Number of ticks simulated
+sim_ops                                     181650742                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             95.468318                       # BTB Hit Percentage
-system.cpu.branchPred.BTBHits                23338838                       # Number of BTB hits
-system.cpu.branchPred.BTBLookups             24446684                       # Number of BTB lookups
-system.cpu.branchPred.RASInCorrect               1344                       # Number of incorrect RAS predictions.
-system.cpu.branchPred.condIncorrect           5759272                       # Number of conditional branches incorrect
-system.cpu.branchPred.condPredicted          40186958                       # Number of conditional branches predicted
-system.cpu.branchPred.lookups                50197812                       # Number of BP lookups
-system.cpu.branchPred.usedRAS                 1870133                       # Number of times the RAS was used to get a target.
-system.cpu.committedInsts                   172317809                       # Number of instructions committed
-system.cpu.committedOps                     188671292                       # Number of ops (including micro ops) committed
-system.cpu.cpi                               1.550346                       # CPI: cycles per instruction
-system.cpu.dcache.LoadLockedReq_accesses::cpu.inst        22407                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total        22407                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_hits::cpu.inst        22407                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total        22407                       # number of LoadLockedReq hits
-system.cpu.dcache.ReadReq_accesses::cpu.inst     30104490                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     30104490                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 68315.588308                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 68315.588308                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 66514.624478                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66514.624478                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits::cpu.inst     30103686                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        30103686                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency::cpu.inst     54925733                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     54925733                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate::cpu.inst     0.000027                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.000027                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses::cpu.inst          804                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total           804                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits::cpu.inst           85                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total           85                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst     47824015                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total     47824015                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst     0.000024                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000024                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses::cpu.inst          719                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total          719                       # number of ReadReq MSHR misses
-system.cpu.dcache.StoreCondReq_accesses::cpu.inst        22407                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total        22407                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_hits::cpu.inst        22407                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total        22407                       # number of StoreCondReq hits
-system.cpu.dcache.WriteReq_accesses::cpu.inst     12364287                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total     12364287                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 70061.205847                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 70061.205847                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 70028.942571                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70028.942571                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits::cpu.inst     12362645                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       12362645                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency::cpu.inst    115040500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total    115040500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate::cpu.inst     0.000133                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.000133                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses::cpu.inst         1642                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total         1642                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits::cpu.inst          545                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total          545                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst     76821750                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total     76821750                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst     0.000089                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000089                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.inst         1097                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total         1097                       # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.demand_accesses::cpu.inst     42468777                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     42468777                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency::cpu.inst 69487.421504                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 69487.421504                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 68637.535793                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 68637.535793                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits::cpu.inst      42466331                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         42466331                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency::cpu.inst    169966233                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total    169966233                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate::cpu.inst     0.000058                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.000058                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses::cpu.inst         2446                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total           2446                       # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits::cpu.inst          630                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total          630                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency::cpu.inst    124645765                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total    124645765                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate::cpu.inst     0.000043                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.000043                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses::cpu.inst         1816                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total         1816                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses::cpu.inst     42468777                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     42468777                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency::cpu.inst 69487.421504                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 69487.421504                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 68637.535793                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 68637.535793                       # average overall mshr miss latency
-system.cpu.dcache.overall_hits::cpu.inst     42466331                       # number of overall hits
-system.cpu.dcache.overall_hits::total        42466331                       # number of overall hits
-system.cpu.dcache.overall_miss_latency::cpu.inst    169966233                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total    169966233                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate::cpu.inst     0.000058                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.000058                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses::cpu.inst         2446                       # number of overall misses
-system.cpu.dcache.overall_misses::total          2446                       # number of overall misses
-system.cpu.dcache.overall_mshr_hits::cpu.inst          630                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total          630                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency::cpu.inst    124645765                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total    124645765                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate::cpu.inst     0.000043                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.000043                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses::cpu.inst         1816                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total         1816                       # number of overall MSHR misses
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           18                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1           34                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2           88                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3          272                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::4         1362                       # Occupied blocks per task id
-system.cpu.dcache.tags.avg_refs          23409.220815                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.data_accesses         85028998                       # Number of data accesses
-system.cpu.dcache.tags.occ_blocks::cpu.inst  1381.804492                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.inst     0.337355                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.337355                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024         1774                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024     0.433105                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.replacements                42                       # number of replacements
-system.cpu.dcache.tags.sampled_refs              1816                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.tag_accesses          85028998                       # Number of tag accesses
-system.cpu.dcache.tags.tagsinuse          1381.804492                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            42511145                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks::writebacks           16                       # number of writebacks
-system.cpu.dcache.writebacks::total                16                       # number of writebacks
-system.cpu.discardedOps                      12279677                       # Number of ops (including micro ops) which were discarded before commit
-system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
-system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
-system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
-system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
-system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
-system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
-system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
-system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
-system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
-system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
-system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
-system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
-system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
-system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
-system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
-system.cpu.dtb.accesses                             0                       # DTB accesses
-system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.hits                                 0                       # DTB hits
-system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.inst_hits                            0                       # ITB inst hits
-system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.misses                               0                       # DTB misses
-system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
-system.cpu.dtb.read_accesses                        0                       # DTB read accesses
-system.cpu.dtb.read_hits                            0                       # DTB read hits
-system.cpu.dtb.read_misses                          0                       # DTB read misses
-system.cpu.dtb.write_accesses                       0                       # DTB write accesses
-system.cpu.dtb.write_hits                           0                       # DTB write hits
-system.cpu.dtb.write_misses                         0                       # DTB write misses
-system.cpu.icache.ReadReq_accesses::cpu.inst     71932968                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     71932968                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 39567.186956                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 39567.186956                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37371.415126                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37371.415126                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits::cpu.inst     71928261                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        71928261                       # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    186242749                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    186242749                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000065                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000065                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses::cpu.inst         4707                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total          4707                       # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    175907251                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    175907251                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000065                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000065                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst         4707                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total         4707                       # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.demand_accesses::cpu.inst     71932968                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     71932968                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 39567.186956                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 39567.186956                       # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37371.415126                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 37371.415126                       # average overall mshr miss latency
-system.cpu.icache.demand_hits::cpu.inst      71928261                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         71928261                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency::cpu.inst    186242749                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    186242749                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000065                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000065                       # miss rate for demand accesses
-system.cpu.icache.demand_misses::cpu.inst         4707                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total           4707                       # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    175907251                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    175907251                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000065                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.000065                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses::cpu.inst         4707                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total         4707                       # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses::cpu.inst     71932968                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     71932968                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 39567.186956                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 39567.186956                       # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37371.415126                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 37371.415126                       # average overall mshr miss latency
-system.cpu.icache.overall_hits::cpu.inst     71928261                       # number of overall hits
-system.cpu.icache.overall_hits::total        71928261                       # number of overall hits
-system.cpu.icache.overall_miss_latency::cpu.inst    186242749                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    186242749                       # number of overall miss cycles
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000065                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000065                       # miss rate for overall accesses
-system.cpu.icache.overall_misses::cpu.inst         4707                       # number of overall misses
-system.cpu.icache.overall_misses::total          4707                       # number of overall misses
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    175907251                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    175907251                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000065                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.000065                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses::cpu.inst         4707                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total         4707                       # number of overall MSHR misses
-system.cpu.icache.tags.age_task_id_blocks_1024::0           53                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1           45                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          503                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3          137                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4         1065                       # Occupied blocks per task id
-system.cpu.icache.tags.avg_refs          15284.373353                       # Average number of references to valid blocks.
-system.cpu.icache.tags.data_accesses        143870642                       # Number of data accesses
-system.cpu.icache.tags.occ_blocks::cpu.inst  1433.013825                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.699714                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.699714                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024         1803                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.880371                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.replacements              2903                       # number of replacements
-system.cpu.icache.tags.sampled_refs              4706                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.tag_accesses         143870642                       # Number of tag accesses
-system.cpu.icache.tags.tagsinuse          1433.013825                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            71928261                       # Total number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.idleCycles                         6392324                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.ipc                               0.645017                       # IPC: instructions per cycle
-system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
-system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
-system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
-system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
-system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
-system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
-system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
-system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
-system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
-system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
-system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
-system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
-system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
-system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
-system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
-system.cpu.itb.accesses                             0                       # DTB accesses
-system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
-system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.hits                                 0                       # DTB hits
-system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.itb.inst_hits                            0                       # ITB inst hits
-system.cpu.itb.inst_misses                          0                       # ITB inst misses
-system.cpu.itb.misses                               0                       # DTB misses
-system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
-system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
-system.cpu.itb.read_accesses                        0                       # DTB read accesses
-system.cpu.itb.read_hits                            0                       # DTB read hits
-system.cpu.itb.read_misses                          0                       # DTB read misses
-system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.write_hits                           0                       # DTB write hits
-system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.l2cache.ReadExReq_accesses::cpu.inst         1097                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total         1097                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69461.202938                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69461.202938                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 56942.378329                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56942.378329                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_hits::cpu.inst            8                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total            8                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst     75643250                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total     75643250                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst     0.992707                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.992707                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses::cpu.inst         1089                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total         1089                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst     62010250                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     62010250                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst     0.992707                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.992707                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst         1089                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total         1089                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses::cpu.inst         5426                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total         5426                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68229.765708                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 68229.765708                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55711.085327                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55711.085327                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits::cpu.inst         2609                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total           2609                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    192203250                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total    192203250                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.519167                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.519167                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses::cpu.inst         2817                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total         2817                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst           16                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total           16                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    156046750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total    156046750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.516218                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.516218                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         2801                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total         2801                       # number of ReadReq MSHR misses
-system.cpu.l2cache.Writeback_accesses::writebacks           16                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total           16                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits::writebacks           16                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total           16                       # number of Writeback hits
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.demand_accesses::cpu.inst         6523                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total         6523                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68573.092678                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 68573.092678                       # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56055.784062                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56055.784062                       # average overall mshr miss latency
-system.cpu.l2cache.demand_hits::cpu.inst         2617                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total            2617                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency::cpu.inst    267846500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total    267846500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.598804                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.598804                       # miss rate for demand accesses
-system.cpu.l2cache.demand_misses::cpu.inst         3906                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total          3906                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_mshr_hits::cpu.inst           16                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total           16                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    218057000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    218057000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.596351                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.596351                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         3890                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total         3890                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses::cpu.inst         6523                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total         6523                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68573.092678                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 68573.092678                       # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56055.784062                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56055.784062                       # average overall mshr miss latency
-system.cpu.l2cache.overall_hits::cpu.inst         2617                       # number of overall hits
-system.cpu.l2cache.overall_hits::total           2617                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency::cpu.inst    267846500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total    267846500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.598804                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.598804                       # miss rate for overall accesses
-system.cpu.l2cache.overall_misses::cpu.inst         3906                       # number of overall misses
-system.cpu.l2cache.overall_misses::total         3906                       # number of overall misses
-system.cpu.l2cache.overall_mshr_hits::cpu.inst           16                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total           16                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    218057000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    218057000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.596351                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.596351                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         3890                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total         3890                       # number of overall MSHR misses
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           37                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1           51                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          538                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3          167                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4         2015                       # Occupied blocks per task id
-system.cpu.l2cache.tags.avg_refs             0.929487                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.data_accesses           56217                       # Number of data accesses
-system.cpu.l2cache.tags.occ_blocks::writebacks     3.030772                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  2008.746792                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.000092                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.061302                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.061395                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024         2808                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.085693                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.sampled_refs             2808                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.tag_accesses            56217                       # Number of tag accesses
-system.cpu.l2cache.tags.tagsinuse         2011.777563                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs               2610                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.numCycles                        267152259                       # number of cpu cycles simulated
-system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.tickCycles                       260759935                       # Number of cycles that the CPU actually ticked
-system.cpu.toL2Bus.data_through_bus            418432                       # Total data (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         9413                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         3648                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total             13061                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy        3285500                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy       7520749                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy       3003735                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
-system.cpu.toL2Bus.throughput                 3132536                       # Throughput (bytes/s)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       301184                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       117248                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total         418432                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.trans_dist::ReadReq           5426                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp          5425                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback           16                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq         1097                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp         1097                       # Transaction distribution
-system.cpu.workload.num_syscalls                  400                       # Number of system calls
-system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.membus.data_through_bus                 248896                       # Total data (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port         7778                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                   7778                       # Packet count per connected master and slave (bytes)
-system.membus.reqLayer0.occupancy             4560000                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           36404000                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
-system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.throughput                      1863327                       # Throughput (bytes/s)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       248896                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total              248896                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.trans_dist::ReadReq                2800                       # Transaction distribution
-system.membus.trans_dist::ReadResp               2800                       # Transaction distribution
-system.membus.trans_dist::ReadExReq              1089                       # Transaction distribution
-system.membus.trans_dist::ReadExResp             1089                       # Transaction distribution
-system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgGap                     34347143.61                       # Average gap between requests
-system.physmem.avgMemAccLat                  25898.62                       # Average memory access latency per DRAM burst
-system.physmem.avgQLat                        7148.62                       # Average queueing delay per DRAM burst
-system.physmem.avgRdBW                           1.86                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        1.86                       # Average system read bandwidth in MiByte/s
-system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
-system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.busUtil                           0.01                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.bw_inst_read::cpu.inst         1042102                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            1042102                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst              1863327                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 1863327                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             1863327                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                1863327                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bytesPerActivate::samples          942                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      263.473461                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     171.306387                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     278.627261                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127            286     30.36%     30.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255          373     39.60%     69.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383           81      8.60%     78.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511           48      5.10%     83.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639           26      2.76%     86.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767           28      2.97%     89.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895           20      2.12%     91.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023           18      1.91%     93.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151           62      6.58%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total            942                       # Bytes accessed per row activation
-system.physmem.bytesReadDRAM                   248896                       # Total number of bytes read from DRAM
-system.physmem.bytesReadSys                    248896                       # Total read bytes from the system interface side
+system.physmem.bytes_read::cpu.inst            247616                       # Number of bytes read from this memory
+system.physmem.bytes_read::total               247616                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       138304                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          138304                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst               3869                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                  3869                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst              1880831                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 1880831                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         1050523                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            1050523                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             1880831                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                1880831                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                          3869                       # Number of read requests accepted
+system.physmem.writeReqs                            0                       # Number of write requests accepted
+system.physmem.readBursts                        3869                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                   247616                       # Total number of bytes read from DRAM
 system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
 system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                    247616                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
-system.physmem.bytes_inst_read::cpu.inst       139200                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          139200                       # Number of instructions bytes read from this memory
-system.physmem.bytes_read::cpu.inst            248896                       # Number of bytes read from this memory
-system.physmem.bytes_read::total               248896                       # Number of bytes read from this memory
-system.physmem.memoryStateTime::IDLE     127581858000                       # Time in different power states
-system.physmem.memoryStateTime::REF        4460300000                       # Time in different power states
-system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT        1531687500                       # Time in different power states
-system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
+system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.num_reads::cpu.inst               3889                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                  3889                       # Number of read requests responded to by this memory
-system.physmem.pageHitRate                      75.67                       # Row buffer hit rate, read and write combined
-system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.perBankRdBursts::0                 305                       # Per bank write bursts
 system.physmem.perBankRdBursts::1                 217                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                 139                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                 312                       # Per bank write bursts
-system.physmem.perBankRdBursts::4                 309                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                 135                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                 313                       # Per bank write bursts
+system.physmem.perBankRdBursts::4                 308                       # Per bank write bursts
 system.physmem.perBankRdBursts::5                 306                       # Per bank write bursts
 system.physmem.perBankRdBursts::6                 273                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                 225                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                 222                       # Per bank write bursts
 system.physmem.perBankRdBursts::8                 249                       # Per bank write bursts
 system.physmem.perBankRdBursts::9                 218                       # Per bank write bursts
-system.physmem.perBankRdBursts::10                300                       # Per bank write bursts
-system.physmem.perBankRdBursts::11                202                       # Per bank write bursts
-system.physmem.perBankRdBursts::12                183                       # Per bank write bursts
-system.physmem.perBankRdBursts::13                219                       # Per bank write bursts
-system.physmem.perBankRdBursts::14                228                       # Per bank write bursts
-system.physmem.perBankRdBursts::15                204                       # Per bank write bursts
+system.physmem.perBankRdBursts::10                295                       # Per bank write bursts
+system.physmem.perBankRdBursts::11                201                       # Per bank write bursts
+system.physmem.perBankRdBursts::12                182                       # Per bank write bursts
+system.physmem.perBankRdBursts::13                218                       # Per bank write bursts
+system.physmem.perBankRdBursts::14                224                       # Per bank write bursts
+system.physmem.perBankRdBursts::15                203                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
 system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
 system.physmem.perBankWrBursts::2                   0                       # Per bank write bursts
@@ -571,8 +69,25 @@ system.physmem.perBankWrBursts::12                  0                       # Pe
 system.physmem.perBankWrBursts::13                  0                       # Per bank write bursts
 system.physmem.perBankWrBursts::14                  0                       # Per bank write bursts
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
-system.physmem.rdQLenPdf::0                      3640                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       237                       # What read queue length does an incoming req see
+system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
+system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
+system.physmem.totGap                    131652381500                       # Total gap between requests
+system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
+system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
+system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
+system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
+system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
+system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
+system.physmem.readPktSize::6                    3869                       # Read request sizes (log2)
+system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
+system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
+system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
+system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
+system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
+system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
+system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                      3617                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       240                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::2                        12                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
@@ -603,22 +118,6 @@ system.physmem.rdQLenPdf::28                        0                       # Wh
 system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.readBursts                        3889                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                    3889                       # Read request sizes (log2)
-system.physmem.readReqs                          3889                       # Number of read requests accepted
-system.physmem.readRowHitRate                   75.67                       # Row buffer hit rate for reads
-system.physmem.readRowHits                       2943                       # Number of row buffer hits during reads
-system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.totBusLat                     19445000                       # Total ticks spent in databus transfers
-system.physmem.totGap                    133576041500                       # Total gap between requests
-system.physmem.totMemAccLat                 100719750                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totQLat                       27801000                       # Total ticks spent queuing
 system.physmem.wrQLenPdf::0                         0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::1                         0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::2                         0                       # What write queue length does an incoming req see
@@ -683,17 +182,518 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.writeReqs                            0                       # Number of write requests accepted
-system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
+system.physmem.bytesPerActivate::samples          903                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      272.372093                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     179.073064                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     280.203163                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127            262     29.01%     29.01% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255          352     38.98%     68.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383           86      9.52%     77.52% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511           48      5.32%     82.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639           35      3.88%     86.71% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767           23      2.55%     89.26% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895           17      1.88%     91.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023           16      1.77%     92.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151           64      7.09%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total            903                       # Bytes accessed per row activation
+system.physmem.totQLat                       27589000                       # Total ticks spent queuing
+system.physmem.totMemAccLat                 100132750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                     19345000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        7130.78                       # Average queueing delay per DRAM burst
+system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
+system.physmem.avgMemAccLat                  25880.78                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           1.88                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        1.88                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
+system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
+system.physmem.busUtil                           0.01                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
+system.physmem.readRowHits                       2961                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.physmem.readRowHitRate                   76.53                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
+system.physmem.avgGap                     34027495.86                       # Average gap between requests
+system.physmem.pageHitRate                      76.53                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE     125800689500                       # Time in different power states
+system.physmem.memoryStateTime::REF        4396080000                       # Time in different power states
+system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
+system.physmem.memoryStateTime::ACT        1453432500                       # Time in different power states
+system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
+system.membus.throughput                      1880831                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq                2779                       # Transaction distribution
+system.membus.trans_dist::ReadResp               2779                       # Transaction distribution
+system.membus.trans_dist::ReadExReq              1090                       # Transaction distribution
+system.membus.trans_dist::ReadExResp             1090                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port         7738                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                   7738                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       247616                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total              247616                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus                 247616                       # Total data (bytes)
+system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy             4528000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
+system.membus.respLayer1.occupancy           36223250                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.cpu.branchPred.lookups                49915423                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          39661220                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           5747038                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             24423675                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                23301282                       # Number of BTB hits
+system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.branchPred.BTBHitPct             95.404488                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 1905800                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect                139                       # Number of incorrect RAS predictions.
+system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
+system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
+system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
+system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
+system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
+system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
+system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
+system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
+system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
+system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
+system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
+system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
+system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
+system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
+system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
+system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
+system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.dtb.inst_hits                            0                       # ITB inst hits
+system.cpu.dtb.inst_misses                          0                       # ITB inst misses
+system.cpu.dtb.read_hits                            0                       # DTB read hits
+system.cpu.dtb.read_misses                          0                       # DTB read misses
+system.cpu.dtb.write_hits                           0                       # DTB write hits
+system.cpu.dtb.write_misses                         0                       # DTB write misses
+system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                        0                       # DTB read accesses
+system.cpu.dtb.write_accesses                       0                       # DTB write accesses
+system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.dtb.hits                                 0                       # DTB hits
+system.cpu.dtb.misses                               0                       # DTB misses
+system.cpu.dtb.accesses                             0                       # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
+system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
+system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
+system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
+system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
+system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
+system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
+system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
+system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
+system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
+system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
+system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
+system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
+system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
+system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
+system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
+system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.itb.inst_hits                            0                       # ITB inst hits
+system.cpu.itb.inst_misses                          0                       # ITB inst misses
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
+system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.itb.hits                                 0                       # DTB hits
+system.cpu.itb.misses                               0                       # DTB misses
+system.cpu.itb.accesses                             0                       # DTB accesses
+system.cpu.workload.num_syscalls                  400                       # Number of system calls
+system.cpu.numCycles                        263304939                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.committedInsts                   172317809                       # Number of instructions committed
+system.cpu.committedOps                     181650742                       # Number of ops (including micro ops) committed
+system.cpu.discardedOps                      11787313                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
+system.cpu.cpi                               1.528019                       # CPI: cycles per instruction
+system.cpu.ipc                               0.654442                       # IPC: instructions per cycle
+system.cpu.tickCycles                       255940225                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                         7364714                       # Total number of cycles that the object has spent stopped
+system.cpu.icache.tags.replacements              2881                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1424.983797                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            71509873                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs              4678                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          15286.420051                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst  1424.983797                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.695793                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.695793                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1797                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           52                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           59                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          503                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3          114                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1069                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.877441                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses         143033782                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        143033782                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     71509873                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        71509873                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      71509873                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         71509873                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     71509873                       # number of overall hits
+system.cpu.icache.overall_hits::total        71509873                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         4679                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          4679                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         4679                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           4679                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         4679                       # number of overall misses
+system.cpu.icache.overall_misses::total          4679                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    184764496                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    184764496                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    184764496                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    184764496                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    184764496                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    184764496                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     71514552                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     71514552                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     71514552                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     71514552                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     71514552                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     71514552                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000065                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000065                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000065                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000065                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000065                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000065                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 39488.030776                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 39488.030776                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 39488.030776                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 39488.030776                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 39488.030776                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 39488.030776                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst         4679                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total         4679                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst         4679                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total         4679                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst         4679                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total         4679                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    174487504                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    174487504                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    174487504                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    174487504                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    174487504                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    174487504                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000065                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000065                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000065                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.000065                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000065                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.000065                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37291.622996                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37291.622996                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37291.622996                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 37291.622996                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37291.622996                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 37291.622996                       # average overall mshr miss latency
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.toL2Bus.throughput                 3161293                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq           5390                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp          5389                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback           16                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq         1098                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp         1098                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         9357                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         3634                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total             12991                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       299392                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       116800                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total         416192                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus            416192                       # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy        3268000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy       7477496                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy       2996735                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
+system.cpu.l2cache.tags.replacements                0                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse         2001.642880                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs               2592                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs             2787                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             0.930032                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks     3.028976                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  1998.613905                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.000092                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.060993                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.061085                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024         2787                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           38                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1           67                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          535                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3          142                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4         2005                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.085052                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses            55917                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses           55917                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.inst         2591                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total           2591                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks           16                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total           16                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.inst            8                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total            8                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst         2599                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total            2599                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst         2599                       # number of overall hits
+system.cpu.l2cache.overall_hits::total           2599                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst         2799                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total         2799                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.inst         1090                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total         1090                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         3889                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total          3889                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         3889                       # number of overall misses
+system.cpu.l2cache.overall_misses::total         3889                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    190654250                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total    190654250                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst     75964500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total     75964500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    266618750                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total    266618750                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    266618750                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    266618750                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst         5390                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total         5390                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks           16                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total           16                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.inst         1098                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total         1098                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst         6488                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total         6488                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst         6488                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total         6488                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.519295                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.519295                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst     0.992714                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.992714                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.599414                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.599414                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.599414                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.599414                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68115.130404                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 68115.130404                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69692.201835                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69692.201835                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68557.148367                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 68557.148367                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68557.148367                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 68557.148367                       # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
+system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst           19                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total           19                       # number of ReadReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst           19                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total           19                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst           19                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total           19                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         2780                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total         2780                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst         1090                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total         1090                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         3870                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total         3870                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         3870                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total         3870                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    154631750                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total    154631750                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst     62298500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     62298500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    216930250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    216930250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    216930250                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    216930250                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.515770                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.515770                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst     0.992714                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.992714                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.596486                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.596486                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.596486                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.596486                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55622.931655                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55622.931655                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 57154.587156                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57154.587156                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56054.328165                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56054.328165                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56054.328165                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56054.328165                       # average overall mshr miss latency
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu.dcache.tags.replacements                42                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          1376.810162                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            40745471                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs              1809                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs          22523.754008                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.inst  1376.810162                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.inst     0.336135                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.336135                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         1767                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           19                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           37                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           85                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3          269                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4         1357                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024     0.431396                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses          81497573                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         81497573                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.inst     28338014                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        28338014                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.inst     12362643                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       12362643                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.inst        22407                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total        22407                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.inst        22407                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total        22407                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.inst      40700657                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         40700657                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.inst     40700657                       # number of overall hits
+system.cpu.dcache.overall_hits::total        40700657                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.inst          767                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total           767                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.inst         1644                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total         1644                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.inst         2411                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total           2411                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.inst         2411                       # number of overall misses
+system.cpu.dcache.overall_misses::total          2411                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.inst     52005983                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     52005983                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.inst    115778750                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total    115778750                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.inst    167784733                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total    167784733                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.inst    167784733                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total    167784733                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.inst     28338781                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     28338781                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.inst     12364287                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total     12364287                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.inst        22407                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total        22407                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.inst        22407                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total        22407                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.inst     40703068                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     40703068                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.inst     40703068                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     40703068                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.inst     0.000027                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.000027                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.inst     0.000133                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.000133                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.inst     0.000059                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.000059                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.inst     0.000059                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.000059                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 67804.410691                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 67804.410691                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 70425.030414                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 70425.030414                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.inst 69591.345085                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 69591.345085                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.inst 69591.345085                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 69591.345085                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks           16                       # number of writebacks
+system.cpu.dcache.writebacks::total                16                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.inst           56                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total           56                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.inst          546                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total          546                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.inst          602                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total          602                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.inst          602                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total          602                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.inst          711                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total          711                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.inst         1098                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total         1098                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.inst         1809                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total         1809                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.inst         1809                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total         1809                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst     47475265                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     47475265                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst     77144500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total     77144500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.inst    124619765                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total    124619765                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.inst    124619765                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total    124619765                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst     0.000025                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000025                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst     0.000089                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000089                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.inst     0.000044                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.000044                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.inst     0.000044                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.000044                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 66772.524613                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66772.524613                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 70259.107468                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70259.107468                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 68888.758983                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 68888.758983                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 68888.758983                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 68888.758983                       # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt
index eafc895c2..790b23ee8 100644
--- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt
@@ -1,62 +1,62 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.074057                       # Number of seconds simulated
-sim_ticks                                 74056845500                       # Number of ticks simulated
-final_tick                                74056845500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.071387                       # Number of seconds simulated
+sim_ticks                                 71387376000                       # Number of ticks simulated
+final_tick                                71387376000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 115398                       # Simulator instruction rate (inst/s)
-host_op_rate                                   126351                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               49598898                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 265028                       # Number of bytes of host memory used
-host_seconds                                  1493.11                       # Real time elapsed on the host
+host_inst_rate                                  91858                       # Simulator instruction rate (inst/s)
+host_op_rate                                    96834                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               38058123                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 257304                       # Number of bytes of host memory used
+host_seconds                                  1875.75                       # Real time elapsed on the host
 sim_insts                                   172303021                       # Number of instructions simulated
-sim_ops                                     188656503                       # Number of ops (including micro ops) simulated
+sim_ops                                     181635953                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            131840                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data            112192                       # Number of bytes read from this memory
-system.physmem.bytes_read::total               244032                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       131840                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          131840                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst               2060                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data               1753                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                  3813                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst              1780254                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              1514944                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 3295198                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         1780254                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            1780254                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             1780254                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             1514944                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                3295198                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                          3814                       # Number of read requests accepted
+system.physmem.bytes_read::cpu.inst            130496                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data            111040                       # Number of bytes read from this memory
+system.physmem.bytes_read::total               241536                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       130496                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          130496                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst               2039                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data               1735                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                  3774                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst              1827998                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              1555457                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 3383455                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         1827998                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            1827998                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             1827998                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             1555457                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                3383455                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                          3774                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
-system.physmem.readBursts                        3814                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                        3774                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                   244096                       # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM                   241536                       # Total number of bytes read from DRAM
 system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
 system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                    244096                       # Total read bytes from the system interface side
+system.physmem.bytesReadSys                    241536                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
 system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs              2                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                 307                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                 215                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                 134                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                 310                       # Per bank write bursts
-system.physmem.perBankRdBursts::4                 299                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                 300                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs             60                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0                 313                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                 214                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                 128                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                 306                       # Per bank write bursts
+system.physmem.perBankRdBursts::4                 297                       # Per bank write bursts
+system.physmem.perBankRdBursts::5                 299                       # Per bank write bursts
 system.physmem.perBankRdBursts::6                 265                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                 223                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                 246                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                 213                       # Per bank write bursts
-system.physmem.perBankRdBursts::10                289                       # Per bank write bursts
-system.physmem.perBankRdBursts::11                196                       # Per bank write bursts
-system.physmem.perBankRdBursts::12                190                       # Per bank write bursts
-system.physmem.perBankRdBursts::13                207                       # Per bank write bursts
-system.physmem.perBankRdBursts::14                219                       # Per bank write bursts
-system.physmem.perBankRdBursts::15                201                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                 217                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                 243                       # Per bank write bursts
+system.physmem.perBankRdBursts::9                 220                       # Per bank write bursts
+system.physmem.perBankRdBursts::10                282                       # Per bank write bursts
+system.physmem.perBankRdBursts::11                189                       # Per bank write bursts
+system.physmem.perBankRdBursts::12                184                       # Per bank write bursts
+system.physmem.perBankRdBursts::13                208                       # Per bank write bursts
+system.physmem.perBankRdBursts::14                212                       # Per bank write bursts
+system.physmem.perBankRdBursts::15                197                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
 system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
 system.physmem.perBankWrBursts::2                   0                       # Per bank write bursts
@@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                     74056827000                       # Total gap between requests
+system.physmem.totGap                     71387262500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                    3814                       # Read request sizes (log2)
+system.physmem.readPktSize::6                    3774                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -90,11 +90,11 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                      2889                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       752                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       131                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                        34                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                         7                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                      2817                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       790                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       125                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                        31                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                        10                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
@@ -186,29 +186,29 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples          775                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      313.641290                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     192.687696                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     311.293227                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127            258     33.29%     33.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255          189     24.39%     57.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383           87     11.23%     68.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511           51      6.58%     75.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639           41      5.29%     80.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767           31      4.00%     84.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895           43      5.55%     90.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023           10      1.29%     91.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151           65      8.39%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total            775                       # Bytes accessed per row activation
-system.physmem.totQLat                       30109750                       # Total ticks spent queuing
-system.physmem.totMemAccLat                 101622250                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                     19070000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        7894.53                       # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples          730                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      328.591781                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     199.502533                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     324.063907                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127            243     33.29%     33.29% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255          162     22.19%     55.48% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383           95     13.01%     68.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511           41      5.62%     74.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639           34      4.66%     78.77% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767           29      3.97%     82.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895           36      4.93%     87.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023           21      2.88%     90.55% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151           69      9.45%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total            730                       # Bytes accessed per row activation
+system.physmem.totQLat                       27328250                       # Total ticks spent queuing
+system.physmem.totMemAccLat                  98090750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                     18870000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        7241.19                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  26644.53                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           3.30                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  25991.19                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           3.38                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        3.30                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        3.38                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
@@ -216,44 +216,44 @@ system.physmem.busUtilRead                       0.03                       # Da
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.01                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                       3033                       # Number of row buffer hits during reads
+system.physmem.readRowHits                       3037                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   79.52                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   80.47                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                     19417101.99                       # Average gap between requests
-system.physmem.pageHitRate                      79.52                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE      70721348250                       # Time in different power states
-system.physmem.memoryStateTime::REF        2472860000                       # Time in different power states
+system.physmem.avgGap                     18915543.85                       # Average gap between requests
+system.physmem.pageHitRate                      80.47                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE      68189011250                       # Time in different power states
+system.physmem.memoryStateTime::REF        2383680000                       # Time in different power states
 system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT         861203250                       # Time in different power states
+system.physmem.memoryStateTime::ACT         812104750                       # Time in different power states
 system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.membus.throughput                      3295198                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq                2737                       # Transaction distribution
-system.membus.trans_dist::ReadResp               2736                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq                2                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp               2                       # Transaction distribution
-system.membus.trans_dist::ReadExReq              1077                       # Transaction distribution
-system.membus.trans_dist::ReadExResp             1077                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port         7631                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                   7631                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       244032                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total              244032                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus                 244032                       # Total data (bytes)
+system.membus.throughput                      3383455                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq                2699                       # Transaction distribution
+system.membus.trans_dist::ReadResp               2699                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq               60                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp              60                       # Transaction distribution
+system.membus.trans_dist::ReadExReq              1075                       # Transaction distribution
+system.membus.trans_dist::ReadExResp             1075                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port         7668                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                   7668                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       241536                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total              241536                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus                 241536                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy             4541000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy             4574500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           35636248                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy           35380947                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.branchPred.lookups                95688557                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          75485372                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           6295432                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             45268261                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                43530249                       # Number of BTB hits
+system.cpu.branchPred.lookups               106458293                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          82706448                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           6339444                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             50217715                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                48291708                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             96.160639                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 4420185                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect              89338                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             96.164686                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 5164625                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect              84625                       # Number of incorrect RAS predictions.
 system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -339,517 +339,520 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  400                       # Number of system calls
-system.cpu.numCycles                        148113692                       # number of cpu cycles simulated
+system.cpu.numCycles                        142774753                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           40192835                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      385592009                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    95688557                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           47950434                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      81543775                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                28012255                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles                4465673                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                    5                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles          5818                       # Number of stall cycles due to pending traps
+system.cpu.fetch.icacheStallCycles           44808389                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      429802861                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   106458293                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           53456333                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      91468493                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                12731388                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles                   27                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles          5563                       # Number of stall cycles due to pending traps
 system.cpu.fetch.PendingQuiesceStallCycles            1                       # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles           43                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                  37392446                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes               1863811                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          147907378                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.849949                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.160123                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.IcacheWaitRetryStallCycles           99                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                  41753796                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               1912042                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          142648266                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              3.160575                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.133574                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 66535735     44.98%     44.98% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  5361707      3.63%     48.61% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 10726789      7.25%     55.86% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 10405351      7.04%     62.90% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  8725871      5.90%     68.80% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  6634741      4.49%     73.28% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  6328592      4.28%     77.56% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  8060301      5.45%     83.01% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                 25128291     16.99%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 53718645     37.66%     37.66% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  6357410      4.46%     42.11% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 10351894      7.26%     49.37% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 14920250     10.46%     59.83% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                 10655390      7.47%     67.30% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  3891108      2.73%     70.03% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  7883355      5.53%     75.56% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  9310317      6.53%     82.08% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 25559897     17.92%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            147907378                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.646048                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        2.603352                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 45234948                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles               3964725                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  76674416                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles                488435                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles               21544854                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved             14463585                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                165860                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              398867240                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                776962                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles               21544854                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 49978288                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                   80802                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles         634035                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  72417632                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles               3251767                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              377266574                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                    64                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                 883323                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                2242172                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                  19804                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.FullRegisterEvents             7460                       # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands           639899653                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            1616068029                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       1531504010                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups           3330597                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps             298044139                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                341855514                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts              25341                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts          25337                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                   6011835                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             44415560                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            16956234                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           6645157                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          4213095                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  334591306                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded               47320                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 251099486                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued           1072213                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined       144899766                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined    380484892                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved           2104                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     147907378                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.697681                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.790678                       # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total            142648266                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.745638                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        3.010356                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 37233141                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              23853545                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  68602562                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               6747325                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                6211693                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved             15955000                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                160395                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              420485829                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                828178                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                6211693                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 42171212                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                18551410                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles         713419                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  69222818                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles               5777714                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              398176302                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                    59                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                1614739                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                2816561                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents                  62575                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.FullRegisterEvents              202                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands           691997012                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            1704697725                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        425662370                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups           3491733                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps             292976929                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                399020083                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts              28576                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts          28600                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  15636023                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             44518617                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            18120521                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           7204434                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          5193927                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  353303303                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded               50659                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 249217571                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            532732                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       170449002                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined    473050896                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved           5443                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     142648266                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.747077                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.881809                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            56583019     38.26%     38.26% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            21897324     14.80%     53.06% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            24121591     16.31%     69.37% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            20330444     13.75%     83.11% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            12466477      8.43%     91.54% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             6673732      4.51%     96.06% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             4321605      2.92%     98.98% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7             1302038      0.88%     99.86% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              211148      0.14%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            54008982     37.86%     37.86% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            21782256     15.27%     53.13% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            24530872     17.20%     70.33% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            16106640     11.29%     81.62% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            11858342      8.31%     89.93% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             6781839      4.75%     94.69% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             5090438      3.57%     98.26% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             1742716      1.22%     99.48% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              746181      0.52%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       147907378                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       142648266                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                 1040958     39.39%     39.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                   5589      0.21%     39.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     39.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     39.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     39.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     39.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     39.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     39.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     39.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     39.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     39.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     39.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     39.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     39.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     39.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     39.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     39.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     39.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     39.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     39.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                97      0.00%     39.61% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     39.61% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     39.61% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt               356      0.01%     39.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     39.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc               45      0.00%     39.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     39.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     39.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     39.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                1222208     46.25%     85.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                373303     14.13%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                 1599616     44.61%     44.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                   5629      0.16%     44.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     44.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     44.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     44.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     44.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     44.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     44.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     44.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     44.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     44.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     44.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     44.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     44.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     44.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     44.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     44.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     44.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     44.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     44.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                43      0.00%     44.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     44.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     44.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                26      0.00%     44.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     44.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc             2425      0.07%     44.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     44.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     44.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     44.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                1462989     40.80%     85.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                515010     14.36%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             195834645     77.99%     77.99% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult               981127      0.39%     78.38% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     78.38% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     78.38% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     78.38% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     78.38% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     78.38% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     78.38% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     78.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     78.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     78.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     78.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     78.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     78.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     78.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     78.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     78.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     78.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     78.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     78.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd           33203      0.01%     78.39% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     78.39% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp          164429      0.07%     78.46% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt          259909      0.10%     78.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv           76654      0.03%     78.59% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc         470113      0.19%     78.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult         206582      0.08%     78.86% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc        71910      0.03%     78.89% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt            320      0.00%     78.89% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             38922233     15.50%     94.39% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            14078361      5.61%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             192832828     77.38%     77.38% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult              1041370      0.42%     77.79% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     77.79% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     77.79% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     77.79% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     77.79% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     77.79% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     77.79% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     77.79% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     77.79% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     77.79% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     77.79% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     77.79% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     77.79% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     77.79% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     77.79% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     77.79% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     77.79% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     77.79% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     77.79% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd           33133      0.01%     77.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     77.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp          164691      0.07%     77.87% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt          264054      0.11%     77.98% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv           76936      0.03%     78.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc         473853      0.19%     78.20% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult         207040      0.08%     78.28% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc        72084      0.03%     78.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt            323      0.00%     78.31% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             39374798     15.80%     94.11% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            14676461      5.89%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              251099486                       # Type of FU issued
-system.cpu.iq.rate                           1.695316                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     2642556                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.010524                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          650051417                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         477257433                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    239511768                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads             3769702                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes            2301296                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses      1862518                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              251853224                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                 1888818                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads          2264941                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              249217571                       # Type of FU issued
+system.cpu.iq.rate                           1.745530                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     3585738                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.014388                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          641399049                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         521384383                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    237201307                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads             3802829                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes            2450137                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses      1875104                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              250898873                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                 1904436                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads          1999527                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads     14566076                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        14946                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        20827                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      4311600                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads     16622473                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        18079                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        32569                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      5475887                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads           16                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked           115                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads       334532                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked           126                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles               21544854                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                    1947                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                  2849                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           334655682                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            756589                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              44415560                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             16956234                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts              24912                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                    319                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                  2632                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          20827                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect        3907560                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect      3770350                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              7677910                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             244706645                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              37396904                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           6392841                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                6211693                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                18514097                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                 29892                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           353371291                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            723756                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts              44518617                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             18120521                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts              28251                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                   2286                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                 27735                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          32569                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        3999566                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      3827175                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              7826741                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             243157329                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              37609930                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           6060242                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                         17056                       # number of nop insts executed
-system.cpu.iew.exec_refs                     51162912                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 53733408                       # Number of branches executed
-system.cpu.iew.exec_stores                   13766008                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.652154                       # Inst execution rate
-system.cpu.iew.wb_sent                      242463171                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     241374286                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 150213875                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 271770811                       # num instructions consuming a value
+system.cpu.iew.exec_nop                         17329                       # number of nop insts executed
+system.cpu.iew.exec_refs                     51859202                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 55857945                       # Number of branches executed
+system.cpu.iew.exec_stores                   14249272                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.703084                       # Inst execution rate
+system.cpu.iew.wb_sent                      240511751                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     239076411                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 145760285                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 269855272                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.629655                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.552723                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.674501                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.540142                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts       145985060                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts       171723245                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls           45216                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts           6141058                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    126362524                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.493092                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.207919                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts           6185443                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    117932320                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.540293                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.243745                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     57333838     45.37%     45.37% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     31277146     24.75%     70.12% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     13531640     10.71%     80.83% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      7550408      5.98%     86.81% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      4276360      3.38%     90.19% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      1325331      1.05%     91.24% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      1692872      1.34%     92.58% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      1209518      0.96%     93.54% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      8165411      6.46%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     51372616     43.56%     43.56% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     31468321     26.68%     70.24% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     11935963     10.12%     80.37% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      6951478      5.89%     86.26% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      3813624      3.23%     89.49% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      1418078      1.20%     90.70% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      1525333      1.29%     91.99% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      1616480      1.37%     93.36% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      7830427      6.64%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    126362524                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    117932320                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts            172317409                       # Number of instructions committed
-system.cpu.commit.committedOps              188670891                       # Number of ops (including micro ops) committed
+system.cpu.commit.committedOps              181650341                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                       42494118                       # Number of memory references committed
-system.cpu.commit.loads                      29849484                       # Number of loads committed
+system.cpu.commit.refs                       40540778                       # Number of memory references committed
+system.cpu.commit.loads                      27896144                       # Number of loads committed
 system.cpu.commit.membars                       22408                       # Number of memory barriers committed
 system.cpu.commit.branches                   40300311                       # Number of branches committed
 system.cpu.commit.fp_insts                    1752310                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                 150106217                       # Number of committed integer instructions.
+system.cpu.commit.int_insts                 143085667                       # Number of committed integer instructions.
 system.cpu.commit.function_calls              1848934                       # Number of function calls committed.
 system.cpu.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu        144055022     76.35%     76.35% # Class of committed instruction
-system.cpu.commit.op_class_0::IntMult          908940      0.48%     76.83% # Class of committed instruction
-system.cpu.commit.op_class_0::IntDiv                0      0.00%     76.83% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatAdd              0      0.00%     76.83% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatCmp              0      0.00%     76.83% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatCvt              0      0.00%     76.83% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMult             0      0.00%     76.83% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatDiv              0      0.00%     76.83% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     76.83% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAdd               0      0.00%     76.83% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     76.83% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAlu               0      0.00%     76.83% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdCmp               0      0.00%     76.83% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdCvt               0      0.00%     76.83% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMisc              0      0.00%     76.83% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMult              0      0.00%     76.83% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     76.83% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdShift             0      0.00%     76.83% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     76.83% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     76.83% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatAdd        32754      0.02%     76.85% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     76.85% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatCmp       154829      0.08%     76.93% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatCvt       238880      0.13%     77.06% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatDiv        76016      0.04%     77.10% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMisc       437591      0.23%     77.33% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMult       200806      0.11%     77.44% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMultAcc        71617      0.04%     77.48% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatSqrt          318      0.00%     77.48% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead        29849484     15.82%     93.30% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite       12644634      6.70%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu        138987812     76.51%     76.51% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult          908940      0.50%     77.01% # Class of committed instruction
+system.cpu.commit.op_class_0::IntDiv                0      0.00%     77.01% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatAdd              0      0.00%     77.01% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCmp              0      0.00%     77.01% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCvt              0      0.00%     77.01% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatMult             0      0.00%     77.01% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatDiv              0      0.00%     77.01% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     77.01% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAdd               0      0.00%     77.01% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     77.01% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAlu               0      0.00%     77.01% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCmp               0      0.00%     77.01% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCvt               0      0.00%     77.01% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMisc              0      0.00%     77.01% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMult              0      0.00%     77.01% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     77.01% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShift             0      0.00%     77.01% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     77.01% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     77.01% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAdd        32754      0.02%     77.03% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     77.03% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCmp       154829      0.09%     77.12% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCvt       238880      0.13%     77.25% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatDiv        76016      0.04%     77.29% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMisc       437591      0.24%     77.53% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMult       200806      0.11%     77.64% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMultAcc        71617      0.04%     77.68% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatSqrt          318      0.00%     77.68% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead        27896144     15.36%     93.04% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite       12644634      6.96%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total         188670891                       # Class of committed instruction
-system.cpu.commit.bw_lim_events               8165411                       # number cycles where commit BW limit reached
+system.cpu.commit.op_class_0::total         181650341                       # Class of committed instruction
+system.cpu.commit.bw_lim_events               7830427                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                    452847863                       # The number of ROB reads
-system.cpu.rob.rob_writes                   690972129                       # The number of ROB writes
-system.cpu.timesIdled                            2844                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                          206314                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads                    463470278                       # The number of ROB reads
+system.cpu.rob.rob_writes                   731648814                       # The number of ROB writes
+system.cpu.timesIdled                            1645                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                          126487                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                   172303021                       # Number of Instructions Simulated
-system.cpu.committedOps                     188656503                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               0.859612                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.859612                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.163316                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.163316                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               1087499674                       # number of integer regfile reads
-system.cpu.int_regfile_writes               386673292                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                   2922602                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                  2532629                       # number of floating regfile writes
-system.cpu.misc_regfile_reads                65625361                       # number of misc regfile reads
+system.cpu.committedOps                     181635953                       # Number of Ops (including micro ops) Simulated
+system.cpu.cpi                               0.828626                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.828626                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.206817                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.206817                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                248213314                       # number of integer regfile reads
+system.cpu.int_regfile_writes               133191535                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                   2934311                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                  2552498                       # number of floating regfile writes
+system.cpu.cc_regfile_reads                 830988511                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                255127381                       # number of cc regfile writes
+system.cpu.misc_regfile_reads                66039150                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                 820036                       # number of misc regfile writes
-system.cpu.toL2Bus.throughput                 5184342                       # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq           4900                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp          4899                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback           16                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq            2                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp            2                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq         1084                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp         1084                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         8245                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         3740                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total             11985                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       263744                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       120064                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total         383808                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus            383808                       # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus          128                       # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy        3017000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.throughput                 5345035                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq           4859                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp          4858                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback           17                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq           61                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp           61                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq         1087                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp         1087                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         8146                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         3823                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total             11969                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       258688                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       118976                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total         377664                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus            377664                       # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus         3904                       # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy        3029000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy       6552747                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy       6522997                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy       3102991                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy       3106540                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu.icache.tags.replacements              2387                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1349.069671                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            37387126                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs              4121                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs           9072.343121                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements              2317                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1337.456920                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            41747829                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs              4039                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          10336.179500                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1349.069671                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.658725                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.658725                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024         1734                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           40                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1           86                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          547                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3           28                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_blocks::cpu.inst  1337.456920                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.653055                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.653055                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1722                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           44                       # Occupied blocks per task id
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+system.cpu.icache.tags.age_task_id_blocks_1024::2          528                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3           30                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::4         1033                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.846680                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          74789015                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         74789015                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     37387126                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        37387126                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      37387126                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         37387126                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     37387126                       # number of overall hits
-system.cpu.icache.overall_hits::total        37387126                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst         5320                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total          5320                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst         5320                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total           5320                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst         5320                       # number of overall misses
-system.cpu.icache.overall_misses::total          5320                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    224799997                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    224799997                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    224799997                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    224799997                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    224799997                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    224799997                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     37392446                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     37392446                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     37392446                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     37392446                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     37392446                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     37392446                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000142                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000142                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000142                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000142                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000142                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000142                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42255.638534                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 42255.638534                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 42255.638534                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 42255.638534                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 42255.638534                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 42255.638534                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs         1071                       # number of cycles access was blocked
+system.cpu.icache.tags.occ_task_id_percent::1024     0.840820                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses          83511695                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         83511695                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     41748272                       # number of ReadReq hits
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+system.cpu.icache.overall_hits::total        41748272                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         5524                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          5524                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         5524                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           5524                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         5524                       # number of overall misses
+system.cpu.icache.overall_misses::total          5524                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    227823494                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    227823494                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    227823494                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    227823494                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    227823494                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    227823494                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     41753796                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     41753796                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     41753796                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     41753796                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     41753796                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     41753796                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000132                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000132                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000132                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000132                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000132                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000132                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 41242.486242                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 41242.486242                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 41242.486242                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 41242.486242                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 41242.486242                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 41242.486242                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs          857                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                18                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    59.500000                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    47.611111                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst         1196                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total         1196                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst         1196                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total         1196                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst         1196                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total         1196                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst         4124                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total         4124                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst         4124                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total         4124                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst         4124                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total         4124                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    168596253                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    168596253                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    168596253                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    168596253                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    168596253                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    168596253                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000110                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000110                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000110                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.000110                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000110                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.000110                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40881.729631                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40881.729631                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40881.729631                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 40881.729631                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40881.729631                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 40881.729631                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         1420                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total         1420                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst         1420                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total         1420                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst         1420                       # number of overall MSHR hits
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+system.cpu.icache.ReadReq_mshr_misses::cpu.inst         4104                       # number of ReadReq MSHR misses
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+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    164891501                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    164891501                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    164891501                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    164891501                       # number of demand (read+write) MSHR miss cycles
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+system.cpu.icache.overall_mshr_miss_latency::total    164891501                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000098                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000098                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000098                       # mshr miss rate for demand accesses
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+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40178.240984                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40178.240984                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40178.240984                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 40178.240984                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40178.240984                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 40178.240984                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse         1967.769315                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs               2148                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs             2745                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             0.782514                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.tagsinuse         1935.733118                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs               2084                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs             2703                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             0.770995                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks     4.017679                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  1427.875766                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   535.875870                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.000123                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.043575                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.016354                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.060052                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024         2745                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           41                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1           96                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          608                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3           28                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4         1972                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.083771                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses            51829                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses           51829                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst         2058                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data           89                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total           2147                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks           16                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total           16                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data            7                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total            7                       # number of ReadExReq hits
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-system.cpu.l2cache.overall_hits::cpu.data           96                       # number of overall hits
-system.cpu.l2cache.overall_hits::total           2154                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst         2064                       # number of ReadReq misses
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-system.cpu.l2cache.UpgradeReq_misses::total            2                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data         1077                       # number of ReadExReq misses
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-system.cpu.l2cache.ReadReq_miss_latency::cpu.data     49531000                       # number of ReadReq miss cycles
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-system.cpu.l2cache.overall_miss_latency::cpu.data    123611000                       # number of overall miss cycles
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-system.cpu.l2cache.ReadReq_accesses::total         4898                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks           16                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total           16                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data            2                       # number of UpgradeReq accesses(hits+misses)
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-system.cpu.l2cache.ReadExReq_accesses::cpu.data         1084                       # number of ReadExReq accesses(hits+misses)
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-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.500728                       # miss rate for ReadReq accesses
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-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data            1                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.993542                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.993542                       # miss rate for ReadExReq accesses
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-system.cpu.l2cache.demand_miss_rate::cpu.data     0.948387                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.639920                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.500728                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.948387                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.639920                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69709.423450                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72097.525473                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 70305.797892                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68783.658310                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68783.658310                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69709.423450                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70074.263039                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 69877.547022                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69709.423450                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70074.263039                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 69877.547022                       # average overall miss latency
+system.cpu.l2cache.tags.occ_blocks::writebacks     3.025142                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  1410.130158                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data   522.577818                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.000092                       # Average percentage of cache occupancy
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+system.cpu.l2cache.tags.occ_task_id_blocks::1024         2703                       # Occupied blocks per task id
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+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          599                       # Occupied blocks per task id
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+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.082489                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses            51495                       # Number of tag accesses
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+system.cpu.l2cache.ReadReq_hits::cpu.inst         2000                       # number of ReadReq hits
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+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70585.193452                       # average ReadReq miss latency
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+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        68990                       # average ReadExReq miss latency
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+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68876.896721                       # average overall miss latency
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+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68876.896721                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69603.606182                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 69211.873351                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -859,201 +862,217 @@ system.cpu.l2cache.avg_blocked_cycles::no_targets          nan
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            3                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           11                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total           14                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           12                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total           15                       # number of ReadReq MSHR hits
 system.cpu.l2cache.demand_mshr_hits::cpu.inst            3                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data           11                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total           14                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data           12                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total           15                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.overall_mshr_hits::cpu.inst            3                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data           11                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total           14                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         2061                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          676                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total         2737                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data            2                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total            2                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         1077                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total         1077                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         2061                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data         1753                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total         3814                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         2061                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data         1753                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total         3814                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    117822250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     40424500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total    158246750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data        20002                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total        20002                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     60589000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     60589000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    117822250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    101013500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    218835750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    117822250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    101013500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    218835750                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.500000                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.871134                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.558800                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.993542                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.993542                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.500000                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.942473                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.637579                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.500000                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.942473                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.637579                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57167.515769                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59799.556213                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57817.592254                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        10001                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        10001                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56257.195915                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56257.195915                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57167.515769                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57623.217342                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57376.966439                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57167.515769                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57623.217342                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57376.966439                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_hits::cpu.data           12                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total           15                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         2040                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          660                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total         2700                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data           60                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total           60                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         1075                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total         1075                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         2040                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data         1735                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total         3775                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         2040                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data         1735                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total         3775                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    114933000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     38476250                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total    153409250                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       623553                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       623553                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     60696250                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     60696250                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    114933000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     99172500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    214105500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    114933000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     99172500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    214105500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.504576                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.874172                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.562734                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.983607                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.983607                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.988960                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.988960                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.504576                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.941911                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.641461                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.504576                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.941911                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.641461                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56339.705882                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58297.348485                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56818.240741                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10392.550000                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10392.550000                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56461.627907                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56461.627907                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56339.705882                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57159.942363                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56716.688742                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56339.705882                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57159.942363                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56716.688742                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.dcache.tags.replacements                56                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          1410.171492                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            47073011                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs              1860                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs          25308.070430                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse          1395.016190                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            47368346                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs              1842                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs          25715.714441                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  1410.171492                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.344280                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.344280                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024         1804                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           26                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1           39                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2          354                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_blocks::cpu.data  1395.016190                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.340580                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.340580                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         1786                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           25                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           36                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          353                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::3            3                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::4         1382                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024     0.440430                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          94167216                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         94167216                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     34671591                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        34671591                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     12356534                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       12356534                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data        22477                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total        22477                       # number of LoadLockedReq hits
+system.cpu.dcache.tags.age_task_id_blocks_1024::4         1369                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024     0.436035                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses          94757994                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         94757994                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     34966407                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        34966407                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     12356440                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       12356440                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data          545                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total           545                       # number of SoftPFReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data        22480                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total        22480                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data        22407                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total        22407                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      47028125                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         47028125                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     47028125                       # number of overall hits
-system.cpu.dcache.overall_hits::total        47028125                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data         1914                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total          1914                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data         7753                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total         7753                       # number of WriteReq misses
+system.cpu.dcache.demand_hits::cpu.data      47322847                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         47322847                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     47323392                       # number of overall hits
+system.cpu.dcache.overall_hits::total        47323392                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data         1942                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total          1942                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data         7847                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total         7847                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data            6                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total            6                       # number of SoftPFReq misses
 system.cpu.dcache.LoadLockedReq_misses::cpu.data            2                       # number of LoadLockedReq misses
 system.cpu.dcache.LoadLockedReq_misses::total            2                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data         9667                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total           9667                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data         9667                       # number of overall misses
-system.cpu.dcache.overall_misses::total          9667                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data    120679977                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total    120679977                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data    501616998                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total    501616998                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       142500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total       142500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data    622296975                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total    622296975                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data    622296975                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total    622296975                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     34673505                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     34673505                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data         9789                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total           9789                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data         9795                       # number of overall misses
+system.cpu.dcache.overall_misses::total          9795                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data    120282480                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total    120282480                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data    504727051                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total    504727051                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       143500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total       143500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data    625009531                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total    625009531                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data    625009531                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total    625009531                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     34968349                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     34968349                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     12364287                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     12364287                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data        22479                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total        22479                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data          551                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total          551                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data        22482                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total        22482                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data        22407                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total        22407                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     47037792                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     47037792                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     47037792                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     47037792                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000055                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.000055                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000627                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.000627                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_accesses::cpu.data     47332636                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     47332636                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     47333187                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     47333187                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000056                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.000056                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000635                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.000635                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.010889                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.010889                       # miss rate for SoftPFReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.000089                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::total     0.000089                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.000206                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.000206                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.000206                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.000206                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63051.189655                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 63051.189655                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64699.728879                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 64699.728879                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        71250                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        71250                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 64373.329368                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 64373.329368                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 64373.329368                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 64373.329368                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs          706                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets           99                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                14                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               1                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    50.428571                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets           99                       # average number of cycles each access was blocked
+system.cpu.dcache.demand_miss_rate::cpu.data     0.000207                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.000207                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.000207                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.000207                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 61937.425335                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 61937.425335                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64321.020900                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 64321.020900                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        71750                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        71750                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 63848.149045                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 63848.149045                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 63809.038387                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 63809.038387                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs          848                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets           85                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                16                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               2                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs           53                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets    42.500000                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks           16                       # number of writebacks
-system.cpu.dcache.writebacks::total                16                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data         1137                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total         1137                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data         6668                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total         6668                       # number of WriteReq MSHR hits
+system.cpu.dcache.writebacks::writebacks           17                       # number of writebacks
+system.cpu.dcache.writebacks::total                17                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data         1189                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total         1189                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data         6701                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total         6701                       # number of WriteReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            2                       # number of LoadLockedReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::total            2                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data         7805                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total         7805                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data         7805                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total         7805                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data          777                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total          777                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data         1085                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total         1085                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data         1862                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total         1862                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data         1862                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total         1862                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     51275761                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total     51275761                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data     75222996                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total     75222996                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data    126498757                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total    126498757                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data    126498757                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total    126498757                       # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_hits::cpu.data         7890                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total         7890                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data         7890                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total         7890                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data          753                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total          753                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data         1146                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total         1146                       # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data            4                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total            4                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data         1899                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total         1899                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data         1903                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total         1903                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     48859513                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     48859513                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data     76658945                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total     76658945                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data       305000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total       305000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data    125518458                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total    125518458                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data    125823458                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total    125823458                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000022                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000022                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000088                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000088                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000093                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000093                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.007260                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.007260                       # mshr miss rate for SoftPFReq accesses
 system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000040                       # mshr miss rate for demand accesses
 system.cpu.dcache.demand_mshr_miss_rate::total     0.000040                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000040                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.000040                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 65991.970399                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 65991.970399                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 69329.950230                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69329.950230                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 67937.033835                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 67937.033835                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67937.033835                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 67937.033835                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 64886.471448                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 64886.471448                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 66892.622164                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66892.622164                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data        76250                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total        76250                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66097.134281                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 66097.134281                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66118.475039                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 66118.475039                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt
index af9e4b297..dd6254b3c 100644
--- a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt
@@ -1,16 +1,16 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.103107                       # Number of seconds simulated
-sim_ticks                                103106766000                       # Number of ticks simulated
-final_tick                               103106766000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.099596                       # Number of seconds simulated
+sim_ticks                                 99596491000                       # Number of ticks simulated
+final_tick                                99596491000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1728223                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1892237                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1034088491                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 304984                       # Number of bytes of host memory used
-host_seconds                                    99.71                       # Real time elapsed on the host
+host_inst_rate                                1821315                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1919960                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1052688537                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 309564                       # Number of bytes of host memory used
+host_seconds                                    94.61                       # Real time elapsed on the host
 sim_insts                                   172317409                       # Number of instructions simulated
-sim_ops                                     188670891                       # Number of ops (including micro ops) simulated
+sim_ops                                     181650341                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst         759440204                       # Number of bytes read from this memory
@@ -21,21 +21,21 @@ system.physmem.bytes_inst_read::total       759440204                       # Nu
 system.physmem.bytes_written::cpu.data       45252940                       # Number of bytes written to this memory
 system.physmem.bytes_written::total          45252940                       # Number of bytes written to this memory
 system.physmem.num_reads::cpu.inst          189860051                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data           29622453                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total             219482504                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data           27777721                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total             217637772                       # Number of read requests responded to by this memory
 system.physmem.num_writes::cpu.data          12386694                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total             12386694                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst           7365570985                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data           1072031112                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              8437602097                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst      7365570985                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total         7365570985                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data           438893991                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total              438893991                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst          7365570985                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data          1510925103                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             8876496088                       # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput                   8876496088                       # Throughput (bytes/s)
+system.physmem.bw_read::cpu.inst           7625170288                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data           1109814813                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              8734985101                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst      7625170288                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total         7625170288                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data           454362795                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total              454362795                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst          7625170288                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data          1564177607                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             9189347896                       # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput                   9189347896                       # Throughput (bytes/s)
 system.membus.data_through_bus              915226805                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
@@ -124,63 +124,65 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  400                       # Number of system calls
-system.cpu.numCycles                        206213533                       # number of cpu cycles simulated
+system.cpu.numCycles                        199192983                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                   172317409                       # Number of instructions committed
-system.cpu.committedOps                     188670891                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses             150106218                       # Number of integer alu accesses
+system.cpu.committedOps                     181650341                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses             143085668                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                1752310                       # Number of float alu accesses
 system.cpu.num_func_calls                     3545028                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts     32494341                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                    150106218                       # number of integer instructions
+system.cpu.num_conditional_control_insts     32201008                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                    143085668                       # number of integer instructions
 system.cpu.num_fp_insts                       1752310                       # number of float instructions
-system.cpu.num_int_register_reads           815315678                       # number of times the integer registers were read
-system.cpu.num_int_register_writes          294073517                       # number of times the integer registers were written
+system.cpu.num_int_register_reads           241970171                       # number of times the integer registers were read
+system.cpu.num_int_register_writes           98192342                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads              2822225                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes             2378039                       # number of times the floating registers were written
-system.cpu.num_mem_refs                      42494119                       # number of memory refs
-system.cpu.num_load_insts                    29849484                       # Number of load instructions
+system.cpu.num_cc_register_reads            543309967                       # number of times the CC registers were read
+system.cpu.num_cc_register_writes           190815535                       # number of times the CC registers were written
+system.cpu.num_mem_refs                      40540779                       # number of memory refs
+system.cpu.num_load_insts                    27896144                       # Number of load instructions
 system.cpu.num_store_insts                   12644635                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                  206213533                       # Number of busy cycles
+system.cpu.num_busy_cycles                  199192983                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                          40300311                       # Number of branches fetched
 system.cpu.op_class::No_OpClass                     0      0.00%      0.00% # Class of executed instruction
-system.cpu.op_class::IntAlu                 144055422     76.35%     76.35% # Class of executed instruction
-system.cpu.op_class::IntMult                   908940      0.48%     76.83% # Class of executed instruction
-system.cpu.op_class::IntDiv                         0      0.00%     76.83% # Class of executed instruction
-system.cpu.op_class::FloatAdd                       0      0.00%     76.83% # Class of executed instruction
-system.cpu.op_class::FloatCmp                       0      0.00%     76.83% # Class of executed instruction
-system.cpu.op_class::FloatCvt                       0      0.00%     76.83% # Class of executed instruction
-system.cpu.op_class::FloatMult                      0      0.00%     76.83% # Class of executed instruction
-system.cpu.op_class::FloatDiv                       0      0.00%     76.83% # Class of executed instruction
-system.cpu.op_class::FloatSqrt                      0      0.00%     76.83% # Class of executed instruction
-system.cpu.op_class::SimdAdd                        0      0.00%     76.83% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc                     0      0.00%     76.83% # Class of executed instruction
-system.cpu.op_class::SimdAlu                        0      0.00%     76.83% # Class of executed instruction
-system.cpu.op_class::SimdCmp                        0      0.00%     76.83% # Class of executed instruction
-system.cpu.op_class::SimdCvt                        0      0.00%     76.83% # Class of executed instruction
-system.cpu.op_class::SimdMisc                       0      0.00%     76.83% # Class of executed instruction
-system.cpu.op_class::SimdMult                       0      0.00%     76.83% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc                    0      0.00%     76.83% # Class of executed instruction
-system.cpu.op_class::SimdShift                      0      0.00%     76.83% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc                   0      0.00%     76.83% # Class of executed instruction
-system.cpu.op_class::SimdSqrt                       0      0.00%     76.83% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd               32754      0.02%     76.85% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu                   0      0.00%     76.85% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp              154829      0.08%     76.93% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt              238880      0.13%     77.06% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv               76016      0.04%     77.10% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc             437591      0.23%     77.33% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult             200806      0.11%     77.44% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc           71617      0.04%     77.48% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt                318      0.00%     77.48% # Class of executed instruction
-system.cpu.op_class::MemRead                 29849484     15.82%     93.30% # Class of executed instruction
-system.cpu.op_class::MemWrite                12644635      6.70%    100.00% # Class of executed instruction
+system.cpu.op_class::IntAlu                 138988212     76.51%     76.51% # Class of executed instruction
+system.cpu.op_class::IntMult                   908940      0.50%     77.01% # Class of executed instruction
+system.cpu.op_class::IntDiv                         0      0.00%     77.01% # Class of executed instruction
+system.cpu.op_class::FloatAdd                       0      0.00%     77.01% # Class of executed instruction
+system.cpu.op_class::FloatCmp                       0      0.00%     77.01% # Class of executed instruction
+system.cpu.op_class::FloatCvt                       0      0.00%     77.01% # Class of executed instruction
+system.cpu.op_class::FloatMult                      0      0.00%     77.01% # Class of executed instruction
+system.cpu.op_class::FloatDiv                       0      0.00%     77.01% # Class of executed instruction
+system.cpu.op_class::FloatSqrt                      0      0.00%     77.01% # Class of executed instruction
+system.cpu.op_class::SimdAdd                        0      0.00%     77.01% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc                     0      0.00%     77.01% # Class of executed instruction
+system.cpu.op_class::SimdAlu                        0      0.00%     77.01% # Class of executed instruction
+system.cpu.op_class::SimdCmp                        0      0.00%     77.01% # Class of executed instruction
+system.cpu.op_class::SimdCvt                        0      0.00%     77.01% # Class of executed instruction
+system.cpu.op_class::SimdMisc                       0      0.00%     77.01% # Class of executed instruction
+system.cpu.op_class::SimdMult                       0      0.00%     77.01% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc                    0      0.00%     77.01% # Class of executed instruction
+system.cpu.op_class::SimdShift                      0      0.00%     77.01% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc                   0      0.00%     77.01% # Class of executed instruction
+system.cpu.op_class::SimdSqrt                       0      0.00%     77.01% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd               32754      0.02%     77.03% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu                   0      0.00%     77.03% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp              154829      0.09%     77.12% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt              238880      0.13%     77.25% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv               76016      0.04%     77.29% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc             437591      0.24%     77.53% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult             200806      0.11%     77.64% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc           71617      0.04%     77.68% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt                318      0.00%     77.68% # Class of executed instruction
+system.cpu.op_class::MemRead                 27896144     15.36%     93.04% # Class of executed instruction
+system.cpu.op_class::MemWrite                12644635      6.96%    100.00% # Class of executed instruction
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::total                  188671292                       # Class of executed instruction
+system.cpu.op_class::total                  181650742                       # Class of executed instruction
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt
index 7e06925a9..6f9f28d30 100644
--- a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt
@@ -1,16 +1,16 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.232072                       # Number of seconds simulated
-sim_ticks                                232072304000                       # Number of ticks simulated
-final_tick                               232072304000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.230173                       # Number of seconds simulated
+sim_ticks                                230173357000                       # Number of ticks simulated
+final_tick                               230173357000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 924224                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1012125                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1248159761                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 313696                       # Number of bytes of host memory used
-host_seconds                                   185.93                       # Real time elapsed on the host
+host_inst_rate                                1246866                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1314511                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1670106565                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 319316                       # Number of bytes of host memory used
+host_seconds                                   137.82                       # Real time elapsed on the host
 sim_insts                                   171842483                       # Number of instructions simulated
-sim_ops                                     188185920                       # Number of ops (including micro ops) simulated
+sim_ops                                     181165370                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst            110656                       # Number of bytes read from this memory
@@ -21,15 +21,15 @@ system.physmem.bytes_inst_read::total          110656                       # Nu
 system.physmem.num_reads::cpu.inst               1729                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data               1724                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                  3453                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst               476817                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data               475438                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                  952255                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          476817                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             476817                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              476817                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data              475438                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                 952255                       # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput                       952255                       # Throughput (bytes/s)
+system.physmem.bw_read::cpu.inst               480751                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data               479360                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                  960111                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          480751                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             480751                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              480751                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data              479360                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                 960111                       # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput                       960111                       # Throughput (bytes/s)
 system.membus.trans_dist::ReadReq                2361                       # Transaction distribution
 system.membus.trans_dist::ReadResp               2361                       # Transaction distribution
 system.membus.trans_dist::ReadExReq              1092                       # Transaction distribution
@@ -40,9 +40,9 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port
 system.membus.tot_pkt_size::total              220992                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.data_through_bus                 220992                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy             3453000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy             3596000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           31077000                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy           31220000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
@@ -130,73 +130,75 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  400                       # Number of system calls
-system.cpu.numCycles                        464144608                       # number of cpu cycles simulated
+system.cpu.numCycles                        460346714                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                   171842483                       # Number of instructions committed
-system.cpu.committedOps                     188185920                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses             150106218                       # Number of integer alu accesses
+system.cpu.committedOps                     181165370                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses             143085668                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                1752310                       # Number of float alu accesses
 system.cpu.num_func_calls                     3545028                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts     32494341                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                    150106218                       # number of integer instructions
+system.cpu.num_conditional_control_insts     32201008                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                    143085668                       # number of integer instructions
 system.cpu.num_fp_insts                       1752310                       # number of float instructions
-system.cpu.num_int_register_reads           904571312                       # number of times the integer registers were read
-system.cpu.num_int_register_writes          294073517                       # number of times the integer registers were written
+system.cpu.num_int_register_reads           242291225                       # number of times the integer registers were read
+system.cpu.num_int_register_writes           98192342                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads              2822225                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes             2378039                       # number of times the floating registers were written
-system.cpu.num_mem_refs                      42494119                       # number of memory refs
-system.cpu.num_load_insts                    29849484                       # Number of load instructions
+system.cpu.num_cc_register_reads            626384527                       # number of times the CC registers were read
+system.cpu.num_cc_register_writes           190815535                       # number of times the CC registers were written
+system.cpu.num_mem_refs                      40540779                       # number of memory refs
+system.cpu.num_load_insts                    27896144                       # Number of load instructions
 system.cpu.num_store_insts                   12644635                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                  464144608                       # Number of busy cycles
+system.cpu.num_busy_cycles                  460346714                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                          40300311                       # Number of branches fetched
 system.cpu.op_class::No_OpClass                     0      0.00%      0.00% # Class of executed instruction
-system.cpu.op_class::IntAlu                 144055422     76.35%     76.35% # Class of executed instruction
-system.cpu.op_class::IntMult                   908940      0.48%     76.83% # Class of executed instruction
-system.cpu.op_class::IntDiv                         0      0.00%     76.83% # Class of executed instruction
-system.cpu.op_class::FloatAdd                       0      0.00%     76.83% # Class of executed instruction
-system.cpu.op_class::FloatCmp                       0      0.00%     76.83% # Class of executed instruction
-system.cpu.op_class::FloatCvt                       0      0.00%     76.83% # Class of executed instruction
-system.cpu.op_class::FloatMult                      0      0.00%     76.83% # Class of executed instruction
-system.cpu.op_class::FloatDiv                       0      0.00%     76.83% # Class of executed instruction
-system.cpu.op_class::FloatSqrt                      0      0.00%     76.83% # Class of executed instruction
-system.cpu.op_class::SimdAdd                        0      0.00%     76.83% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc                     0      0.00%     76.83% # Class of executed instruction
-system.cpu.op_class::SimdAlu                        0      0.00%     76.83% # Class of executed instruction
-system.cpu.op_class::SimdCmp                        0      0.00%     76.83% # Class of executed instruction
-system.cpu.op_class::SimdCvt                        0      0.00%     76.83% # Class of executed instruction
-system.cpu.op_class::SimdMisc                       0      0.00%     76.83% # Class of executed instruction
-system.cpu.op_class::SimdMult                       0      0.00%     76.83% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc                    0      0.00%     76.83% # Class of executed instruction
-system.cpu.op_class::SimdShift                      0      0.00%     76.83% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc                   0      0.00%     76.83% # Class of executed instruction
-system.cpu.op_class::SimdSqrt                       0      0.00%     76.83% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd               32754      0.02%     76.85% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu                   0      0.00%     76.85% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp              154829      0.08%     76.93% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt              238880      0.13%     77.06% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv               76016      0.04%     77.10% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc             437591      0.23%     77.33% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult             200806      0.11%     77.44% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc           71617      0.04%     77.48% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt                318      0.00%     77.48% # Class of executed instruction
-system.cpu.op_class::MemRead                 29849484     15.82%     93.30% # Class of executed instruction
-system.cpu.op_class::MemWrite                12644635      6.70%    100.00% # Class of executed instruction
+system.cpu.op_class::IntAlu                 138988212     76.51%     76.51% # Class of executed instruction
+system.cpu.op_class::IntMult                   908940      0.50%     77.01% # Class of executed instruction
+system.cpu.op_class::IntDiv                         0      0.00%     77.01% # Class of executed instruction
+system.cpu.op_class::FloatAdd                       0      0.00%     77.01% # Class of executed instruction
+system.cpu.op_class::FloatCmp                       0      0.00%     77.01% # Class of executed instruction
+system.cpu.op_class::FloatCvt                       0      0.00%     77.01% # Class of executed instruction
+system.cpu.op_class::FloatMult                      0      0.00%     77.01% # Class of executed instruction
+system.cpu.op_class::FloatDiv                       0      0.00%     77.01% # Class of executed instruction
+system.cpu.op_class::FloatSqrt                      0      0.00%     77.01% # Class of executed instruction
+system.cpu.op_class::SimdAdd                        0      0.00%     77.01% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc                     0      0.00%     77.01% # Class of executed instruction
+system.cpu.op_class::SimdAlu                        0      0.00%     77.01% # Class of executed instruction
+system.cpu.op_class::SimdCmp                        0      0.00%     77.01% # Class of executed instruction
+system.cpu.op_class::SimdCvt                        0      0.00%     77.01% # Class of executed instruction
+system.cpu.op_class::SimdMisc                       0      0.00%     77.01% # Class of executed instruction
+system.cpu.op_class::SimdMult                       0      0.00%     77.01% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc                    0      0.00%     77.01% # Class of executed instruction
+system.cpu.op_class::SimdShift                      0      0.00%     77.01% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc                   0      0.00%     77.01% # Class of executed instruction
+system.cpu.op_class::SimdSqrt                       0      0.00%     77.01% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd               32754      0.02%     77.03% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu                   0      0.00%     77.03% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp              154829      0.09%     77.12% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt              238880      0.13%     77.25% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv               76016      0.04%     77.29% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc             437591      0.24%     77.53% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult             200806      0.11%     77.64% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc           71617      0.04%     77.68% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt                318      0.00%     77.68% # Class of executed instruction
+system.cpu.op_class::MemRead                 27896144     15.36%     93.04% # Class of executed instruction
+system.cpu.op_class::MemWrite                12644635      6.96%    100.00% # Class of executed instruction
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::total                  188671292                       # Class of executed instruction
+system.cpu.op_class::total                  181650742                       # Class of executed instruction
 system.cpu.icache.tags.replacements              1506                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1147.986161                       # Cycle average of tags in use
+system.cpu.icache.tags.tagsinuse          1147.992604                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs           189857001                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs              3051                       # Sample count of references to valid blocks.
 system.cpu.icache.tags.avg_refs          62227.794494                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1147.986161                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.560540                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.560540                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst  1147.992604                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.560543                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.560543                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         1545                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           24                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1           21                       # Occupied blocks per task id
@@ -218,12 +220,12 @@ system.cpu.icache.demand_misses::cpu.inst         3051                       # n
 system.cpu.icache.demand_misses::total           3051                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst         3051                       # number of overall misses
 system.cpu.icache.overall_misses::total          3051                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    112281000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    112281000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    112281000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    112281000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    112281000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    112281000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    112370500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    112370500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    112370500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    112370500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    112370500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    112370500                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst    189860052                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total    189860052                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst    189860052                       # number of demand (read+write) accesses
@@ -236,12 +238,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.000016
 system.cpu.icache.demand_miss_rate::total     0.000016                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000016                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000016                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36801.376598                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 36801.376598                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 36801.376598                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 36801.376598                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 36801.376598                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 36801.376598                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36830.711242                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 36830.711242                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 36830.711242                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 36830.711242                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 36830.711242                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 36830.711242                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -256,34 +258,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst         3051
 system.cpu.icache.demand_mshr_misses::total         3051                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst         3051                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total         3051                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    106179000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    106179000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    106179000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    106179000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    106179000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    106179000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    106268500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    106268500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    106268500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    106268500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    106268500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    106268500                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000016                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000016                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000016                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000016                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000016                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000016                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34801.376598                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 34801.376598                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34801.376598                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 34801.376598                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34801.376598                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 34801.376598                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34830.711242                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 34830.711242                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34830.711242                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 34830.711242                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34830.711242                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 34830.711242                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse         1675.655740                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse         1675.663358                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs               1380                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs             2369                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs             0.582524                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks     3.038044                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  1169.032828                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   503.584868                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::writebacks     3.037779                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  1169.036759                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data   503.588821                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_percent::writebacks     0.000093                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.035676                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.015368                       # Average percentage of cache occupancy
@@ -321,17 +323,17 @@ system.cpu.l2cache.demand_misses::total          3453                       # nu
 system.cpu.l2cache.overall_misses::cpu.inst         1729                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data         1724                       # number of overall misses
 system.cpu.l2cache.overall_misses::total         3453                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     89908000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data     32864000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total    122772000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data     56784000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total     56784000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     89908000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data     89648000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total    179556000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     89908000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data     89648000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total    179556000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     89997500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data     32887000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total    122884500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data     56814500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total     56814500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     89997500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data     89701500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total    179699000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     89997500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data     89701500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    179699000                       # number of overall miss cycles
 system.cpu.l2cache.ReadReq_accesses::cpu.inst         3051                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::cpu.data          689                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::total         3740                       # number of ReadReq accesses(hits+misses)
@@ -356,17 +358,17 @@ system.cpu.l2cache.demand_miss_rate::total     0.713430                       #
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.566699                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.963667                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.713430                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst        52000                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data        52000                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total        52000                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        52000                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total        52000                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data        52000                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total        52000                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data        52000                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total        52000                       # average overall miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52051.764025                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52036.392405                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 52047.649301                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52027.930403                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52027.930403                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52051.764025                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52031.032483                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 52041.413264                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52051.764025                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52031.032483                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 52041.413264                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -421,14 +423,14 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40000
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total        40000                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.dcache.tags.replacements                40                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          1363.611259                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            42007358                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse          1363.619284                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            40162626                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs              1789                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs          23480.915595                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs          22449.762996                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  1363.611259                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.332913                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.332913                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data  1363.619284                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.332915                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.332915                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         1749                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           14                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1           21                       # Occupied blocks per task id
@@ -436,64 +438,72 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2           67
 system.cpu.dcache.tags.age_task_id_blocks_1024::3          302                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::4         1345                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024     0.427002                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          84020083                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         84020083                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     29599357                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        29599357                       # number of ReadReq hits
+system.cpu.dcache.tags.tag_accesses          80330619                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         80330619                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     27754163                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        27754163                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data     12363187                       # number of WriteReq hits
 system.cpu.dcache.WriteReq_hits::total       12363187                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data          462                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total           462                       # number of SoftPFReq hits
 system.cpu.dcache.LoadLockedReq_hits::cpu.data        22407                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total        22407                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data        22407                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total        22407                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      41962544                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         41962544                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     41962544                       # number of overall hits
-system.cpu.dcache.overall_hits::total        41962544                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data          689                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total           689                       # number of ReadReq misses
+system.cpu.dcache.demand_hits::cpu.data      40117350                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         40117350                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     40117812                       # number of overall hits
+system.cpu.dcache.overall_hits::total        40117812                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data          688                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total           688                       # number of ReadReq misses
 system.cpu.dcache.WriteReq_misses::cpu.data         1100                       # number of WriteReq misses
 system.cpu.dcache.WriteReq_misses::total         1100                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data         1789                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total           1789                       # number of demand (read+write) misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data            1                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total            1                       # number of SoftPFReq misses
+system.cpu.dcache.demand_misses::cpu.data         1788                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total           1788                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data         1789                       # number of overall misses
 system.cpu.dcache.overall_misses::total          1789                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data     35501000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     35501000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data     60164000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total     60164000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     95665000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     95665000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     95665000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     95665000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     29600046                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     29600046                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_miss_latency::cpu.data     35469000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     35469000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data     60194500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total     60194500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     95663500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     95663500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     95663500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     95663500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     27754851                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     27754851                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     12364287                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     12364287                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data          463                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total          463                       # number of SoftPFReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::cpu.data        22407                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::total        22407                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data        22407                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total        22407                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     41964333                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     41964333                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     41964333                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     41964333                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000023                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.000023                       # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data     40119138                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     40119138                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     40119601                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     40119601                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000025                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.000025                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000089                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_miss_rate::total     0.000089                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.000043                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.000043                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.000043                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.000043                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51525.399129                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 51525.399129                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54694.545455                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 54694.545455                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 53474.007826                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 53474.007826                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 53474.007826                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 53474.007826                       # average overall miss latency
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.002160                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.002160                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.000045                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.000045                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.000045                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.000045                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51553.779070                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 51553.779070                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54722.272727                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 54722.272727                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 53503.076063                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 53503.076063                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 53473.169368                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 53473.169368                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -504,40 +514,48 @@ system.cpu.dcache.fast_writes                       0                       # nu
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks           16                       # number of writebacks
 system.cpu.dcache.writebacks::total                16                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data          689                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total          689                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data          688                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total          688                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data         1100                       # number of WriteReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::total         1100                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data         1789                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total         1789                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data            1                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total            1                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data         1788                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total         1788                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data         1789                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total         1789                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     34123000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total     34123000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data     57964000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total     57964000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data     92087000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total     92087000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data     92087000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total     92087000                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000023                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000023                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     34093000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     34093000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data     57994500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total     57994500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data        53000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total        53000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data     92087500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total     92087500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data     92140500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total     92140500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000025                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000025                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000089                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000089                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000043                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.000043                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000043                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.000043                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 49525.399129                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 49525.399129                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52694.545455                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52694.545455                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51474.007826                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 51474.007826                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51474.007826                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 51474.007826                       # average overall mshr miss latency
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.002160                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.002160                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000045                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.000045                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000045                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.000045                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 49553.779070                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 49553.779070                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52722.272727                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52722.272727                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data        53000                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total        53000                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51503.076063                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 51503.076063                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51503.912800                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 51503.912800                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.throughput                 1339169                       # Throughput (bytes/s)
+system.cpu.toL2Bus.throughput                 1350217                       # Throughput (bytes/s)
 system.cpu.toL2Bus.trans_dist::ReadReq           3740                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadResp          3740                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::Writeback           16                       # Transaction distribution
diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt
index 27be407ab..7d03f3ce8 100644
--- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt
@@ -1,62 +1,62 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.145755                       # Number of seconds simulated
-sim_ticks                                145755370500                       # Number of ticks simulated
-final_tick                               145755370500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.148587                       # Number of seconds simulated
+sim_ticks                                148587085500                       # Number of ticks simulated
+final_tick                               148587085500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  67444                       # Simulator instruction rate (inst/s)
-host_op_rate                                   113042                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               74431489                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 330012                       # Number of bytes of host memory used
-host_seconds                                  1958.25                       # Real time elapsed on the host
+host_inst_rate                                 101386                       # Simulator instruction rate (inst/s)
+host_op_rate                                   169932                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              114064202                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 285092                       # Number of bytes of host memory used
+host_seconds                                  1302.66                       # Real time elapsed on the host
 sim_insts                                   132071192                       # Number of instructions simulated
 sim_ops                                     221363384                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            218240                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data            125376                       # Number of bytes read from this memory
-system.physmem.bytes_read::total               343616                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       218240                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          218240                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst               3410                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data               1959                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                  5369                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst              1497303                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data               860181                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 2357484                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         1497303                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            1497303                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             1497303                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data              860181                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                2357484                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                          5369                       # Number of read requests accepted
+system.physmem.bytes_read::cpu.inst            225472                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data            125440                       # Number of bytes read from this memory
+system.physmem.bytes_read::total               350912                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       225472                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          225472                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst               3523                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data               1960                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                  5483                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst              1517440                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data               844219                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 2361659                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         1517440                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            1517440                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             1517440                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data              844219                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                2361659                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                          5483                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
-system.physmem.readBursts                        5369                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                        5483                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                   343616                       # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM                   350912                       # Total number of bytes read from DRAM
 system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
 system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                    343616                       # Total read bytes from the system interface side
+system.physmem.bytesReadSys                    350912                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
 system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs            207                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                 284                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                 359                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                 451                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                 358                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs            350                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0                 310                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                 352                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                 465                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                 360                       # Per bank write bursts
 system.physmem.perBankRdBursts::4                 334                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                 327                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                 401                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                 381                       # Per bank write bursts
+system.physmem.perBankRdBursts::5                 328                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                 400                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                 386                       # Per bank write bursts
 system.physmem.perBankRdBursts::8                 341                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                 279                       # Per bank write bursts
-system.physmem.perBankRdBursts::10                232                       # Per bank write bursts
-system.physmem.perBankRdBursts::11                279                       # Per bank write bursts
-system.physmem.perBankRdBursts::12                208                       # Per bank write bursts
-system.physmem.perBankRdBursts::13                464                       # Per bank write bursts
-system.physmem.perBankRdBursts::14                389                       # Per bank write bursts
-system.physmem.perBankRdBursts::15                282                       # Per bank write bursts
+system.physmem.perBankRdBursts::9                 281                       # Per bank write bursts
+system.physmem.perBankRdBursts::10                278                       # Per bank write bursts
+system.physmem.perBankRdBursts::11                258                       # Per bank write bursts
+system.physmem.perBankRdBursts::12                226                       # Per bank write bursts
+system.physmem.perBankRdBursts::13                469                       # Per bank write bursts
+system.physmem.perBankRdBursts::14                405                       # Per bank write bursts
+system.physmem.perBankRdBursts::15                290                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
 system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
 system.physmem.perBankWrBursts::2                   0                       # Per bank write bursts
@@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    145755124000                       # Total gap between requests
+system.physmem.totGap                    148587005000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                    5369                       # Read request sizes (log2)
+system.physmem.readPktSize::6                    5483                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -90,11 +90,11 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                      4318                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       864                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                      4379                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       915                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::2                       165                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                        20                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                         2                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                        21                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                         3                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
@@ -186,26 +186,26 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples         1076                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      318.156134                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     184.849707                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     333.212521                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127            414     38.48%     38.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255          235     21.84%     60.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383          101      9.39%     69.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511           58      5.39%     75.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639           43      4.00%     79.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767           47      4.37%     83.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895           34      3.16%     86.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023           19      1.77%     88.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151          125     11.62%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total           1076                       # Bytes accessed per row activation
-system.physmem.totQLat                       40846250                       # Total ticks spent queuing
-system.physmem.totMemAccLat                 141515000                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                     26845000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        7607.79                       # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples         1137                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      307.616535                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     177.186204                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     330.211340                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127            456     40.11%     40.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255          252     22.16%     62.27% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383           97      8.53%     70.80% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511           50      4.40%     75.20% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639           53      4.66%     79.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767           61      5.36%     85.22% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895           21      1.85%     87.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023           17      1.50%     88.57% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151          130     11.43%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total           1137                       # Bytes accessed per row activation
+system.physmem.totQLat                       38062500                       # Total ticks spent queuing
+system.physmem.totMemAccLat                 140868750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                     27415000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        6941.91                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  26357.79                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  25691.91                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                           2.36                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                        2.36                       # Average system read bandwidth in MiByte/s
@@ -214,280 +214,281 @@ system.physmem.peakBW                        12800.00                       # Th
 system.physmem.busUtil                           0.02                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.02                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.07                       # Average read queue length when enqueuing
+system.physmem.avgRdQLen                         1.03                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                       4285                       # Number of row buffer hits during reads
+system.physmem.readRowHits                       4339                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   79.81                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   79.14                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                     27147536.60                       # Average gap between requests
-system.physmem.pageHitRate                      79.81                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE     139292792000                       # Time in different power states
-system.physmem.memoryStateTime::REF        4866940000                       # Time in different power states
+system.physmem.avgGap                     27099581.43                       # Average gap between requests
+system.physmem.pageHitRate                      79.14                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE     141978840750                       # Time in different power states
+system.physmem.memoryStateTime::REF        4961580000                       # Time in different power states
 system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT        1591366500                       # Time in different power states
+system.physmem.memoryStateTime::ACT        1644861750                       # Time in different power states
 system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.membus.throughput                      2357484                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq                3832                       # Transaction distribution
-system.membus.trans_dist::ReadResp               3832                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq              207                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp             207                       # Transaction distribution
-system.membus.trans_dist::ReadExReq              1537                       # Transaction distribution
-system.membus.trans_dist::ReadExResp             1537                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        11152                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total        11152                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                  11152                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       343616                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total       343616                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total              343616                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus                 343616                       # Total data (bytes)
+system.membus.throughput                      2361659                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq                3951                       # Transaction distribution
+system.membus.trans_dist::ReadResp               3951                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq              350                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp             350                       # Transaction distribution
+system.membus.trans_dist::ReadExReq              1532                       # Transaction distribution
+system.membus.trans_dist::ReadExResp             1532                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        11666                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total        11666                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                  11666                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       350912                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total       350912                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total              350912                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus                 350912                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy             6685000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy             7101000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           50563044                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy           51987900                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.branchPred.lookups                19312355                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          19312355                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           1526222                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             12165390                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                11208509                       # Number of BTB hits
+system.cpu.branchPred.lookups                22396239                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          22396239                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           1554538                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             14104442                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                13258278                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             92.134399                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 1374126                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect              24109                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             94.000727                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 1524438                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect              22257                       # Number of incorrect RAS predictions.
 system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
 system.cpu.workload.num_syscalls                  400                       # Number of system calls
-system.cpu.numCycles                        291824777                       # number of cpu cycles simulated
+system.cpu.numCycles                        297174180                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           24324759                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      214691013                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    19312355                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           12582635                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      56144836                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                16970936                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles              176562009                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                 2090                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles         11526                       # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles           39                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                  23234678                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                287353                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          272218372                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.300706                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.783258                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles           27916282                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      249227309                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    22396239                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           14782716                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     267173177                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 3706948                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles                         35                       # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles                 5683                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles         49787                       # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles           13                       # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles          112                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                  26681234                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                258392                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          296998563                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.383031                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.791258                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                217566223     79.92%     79.92% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  2932645      1.08%     81.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  2385496      0.88%     81.88% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  2737910      1.01%     82.88% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  3337902      1.23%     84.11% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  3515947      1.29%     85.40% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  4015286      1.48%     86.88% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  2680056      0.98%     87.86% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                 33046907     12.14%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                228914394     77.08%     77.08% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  5078121      1.71%     78.79% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  4142401      1.39%     80.18% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  4790312      1.61%     81.79% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  4897925      1.65%     83.44% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  5093198      1.71%     85.16% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  5344969      1.80%     86.96% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  4001055      1.35%     88.30% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 34736188     11.70%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            272218372                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.066178                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.735685                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 35961276                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             167476538                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  44947862                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               8659583                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles               15173113                       # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts              347461862                       # Number of instructions handled by decode
-system.cpu.rename.SquashCycles               15173113                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 42752504                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles               116485143                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles          31994                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  45803186                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              51972432                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              340800862                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                 21864                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents               45640903                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                6024783                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                 135945                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands           394811664                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             947446953                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        625588632                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups           4495188                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total            296998563                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.075364                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.838657                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 16354452                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             230786837                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  26168548                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              21835252                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                1853474                       # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts              359377278                       # Number of instructions handled by decode
+system.cpu.rename.SquashCycles                1853474                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 24140537                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles               162592213                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles          34818                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  38296584                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              70080937                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              350637562                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                 41127                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents               61846506                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                7943239                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents                 152837                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands           405833434                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             972943751                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        642292546                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups           4668888                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps             259429450                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                135382214                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts               2125                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts           2128                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  90643821                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             87211861                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            31146341                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads          61275223                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores         20328080                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  332778184                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                4631                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 263626408                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            192005                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined       111021931                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined    233004479                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved           3386                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     272218372                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.968437                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.359512                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                146403984                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts               2369                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts           2300                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                 128426201                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             89689525                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            32027647                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          63947531                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         21534219                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  341381240                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                5216                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 266882213                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued             74332                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       119621882                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined    250682367                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved           3971                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     296998563                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.898598                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.365381                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           146051537     53.65%     53.65% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            54756567     20.11%     73.77% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            34141482     12.54%     86.31% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            19064760      7.00%     93.31% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            11177424      4.11%     97.42% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             4331751      1.59%     99.01% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             1975514      0.73%     99.74% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7              583634      0.21%     99.95% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              135703      0.05%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           171353571     57.70%     57.70% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            54179431     18.24%     75.94% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            33564937     11.30%     87.24% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            19156299      6.45%     93.69% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            10836839      3.65%     97.34% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             4376133      1.47%     98.81% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             2240693      0.75%     99.57% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7              893448      0.30%     99.87% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              397212      0.13%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       272218372                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       296998563                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                  150028      5.32%      5.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%      5.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      5.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      5.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      5.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      5.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      5.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      5.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      5.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      5.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      5.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      5.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      5.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      5.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      5.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      5.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      5.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      5.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      5.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      5.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      5.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      5.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      5.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      5.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      5.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      5.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      5.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      5.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      5.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                2336090     82.83%     88.15% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                334182     11.85%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  240121      7.41%      7.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      7.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      7.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      7.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      7.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      7.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      7.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      7.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      7.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      7.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      7.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      7.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      7.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      7.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      7.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      7.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      7.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      7.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      7.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      7.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      7.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      7.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      7.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      7.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      7.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      7.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      7.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      7.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      7.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                2588686     79.93%     87.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                410086     12.66%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass           1210869      0.46%      0.46% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             164756015     62.50%     62.96% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult               789411      0.30%     63.25% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv               7036440      2.67%     65.92% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd             1209865      0.46%     66.38% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     66.38% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     66.38% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     66.38% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     66.38% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     66.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     66.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     66.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     66.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     66.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     66.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     66.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     66.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     66.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     66.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     66.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     66.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     66.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     66.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     66.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     66.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     66.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     66.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     66.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     66.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     66.38% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             65957948     25.02%     91.40% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            22665860      8.60%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass           1211280      0.45%      0.45% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             167297217     62.69%     63.14% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult               790659      0.30%     63.44% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv               7035808      2.64%     66.07% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd             1214833      0.46%     66.53% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     66.53% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     66.53% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     66.53% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     66.53% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     66.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     66.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     66.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     66.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     66.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     66.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     66.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     66.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     66.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     66.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     66.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     66.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     66.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     66.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     66.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     66.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     66.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     66.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     66.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     66.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     66.53% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             66531787     24.93%     91.46% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            22800629      8.54%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              263626408                       # Type of FU issued
-system.cpu.iq.rate                           0.903372                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     2820300                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.010698                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          797512450                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         440004694                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    258018761                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads             4971043                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes            4096196                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses      2387913                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              262734744                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                 2501095                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads         18875446                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              266882213                       # Type of FU issued
+system.cpu.iq.rate                           0.898067                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     3238893                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.012136                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          829077263                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         457002634                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    260953197                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads             4998951                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes            4330787                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses      2399211                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              266394178                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                 2515648                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads         18924906                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads     30562274                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        18312                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation       301481                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores     10630624                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads     33039938                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        13805                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation       330906                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores     11511930                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads        50310                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked             1                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads        51585                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked            19                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles               15173113                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                84276429                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles               5906270                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           332782815                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            102069                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              87211861                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             31146341                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts               2037                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                2851984                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                388220                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents         301481                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         659051                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       922496                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              1581547                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             261729032                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              65162827                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           1897376                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                1853474                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles               126194753                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles               5535533                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           341386456                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            110817                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts              89689525                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             32027647                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts               2236                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                2225894                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                376853                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents         330906                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         685400                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       928719                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              1614119                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             264771892                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              65665679                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           2110321                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                             0                       # number of nop insts executed
-system.cpu.iew.exec_refs                     87627279                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 14424837                       # Number of branches executed
-system.cpu.iew.exec_stores                   22464452                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.896870                       # Inst execution rate
-system.cpu.iew.wb_sent                      261068756                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     260406674                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 208884231                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 374053492                       # num instructions consuming a value
+system.cpu.iew.exec_refs                     88263450                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 14588563                       # Number of branches executed
+system.cpu.iew.exec_stores                   22597771                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.890965                       # Inst execution rate
+system.cpu.iew.wb_sent                      264070010                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     263352408                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 208938306                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 376948521                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.892339                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.558434                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       0.886189                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.554289                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts       111590930                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts       120072652                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls            1245                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts           1527972                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    257045259                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.861184                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.643795                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts           1559859                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    280678389                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.788673                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.596070                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    157102684     61.12%     61.12% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     57671303     22.44%     83.55% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     14254075      5.55%     89.10% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     12075323      4.70%     93.80% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      4232227      1.65%     95.44% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      2930251      1.14%     96.58% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6       914346      0.36%     96.94% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      1028677      0.40%     97.34% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      6836373      2.66%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    180909203     64.45%     64.45% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     57692004     20.55%     85.01% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     14189338      5.06%     90.06% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     11904368      4.24%     94.31% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      4187159      1.49%     95.80% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      2885597      1.03%     96.83% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6       913299      0.33%     97.15% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      1056183      0.38%     97.53% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      6941238      2.47%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    257045259                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    280678389                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts            132071192                       # Number of instructions committed
 system.cpu.commit.committedOps              221363384                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -533,241 +534,241 @@ system.cpu.commit.op_class_0::MemWrite       20515717      9.27%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total         221363384                       # Class of committed instruction
-system.cpu.commit.bw_lim_events               6836373                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events               6941238                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                    583163200                       # The number of ROB reads
-system.cpu.rob.rob_writes                   681115892                       # The number of ROB writes
-system.cpu.timesIdled                         5968247                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                        19606405                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads                    615173187                       # The number of ROB reads
+system.cpu.rob.rob_writes                   699236981                       # The number of ROB writes
+system.cpu.timesIdled                            3132                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                          175617                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                   132071192                       # Number of Instructions Simulated
 system.cpu.committedOps                     221363384                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               2.209602                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         2.209602                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.452570                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.452570                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                453845201                       # number of integer regfile reads
-system.cpu.int_regfile_writes               236601026                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                   3267567                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                  2048085                       # number of floating regfile writes
-system.cpu.cc_regfile_reads                 102937064                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                 59977801                       # number of cc regfile writes
-system.cpu.misc_regfile_reads               135125313                       # number of misc regfile reads
+system.cpu.cpi                               2.250106                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         2.250106                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.444424                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.444424                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                456530694                       # number of integer regfile reads
+system.cpu.int_regfile_writes               239288826                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                   3276715                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                  2059644                       # number of floating regfile writes
+system.cpu.cc_regfile_reads                 102986535                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                 60205049                       # number of cc regfile writes
+system.cpu.misc_regfile_reads               136896298                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                   1689                       # number of misc regfile writes
-system.cpu.toL2Bus.throughput                 4014617                       # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq           7586                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp          7585                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback           14                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq          208                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp          208                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq         1544                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp         1544                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        14042                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         4438                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total             18480                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       442624                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       129152                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total         571776                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus            571776                       # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus        13376                       # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy        4690000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.throughput                 4492019                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq           8845                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp          8844                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback           38                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq          353                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp          353                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq         1547                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp         1547                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        16361                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         4810                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total             21171                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       512128                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       132544                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total         644672                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus            644672                       # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus        22784                       # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy        5429500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy      11276499                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy      13138750                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy       3488206                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy       3605850                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu.icache.tags.replacements              4946                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1631.815497                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            23225438                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs              6919                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs           3356.762249                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements              6027                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1644.648933                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            26670487                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs              8006                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs           3331.312391                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1631.815497                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.796785                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.796785                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024         1973                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           90                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          175                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          771                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3          126                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4          811                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.963379                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          46476479                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         46476479                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     23225439                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        23225439                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      23225439                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         23225439                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     23225439                       # number of overall hits
-system.cpu.icache.overall_hits::total        23225439                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst         9238                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total          9238                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst         9238                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total           9238                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst         9238                       # number of overall misses
-system.cpu.icache.overall_misses::total          9238                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    372844498                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    372844498                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    372844498                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    372844498                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    372844498                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    372844498                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     23234677                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     23234677                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     23234677                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     23234677                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     23234677                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     23234677                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000398                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000398                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000398                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000398                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000398                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000398                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 40359.872050                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 40359.872050                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 40359.872050                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 40359.872050                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 40359.872050                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 40359.872050                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs         1450                       # number of cycles access was blocked
+system.cpu.icache.tags.occ_blocks::cpu.inst  1644.648933                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.803051                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.803051                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1979                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          102                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          191                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          791                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3          137                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4          758                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.966309                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses          53370822                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         53370822                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     26670487                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        26670487                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      26670487                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         26670487                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     26670487                       # number of overall hits
+system.cpu.icache.overall_hits::total        26670487                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst        10745                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total         10745                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst        10745                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total          10745                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst        10745                       # number of overall misses
+system.cpu.icache.overall_misses::total         10745                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    397133250                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    397133250                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    397133250                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    397133250                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    397133250                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    397133250                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     26681232                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     26681232                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     26681232                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     26681232                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     26681232                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     26681232                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000403                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000403                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000403                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000403                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000403                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000403                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36959.818520                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 36959.818520                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 36959.818520                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 36959.818520                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 36959.818520                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 36959.818520                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs         1215                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                16                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                29                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    90.625000                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    41.896552                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst         2112                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total         2112                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst         2112                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total         2112                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst         2112                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total         2112                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst         7126                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total         7126                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst         7126                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total         7126                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst         7126                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total         7126                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    278959750                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    278959750                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    278959750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    278959750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    278959750                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    278959750                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000307                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000307                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000307                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.000307                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000307                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.000307                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 39146.751333                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 39146.751333                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 39146.751333                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 39146.751333                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39146.751333                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 39146.751333                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         2386                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total         2386                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst         2386                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total         2386                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst         2386                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total         2386                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst         8359                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total         8359                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst         8359                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total         8359                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst         8359                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total         8359                       # number of overall MSHR misses
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+system.cpu.icache.overall_avg_mshr_miss_latency::total 35255.203972                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse         2576.667242                       # Cycle average of tags in use
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-system.cpu.l2cache.tags.avg_refs             0.925182                       # Average number of references to valid blocks.
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 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks     2.524275                       # Average occupied blocks per requestor
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-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.117065                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses            78525                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses           78525                       # Number of data accesses
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-system.cpu.l2cache.Writeback_hits::total           14                       # number of Writeback hits
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-system.cpu.l2cache.UpgradeReq_accesses::cpu.data          208                       # number of UpgradeReq accesses(hits+misses)
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-system.cpu.l2cache.overall_miss_rate::cpu.data     0.977545                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.601950                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69352.169452                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78012.440758                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 70305.635273                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 67338.158751                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67338.158751                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69352.169452                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69637.570189                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 69456.284916                       # average overall miss latency
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-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69637.570189                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 69456.284916                       # average overall miss latency
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+system.cpu.l2cache.tags.occ_blocks::cpu.inst  2327.129547                       # Average occupied blocks per requestor
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+system.cpu.l2cache.overall_miss_rate::total     0.546433                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68439.770148                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76514.602804                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 69314.271255                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 67462.956919                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67462.956919                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68439.770148                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69439.540816                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 68797.091539                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68439.770148                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69439.540816                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 68797.091539                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -776,175 +777,175 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3411                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          422                       # number of ReadReq MSHR misses
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-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data          207                       # number of UpgradeReq MSHR misses
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-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         1537                       # number of ReadExReq MSHR misses
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-system.cpu.l2cache.demand_mshr_misses::cpu.data         1959                       # number of demand (read+write) MSHR misses
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-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    193816250                       # number of ReadReq MSHR miss cycles
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-system.cpu.l2cache.ReadReq_mshr_miss_latency::total    221503500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data      2079206                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total      2079206                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     84212750                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     84212750                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    193816250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    111900000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    305716250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    193816250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    111900000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    305716250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.493133                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.917391                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.519588                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.995192                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.995192                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.995466                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.995466                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.493133                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.977545                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.601950                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.493133                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.977545                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.601950                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56820.946936                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65609.597156                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57788.546830                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10044.473430                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10044.473430                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54790.338321                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54790.338321                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56820.946936                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57120.980092                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56930.400372                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56820.946936                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57120.980092                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56930.400372                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3524                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          428                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total         3952                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data          350                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total          350                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         1532                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total         1532                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         3524                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data         1960                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total         5484                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         3524                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data         1960                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total         5484                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    197010750                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     27426750                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total    224437500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data      3500350                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total      3500350                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     84053250                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     84053250                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    197010750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    111480000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    308490750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    197010750                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    111480000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    308490750                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.440335                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.880658                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.465544                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.991501                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.991501                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.990304                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.990304                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.440335                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.964092                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.546433                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.440335                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.964092                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.546433                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55905.434166                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64081.191589                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56790.865385                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        10001                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        10001                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54865.045692                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54865.045692                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55905.434166                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 56877.551020                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56252.871991                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55905.434166                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 56877.551020                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56252.871991                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements                57                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          1440.781031                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            66638710                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs              2004                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs          33252.849301                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.replacements                91                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          1449.080763                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            67091510                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs              2033                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs          33001.234629                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  1440.781031                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.351753                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.351753                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024         1947                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           14                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1           34                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2           71                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3          428                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::4         1400                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024     0.475342                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         133284338                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        133284338                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     46124427                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        46124427                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     20513978                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       20513978                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data      66638405                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         66638405                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     66638405                       # number of overall hits
-system.cpu.dcache.overall_hits::total        66638405                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data         1009                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total          1009                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data         1753                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total         1753                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data         2762                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total           2762                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data         2762                       # number of overall misses
-system.cpu.dcache.overall_misses::total          2762                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data     63292597                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     63292597                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data    114179456                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total    114179456                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data    177472053                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total    177472053                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data    177472053                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total    177472053                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     46125436                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     46125436                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.tags.occ_blocks::cpu.data  1449.080763                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.353779                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.353779                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         1942                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           22                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           27                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           64                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3          432                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4         1397                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024     0.474121                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses         134190055                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        134190055                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     46577118                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        46577118                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     20513830                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       20513830                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data      67090948                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         67090948                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     67090948                       # number of overall hits
+system.cpu.dcache.overall_hits::total        67090948                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data         1162                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total          1162                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data         1901                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total         1901                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data         3063                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total           3063                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data         3063                       # number of overall misses
+system.cpu.dcache.overall_misses::total          3063                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data     64753959                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     64753959                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data    117721350                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total    117721350                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data    182475309                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total    182475309                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data    182475309                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total    182475309                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     46578280                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     46578280                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     20515731                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     20515731                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     66641167                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     66641167                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     66641167                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     66641167                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000022                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.000022                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000085                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.000085                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.000041                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.000041                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.000041                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.000041                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62728.044599                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 62728.044599                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65133.745579                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 65133.745579                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 64254.906951                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 64254.906951                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 64254.906951                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 64254.906951                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs           94                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                 2                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs           47                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.demand_accesses::cpu.data     67094011                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     67094011                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     67094011                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     67094011                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000025                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.000025                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000093                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.000093                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.000046                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.000046                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.000046                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.000046                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55726.298623                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 55726.298623                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61926.012625                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 61926.012625                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 59574.047992                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 59574.047992                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 59574.047992                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 59574.047992                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs          303                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets           50                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 5                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               1                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    60.600000                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets           50                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks           14                       # number of writebacks
-system.cpu.dcache.writebacks::total                14                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data          548                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total          548                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data            2                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total            2                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data          550                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total          550                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data          550                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total          550                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data          461                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total          461                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data         1751                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total         1751                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data         2212                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total         2212                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data         2212                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total         2212                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     33831000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total     33831000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    109893794                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total    109893794                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data    143724794                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total    143724794                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data    143724794                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total    143724794                       # number of overall MSHR miss cycles
+system.cpu.dcache.writebacks::writebacks           38                       # number of writebacks
+system.cpu.dcache.writebacks::total                38                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data          676                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total          676                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data            1                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total            1                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data          677                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total          677                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data          677                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total          677                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data          486                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total          486                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data         1900                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total         1900                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data         2386                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total         2386                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data         2386                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total         2386                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     33826250                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     33826250                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    113234400                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total    113234400                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data    147060650                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total    147060650                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data    147060650                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total    147060650                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000010                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000010                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000085                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000085                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000033                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.000033                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000033                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.000033                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 73386.117137                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 73386.117137                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62760.590520                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62760.590520                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 64975.042495                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 64975.042495                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 64975.042495                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 64975.042495                       # average overall mshr miss latency
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000093                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000093                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000036                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.000036                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000036                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.000036                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 69601.337449                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 69601.337449                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59597.052632                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59597.052632                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61634.807209                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 61634.807209                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61634.807209                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 61634.807209                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt
index 44f9ef01c..87d1939f2 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt
@@ -1,70 +1,73 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  1.870336                       # Number of seconds simulated
-sim_ticks                                1870335522500                       # Number of ticks simulated
-final_tick                               1870335522500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  1.870335                       # Number of seconds simulated
+sim_ticks                                1870335131500                       # Number of ticks simulated
+final_tick                               1870335131500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                2258331                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2258329                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            66881420828                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 346748                       # Number of bytes of host memory used
-host_seconds                                    27.97                       # Real time elapsed on the host
-sim_insts                                    63154034                       # Number of instructions simulated
-sim_ops                                      63154034                       # Number of ops (including micro ops) simulated
+host_inst_rate                                1824221                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1824220                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            54024573563                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 318368                       # Number of bytes of host memory used
+host_seconds                                    34.62                       # Real time elapsed on the host
+sim_insts                                    63154606                       # Number of instructions simulated
+sim_ops                                      63154606                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu0.inst           761216                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data         66693056                       # Number of bytes read from this memory
-system.physmem.bytes_read::tsunami.ide        2649600                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst           761088                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data         66705472                       # Number of bytes read from this memory
+system.physmem.bytes_read::tsunami.ide            960                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu1.inst           110976                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data           668672                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             70883520                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       761216                       # Number of instructions bytes read from this memory
+system.physmem.bytes_read::cpu1.data           674112                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             68252608                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       761088                       # Number of instructions bytes read from this memory
 system.physmem.bytes_inst_read::cpu1.inst       110976                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          872192                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7861504                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7861504                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.inst             11894                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data           1042079                       # Number of read requests responded to by this memory
-system.physmem.num_reads::tsunami.ide           41400                       # Number of read requests responded to by this memory
+system.physmem.bytes_inst_read::total          872064                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      5204096                       # Number of bytes written to this memory
+system.physmem.bytes_written::tsunami.ide      2659328                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7863424                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.inst             11892                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data           1042273                       # Number of read requests responded to by this memory
+system.physmem.num_reads::tsunami.ide              15                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu1.inst              1734                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data             10448                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1107555                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          122836                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               122836                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.inst              406994                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data            35658338                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::tsunami.ide           1416644                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_reads::cpu1.data             10533                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               1066447                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           81314                       # Number of write requests responded to by this memory
+system.physmem.num_writes::tsunami.ide          41552                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               122866                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.inst              406926                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data            35664984                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::tsunami.ide               513                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu1.inst               59335                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              357514                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                37898826                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         406994                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              360423                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                36492181                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         406926                       # Instruction read bandwidth from this memory (bytes/s)
 system.physmem.bw_inst_read::cpu1.inst          59335                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             466329                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           4203259                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                4203259                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           4203259                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             406994                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data           35658338                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::tsunami.ide          1416644                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_inst_read::total             466261                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           2782440                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::tsunami.ide          1421846                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                4204286                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           2782440                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             406926                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data           35664984                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::tsunami.ide          1422359                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu1.inst              59335                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             357514                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               42102084                       # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput                     42160248                       # Throughput (bytes/s)
-system.membus.data_through_bus               78853810                       # Total data (bytes)
+system.physmem.bw_total::cpu1.data             360423                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               40696467                       # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput                     40739369                       # Throughput (bytes/s)
+system.membus.data_through_bus               76196274                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.l2c.tags.replacements                  1000626                       # number of replacements
-system.l2c.tags.tagsinuse                65381.922680                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    2464737                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                  1065768                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                     2.312639                       # Average number of references to valid blocks.
+system.l2c.tags.replacements                  1000624                       # number of replacements
+system.l2c.tags.tagsinuse                65381.923240                       # Cycle average of tags in use
+system.l2c.tags.total_refs                    2464778                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                  1065766                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                     2.312682                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle                838081000                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   56158.702580                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     4894.236968                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     4134.601551                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst      174.423287                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data       19.958294                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::writebacks   56158.686870                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     4894.230886                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     4134.623273                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst      174.423683                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data       19.958527                       # Average occupied blocks per requestor
 system.l2c.tags.occ_percent::writebacks      0.856914                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu0.inst       0.074680                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu0.data       0.063089                       # Average percentage of cache occupancy
@@ -75,42 +78,42 @@ system.l2c.tags.occ_task_id_blocks::1024        65142                       # Oc
 system.l2c.tags.age_task_id_blocks_1024::0          769                       # Occupied blocks per task id
 system.l2c.tags.age_task_id_blocks_1024::1         3264                       # Occupied blocks per task id
 system.l2c.tags.age_task_id_blocks_1024::2         6912                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         6232                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        47965                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3         6213                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        47984                       # Occupied blocks per task id
 system.l2c.tags.occ_task_id_percent::1024     0.993988                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                 32109442                       # Number of tag accesses
-system.l2c.tags.data_accesses                32109442                       # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.inst             873086                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data             763077                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst             101896                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data              36734                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                1774793                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks          816653                       # number of Writeback hits
-system.l2c.Writeback_hits::total               816653                       # number of Writeback hits
+system.l2c.tags.tag_accesses                 32109770                       # Number of tag accesses
+system.l2c.tags.data_accesses                32109770                       # Number of data accesses
+system.l2c.ReadReq_hits::cpu0.inst             873092                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.data             763091                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.inst             101902                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.data              36740                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                1774825                       # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks          816663                       # number of Writeback hits
+system.l2c.Writeback_hits::total               816663                       # number of Writeback hits
 system.l2c.UpgradeReq_hits::cpu0.data             135                       # number of UpgradeReq hits
 system.l2c.UpgradeReq_hits::cpu1.data              37                       # number of UpgradeReq hits
 system.l2c.UpgradeReq_hits::total                 172                       # number of UpgradeReq hits
 system.l2c.SCUpgradeReq_hits::cpu0.data            14                       # number of SCUpgradeReq hits
 system.l2c.SCUpgradeReq_hits::cpu1.data             9                       # number of SCUpgradeReq hits
 system.l2c.SCUpgradeReq_hits::total                23                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data           166234                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data            14285                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               180519                       # number of ReadExReq hits
-system.l2c.demand_hits::cpu0.inst              873086                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data              929311                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst              101896                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data               51019                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 1955312                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.inst             873086                       # number of overall hits
-system.l2c.overall_hits::cpu0.data             929311                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst             101896                       # number of overall hits
-system.l2c.overall_hits::cpu1.data              51019                       # number of overall hits
-system.l2c.overall_hits::total                1955312                       # number of overall hits
-system.l2c.ReadReq_misses::cpu0.inst            11894                       # number of ReadReq misses
+system.l2c.ReadExReq_hits::cpu0.data           166232                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data            14288                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               180520                       # number of ReadExReq hits
+system.l2c.demand_hits::cpu0.inst              873092                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data              929323                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst              101902                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data               51028                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                 1955345                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.inst             873092                       # number of overall hits
+system.l2c.overall_hits::cpu0.data             929323                       # number of overall hits
+system.l2c.overall_hits::cpu1.inst             101902                       # number of overall hits
+system.l2c.overall_hits::cpu1.data              51028                       # number of overall hits
+system.l2c.overall_hits::total                1955345                       # number of overall hits
+system.l2c.ReadReq_misses::cpu0.inst            11892                       # number of ReadReq misses
 system.l2c.ReadReq_misses::cpu0.data           926761                       # number of ReadReq misses
 system.l2c.ReadReq_misses::cpu1.inst             1734                       # number of ReadReq misses
 system.l2c.ReadReq_misses::cpu1.data              908                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total               941297                       # number of ReadReq misses
+system.l2c.ReadReq_misses::total               941295                       # number of ReadReq misses
 system.l2c.UpgradeReq_misses::cpu0.data          2442                       # number of UpgradeReq misses
 system.l2c.UpgradeReq_misses::cpu1.data           570                       # number of UpgradeReq misses
 system.l2c.UpgradeReq_misses::total              3012                       # number of UpgradeReq misses
@@ -120,66 +123,66 @@ system.l2c.SCUpgradeReq_misses::total             165                       # nu
 system.l2c.ReadExReq_misses::cpu0.data         115706                       # number of ReadExReq misses
 system.l2c.ReadExReq_misses::cpu1.data           9662                       # number of ReadExReq misses
 system.l2c.ReadExReq_misses::total             125368                       # number of ReadExReq misses
-system.l2c.demand_misses::cpu0.inst             11894                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.inst             11892                       # number of demand (read+write) misses
 system.l2c.demand_misses::cpu0.data           1042467                       # number of demand (read+write) misses
 system.l2c.demand_misses::cpu1.inst              1734                       # number of demand (read+write) misses
 system.l2c.demand_misses::cpu1.data             10570                       # number of demand (read+write) misses
-system.l2c.demand_misses::total               1066665                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.inst            11894                       # number of overall misses
+system.l2c.demand_misses::total               1066663                       # number of demand (read+write) misses
+system.l2c.overall_misses::cpu0.inst            11892                       # number of overall misses
 system.l2c.overall_misses::cpu0.data          1042467                       # number of overall misses
 system.l2c.overall_misses::cpu1.inst             1734                       # number of overall misses
 system.l2c.overall_misses::cpu1.data            10570                       # number of overall misses
-system.l2c.overall_misses::total              1066665                       # number of overall misses
-system.l2c.ReadReq_accesses::cpu0.inst         884980                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.data        1689838                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.inst         103630                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.data          37642                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total            2716090                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks       816653                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total           816653                       # number of Writeback accesses(hits+misses)
+system.l2c.overall_misses::total              1066663                       # number of overall misses
+system.l2c.ReadReq_accesses::cpu0.inst         884984                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.data        1689852                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.inst         103636                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.data          37648                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total            2716120                       # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks       816663                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total           816663                       # number of Writeback accesses(hits+misses)
 system.l2c.UpgradeReq_accesses::cpu0.data         2577                       # number of UpgradeReq accesses(hits+misses)
 system.l2c.UpgradeReq_accesses::cpu1.data          607                       # number of UpgradeReq accesses(hits+misses)
 system.l2c.UpgradeReq_accesses::total            3184                       # number of UpgradeReq accesses(hits+misses)
 system.l2c.SCUpgradeReq_accesses::cpu0.data           79                       # number of SCUpgradeReq accesses(hits+misses)
 system.l2c.SCUpgradeReq_accesses::cpu1.data          109                       # number of SCUpgradeReq accesses(hits+misses)
 system.l2c.SCUpgradeReq_accesses::total           188                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data       281940                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data        23947                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           305887                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.inst          884980                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data         1971778                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst          103630                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data           61589                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             3021977                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst         884980                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data        1971778                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst         103630                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data          61589                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            3021977                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst      0.013440                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data      0.548432                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst      0.016733                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data      0.024122                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.346563                       # miss rate for ReadReq accesses
+system.l2c.ReadExReq_accesses::cpu0.data       281938                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data        23950                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           305888                       # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.inst          884984                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data         1971790                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst          103636                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data           61598                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total             3022008                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst         884984                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data        1971790                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst         103636                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data          61598                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            3022008                       # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu0.inst      0.013438                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.data      0.548427                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.inst      0.016732                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.data      0.024118                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.346559                       # miss rate for ReadReq accesses
 system.l2c.UpgradeReq_miss_rate::cpu0.data     0.947614                       # miss rate for UpgradeReq accesses
 system.l2c.UpgradeReq_miss_rate::cpu1.data     0.939044                       # miss rate for UpgradeReq accesses
 system.l2c.UpgradeReq_miss_rate::total       0.945980                       # miss rate for UpgradeReq accesses
 system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.822785                       # miss rate for SCUpgradeReq accesses
 system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.917431                       # miss rate for SCUpgradeReq accesses
 system.l2c.SCUpgradeReq_miss_rate::total     0.877660                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.410392                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.403474                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.409851                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.013440                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.528694                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.016733                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.171622                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.352969                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.013440                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.528694                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.016733                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.171622                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.352969                       # miss rate for overall accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.410395                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.403424                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.409849                       # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.013438                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.528691                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.016732                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.171596                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.352965                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.013438                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.528691                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.016732                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.171596                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.352965                       # miss rate for overall accesses
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -188,16 +191,16 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks               81316                       # number of writebacks
-system.l2c.writebacks::total                    81316                       # number of writebacks
+system.l2c.writebacks::writebacks               81314                       # number of writebacks
+system.l2c.writebacks::total                    81314                       # number of writebacks
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
 system.iocache.tags.replacements                41695                       # number of replacements
-system.iocache.tags.tagsinuse                0.435437                       # Cycle average of tags in use
+system.iocache.tags.tagsinuse                0.435433                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs                41711                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
 system.iocache.tags.warmup_cycle         1685787165017                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::tsunami.ide     0.435437                       # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::tsunami.ide     0.435433                       # Average occupied blocks per requestor
 system.iocache.tags.occ_percent::tsunami.ide     0.027215                       # Average percentage of cache occupancy
 system.iocache.tags.occ_percent::total       0.027215                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
@@ -205,26 +208,24 @@ system.iocache.tags.age_task_id_blocks_1023::2           16
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
 system.iocache.tags.tag_accesses               375543                       # Number of tag accesses
 system.iocache.tags.data_accesses              375543                       # Number of data accesses
+system.iocache.WriteInvalidateReq_hits::tsunami.ide        41552                       # number of WriteInvalidateReq hits
+system.iocache.WriteInvalidateReq_hits::total        41552                       # number of WriteInvalidateReq hits
 system.iocache.ReadReq_misses::tsunami.ide          175                       # number of ReadReq misses
 system.iocache.ReadReq_misses::total              175                       # number of ReadReq misses
-system.iocache.WriteReq_misses::tsunami.ide        41552                       # number of WriteReq misses
-system.iocache.WriteReq_misses::total           41552                       # number of WriteReq misses
-system.iocache.demand_misses::tsunami.ide        41727                       # number of demand (read+write) misses
-system.iocache.demand_misses::total             41727                       # number of demand (read+write) misses
-system.iocache.overall_misses::tsunami.ide        41727                       # number of overall misses
-system.iocache.overall_misses::total            41727                       # number of overall misses
+system.iocache.demand_misses::tsunami.ide          175                       # number of demand (read+write) misses
+system.iocache.demand_misses::total               175                       # number of demand (read+write) misses
+system.iocache.overall_misses::tsunami.ide          175                       # number of overall misses
+system.iocache.overall_misses::total              175                       # number of overall misses
 system.iocache.ReadReq_accesses::tsunami.ide          175                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            175                       # number of ReadReq accesses(hits+misses)
-system.iocache.WriteReq_accesses::tsunami.ide        41552                       # number of WriteReq accesses(hits+misses)
-system.iocache.WriteReq_accesses::total         41552                       # number of WriteReq accesses(hits+misses)
-system.iocache.demand_accesses::tsunami.ide        41727                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total           41727                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::tsunami.ide        41727                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total          41727                       # number of overall (read+write) accesses
+system.iocache.WriteInvalidateReq_accesses::tsunami.ide        41552                       # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::total        41552                       # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.demand_accesses::tsunami.ide          175                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total             175                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::tsunami.ide          175                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total            175                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
-system.iocache.WriteReq_miss_rate::tsunami.ide            1                       # miss rate for WriteReq accesses
-system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
 system.iocache.demand_miss_rate::tsunami.ide            1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
@@ -235,10 +236,8 @@ system.iocache.blocked::no_mshrs                    0                       # nu
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
 system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.fast_writes                          0                       # number of fast writes performed
+system.iocache.fast_writes                      41552                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.writebacks::writebacks           41520                       # number of writebacks
-system.iocache.writebacks::total                41520                       # number of writebacks
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
@@ -256,22 +255,22 @@ system.cpu0.dtb.fetch_hits                          0                       # IT
 system.cpu0.dtb.fetch_misses                        0                       # ITB misses
 system.cpu0.dtb.fetch_acv                           0                       # ITB acv
 system.cpu0.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu0.dtb.read_hits                     9154530                       # DTB read hits
+system.cpu0.dtb.read_hits                     9154569                       # DTB read hits
 system.cpu0.dtb.read_misses                      7079                       # DTB read misses
 system.cpu0.dtb.read_acv                          152                       # DTB read access violations
 system.cpu0.dtb.read_accesses                  508987                       # DTB read accesses
-system.cpu0.dtb.write_hits                    5936899                       # DTB write hits
+system.cpu0.dtb.write_hits                    5936918                       # DTB write hits
 system.cpu0.dtb.write_misses                      726                       # DTB write misses
 system.cpu0.dtb.write_acv                          99                       # DTB write access violations
 system.cpu0.dtb.write_accesses                 189050                       # DTB write accesses
-system.cpu0.dtb.data_hits                    15091429                       # DTB hits
+system.cpu0.dtb.data_hits                    15091487                       # DTB hits
 system.cpu0.dtb.data_misses                      7805                       # DTB misses
 system.cpu0.dtb.data_acv                          251                       # DTB access violations
 system.cpu0.dtb.data_accesses                  698037                       # DTB accesses
-system.cpu0.itb.fetch_hits                    3855556                       # ITB hits
+system.cpu0.itb.fetch_hits                    3855534                       # ITB hits
 system.cpu0.itb.fetch_misses                     3485                       # ITB misses
 system.cpu0.itb.fetch_acv                         127                       # ITB acv
-system.cpu0.itb.fetch_accesses                3859041                       # ITB accesses
+system.cpu0.itb.fetch_accesses                3859019                       # ITB accesses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.read_acv                            0                       # DTB read access violations
@@ -284,34 +283,34 @@ system.cpu0.itb.data_hits                           0                       # DT
 system.cpu0.itb.data_misses                         0                       # DTB misses
 system.cpu0.itb.data_acv                            0                       # DTB access violations
 system.cpu0.itb.data_accesses                       0                       # DTB accesses
-system.cpu0.numCycles                      3740671046                       # number of cpu cycles simulated
+system.cpu0.numCycles                      3740670264                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                   57222076                       # Number of instructions committed
-system.cpu0.committedOps                     57222076                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses             53249924                       # Number of integer alu accesses
+system.cpu0.committedInsts                   57222643                       # Number of instructions committed
+system.cpu0.committedOps                     57222643                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses             53250480                       # Number of integer alu accesses
 system.cpu0.num_fp_alu_accesses                299810                       # Number of float alu accesses
-system.cpu0.num_func_calls                    1399585                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts      6808233                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                    53249924                       # number of integer instructions
+system.cpu0.num_func_calls                    1399593                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts      6808341                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                    53250480                       # number of integer instructions
 system.cpu0.num_fp_insts                       299810                       # number of float instructions
-system.cpu0.num_int_register_reads           73318596                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes          39827534                       # number of times the integer registers were written
+system.cpu0.num_int_register_reads           73319539                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes          39827957                       # number of times the integer registers were written
 system.cpu0.num_fp_register_reads              147724                       # number of times the floating registers were read
 system.cpu0.num_fp_register_writes             150835                       # number of times the floating registers were written
-system.cpu0.num_mem_refs                     15135515                       # number of memory refs
-system.cpu0.num_load_insts                    9184477                       # Number of load instructions
-system.cpu0.num_store_insts                   5951038                       # Number of store instructions
-system.cpu0.num_idle_cycles              3683437200.584730                       # Number of idle cycles
-system.cpu0.num_busy_cycles              57233845.415270                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.015300                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.984700                       # Percentage of idle cycles
-system.cpu0.Branches                          8650704                       # Number of branches fetched
-system.cpu0.op_class::No_OpClass              3102513      5.42%      5.42% # Class of executed instruction
-system.cpu0.op_class::IntAlu                 37823162     66.09%     71.51% # Class of executed instruction
-system.cpu0.op_class::IntMult                   59490      0.10%     71.61% # Class of executed instruction
-system.cpu0.op_class::IntDiv                        0      0.00%     71.61% # Class of executed instruction
-system.cpu0.op_class::FloatAdd                  18488      0.03%     71.65% # Class of executed instruction
+system.cpu0.num_mem_refs                     15135573                       # number of memory refs
+system.cpu0.num_load_insts                    9184516                       # Number of load instructions
+system.cpu0.num_store_insts                   5951057                       # Number of store instructions
+system.cpu0.num_idle_cycles              3683435851.584730                       # Number of idle cycles
+system.cpu0.num_busy_cycles              57234412.415270                       # Number of busy cycles
+system.cpu0.not_idle_fraction                0.015301                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                    0.984699                       # Percentage of idle cycles
+system.cpu0.Branches                          8650822                       # Number of branches fetched
+system.cpu0.op_class::No_OpClass              3102524      5.42%      5.42% # Class of executed instruction
+system.cpu0.op_class::IntAlu                 37811313     66.07%     71.49% # Class of executed instruction
+system.cpu0.op_class::IntMult                   59497      0.10%     71.59% # Class of executed instruction
+system.cpu0.op_class::IntDiv                        0      0.00%     71.59% # Class of executed instruction
+system.cpu0.op_class::FloatAdd                  30844      0.05%     71.65% # Class of executed instruction
 system.cpu0.op_class::FloatCmp                      0      0.00%     71.65% # Class of executed instruction
 system.cpu0.op_class::FloatCvt                      0      0.00%     71.65% # Class of executed instruction
 system.cpu0.op_class::FloatMult                     0      0.00%     71.65% # Class of executed instruction
@@ -337,38 +336,38 @@ system.cpu0.op_class::SimdFloatMisc                 0      0.00%     71.65% # Cl
 system.cpu0.op_class::SimdFloatMult                 0      0.00%     71.65% # Class of executed instruction
 system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     71.65% # Class of executed instruction
 system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     71.65% # Class of executed instruction
-system.cpu0.op_class::MemRead                 9401052     16.43%     88.08% # Class of executed instruction
-system.cpu0.op_class::MemWrite                5956984     10.41%     98.49% # Class of executed instruction
-system.cpu0.op_class::IprAccess                866222      1.51%    100.00% # Class of executed instruction
+system.cpu0.op_class::MemRead                 9401091     16.43%     88.08% # Class of executed instruction
+system.cpu0.op_class::MemWrite                5957003     10.41%     98.49% # Class of executed instruction
+system.cpu0.op_class::IprAccess                866206      1.51%    100.00% # Class of executed instruction
 system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu0.op_class::total                  57230132                       # Class of executed instruction
+system.cpu0.op_class::total                  57230699                       # Class of executed instruction
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu0.kern.inst.quiesce                    6283                       # number of quiesce instructions executed
-system.cpu0.kern.inst.hwrei                    197120                       # number of hwrei instructions executed
+system.cpu0.kern.inst.hwrei                    197118                       # number of hwrei instructions executed
 system.cpu0.kern.ipl_count::0                   71004     40.60%     40.60% # number of times we switched to this ipl
 system.cpu0.kern.ipl_count::21                    243      0.14%     40.74% # number of times we switched to this ipl
 system.cpu0.kern.ipl_count::22                   1908      1.09%     41.83% # number of times we switched to this ipl
 system.cpu0.kern.ipl_count::30                      8      0.00%     41.84% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::31                 101705     58.16%    100.00% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::total              174868                       # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::31                 101703     58.16%    100.00% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::total              174866                       # number of times we switched to this ipl
 system.cpu0.kern.ipl_good::0                    69637     49.24%     49.24% # number of times we switched to this ipl from a different ipl
 system.cpu0.kern.ipl_good::21                     243      0.17%     49.41% # number of times we switched to this ipl from a different ipl
 system.cpu0.kern.ipl_good::22                    1908      1.35%     50.76% # number of times we switched to this ipl from a different ipl
 system.cpu0.kern.ipl_good::30                       8      0.01%     50.77% # number of times we switched to this ipl from a different ipl
 system.cpu0.kern.ipl_good::31                   69629     49.23%    100.00% # number of times we switched to this ipl from a different ipl
 system.cpu0.kern.ipl_good::total               141425                       # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_ticks::0            1852989766500     99.07%     99.07% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::0            1852989089000     99.07%     99.07% # number of cycles we spent at this ipl
 system.cpu0.kern.ipl_ticks::21               20110000      0.00%     99.07% # number of cycles we spent at this ipl
 system.cpu0.kern.ipl_ticks::22               82044000      0.00%     99.08% # number of cycles we spent at this ipl
 system.cpu0.kern.ipl_ticks::30                 949500      0.00%     99.08% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::31            17242445000      0.92%    100.00% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::total        1870335315000                       # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::31            17242731500      0.92%    100.00% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::total        1870334924000                       # number of cycles we spent at this ipl
 system.cpu0.kern.ipl_used::0                 0.980748                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::21                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::31                0.684617                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::total             0.808753                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used::31                0.684631                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used::total             0.808762                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.syscall::2                         6      2.65%      2.65% # number of syscalls executed
 system.cpu0.kern.syscall::3                        19      8.41%     11.06% # number of syscalls executed
 system.cpu0.kern.syscall::4                         2      0.88%     11.95% # number of syscalls executed
@@ -408,7 +407,7 @@ system.cpu0.kern.callpal::wrvptptr                  1      0.00%      0.06% # nu
 system.cpu0.kern.callpal::swpctx                 3762      2.05%      2.11% # number of callpals executed
 system.cpu0.kern.callpal::tbi                      38      0.02%      2.14% # number of callpals executed
 system.cpu0.kern.callpal::wrent                     7      0.00%      2.14% # number of callpals executed
-system.cpu0.kern.callpal::swpipl               168035     91.68%     93.82% # number of callpals executed
+system.cpu0.kern.callpal::swpipl               168033     91.68%     93.82% # number of callpals executed
 system.cpu0.kern.callpal::rdps                   6150      3.36%     97.17% # number of callpals executed
 system.cpu0.kern.callpal::wrkgp                     1      0.00%     97.17% # number of callpals executed
 system.cpu0.kern.callpal::wrusp                     3      0.00%     97.17% # number of callpals executed
@@ -417,19 +416,19 @@ system.cpu0.kern.callpal::whami                     2      0.00%     97.18% # nu
 system.cpu0.kern.callpal::rti                    4673      2.55%     99.73% # number of callpals executed
 system.cpu0.kern.callpal::callsys                 357      0.19%     99.92% # number of callpals executed
 system.cpu0.kern.callpal::imb                     142      0.08%    100.00% # number of callpals executed
-system.cpu0.kern.callpal::total                183291                       # number of callpals executed
+system.cpu0.kern.callpal::total                183289                       # number of callpals executed
 system.cpu0.kern.mode_switch::kernel             7091                       # number of protection mode switches
-system.cpu0.kern.mode_switch::user               1158                       # number of protection mode switches
+system.cpu0.kern.mode_switch::user               1156                       # number of protection mode switches
 system.cpu0.kern.mode_switch::idle                  0                       # number of protection mode switches
-system.cpu0.kern.mode_good::kernel               1157                      
-system.cpu0.kern.mode_good::user                 1158                      
+system.cpu0.kern.mode_good::kernel               1155                      
+system.cpu0.kern.mode_good::user                 1156                      
 system.cpu0.kern.mode_good::idle                    0                      
-system.cpu0.kern.mode_switch_good::kernel     0.163165                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good::kernel     0.162883                       # fraction of useful protection mode switches
 system.cpu0.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
 system.cpu0.kern.mode_switch_good::idle           nan                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good::total     0.280640                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_ticks::kernel      1869378305000     99.95%     99.95% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks::user           957009000      0.05%    100.00% # number of ticks spent at the given mode
+system.cpu0.kern.mode_switch_good::total     0.280223                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_ticks::kernel      1869377924000     99.95%     99.95% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks::user           956999000      0.05%    100.00% # number of ticks spent at the given mode
 system.cpu0.kern.mode_ticks::idle                   0      0.00%    100.00% # number of ticks spent at the given mode
 system.cpu0.kern.swap_context                    3763                       # number of times the context was actually changed
 system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
@@ -463,18 +462,18 @@ system.tsunami.ethernet.totalRxOrn                  0                       # to
 system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
 system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
 system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
-system.toL2Bus.throughput                   131930255                       # Throughput (bytes/s)
-system.toL2Bus.data_through_bus             246743474                       # Total data (bytes)
-system.toL2Bus.snoop_data_through_bus           10368                       # Total snoop data (bytes)
+system.toL2Bus.throughput                   133353257                       # Throughput (bytes/s)
+system.toL2Bus.data_through_bus             246745714                       # Total data (bytes)
+system.toL2Bus.snoop_data_through_bus         2669568                       # Total snoop data (bytes)
 system.iobus.throughput                       1460501                       # Throughput (bytes/s)
 system.iobus.data_through_bus                 2731626                       # Total data (bytes)
-system.cpu0.icache.tags.replacements           884404                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.244754                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs           56345132                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs           884916                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            63.672859                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.replacements           884408                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.244752                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs           56345695                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs           884920                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            63.673208                       # Average number of references to valid blocks.
 system.cpu0.icache.tags.warmup_cycle       9786576500                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.244754                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.244752                       # Average occupied blocks per requestor
 system.cpu0.icache.tags.occ_percent::cpu0.inst     0.998525                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_percent::total     0.998525                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
@@ -482,26 +481,26 @@ system.cpu0.icache.tags.age_task_id_blocks_1024::0           59
 system.cpu0.icache.tags.age_task_id_blocks_1024::1          108                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::2          345                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses         58115132                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses        58115132                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst     56345132                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total       56345132                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst     56345132                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total        56345132                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst     56345132                       # number of overall hits
-system.cpu0.icache.overall_hits::total       56345132                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst       885000                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total       885000                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst       885000                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total        885000                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst       885000                       # number of overall misses
-system.cpu0.icache.overall_misses::total       885000                       # number of overall misses
-system.cpu0.icache.ReadReq_accesses::cpu0.inst     57230132                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total     57230132                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst     57230132                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total     57230132                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst     57230132                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total     57230132                       # number of overall (read+write) accesses
+system.cpu0.icache.tags.tag_accesses         58115703                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses        58115703                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst     56345695                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total       56345695                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst     56345695                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total        56345695                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst     56345695                       # number of overall hits
+system.cpu0.icache.overall_hits::total       56345695                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst       885004                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total       885004                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst       885004                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total        885004                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst       885004                       # number of overall misses
+system.cpu0.icache.overall_misses::total       885004                       # number of overall misses
+system.cpu0.icache.ReadReq_accesses::cpu0.inst     57230699                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total     57230699                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst     57230699                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total     57230699                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst     57230699                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total     57230699                       # number of overall (read+write) accesses
 system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.015464                       # miss rate for ReadReq accesses
 system.cpu0.icache.ReadReq_miss_rate::total     0.015464                       # miss rate for ReadReq accesses
 system.cpu0.icache.demand_miss_rate::cpu0.inst     0.015464                       # miss rate for demand accesses
@@ -517,13 +516,13 @@ system.cpu0.icache.avg_blocked_cycles::no_targets          nan
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.dcache.tags.replacements          1978686                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          507.129778                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           13123753                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs          1979198                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs             6.630844                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.replacements          1978697                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          507.129647                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs           13123800                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs          1979209                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs             6.630831                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle         10840000                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   507.129778                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   507.129647                       # Average occupied blocks per requestor
 system.cpu0.dcache.tags.occ_percent::cpu0.data     0.990488                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_percent::total     0.990488                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
@@ -531,44 +530,44 @@ system.cpu0.dcache.tags.age_task_id_blocks_1024::0          443
 system.cpu0.dcache.tags.age_task_id_blocks_1024::1           65                       # Occupied blocks per task id
 system.cpu0.dcache.tags.age_task_id_blocks_1024::2            4                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses         62404072                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses        62404072                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data      7298337                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total        7298337                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data      5462263                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total       5462263                       # number of WriteReq hits
+system.cpu0.dcache.tags.tag_accesses         62404315                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses        62404315                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data      7298365                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total        7298365                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data      5462282                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total       5462282                       # number of WriteReq hits
 system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       172144                       # number of LoadLockedReq hits
 system.cpu0.dcache.LoadLockedReq_hits::total       172144                       # number of LoadLockedReq hits
 system.cpu0.dcache.StoreCondReq_hits::cpu0.data       186624                       # number of StoreCondReq hits
 system.cpu0.dcache.StoreCondReq_hits::total       186624                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data     12760600                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        12760600                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data     12760600                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       12760600                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data      1683332                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total      1683332                       # number of ReadReq misses
+system.cpu0.dcache.demand_hits::cpu0.data     12760647                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total        12760647                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data     12760647                       # number of overall hits
+system.cpu0.dcache.overall_hits::total       12760647                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data      1683343                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total      1683343                       # number of ReadReq misses
 system.cpu0.dcache.WriteReq_misses::cpu0.data       285998                       # number of WriteReq misses
 system.cpu0.dcache.WriteReq_misses::total       285998                       # number of WriteReq misses
 system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        16153                       # number of LoadLockedReq misses
 system.cpu0.dcache.LoadLockedReq_misses::total        16153                       # number of LoadLockedReq misses
 system.cpu0.dcache.StoreCondReq_misses::cpu0.data          714                       # number of StoreCondReq misses
 system.cpu0.dcache.StoreCondReq_misses::total          714                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data      1969330                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       1969330                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data      1969330                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      1969330                       # number of overall misses
-system.cpu0.dcache.ReadReq_accesses::cpu0.data      8981669                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total      8981669                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data      5748261                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total      5748261                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.demand_misses::cpu0.data      1969341                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total       1969341                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data      1969341                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      1969341                       # number of overall misses
+system.cpu0.dcache.ReadReq_accesses::cpu0.data      8981708                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total      8981708                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data      5748280                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total      5748280                       # number of WriteReq accesses(hits+misses)
 system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       188297                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu0.dcache.LoadLockedReq_accesses::total       188297                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       187338                       # number of StoreCondReq accesses(hits+misses)
 system.cpu0.dcache.StoreCondReq_accesses::total       187338                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data     14729930                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     14729930                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data     14729930                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     14729930                       # number of overall (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu0.data     14729988                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     14729988                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data     14729988                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     14729988                       # number of overall (read+write) accesses
 system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.187419                       # miss rate for ReadReq accesses
 system.cpu0.dcache.ReadReq_miss_rate::total     0.187419                       # miss rate for ReadReq accesses
 system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.049754                       # miss rate for WriteReq accesses
@@ -589,8 +588,8 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       775641                       # number of writebacks
-system.cpu0.dcache.writebacks::total           775641                       # number of writebacks
+system.cpu0.dcache.writebacks::writebacks       775643                       # number of writebacks
+system.cpu0.dcache.writebacks::total           775643                       # number of writebacks
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.dtb.fetch_hits                          0                       # ITB hits
 system.cpu1.dtb.fetch_misses                        0                       # ITB misses
@@ -624,34 +623,34 @@ system.cpu1.itb.data_hits                           0                       # DT
 system.cpu1.itb.data_misses                         0                       # DTB misses
 system.cpu1.itb.data_acv                            0                       # DTB access violations
 system.cpu1.itb.data_accesses                       0                       # DTB accesses
-system.cpu1.numCycles                      3740248881                       # number of cpu cycles simulated
+system.cpu1.numCycles                      3740248099                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                    5931958                       # Number of instructions committed
-system.cpu1.committedOps                      5931958                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses              5550578                       # Number of integer alu accesses
+system.cpu1.committedInsts                    5931963                       # Number of instructions committed
+system.cpu1.committedOps                      5931963                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses              5550581                       # Number of integer alu accesses
 system.cpu1.num_fp_alu_accesses                 28590                       # Number of float alu accesses
 system.cpu1.num_func_calls                     182742                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts       577190                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                     5550578                       # number of integer instructions
+system.cpu1.num_conditional_control_insts       577192                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                     5550581                       # number of integer instructions
 system.cpu1.num_fp_insts                        28590                       # number of float instructions
-system.cpu1.num_int_register_reads            7657288                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes           4163275                       # number of times the integer registers were written
+system.cpu1.num_int_register_reads            7657293                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes           4163277                       # number of times the integer registers were written
 system.cpu1.num_fp_register_reads               17889                       # number of times the floating registers were read
 system.cpu1.num_fp_register_writes              17683                       # number of times the floating registers were written
 system.cpu1.num_mem_refs                      1926244                       # number of memory refs
 system.cpu1.num_load_insts                    1170888                       # Number of load instructions
 system.cpu1.num_store_insts                    755356                       # Number of store instructions
-system.cpu1.num_idle_cycles              3734312190.077655                       # Number of idle cycles
-system.cpu1.num_busy_cycles              5936690.922345                       # Number of busy cycles
+system.cpu1.num_idle_cycles              3734311403.078359                       # Number of idle cycles
+system.cpu1.num_busy_cycles              5936695.921641                       # Number of busy cycles
 system.cpu1.not_idle_fraction                0.001587                       # Percentage of non-idle cycles
 system.cpu1.idle_fraction                    0.998413                       # Percentage of idle cycles
-system.cpu1.Branches                           836747                       # Number of branches fetched
+system.cpu1.Branches                           836749                       # Number of branches fetched
 system.cpu1.op_class::No_OpClass               239814      4.04%      4.04% # Class of executed instruction
-system.cpu1.op_class::IntAlu                  3533366     59.53%     63.57% # Class of executed instruction
+system.cpu1.op_class::IntAlu                  3533248     59.52%     63.56% # Class of executed instruction
 system.cpu1.op_class::IntMult                    9651      0.16%     63.73% # Class of executed instruction
 system.cpu1.op_class::IntDiv                        0      0.00%     63.73% # Class of executed instruction
-system.cpu1.op_class::FloatAdd                   7265      0.12%     63.85% # Class of executed instruction
+system.cpu1.op_class::FloatAdd                   7388      0.12%     63.85% # Class of executed instruction
 system.cpu1.op_class::FloatCmp                      0      0.00%     63.85% # Class of executed instruction
 system.cpu1.op_class::FloatCvt                      0      0.00%     63.85% # Class of executed instruction
 system.cpu1.op_class::FloatMult                     0      0.00%     63.85% # Class of executed instruction
@@ -681,9 +680,9 @@ system.cpu1.op_class::MemRead                 1191429     20.07%     83.95% # Cl
 system.cpu1.op_class::MemWrite                 755540     12.73%     96.68% # Class of executed instruction
 system.cpu1.op_class::IprAccess                197280      3.32%    100.00% # Class of executed instruction
 system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu1.op_class::total                   5935766                       # Class of executed instruction
+system.cpu1.op_class::total                   5935771                       # Class of executed instruction
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                    2204                       # number of quiesce instructions executed
+system.cpu1.kern.inst.quiesce                    2205                       # number of quiesce instructions executed
 system.cpu1.kern.inst.hwrei                     39554                       # number of hwrei instructions executed
 system.cpu1.kern.ipl_count::0                   10328     33.46%     33.46% # number of times we switched to this ipl
 system.cpu1.kern.ipl_count::22                   1907      6.18%     39.64% # number of times we switched to this ipl
@@ -695,11 +694,11 @@ system.cpu1.kern.ipl_good::22                    1907      8.46%     54.23% # nu
 system.cpu1.kern.ipl_good::30                     110      0.49%     54.72% # number of times we switched to this ipl from a different ipl
 system.cpu1.kern.ipl_good::31                   10208     45.28%    100.00% # number of times we switched to this ipl from a different ipl
 system.cpu1.kern.ipl_good::total                22543                       # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_ticks::0            1859123008500     99.41%     99.41% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::0            1859122617500     99.41%     99.41% # number of cycles we spent at this ipl
 system.cpu1.kern.ipl_ticks::22               82001000      0.00%     99.42% # number of cycles we spent at this ipl
 system.cpu1.kern.ipl_ticks::30               14064500      0.00%     99.42% # number of cycles we spent at this ipl
 system.cpu1.kern.ipl_ticks::31            10905353000      0.58%    100.00% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::total        1870124427000                       # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::total        1870124036000                       # number of cycles we spent at this ipl
 system.cpu1.kern.ipl_used::0                 0.999032                       # fraction of swpipl calls that actually changed the ipl
 system.cpu1.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu1.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
@@ -751,48 +750,48 @@ system.cpu1.kern.mode_switch_good::kernel     0.592449                       # f
 system.cpu1.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
 system.cpu1.kern.mode_switch_good::idle      0.015640                       # fraction of useful protection mode switches
 system.cpu1.kern.mode_switch_good::total     0.334518                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_ticks::kernel        1373917500      0.07%      0.07% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::kernel        1373909000      0.07%      0.07% # number of ticks spent at the given mode
 system.cpu1.kern.mode_ticks::user           508289000      0.03%      0.10% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::idle        1868002549000     99.90%    100.00% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::idle        1868002186500     99.90%    100.00% # number of ticks spent at the given mode
 system.cpu1.kern.swap_context                     471                       # number of times the context was actually changed
-system.cpu1.icache.tags.replacements           103091                       # number of replacements
-system.cpu1.icache.tags.tagsinuse          427.126317                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs            5832136                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs           103603                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs            56.293119                       # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle     1868933059000                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst   427.126317                       # Average occupied blocks per requestor
+system.cpu1.icache.tags.replacements           103097                       # number of replacements
+system.cpu1.icache.tags.tagsinuse          427.126315                       # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs            5832135                       # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs           103609                       # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs            56.289849                       # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle     1868932699000                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tags.occ_blocks::cpu1.inst   427.126315                       # Average occupied blocks per requestor
 system.cpu1.icache.tags.occ_percent::cpu1.inst     0.834231                       # Average percentage of cache occupancy
 system.cpu1.icache.tags.occ_percent::total     0.834231                       # Average percentage of cache occupancy
 system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu1.icache.tags.age_task_id_blocks_1024::2          512                       # Occupied blocks per task id
 system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses          6039396                       # Number of tag accesses
-system.cpu1.icache.tags.data_accesses         6039396                       # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst      5832136                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total        5832136                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst      5832136                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total         5832136                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst      5832136                       # number of overall hits
-system.cpu1.icache.overall_hits::total        5832136                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst       103630                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total       103630                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst       103630                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total        103630                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst       103630                       # number of overall misses
-system.cpu1.icache.overall_misses::total       103630                       # number of overall misses
-system.cpu1.icache.ReadReq_accesses::cpu1.inst      5935766                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total      5935766                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst      5935766                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total      5935766                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst      5935766                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total      5935766                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.017459                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.017459                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.017459                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.017459                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.017459                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.017459                       # miss rate for overall accesses
+system.cpu1.icache.tags.tag_accesses          6039407                       # Number of tag accesses
+system.cpu1.icache.tags.data_accesses         6039407                       # Number of data accesses
+system.cpu1.icache.ReadReq_hits::cpu1.inst      5832135                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total        5832135                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst      5832135                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total         5832135                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst      5832135                       # number of overall hits
+system.cpu1.icache.overall_hits::total        5832135                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst       103636                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total       103636                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst       103636                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total        103636                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst       103636                       # number of overall misses
+system.cpu1.icache.overall_misses::total       103636                       # number of overall misses
+system.cpu1.icache.ReadReq_accesses::cpu1.inst      5935771                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total      5935771                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst      5935771                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total      5935771                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst      5935771                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total      5935771                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.017460                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.017460                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.017460                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.017460                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.017460                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.017460                       # miss rate for overall accesses
 system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -802,45 +801,45 @@ system.cpu1.icache.avg_blocked_cycles::no_targets          nan
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.dcache.tags.replacements            62044                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse          421.562730                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs            1836054                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs            62382                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs            29.432432                       # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle     1851115552500                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data   421.562730                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data     0.823365                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total     0.823365                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.replacements            62047                       # number of replacements
+system.cpu1.dcache.tags.tagsinuse          421.558473                       # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs            1836050                       # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs            62385                       # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs            29.430953                       # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle     1851115162500                       # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.occ_blocks::cpu1.data   421.558473                       # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data     0.823356                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total     0.823356                       # Average percentage of cache occupancy
 system.cpu1.dcache.tags.occ_task_id_blocks::1024          338                       # Occupied blocks per task id
 system.cpu1.dcache.tags.age_task_id_blocks_1024::2          337                       # Occupied blocks per task id
 system.cpu1.dcache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
 system.cpu1.dcache.tags.occ_task_id_percent::1024     0.660156                       # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses          7735310                       # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses         7735310                       # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data      1109521                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total        1109521                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data       707457                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total        707457                       # number of WriteReq hits
+system.cpu1.dcache.tags.tag_accesses          7735314                       # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses         7735314                       # Number of data accesses
+system.cpu1.dcache.ReadReq_hits::cpu1.data      1109520                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total        1109520                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data       707454                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total        707454                       # number of WriteReq hits
 system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        15133                       # number of LoadLockedReq hits
 system.cpu1.dcache.LoadLockedReq_hits::total        15133                       # number of LoadLockedReq hits
 system.cpu1.dcache.StoreCondReq_hits::cpu1.data        15610                       # number of StoreCondReq hits
 system.cpu1.dcache.StoreCondReq_hits::total        15610                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data      1816978                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total         1816978                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data      1816978                       # number of overall hits
-system.cpu1.dcache.overall_hits::total        1816978                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data        41444                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total        41444                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data        25848                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total        25848                       # number of WriteReq misses
+system.cpu1.dcache.demand_hits::cpu1.data      1816974                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total         1816974                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data      1816974                       # number of overall hits
+system.cpu1.dcache.overall_hits::total        1816974                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data        41445                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total        41445                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data        25851                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total        25851                       # number of WriteReq misses
 system.cpu1.dcache.LoadLockedReq_misses::cpu1.data         1285                       # number of LoadLockedReq misses
 system.cpu1.dcache.LoadLockedReq_misses::total         1285                       # number of LoadLockedReq misses
 system.cpu1.dcache.StoreCondReq_misses::cpu1.data          735                       # number of StoreCondReq misses
 system.cpu1.dcache.StoreCondReq_misses::total          735                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data        67292                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total         67292                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data        67292                       # number of overall misses
-system.cpu1.dcache.overall_misses::total        67292                       # number of overall misses
+system.cpu1.dcache.demand_misses::cpu1.data        67296                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total         67296                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data        67296                       # number of overall misses
+system.cpu1.dcache.overall_misses::total        67296                       # number of overall misses
 system.cpu1.dcache.ReadReq_accesses::cpu1.data      1150965                       # number of ReadReq accesses(hits+misses)
 system.cpu1.dcache.ReadReq_accesses::total      1150965                       # number of ReadReq accesses(hits+misses)
 system.cpu1.dcache.WriteReq_accesses::cpu1.data       733305                       # number of WriteReq accesses(hits+misses)
@@ -853,18 +852,18 @@ system.cpu1.dcache.demand_accesses::cpu1.data      1884270
 system.cpu1.dcache.demand_accesses::total      1884270                       # number of demand (read+write) accesses
 system.cpu1.dcache.overall_accesses::cpu1.data      1884270                       # number of overall (read+write) accesses
 system.cpu1.dcache.overall_accesses::total      1884270                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.036008                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.036008                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.035249                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.035249                       # miss rate for WriteReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.036009                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.036009                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.035253                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.035253                       # miss rate for WriteReq accesses
 system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.078268                       # miss rate for LoadLockedReq accesses
 system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.078268                       # miss rate for LoadLockedReq accesses
 system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.044968                       # miss rate for StoreCondReq accesses
 system.cpu1.dcache.StoreCondReq_miss_rate::total     0.044968                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.035713                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.035713                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.035713                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.035713                       # miss rate for overall accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.035715                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.035715                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.035715                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.035715                       # miss rate for overall accesses
 system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -873,8 +872,8 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks        41012                       # number of writebacks
-system.cpu1.dcache.writebacks::total            41012                       # number of writebacks
+system.cpu1.dcache.writebacks::writebacks        41020                       # number of writebacks
+system.cpu1.dcache.writebacks::total            41020                       # number of writebacks
 system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt
index d987ad3fa..8a7bfd4c1 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt
@@ -1,55 +1,58 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  1.829332                       # Number of seconds simulated
-sim_ticks                                1829332258000                       # Number of ticks simulated
-final_tick                               1829332258000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                1829332049000                       # Number of ticks simulated
+final_tick                               1829332049000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                2367650                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2367648                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            72140813877                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 343680                       # Number of bytes of host memory used
-host_seconds                                    25.36                       # Real time elapsed on the host
-sim_insts                                    60038305                       # Number of instructions simulated
-sim_ops                                      60038305                       # Number of ops (including micro ops) simulated
+host_inst_rate                                2314619                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2314617                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            70524837278                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 315304                       # Number of bytes of host memory used
+host_seconds                                    25.94                       # Real time elapsed on the host
+sim_insts                                    60038433                       # Number of instructions simulated
+sim_ops                                      60038433                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst            857984                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          66839424                       # Number of bytes read from this memory
-system.physmem.bytes_read::tsunami.ide        2652288                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             70349696                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          66856384                       # Number of bytes read from this memory
+system.physmem.bytes_read::tsunami.ide            960                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             67715328                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read::cpu.inst       857984                       # Number of instructions bytes read from this memory
 system.physmem.bytes_inst_read::total          857984                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7411392                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7411392                       # Number of bytes written to this memory
+system.physmem.bytes_written::writebacks      4754240                       # Number of bytes written to this memory
+system.physmem.bytes_written::tsunami.ide      2659328                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7413568                       # Number of bytes written to this memory
 system.physmem.num_reads::cpu.inst              13406                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data            1044366                       # Number of read requests responded to by this memory
-system.physmem.num_reads::tsunami.ide           41442                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1099214                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          115803                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               115803                       # Number of write requests responded to by this memory
+system.physmem.num_reads::cpu.data            1044631                       # Number of read requests responded to by this memory
+system.physmem.num_reads::tsunami.ide              15                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               1058052                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           74285                       # Number of write requests responded to by this memory
+system.physmem.num_writes::tsunami.ide          41552                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               115837                       # Number of write requests responded to by this memory
 system.physmem.bw_read::cpu.inst               469015                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             36537607                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::tsunami.ide           1449867                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                38456489                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             36546883                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::tsunami.ide               525                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                37016422                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_inst_read::cpu.inst          469015                       # Instruction read bandwidth from this memory (bytes/s)
 system.physmem.bw_inst_read::total             469015                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           4051419                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                4051419                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           4051419                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::writebacks           2598894                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::tsunami.ide          1453715                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                4052609                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           2598894                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.inst              469015                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            36537607                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::tsunami.ide          1449867                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               42507908                       # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput                     42552540                       # Throughput (bytes/s)
-system.membus.data_through_bus               77842734                       # Total data (bytes)
+system.physmem.bw_total::cpu.data            36546883                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::tsunami.ide          1454240                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               41069032                       # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput                     41099809                       # Throughput (bytes/s)
+system.membus.data_through_bus               75185198                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
 system.iocache.tags.replacements                41686                       # number of replacements
-system.iocache.tags.tagsinuse                1.225570                       # Cycle average of tags in use
+system.iocache.tags.tagsinuse                1.225568                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs                41702                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
 system.iocache.tags.warmup_cycle         1685780659017                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::tsunami.ide     1.225570                       # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::tsunami.ide     1.225568                       # Average occupied blocks per requestor
 system.iocache.tags.occ_percent::tsunami.ide     0.076598                       # Average percentage of cache occupancy
 system.iocache.tags.occ_percent::total       0.076598                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
@@ -57,26 +60,24 @@ system.iocache.tags.age_task_id_blocks_1023::2           16
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
 system.iocache.tags.tag_accesses               375534                       # Number of tag accesses
 system.iocache.tags.data_accesses              375534                       # Number of data accesses
+system.iocache.WriteInvalidateReq_hits::tsunami.ide        41552                       # number of WriteInvalidateReq hits
+system.iocache.WriteInvalidateReq_hits::total        41552                       # number of WriteInvalidateReq hits
 system.iocache.ReadReq_misses::tsunami.ide          174                       # number of ReadReq misses
 system.iocache.ReadReq_misses::total              174                       # number of ReadReq misses
-system.iocache.WriteReq_misses::tsunami.ide        41552                       # number of WriteReq misses
-system.iocache.WriteReq_misses::total           41552                       # number of WriteReq misses
-system.iocache.demand_misses::tsunami.ide        41726                       # number of demand (read+write) misses
-system.iocache.demand_misses::total             41726                       # number of demand (read+write) misses
-system.iocache.overall_misses::tsunami.ide        41726                       # number of overall misses
-system.iocache.overall_misses::total            41726                       # number of overall misses
+system.iocache.demand_misses::tsunami.ide          174                       # number of demand (read+write) misses
+system.iocache.demand_misses::total               174                       # number of demand (read+write) misses
+system.iocache.overall_misses::tsunami.ide          174                       # number of overall misses
+system.iocache.overall_misses::total              174                       # number of overall misses
 system.iocache.ReadReq_accesses::tsunami.ide          174                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            174                       # number of ReadReq accesses(hits+misses)
-system.iocache.WriteReq_accesses::tsunami.ide        41552                       # number of WriteReq accesses(hits+misses)
-system.iocache.WriteReq_accesses::total         41552                       # number of WriteReq accesses(hits+misses)
-system.iocache.demand_accesses::tsunami.ide        41726                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total           41726                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::tsunami.ide        41726                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total          41726                       # number of overall (read+write) accesses
+system.iocache.WriteInvalidateReq_accesses::tsunami.ide        41552                       # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::total        41552                       # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.demand_accesses::tsunami.ide          174                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total             174                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::tsunami.ide          174                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total            174                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
-system.iocache.WriteReq_miss_rate::tsunami.ide            1                       # miss rate for WriteReq accesses
-system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
 system.iocache.demand_miss_rate::tsunami.ide            1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
@@ -87,10 +88,8 @@ system.iocache.blocked::no_mshrs                    0                       # nu
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
 system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.fast_writes                          0                       # number of fast writes performed
+system.iocache.fast_writes                      41552                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.writebacks::writebacks           41512                       # number of writebacks
-system.iocache.writebacks::total                41512                       # number of writebacks
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
@@ -109,7 +108,7 @@ system.cpu.dtb.fetch_hits                           0                       # IT
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                      9710427                       # DTB read hits
+system.cpu.dtb.read_hits                      9710428                       # DTB read hits
 system.cpu.dtb.read_misses                      10329                       # DTB read misses
 system.cpu.dtb.read_acv                           210                       # DTB read access violations
 system.cpu.dtb.read_accesses                   728856                       # DTB read accesses
@@ -117,14 +116,14 @@ system.cpu.dtb.write_hits                     6352498                       # DT
 system.cpu.dtb.write_misses                      1142                       # DTB write misses
 system.cpu.dtb.write_acv                          157                       # DTB write access violations
 system.cpu.dtb.write_accesses                  291931                       # DTB write accesses
-system.cpu.dtb.data_hits                     16062925                       # DTB hits
+system.cpu.dtb.data_hits                     16062926                       # DTB hits
 system.cpu.dtb.data_misses                      11471                       # DTB misses
 system.cpu.dtb.data_acv                           367                       # DTB access violations
 system.cpu.dtb.data_accesses                  1020787                       # DTB accesses
-system.cpu.itb.fetch_hits                     4974648                       # ITB hits
+system.cpu.itb.fetch_hits                     4974637                       # ITB hits
 system.cpu.itb.fetch_misses                      5006                       # ITB misses
 system.cpu.itb.fetch_acv                          184                       # ITB acv
-system.cpu.itb.fetch_accesses                 4979654                       # ITB accesses
+system.cpu.itb.fetch_accesses                 4979643                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -137,34 +136,34 @@ system.cpu.itb.data_hits                            0                       # DT
 system.cpu.itb.data_misses                          0                       # DTB misses
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
-system.cpu.numCycles                       3658664517                       # number of cpu cycles simulated
+system.cpu.numCycles                       3658664099                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                    60038305                       # Number of instructions committed
-system.cpu.committedOps                      60038305                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses              55913521                       # Number of integer alu accesses
+system.cpu.committedInsts                    60038433                       # Number of instructions committed
+system.cpu.committedOps                      60038433                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses              55913650                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                 324460                       # Number of float alu accesses
 system.cpu.num_func_calls                     1484182                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts      7110746                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                     55913521                       # number of integer instructions
+system.cpu.num_conditional_control_insts      7110776                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                     55913650                       # number of integer instructions
 system.cpu.num_fp_insts                        324460                       # number of float instructions
-system.cpu.num_int_register_reads            76953934                       # number of times the integer registers were read
-system.cpu.num_int_register_writes           41740225                       # number of times the integer registers were written
+system.cpu.num_int_register_reads            76954165                       # number of times the integer registers were read
+system.cpu.num_int_register_writes           41740323                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads               163642                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes              166520                       # number of times the floating registers were written
-system.cpu.num_mem_refs                      16115709                       # number of memory refs
-system.cpu.num_load_insts                     9747513                       # Number of load instructions
+system.cpu.num_mem_refs                      16115710                       # number of memory refs
+system.cpu.num_load_insts                     9747514                       # Number of load instructions
 system.cpu.num_store_insts                    6368196                       # Number of store instructions
-system.cpu.num_idle_cycles               3598609086.391618                       # Number of idle cycles
-system.cpu.num_busy_cycles               60055430.608382                       # Number of busy cycles
+system.cpu.num_idle_cycles               3598608539.425618                       # Number of idle cycles
+system.cpu.num_busy_cycles               60055559.574382                       # Number of busy cycles
 system.cpu.not_idle_fraction                 0.016415                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                     0.983585                       # Percentage of idle cycles
-system.cpu.Branches                           9064385                       # Number of branches fetched
-system.cpu.op_class::No_OpClass               3199104      5.33%      5.33% # Class of executed instruction
-system.cpu.op_class::IntAlu                  39460699     65.71%     71.04% # Class of executed instruction
-system.cpu.op_class::IntMult                    60680      0.10%     71.14% # Class of executed instruction
-system.cpu.op_class::IntDiv                         0      0.00%     71.14% # Class of executed instruction
-system.cpu.op_class::FloatAdd                   25609      0.04%     71.18% # Class of executed instruction
+system.cpu.Branches                           9064413                       # Number of branches fetched
+system.cpu.op_class::No_OpClass               3199106      5.33%      5.33% # Class of executed instruction
+system.cpu.op_class::IntAlu                  39448354     65.69%     71.02% # Class of executed instruction
+system.cpu.op_class::IntMult                    60680      0.10%     71.12% # Class of executed instruction
+system.cpu.op_class::IntDiv                         0      0.00%     71.12% # Class of executed instruction
+system.cpu.op_class::FloatAdd                   38087      0.06%     71.18% # Class of executed instruction
 system.cpu.op_class::FloatCmp                       0      0.00%     71.18% # Class of executed instruction
 system.cpu.op_class::FloatCvt                       0      0.00%     71.18% # Class of executed instruction
 system.cpu.op_class::FloatMult                      0      0.00%     71.18% # Class of executed instruction
@@ -190,34 +189,34 @@ system.cpu.op_class::SimdFloatMisc                  0      0.00%     71.19% # Cl
 system.cpu.op_class::SimdFloatMult                  0      0.00%     71.19% # Class of executed instruction
 system.cpu.op_class::SimdFloatMultAcc               0      0.00%     71.19% # Class of executed instruction
 system.cpu.op_class::SimdFloatSqrt                  0      0.00%     71.19% # Class of executed instruction
-system.cpu.op_class::MemRead                  9975081     16.61%     87.80% # Class of executed instruction
+system.cpu.op_class::MemRead                  9975082     16.61%     87.80% # Class of executed instruction
 system.cpu.op_class::MemWrite                 6374117     10.61%     98.42% # Class of executed instruction
-system.cpu.op_class::IprAccess                 951217      1.58%    100.00% # Class of executed instruction
+system.cpu.op_class::IprAccess                 951209      1.58%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::total                   60050143                       # Class of executed instruction
+system.cpu.op_class::total                   60050271                       # Class of executed instruction
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
 system.cpu.kern.inst.quiesce                     6357                       # number of quiesce instructions executed
-system.cpu.kern.inst.hwrei                     211319                       # number of hwrei instructions executed
+system.cpu.kern.inst.hwrei                     211318                       # number of hwrei instructions executed
 system.cpu.kern.ipl_count::0                    74830     40.99%     40.99% # number of times we switched to this ipl
 system.cpu.kern.ipl_count::21                     243      0.13%     41.12% # number of times we switched to this ipl
 system.cpu.kern.ipl_count::22                    1866      1.02%     42.14% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::31                  105623     57.86%    100.00% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::total               182562                       # number of times we switched to this ipl
+system.cpu.kern.ipl_count::31                  105622     57.86%    100.00% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::total               182561                       # number of times we switched to this ipl
 system.cpu.kern.ipl_good::0                     73463     49.29%     49.29% # number of times we switched to this ipl from a different ipl
 system.cpu.kern.ipl_good::21                      243      0.16%     49.46% # number of times we switched to this ipl from a different ipl
 system.cpu.kern.ipl_good::22                     1866      1.25%     50.71% # number of times we switched to this ipl from a different ipl
 system.cpu.kern.ipl_good::31                    73463     49.29%    100.00% # number of times we switched to this ipl from a different ipl
 system.cpu.kern.ipl_good::total                149035                       # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_ticks::0             1811927407500     99.05%     99.05% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::0             1811927133000     99.05%     99.05% # number of cycles we spent at this ipl
 system.cpu.kern.ipl_ticks::21                20110000      0.00%     99.05% # number of cycles we spent at this ipl
 system.cpu.kern.ipl_ticks::22                80238000      0.00%     99.05% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::31             17304295000      0.95%    100.00% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::total         1829332050500                       # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::31             17304360500      0.95%    100.00% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::total         1829331841500                       # number of cycles we spent at this ipl
 system.cpu.kern.ipl_used::0                  0.981732                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.ipl_used::21                        1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.ipl_used::22                        1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::31                 0.695521                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::total              0.816353                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used::31                 0.695527                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used::total              0.816357                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.syscall::2                          8      2.45%      2.45% # number of syscalls executed
 system.cpu.kern.syscall::3                         30      9.20%     11.66% # number of syscalls executed
 system.cpu.kern.syscall::4                          4      1.23%     12.88% # number of syscalls executed
@@ -256,7 +255,7 @@ system.cpu.kern.callpal::wrvptptr                   1      0.00%      0.00% # nu
 system.cpu.kern.callpal::swpctx                  4177      2.17%      2.18% # number of callpals executed
 system.cpu.kern.callpal::tbi                       54      0.03%      2.20% # number of callpals executed
 system.cpu.kern.callpal::wrent                      7      0.00%      2.21% # number of callpals executed
-system.cpu.kern.callpal::swpipl                175249     91.19%     93.40% # number of callpals executed
+system.cpu.kern.callpal::swpipl                175248     91.19%     93.40% # number of callpals executed
 system.cpu.kern.callpal::rdps                    6771      3.52%     96.92% # number of callpals executed
 system.cpu.kern.callpal::wrkgp                      1      0.00%     96.92% # number of callpals executed
 system.cpu.kern.callpal::wrusp                      7      0.00%     96.92% # number of callpals executed
@@ -265,20 +264,20 @@ system.cpu.kern.callpal::whami                      2      0.00%     96.93% # nu
 system.cpu.kern.callpal::rti                     5203      2.71%     99.64% # number of callpals executed
 system.cpu.kern.callpal::callsys                  515      0.27%     99.91% # number of callpals executed
 system.cpu.kern.callpal::imb                      181      0.09%    100.00% # number of callpals executed
-system.cpu.kern.callpal::total                 192180                       # number of callpals executed
+system.cpu.kern.callpal::total                 192179                       # number of callpals executed
 system.cpu.kern.mode_switch::kernel              5949                       # number of protection mode switches
-system.cpu.kern.mode_switch::user                1738                       # number of protection mode switches
+system.cpu.kern.mode_switch::user                1737                       # number of protection mode switches
 system.cpu.kern.mode_switch::idle                2097                       # number of protection mode switches
-system.cpu.kern.mode_good::kernel                1909                      
-system.cpu.kern.mode_good::user                  1738                      
+system.cpu.kern.mode_good::kernel                1908                      
+system.cpu.kern.mode_good::user                  1737                      
 system.cpu.kern.mode_good::idle                   171                      
-system.cpu.kern.mode_switch_good::kernel     0.320894                       # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good::kernel     0.320726                       # fraction of useful protection mode switches
 system.cpu.kern.mode_switch_good::user              1                       # fraction of useful protection mode switches
 system.cpu.kern.mode_switch_good::idle       0.081545                       # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::total      0.390229                       # fraction of useful protection mode switches
-system.cpu.kern.mode_ticks::kernel        26834202500      1.47%      1.47% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::user           1465074000      0.08%      1.55% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::idle         1801032773000     98.45%    100.00% # number of ticks spent at the given mode
+system.cpu.kern.mode_switch_good::total      0.390064                       # fraction of useful protection mode switches
+system.cpu.kern.mode_ticks::kernel        26834199500      1.47%      1.47% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::user           1465069000      0.08%      1.55% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::idle         1801032572000     98.45%    100.00% # number of ticks spent at the given mode
 system.cpu.kern.swap_context                     4178                       # number of times the context was actually changed
 system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
 system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
@@ -313,13 +312,13 @@ system.tsunami.ethernet.postedInterrupts            0                       # nu
 system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
 system.iobus.throughput                       1480181                       # Throughput (bytes/s)
 system.iobus.data_through_bus                 2707742                       # Total data (bytes)
-system.cpu.icache.tags.replacements            919594                       # number of replacements
-system.cpu.icache.tags.tagsinuse           511.215243                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            59129922                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs            920106                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             64.264250                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements            919591                       # number of replacements
+system.cpu.icache.tags.tagsinuse           511.215239                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            59130053                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs            920103                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             64.264602                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle        9686972500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   511.215243                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_blocks::cpu.inst   511.215239                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.998467                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.998467                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
@@ -327,26 +326,26 @@ system.cpu.icache.tags.age_task_id_blocks_1024::0           63
 system.cpu.icache.tags.age_task_id_blocks_1024::1          117                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::2          332                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          60970364                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         60970364                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     59129922                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        59129922                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      59129922                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         59129922                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     59129922                       # number of overall hits
-system.cpu.icache.overall_hits::total        59129922                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst       920221                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total        920221                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst       920221                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total         920221                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst       920221                       # number of overall misses
-system.cpu.icache.overall_misses::total        920221                       # number of overall misses
-system.cpu.icache.ReadReq_accesses::cpu.inst     60050143                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     60050143                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     60050143                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     60050143                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     60050143                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     60050143                       # number of overall (read+write) accesses
+system.cpu.icache.tags.tag_accesses          60970489                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         60970489                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     59130053                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        59130053                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      59130053                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         59130053                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     59130053                       # number of overall hits
+system.cpu.icache.overall_hits::total        59130053                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst       920218                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total        920218                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst       920218                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total         920218                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst       920218                       # number of overall misses
+system.cpu.icache.overall_misses::total        920218                       # number of overall misses
+system.cpu.icache.ReadReq_accesses::cpu.inst     60050271                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     60050271                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     60050271                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     60050271                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     60050271                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     60050271                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.015324                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.015324                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.015324                       # miss rate for demand accesses
@@ -362,15 +361,15 @@ system.cpu.icache.avg_blocked_cycles::no_targets          nan
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements           992301                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        65424.374305                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            2433239                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs          1057464                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             2.301014                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements           992295                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        65424.374544                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            2433214                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs          1057458                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             2.301003                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle        614754000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 56309.122439                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  4867.329747                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  4247.922119                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::writebacks 56309.107765                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  4867.336412                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  4247.930367                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_percent::writebacks     0.859209                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.074270                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.064818                       # Average percentage of cache occupancy
@@ -379,67 +378,67 @@ system.cpu.l2cache.tags.occ_task_id_blocks::1024        65163
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0          781                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::1         3260                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::2         4024                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         3055                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        54043                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         3048                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        54050                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.994308                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         31737437                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        31737437                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst       906797                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data       811229                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        1718026                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks       833491                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total       833491                       # number of Writeback hits
+system.cpu.l2cache.tags.tag_accesses         31737120                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        31737120                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.inst       906794                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data       811217                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total        1718011                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks       833475                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total       833475                       # number of Writeback hits
 system.cpu.l2cache.UpgradeReq_hits::cpu.data            4                       # number of UpgradeReq hits
 system.cpu.l2cache.UpgradeReq_hits::total            4                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       187229                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       187229                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst       906797                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data       998458                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         1905255                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst       906797                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data       998458                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        1905255                       # number of overall hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       187228                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       187228                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst       906794                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data       998445                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         1905239                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst       906794                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data       998445                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        1905239                       # number of overall hits
 system.cpu.l2cache.ReadReq_misses::cpu.inst        13406                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_misses::cpu.data       927640                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_misses::total       941046                       # number of ReadReq misses
 system.cpu.l2cache.UpgradeReq_misses::cpu.data           12                       # number of UpgradeReq misses
 system.cpu.l2cache.UpgradeReq_misses::total           12                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       117117                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       117117                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data       117111                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       117111                       # number of ReadExReq misses
 system.cpu.l2cache.demand_misses::cpu.inst        13406                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data      1044757                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total       1058163                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data      1044751                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total       1058157                       # number of demand (read+write) misses
 system.cpu.l2cache.overall_misses::cpu.inst        13406                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data      1044757                       # number of overall misses
-system.cpu.l2cache.overall_misses::total      1058163                       # number of overall misses
-system.cpu.l2cache.ReadReq_accesses::cpu.inst       920203                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data      1738869                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total      2659072                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks       833491                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total       833491                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.overall_misses::cpu.data      1044751                       # number of overall misses
+system.cpu.l2cache.overall_misses::total      1058157                       # number of overall misses
+system.cpu.l2cache.ReadReq_accesses::cpu.inst       920200                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data      1738857                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total      2659057                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks       833475                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total       833475                       # number of Writeback accesses(hits+misses)
 system.cpu.l2cache.UpgradeReq_accesses::cpu.data           16                       # number of UpgradeReq accesses(hits+misses)
 system.cpu.l2cache.UpgradeReq_accesses::total           16                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       304346                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       304346                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst       920203                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      2043215                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      2963418                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst       920203                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      2043215                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      2963418                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       304339                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       304339                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst       920200                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      2043196                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      2963396                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst       920200                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      2043196                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      2963396                       # number of overall (read+write) accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.014569                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.533473                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.353900                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.533477                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.353902                       # miss rate for ReadReq accesses
 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.750000                       # miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_miss_rate::total     0.750000                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.384815                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.384815                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.384804                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.384804                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_miss_rate::cpu.inst     0.014569                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.511330                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.357075                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.511332                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.357076                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.014569                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.511330                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.357075                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.511332                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.357076                       # miss rate for overall accesses
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -448,14 +447,14 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        74291                       # number of writebacks
-system.cpu.l2cache.writebacks::total            74291                       # number of writebacks
+system.cpu.l2cache.writebacks::writebacks        74285                       # number of writebacks
+system.cpu.l2cache.writebacks::total            74285                       # number of writebacks
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements           2042702                       # number of replacements
+system.cpu.dcache.tags.replacements           2042683                       # number of replacements
 system.cpu.dcache.tags.tagsinuse           511.997802                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            14038431                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           2043214                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs              6.870759                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.total_refs            14038451                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           2043195                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs              6.870833                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle          10840000                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.tags.occ_blocks::cpu.data   511.997802                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.999996                       # Average percentage of cache occupancy
@@ -465,52 +464,52 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0          443
 system.cpu.dcache.tags.age_task_id_blocks_1024::1           66                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::2            3                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          66369799                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         66369799                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data      7807780                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total         7807780                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      5848212                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        5848212                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data       183141                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       183141                       # number of LoadLockedReq hits
+system.cpu.dcache.tags.tag_accesses          66369784                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         66369784                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data      7807792                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total         7807792                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      5848219                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        5848219                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data       183142                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total       183142                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data       199282                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total       199282                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      13655992                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         13655992                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     13655992                       # number of overall hits
-system.cpu.dcache.overall_hits::total        13655992                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      1721707                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       1721707                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       304362                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       304362                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data        17162                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total        17162                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data      2026069                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        2026069                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      2026069                       # number of overall misses
-system.cpu.dcache.overall_misses::total       2026069                       # number of overall misses
-system.cpu.dcache.ReadReq_accesses::cpu.data      9529487                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total      9529487                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_hits::cpu.data      13656011                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         13656011                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     13656011                       # number of overall hits
+system.cpu.dcache.overall_hits::total        13656011                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      1721696                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       1721696                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       304355                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       304355                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data        17161                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total        17161                       # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data      2026051                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        2026051                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      2026051                       # number of overall misses
+system.cpu.dcache.overall_misses::total       2026051                       # number of overall misses
+system.cpu.dcache.ReadReq_accesses::cpu.data      9529488                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total      9529488                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data      6152574                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total      6152574                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::cpu.data       200303                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::total       200303                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data       199282                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total       199282                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     15682061                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     15682061                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     15682061                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     15682061                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.180672                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.180672                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.049469                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.049469                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.085680                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.085680                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.129197                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.129197                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.129197                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.129197                       # miss rate for overall accesses
+system.cpu.dcache.demand_accesses::cpu.data     15682062                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     15682062                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     15682062                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     15682062                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.180670                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.180670                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.049468                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.049468                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.085675                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.085675                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.129195                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.129195                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.129195                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.129195                       # miss rate for overall accesses
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -519,11 +518,11 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       833491                       # number of writebacks
-system.cpu.dcache.writebacks::total            833491                       # number of writebacks
+system.cpu.dcache.writebacks::writebacks       833475                       # number of writebacks
+system.cpu.dcache.writebacks::total            833475                       # number of writebacks
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.throughput               132867917                       # Throughput (bytes/s)
-system.cpu.toL2Bus.data_through_bus         243049454                       # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus        10112                       # Total snoop data (bytes)
+system.cpu.toL2Bus.throughput               134320283                       # Throughput (bytes/s)
+system.cpu.toL2Bus.data_through_bus         243047022                       # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus      2669376                       # Total snoop data (bytes)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
index a1c48ce35..034bdfed2 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
@@ -1,137 +1,140 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  1.962822                       # Number of seconds simulated
-sim_ticks                                1962822184500                       # Number of ticks simulated
-final_tick                               1962822184500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  1.962815                       # Number of seconds simulated
+sim_ticks                                1962815218500                       # Number of ticks simulated
+final_tick                               1962815218500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 916137                       # Simulator instruction rate (inst/s)
-host_op_rate                                   916137                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            30287148246                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 346744                       # Number of bytes of host memory used
-host_seconds                                    64.81                       # Real time elapsed on the host
-sim_insts                                    59372170                       # Number of instructions simulated
-sim_ops                                      59372170                       # Number of ops (including micro ops) simulated
+host_inst_rate                                1506000                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1505999                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            49787604582                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 317424                       # Number of bytes of host memory used
+host_seconds                                    39.42                       # Real time elapsed on the host
+sim_insts                                    59372159                       # Number of instructions simulated
+sim_ops                                      59372159                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu0.inst           724800                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data         24150336                       # Number of bytes read from this memory
-system.physmem.bytes_read::tsunami.ide        2649344                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           138496                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data          1080640                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             28743616                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       724800                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       138496                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          863296                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7747520                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7747520                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.inst             11325                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data            377349                       # Number of read requests responded to by this memory
-system.physmem.num_reads::tsunami.ide           41396                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              2164                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data             16885                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                449119                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          121055                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               121055                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.inst              369264                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data            12303884                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::tsunami.ide           1349763                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               70560                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              550554                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                14644024                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         369264                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          70560                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             439824                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           3947133                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                3947133                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           3947133                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             369264                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data           12303884                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::tsunami.ide          1349763                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              70560                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             550554                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               18591157                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        449119                       # Number of read requests accepted
-system.physmem.writeReqs                       121055                       # Number of write requests accepted
-system.physmem.readBursts                      449119                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     121055                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 28736320                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      7296                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   7746176                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  28743616                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                7747520                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      114                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytes_read::cpu0.inst           724992                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data         24166912                       # Number of bytes read from this memory
+system.physmem.bytes_read::tsunami.ide            960                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           138560                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data          1080576                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             26112000                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       724992                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       138560                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          863552                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      5090112                       # Number of bytes written to this memory
+system.physmem.bytes_written::tsunami.ide      2659328                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7749440                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.inst             11328                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data            377608                       # Number of read requests responded to by this memory
+system.physmem.num_reads::tsunami.ide              15                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst              2165                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data             16884                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                408000                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           79533                       # Number of write requests responded to by this memory
+system.physmem.num_writes::tsunami.ide          41552                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               121085                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.inst              369363                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data            12312372                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::tsunami.ide               489                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               70592                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              550524                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                13303341                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         369363                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          70592                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             439956                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           2593271                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::tsunami.ide          1354854                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                3948125                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           2593271                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             369363                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data           12312372                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::tsunami.ide          1355343                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              70592                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             550524                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               17251466                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        408000                       # Number of read requests accepted
+system.physmem.writeReqs                       121085                       # Number of write requests accepted
+system.physmem.readBursts                      408000                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     121085                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 26099968                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     12032                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   7747840                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  26112000                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                7749440                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      188                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs           3360                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               28065                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               28141                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               27986                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               28553                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               28160                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               27775                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               27616                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               27528                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               27559                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               27974                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              27981                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              28021                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              28612                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              28738                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              28459                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              27837                       # Per bank write bursts
+system.physmem.perBankRdBursts::0               25223                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               25569                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               25254                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               25702                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               25695                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               25237                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               25154                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               25289                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               25197                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               25673                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              25761                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              25821                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              25887                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              25811                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              25568                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              24971                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                7862                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                7636                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                7635                       # Per bank write bursts
 system.physmem.perBankWrBursts::2                7481                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                8065                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                7619                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                8078                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                7635                       # Per bank write bursts
 system.physmem.perBankWrBursts::5                7244                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                7159                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                6941                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                7160                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                6937                       # Per bank write bursts
 system.physmem.perBankWrBursts::8                6882                       # Per bank write bursts
 system.physmem.perBankWrBursts::9                7297                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               7427                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               7400                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               7429                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               7398                       # Per bank write bursts
 system.physmem.perBankWrBursts::12               8124                       # Per bank write bursts
 system.physmem.perBankWrBursts::13               8265                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               8168                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               8169                       # Per bank write bursts
 system.physmem.perBankWrBursts::15               7464                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                           8                       # Number of times write queue was full causing retry
-system.physmem.totGap                    1962815073500                       # Total gap between requests
+system.physmem.numWrRetry                           6                       # Number of times write queue was full causing retry
+system.physmem.totGap                    1962808109000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  449119                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  408000                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 121055                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    407912                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      1721                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                      2712                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                      1276                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                      1995                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                      4350                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                      3947                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                      3971                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                      2533                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                      2190                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                     2125                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                     2091                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                     1633                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                     1613                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                     1890                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                     1879                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                     2087                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                     1205                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                      975                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                      896                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                        4                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 121085                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    407738                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                        61                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                         1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                         1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                         1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                         1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                         1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                         1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
@@ -158,356 +161,357 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     1425                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     1547                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     4875                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     4920                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     4927                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     4931                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     4933                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     5043                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     5216                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     5300                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     5467                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     5674                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     5678                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     5762                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     5841                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     5977                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     5938                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     6015                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      879                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      905                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      923                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      879                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      937                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      961                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                     1045                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      965                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                     1159                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                     1188                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                     1167                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                     1240                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                     1400                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                     1637                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                     1890                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                     2102                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                     1946                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                     1888                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                     1710                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                     1689                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                     1830                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                     1638                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                      806                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                      341                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                      205                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                      121                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       40                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       32                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       20                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       14                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       14                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        68642                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      531.489409                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     323.678439                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     416.279001                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          15609     22.74%     22.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        11929     17.38%     40.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         5150      7.50%     47.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3087      4.50%     52.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         3390      4.94%     57.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1779      2.59%     59.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1473      2.15%     61.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1315      1.92%     63.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        24910     36.29%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          68642                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          7087                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        63.355581                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev     1920.089024                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-4095           7082     99.93%     99.93% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::4096-8191            1      0.01%     99.94% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::40960-45055            1      0.01%     99.96% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::57344-61439            1      0.01%     99.97% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::73728-77823            1      0.01%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::122880-126975            1      0.01%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            7087                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          7087                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        17.078312                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.846071                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        3.814192                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16               5314     74.98%     74.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17                115      1.62%     76.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18               1264     17.84%     94.44% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19                 37      0.52%     94.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                 12      0.17%     95.13% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21                 12      0.17%     95.30% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22                 26      0.37%     95.67% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23                 96      1.35%     97.02% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24                 18      0.25%     97.28% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::25                 39      0.55%     97.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26                 16      0.23%     98.05% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::27                 10      0.14%     98.19% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28                 12      0.17%     98.36% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::29                  8      0.11%     98.48% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::30                  4      0.06%     98.53% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::31                 15      0.21%     98.74% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32                  3      0.04%     98.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::34                  4      0.06%     98.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::35                  2      0.03%     98.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36                  1      0.01%     98.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::37                  3      0.04%     98.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::38                  2      0.03%     98.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::39                 10      0.14%     99.10% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40                  6      0.08%     99.18% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::41                  6      0.08%     99.27% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::42                  2      0.03%     99.29% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::43                  2      0.03%     99.32% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44                  2      0.03%     99.35% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::45                  4      0.06%     99.41% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::46                  1      0.01%     99.42% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::47                 10      0.14%     99.56% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48                  2      0.03%     99.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::50                  2      0.03%     99.62% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::55                  1      0.01%     99.63% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56                  9      0.13%     99.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::57                 14      0.20%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::58                  3      0.04%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            7087                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     7297703000                       # Total ticks spent queuing
-system.physmem.totMemAccLat               15716546750                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   2245025000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       16253.06                       # Average queueing delay per DRAM burst
+system.physmem.wrQLenPdf::15                     1952                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     2710                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     5918                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::22                     8568                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::57                       80                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::61                       25                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       16                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                       13                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        66023                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      512.666919                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     309.343673                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     413.043592                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          15664     23.73%     23.73% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        11865     17.97%     41.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         5137      7.78%     49.48% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3080      4.67%     54.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         3330      5.04%     59.19% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1778      2.69%     61.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1463      2.22%     64.09% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1306      1.98%     66.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        22400     33.93%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          66023                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          5447                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        74.865981                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev     2190.069327                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-4095           5442     99.91%     99.91% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::4096-8191            1      0.02%     99.93% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::40960-45055            1      0.02%     99.94% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::57344-61439            1      0.02%     99.96% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::73728-77823            1      0.02%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::122880-126975            1      0.02%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total            5447                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          5447                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        22.225078                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       19.080270                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       19.855094                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            4780     87.75%     87.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23              19      0.35%     88.10% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27              16      0.29%     88.40% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31             235      4.31%     92.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35              38      0.70%     93.41% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39               9      0.17%     93.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43              13      0.24%     93.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47              10      0.18%     94.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51              23      0.42%     94.42% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55               3      0.06%     94.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59               2      0.04%     94.51% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63               1      0.02%     94.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67               7      0.13%     94.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71               5      0.09%     94.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75               4      0.07%     94.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83              29      0.53%     95.36% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87              14      0.26%     95.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91               6      0.11%     95.72% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95               6      0.11%     95.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99             182      3.34%     99.17% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             1      0.02%     99.19% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111             2      0.04%     99.23% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115             2      0.04%     99.27% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-123             1      0.02%     99.28% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127             1      0.02%     99.30% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131            10      0.18%     99.49% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135             2      0.04%     99.52% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-139             5      0.09%     99.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143             5      0.09%     99.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147             8      0.15%     99.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::148-151             1      0.02%     99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-155             1      0.02%     99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-163             2      0.04%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::180-183             1      0.02%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::208-211             1      0.02%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::224-227             2      0.04%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            5447                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     2167934250                       # Total ticks spent queuing
+system.physmem.totMemAccLat                9814409250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   2039060000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        5316.01                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  35003.06                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          14.64                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  24066.01                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          13.30                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           3.95                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       14.64                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       13.30                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        3.95                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           0.15                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       0.11                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                           0.13                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       0.10                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.01                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        25.12                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     403892                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     97505                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   89.95                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  80.55                       # Row buffer hit rate for writes
-system.physmem.avgGap                      3442484.35                       # Average gap between requests
-system.physmem.pageHitRate                      87.96                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE     1840580762750                       # Time in different power states
-system.physmem.memoryStateTime::REF       65542880000                       # Time in different power states
+system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        25.06                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     365758                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     97091                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   89.69                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  80.18                       # Row buffer hit rate for writes
+system.physmem.avgGap                      3709816.21                       # Average gap between requests
+system.physmem.pageHitRate                      87.51                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE     1840831671000                       # Time in different power states
+system.physmem.memoryStateTime::REF       65542620000                       # Time in different power states
 system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT       56696821000                       # Time in different power states
+system.physmem.memoryStateTime::ACT       56438386500                       # Time in different power states
 system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.membus.throughput                     18645480                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq              292657                       # Transaction distribution
-system.membus.trans_dist::ReadResp             292657                       # Transaction distribution
+system.membus.throughput                     17291736                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq              292660                       # Transaction distribution
+system.membus.trans_dist::ReadResp             292660                       # Transaction distribution
 system.membus.trans_dist::WriteReq              12414                       # Transaction distribution
 system.membus.trans_dist::WriteResp             12414                       # Transaction distribution
-system.membus.trans_dist::Writeback            121055                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             4555                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq           1018                       # Transaction distribution
+system.membus.trans_dist::Writeback             79533                       # Transaction distribution
+system.membus.trans_dist::WriteInvalidateReq        41552                       # Transaction distribution
+system.membus.trans_dist::WriteInvalidateResp        41552                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq             4556                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq           1019                       # Transaction distribution
 system.membus.trans_dist::UpgradeResp            3360                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            164356                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           164254                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            122803                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           122701                       # Transaction distribution
 system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave        39228                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       904273                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total       943501                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       124647                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       124647                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1068148                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       904540                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total       943768                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        83295                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total        83295                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                1027063                       # Packet count per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave        68738                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port     31184320                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::total     31253058                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port      5306816                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::total      5306816                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total            36559874                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus               36559874                       # Total data (bytes)
-system.membus.snoop_data_through_bus            37888                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy            39221000                       # Layer occupancy (ticks)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port     31201152                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::total     31269890                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port      2660288                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.iocache.mem_side::total      2660288                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total            33930178                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus               33930178                       # Total data (bytes)
+system.membus.snoop_data_through_bus            10304                       # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy            39224500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy          1574833000                       # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy          1533573250                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.1                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         3826410374                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         3826483141                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
-system.membus.respLayer2.occupancy          376647250                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy           43139750                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.l2c.tags.replacements                   342221                       # number of replacements
-system.l2c.tags.tagsinuse                65256.412579                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    2544259                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                   407367                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                     6.245619                       # Average number of references to valid blocks.
+system.l2c.tags.replacements                   342222                       # number of replacements
+system.l2c.tags.tagsinuse                65256.426750                       # Cycle average of tags in use
+system.l2c.tags.total_refs                    2542307                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                   407368                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                     6.240812                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle               8652281750                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   55518.574788                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     3744.543964                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     4299.514442                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst     1171.756098                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data      522.023286                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.847146                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.057137                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.065605                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.017880                       # Average percentage of cache occupancy
+system.l2c.tags.occ_blocks::writebacks   55518.260732                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     3744.767678                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     4299.632317                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst     1171.746225                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data      522.019798                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.847141                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst       0.057141                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data       0.065607                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.017879                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu1.data       0.007965                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::total           0.995734                       # Average percentage of cache occupancy
 system.l2c.tags.occ_task_id_blocks::1024        65146                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0          114                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1          752                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0          118                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1          748                       # Occupied blocks per task id
 system.l2c.tags.age_task_id_blocks_1024::2         5288                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         7256                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        51736                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3         7253                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        51739                       # Occupied blocks per task id
 system.l2c.tags.occ_task_id_percent::1024     0.994049                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                 26948745                       # Number of tag accesses
-system.l2c.tags.data_accesses                26948745                       # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.inst             527962                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data             377923                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst             461443                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data             449896                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                1817224                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks          850135                       # number of Writeback hits
-system.l2c.Writeback_hits::total               850135                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data             136                       # number of UpgradeReq hits
+system.l2c.tags.tag_accesses                 26946350                       # Number of tag accesses
+system.l2c.tags.data_accesses                26946350                       # Number of data accesses
+system.l2c.ReadReq_hits::cpu0.inst             527823                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.data             377901                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.inst             461413                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.data             449863                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                1817000                       # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks          850078                       # number of Writeback hits
+system.l2c.Writeback_hits::total               850078                       # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu0.data             135                       # number of UpgradeReq hits
 system.l2c.UpgradeReq_hits::cpu1.data              70                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                 206                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data            24                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data            20                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total                44                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data           113466                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data            85009                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               198475                       # number of ReadExReq hits
-system.l2c.demand_hits::cpu0.inst              527962                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data              491389                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst              461443                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data              534905                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 2015699                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.inst             527962                       # number of overall hits
-system.l2c.overall_hits::cpu0.data             491389                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst             461443                       # number of overall hits
-system.l2c.overall_hits::cpu1.data             534905                       # number of overall hits
-system.l2c.overall_hits::total                2015699                       # number of overall hits
-system.l2c.ReadReq_misses::cpu0.inst            11328                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.data           270740                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.inst             2172                       # number of ReadReq misses
+system.l2c.UpgradeReq_hits::total                 205                       # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu0.data            25                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu1.data            21                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total                46                       # number of SCUpgradeReq hits
+system.l2c.ReadExReq_hits::cpu0.data           113452                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data            85004                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               198456                       # number of ReadExReq hits
+system.l2c.demand_hits::cpu0.inst              527823                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data              491353                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst              461413                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data              534867                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                 2015456                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.inst             527823                       # number of overall hits
+system.l2c.overall_hits::cpu0.data             491353                       # number of overall hits
+system.l2c.overall_hits::cpu1.inst             461413                       # number of overall hits
+system.l2c.overall_hits::cpu1.data             534867                       # number of overall hits
+system.l2c.overall_hits::total                2015456                       # number of overall hits
+system.l2c.ReadReq_misses::cpu0.inst            11331                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.data           270739                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.inst             2173                       # number of ReadReq misses
 system.l2c.ReadReq_misses::cpu1.data             1052                       # number of ReadReq misses
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 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -516,8 +520,8 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
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 system.l2c.ReadReq_mshr_hits::cpu0.inst             3                       # number of ReadReq MSHR hits
 system.l2c.ReadReq_mshr_hits::cpu1.inst             8                       # number of ReadReq MSHR hits
 system.l2c.ReadReq_mshr_hits::total                11                       # number of ReadReq MSHR hits
@@ -527,111 +531,111 @@ system.l2c.demand_mshr_hits::total                 11                       # nu
 system.l2c.overall_mshr_hits::cpu0.inst             3                       # number of overall MSHR hits
 system.l2c.overall_mshr_hits::cpu1.inst             8                       # number of overall MSHR hits
 system.l2c.overall_mshr_hits::total                11                       # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses::cpu0.inst        11325                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.data       270740                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.inst         2164                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu0.inst        11328                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu0.data       270739                       # number of ReadReq MSHR misses
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 system.l2c.ReadReq_mshr_misses::cpu1.data         1052                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total          285281                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::total          285284                       # number of ReadReq MSHR misses
 system.l2c.UpgradeReq_mshr_misses::cpu0.data         2603                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data          468                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total         3071                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.data          469                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total         3072                       # number of UpgradeReq MSHR misses
 system.l2c.SCUpgradeReq_mshr_misses::cpu0.data           62                       # number of SCUpgradeReq MSHR misses
 system.l2c.SCUpgradeReq_mshr_misses::cpu1.data           80                       # number of SCUpgradeReq MSHR misses
 system.l2c.SCUpgradeReq_mshr_misses::total          142                       # number of SCUpgradeReq MSHR misses
 system.l2c.ReadExReq_mshr_misses::cpu0.data       107000                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data        15849                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total        122849                       # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses::cpu0.inst        11325                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.data       377740                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst         2164                       # number of demand (read+write) MSHR misses
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-system.l2c.overall_mshr_misses::cpu0.inst        11325                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.data       377740                       # number of overall MSHR misses
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-system.l2c.ReadReq_mshr_miss_latency::cpu0.data  14211795014                       # number of ReadReq MSHR miss cycles
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-system.l2c.ReadReq_mshr_miss_latency::cpu1.data     66581750                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total  15100089018                       # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     26041101                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data      4800968                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total     30842069                       # number of UpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_misses::cpu1.data        15847                       # number of ReadExReq MSHR misses
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+system.l2c.ReadReq_mshr_miss_latency::cpu0.data  14211900500                       # number of ReadReq MSHR miss cycles
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+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data      4690469                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total     30725071                       # number of UpgradeReq MSHR miss cycles
 system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data       620062                       # number of SCUpgradeReq MSHR miss cycles
 system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data       800080                       # number of SCUpgradeReq MSHR miss cycles
 system.l2c.SCUpgradeReq_mshr_miss_latency::total      1420142                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   5999010131                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    959576266                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total   6958586397                       # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.inst    689008754                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.data  20210805145                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst    132703500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data   1026158016                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total  22058675415                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.inst    689008754                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.data  20210805145                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst    132703500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data   1026158016                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total  22058675415                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data    941946500                       # number of ReadReq MSHR uncacheable cycles
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+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    958453765                       # number of ReadExReq MSHR miss cycles
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+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data    941946000                       # number of ReadReq MSHR uncacheable cycles
 system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    449028500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total   1390975000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   1618779500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    858260500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total   2477040000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data   2560726000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data   1307289000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total   3868015000                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.021000                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.417382                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.004668                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_uncacheable_latency::total   1390974500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   1618783500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    858261500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total   2477045000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data   2560729500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data   1307290000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total   3868019500                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.021011                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.417395                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.004670                       # mshr miss rate for ReadReq accesses
 system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.002333                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.135686                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.950347                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.869888                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.937138                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.720930                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.800000                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.763441                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.485336                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.157142                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.382321                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.021000                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.434619                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.004668                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.030629                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.168382                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.021000                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.434619                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.004668                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.030629                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.168382                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 60839.625077                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 52492.409744                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 61323.243993                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 63290.636882                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 52930.580789                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10004.264695                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10258.478632                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10043.005210                       # average UpgradeReq mshr miss latency
+system.l2c.ReadReq_mshr_miss_rate::total     0.135701                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.950694                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.870130                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.937443                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.712644                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.792079                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.755319                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.485366                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.157133                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.382340                       # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.021011                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.434636                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.004670                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.030627                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.168399                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.021011                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.434636                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.004670                       # mshr miss rate for overall accesses
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+system.l2c.overall_mshr_miss_rate::total     0.168399                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 60278.469280                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 52492.993252                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 61937.413395                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data        63000                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 52912.555559                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001.767960                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data        10001                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10001.650716                       # average UpgradeReq mshr miss latency
 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data        10001                       # average SCUpgradeReq mshr miss latency
 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data        10001                       # average SCUpgradeReq mshr miss latency
 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        10001                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 56065.515243                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 60544.909206                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 56643.410992                       # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 60839.625077                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 53504.540544                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 61323.243993                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 60715.816579                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 54048.159692                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 60839.625077                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 53504.540544                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 61323.243993                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 60715.816579                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 54048.159692                       # average overall mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 56070.797953                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 60481.716729                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 56639.797032                       # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 60278.469280                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 53506.457848                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 61937.413395                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 60638.485413                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 54034.451306                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 60278.469280                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 53506.457848                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 61937.413395                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 60638.485413                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 54034.451306                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -643,101 +647,93 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf
 system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
 system.iocache.tags.replacements                41699                       # number of replacements
-system.iocache.tags.tagsinuse                0.570023                       # Cycle average of tags in use
+system.iocache.tags.tagsinuse                0.569942                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs                41715                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         1756486423000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::tsunami.ide     0.570023                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::tsunami.ide     0.035626                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.035626                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         1756486320000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::tsunami.ide     0.569942                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::tsunami.ide     0.035621                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.035621                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
 system.iocache.tags.tag_accesses               375552                       # Number of tag accesses
 system.iocache.tags.data_accesses              375552                       # Number of data accesses
+system.iocache.WriteInvalidateReq_hits::tsunami.ide        41552                       # number of WriteInvalidateReq hits
+system.iocache.WriteInvalidateReq_hits::total        41552                       # number of WriteInvalidateReq hits
 system.iocache.ReadReq_misses::tsunami.ide          176                       # number of ReadReq misses
 system.iocache.ReadReq_misses::total              176                       # number of ReadReq misses
-system.iocache.WriteReq_misses::tsunami.ide        41552                       # number of WriteReq misses
-system.iocache.WriteReq_misses::total           41552                       # number of WriteReq misses
-system.iocache.demand_misses::tsunami.ide        41728                       # number of demand (read+write) misses
-system.iocache.demand_misses::total             41728                       # number of demand (read+write) misses
-system.iocache.overall_misses::tsunami.ide        41728                       # number of overall misses
-system.iocache.overall_misses::total            41728                       # number of overall misses
-system.iocache.ReadReq_miss_latency::tsunami.ide     21474883                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     21474883                       # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency::tsunami.ide  12370994210                       # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_latency::total  12370994210                       # number of WriteReq miss cycles
-system.iocache.demand_miss_latency::tsunami.ide  12392469093                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total  12392469093                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::tsunami.ide  12392469093                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total  12392469093                       # number of overall miss cycles
+system.iocache.demand_misses::tsunami.ide          176                       # number of demand (read+write) misses
+system.iocache.demand_misses::total               176                       # number of demand (read+write) misses
+system.iocache.overall_misses::tsunami.ide          176                       # number of overall misses
+system.iocache.overall_misses::total              176                       # number of overall misses
+system.iocache.ReadReq_miss_latency::tsunami.ide     21474383                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     21474383                       # number of ReadReq miss cycles
+system.iocache.demand_miss_latency::tsunami.ide     21474383                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total     21474383                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::tsunami.ide     21474383                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total     21474383                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::tsunami.ide          176                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            176                       # number of ReadReq accesses(hits+misses)
-system.iocache.WriteReq_accesses::tsunami.ide        41552                       # number of WriteReq accesses(hits+misses)
-system.iocache.WriteReq_accesses::total         41552                       # number of WriteReq accesses(hits+misses)
-system.iocache.demand_accesses::tsunami.ide        41728                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total           41728                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::tsunami.ide        41728                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total          41728                       # number of overall (read+write) accesses
+system.iocache.WriteInvalidateReq_accesses::tsunami.ide        41552                       # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::total        41552                       # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.demand_accesses::tsunami.ide          176                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total             176                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::tsunami.ide          176                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total            176                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
-system.iocache.WriteReq_miss_rate::tsunami.ide            1                       # miss rate for WriteReq accesses
-system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
 system.iocache.demand_miss_rate::tsunami.ide            1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122016.380682                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 122016.380682                       # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::tsunami.ide 297723.195273                       # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total 297723.195273                       # average WriteReq miss latency
-system.iocache.demand_avg_miss_latency::tsunami.ide 296982.100580                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 296982.100580                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::tsunami.ide 296982.100580                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 296982.100580                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs        362942                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122013.539773                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 122013.539773                       # average ReadReq miss latency
+system.iocache.demand_avg_miss_latency::tsunami.ide 122013.539773                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 122013.539773                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::tsunami.ide 122013.539773                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 122013.539773                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                28216                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs    12.862986                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.fast_writes                          0                       # number of fast writes performed
+system.iocache.fast_writes                      41552                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.writebacks::writebacks           41523                       # number of writebacks
-system.iocache.writebacks::total                41523                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::tsunami.ide          176                       # number of ReadReq MSHR misses
 system.iocache.ReadReq_mshr_misses::total          176                       # number of ReadReq MSHR misses
-system.iocache.WriteReq_mshr_misses::tsunami.ide        41552                       # number of WriteReq MSHR misses
-system.iocache.WriteReq_mshr_misses::total        41552                       # number of WriteReq MSHR misses
-system.iocache.demand_mshr_misses::tsunami.ide        41728                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total        41728                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::tsunami.ide        41728                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total        41728                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     12321883                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     12321883                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::tsunami.ide  10208100710                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::total  10208100710                       # number of WriteReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::tsunami.ide  10220422593                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total  10220422593                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::tsunami.ide  10220422593                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total  10220422593                       # number of overall MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide        41552                       # number of WriteInvalidateReq MSHR misses
+system.iocache.WriteInvalidateReq_mshr_misses::total        41552                       # number of WriteInvalidateReq MSHR misses
+system.iocache.demand_mshr_misses::tsunami.ide          176                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total          176                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::tsunami.ide          176                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total          176                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     12321383                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     12321383                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide   2504351556                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::total   2504351556                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::tsunami.ide     12321383                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total     12321383                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::tsunami.ide     12321383                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total     12321383                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
-system.iocache.WriteReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteReq accesses
-system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
+system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteInvalidateReq accesses
 system.iocache.demand_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for demand accesses
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70010.698864                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 70010.698864                       # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 245670.502262                       # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total 245670.502262                       # average WriteReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 244929.605852                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 244929.605852                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 244929.605852                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 244929.605852                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70007.857955                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 70007.857955                       # average ReadReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 60270.301213                       # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60270.301213                       # average WriteInvalidateReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70007.857955                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 70007.857955                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70007.857955                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 70007.857955                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
@@ -755,22 +751,22 @@ system.cpu0.dtb.fetch_hits                          0                       # IT
 system.cpu0.dtb.fetch_misses                        0                       # ITB misses
 system.cpu0.dtb.fetch_acv                           0                       # ITB acv
 system.cpu0.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu0.dtb.read_hits                     6067358                       # DTB read hits
+system.cpu0.dtb.read_hits                     6067147                       # DTB read hits
 system.cpu0.dtb.read_misses                      7765                       # DTB read misses
 system.cpu0.dtb.read_acv                          210                       # DTB read access violations
 system.cpu0.dtb.read_accesses                  524069                       # DTB read accesses
-system.cpu0.dtb.write_hits                    4265662                       # DTB write hits
+system.cpu0.dtb.write_hits                    4265547                       # DTB write hits
 system.cpu0.dtb.write_misses                      910                       # DTB write misses
 system.cpu0.dtb.write_acv                         133                       # DTB write access violations
 system.cpu0.dtb.write_accesses                 202595                       # DTB write accesses
-system.cpu0.dtb.data_hits                    10333020                       # DTB hits
+system.cpu0.dtb.data_hits                    10332694                       # DTB hits
 system.cpu0.dtb.data_misses                      8675                       # DTB misses
 system.cpu0.dtb.data_acv                          343                       # DTB access violations
 system.cpu0.dtb.data_accesses                  726664                       # DTB accesses
-system.cpu0.itb.fetch_hits                    3354842                       # ITB hits
+system.cpu0.itb.fetch_hits                    3354719                       # ITB hits
 system.cpu0.itb.fetch_misses                     3984                       # ITB misses
 system.cpu0.itb.fetch_acv                         184                       # ITB acv
-system.cpu0.itb.fetch_accesses                3358826                       # ITB accesses
+system.cpu0.itb.fetch_accesses                3358703                       # ITB accesses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.read_acv                            0                       # DTB read access violations
@@ -783,34 +779,34 @@ system.cpu0.itb.data_hits                           0                       # DT
 system.cpu0.itb.data_misses                         0                       # DTB misses
 system.cpu0.itb.data_acv                            0                       # DTB access violations
 system.cpu0.itb.data_accesses                       0                       # DTB accesses
-system.cpu0.numCycles                      3925644369                       # number of cpu cycles simulated
+system.cpu0.numCycles                      3925630437                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                   38276564                       # Number of instructions committed
-system.cpu0.committedOps                     38276564                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses             35596868                       # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses                153627                       # Number of float alu accesses
-system.cpu0.num_func_calls                     936507                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts      4464991                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                    35596868                       # number of integer instructions
-system.cpu0.num_fp_insts                       153627                       # number of float instructions
-system.cpu0.num_int_register_reads           48919002                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes          26532177                       # number of times the integer registers were written
-system.cpu0.num_fp_register_reads               75066                       # number of times the floating registers were read
-system.cpu0.num_fp_register_writes              75978                       # number of times the floating registers were written
-system.cpu0.num_mem_refs                     10366198                       # number of memory refs
-system.cpu0.num_load_insts                    6090760                       # Number of load instructions
-system.cpu0.num_store_insts                   4275438                       # Number of store instructions
-system.cpu0.num_idle_cycles              3742234246.498094                       # Number of idle cycles
-system.cpu0.num_busy_cycles              183410122.501907                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.046721                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.953279                       # Percentage of idle cycles
-system.cpu0.Branches                          5694814                       # Number of branches fetched
-system.cpu0.op_class::No_OpClass              2096369      5.48%      5.48% # Class of executed instruction
-system.cpu0.op_class::IntAlu                 24995370     65.29%     70.76% # Class of executed instruction
-system.cpu0.op_class::IntMult                   39322      0.10%     70.86% # Class of executed instruction
-system.cpu0.op_class::IntDiv                        0      0.00%     70.86% # Class of executed instruction
-system.cpu0.op_class::FloatAdd                  12602      0.03%     70.90% # Class of executed instruction
+system.cpu0.committedInsts                   38276405                       # Number of instructions committed
+system.cpu0.committedOps                     38276405                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses             35596815                       # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses                153493                       # Number of float alu accesses
+system.cpu0.num_func_calls                     936479                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts      4465105                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                    35596815                       # number of integer instructions
+system.cpu0.num_fp_insts                       153493                       # number of float instructions
+system.cpu0.num_int_register_reads           48919188                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes          26532196                       # number of times the integer registers were written
+system.cpu0.num_fp_register_reads               75000                       # number of times the floating registers were read
+system.cpu0.num_fp_register_writes              75910                       # number of times the floating registers were written
+system.cpu0.num_mem_refs                     10365856                       # number of memory refs
+system.cpu0.num_load_insts                    6090539                       # Number of load instructions
+system.cpu0.num_store_insts                   4275317                       # Number of store instructions
+system.cpu0.num_idle_cycles              3742236660.998093                       # Number of idle cycles
+system.cpu0.num_busy_cycles              183393776.001907                       # Number of busy cycles
+system.cpu0.not_idle_fraction                0.046717                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                    0.953283                       # Percentage of idle cycles
+system.cpu0.Branches                          5694884                       # Number of branches fetched
+system.cpu0.op_class::No_OpClass              2096297      5.48%      5.48% # Class of executed instruction
+system.cpu0.op_class::IntAlu                 24983670     65.26%     70.73% # Class of executed instruction
+system.cpu0.op_class::IntMult                   39322      0.10%     70.83% # Class of executed instruction
+system.cpu0.op_class::IntDiv                        0      0.00%     70.83% # Class of executed instruction
+system.cpu0.op_class::FloatAdd                  24596      0.06%     70.90% # Class of executed instruction
 system.cpu0.op_class::FloatCmp                      0      0.00%     70.90% # Class of executed instruction
 system.cpu0.op_class::FloatCvt                      0      0.00%     70.90% # Class of executed instruction
 system.cpu0.op_class::FloatMult                     0      0.00%     70.90% # Class of executed instruction
@@ -836,37 +832,37 @@ system.cpu0.op_class::SimdFloatMisc                 0      0.00%     70.90% # Cl
 system.cpu0.op_class::SimdFloatMult                 0      0.00%     70.90% # Class of executed instruction
 system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     70.90% # Class of executed instruction
 system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     70.90% # Class of executed instruction
-system.cpu0.op_class::MemRead                 6233117     16.28%     87.18% # Class of executed instruction
-system.cpu0.op_class::MemWrite                4280683     11.18%     98.36% # Class of executed instruction
-system.cpu0.op_class::IprAccess                626236      1.64%    100.00% # Class of executed instruction
+system.cpu0.op_class::MemRead                 6232893     16.28%     87.18% # Class of executed instruction
+system.cpu0.op_class::MemWrite                4280562     11.18%     98.36% # Class of executed instruction
+system.cpu0.op_class::IprAccess                626200      1.64%    100.00% # Class of executed instruction
 system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu0.op_class::total                  38285582                       # Class of executed instruction
+system.cpu0.op_class::total                  38285423                       # Class of executed instruction
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                    4866                       # number of quiesce instructions executed
-system.cpu0.kern.inst.hwrei                    138364                       # number of hwrei instructions executed
-system.cpu0.kern.ipl_count::0                   44810     38.76%     38.76% # number of times we switched to this ipl
+system.cpu0.kern.inst.quiesce                    4863                       # number of quiesce instructions executed
+system.cpu0.kern.inst.hwrei                    138357                       # number of hwrei instructions executed
+system.cpu0.kern.ipl_count::0                   44808     38.76%     38.76% # number of times we switched to this ipl
 system.cpu0.kern.ipl_count::21                    131      0.11%     38.88% # number of times we switched to this ipl
 system.cpu0.kern.ipl_count::22                   1975      1.71%     40.58% # number of times we switched to this ipl
 system.cpu0.kern.ipl_count::30                     16      0.01%     40.60% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::31                  68668     59.40%    100.00% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::total              115600                       # number of times we switched to this ipl
-system.cpu0.kern.ipl_good::0                    44285     48.84%     48.84% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_count::31                  68665     59.40%    100.00% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::total              115595                       # number of times we switched to this ipl
+system.cpu0.kern.ipl_good::0                    44283     48.84%     48.84% # number of times we switched to this ipl from a different ipl
 system.cpu0.kern.ipl_good::21                     131      0.14%     48.98% # number of times we switched to this ipl from a different ipl
 system.cpu0.kern.ipl_good::22                    1975      2.18%     51.16% # number of times we switched to this ipl from a different ipl
 system.cpu0.kern.ipl_good::30                      16      0.02%     51.18% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::31                   44269     48.82%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::total                90676                       # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_ticks::0            1909704051500     97.29%     97.29% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::21               94854000      0.00%     97.30% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::22              764030500      0.04%     97.34% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_good::31                   44267     48.82%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::total                90672                       # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_ticks::0            1909699143000     97.29%     97.29% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::21               95243500      0.00%     97.30% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::22              764380500      0.04%     97.34% # number of cycles we spent at this ipl
 system.cpu0.kern.ipl_ticks::30               12585500      0.00%     97.34% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::31            52245891000      2.66%    100.00% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::total        1962821412500                       # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_used::0                 0.988284                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_ticks::31            52243094000      2.66%    100.00% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::total        1962814446500                       # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_used::0                 0.988283                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::21                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::31                0.644682                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used::31                0.644681                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::total             0.784394                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.syscall::2                         8      3.42%      3.42% # number of syscalls executed
 system.cpu0.kern.syscall::3                        20      8.55%     11.97% # number of syscalls executed
@@ -903,10 +899,10 @@ system.cpu0.kern.callpal::wripir                   86      0.07%      0.07% # nu
 system.cpu0.kern.callpal::wrmces                    1      0.00%      0.07% # number of callpals executed
 system.cpu0.kern.callpal::wrfen                     1      0.00%      0.07% # number of callpals executed
 system.cpu0.kern.callpal::wrvptptr                  1      0.00%      0.07% # number of callpals executed
-system.cpu0.kern.callpal::swpctx                 2218      1.80%      1.88% # number of callpals executed
+system.cpu0.kern.callpal::swpctx                 2216      1.80%      1.87% # number of callpals executed
 system.cpu0.kern.callpal::tbi                      51      0.04%      1.92% # number of callpals executed
 system.cpu0.kern.callpal::wrent                     7      0.01%      1.92% # number of callpals executed
-system.cpu0.kern.callpal::swpipl               109461     88.95%     90.88% # number of callpals executed
+system.cpu0.kern.callpal::swpipl               109456     88.95%     90.88% # number of callpals executed
 system.cpu0.kern.callpal::rdps                   6662      5.41%     96.29% # number of callpals executed
 system.cpu0.kern.callpal::wrkgp                     1      0.00%     96.29% # number of callpals executed
 system.cpu0.kern.callpal::wrusp                     4      0.00%     96.29% # number of callpals executed
@@ -915,21 +911,21 @@ system.cpu0.kern.callpal::whami                     2      0.00%     96.30% # nu
 system.cpu0.kern.callpal::rti                    4016      3.26%     99.57% # number of callpals executed
 system.cpu0.kern.callpal::callsys                 394      0.32%     99.89% # number of callpals executed
 system.cpu0.kern.callpal::imb                     139      0.11%    100.00% # number of callpals executed
-system.cpu0.kern.callpal::total                123054                       # number of callpals executed
-system.cpu0.kern.mode_switch::kernel             5726                       # number of protection mode switches
-system.cpu0.kern.mode_switch::user               1371                       # number of protection mode switches
+system.cpu0.kern.callpal::total                123047                       # number of callpals executed
+system.cpu0.kern.mode_switch::kernel             5724                       # number of protection mode switches
+system.cpu0.kern.mode_switch::user               1372                       # number of protection mode switches
 system.cpu0.kern.mode_switch::idle                  0                       # number of protection mode switches
-system.cpu0.kern.mode_good::kernel               1370                      
-system.cpu0.kern.mode_good::user                 1371                      
+system.cpu0.kern.mode_good::kernel               1371                      
+system.cpu0.kern.mode_good::user                 1372                      
 system.cpu0.kern.mode_good::idle                    0                      
-system.cpu0.kern.mode_switch_good::kernel     0.239260                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good::kernel     0.239518                       # fraction of useful protection mode switches
 system.cpu0.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
 system.cpu0.kern.mode_switch_good::idle           nan                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good::total     0.386220                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_ticks::kernel      1959031016000     99.81%     99.81% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks::user          3790392000      0.19%    100.00% # number of ticks spent at the given mode
+system.cpu0.kern.mode_switch_good::total     0.386556                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_ticks::kernel      1959023925000     99.81%     99.81% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks::user          3790517000      0.19%    100.00% # number of ticks spent at the given mode
 system.cpu0.kern.mode_ticks::idle                   0      0.00%    100.00% # number of ticks spent at the given mode
-system.cpu0.kern.swap_context                    2219                       # number of times the context was actually changed
+system.cpu0.kern.swap_context                    2217                       # number of times the context was actually changed
 system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
 system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
 system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
@@ -961,42 +957,43 @@ system.tsunami.ethernet.totalRxOrn                  0                       # to
 system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
 system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
 system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
-system.toL2Bus.throughput                   108070579                       # Throughput (bytes/s)
-system.toL2Bus.trans_dist::ReadReq            2148343                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           2148328                       # Transaction distribution
+system.toL2Bus.throughput                   109416622                       # Throughput (bytes/s)
+system.toL2Bus.trans_dist::ReadReq            2148133                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp           2148118                       # Transaction distribution
 system.toL2Bus.trans_dist::WriteReq             12414                       # Transaction distribution
 system.toL2Bus.trans_dist::WriteResp            12414                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback           850135                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq            4614                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq          1062                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp           5676                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           363639                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          322090                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      1078600                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      2181406                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side       927231                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side      1598323                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               5785560                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     34514560                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     81611821                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side     29671360                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side     63815893                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size::total          209613634                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.data_through_bus             209603138                       # Total data (bytes)
-system.toL2Bus.snoop_data_through_bus         2520192                       # Total snoop data (bytes)
-system.toL2Bus.reqLayer0.occupancy         5075991989                       # Layer occupancy (ticks)
+system.toL2Bus.trans_dist::Writeback           850078                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateReq        41558                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq            4615                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq          1065                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp           5680                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq           322069                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp          322069                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      1078328                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      2181300                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side       927173                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side      1598235                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total               5785036                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     34505856                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     81606637                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side     29669504                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side     63812309                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size::total          209594306                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.data_through_bus             209584002                       # Total data (bytes)
+system.toL2Bus.snoop_data_through_bus         5180608                       # Total snoop data (bytes)
+system.toL2Bus.reqLayer0.occupancy         5075622491                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.3                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy           738000                       # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy           724500                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy        2429088500                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy        2428486244                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy        4030648808                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy        4030575545                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.2                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy        2086694241                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy        2086565739                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer2.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy        2646669064                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy        2646502814                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer3.utilization             0.1                       # Layer utilization (%)
-system.iobus.throughput                       1391043                       # Throughput (bytes/s)
+system.iobus.throughput                       1391048                       # Throughput (bytes/s)
 system.iobus.trans_dist::ReadReq                 7376                       # Transaction distribution
 system.iobus.trans_dist::ReadResp                7376                       # Transaction distribution
 system.iobus.trans_dist::WriteReq               53966                       # Transaction distribution
@@ -1056,21 +1053,21 @@ system.iobus.reqLayer27.occupancy               76000                       # La
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer28.occupancy              110000                       # Layer occupancy (ticks)
 system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer29.occupancy           380139843                       # Layer occupancy (ticks)
+system.iobus.reqLayer29.occupancy           374413689                       # Layer occupancy (ticks)
 system.iobus.reqLayer29.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer30.occupancy               30000                       # Layer occupancy (ticks)
 system.iobus.reqLayer30.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy            26814000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer1.occupancy            43231750                       # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy            42018250                       # Layer occupancy (ticks)
 system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
-system.cpu0.icache.tags.replacements           538677                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          508.393435                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs           37746273                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs           539189                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            70.005644                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.replacements           538541                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          508.393356                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs           37746250                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs           539053                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            70.023263                       # Average number of references to valid blocks.
 system.cpu0.icache.tags.warmup_cycle      40276505250                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   508.393435                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   508.393356                       # Average occupied blocks per requestor
 system.cpu0.icache.tags.occ_percent::cpu0.inst     0.992956                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_percent::total     0.992956                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
@@ -1079,44 +1076,44 @@ system.cpu0.icache.tags.age_task_id_blocks_1024::1            1
 system.cpu0.icache.tags.age_task_id_blocks_1024::2          442                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::3           17                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses         38824893                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses        38824893                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst     37746273                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total       37746273                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst     37746273                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total        37746273                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst     37746273                       # number of overall hits
-system.cpu0.icache.overall_hits::total       37746273                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst       539310                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total       539310                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst       539310                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total        539310                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst       539310                       # number of overall misses
-system.cpu0.icache.overall_misses::total       539310                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst   7764312000                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total   7764312000                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst   7764312000                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total   7764312000                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst   7764312000                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total   7764312000                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst     38285583                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total     38285583                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst     38285583                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total     38285583                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst     38285583                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total     38285583                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.014087                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.014087                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.014087                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.014087                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.014087                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.014087                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14396.751405                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 14396.751405                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14396.751405                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 14396.751405                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14396.751405                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 14396.751405                       # average overall miss latency
+system.cpu0.icache.tags.tag_accesses         38824598                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses        38824598                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst     37746250                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total       37746250                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst     37746250                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total        37746250                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst     37746250                       # number of overall hits
+system.cpu0.icache.overall_hits::total       37746250                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst       539174                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total       539174                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst       539174                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total        539174                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst       539174                       # number of overall misses
+system.cpu0.icache.overall_misses::total       539174                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst   7756302744                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total   7756302744                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst   7756302744                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total   7756302744                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst   7756302744                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total   7756302744                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst     38285424                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total     38285424                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst     38285424                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total     38285424                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst     38285424                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total     38285424                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.014083                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.014083                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.014083                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.014083                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.014083                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.014083                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14385.528130                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 14385.528130                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14385.528130                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 14385.528130                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14385.528130                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 14385.528130                       # average overall miss latency
 system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1125,119 +1122,119 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       539310                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total       539310                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst       539310                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total       539310                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst       539310                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total       539310                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   6681305000                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total   6681305000                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   6681305000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total   6681305000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   6681305000                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total   6681305000                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.014087                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.014087                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.014087                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.014087                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.014087                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.014087                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12388.616936                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12388.616936                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12388.616936                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 12388.616936                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12388.616936                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 12388.616936                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       539174                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total       539174                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst       539174                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total       539174                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst       539174                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total       539174                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   6673548256                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total   6673548256                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   6673548256                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total   6673548256                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   6673548256                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total   6673548256                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.014083                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.014083                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.014083                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.014083                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.014083                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.014083                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12377.355466                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12377.355466                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12377.355466                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 12377.355466                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12377.355466                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 12377.355466                       # average overall mshr miss latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.dcache.tags.replacements           871224                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          481.747613                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs            9466123                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs           871736                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            10.858933                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.replacements           871192                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          481.742326                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs            9465806                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs           871704                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            10.858968                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle        108210250                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   481.747613                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.940913                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.940913                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   481.742326                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.940903                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.940903                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0          122                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          322                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0          125                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          319                       # Occupied blocks per task id
 system.cpu0.dcache.tags.age_task_id_blocks_1024::2           68                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses         42234072                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses        42234072                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data      5299987                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total        5299987                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data      3905819                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total       3905819                       # number of WriteReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       124795                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       124795                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       131586                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       131586                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data      9205806                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total         9205806                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data      9205806                       # number of overall hits
-system.cpu0.dcache.overall_hits::total        9205806                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data       645326                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total       645326                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data       224198                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total       224198                       # number of WriteReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         7833                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total         7833                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data          495                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total          495                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data       869524                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total        869524                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data       869524                       # number of overall misses
-system.cpu0.dcache.overall_misses::total       869524                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  23374169264                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total  23374169264                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data   9262123232                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total   9262123232                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    102899750                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total    102899750                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data      3567062                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total      3567062                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data  32636292496                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total  32636292496                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data  32636292496                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total  32636292496                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data      5945313                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total      5945313                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data      4130017                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total      4130017                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       132628                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       132628                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       132081                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       132081                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data     10075330                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     10075330                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data     10075330                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     10075330                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.108544                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.108544                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.054285                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.054285                       # miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.059060                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.059060                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.003748                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.003748                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.086302                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.086302                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.086302                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.086302                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 36220.715211                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 36220.715211                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 41312.247353                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 41312.247353                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13136.697306                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13136.697306                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data  7206.185859                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total  7206.185859                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 37533.515459                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 37533.515459                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 37533.515459                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 37533.515459                       # average overall miss latency
+system.cpu0.dcache.tags.tag_accesses         42232679                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses        42232679                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data      5299779                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total        5299779                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data      3905718                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total       3905718                       # number of WriteReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       124794                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       124794                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data       131579                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       131579                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data      9205497                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total         9205497                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data      9205497                       # number of overall hits
+system.cpu0.dcache.overall_hits::total        9205497                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data       645318                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total       645318                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data       224183                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total       224183                       # number of WriteReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         7829                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total         7829                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data          497                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total          497                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data       869501                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total        869501                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data       869501                       # number of overall misses
+system.cpu0.dcache.overall_misses::total       869501                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  23374202500                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total  23374202500                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data   9262527483                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total   9262527483                       # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    102834500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total    102834500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data      3584562                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total      3584562                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data  32636729983                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total  32636729983                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data  32636729983                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total  32636729983                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data      5945097                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total      5945097                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data      4129901                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total      4129901                       # number of WriteReq accesses(hits+misses)
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+system.cpu0.dcache.LoadLockedReq_accesses::total       132623                       # number of LoadLockedReq accesses(hits+misses)
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+system.cpu0.dcache.StoreCondReq_accesses::total       132076                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data     10074998                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     10074998                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data     10074998                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     10074998                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.108546                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.108546                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.054283                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.054283                       # miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.059032                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.059032                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.003763                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.003763                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.086303                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.086303                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.086303                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.086303                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 36221.215742                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 36221.215742                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 41316.814758                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 41316.814758                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13135.074722                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13135.074722                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data  7212.398390                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total  7212.398390                       # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 37535.011441                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 37535.011441                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 37535.011441                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 37535.011441                       # average overall miss latency
 system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1246,62 +1243,62 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       405192                       # number of writebacks
-system.cpu0.dcache.writebacks::total           405192                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       645326                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       645326                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       224198                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       224198                       # number of WriteReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         7833                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total         7833                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data          495                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total          495                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data       869524                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total       869524                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data       869524                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total       869524                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  21958342736                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total  21958342736                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   8764766768                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total   8764766768                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     87220250                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     87220250                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data      2576938                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total      2576938                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  30723109504                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  30723109504                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  30723109504                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  30723109504                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   1004924500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   1004924500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   1718153000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   1718153000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   2723077500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total   2723077500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.108544                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.108544                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.054285                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.054285                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.059060                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.059060                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.003748                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.003748                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.086302                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.086302                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.086302                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.086302                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 34026.744213                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 34026.744213                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 39093.866886                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 39093.866886                       # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11134.973829                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11134.973829                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data  5205.935354                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total  5205.935354                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 35333.250726                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 35333.250726                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 35333.250726                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 35333.250726                       # average overall mshr miss latency
+system.cpu0.dcache.writebacks::writebacks       405151                       # number of writebacks
+system.cpu0.dcache.writebacks::total           405151                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       645318                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total       645318                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       224183                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       224183                       # number of WriteReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         7829                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total         7829                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data          497                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total          497                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data       869501                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total       869501                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data       869501                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total       869501                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  21958327500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total  21958327500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   8765186517                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total   8765186517                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     87163500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     87163500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data      2590438                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total      2590438                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  30723514017                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  30723514017                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  30723514017                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  30723514017                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   1004927000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   1004927000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   1718158000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   1718158000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   2723085000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total   2723085000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.108546                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.108546                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.054283                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.054283                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.059032                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.059032                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.003763                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.003763                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.086303                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.086303                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.086303                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.086303                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 34027.142432                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 34027.142432                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 39098.354991                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 39098.354991                       # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11133.414229                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11133.414229                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data  5212.148893                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total  5212.148893                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 35334.650583                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 35334.650583                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 35334.650583                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 35334.650583                       # average overall mshr miss latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
@@ -1313,22 +1310,22 @@ system.cpu1.dtb.fetch_hits                          0                       # IT
 system.cpu1.dtb.fetch_misses                        0                       # ITB misses
 system.cpu1.dtb.fetch_acv                           0                       # ITB acv
 system.cpu1.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu1.dtb.read_hits                     3617105                       # DTB read hits
+system.cpu1.dtb.read_hits                     3617054                       # DTB read hits
 system.cpu1.dtb.read_misses                      2620                       # DTB read misses
 system.cpu1.dtb.read_acv                            0                       # DTB read access violations
 system.cpu1.dtb.read_accesses                  205337                       # DTB read accesses
-system.cpu1.dtb.write_hits                    2433899                       # DTB write hits
+system.cpu1.dtb.write_hits                    2433875                       # DTB write hits
 system.cpu1.dtb.write_misses                      235                       # DTB write misses
 system.cpu1.dtb.write_acv                          24                       # DTB write access violations
 system.cpu1.dtb.write_accesses                  89739                       # DTB write accesses
-system.cpu1.dtb.data_hits                     6051004                       # DTB hits
+system.cpu1.dtb.data_hits                     6050929                       # DTB hits
 system.cpu1.dtb.data_misses                      2855                       # DTB misses
 system.cpu1.dtb.data_acv                           24                       # DTB access violations
 system.cpu1.dtb.data_accesses                  295076                       # DTB accesses
-system.cpu1.itb.fetch_hits                    1988116                       # ITB hits
+system.cpu1.itb.fetch_hits                    1988100                       # ITB hits
 system.cpu1.itb.fetch_misses                     1064                       # ITB misses
 system.cpu1.itb.fetch_acv                           0                       # ITB acv
-system.cpu1.itb.fetch_accesses                1989180                       # ITB accesses
+system.cpu1.itb.fetch_accesses                1989164                       # ITB accesses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.read_acv                            0                       # DTB read access violations
@@ -1341,34 +1338,34 @@ system.cpu1.itb.data_hits                           0                       # DT
 system.cpu1.itb.data_misses                         0                       # DTB misses
 system.cpu1.itb.data_acv                            0                       # DTB access violations
 system.cpu1.itb.data_accesses                       0                       # DTB accesses
-system.cpu1.numCycles                      3923841481                       # number of cpu cycles simulated
+system.cpu1.numCycles                      3923841470                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                   21095606                       # Number of instructions committed
-system.cpu1.committedOps                     21095606                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses             19410796                       # Number of integer alu accesses
+system.cpu1.committedInsts                   21095754                       # Number of instructions committed
+system.cpu1.committedOps                     21095754                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses             19410964                       # Number of integer alu accesses
 system.cpu1.num_fp_alu_accesses                175175                       # Number of float alu accesses
-system.cpu1.num_func_calls                     648522                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts      2286515                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                    19410796                       # number of integer instructions
+system.cpu1.num_func_calls                     648514                       # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts      2286581                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                    19410964                       # number of integer instructions
 system.cpu1.num_fp_insts                       175175                       # number of float instructions
-system.cpu1.num_int_register_reads           26519930                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes          14289781                       # number of times the integer registers were written
+system.cpu1.num_int_register_reads           26520307                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes          14289908                       # number of times the integer registers were written
 system.cpu1.num_fp_register_reads               90745                       # number of times the floating registers were read
 system.cpu1.num_fp_register_writes              92744                       # number of times the floating registers were written
-system.cpu1.num_mem_refs                      6073244                       # number of memory refs
-system.cpu1.num_load_insts                    3630952                       # Number of load instructions
-system.cpu1.num_store_insts                   2442292                       # Number of store instructions
-system.cpu1.num_idle_cycles              3837671905.347151                       # Number of idle cycles
-system.cpu1.num_busy_cycles              86169575.652849                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.021961                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.978039                       # Percentage of idle cycles
-system.cpu1.Branches                          3164985                       # Number of branches fetched
-system.cpu1.op_class::No_OpClass              1250072      5.92%      5.92% # Class of executed instruction
-system.cpu1.op_class::IntAlu                 13187049     62.50%     68.43% # Class of executed instruction
-system.cpu1.op_class::IntMult                   30193      0.14%     68.57% # Class of executed instruction
+system.cpu1.num_mem_refs                      6073169                       # number of memory refs
+system.cpu1.num_load_insts                    3630901                       # Number of load instructions
+system.cpu1.num_store_insts                   2442268                       # Number of store instructions
+system.cpu1.num_idle_cycles              3837673362.965370                       # Number of idle cycles
+system.cpu1.num_busy_cycles              86168107.034630                       # Number of busy cycles
+system.cpu1.not_idle_fraction                0.021960                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                    0.978040                       # Percentage of idle cycles
+system.cpu1.Branches                          3165037                       # Number of branches fetched
+system.cpu1.op_class::No_OpClass              1250062      5.92%      5.92% # Class of executed instruction
+system.cpu1.op_class::IntAlu                 13186802     62.50%     68.43% # Class of executed instruction
+system.cpu1.op_class::IntMult                   30198      0.14%     68.57% # Class of executed instruction
 system.cpu1.op_class::IntDiv                        0      0.00%     68.57% # Class of executed instruction
-system.cpu1.op_class::FloatAdd                  13163      0.06%     68.63% # Class of executed instruction
+system.cpu1.op_class::FloatAdd                  13644      0.06%     68.63% # Class of executed instruction
 system.cpu1.op_class::FloatCmp                      0      0.00%     68.63% # Class of executed instruction
 system.cpu1.op_class::FloatCvt                      0      0.00%     68.63% # Class of executed instruction
 system.cpu1.op_class::FloatMult                     0      0.00%     68.63% # Class of executed instruction
@@ -1394,34 +1391,34 @@ system.cpu1.op_class::SimdFloatMisc                 0      0.00%     68.64% # Cl
 system.cpu1.op_class::SimdFloatMult                 0      0.00%     68.64% # Class of executed instruction
 system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     68.64% # Class of executed instruction
 system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     68.64% # Class of executed instruction
-system.cpu1.op_class::MemRead                 3726131     17.66%     86.30% # Class of executed instruction
-system.cpu1.op_class::MemWrite                2443312     11.58%     97.88% # Class of executed instruction
-system.cpu1.op_class::IprAccess                446806      2.12%    100.00% # Class of executed instruction
+system.cpu1.op_class::MemRead                 3726078     17.66%     86.30% # Class of executed instruction
+system.cpu1.op_class::MemWrite                2443288     11.58%     97.88% # Class of executed instruction
+system.cpu1.op_class::IprAccess                446802      2.12%    100.00% # Class of executed instruction
 system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu1.op_class::total                  21098485                       # Class of executed instruction
+system.cpu1.op_class::total                  21098633                       # Class of executed instruction
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu1.kern.inst.quiesce                    3863                       # number of quiesce instructions executed
-system.cpu1.kern.inst.hwrei                    100735                       # number of hwrei instructions executed
-system.cpu1.kern.ipl_count::0                   37219     40.29%     40.29% # number of times we switched to this ipl
+system.cpu1.kern.inst.hwrei                    100733                       # number of hwrei instructions executed
+system.cpu1.kern.ipl_count::0                   37218     40.29%     40.29% # number of times we switched to this ipl
 system.cpu1.kern.ipl_count::22                   1970      2.13%     42.42% # number of times we switched to this ipl
 system.cpu1.kern.ipl_count::30                     86      0.09%     42.51% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::31                  53109     57.49%    100.00% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::total               92384                       # number of times we switched to this ipl
-system.cpu1.kern.ipl_good::0                    36367     48.68%     48.68% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_count::31                  53108     57.49%    100.00% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::total               92382                       # number of times we switched to this ipl
+system.cpu1.kern.ipl_good::0                    36366     48.68%     48.68% # number of times we switched to this ipl from a different ipl
 system.cpu1.kern.ipl_good::22                    1970      2.64%     51.32% # number of times we switched to this ipl from a different ipl
 system.cpu1.kern.ipl_good::30                      86      0.12%     51.43% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::31                   36281     48.57%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::total                74704                       # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_ticks::0            1906656399000     97.18%     97.18% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::22              706249000      0.04%     97.22% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_good::31                   36280     48.57%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::total                74702                       # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_ticks::0            1906657223000     97.18%     97.18% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::22              706239500      0.04%     97.22% # number of cycles we spent at this ipl
 system.cpu1.kern.ipl_ticks::30               59367000      0.00%     97.22% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::31            54498695500      2.78%    100.00% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::total        1961920710500                       # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::31            54497875500      2.78%    100.00% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::total        1961920705000                       # number of cycles we spent at this ipl
 system.cpu1.kern.ipl_used::0                 0.977108                       # fraction of swpipl calls that actually changed the ipl
 system.cpu1.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu1.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::31                0.683142                       # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::total             0.808625                       # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.ipl_used::31                0.683136                       # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.ipl_used::total             0.808621                       # fraction of swpipl calls that actually changed the ipl
 system.cpu1.kern.syscall::3                        10     10.87%     10.87% # number of syscalls executed
 system.cpu1.kern.syscall::6                         9      9.78%     20.65% # number of syscalls executed
 system.cpu1.kern.syscall::15                        1      1.09%     21.74% # number of syscalls executed
@@ -1443,7 +1440,7 @@ system.cpu1.kern.callpal::wrfen                     1      0.00%      0.02% # nu
 system.cpu1.kern.callpal::swpctx                 2020      2.13%      2.15% # number of callpals executed
 system.cpu1.kern.callpal::tbi                       3      0.00%      2.16% # number of callpals executed
 system.cpu1.kern.callpal::wrent                     7      0.01%      2.16% # number of callpals executed
-system.cpu1.kern.callpal::swpipl                87061     91.90%     94.06% # number of callpals executed
+system.cpu1.kern.callpal::swpipl                87059     91.90%     94.06% # number of callpals executed
 system.cpu1.kern.callpal::rdps                   2187      2.31%     96.37% # number of callpals executed
 system.cpu1.kern.callpal::wrkgp                     1      0.00%     96.37% # number of callpals executed
 system.cpu1.kern.callpal::wrusp                     3      0.00%     96.38% # number of callpals executed
@@ -1452,72 +1449,72 @@ system.cpu1.kern.callpal::rti                    3266      3.45%     99.83% # nu
 system.cpu1.kern.callpal::callsys                 121      0.13%     99.95% # number of callpals executed
 system.cpu1.kern.callpal::imb                      42      0.04%    100.00% # number of callpals executed
 system.cpu1.kern.callpal::rdunique                  1      0.00%    100.00% # number of callpals executed
-system.cpu1.kern.callpal::total                 94734                       # number of callpals executed
+system.cpu1.kern.callpal::total                 94732                       # number of callpals executed
 system.cpu1.kern.mode_switch::kernel             2415                       # number of protection mode switches
-system.cpu1.kern.mode_switch::user                366                       # number of protection mode switches
+system.cpu1.kern.mode_switch::user                367                       # number of protection mode switches
 system.cpu1.kern.mode_switch::idle               2037                       # number of protection mode switches
-system.cpu1.kern.mode_good::kernel                414                      
-system.cpu1.kern.mode_good::user                  366                      
+system.cpu1.kern.mode_good::kernel                415                      
+system.cpu1.kern.mode_good::user                  367                      
 system.cpu1.kern.mode_good::idle                   48                      
-system.cpu1.kern.mode_switch_good::kernel     0.171429                       # fraction of useful protection mode switches
+system.cpu1.kern.mode_switch_good::kernel     0.171843                       # fraction of useful protection mode switches
 system.cpu1.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
 system.cpu1.kern.mode_switch_good::idle      0.023564                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::total     0.171856                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_ticks::kernel       65780447000      3.35%      3.35% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::user          1486717000      0.08%      3.43% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::idle        1893764152500     96.57%    100.00% # number of ticks spent at the given mode
+system.cpu1.kern.mode_switch_good::total     0.172235                       # fraction of useful protection mode switches
+system.cpu1.kern.mode_ticks::kernel       65779284000      3.35%      3.35% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::user          1486343500      0.08%      3.43% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::idle        1893759051500     96.57%    100.00% # number of ticks spent at the given mode
 system.cpu1.kern.swap_context                    2021                       # number of times the context was actually changed
-system.cpu1.icache.tags.replacements           463064                       # number of replacements
-system.cpu1.icache.tags.tagsinuse          500.061225                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs           20634869                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs           463576                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs            44.512376                       # Average number of references to valid blocks.
+system.cpu1.icache.tags.replacements           463035                       # number of replacements
+system.cpu1.icache.tags.tagsinuse          500.061178                       # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs           20635046                       # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs           463547                       # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs            44.515542                       # Average number of references to valid blocks.
 system.cpu1.icache.tags.warmup_cycle      97712638250                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst   500.061225                       # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_blocks::cpu1.inst   500.061178                       # Average occupied blocks per requestor
 system.cpu1.icache.tags.occ_percent::cpu1.inst     0.976682                       # Average percentage of cache occupancy
 system.cpu1.icache.tags.occ_percent::total     0.976682                       # Average percentage of cache occupancy
 system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu1.icache.tags.age_task_id_blocks_1024::2          108                       # Occupied blocks per task id
 system.cpu1.icache.tags.age_task_id_blocks_1024::3          404                       # Occupied blocks per task id
 system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses         21562101                       # Number of tag accesses
-system.cpu1.icache.tags.data_accesses        21562101                       # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst     20634869                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total       20634869                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst     20634869                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total        20634869                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst     20634869                       # number of overall hits
-system.cpu1.icache.overall_hits::total       20634869                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst       463616                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total       463616                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst       463616                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total        463616                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst       463616                       # number of overall misses
-system.cpu1.icache.overall_misses::total       463616                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   6201828741                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total   6201828741                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst   6201828741                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total   6201828741                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst   6201828741                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total   6201828741                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst     21098485                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total     21098485                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst     21098485                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total     21098485                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst     21098485                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total     21098485                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.021974                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.021974                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.021974                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.021974                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.021974                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.021974                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13377.080905                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 13377.080905                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13377.080905                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 13377.080905                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13377.080905                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 13377.080905                       # average overall miss latency
+system.cpu1.icache.tags.tag_accesses         21562220                       # Number of tag accesses
+system.cpu1.icache.tags.data_accesses        21562220                       # Number of data accesses
+system.cpu1.icache.ReadReq_hits::cpu1.inst     20635046                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total       20635046                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst     20635046                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total        20635046                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst     20635046                       # number of overall hits
+system.cpu1.icache.overall_hits::total       20635046                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst       463587                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total       463587                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst       463587                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total        463587                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst       463587                       # number of overall misses
+system.cpu1.icache.overall_misses::total       463587                       # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   6202855739                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total   6202855739                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst   6202855739                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total   6202855739                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst   6202855739                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total   6202855739                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst     21098633                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total     21098633                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst     21098633                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total     21098633                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst     21098633                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total     21098633                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.021972                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.021972                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.021972                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.021972                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.021972                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.021972                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13380.133047                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 13380.133047                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13380.133047                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 13380.133047                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13380.133047                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 13380.133047                       # average overall miss latency
 system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1526,118 +1523,118 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       463616                       # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total       463616                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst       463616                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total       463616                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst       463616                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total       463616                       # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   5273752259                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total   5273752259                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   5273752259                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total   5273752259                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   5273752259                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total   5273752259                       # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.021974                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.021974                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.021974                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.021974                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.021974                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.021974                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11375.259394                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11375.259394                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11375.259394                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 11375.259394                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11375.259394                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 11375.259394                       # average overall mshr miss latency
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       463587                       # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total       463587                       # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst       463587                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total       463587                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst       463587                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total       463587                       # number of overall MSHR misses
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   5274833261                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total   5274833261                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   5274833261                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total   5274833261                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   5274833261                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total   5274833261                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.021972                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.021972                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.021972                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total     0.021972                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.021972                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total     0.021972                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11378.302802                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11378.302802                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11378.302802                       # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total 11378.302802                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11378.302802                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total 11378.302802                       # average overall mshr miss latency
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.dcache.tags.replacements           581734                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse          492.027113                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs            5462976                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs           582077                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs             9.385315                       # Average number of references to valid blocks.
+system.cpu1.dcache.tags.replacements           581700                       # number of replacements
+system.cpu1.dcache.tags.tagsinuse          492.027042                       # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs            5462019                       # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs           582040                       # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs             9.384267                       # Average number of references to valid blocks.
 system.cpu1.dcache.tags.warmup_cycle      61159690250                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data   492.027113                       # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_blocks::cpu1.data   492.027042                       # Average occupied blocks per requestor
 system.cpu1.dcache.tags.occ_percent::cpu1.data     0.960990                       # Average percentage of cache occupancy
 system.cpu1.dcache.tags.occ_percent::total     0.960990                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024          343                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2           43                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::3          300                       # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024     0.669922                       # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses         24828652                       # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses        24828652                       # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data      3080166                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total        3080166                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data      2260006                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total       2260006                       # number of WriteReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        60928                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total        60928                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data        71558                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total        71558                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data      5340172                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total         5340172                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data      5340172                       # number of overall hits
-system.cpu1.dcache.overall_hits::total        5340172                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data       473210                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total       473210                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data       102503                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total       102503                       # number of WriteReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        11672                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total        11672                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data          567                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total          567                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data       575713                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total        575713                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data       575713                       # number of overall misses
-system.cpu1.dcache.overall_misses::total       575713                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   5938920500                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total   5938920500                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   2340100234                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total   2340100234                       # number of WriteReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    149905750                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total    149905750                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data      4163080                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total      4163080                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data   8279020734                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total   8279020734                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data   8279020734                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total   8279020734                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data      3553376                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total      3553376                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data      2362509                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total      2362509                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        72600                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total        72600                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        72125                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total        72125                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data      5915885                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total      5915885                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data      5915885                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total      5915885                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.133172                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.133172                       # miss rate for ReadReq accesses
+system.cpu1.dcache.tags.occ_task_id_blocks::1024          340                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2           42                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::3          298                       # Occupied blocks per task id
+system.cpu1.dcache.tags.occ_task_id_percent::1024     0.664062                       # Percentage of cache occupancy per task id
+system.cpu1.dcache.tags.tag_accesses         24828314                       # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses        24828314                       # Number of data accesses
+system.cpu1.dcache.ReadReq_hits::cpu1.data      3080149                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total        3080149                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data      2259986                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total       2259986                       # number of WriteReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        60927                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total        60927                       # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data        71555                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total        71555                       # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data      5340135                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total         5340135                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data      5340135                       # number of overall hits
+system.cpu1.dcache.overall_hits::total        5340135                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data       473178                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total       473178                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data       102501                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total       102501                       # number of WriteReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        11671                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total        11671                       # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data          568                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total          568                       # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data       575679                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total        575679                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data       575679                       # number of overall misses
+system.cpu1.dcache.overall_misses::total       575679                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   5938208750                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total   5938208750                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   2338814234                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total   2338814234                       # number of WriteReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    149892750                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total    149892750                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data      4181580                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total      4181580                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data   8277022984                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total   8277022984                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data   8277022984                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total   8277022984                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data      3553327                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total      3553327                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data      2362487                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total      2362487                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        72598                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total        72598                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        72123                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total        72123                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data      5915814                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total      5915814                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data      5915814                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total      5915814                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.133165                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.133165                       # miss rate for ReadReq accesses
 system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.043387                       # miss rate for WriteReq accesses
 system.cpu1.dcache.WriteReq_miss_rate::total     0.043387                       # miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.160771                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.160771                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.007861                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total     0.007861                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.097316                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.097316                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.097316                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.097316                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12550.285286                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 12550.285286                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22829.578003                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 22829.578003                       # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12843.193112                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 12843.193112                       # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data  7342.292769                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total  7342.292769                       # average StoreCondReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14380.465152                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 14380.465152                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14380.465152                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 14380.465152                       # average overall miss latency
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.160762                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.160762                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.007875                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total     0.007875                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.097312                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.097312                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.097312                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.097312                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12549.629843                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 12549.629843                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22817.477234                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 22817.477234                       # average WriteReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12843.179676                       # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 12843.179676                       # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data  7361.936620                       # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total  7361.936620                       # average StoreCondReq miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14377.844222                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 14377.844222                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14377.844222                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 14377.844222                       # average overall miss latency
 system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1646,62 +1643,62 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks       444943                       # number of writebacks
-system.cpu1.dcache.writebacks::total           444943                       # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       473210                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total       473210                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data       102503                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total       102503                       # number of WriteReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data        11672                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total        11672                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data          567                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total          567                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data       575713                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total       575713                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data       575713                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total       575713                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   4992146500                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total   4992146500                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   2128603766                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total   2128603766                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data    126561250                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total    126561250                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data      3028920                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total      3028920                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   7120750266                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total   7120750266                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   7120750266                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total   7120750266                       # number of overall MSHR miss cycles
+system.cpu1.dcache.writebacks::writebacks       444927                       # number of writebacks
+system.cpu1.dcache.writebacks::total           444927                       # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       473178                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total       473178                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data       102501                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total       102501                       # number of WriteReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data        11671                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total        11671                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data          568                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total          568                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data       575679                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total       575679                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data       575679                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total       575679                       # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   4991497250                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total   4991497250                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   2127317766                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total   2127317766                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data    126550250                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total    126550250                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data      3045420                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total      3045420                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   7118815016                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total   7118815016                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   7118815016                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total   7118815016                       # number of overall MSHR miss cycles
 system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    479658500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total    479658500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    907861000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    907861000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   1387519500                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total   1387519500                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.133172                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.133172                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    907862000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    907862000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   1387520500                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total   1387520500                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.133165                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.133165                       # mshr miss rate for ReadReq accesses
 system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.043387                       # mshr miss rate for WriteReq accesses
 system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.043387                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.160771                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.160771                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.007861                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.007861                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.097316                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.097316                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.097316                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.097316                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10549.537203                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10549.537203                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 20766.258217                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 20766.258217                       # average WriteReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 10843.150274                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10843.150274                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data  5342.010582                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total  5342.010582                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12368.576471                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12368.576471                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12368.576471                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12368.576471                       # average overall mshr miss latency
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.160762                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.160762                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.007875                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.007875                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.097312                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total     0.097312                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.097312                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total     0.097312                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10548.878540                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10548.878540                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 20754.117189                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 20754.117189                       # average WriteReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 10843.136835                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10843.136835                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data  5361.654930                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total  5361.654930                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12365.945285                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12365.945285                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12365.945285                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12365.945285                       # average overall mshr miss latency
 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
index 24f1d16b8..7916cb036 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
@@ -1,127 +1,130 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  1.919447                       # Number of seconds simulated
-sim_ticks                                1919446558000                       # Number of ticks simulated
-final_tick                               1919446558000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  1.919439                       # Number of seconds simulated
+sim_ticks                                1919438772000                       # Number of ticks simulated
+final_tick                               1919438772000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 885398                       # Simulator instruction rate (inst/s)
-host_op_rate                                   885398                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            30291378157                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 344696                       # Number of bytes of host memory used
-host_seconds                                    63.37                       # Real time elapsed on the host
-sim_insts                                    56104177                       # Number of instructions simulated
-sim_ops                                      56104177                       # Number of ops (including micro ops) simulated
+host_inst_rate                                1398299                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1398299                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            47840414078                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 314348                       # Number of bytes of host memory used
+host_seconds                                    40.12                       # Real time elapsed on the host
+sim_insts                                    56102112                       # Number of instructions simulated
+sim_ops                                      56102112                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            850752                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          24858240                       # Number of bytes read from this memory
-system.physmem.bytes_read::tsunami.ide        2652352                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             28361344                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       850752                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          850752                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7404032                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7404032                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst              13293                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             388410                       # Number of read requests responded to by this memory
-system.physmem.num_reads::tsunami.ide           41443                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                443146                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          115688                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               115688                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               443228                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             12950733                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::tsunami.ide           1381832                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                14775792                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          443228                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             443228                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           3857379                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                3857379                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           3857379                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              443228                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            12950733                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::tsunami.ide          1381832                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               18633171                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        443146                       # Number of read requests accepted
-system.physmem.writeReqs                       115688                       # Number of write requests accepted
-system.physmem.readBursts                      443146                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     115688                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 28353856                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      7488                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   7402304                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  28361344                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                7404032                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      117                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytes_read::cpu.inst            850816                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          24875968                       # Number of bytes read from this memory
+system.physmem.bytes_read::tsunami.ide            960                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             25727744                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       850816                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          850816                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      4747712                       # Number of bytes written to this memory
+system.physmem.bytes_written::tsunami.ide      2659328                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7407040                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst              13294                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             388687                       # Number of read requests responded to by this memory
+system.physmem.num_reads::tsunami.ide              15                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                401996                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           74183                       # Number of write requests responded to by this memory
+system.physmem.num_writes::tsunami.ide          41552                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               115735                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst               443263                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             12960022                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::tsunami.ide               500                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                13403785                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          443263                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             443263                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           2473490                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::tsunami.ide          1385472                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                3858961                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           2473490                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              443263                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            12960022                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::tsunami.ide          1385972                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               17262746                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        401996                       # Number of read requests accepted
+system.physmem.writeReqs                       115735                       # Number of write requests accepted
+system.physmem.readBursts                      401996                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     115735                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 25716224                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     11520                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   7405312                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  25727744                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                7407040                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      180                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs            130                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               27768                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               28019                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               28336                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               28020                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               27518                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               27546                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               26737                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               26852                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               27860                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               27104                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              27841                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              27413                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              27378                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              28201                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              28236                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              28200                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs            132                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               25161                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               25541                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               25618                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               25537                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               24981                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               24976                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               24228                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               24506                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               25159                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               24820                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              25363                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              24840                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              24420                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              25388                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              25795                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              25483                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                7550                       # Per bank write bursts
 system.physmem.perBankWrBursts::1                7529                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                7869                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                7540                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                7880                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                7553                       # Per bank write bursts
 system.physmem.perBankWrBursts::4                7115                       # Per bank write bursts
 system.physmem.perBankWrBursts::5                6983                       # Per bank write bursts
 system.physmem.perBankWrBursts::6                6321                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                6313                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                6319                       # Per bank write bursts
 system.physmem.perBankWrBursts::8                7293                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                6538                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                6554                       # Per bank write bursts
 system.physmem.perBankWrBursts::10               7205                       # Per bank write bursts
 system.physmem.perBankWrBursts::11               6861                       # Per bank write bursts
 system.physmem.perBankWrBursts::12               6964                       # Per bank write bursts
 system.physmem.perBankWrBursts::13               7821                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               7979                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               7980                       # Per bank write bursts
 system.physmem.perBankWrBursts::15               7780                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                          11                       # Number of times write queue was full causing retry
-system.physmem.totGap                    1919434637000                       # Total gap between requests
+system.physmem.totGap                    1919426851000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  443146                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  401996                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 115688                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    401962                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      1642                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                      2685                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                      1248                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                      1966                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                      4407                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                      3974                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                      3974                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                      2507                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                      2187                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                     2134                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                     2102                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                     1622                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                     1616                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                     1907                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                     1876                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                     2136                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                     1224                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                      966                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                      883                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                       11                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 115735                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    401802                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                         1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                         1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                         1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                         1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                         1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                         1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                         1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
@@ -148,278 +151,267 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     1354                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     1478                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     4562                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     4579                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     4593                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     4592                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     4608                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     4699                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     4858                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     4946                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     5128                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     5346                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     5326                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     5448                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     5540                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     5685                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     5621                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     5715                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      897                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      915                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      934                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      861                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      945                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      959                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                     1033                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      949                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                     1139                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                     1162                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                     1146                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                     1232                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                     1390                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                     1625                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                     1897                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                     2098                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                     1909                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                     1878                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                     1683                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                     1684                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                     1800                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                     1629                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                      867                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                      418                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                      235                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                      155                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       52                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       41                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       26                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       18                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       18                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        66429                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      538.261302                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     328.855989                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     417.099114                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          14887     22.41%     22.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        11472     17.27%     39.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         4684      7.05%     46.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3132      4.71%     51.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         3072      4.62%     56.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1874      2.82%     58.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1342      2.02%     60.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1444      2.17%     63.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        24522     36.91%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          66429                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          6775                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        65.389077                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::gmean       16.529238                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev     2564.130292                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-8191           6772     99.96%     99.96% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::40960-49151            1      0.01%     99.97% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::57344-65535            1      0.01%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::196608-204799            1      0.01%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            6775                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          6775                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        17.071734                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.848509                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        3.695111                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16               5062     74.72%     74.72% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17                127      1.87%     76.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18               1207     17.82%     94.41% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19                 25      0.37%     94.77% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                 12      0.18%     94.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21                 16      0.24%     95.19% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22                 18      0.27%     95.45% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23                 98      1.45%     96.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24                 22      0.32%     97.23% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::25                 41      0.61%     97.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26                 20      0.30%     98.13% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::27                  8      0.12%     98.24% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28                  7      0.10%     98.35% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::29                  8      0.12%     98.46% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::30                  7      0.10%     98.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::31                 15      0.22%     98.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32                  9      0.13%     98.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::33                  1      0.01%     98.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::34                  1      0.01%     98.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::35                  1      0.01%     98.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::37                  1      0.01%     98.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::38                  1      0.01%     99.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::39                  4      0.06%     99.06% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40                  9      0.13%     99.19% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::41                  8      0.12%     99.31% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::42                  2      0.03%     99.34% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::43                  2      0.03%     99.37% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44                  2      0.03%     99.39% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::45                  1      0.01%     99.41% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::46                  1      0.01%     99.42% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::47                  8      0.12%     99.54% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48                  7      0.10%     99.65% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::49                  1      0.01%     99.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::50                  2      0.03%     99.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::51                  2      0.03%     99.72% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52                  1      0.01%     99.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::54                  1      0.01%     99.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56                  7      0.10%     99.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::57                  9      0.13%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::59                  1      0.01%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            6775                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     7315796250                       # Total ticks spent queuing
-system.physmem.totMemAccLat               15622590000                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   2215145000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       16513.13                       # Average queueing delay per DRAM burst
+system.physmem.wrQLenPdf::15                     1859                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     2606                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     5607                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     5735                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     5978                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     6706                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     6976                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     8149                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     8460                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     8432                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     8109                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     8281                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     6824                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     6355                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     5592                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     5334                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     5330                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     5306                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      213                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      190                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      175                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      156                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      153                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      129                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      122                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      128                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      172                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      155                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      170                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      198                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      218                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      205                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      182                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      176                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      146                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                      120                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                      111                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                      104                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                      111                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                      122                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                      116                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                      111                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                      111                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                       94                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                       70                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                       53                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                       30                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       16                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                       24                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        63869                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      518.585480                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     313.979775                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     413.923527                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          14875     23.29%     23.29% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        11515     18.03%     41.32% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         4721      7.39%     48.71% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3142      4.92%     53.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         3018      4.73%     58.36% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1863      2.92%     61.27% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1301      2.04%     63.31% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1404      2.20%     65.51% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        22030     34.49%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          63869                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          5101                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        78.768477                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev     2955.016496                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-8191           5098     99.94%     99.94% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::40960-49151            1      0.02%     99.96% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::57344-65535            1      0.02%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::196608-204799            1      0.02%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total            5101                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          5101                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        22.683395                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       19.235797                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       21.276820                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            4452     87.28%     87.28% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23              22      0.43%     87.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27              15      0.29%     88.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31             224      4.39%     92.39% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35              41      0.80%     93.20% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39               6      0.12%     93.32% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43               9      0.18%     93.49% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47               7      0.14%     93.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51              19      0.37%     94.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55               2      0.04%     94.04% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59               4      0.08%     94.12% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63               2      0.04%     94.16% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67              11      0.22%     94.37% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71               3      0.06%     94.43% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75               7      0.14%     94.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83              30      0.59%     95.16% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87              13      0.25%     95.41% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91               3      0.06%     95.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95               1      0.02%     95.49% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99             166      3.25%     98.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103            10      0.20%     98.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115             2      0.04%     98.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-123             6      0.12%     99.10% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131             4      0.08%     99.18% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135             2      0.04%     99.22% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-139             6      0.12%     99.33% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143             9      0.18%     99.51% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147             9      0.18%     99.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::148-151             1      0.02%     99.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-155             3      0.06%     99.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159             2      0.04%     99.80% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-163             3      0.06%     99.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::164-167             1      0.02%     99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::168-171             1      0.02%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::220-223             1      0.02%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::224-227             4      0.08%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            5101                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     2117396500                       # Total ticks spent queuing
+system.physmem.totMemAccLat                9651446500                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   2009080000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        5269.57                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  35263.13                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          14.77                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  24019.57                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          13.40                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           3.86                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       14.78                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       13.40                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        3.86                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           0.15                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       0.12                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                           0.13                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       0.10                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.01                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        23.40                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     398273                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     93988                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   89.90                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  81.24                       # Row buffer hit rate for writes
-system.physmem.avgGap                      3434713.42                       # Average gap between requests
-system.physmem.pageHitRate                      88.11                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE     1800016178000                       # Time in different power states
-system.physmem.memoryStateTime::REF       64094420000                       # Time in different power states
+system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        23.42                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     360116                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     93539                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   89.62                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  80.82                       # Row buffer hit rate for writes
+system.physmem.avgGap                      3707382.50                       # Average gap between requests
+system.physmem.pageHitRate                      87.65                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE     1800046548500                       # Time in different power states
+system.physmem.memoryStateTime::REF       64094160000                       # Time in different power states
 system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT       55332653250                       # Time in different power states
+system.physmem.memoryStateTime::ACT       55294756500                       # Time in different power states
 system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.membus.throughput                     18674823                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq              292356                       # Transaction distribution
-system.membus.trans_dist::ReadResp             292356                       # Transaction distribution
+system.membus.throughput                     17291227                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq              292357                       # Transaction distribution
+system.membus.trans_dist::ReadResp             292357                       # Transaction distribution
 system.membus.trans_dist::WriteReq               9649                       # Transaction distribution
 system.membus.trans_dist::WriteResp              9649                       # Transaction distribution
-system.membus.trans_dist::Writeback            115688                       # Transaction distribution
+system.membus.trans_dist::Writeback             74183                       # Transaction distribution
+system.membus.trans_dist::WriteInvalidateReq        41552                       # Transaction distribution
+system.membus.trans_dist::WriteInvalidateResp        41552                       # Transaction distribution
 system.membus.trans_dist::UpgradeReq              132                       # Transaction distribution
 system.membus.trans_dist::UpgradeResp             132                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            158273                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           158273                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            116727                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           116727                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave        33158                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       878115                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total       911273                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       124680                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       124680                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1035953                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       878409                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total       911567                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        83292                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total        83292                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 994859                       # Packet count per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave        44556                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     30456256                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total     30500812                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port      5309120                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::total      5309120                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total            35809932                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus               35809932                       # Total data (bytes)
-system.membus.snoop_data_through_bus            35392                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy            32376000                       # Layer occupancy (ticks)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     30474496                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total     30519052                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port      2660288                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.iocache.mem_side::total      2660288                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total            33179340                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus               33179340                       # Total data (bytes)
+system.membus.snoop_data_through_bus            10112                       # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy            32375500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy          1491996000                       # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy          1450892000                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.1                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         3751677600                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         3751806368                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
-system.membus.respLayer2.occupancy          376660500                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy           43113000                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
 system.iocache.tags.replacements                41685                       # number of replacements
-system.iocache.tags.tagsinuse                1.344872                       # Cycle average of tags in use
+system.iocache.tags.tagsinuse                1.344805                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs                41701                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         1753525004000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::tsunami.ide     1.344872                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::tsunami.ide     0.084054                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.084054                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         1753524887000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::tsunami.ide     1.344805                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::tsunami.ide     0.084050                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.084050                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
 system.iocache.tags.tag_accesses               375525                       # Number of tag accesses
 system.iocache.tags.data_accesses              375525                       # Number of data accesses
+system.iocache.WriteInvalidateReq_hits::tsunami.ide        41552                       # number of WriteInvalidateReq hits
+system.iocache.WriteInvalidateReq_hits::total        41552                       # number of WriteInvalidateReq hits
 system.iocache.ReadReq_misses::tsunami.ide          173                       # number of ReadReq misses
 system.iocache.ReadReq_misses::total              173                       # number of ReadReq misses
-system.iocache.WriteReq_misses::tsunami.ide        41552                       # number of WriteReq misses
-system.iocache.WriteReq_misses::total           41552                       # number of WriteReq misses
-system.iocache.demand_misses::tsunami.ide        41725                       # number of demand (read+write) misses
-system.iocache.demand_misses::total             41725                       # number of demand (read+write) misses
-system.iocache.overall_misses::tsunami.ide        41725                       # number of overall misses
-system.iocache.overall_misses::total            41725                       # number of overall misses
-system.iocache.ReadReq_miss_latency::tsunami.ide     21253133                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     21253133                       # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency::tsunami.ide  12447285431                       # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_latency::total  12447285431                       # number of WriteReq miss cycles
-system.iocache.demand_miss_latency::tsunami.ide  12468538564                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total  12468538564                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::tsunami.ide  12468538564                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total  12468538564                       # number of overall miss cycles
+system.iocache.demand_misses::tsunami.ide          173                       # number of demand (read+write) misses
+system.iocache.demand_misses::total               173                       # number of demand (read+write) misses
+system.iocache.overall_misses::tsunami.ide          173                       # number of overall misses
+system.iocache.overall_misses::total              173                       # number of overall misses
+system.iocache.ReadReq_miss_latency::tsunami.ide     21133383                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     21133383                       # number of ReadReq miss cycles
+system.iocache.demand_miss_latency::tsunami.ide     21133383                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total     21133383                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::tsunami.ide     21133383                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total     21133383                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::tsunami.ide          173                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            173                       # number of ReadReq accesses(hits+misses)
-system.iocache.WriteReq_accesses::tsunami.ide        41552                       # number of WriteReq accesses(hits+misses)
-system.iocache.WriteReq_accesses::total         41552                       # number of WriteReq accesses(hits+misses)
-system.iocache.demand_accesses::tsunami.ide        41725                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total           41725                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::tsunami.ide        41725                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total          41725                       # number of overall (read+write) accesses
+system.iocache.WriteInvalidateReq_accesses::tsunami.ide        41552                       # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::total        41552                       # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.demand_accesses::tsunami.ide          173                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total             173                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::tsunami.ide          173                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total            173                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
-system.iocache.WriteReq_miss_rate::tsunami.ide            1                       # miss rate for WriteReq accesses
-system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
 system.iocache.demand_miss_rate::tsunami.ide            1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122850.479769                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 122850.479769                       # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::tsunami.ide 299559.237365                       # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total 299559.237365                       # average WriteReq miss latency
-system.iocache.demand_avg_miss_latency::tsunami.ide 298826.568340                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 298826.568340                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::tsunami.ide 298826.568340                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 298826.568340                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs        365803                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122158.283237                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 122158.283237                       # average ReadReq miss latency
+system.iocache.demand_avg_miss_latency::tsunami.ide 122158.283237                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 122158.283237                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::tsunami.ide 122158.283237                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 122158.283237                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                28265                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs    12.941907                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.fast_writes                          0                       # number of fast writes performed
+system.iocache.fast_writes                      41552                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.writebacks::writebacks           41512                       # number of writebacks
-system.iocache.writebacks::total                41512                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::tsunami.ide          173                       # number of ReadReq MSHR misses
 system.iocache.ReadReq_mshr_misses::total          173                       # number of ReadReq MSHR misses
-system.iocache.WriteReq_mshr_misses::tsunami.ide        41552                       # number of WriteReq MSHR misses
-system.iocache.WriteReq_mshr_misses::total        41552                       # number of WriteReq MSHR misses
-system.iocache.demand_mshr_misses::tsunami.ide        41725                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total        41725                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::tsunami.ide        41725                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total        41725                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     12255133                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     12255133                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::tsunami.ide  10284312431                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::total  10284312431                       # number of WriteReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::tsunami.ide  10296567564                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total  10296567564                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::tsunami.ide  10296567564                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total  10296567564                       # number of overall MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide        41552                       # number of WriteInvalidateReq MSHR misses
+system.iocache.WriteInvalidateReq_mshr_misses::total        41552                       # number of WriteInvalidateReq MSHR misses
+system.iocache.demand_mshr_misses::tsunami.ide          173                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total          173                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::tsunami.ide          173                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total          173                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     12136383                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     12136383                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide   2506570306                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::total   2506570306                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::tsunami.ide     12136383                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total     12136383                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::tsunami.ide     12136383                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total     12136383                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
-system.iocache.WriteReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteReq accesses
-system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
+system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteInvalidateReq accesses
 system.iocache.demand_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for demand accesses
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70838.919075                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 70838.919075                       # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 247504.631089                       # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total 247504.631089                       # average WriteReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 246772.140539                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 246772.140539                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 246772.140539                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 246772.140539                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70152.502890                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 70152.502890                       # average ReadReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 60323.698161                       # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60323.698161                       # average WriteInvalidateReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70152.502890                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 70152.502890                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70152.502890                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 70152.502890                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
@@ -438,22 +430,22 @@ system.cpu.dtb.fetch_hits                           0                       # IT
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                      9052923                       # DTB read hits
-system.cpu.dtb.read_misses                      10354                       # DTB read misses
+system.cpu.dtb.read_hits                      9052614                       # DTB read hits
+system.cpu.dtb.read_misses                      10356                       # DTB read misses
 system.cpu.dtb.read_acv                           210                       # DTB read access violations
-system.cpu.dtb.read_accesses                   728911                       # DTB read accesses
-system.cpu.dtb.write_hits                     6349403                       # DTB write hits
-system.cpu.dtb.write_misses                      1143                       # DTB write misses
+system.cpu.dtb.read_accesses                   728915                       # DTB read accesses
+system.cpu.dtb.write_hits                     6349217                       # DTB write hits
+system.cpu.dtb.write_misses                      1144                       # DTB write misses
 system.cpu.dtb.write_acv                          157                       # DTB write access violations
-system.cpu.dtb.write_accesses                  291932                       # DTB write accesses
-system.cpu.dtb.data_hits                     15402326                       # DTB hits
-system.cpu.dtb.data_misses                      11497                       # DTB misses
+system.cpu.dtb.write_accesses                  291933                       # DTB write accesses
+system.cpu.dtb.data_hits                     15401831                       # DTB hits
+system.cpu.dtb.data_misses                      11500                       # DTB misses
 system.cpu.dtb.data_acv                           367                       # DTB access violations
-system.cpu.dtb.data_accesses                  1020843                       # DTB accesses
-system.cpu.itb.fetch_hits                     4974965                       # ITB hits
+system.cpu.dtb.data_accesses                  1020848                       # DTB accesses
+system.cpu.itb.fetch_hits                     4974960                       # ITB hits
 system.cpu.itb.fetch_misses                      5010                       # ITB misses
 system.cpu.itb.fetch_acv                          184                       # ITB acv
-system.cpu.itb.fetch_accesses                 4979975                       # ITB accesses
+system.cpu.itb.fetch_accesses                 4979970                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -466,34 +458,34 @@ system.cpu.itb.data_hits                            0                       # DT
 system.cpu.itb.data_misses                          0                       # DTB misses
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
-system.cpu.numCycles                       3838893116                       # number of cpu cycles simulated
+system.cpu.numCycles                       3838877544                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                    56104177                       # Number of instructions committed
-system.cpu.committedOps                      56104177                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses              51979169                       # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses                 324594                       # Number of float alu accesses
-system.cpu.num_func_calls                     1481286                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts      6461218                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                     51979169                       # number of integer instructions
-system.cpu.num_fp_insts                        324594                       # number of float instructions
-system.cpu.num_int_register_reads            71209746                       # number of times the integer registers were read
-system.cpu.num_int_register_writes           38460532                       # number of times the integer registers were written
-system.cpu.num_fp_register_reads               163708                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes              166588                       # number of times the floating registers were written
-system.cpu.num_mem_refs                      15454993                       # number of memory refs
-system.cpu.num_load_insts                     9089820                       # Number of load instructions
-system.cpu.num_store_insts                    6365173                       # Number of store instructions
-system.cpu.num_idle_cycles               3587243859.498131                       # Number of idle cycles
-system.cpu.num_busy_cycles               251649256.501869                       # Number of busy cycles
-system.cpu.not_idle_fraction                 0.065553                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                     0.934447                       # Percentage of idle cycles
-system.cpu.Branches                           8413035                       # Number of branches fetched
-system.cpu.op_class::No_OpClass               3197761      5.70%      5.70% # Class of executed instruction
-system.cpu.op_class::IntAlu                  36186344     64.48%     70.18% # Class of executed instruction
-system.cpu.op_class::IntMult                    61011      0.11%     70.29% # Class of executed instruction
-system.cpu.op_class::IntDiv                         0      0.00%     70.29% # Class of executed instruction
-system.cpu.op_class::FloatAdd                   25613      0.05%     70.34% # Class of executed instruction
+system.cpu.committedInsts                    56102112                       # Number of instructions committed
+system.cpu.committedOps                      56102112                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses              51977185                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses                 324460                       # Number of float alu accesses
+system.cpu.num_func_calls                     1481236                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts      6460933                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                     51977185                       # number of integer instructions
+system.cpu.num_fp_insts                        324460                       # number of float instructions
+system.cpu.num_int_register_reads            71206533                       # number of times the integer registers were read
+system.cpu.num_int_register_writes           38459103                       # number of times the integer registers were written
+system.cpu.num_fp_register_reads               163642                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes              166520                       # number of times the floating registers were written
+system.cpu.num_mem_refs                      15454487                       # number of memory refs
+system.cpu.num_load_insts                     9089505                       # Number of load instructions
+system.cpu.num_store_insts                    6364982                       # Number of store instructions
+system.cpu.num_idle_cycles               3587234430.998131                       # Number of idle cycles
+system.cpu.num_busy_cycles               251643113.001869                       # Number of busy cycles
+system.cpu.not_idle_fraction                 0.065551                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                     0.934449                       # Percentage of idle cycles
+system.cpu.Branches                           8412678                       # Number of branches fetched
+system.cpu.op_class::No_OpClass               3197715      5.70%      5.70% # Class of executed instruction
+system.cpu.op_class::IntAlu                  36172357     64.46%     70.16% # Class of executed instruction
+system.cpu.op_class::IntMult                    61004      0.11%     70.27% # Class of executed instruction
+system.cpu.op_class::IntDiv                         0      0.00%     70.27% # Class of executed instruction
+system.cpu.op_class::FloatAdd                   38087      0.07%     70.34% # Class of executed instruction
 system.cpu.op_class::FloatCmp                       0      0.00%     70.34% # Class of executed instruction
 system.cpu.op_class::FloatCvt                       0      0.00%     70.34% # Class of executed instruction
 system.cpu.op_class::FloatMult                      0      0.00%     70.34% # Class of executed instruction
@@ -519,34 +511,34 @@ system.cpu.op_class::SimdFloatMisc                  0      0.00%     70.34% # Cl
 system.cpu.op_class::SimdFloatMult                  0      0.00%     70.34% # Class of executed instruction
 system.cpu.op_class::SimdFloatMultAcc               0      0.00%     70.34% # Class of executed instruction
 system.cpu.op_class::SimdFloatSqrt                  0      0.00%     70.34% # Class of executed instruction
-system.cpu.op_class::MemRead                  9316905     16.60%     86.95% # Class of executed instruction
-system.cpu.op_class::MemWrite                 6371245     11.35%     98.30% # Class of executed instruction
-system.cpu.op_class::IprAccess                 953526      1.70%    100.00% # Class of executed instruction
+system.cpu.op_class::MemRead                  9316582     16.60%     86.95% # Class of executed instruction
+system.cpu.op_class::MemWrite                 6371054     11.35%     98.30% # Class of executed instruction
+system.cpu.op_class::IprAccess                 953544      1.70%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::total                   56116041                       # Class of executed instruction
+system.cpu.op_class::total                   56113979                       # Class of executed instruction
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
 system.cpu.kern.inst.quiesce                     6378                       # number of quiesce instructions executed
-system.cpu.kern.inst.hwrei                     212017                       # number of hwrei instructions executed
+system.cpu.kern.inst.hwrei                     212019                       # number of hwrei instructions executed
 system.cpu.kern.ipl_count::0                    74895     40.89%     40.89% # number of times we switched to this ipl
 system.cpu.kern.ipl_count::21                     131      0.07%     40.96% # number of times we switched to this ipl
 system.cpu.kern.ipl_count::22                    1931      1.05%     42.01% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::31                  106210     57.99%    100.00% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::total               183167                       # number of times we switched to this ipl
+system.cpu.kern.ipl_count::31                  106211     57.99%    100.00% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::total               183168                       # number of times we switched to this ipl
 system.cpu.kern.ipl_good::0                     73528     49.31%     49.31% # number of times we switched to this ipl from a different ipl
 system.cpu.kern.ipl_good::21                      131      0.09%     49.40% # number of times we switched to this ipl from a different ipl
 system.cpu.kern.ipl_good::22                     1931      1.29%     50.69% # number of times we switched to this ipl from a different ipl
 system.cpu.kern.ipl_good::31                    73528     49.31%    100.00% # number of times we switched to this ipl from a different ipl
 system.cpu.kern.ipl_good::total                149118                       # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_ticks::0             1857252195000     96.76%     96.76% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::21                91387500      0.00%     96.76% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::22               737178000      0.04%     96.80% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::31             61365063500      3.20%    100.00% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::total         1919445824000                       # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::0             1857248521000     96.76%     96.76% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::21                91287500      0.00%     96.76% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::22               737179000      0.04%     96.80% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::31             61361050500      3.20%    100.00% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::total         1919438038000                       # number of cycles we spent at this ipl
 system.cpu.kern.ipl_used::0                  0.981748                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.ipl_used::21                        1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.ipl_used::22                        1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::31                 0.692289                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::total              0.814110                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used::31                 0.692282                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used::total              0.814105                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.syscall::2                          8      2.45%      2.45% # number of syscalls executed
 system.cpu.kern.syscall::3                         30      9.20%     11.66% # number of syscalls executed
 system.cpu.kern.syscall::4                          4      1.23%     12.88% # number of syscalls executed
@@ -582,10 +574,10 @@ system.cpu.kern.callpal::cserve                     1      0.00%      0.00% # nu
 system.cpu.kern.callpal::wrmces                     1      0.00%      0.00% # number of callpals executed
 system.cpu.kern.callpal::wrfen                      1      0.00%      0.00% # number of callpals executed
 system.cpu.kern.callpal::wrvptptr                   1      0.00%      0.00% # number of callpals executed
-system.cpu.kern.callpal::swpctx                  4179      2.17%      2.17% # number of callpals executed
+system.cpu.kern.callpal::swpctx                  4177      2.17%      2.17% # number of callpals executed
 system.cpu.kern.callpal::tbi                       54      0.03%      2.20% # number of callpals executed
 system.cpu.kern.callpal::wrent                      7      0.00%      2.20% # number of callpals executed
-system.cpu.kern.callpal::swpipl                175948     91.21%     93.41% # number of callpals executed
+system.cpu.kern.callpal::swpipl                175949     91.22%     93.41% # number of callpals executed
 system.cpu.kern.callpal::rdps                    6832      3.54%     96.96% # number of callpals executed
 system.cpu.kern.callpal::wrkgp                      1      0.00%     96.96% # number of callpals executed
 system.cpu.kern.callpal::wrusp                      7      0.00%     96.96% # number of callpals executed
@@ -594,21 +586,21 @@ system.cpu.kern.callpal::whami                      2      0.00%     96.97% # nu
 system.cpu.kern.callpal::rti                     5156      2.67%     99.64% # number of callpals executed
 system.cpu.kern.callpal::callsys                  515      0.27%     99.91% # number of callpals executed
 system.cpu.kern.callpal::imb                      181      0.09%    100.00% # number of callpals executed
-system.cpu.kern.callpal::total                 192895                       # number of callpals executed
-system.cpu.kern.mode_switch::kernel              5904                       # number of protection mode switches
-system.cpu.kern.mode_switch::user                1741                       # number of protection mode switches
+system.cpu.kern.callpal::total                 192894                       # number of callpals executed
+system.cpu.kern.mode_switch::kernel              5902                       # number of protection mode switches
+system.cpu.kern.mode_switch::user                1742                       # number of protection mode switches
 system.cpu.kern.mode_switch::idle                2097                       # number of protection mode switches
 system.cpu.kern.mode_good::kernel                1912                      
-system.cpu.kern.mode_good::user                  1741                      
-system.cpu.kern.mode_good::idle                   171                      
-system.cpu.kern.mode_switch_good::kernel     0.323848                       # fraction of useful protection mode switches
+system.cpu.kern.mode_good::user                  1742                      
+system.cpu.kern.mode_good::idle                   170                      
+system.cpu.kern.mode_switch_good::kernel     0.323958                       # fraction of useful protection mode switches
 system.cpu.kern.mode_switch_good::user              1                       # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::idle       0.081545                       # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::total      0.392527                       # fraction of useful protection mode switches
-system.cpu.kern.mode_ticks::kernel        46108525500      2.40%      2.40% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::user           5189217000      0.27%      2.67% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::idle         1868148079500     97.33%    100.00% # number of ticks spent at the given mode
-system.cpu.kern.swap_context                     4180                       # number of times the context was actually changed
+system.cpu.kern.mode_switch_good::idle       0.081068                       # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good::total      0.392567                       # fraction of useful protection mode switches
+system.cpu.kern.mode_ticks::kernel        46116573000      2.40%      2.40% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::user           5192895500      0.27%      2.67% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::idle         1868128567500     97.33%    100.00% # number of ticks spent at the given mode
+system.cpu.kern.swap_context                     4178                       # number of times the context was actually changed
 system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
 system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
 system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
@@ -640,7 +632,7 @@ system.tsunami.ethernet.totalRxOrn                  0                       # to
 system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
 system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
 system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
-system.iobus.throughput                       1409867                       # Throughput (bytes/s)
+system.iobus.throughput                       1409873                       # Throughput (bytes/s)
 system.iobus.trans_dist::ReadReq                 7103                       # Transaction distribution
 system.iobus.trans_dist::ReadResp                7103                       # Transaction distribution
 system.iobus.trans_dist::WriteReq               51201                       # Transaction distribution
@@ -700,21 +692,21 @@ system.iobus.reqLayer27.occupancy               76000                       # La
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer28.occupancy              110000                       # Layer occupancy (ticks)
 system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer29.occupancy           380199064                       # Layer occupancy (ticks)
+system.iobus.reqLayer29.occupancy           374407689                       # Layer occupancy (ticks)
 system.iobus.reqLayer29.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer30.occupancy               30000                       # Layer occupancy (ticks)
 system.iobus.reqLayer30.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy            23509000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer1.occupancy            43233500                       # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy            42014000                       # Layer occupancy (ticks)
 system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
-system.cpu.icache.tags.replacements            927875                       # number of replacements
-system.cpu.icache.tags.tagsinuse           508.303976                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            55187496                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs            928386                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             59.444559                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements            927724                       # number of replacements
+system.cpu.icache.tags.tagsinuse           508.304001                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            55185585                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs            928235                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             59.452170                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle       39855277250                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   508.303976                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_blocks::cpu.inst   508.304001                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.992781                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.992781                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
@@ -723,44 +715,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1            1
 system.cpu.icache.tags.age_task_id_blocks_1024::2          438                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::3            9                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          57044588                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         57044588                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     55187496                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        55187496                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      55187496                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         55187496                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     55187496                       # number of overall hits
-system.cpu.icache.overall_hits::total        55187496                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst       928546                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total        928546                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst       928546                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total         928546                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst       928546                       # number of overall misses
-system.cpu.icache.overall_misses::total        928546                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  12910342260                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  12910342260                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  12910342260                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  12910342260                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  12910342260                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  12910342260                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     56116042                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     56116042                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     56116042                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     56116042                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     56116042                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     56116042                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.016547                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.016547                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.016547                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.016547                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.016547                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.016547                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13903.826262                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13903.826262                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13903.826262                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13903.826262                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13903.826262                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13903.826262                       # average overall miss latency
+system.cpu.icache.tags.tag_accesses          57042375                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         57042375                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     55185585                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        55185585                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      55185585                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         55185585                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     55185585                       # number of overall hits
+system.cpu.icache.overall_hits::total        55185585                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst       928395                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total        928395                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst       928395                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total         928395                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst       928395                       # number of overall misses
+system.cpu.icache.overall_misses::total        928395                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  12914246500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  12914246500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  12914246500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  12914246500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  12914246500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  12914246500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     56113980                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     56113980                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     56113980                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     56113980                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     56113980                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     56113980                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.016545                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.016545                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.016545                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.016545                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.016545                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.016545                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13910.293033                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13910.293033                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13910.293033                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13910.293033                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13910.293033                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13910.293033                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -769,135 +761,135 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
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-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11898.265396                       # average overall mshr miss latency
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+system.cpu.icache.overall_avg_mshr_miss_latency::total 11904.719974                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements           336232                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        65296.289611                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            2446119                       # Total number of references to valid blocks.
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-system.cpu.l2cache.tags.occ_blocks::writebacks 55555.447127                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  4766.385283                       # Average occupied blocks per requestor
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+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.014320                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.279596                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.173396                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73195.238453                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 65072.018863                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 65450.594032                       # average ReadReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data         7192                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total         7192                       # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69040.824085                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69040.824085                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73195.238453                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 66264.744837                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 66493.876849                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73195.238453                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 66264.744837                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 66493.876849                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -906,66 +898,66 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        74176                       # number of writebacks
-system.cpu.l2cache.writebacks::total            74176                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        13293                       # number of ReadReq MSHR misses
+system.cpu.l2cache.writebacks::writebacks        74183                       # number of writebacks
+system.cpu.l2cache.writebacks::total            74183                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        13294                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadReq_mshr_misses::cpu.data       271960                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total       285253                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total       285254                       # number of ReadReq MSHR misses
 system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data           13                       # number of UpgradeReq MSHR misses
 system.cpu.l2cache.UpgradeReq_mshr_misses::total           13                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       116840                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       116840                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst        13293                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       388800                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       402093                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst        13293                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       388800                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       402093                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    800656260                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  14299493254                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total  15100149514                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       230011                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       230011                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   6607242375                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   6607242375                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    800656260                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  20906735629                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  21707391889                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    800656260                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  20906735629                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  21707391889                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   1334145500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   1334145500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   1895432500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   1895432500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   3229578000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total   3229578000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.014316                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.250313                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.141564                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       116846                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       116846                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst        13294                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       388806                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       402100                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst        13294                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       388806                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       402100                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    806506000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  14297020250                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total  15103526250                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       130013                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       130013                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   6606288869                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   6606288869                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    806506000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  20903309119                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  21709815119                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    806506000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  20903309119                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  21709815119                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   1334146000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   1334146000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   1895431500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   1895431500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   3229577500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total   3229577500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.014320                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.250330                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.141581                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.764706                       # mshr miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.764706                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.384060                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.384060                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.014316                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.279571                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.173374                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.014316                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.279571                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.173374                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60231.419544                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52579.398640                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 52935.988452                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17693.153846                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17693.153846                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56549.489687                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56549.489687                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60231.419544                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53772.468182                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53985.997988                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60231.419544                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53772.468182                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53985.997988                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.384122                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.384122                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.014320                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.279596                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.173396                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.014320                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.279596                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.173396                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60666.917406                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52570.305376                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 52947.640524                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        10001                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        10001                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56538.425526                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56538.425526                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60666.917406                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53762.825468                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53991.084603                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60666.917406                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53762.825468                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53991.084603                       # average overall mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
@@ -973,13 +965,13 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements           1390190                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.978877                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            14030691                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           1390702                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             10.088927                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.replacements           1390084                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.978881                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            14030288                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           1390596                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             10.089406                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle         107775250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.978877                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.978881                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.999959                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.999959                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
@@ -987,72 +979,72 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0          187
 system.cpu.dcache.tags.age_task_id_blocks_1024::1          257                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::2           68                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          63076279                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         63076279                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data      7802806                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total         7802806                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      5845593                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        5845593                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data       183040                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       183040                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data       199235                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total       199235                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      13648399                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         13648399                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     13648399                       # number of overall hits
-system.cpu.dcache.overall_hits::total        13648399                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      1069264                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       1069264                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       304240                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       304240                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data        17216                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total        17216                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data      1373504                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        1373504                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      1373504                       # number of overall misses
-system.cpu.dcache.overall_misses::total       1373504                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  29001409504                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  29001409504                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  10907701386                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  10907701386                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    228213250                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total    228213250                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  39909110890                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  39909110890                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  39909110890                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  39909110890                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data      8872070                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total      8872070                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data      6149833                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total      6149833                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data       200256                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total       200256                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data       199235                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total       199235                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     15021903                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     15021903                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     15021903                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     15021903                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.120520                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.120520                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.049471                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.049471                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.085970                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.085970                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.091433                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.091433                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.091433                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.091433                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27122.777447                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 27122.777447                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35852.292223                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 35852.292223                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13255.881157                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13255.881157                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 29056.421306                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 29056.421306                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 29056.421306                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 29056.421306                       # average overall miss latency
+system.cpu.dcache.tags.tag_accesses          63074137                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         63074137                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data      7802568                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total         7802568                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      5845442                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        5845442                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data       183034                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total       183034                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data       199227                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total       199227                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data      13648010                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         13648010                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     13648010                       # number of overall hits
+system.cpu.dcache.overall_hits::total        13648010                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      1069193                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       1069193                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       304207                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       304207                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data        17214                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total        17214                       # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data      1373400                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        1373400                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      1373400                       # number of overall misses
+system.cpu.dcache.overall_misses::total       1373400                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  28998201750                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  28998201750                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  10906246382                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  10906246382                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    228174000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total    228174000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  39904448132                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  39904448132                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  39904448132                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  39904448132                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data      8871761                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total      8871761                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data      6149649                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total      6149649                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data       200248                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total       200248                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data       199227                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total       199227                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     15021410                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     15021410                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     15021410                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     15021410                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.120516                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.120516                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.049467                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.049467                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.085963                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.085963                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.091429                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.091429                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.091429                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.091429                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27121.578377                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 27121.578377                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35851.398495                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 35851.398495                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13255.141164                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13255.141164                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 29055.226541                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 29055.226541                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 29055.226541                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 29055.226541                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -1061,54 +1053,54 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       834591                       # number of writebacks
-system.cpu.dcache.writebacks::total            834591                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1069264                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      1069264                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       304240                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       304240                       # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        17216                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total        17216                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      1373504                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      1373504                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      1373504                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      1373504                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  26737269496                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  26737269496                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  10246531614                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  10246531614                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    193767750                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    193767750                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  36983801110                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  36983801110                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  36983801110                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  36983801110                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   1424235500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   1424235500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2011220500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2011220500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   3435456000                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total   3435456000                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.120520                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.120520                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.049471                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.049471                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.085970                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.085970                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.091433                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.091433                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.091433                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.091433                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25005.302242                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25005.302242                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33679.107330                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33679.107330                       # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11255.097003                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11255.097003                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26926.606046                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 26926.606046                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26926.606046                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 26926.606046                       # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks       834526                       # number of writebacks
+system.cpu.dcache.writebacks::total            834526                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1069193                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      1069193                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       304207                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       304207                       # number of WriteReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        17214                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total        17214                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      1373400                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      1373400                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      1373400                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      1373400                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  26734131250                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  26734131250                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  10245126618                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  10245126618                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    193732000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    193732000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  36979257868                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  36979257868                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  36979257868                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  36979257868                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   1424236000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   1424236000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2011219500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2011219500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   3435455500                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total   3435455500                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.120516                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.120516                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.049467                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.049467                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.085963                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.085963                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.091429                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.091429                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.091429                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.091429                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25004.027570                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25004.027570                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33678.142245                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33678.142245                       # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11254.327873                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11254.327873                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26925.337023                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 26925.337023                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26925.337023                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 26925.337023                       # average overall mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
@@ -1116,31 +1108,32 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.throughput               105186760                       # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq        2022129                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       2022112                       # Transaction distribution
+system.cpu.toL2Bus.throughput               106562255                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq        2021905                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       2021888                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteReq          9649                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteResp         9649                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback       834591                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback       834526                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteInvalidateReq        41563                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::UpgradeReq           17                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::UpgradeResp           17                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       345775                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       304224                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1857072                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      3649346                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           5506418                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     59425664                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    142473420                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total      201899084                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus         201889036                       # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus        11328                       # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy     2424633500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.trans_dist::ReadExReq       304190                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       304190                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1856770                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      3649068                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           5505838                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     59416000                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    142462412                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total      201878412                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus         201868428                       # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus      2671296                       # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy     2424407500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy       235500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.occupancy       234000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy    1395400760                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy    1395179500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    2186975140                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    2186860632                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt
index 547f88656..df149be6e 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt
@@ -1,73 +1,69 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.912098                       # Number of seconds simulated
-sim_ticks                                912098398000                       # Number of ticks simulated
-final_tick                               912098398000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.900855                       # Number of seconds simulated
+sim_ticks                                900854787500                       # Number of ticks simulated
+final_tick                               900854787500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1024713                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1319299                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            15163617701                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 465872                       # Number of bytes of host memory used
-host_seconds                                    60.15                       # Real time elapsed on the host
-sim_insts                                    61636937                       # Number of instructions simulated
-sim_ops                                      79356422                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 875862                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1055198                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            12821864647                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 433912                       # Number of bytes of host memory used
+host_seconds                                    70.26                       # Real time elapsed on the host
+sim_insts                                    61537412                       # Number of instructions simulated
+sim_ops                                      74137396                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::realview.clcd     39321600                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.dtb.walker           64                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.dtb.walker          256                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.itb.walker          192                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst           502220                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data          6235260                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker          192                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           214596                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data          3364600                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             49638724                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       502220                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       214596                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          716816                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      4195904                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0.data         17000                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1.data       3010088                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7222992                       # Number of bytes written to this memory
+system.physmem.bytes_read::cpu0.inst           460108                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data          6580092                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           258564                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data          2992120                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             49612932                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       460108                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       258564                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          718672                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      4174784                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0.data       3027048                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1.data            40                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7201872                       # Number of bytes written to this memory
 system.physmem.num_reads::realview.clcd       4915200                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.dtb.walker            1                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.dtb.walker            4                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu0.itb.walker            3                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             14075                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data             97500                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker            3                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              3444                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data             52600                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               5082826                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           65561                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0.data             4250                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1.data           752522                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               822333                       # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd        43111138                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.dtb.walker            70                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker           211                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst              550620                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data             6836170                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker           211                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst              235277                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data             3688856                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                54422554                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         550620                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst         235277                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             785898                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           4600276                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data              18638                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data            3300179                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                7919093                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           4600276                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd       43111138                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker           70                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker          211                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             550620                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data            6854809                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker          211                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst             235277                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data            6989035                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               62341647                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.num_reads::cpu0.inst             13417                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data            102873                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst              4131                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data             46770                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               5082398                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           65231                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0.data           756762                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu1.data               10                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               822003                       # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd        43649210                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.dtb.walker           284                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker           213                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst              510746                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data             7304276                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst              287021                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data             3321423                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                55073173                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         510746                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst         287021                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             797767                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           4634247                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data            3360195                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1.data                 44                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                7994487                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           4634247                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd       43649210                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker          284                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker          213                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             510746                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data           10664471                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst             287021                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data            3321468                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               63067661                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bytes_read::cpu0.inst           20                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu1.inst           48                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total            68                       # Number of bytes read from this memory
@@ -86,188 +82,180 @@ system.realview.nvmem.bw_inst_read::total           75                       # I
 system.realview.nvmem.bw_total::cpu0.inst           22                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::cpu1.inst           53                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::total              75                       # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput                     64987015                       # Throughput (bytes/s)
-system.membus.data_through_bus               59274552                       # Total data (bytes)
+system.membus.throughput                     65740815                       # Throughput (bytes/s)
+system.membus.data_through_bus               59222928                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.l2c.tags.replacements                    70660                       # number of replacements
-system.l2c.tags.tagsinuse                51560.418077                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    1623334                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                   135812                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                    11.952802                       # Average number of references to valid blocks.
+system.l2c.tags.replacements                    70256                       # number of replacements
+system.l2c.tags.tagsinuse                51491.506872                       # Cycle average of tags in use
+system.l2c.tags.total_refs                    1633923                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                   135467                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                    12.061410                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   39278.982234                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker     0.000049                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker     0.001109                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     4358.948754                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     2482.442784                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker     2.678936                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst     2126.447479                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data     3310.916734                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.599350                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000000                       # Average percentage of cache occupancy
+system.l2c.tags.occ_blocks::writebacks   39155.338647                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.dtb.walker     2.673377                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker     0.001056                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     4830.605577                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     5154.208952                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst     1696.649192                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data      652.030072                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.597463                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000041                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu0.itb.walker     0.000000                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.066512                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.037879                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000041                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.032447                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.050521                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.786750                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst       0.073709                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data       0.078647                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.025889                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data       0.009949                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.785698                       # Average percentage of cache occupancy
 system.l2c.tags.occ_task_id_blocks::1023            4                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024        65148                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1024        65207                       # Occupied blocks per task id
 system.l2c.tags.age_task_id_blocks_1023::2            1                       # Occupied blocks per task id
 system.l2c.tags.age_task_id_blocks_1023::4            3                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0           50                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1          203                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         3771                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3        12549                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        48575                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0           24                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1          259                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2         3953                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3        12685                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        48286                       # Occupied blocks per task id
 system.l2c.tags.occ_task_id_percent::1023     0.000061                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024     0.994080                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                 16908072                       # Number of tag accesses
-system.l2c.tags.data_accesses                16908072                       # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.dtb.walker         3874                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker         1919                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.inst             421038                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data             175187                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker         5331                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker         1734                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst             430511                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data             169510                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                1209104                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks          567806                       # number of Writeback hits
-system.l2c.Writeback_hits::total               567806                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data             611                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data             663                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                1274                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data           137                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data            31                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total               168                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data            58145                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data            50213                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               108358                       # number of ReadExReq hits
-system.l2c.demand_hits::cpu0.dtb.walker          3874                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker          1919                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst              421038                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data              233332                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker          5331                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker          1734                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst              430511                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data              219723                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 1317462                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker         3874                       # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker         1919                       # number of overall hits
-system.l2c.overall_hits::cpu0.inst             421038                       # number of overall hits
-system.l2c.overall_hits::cpu0.data             233332                       # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker         5331                       # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker         1734                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst             430511                       # number of overall hits
-system.l2c.overall_hits::cpu1.data             219723                       # number of overall hits
-system.l2c.overall_hits::total                1317462                       # number of overall hits
-system.l2c.ReadReq_misses::cpu0.dtb.walker            1                       # number of ReadReq misses
+system.l2c.tags.occ_task_id_percent::1024     0.994980                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                 16963603                       # Number of tag accesses
+system.l2c.tags.data_accesses                16963603                       # Number of data accesses
+system.l2c.ReadReq_hits::cpu0.dtb.walker         4298                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.itb.walker         1596                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.inst             413244                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.data             202837                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.dtb.walker         4578                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.itb.walker         1943                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.inst             438543                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.data             146503                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                1213542                       # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks          571726                       # number of Writeback hits
+system.l2c.Writeback_hits::total               571726                       # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu0.data            1266                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data             397                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                1663                       # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu0.data           238                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu1.data            38                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total               276                       # number of SCUpgradeReq hits
+system.l2c.ReadExReq_hits::cpu0.data            51499                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data            57148                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               108647                       # number of ReadExReq hits
+system.l2c.demand_hits::cpu0.dtb.walker          4298                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.itb.walker          1596                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.inst              413244                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data              254336                       # number of demand (read+write) hits
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+system.l2c.demand_hits::total                 1322189                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.dtb.walker         4298                       # number of overall hits
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+system.l2c.overall_hits::total                1322189                       # number of overall hits
+system.l2c.ReadReq_misses::cpu0.dtb.walker            4                       # number of ReadReq misses
 system.l2c.ReadReq_misses::cpu0.itb.walker            3                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.inst             7432                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.data             6392                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.dtb.walker            3                       # number of ReadReq misses
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-system.l2c.ReadReq_misses::cpu1.data             5276                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total                22454                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0.data          4941                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data          4450                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total              9391                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.data          741                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu1.data          490                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total            1231                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data          92465                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data          48373                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             140838                       # number of ReadExReq misses
-system.l2c.demand_misses::cpu0.dtb.walker            1                       # number of demand (read+write) misses
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+system.l2c.ReadReq_misses::total                22342                       # number of ReadReq misses
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+system.l2c.UpgradeReq_misses::cpu1.data          5033                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total              7939                       # number of UpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu0.data          414                       # number of SCUpgradeReq misses
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+system.l2c.ReadExReq_misses::total             140545                       # number of ReadExReq misses
+system.l2c.demand_misses::cpu0.dtb.walker            4                       # number of demand (read+write) misses
 system.l2c.demand_misses::cpu0.itb.walker            3                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst              7432                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data             98857                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.dtb.walker            3                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst              3347                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data             53649                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                163292                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.dtb.walker            1                       # number of overall misses
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+system.l2c.demand_misses::cpu0.data            103726                       # number of demand (read+write) misses
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+system.l2c.demand_misses::total                162887                       # number of demand (read+write) misses
+system.l2c.overall_misses::cpu0.dtb.walker            4                       # number of overall misses
 system.l2c.overall_misses::cpu0.itb.walker            3                       # number of overall misses
-system.l2c.overall_misses::cpu0.inst             7432                       # number of overall misses
-system.l2c.overall_misses::cpu0.data            98857                       # number of overall misses
-system.l2c.overall_misses::cpu1.dtb.walker            3                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst             3347                       # number of overall misses
-system.l2c.overall_misses::cpu1.data            53649                       # number of overall misses
-system.l2c.overall_misses::total               163292                       # number of overall misses
-system.l2c.ReadReq_accesses::cpu0.dtb.walker         3875                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.itb.walker         1922                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.inst         428470                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.data         181579                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.dtb.walker         5334                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.itb.walker         1734                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.inst         433858                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.data         174786                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total            1231558                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks       567806                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total           567806                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data         5552                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data         5113                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total           10665                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu0.data          878                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu1.data          521                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total          1399                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data       150610                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data        98586                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           249196                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.dtb.walker         3875                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.itb.walker         1922                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst          428470                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data          332189                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.dtb.walker         5334                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.itb.walker         1734                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst          433858                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data          273372                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             1480754                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker         3875                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker         1922                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst         428470                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data         332189                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker         5334                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker         1734                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst         433858                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data         273372                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            1480754                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.000258                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.001561                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst      0.017345                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data      0.035202                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.000562                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst      0.007715                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data      0.030185                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.018232                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.889950                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.870331                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.880544                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.843964                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.940499                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.879914                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.613937                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.490668                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.565170                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker     0.000258                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker     0.001561                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.017345                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.297593                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.dtb.walker     0.000562                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.007715                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.196249                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.110276                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker     0.000258                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker     0.001561                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.017345                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.297593                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker     0.000562                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.007715                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.196249                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.110276                       # miss rate for overall accesses
+system.l2c.overall_misses::cpu0.inst             6774                       # number of overall misses
+system.l2c.overall_misses::cpu0.data           103726                       # number of overall misses
+system.l2c.overall_misses::cpu1.inst             4034                       # number of overall misses
+system.l2c.overall_misses::cpu1.data            48346                       # number of overall misses
+system.l2c.overall_misses::total               162887                       # number of overall misses
+system.l2c.ReadReq_accesses::cpu0.dtb.walker         4302                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.itb.walker         1599                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.inst         420018                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.data         212536                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.dtb.walker         4578                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.itb.walker         1943                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.inst         442577                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.data         148331                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total            1235884                       # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks       571726                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total           571726                       # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data         4172                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data         5430                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total            9602                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu0.data          652                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu1.data          700                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total          1352                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data       145526                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data       103666                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           249192                       # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.dtb.walker         4302                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.itb.walker         1599                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst          420018                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data          358062                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.dtb.walker         4578                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.itb.walker         1943                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst          442577                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data          251997                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total             1485076                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker         4302                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.itb.walker         1599                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst         420018                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data         358062                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.dtb.walker         4578                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.itb.walker         1943                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst         442577                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data         251997                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            1485076                       # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.000930                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.001876                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.inst      0.016128                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.data      0.045635                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.inst      0.009115                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.data      0.012324                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.018078                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.696548                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.926888                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.826807                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.634969                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.945714                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.795858                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.646118                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.448730                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.564003                       # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker     0.000930                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker     0.001876                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.016128                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.289687                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.009115                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.191851                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.109683                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker     0.000930                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker     0.001876                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.016128                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.289687                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.009115                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.191851                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.109683                       # miss rate for overall accesses
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -276,8 +264,8 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks               65561                       # number of writebacks
-system.l2c.writebacks::total                    65561                       # number of writebacks
+system.l2c.writebacks::writebacks               65231                       # number of writebacks
+system.l2c.writebacks::total                    65231                       # number of writebacks
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
 system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
 system.cf0.dma_read_bytes                           0                       # Number of bytes transfered via DMA reads (not PRD).
@@ -285,11 +273,11 @@ system.cf0.dma_read_txs                             0                       # Nu
 system.cf0.dma_write_full_pages                     0                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                          0                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
-system.toL2Bus.throughput                   154019817                       # Throughput (bytes/s)
-system.toL2Bus.data_through_bus             140481228                       # Total data (bytes)
+system.toL2Bus.throughput                   156214740                       # Throughput (bytes/s)
+system.toL2Bus.data_through_bus             140726796                       # Total data (bytes)
 system.toL2Bus.snoop_data_through_bus               0                       # Total snoop data (bytes)
-system.iobus.throughput                      45731035                       # Throughput (bytes/s)
-system.iobus.data_through_bus                41711204                       # Total data (bytes)
+system.iobus.throughput                      46301771                       # Throughput (bytes/s)
+system.iobus.data_through_bus                41711172                       # Total data (bytes)
 system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -313,25 +301,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # D
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                     7977762                       # DTB read hits
-system.cpu0.dtb.read_misses                      3611                       # DTB read misses
-system.cpu0.dtb.write_hits                    5967140                       # DTB write hits
-system.cpu0.dtb.write_misses                      672                       # DTB write misses
+system.cpu0.dtb.read_hits                     7391669                       # DTB read hits
+system.cpu0.dtb.read_misses                      1915                       # DTB read misses
+system.cpu0.dtb.write_hits                    6659638                       # DTB write hits
+system.cpu0.dtb.write_misses                     1130                       # DTB write misses
 system.cpu0.dtb.flush_tlb                           4                       # Number of times complete TLB was flushed
 system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
 system.cpu0.dtb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.dtb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                    1905                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.flush_entries                    1223                       # Number of entries that have been flushed from TLB
 system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                   135                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.prefetch_faults                    84                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                      248                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                 7981373                       # DTB read accesses
-system.cpu0.dtb.write_accesses                5967812                       # DTB write accesses
+system.cpu0.dtb.perms_faults                      185                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses                 7393584                       # DTB read accesses
+system.cpu0.dtb.write_accesses                6660768                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                         13944902                       # DTB hits
-system.cpu0.dtb.misses                           4283                       # DTB misses
-system.cpu0.dtb.accesses                     13949185                       # DTB accesses
+system.cpu0.dtb.hits                         14051307                       # DTB hits
+system.cpu0.dtb.misses                           3045                       # DTB misses
+system.cpu0.dtb.accesses                     14054352                       # DTB accesses
 system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -353,8 +341,8 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.inst_hits                    30248608                       # ITB inst hits
-system.cpu0.itb.inst_misses                      2175                       # ITB inst misses
+system.cpu0.itb.inst_hits                    37936012                       # ITB inst hits
+system.cpu0.itb.inst_misses                      1207                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
@@ -363,116 +351,118 @@ system.cpu0.itb.flush_tlb                           4                       # Nu
 system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
 system.cpu0.itb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.itb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                    1280                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_entries                     848                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses                30250783                       # ITB inst accesses
-system.cpu0.itb.hits                         30248608                       # DTB hits
-system.cpu0.itb.misses                           2175                       # DTB misses
-system.cpu0.itb.accesses                     30250783                       # DTB accesses
-system.cpu0.numCycles                      1823674676                       # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses                37937219                       # ITB inst accesses
+system.cpu0.itb.hits                         37936012                       # DTB hits
+system.cpu0.itb.misses                           1207                       # DTB misses
+system.cpu0.itb.accesses                     37937219                       # DTB accesses
+system.cpu0.numCycles                      1801227301                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                   29759626                       # Number of instructions committed
-system.cpu0.committedOps                     39141026                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses             34755088                       # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses                  5449                       # Number of float alu accesses
-system.cpu0.num_func_calls                    1242746                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts      4045769                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                    34755088                       # number of integer instructions
-system.cpu0.num_fp_insts                         5449                       # number of float instructions
-system.cpu0.num_int_register_reads          179913159                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes          36837171                       # number of times the integer registers were written
-system.cpu0.num_fp_register_reads                4535                       # number of times the floating registers were read
-system.cpu0.num_fp_register_writes                916                       # number of times the floating registers were written
-system.cpu0.num_mem_refs                     14629859                       # number of memory refs
-system.cpu0.num_load_insts                    8359235                       # Number of load instructions
-system.cpu0.num_store_insts                   6270624                       # Number of store instructions
-system.cpu0.num_idle_cycles              1783997876.499954                       # Number of idle cycles
-system.cpu0.num_busy_cycles              39676799.500046                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.021757                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.978243                       # Percentage of idle cycles
-system.cpu0.Branches                          5492144                       # Number of branches fetched
-system.cpu0.op_class::No_OpClass                16326      0.04%      0.04% # Class of executed instruction
-system.cpu0.op_class::IntAlu                 24520115     62.53%     62.57% # Class of executed instruction
-system.cpu0.op_class::IntMult                   45259      0.12%     62.69% # Class of executed instruction
-system.cpu0.op_class::IntDiv                        0      0.00%     62.69% # Class of executed instruction
-system.cpu0.op_class::FloatAdd                      0      0.00%     62.69% # Class of executed instruction
-system.cpu0.op_class::FloatCmp                      0      0.00%     62.69% # Class of executed instruction
-system.cpu0.op_class::FloatCvt                      0      0.00%     62.69% # Class of executed instruction
-system.cpu0.op_class::FloatMult                     0      0.00%     62.69% # Class of executed instruction
-system.cpu0.op_class::FloatDiv                      0      0.00%     62.69% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt                     0      0.00%     62.69% # Class of executed instruction
-system.cpu0.op_class::SimdAdd                       0      0.00%     62.69% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc                    0      0.00%     62.69% # Class of executed instruction
-system.cpu0.op_class::SimdAlu                       0      0.00%     62.69% # Class of executed instruction
-system.cpu0.op_class::SimdCmp                       0      0.00%     62.69% # Class of executed instruction
-system.cpu0.op_class::SimdCvt                       0      0.00%     62.69% # Class of executed instruction
-system.cpu0.op_class::SimdMisc                      0      0.00%     62.69% # Class of executed instruction
-system.cpu0.op_class::SimdMult                      0      0.00%     62.69% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc                   0      0.00%     62.69% # Class of executed instruction
-system.cpu0.op_class::SimdShift                     0      0.00%     62.69% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc                  0      0.00%     62.69% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt                      0      0.00%     62.69% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd                  0      0.00%     62.69% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu                  0      0.00%     62.69% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp                  0      0.00%     62.69% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt                  0      0.00%     62.69% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv                  0      0.00%     62.69% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc              1421      0.00%     62.69% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult                 0      0.00%     62.69% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     62.69% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     62.69% # Class of executed instruction
-system.cpu0.op_class::MemRead                 8359235     21.32%     84.01% # Class of executed instruction
-system.cpu0.op_class::MemWrite                6270624     15.99%    100.00% # Class of executed instruction
+system.cpu0.committedInsts                   37698803                       # Number of instructions committed
+system.cpu0.committedOps                     44946380                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses             39863943                       # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses                  4171                       # Number of float alu accesses
+system.cpu0.num_func_calls                    1205467                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts      4697957                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                    39863943                       # number of integer instructions
+system.cpu0.num_fp_insts                         4171                       # number of float instructions
+system.cpu0.num_int_register_reads           70363299                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes          26108579                       # number of times the integer registers were written
+system.cpu0.num_fp_register_reads                3915                       # number of times the floating registers were read
+system.cpu0.num_fp_register_writes                256                       # number of times the floating registers were written
+system.cpu0.num_cc_register_reads           134797325                       # number of times the CC registers were read
+system.cpu0.num_cc_register_writes           18388517                       # number of times the CC registers were written
+system.cpu0.num_mem_refs                     14597479                       # number of memory refs
+system.cpu0.num_load_insts                    7571296                       # Number of load instructions
+system.cpu0.num_store_insts                   7026183                       # Number of store instructions
+system.cpu0.num_idle_cycles              1756006001.161348                       # Number of idle cycles
+system.cpu0.num_busy_cycles              45221299.838652                       # Number of busy cycles
+system.cpu0.not_idle_fraction                0.025106                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                    0.974894                       # Percentage of idle cycles
+system.cpu0.Branches                          6054325                       # Number of branches fetched
+system.cpu0.op_class::No_OpClass                13280      0.03%      0.03% # Class of executed instruction
+system.cpu0.op_class::IntAlu                 30338974     67.42%     67.45% # Class of executed instruction
+system.cpu0.op_class::IntMult                   51765      0.12%     67.56% # Class of executed instruction
+system.cpu0.op_class::IntDiv                        0      0.00%     67.56% # Class of executed instruction
+system.cpu0.op_class::FloatAdd                      0      0.00%     67.56% # Class of executed instruction
+system.cpu0.op_class::FloatCmp                      0      0.00%     67.56% # Class of executed instruction
+system.cpu0.op_class::FloatCvt                      0      0.00%     67.56% # Class of executed instruction
+system.cpu0.op_class::FloatMult                     0      0.00%     67.56% # Class of executed instruction
+system.cpu0.op_class::FloatDiv                      0      0.00%     67.56% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt                     0      0.00%     67.56% # Class of executed instruction
+system.cpu0.op_class::SimdAdd                       0      0.00%     67.56% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc                    0      0.00%     67.56% # Class of executed instruction
+system.cpu0.op_class::SimdAlu                       0      0.00%     67.56% # Class of executed instruction
+system.cpu0.op_class::SimdCmp                       0      0.00%     67.56% # Class of executed instruction
+system.cpu0.op_class::SimdCvt                       0      0.00%     67.56% # Class of executed instruction
+system.cpu0.op_class::SimdMisc                      0      0.00%     67.56% # Class of executed instruction
+system.cpu0.op_class::SimdMult                      0      0.00%     67.56% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc                   0      0.00%     67.56% # Class of executed instruction
+system.cpu0.op_class::SimdShift                     0      0.00%     67.56% # Class of executed instruction
+system.cpu0.op_class::SimdShiftAcc                  0      0.00%     67.56% # Class of executed instruction
+system.cpu0.op_class::SimdSqrt                      0      0.00%     67.56% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAdd                  0      0.00%     67.56% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAlu                  0      0.00%     67.56% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCmp                  0      0.00%     67.56% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCvt                  0      0.00%     67.56% # Class of executed instruction
+system.cpu0.op_class::SimdFloatDiv                  0      0.00%     67.56% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc               639      0.00%     67.56% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMult                 0      0.00%     67.56% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     67.56% # Class of executed instruction
+system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     67.56% # Class of executed instruction
+system.cpu0.op_class::MemRead                 7571296     16.82%     84.39% # Class of executed instruction
+system.cpu0.op_class::MemWrite                7026183     15.61%    100.00% # Class of executed instruction
 system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu0.op_class::total                  39212980                       # Class of executed instruction
+system.cpu0.op_class::total                  45002137                       # Class of executed instruction
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                   50449                       # number of quiesce instructions executed
-system.cpu0.icache.tags.replacements           428546                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.014878                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs           29820919                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs           429058                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            69.503235                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle      64538774500                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.014878                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.998076                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.998076                       # Average percentage of cache occupancy
+system.cpu0.kern.inst.quiesce                   42773                       # number of quiesce instructions executed
+system.cpu0.icache.tags.replacements           419775                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.035896                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs           37516680                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs           420287                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            89.264431                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle      64363581500                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.035896                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.998117                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.998117                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::2          508                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::3            4                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses         30679037                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses        30679037                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst     29820919                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total       29820919                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst     29820919                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total        29820919                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst     29820919                       # number of overall hits
-system.cpu0.icache.overall_hits::total       29820919                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst       429059                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total       429059                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst       429059                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total        429059                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst       429059                       # number of overall misses
-system.cpu0.icache.overall_misses::total       429059                       # number of overall misses
-system.cpu0.icache.ReadReq_accesses::cpu0.inst     30249978                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total     30249978                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst     30249978                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total     30249978                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst     30249978                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total     30249978                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.014184                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.014184                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.014184                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.014184                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.014184                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.014184                       # miss rate for overall accesses
+system.cpu0.icache.tags.tag_accesses         38357256                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses        38357256                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst     37516680                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total       37516680                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst     37516680                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total        37516680                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst     37516680                       # number of overall hits
+system.cpu0.icache.overall_hits::total       37516680                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst       420288                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total       420288                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst       420288                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total        420288                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst       420288                       # number of overall misses
+system.cpu0.icache.overall_misses::total       420288                       # number of overall misses
+system.cpu0.icache.ReadReq_accesses::cpu0.inst     37936968                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total     37936968                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst     37936968                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total     37936968                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst     37936968                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total     37936968                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.011079                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.011079                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.011079                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.011079                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.011079                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.011079                       # miss rate for overall accesses
 system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -482,68 +472,76 @@ system.cpu0.icache.avg_blocked_cycles::no_targets          nan
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.dcache.tags.replacements           323608                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          494.763142                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           12469968                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs           323980                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            38.489931                       # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle         22120000                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   494.763142                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.966334                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.966334                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_task_id_blocks::1024          372                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2          372                       # Occupied blocks per task id
-system.cpu0.dcache.tags.occ_task_id_percent::1024     0.726562                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses         51685336                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses        51685336                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data      6513975                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total        6513975                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data      5631422                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total       5631422                       # number of WriteReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       151763                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       151763                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       153180                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       153180                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data     12145397                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        12145397                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data     12145397                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       12145397                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data       197167                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total       197167                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data       167350                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total       167350                       # number of WriteReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         9208                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total         9208                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data         7466                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total         7466                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data       364517                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total        364517                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data       364517                       # number of overall misses
-system.cpu0.dcache.overall_misses::total       364517                       # number of overall misses
-system.cpu0.dcache.ReadReq_accesses::cpu0.data      6711142                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total      6711142                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data      5798772                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total      5798772                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       160971                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       160971                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       160646                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       160646                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data     12509914                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     12509914                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data     12509914                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     12509914                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.029379                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.029379                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.028860                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.028860                       # miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.057203                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.057203                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.046475                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.046475                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.029138                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.029138                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.029138                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.029138                       # miss rate for overall accesses
+system.cpu0.dcache.tags.replacements           348431                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          471.119339                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs           12834011                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs           348738                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            36.801298                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.warmup_cycle         22109000                       # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   471.119339                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.920155                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.920155                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_task_id_blocks::1024          307                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2          307                       # Occupied blocks per task id
+system.cpu0.dcache.tags.occ_task_id_percent::1024     0.599609                       # Percentage of cache occupancy per task id
+system.cpu0.dcache.tags.tag_accesses         53249455                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses        53249455                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data      6868875                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total        6868875                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data      5598061                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total       5598061                       # number of WriteReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu0.data        78744                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::total        78744                       # number of SoftPFReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       135195                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       135195                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data       136387                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       136387                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data     12466936                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total        12466936                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data     12545680                       # number of overall hits
+system.cpu0.dcache.overall_hits::total       12545680                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data       173318                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total       173318                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data       159147                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total       159147                       # number of WriteReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu0.data        50343                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::total        50343                       # number of SoftPFReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         9388                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total         9388                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data         7646                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total         7646                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data       332465                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total        332465                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data       382808                       # number of overall misses
+system.cpu0.dcache.overall_misses::total       382808                       # number of overall misses
+system.cpu0.dcache.ReadReq_accesses::cpu0.data      7042193                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total      7042193                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data      5757208                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total      5757208                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       129087                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total       129087                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       144583                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       144583                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       144033                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       144033                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data     12799401                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     12799401                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data     12928488                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     12928488                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.024611                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.024611                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.027643                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.027643                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.389993                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.389993                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.064932                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.064932                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.053085                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.053085                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.025975                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.025975                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.029610                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.029610                       # miss rate for overall accesses
 system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -552,8 +550,8 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       300957                       # number of writebacks
-system.cpu0.dcache.writebacks::total           300957                       # number of writebacks
+system.cpu0.dcache.writebacks::writebacks       321785                       # number of writebacks
+system.cpu0.dcache.writebacks::total           321785                       # number of writebacks
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
@@ -578,25 +576,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # D
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                     7365100                       # DTB read hits
-system.cpu1.dtb.read_misses                      3705                       # DTB read misses
-system.cpu1.dtb.write_hits                    5489754                       # DTB write hits
-system.cpu1.dtb.write_misses                     1595                       # DTB write misses
+system.cpu1.dtb.read_hits                     6028686                       # DTB read hits
+system.cpu1.dtb.read_misses                      5403                       # DTB read misses
+system.cpu1.dtb.write_hits                    4781604                       # DTB write hits
+system.cpu1.dtb.write_misses                     1104                       # DTB write misses
 system.cpu1.dtb.flush_tlb                           4                       # Number of times complete TLB was flushed
 system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
 system.cpu1.dtb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.dtb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                    1696                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.flush_entries                    2367                       # Number of entries that have been flushed from TLB
 system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                   145                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.prefetch_faults                   185                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                      204                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                 7368805                       # DTB read accesses
-system.cpu1.dtb.write_accesses                5491349                       # DTB write accesses
+system.cpu1.dtb.perms_faults                      267                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses                 6034089                       # DTB read accesses
+system.cpu1.dtb.write_accesses                4782708                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                         12854854                       # DTB hits
-system.cpu1.dtb.misses                           5300                       # DTB misses
-system.cpu1.dtb.accesses                     12860154                       # DTB accesses
+system.cpu1.dtb.hits                         10810290                       # DTB hits
+system.cpu1.dtb.misses                           6507                       # DTB misses
+system.cpu1.dtb.accesses                     10816797                       # DTB accesses
 system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -618,8 +616,8 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.inst_hits                    32413691                       # ITB inst hits
-system.cpu1.itb.inst_misses                      2200                       # ITB inst misses
+system.cpu1.itb.inst_hits                    24626141                       # ITB inst hits
+system.cpu1.itb.inst_misses                      3166                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
@@ -628,118 +626,120 @@ system.cpu1.itb.flush_tlb                           4                       # Nu
 system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
 system.cpu1.itb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.itb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                    1176                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries                    1581                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses                32415891                       # ITB inst accesses
-system.cpu1.itb.hits                         32413691                       # DTB hits
-system.cpu1.itb.misses                           2200                       # DTB misses
-system.cpu1.itb.accesses                     32415891                       # DTB accesses
-system.cpu1.numCycles                      1824196797                       # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses                24629307                       # ITB inst accesses
+system.cpu1.itb.hits                         24626141                       # DTB hits
+system.cpu1.itb.misses                           3166                       # DTB misses
+system.cpu1.itb.accesses                     24629307                       # DTB accesses
+system.cpu1.numCycles                      1801709576                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                   31877311                       # Number of instructions committed
-system.cpu1.committedOps                     40215396                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses             35862250                       # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses                  4436                       # Number of float alu accesses
-system.cpu1.num_func_calls                     955425                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts      4048275                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                    35862250                       # number of integer instructions
-system.cpu1.num_fp_insts                         4436                       # number of float instructions
-system.cpu1.num_int_register_reads          183631460                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes          39072446                       # number of times the integer registers were written
-system.cpu1.num_fp_register_reads                3022                       # number of times the floating registers were read
-system.cpu1.num_fp_register_writes               1416                       # number of times the floating registers were written
-system.cpu1.num_mem_refs                     13371151                       # number of memory refs
-system.cpu1.num_load_insts                    7642991                       # Number of load instructions
-system.cpu1.num_store_insts                   5728160                       # Number of store instructions
-system.cpu1.num_idle_cycles              1783402877.755682                       # Number of idle cycles
-system.cpu1.num_busy_cycles              40793919.244318                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.022363                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.977637                       # Percentage of idle cycles
-system.cpu1.Branches                          5037975                       # Number of branches fetched
-system.cpu1.op_class::No_OpClass                12508      0.03%      0.03% # Class of executed instruction
-system.cpu1.op_class::IntAlu                 26844895     66.65%     66.68% # Class of executed instruction
-system.cpu1.op_class::IntMult                   49628      0.12%     66.80% # Class of executed instruction
-system.cpu1.op_class::IntDiv                        0      0.00%     66.80% # Class of executed instruction
-system.cpu1.op_class::FloatAdd                      0      0.00%     66.80% # Class of executed instruction
-system.cpu1.op_class::FloatCmp                      0      0.00%     66.80% # Class of executed instruction
-system.cpu1.op_class::FloatCvt                      0      0.00%     66.80% # Class of executed instruction
-system.cpu1.op_class::FloatMult                     0      0.00%     66.80% # Class of executed instruction
-system.cpu1.op_class::FloatDiv                      0      0.00%     66.80% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt                     0      0.00%     66.80% # Class of executed instruction
-system.cpu1.op_class::SimdAdd                       0      0.00%     66.80% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc                    0      0.00%     66.80% # Class of executed instruction
-system.cpu1.op_class::SimdAlu                       0      0.00%     66.80% # Class of executed instruction
-system.cpu1.op_class::SimdCmp                       0      0.00%     66.80% # Class of executed instruction
-system.cpu1.op_class::SimdCvt                       0      0.00%     66.80% # Class of executed instruction
-system.cpu1.op_class::SimdMisc                      0      0.00%     66.80% # Class of executed instruction
-system.cpu1.op_class::SimdMult                      0      0.00%     66.80% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc                   0      0.00%     66.80% # Class of executed instruction
-system.cpu1.op_class::SimdShift                     0      0.00%     66.80% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc                  0      0.00%     66.80% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt                      0      0.00%     66.80% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd                  0      0.00%     66.80% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu                  0      0.00%     66.80% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp                  0      0.00%     66.80% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt                  0      0.00%     66.80% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv                  0      0.00%     66.80% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc               737      0.00%     66.80% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult                 0      0.00%     66.80% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     66.80% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     66.80% # Class of executed instruction
-system.cpu1.op_class::MemRead                 7642991     18.98%     85.78% # Class of executed instruction
-system.cpu1.op_class::MemWrite                5728160     14.22%    100.00% # Class of executed instruction
+system.cpu1.committedInsts                   23838609                       # Number of instructions committed
+system.cpu1.committedOps                     29191016                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses             25547086                       # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses                  5650                       # Number of float alu accesses
+system.cpu1.num_func_calls                     987842                       # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts      2987341                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                    25547086                       # number of integer instructions
+system.cpu1.num_fp_insts                         5650                       # number of float instructions
+system.cpu1.num_int_register_reads           48277330                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes          17495174                       # number of times the integer registers were written
+system.cpu1.num_fp_register_reads                3706                       # number of times the floating registers were read
+system.cpu1.num_fp_register_writes               1948                       # number of times the floating registers were written
+system.cpu1.num_cc_register_reads            86963152                       # number of times the CC registers were read
+system.cpu1.num_cc_register_writes           11050350                       # number of times the CC registers were written
+system.cpu1.num_mem_refs                     11165955                       # number of memory refs
+system.cpu1.num_load_insts                    6206289                       # Number of load instructions
+system.cpu1.num_store_insts                   4959666                       # Number of store instructions
+system.cpu1.num_idle_cycles              1771680344.893366                       # Number of idle cycles
+system.cpu1.num_busy_cycles              30029231.106634                       # Number of busy cycles
+system.cpu1.not_idle_fraction                0.016667                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                    0.983333                       # Percentage of idle cycles
+system.cpu1.Branches                          4459555                       # Number of branches fetched
+system.cpu1.op_class::No_OpClass                15552      0.05%      0.05% # Class of executed instruction
+system.cpu1.op_class::IntAlu                 18046643     61.66%     61.71% # Class of executed instruction
+system.cpu1.op_class::IntMult                   40424      0.14%     61.85% # Class of executed instruction
+system.cpu1.op_class::IntDiv                        0      0.00%     61.85% # Class of executed instruction
+system.cpu1.op_class::FloatAdd                      0      0.00%     61.85% # Class of executed instruction
+system.cpu1.op_class::FloatCmp                      0      0.00%     61.85% # Class of executed instruction
+system.cpu1.op_class::FloatCvt                      0      0.00%     61.85% # Class of executed instruction
+system.cpu1.op_class::FloatMult                     0      0.00%     61.85% # Class of executed instruction
+system.cpu1.op_class::FloatDiv                      0      0.00%     61.85% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt                     0      0.00%     61.85% # Class of executed instruction
+system.cpu1.op_class::SimdAdd                       0      0.00%     61.85% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc                    0      0.00%     61.85% # Class of executed instruction
+system.cpu1.op_class::SimdAlu                       0      0.00%     61.85% # Class of executed instruction
+system.cpu1.op_class::SimdCmp                       0      0.00%     61.85% # Class of executed instruction
+system.cpu1.op_class::SimdCvt                       0      0.00%     61.85% # Class of executed instruction
+system.cpu1.op_class::SimdMisc                      0      0.00%     61.85% # Class of executed instruction
+system.cpu1.op_class::SimdMult                      0      0.00%     61.85% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc                   0      0.00%     61.85% # Class of executed instruction
+system.cpu1.op_class::SimdShift                     0      0.00%     61.85% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc                  0      0.00%     61.85% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt                      0      0.00%     61.85% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd                  0      0.00%     61.85% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu                  0      0.00%     61.85% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp                  0      0.00%     61.85% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt                  0      0.00%     61.85% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv                  0      0.00%     61.85% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc              1539      0.01%     61.85% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult                 0      0.00%     61.85% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     61.85% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     61.85% # Class of executed instruction
+system.cpu1.op_class::MemRead                 6206289     21.20%     83.06% # Class of executed instruction
+system.cpu1.op_class::MemWrite                4959666     16.94%    100.00% # Class of executed instruction
 system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu1.op_class::total                  40278919                       # Class of executed instruction
+system.cpu1.op_class::total                  29270113                       # Class of executed instruction
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                   40450                       # number of quiesce instructions executed
-system.cpu1.icache.tags.replacements           433942                       # number of replacements
-system.cpu1.icache.tags.tagsinuse          475.447061                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs           31980510                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs           434454                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs            73.610808                       # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle      69969391500                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst   475.447061                       # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst     0.928608                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total     0.928608                       # Average percentage of cache occupancy
+system.cpu1.kern.inst.quiesce                   48301                       # number of quiesce instructions executed
+system.cpu1.icache.tags.replacements           442993                       # number of replacements
+system.cpu1.icache.tags.tagsinuse          472.644505                       # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs           24184321                       # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs           443505                       # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs            54.529985                       # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle     254679414000                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tags.occ_blocks::cpu1.inst   472.644505                       # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst     0.923134                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total     0.923134                       # Average percentage of cache occupancy
 system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::0          168                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::1           63                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::2          261                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::3           20                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::0          187                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::1           50                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::2          257                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::3           18                       # Occupied blocks per task id
 system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses         32849418                       # Number of tag accesses
-system.cpu1.icache.tags.data_accesses        32849418                       # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst     31980510                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total       31980510                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst     31980510                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total        31980510                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst     31980510                       # number of overall hits
-system.cpu1.icache.overall_hits::total       31980510                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst       434454                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total       434454                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst       434454                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total        434454                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst       434454                       # number of overall misses
-system.cpu1.icache.overall_misses::total       434454                       # number of overall misses
-system.cpu1.icache.ReadReq_accesses::cpu1.inst     32414964                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total     32414964                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst     32414964                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total     32414964                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst     32414964                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total     32414964                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.013403                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.013403                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.013403                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.013403                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.013403                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.013403                       # miss rate for overall accesses
+system.cpu1.icache.tags.tag_accesses         25071331                       # Number of tag accesses
+system.cpu1.icache.tags.data_accesses        25071331                       # Number of data accesses
+system.cpu1.icache.ReadReq_hits::cpu1.inst     24184321                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total       24184321                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst     24184321                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total        24184321                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst     24184321                       # number of overall hits
+system.cpu1.icache.overall_hits::total       24184321                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst       443505                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total       443505                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst       443505                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total        443505                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst       443505                       # number of overall misses
+system.cpu1.icache.overall_misses::total       443505                       # number of overall misses
+system.cpu1.icache.ReadReq_accesses::cpu1.inst     24627826                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total     24627826                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst     24627826                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total     24627826                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst     24627826                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total     24627826                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.018008                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.018008                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.018008                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.018008                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.018008                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.018008                       # miss rate for overall accesses
 system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -749,71 +749,79 @@ system.cpu1.icache.avg_blocked_cycles::no_targets          nan
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.dcache.tags.replacements           294289                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse          447.572964                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs           11708149                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs           294801                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs            39.715432                       # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle      67295121500                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data   447.572964                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data     0.874166                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total     0.874166                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.replacements           274056                       # number of replacements
+system.cpu1.dcache.tags.tagsinuse          468.122166                       # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs            9407683                       # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs           274568                       # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs            34.263581                       # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle      94419429000                       # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.occ_blocks::cpu1.data   468.122166                       # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data     0.914301                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total     0.914301                       # Average percentage of cache occupancy
 system.cpu1.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::0          267                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::1          226                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2           17                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::0          322                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::1          170                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2           19                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
 system.cpu1.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses         48419346                       # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses        48419346                       # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data      7002504                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total        7002504                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data      4520263                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total       4520263                       # number of WriteReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        77967                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total        77967                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data        79030                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total        79030                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data     11522767                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total        11522767                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data     11522767                       # number of overall hits
-system.cpu1.dcache.overall_hits::total       11522767                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data       198274                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total       198274                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data       126068                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total       126068                       # number of WriteReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        11260                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total        11260                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data        10133                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total        10133                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data       324342                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total        324342                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data       324342                       # number of overall misses
-system.cpu1.dcache.overall_misses::total       324342                       # number of overall misses
-system.cpu1.dcache.ReadReq_accesses::cpu1.data      7200778                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total      7200778                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data      4646331                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total      4646331                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        89227                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total        89227                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        89163                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total        89163                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data     11847109                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total     11847109                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data     11847109                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total     11847109                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.027535                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.027535                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.027133                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.027133                       # miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.126195                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.126195                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.113646                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total     0.113646                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.027377                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.027377                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.027377                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.027377                       # miss rate for overall accesses
+system.cpu1.dcache.tags.tag_accesses         39106907                       # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses        39106907                       # Number of data accesses
+system.cpu1.dcache.ReadReq_hits::cpu1.data      4611957                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total        4611957                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data      4543395                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total       4543395                       # number of WriteReq hits
+system.cpu1.dcache.SoftPFReq_hits::cpu1.data        35603                       # number of SoftPFReq hits
+system.cpu1.dcache.SoftPFReq_hits::total        35603                       # number of SoftPFReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        94939                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total        94939                       # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data        95657                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total        95657                       # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data      9155352                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total         9155352                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data      9190955                       # number of overall hits
+system.cpu1.dcache.overall_hits::total        9190955                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data       143554                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total       143554                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data       130048                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total       130048                       # number of WriteReq misses
+system.cpu1.dcache.SoftPFReq_misses::cpu1.data        27770                       # number of SoftPFReq misses
+system.cpu1.dcache.SoftPFReq_misses::total        27770                       # number of SoftPFReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        10527                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total        10527                       # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data         9468                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total         9468                       # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data       273602                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total        273602                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data       301372                       # number of overall misses
+system.cpu1.dcache.overall_misses::total       301372                       # number of overall misses
+system.cpu1.dcache.ReadReq_accesses::cpu1.data      4755511                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total      4755511                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data      4673443                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total      4673443                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::cpu1.data        63373                       # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::total        63373                       # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data       105466                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total       105466                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data       105125                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total       105125                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data      9428954                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total      9428954                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data      9492327                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total      9492327                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.030187                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.030187                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.027827                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.027827                       # miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.438199                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::total     0.438199                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.099814                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.099814                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.090064                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total     0.090064                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.029017                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.029017                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.031749                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.031749                       # miss rate for overall accesses
 system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -822,8 +830,8 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks       266849                       # number of writebacks
-system.cpu1.dcache.writebacks::total           266849                       # number of writebacks
+system.cpu1.dcache.writebacks::writebacks       249941                       # number of writebacks
+system.cpu1.dcache.writebacks::total           249941                       # number of writebacks
 system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.iocache.tags.replacements                    0                       # number of replacements
 system.iocache.tags.tagsinuse                       0                       # Cycle average of tags in use
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
index 04261a831..511b86cf1 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
@@ -1,18 +1,56 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.332812                       # Number of seconds simulated
-sim_ticks                                2332811899500                       # Number of ticks simulated
-final_tick                               2332811899500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.321351                       # Number of seconds simulated
+sim_ticks                                2321351025500                       # Number of ticks simulated
+final_tick                               2321351025500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 975328                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1254205                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            37662621026                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 462792                       # Number of bytes of host memory used
-host_seconds                                    61.94                       # Real time elapsed on the host
-sim_insts                                    60411489                       # Number of instructions simulated
-sim_ops                                      77685090                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 818788                       # Simulator instruction rate (inst/s)
+host_op_rate                                   985991                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            31464875718                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 430844                       # Number of bytes of host memory used
+host_seconds                                    73.78                       # Real time elapsed on the host
+sim_insts                                    60406834                       # Number of instructions simulated
+sim_ops                                      72742429                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
+system.physmem.bytes_read::realview.clcd    110100480                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker          320                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker          192                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst            705416                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           9071832                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            119878240                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       705416                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          705416                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      3703872                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu.data        3015816                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           6719688                       # Number of bytes written to this memory
+system.physmem.num_reads::realview.clcd      13762560                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.dtb.walker            5                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker            3                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst              17234                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             141773                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total              13921575                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           57873                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu.data            753954                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               811827                       # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd        47429483                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.dtb.walker            138                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker             83                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               303882                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              3907997                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                51641582                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          303882                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             303882                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1595567                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data             1299164                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                2894732                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1595567                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd       47429483                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker           138                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker            83                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              303882                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             5207161                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               54536314                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bytes_read::cpu.inst           20                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total            20                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_inst_read::cpu.inst           20                       # Number of instructions bytes read from this memory
@@ -25,46 +63,8 @@ system.realview.nvmem.bw_inst_read::cpu.inst            9
 system.realview.nvmem.bw_inst_read::total            9                       # Instruction read bandwidth from this memory (bytes/s)
 system.realview.nvmem.bw_total::cpu.inst            9                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::total               9                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bytes_read::realview.clcd    111673344                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.dtb.walker          320                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker          192                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst            705160                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           9071768                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            121450784                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       705160                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          705160                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      3703424                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu.data        3015816                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           6719240                       # Number of bytes written to this memory
-system.physmem.num_reads::realview.clcd      13959168                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.dtb.walker            5                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker            3                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst              17230                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             141782                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total              14118188                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           57866                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu.data            753954                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               811820                       # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd        47870702                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.dtb.walker            137                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker             82                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               302279                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              3888770                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                52061970                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          302279                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             302279                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1587536                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data             1292781                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2880318                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1587536                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd       47870702                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker           137                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker            82                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              302279                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             5181551                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               54942288                       # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput                     55969769                       # Throughput (bytes/s)
-system.membus.data_through_bus              130566943                       # Total data (bytes)
+system.membus.throughput                     55568847                       # Throughput (bytes/s)
+system.membus.data_through_bus              128994799                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
 system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
 system.cf0.dma_read_bytes                           0                       # Number of bytes transfered via DMA reads (not PRD).
@@ -72,8 +72,8 @@ system.cf0.dma_read_txs                             0                       # Nu
 system.cf0.dma_write_full_pages                     0                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                          0                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
-system.iobus.throughput                      48895283                       # Throughput (bytes/s)
-system.iobus.data_through_bus               114063499                       # Total data (bytes)
+system.iobus.throughput                      48459111                       # Throughput (bytes/s)
+system.iobus.data_through_bus               112490607                       # Total data (bytes)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
@@ -98,25 +98,25 @@ system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DT
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.read_hits                     14971763                       # DTB read hits
-system.cpu.dtb.read_misses                       7294                       # DTB read misses
-system.cpu.dtb.write_hits                    11217184                       # DTB write hits
+system.cpu.dtb.read_hits                     13142244                       # DTB read hits
+system.cpu.dtb.read_misses                       7297                       # DTB read misses
+system.cpu.dtb.write_hits                    11216207                       # DTB write hits
 system.cpu.dtb.write_misses                      2181                       # DTB write misses
 system.cpu.dtb.flush_tlb                            2                       # Number of times complete TLB was flushed
 system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
 system.cpu.dtb.flush_tlb_mva_asid                1439                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.dtb.flush_tlb_asid                      63                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries                     3403                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.flush_entries                     3399                       # Number of entries that have been flushed from TLB
 system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.dtb.prefetch_faults                    174                       # Number of TLB faults due to prefetch
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
 system.cpu.dtb.perms_faults                       452                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses                 14979057                       # DTB read accesses
-system.cpu.dtb.write_accesses                11219365                       # DTB write accesses
+system.cpu.dtb.read_accesses                 13149541                       # DTB read accesses
+system.cpu.dtb.write_accesses                11218388                       # DTB write accesses
 system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.hits                          26188947                       # DTB hits
-system.cpu.dtb.misses                            9475                       # DTB misses
-system.cpu.dtb.accesses                      26198422                       # DTB accesses
+system.cpu.dtb.hits                          24358451                       # DTB hits
+system.cpu.dtb.misses                            9478                       # DTB misses
+system.cpu.dtb.accesses                      24367929                       # DTB accesses
 system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -138,7 +138,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.inst_hits                     61434680                       # ITB inst hits
+system.cpu.itb.inst_hits                     61430007                       # ITB inst hits
 system.cpu.itb.inst_misses                       4471                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
@@ -155,105 +155,107 @@ system.cpu.itb.domain_faults                        0                       # Nu
 system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
 system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.inst_accesses                 61439151                       # ITB inst accesses
-system.cpu.itb.hits                          61434680                       # DTB hits
+system.cpu.itb.inst_accesses                 61434478                       # ITB inst accesses
+system.cpu.itb.hits                          61430007                       # DTB hits
 system.cpu.itb.misses                            4471                       # DTB misses
-system.cpu.itb.accesses                      61439151                       # DTB accesses
-system.cpu.numCycles                       4665623800                       # number of cpu cycles simulated
+system.cpu.itb.accesses                      61434478                       # DTB accesses
+system.cpu.numCycles                       4642702052                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                    60411489                       # Number of instructions committed
-system.cpu.committedOps                      77685090                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses              69133554                       # Number of integer alu accesses
+system.cpu.committedInsts                    60406834                       # Number of instructions committed
+system.cpu.committedOps                      72742429                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses              64191430                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                  10269                       # Number of float alu accesses
-system.cpu.num_func_calls                     2136078                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts      7942566                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                     69133554                       # number of integer instructions
+system.cpu.num_func_calls                     2135762                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts      7544984                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                     64191430                       # number of integer instructions
 system.cpu.num_fp_insts                         10269                       # number of float instructions
-system.cpu.num_int_register_reads           355910547                       # number of times the integer registers were read
-system.cpu.num_int_register_writes           74442273                       # number of times the integer registers were written
+system.cpu.num_int_register_reads           116427347                       # number of times the integer registers were read
+system.cpu.num_int_register_writes           42818107                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                 7493                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                2780                       # number of times the floating registers were written
-system.cpu.num_mem_refs                      27362421                       # number of memory refs
-system.cpu.num_load_insts                    15640088                       # Number of load instructions
-system.cpu.num_store_insts                   11722333                       # Number of store instructions
-system.cpu.num_idle_cycles               4586822073.007144                       # Number of idle cycles
-system.cpu.num_busy_cycles               78801726.992856                       # Number of busy cycles
-system.cpu.not_idle_fraction                 0.016890                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                     0.983110                       # Percentage of idle cycles
-system.cpu.Branches                          10299261                       # Number of branches fetched
+system.cpu.num_cc_register_reads            217570004                       # number of times the CC registers were read
+system.cpu.num_cc_register_writes            28977741                       # number of times the CC registers were written
+system.cpu.num_mem_refs                      25221274                       # number of memory refs
+system.cpu.num_load_insts                    13499937                       # Number of load instructions
+system.cpu.num_store_insts                   11721337                       # Number of store instructions
+system.cpu.num_idle_cycles               4568843017.980124                       # Number of idle cycles
+system.cpu.num_busy_cycles               73859034.019877                       # Number of busy cycles
+system.cpu.not_idle_fraction                 0.015909                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                     0.984091                       # Percentage of idle cycles
+system.cpu.Branches                          10298517                       # Number of branches fetched
 system.cpu.op_class::No_OpClass                 28518      0.04%      0.04% # Class of executed instruction
-system.cpu.op_class::IntAlu                  50337551     64.69%     64.72% # Class of executed instruction
-system.cpu.op_class::IntMult                    87780      0.11%     64.84% # Class of executed instruction
-system.cpu.op_class::IntDiv                         0      0.00%     64.84% # Class of executed instruction
-system.cpu.op_class::FloatAdd                       0      0.00%     64.84% # Class of executed instruction
-system.cpu.op_class::FloatCmp                       0      0.00%     64.84% # Class of executed instruction
-system.cpu.op_class::FloatCvt                       0      0.00%     64.84% # Class of executed instruction
-system.cpu.op_class::FloatMult                      0      0.00%     64.84% # Class of executed instruction
-system.cpu.op_class::FloatDiv                       0      0.00%     64.84% # Class of executed instruction
-system.cpu.op_class::FloatSqrt                      0      0.00%     64.84% # Class of executed instruction
-system.cpu.op_class::SimdAdd                        0      0.00%     64.84% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc                     0      0.00%     64.84% # Class of executed instruction
-system.cpu.op_class::SimdAlu                        0      0.00%     64.84% # Class of executed instruction
-system.cpu.op_class::SimdCmp                        0      0.00%     64.84% # Class of executed instruction
-system.cpu.op_class::SimdCvt                        0      0.00%     64.84% # Class of executed instruction
-system.cpu.op_class::SimdMisc                       0      0.00%     64.84% # Class of executed instruction
-system.cpu.op_class::SimdMult                       0      0.00%     64.84% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc                    0      0.00%     64.84% # Class of executed instruction
-system.cpu.op_class::SimdShift                      0      0.00%     64.84% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc                   0      0.00%     64.84% # Class of executed instruction
-system.cpu.op_class::SimdSqrt                       0      0.00%     64.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd                   0      0.00%     64.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu                   0      0.00%     64.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp                   0      0.00%     64.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt                   0      0.00%     64.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv                   0      0.00%     64.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc               2117      0.00%     64.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult                  0      0.00%     64.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc               0      0.00%     64.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt                  0      0.00%     64.84% # Class of executed instruction
-system.cpu.op_class::MemRead                 15640088     20.10%     84.94% # Class of executed instruction
-system.cpu.op_class::MemWrite                11722333     15.06%    100.00% # Class of executed instruction
+system.cpu.op_class::IntAlu                  47536032     65.23%     65.27% # Class of executed instruction
+system.cpu.op_class::IntMult                    87771      0.12%     65.39% # Class of executed instruction
+system.cpu.op_class::IntDiv                         0      0.00%     65.39% # Class of executed instruction
+system.cpu.op_class::FloatAdd                       0      0.00%     65.39% # Class of executed instruction
+system.cpu.op_class::FloatCmp                       0      0.00%     65.39% # Class of executed instruction
+system.cpu.op_class::FloatCvt                       0      0.00%     65.39% # Class of executed instruction
+system.cpu.op_class::FloatMult                      0      0.00%     65.39% # Class of executed instruction
+system.cpu.op_class::FloatDiv                       0      0.00%     65.39% # Class of executed instruction
+system.cpu.op_class::FloatSqrt                      0      0.00%     65.39% # Class of executed instruction
+system.cpu.op_class::SimdAdd                        0      0.00%     65.39% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc                     0      0.00%     65.39% # Class of executed instruction
+system.cpu.op_class::SimdAlu                        0      0.00%     65.39% # Class of executed instruction
+system.cpu.op_class::SimdCmp                        0      0.00%     65.39% # Class of executed instruction
+system.cpu.op_class::SimdCvt                        0      0.00%     65.39% # Class of executed instruction
+system.cpu.op_class::SimdMisc                       0      0.00%     65.39% # Class of executed instruction
+system.cpu.op_class::SimdMult                       0      0.00%     65.39% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc                    0      0.00%     65.39% # Class of executed instruction
+system.cpu.op_class::SimdShift                      0      0.00%     65.39% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc                   0      0.00%     65.39% # Class of executed instruction
+system.cpu.op_class::SimdSqrt                       0      0.00%     65.39% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd                   0      0.00%     65.39% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu                   0      0.00%     65.39% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp                   0      0.00%     65.39% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt                   0      0.00%     65.39% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv                   0      0.00%     65.39% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc               2113      0.00%     65.39% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult                  0      0.00%     65.39% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc               0      0.00%     65.39% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt                  0      0.00%     65.39% # Class of executed instruction
+system.cpu.op_class::MemRead                 13499937     18.52%     83.92% # Class of executed instruction
+system.cpu.op_class::MemWrite                11721337     16.08%    100.00% # Class of executed instruction
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::total                   77818387                       # Class of executed instruction
+system.cpu.op_class::total                   72875708                       # Class of executed instruction
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.quiesce                    82795                       # number of quiesce instructions executed
-system.cpu.icache.tags.replacements            850590                       # number of replacements
-system.cpu.icache.tags.tagsinuse           511.678462                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            60586338                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs            851102                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             71.185754                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle        5711018500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   511.678462                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.999372                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.999372                       # Average percentage of cache occupancy
+system.cpu.kern.inst.quiesce                    82781                       # number of quiesce instructions executed
+system.cpu.icache.tags.replacements            850515                       # number of replacements
+system.cpu.icache.tags.tagsinuse           511.689593                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            60581740                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs            851027                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             71.186625                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle        5455017500                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   511.689593                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.999394                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.999394                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          177                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1           78                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          255                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          200                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           62                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          249                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          62288542                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         62288542                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     60586338                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        60586338                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      60586338                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         60586338                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     60586338                       # number of overall hits
-system.cpu.icache.overall_hits::total        60586338                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst       851102                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total        851102                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst       851102                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total         851102                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst       851102                       # number of overall misses
-system.cpu.icache.overall_misses::total        851102                       # number of overall misses
-system.cpu.icache.ReadReq_accesses::cpu.inst     61437440                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     61437440                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     61437440                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     61437440                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     61437440                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     61437440                       # number of overall (read+write) accesses
+system.cpu.icache.tags.tag_accesses          62283794                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         62283794                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     60581740                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        60581740                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      60581740                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         60581740                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     60581740                       # number of overall hits
+system.cpu.icache.overall_hits::total        60581740                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst       851027                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total        851027                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst       851027                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total         851027                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst       851027                       # number of overall misses
+system.cpu.icache.overall_misses::total        851027                       # number of overall misses
+system.cpu.icache.ReadReq_accesses::cpu.inst     61432767                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     61432767                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     61432767                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     61432767                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     61432767                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     61432767                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.013853                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.013853                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.013853                       # miss rate for demand accesses
@@ -269,115 +271,115 @@ system.cpu.icache.avg_blocked_cycles::no_targets          nan
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements            62245                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        50007.460447                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            1669929                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           127630                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            13.084142                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle     2316903124500                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 36899.777920                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker     2.960146                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.993931                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  7014.716487                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  6089.011961                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.563046                       # Average percentage of cache occupancy
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+system.cpu.l2cache.tags.tagsinuse        50006.834636                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            1669916                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           127635                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            13.083527                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle     2306278064000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 36897.866975                       # Average occupied blocks per requestor
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 system.cpu.l2cache.tags.occ_task_id_blocks::1023            5                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_blocks::1024        65380                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1023::4            5                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0           40                       # Occupied blocks per task id
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-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         9187                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        52388                       # Occupied blocks per task id
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 system.cpu.l2cache.tags.occ_task_id_percent::1023     0.000076                       # Percentage of cache occupancy per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.997620                       # Percentage of cache occupancy per task id
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-system.cpu.l2cache.Writeback_hits::writebacks       592648                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total       592648                       # number of Writeback hits
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 system.cpu.l2cache.UpgradeReq_hits::cpu.data           26                       # number of UpgradeReq hits
 system.cpu.l2cache.UpgradeReq_hits::total           26                       # number of UpgradeReq hits
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 system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker            5                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_misses::cpu.itb.walker            3                       # number of ReadReq misses
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 system.cpu.l2cache.ReadReq_misses::cpu.data         9871                       # number of ReadReq misses
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-system.cpu.l2cache.Writeback_accesses::writebacks       592648                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total       592648                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data         2945                       # number of UpgradeReq accesses(hits+misses)
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-system.cpu.l2cache.ReadExReq_accesses::total       247209                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.dtb.walker         7512                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.itb.walker         3132                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.inst       849475                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data       623855                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      1483974                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.dtb.walker         7512                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.itb.walker         3132                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst       849475                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data       623855                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      1483974                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.000666                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.000958                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.012483                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.026208                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.016562                       # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.991171                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.991171                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.539908                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.539908                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.000666                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000958                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.012483                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.229767                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.103744                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.000666                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000958                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.012483                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.229767                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.103744                       # miss rate for overall accesses
+system.cpu.l2cache.overall_misses::cpu.inst        10608                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data       143345                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       153961                       # number of overall misses
+system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker         7546                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker         3154                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.inst       849401                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data       376661                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total      1236762                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks       592642                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total       592642                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data         2943                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total         2943                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       247180                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       247180                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.dtb.walker         7546                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.itb.walker         3154                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst       849401                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data       623841                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      1483942                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.dtb.walker         7546                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.itb.walker         3154                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst       849401                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data       623841                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      1483942                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.000663                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.000951                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.012489                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.026207                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.016565                       # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.991165                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total     0.991165                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.539987                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.539987                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.000663                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000951                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.012489                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.229778                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.103751                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.000663                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000951                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.012489                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.229778                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.103751                       # miss rate for overall accesses
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -386,69 +388,77 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        57866                       # number of writebacks
-system.cpu.l2cache.writebacks::total            57866                       # number of writebacks
+system.cpu.l2cache.writebacks::writebacks        57873                       # number of writebacks
+system.cpu.l2cache.writebacks::total            57873                       # number of writebacks
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements            623343                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.997030                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            23629012                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs            623855                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             37.875808                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle          21768000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.997030                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.replacements            623329                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.997018                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            21798545                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            623841                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             34.942469                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle          21757000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.997018                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.999994                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.999994                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          278                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          208                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2           26                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          291                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          197                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           24                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          97635323                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         97635323                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     13180574                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        13180574                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      9962233                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        9962233                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data       236039                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       236039                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data       247221                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total       247221                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      23142807                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         23142807                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     23142807                       # number of overall hits
-system.cpu.dcache.overall_hits::total        23142807                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       365463                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        365463                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       250154                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       250154                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data        11183                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total        11183                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data       615617                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total         615617                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data       615617                       # number of overall misses
-system.cpu.dcache.overall_misses::total        615617                       # number of overall misses
-system.cpu.dcache.ReadReq_accesses::cpu.data     13546037                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     13546037                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data     10212387                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total     10212387                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data       247222                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total       247222                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data       247221                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total       247221                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     23758424                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     23758424                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     23758424                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     23758424                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.026979                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.026979                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.024495                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.024495                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.045235                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.045235                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.025912                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.025912                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.025912                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.025912                       # miss rate for overall accesses
+system.cpu.dcache.tags.tag_accesses          90313385                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         90313385                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     11240226                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        11240226                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      9961316                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        9961316                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data       110856                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total        110856                       # number of SoftPFReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data       236008                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total       236008                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data       247196                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total       247196                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data      21201542                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         21201542                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     21312398                       # number of overall hits
+system.cpu.dcache.overall_hits::total        21312398                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       292030                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        292030                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       250123                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       250123                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data        73442                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total        73442                       # number of SoftPFReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data        11189                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total        11189                       # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data       542153                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total         542153                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data       615595                       # number of overall misses
+system.cpu.dcache.overall_misses::total        615595                       # number of overall misses
+system.cpu.dcache.ReadReq_accesses::cpu.data     11532256                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     11532256                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data     10211439                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total     10211439                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data       184298                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total       184298                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data       247197                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total       247197                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data       247196                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total       247196                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     21743695                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     21743695                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     21927993                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     21927993                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.025323                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.025323                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.024494                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.024494                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.398496                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.398496                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.045263                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.045263                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.024934                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.024934                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.028073                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.028073                       # miss rate for overall accesses
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -457,11 +467,11 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       592648                       # number of writebacks
-system.cpu.dcache.writebacks::total            592648                       # number of writebacks
+system.cpu.dcache.writebacks::writebacks       592642                       # number of writebacks
+system.cpu.dcache.writebacks::total            592642                       # number of writebacks
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.throughput                59102995                       # Throughput (bytes/s)
-system.cpu.toL2Bus.data_through_bus         137876171                       # Total data (bytes)
+system.cpu.toL2Bus.throughput                59392167                       # Throughput (bytes/s)
+system.cpu.toL2Bus.data_through_bus         137870067                       # Total data (bytes)
 system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
 system.iocache.tags.replacements                    0                       # number of replacements
 system.iocache.tags.tagsinuse                       0                       # Cycle average of tags in use
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
index 8e4b444a3..051c13810 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
@@ -1,156 +1,156 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  1.195945                       # Number of seconds simulated
-sim_ticks                                1195945260000                       # Number of ticks simulated
-final_tick                               1195945260000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  1.194312                       # Number of seconds simulated
+sim_ticks                                1194312178000                       # Number of ticks simulated
+final_tick                               1194312178000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 424891                       # Simulator instruction rate (inst/s)
-host_op_rate                                   541366                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             8267957779                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 468940                       # Number of bytes of host memory used
-host_seconds                                   144.65                       # Real time elapsed on the host
-sim_insts                                    61459750                       # Number of instructions simulated
-sim_ops                                      78307634                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 475403                       # Simulator instruction rate (inst/s)
+host_op_rate                                   567868                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             9241250441                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 438040                       # Number of bytes of host memory used
+host_seconds                                   129.24                       # Real time elapsed on the host
+sim_insts                                    61439698                       # Number of instructions simulated
+sim_ops                                      73389630                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::realview.clcd     51904512                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.dtb.walker           64                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.itb.walker          128                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst           393612                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data          4714684                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst           393932                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data          4710012                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu1.dtb.walker          256                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu1.itb.walker           64                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           324676                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data          4804472                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             62142468                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       393612                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       324676                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          718288                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      4110592                       # Number of bytes written to this memory
+system.physmem.bytes_read::cpu1.inst           323460                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data          4796088                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             62128516                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       393932                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       323460                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          717392                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      4097216                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.data         17000                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu1.data       3010344                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7137936                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7124560                       # Number of bytes written to this memory
 system.physmem.num_reads::realview.clcd       6488064                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu0.dtb.walker            1                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu0.itb.walker            2                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             12378                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data             73741                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             12383                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data             73653                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu1.dtb.walker            4                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu1.itb.walker            1                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              5164                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data             75098                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               6654453                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           64228                       # Number of write requests responded to by this memory
+system.physmem.num_reads::cpu1.inst              5145                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data             74957                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               6654210                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           64019                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.data             4250                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu1.data           752586                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               821064                       # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd        43400408                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total               820855                       # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd        43459753                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu0.dtb.walker            54                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu0.itb.walker           107                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst              329122                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data             3942224                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst              329840                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data             3943703                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu1.dtb.walker           214                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu1.itb.walker            54                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst              271481                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data             4017301                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                51960963                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         329122                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst         271481                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             600603                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           3437107                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data              14215                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data            2517125                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                5968447                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           3437107                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd       43400408                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst              270834                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data             4015774                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                52020332                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         329840                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst         270834                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             600674                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           3430607                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data              14234                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1.data            2520567                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                5965408                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           3430607                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd       43459753                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.dtb.walker           54                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.itb.walker          107                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             329122                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data            3956439                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             329840                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data            3957937                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu1.dtb.walker          214                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu1.itb.walker           54                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst             271481                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data            6534426                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               57929411                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                       6654453                       # Number of read requests accepted
-system.physmem.writeReqs                       821064                       # Number of write requests accepted
-system.physmem.readBursts                     6654453                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     821064                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                425841472                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     43520                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   7149184                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  62142468                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                7137936                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      680                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                  709327                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs          12098                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0              415328                       # Per bank write bursts
-system.physmem.perBankRdBursts::1              415212                       # Per bank write bursts
-system.physmem.perBankRdBursts::2              415403                       # Per bank write bursts
-system.physmem.perBankRdBursts::3              415611                       # Per bank write bursts
-system.physmem.perBankRdBursts::4              422397                       # Per bank write bursts
-system.physmem.perBankRdBursts::5              415577                       # Per bank write bursts
-system.physmem.perBankRdBursts::6              415747                       # Per bank write bursts
-system.physmem.perBankRdBursts::7              415496                       # Per bank write bursts
-system.physmem.perBankRdBursts::8              416027                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              415632                       # Per bank write bursts
-system.physmem.perBankRdBursts::10             415426                       # Per bank write bursts
-system.physmem.perBankRdBursts::11             414842                       # Per bank write bursts
-system.physmem.perBankRdBursts::12             414820                       # Per bank write bursts
-system.physmem.perBankRdBursts::13             415557                       # Per bank write bursts
-system.physmem.perBankRdBursts::14             415554                       # Per bank write bursts
-system.physmem.perBankRdBursts::15             415144                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                6840                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                6732                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                6969                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                7025                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                7326                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                7107                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                7317                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                7078                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                7464                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                7155                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               7023                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               6543                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               6616                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               6901                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               6977                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               6633                       # Per bank write bursts
+system.physmem.bw_total::cpu1.inst             270834                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data            6536341                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               57985740                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                       6654210                       # Number of read requests accepted
+system.physmem.writeReqs                       820855                       # Number of write requests accepted
+system.physmem.readBursts                     6654210                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     820855                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                425838464                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     30976                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   7136448                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  62128516                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                7124560                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      484                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                  709321                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs          12079                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0              415236                       # Per bank write bursts
+system.physmem.perBankRdBursts::1              415218                       # Per bank write bursts
+system.physmem.perBankRdBursts::2              415240                       # Per bank write bursts
+system.physmem.perBankRdBursts::3              415658                       # Per bank write bursts
+system.physmem.perBankRdBursts::4              422402                       # Per bank write bursts
+system.physmem.perBankRdBursts::5              415506                       # Per bank write bursts
+system.physmem.perBankRdBursts::6              415779                       # Per bank write bursts
+system.physmem.perBankRdBursts::7              415682                       # Per bank write bursts
+system.physmem.perBankRdBursts::8              416047                       # Per bank write bursts
+system.physmem.perBankRdBursts::9              415577                       # Per bank write bursts
+system.physmem.perBankRdBursts::10             415398                       # Per bank write bursts
+system.physmem.perBankRdBursts::11             414862                       # Per bank write bursts
+system.physmem.perBankRdBursts::12             415007                       # Per bank write bursts
+system.physmem.perBankRdBursts::13             415552                       # Per bank write bursts
+system.physmem.perBankRdBursts::14             415496                       # Per bank write bursts
+system.physmem.perBankRdBursts::15             415066                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                6763                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                6728                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                6819                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                7055                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                7301                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                7028                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                7316                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                7231                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                7485                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                7107                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               7000                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               6549                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               6696                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               6902                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               6960                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               6567                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    1195940759000                       # Total gap between requests
+system.physmem.totGap                    1194307723500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::2                    6849                       # Read request sizes (log2)
-system.physmem.readPktSize::3                 6488064                       # Read request sizes (log2)
+system.physmem.readPktSize::2                    6799                       # Read request sizes (log2)
+system.physmem.readPktSize::3                 6488089                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  159540                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  159322                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                 756836                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                  64228                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    572493                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    410656                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                    412880                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                    461685                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                    417933                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                    446395                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                   1149366                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                   1113988                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                   1438120                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                     64577                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                    50343                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                    45843                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                    44044                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                     8771                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                     8319                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                     8183                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                      162                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                       15                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                  64019                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    572550                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    410650                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                    412558                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                    460055                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                    417389                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                    445707                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                   1151151                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                   1116358                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                   1442650                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                     62467                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                    48974                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                    44870                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                    43130                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                     8689                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                     8270                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                     8147                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                      108                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                        3                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
@@ -180,24 +180,24 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     3947                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     4027                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     3883                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     3903                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::17                     6452                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     6482                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     6480                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::19                     6485                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     6483                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     6487                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     6486                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     6490                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     6486                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     6486                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     6484                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     6500                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     6486                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     6488                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     6485                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     6491                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     6485                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     6483                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     6485                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     6483                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     6486                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     6495                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     6488                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     6484                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::30                     6486                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     6485                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     6482                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     6484                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     6481                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
@@ -229,66 +229,67 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       473596                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      914.261641                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     784.047795                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     289.306705                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          25239      5.33%      5.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        21585      4.56%      9.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         5945      1.26%     11.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         2453      0.52%     11.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2290      0.48%     12.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1636      0.35%     12.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         4075      0.86%     13.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          899      0.19%     13.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151       409474     86.46%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         473596                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          6482                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean      1026.497532                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev    34346.134147                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-131071         6476     99.91%     99.91% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::131072-262143            3      0.05%     99.95% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::524288-655359            1      0.02%     99.97% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::786432-917503            1      0.02%     99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2.49037e+06-2.62144e+06            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            6482                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          6482                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        17.233261                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       17.205432                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        0.970583                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16               2453     37.84%     37.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17                 80      1.23%     39.08% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18               3936     60.72%     99.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19                 11      0.17%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                  1      0.02%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21                  1      0.02%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            6482                       # Writes before turning the bus around for reads
-system.physmem.totQLat                   171035006500                       # Total ticks spent queuing
-system.physmem.totMemAccLat              295793250250                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                  33268865000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       25704.97                       # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples       473292                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      914.815615                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     785.169464                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     288.643252                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          25022      5.29%      5.29% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        21566      4.56%      9.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         5869      1.24%     11.08% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         2391      0.51%     11.59% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2344      0.50%     12.08% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1629      0.34%     12.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         4093      0.86%     13.29% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          899      0.19%     13.48% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151       409479     86.52%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         473292                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          6481                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean      1026.648974                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev    26505.494009                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-65535          6473     99.88%     99.88% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::65536-131071            1      0.02%     99.89% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::196608-262143            3      0.05%     99.94% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::589824-655359            1      0.02%     99.95% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::786432-851967            1      0.02%     99.97% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::983040-1.04858e+06            1      0.02%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1.50733e+06-1.57286e+06            1      0.02%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total            6481                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          6481                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.205215                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       17.176618                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        0.984217                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               2581     39.82%     39.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17                 15      0.23%     40.06% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18               3862     59.59%     99.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19                 20      0.31%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                  3      0.05%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            6481                       # Writes before turning the bus around for reads
+system.physmem.totQLat                   170730095750                       # Total ticks spent queuing
+system.physmem.totMemAccLat              295487458250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                  33268630000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       25659.32                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  44454.97                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         356.07                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  44409.32                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         356.56                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           5.98                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       51.96                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       52.02                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        5.97                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           2.83                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       2.78                       # Data bus utilization in percentage for reads
+system.physmem.busUtilRead                       2.79                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.05                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         4.89                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        27.45                       # Average write queue length when enqueuing
-system.physmem.readRowHits                    6199461                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     92422                       # Number of row buffer hits during writes
+system.physmem.avgRdQLen                         4.36                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        23.98                       # Average write queue length when enqueuing
+system.physmem.readRowHits                    6199598                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     92343                       # Number of row buffer hits during writes
 system.physmem.readRowHitRate                   93.17                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  82.71                       # Row buffer hit rate for writes
-system.physmem.avgGap                       159981.01                       # Average gap between requests
+system.physmem.writeRowHitRate                  82.79                       # Row buffer hit rate for writes
+system.physmem.avgGap                       159772.22                       # Average gap between requests
 system.physmem.pageHitRate                      93.00                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE     947634468500                       # Time in different power states
-system.physmem.memoryStateTime::REF       39935220000                       # Time in different power states
+system.physmem.memoryStateTime::IDLE     945808643750                       # Time in different power states
+system.physmem.memoryStateTime::REF       39880620000                       # Time in different power states
 system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT      208375212750                       # Time in different power states
+system.physmem.memoryStateTime::ACT      208620525000                       # Time in different power states
 system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
 system.realview.nvmem.bytes_read::cpu0.inst           20                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu1.inst           48                       # Number of bytes read from this memory
@@ -308,314 +309,314 @@ system.realview.nvmem.bw_inst_read::total           57                       # I
 system.realview.nvmem.bw_total::cpu0.inst           17                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::cpu1.inst           40                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::total              57                       # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput                     59946686                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq             7703403                       # Transaction distribution
-system.membus.trans_dist::ReadResp            7703403                       # Transaction distribution
-system.membus.trans_dist::WriteReq             767582                       # Transaction distribution
-system.membus.trans_dist::WriteResp            767582                       # Transaction distribution
-system.membus.trans_dist::Writeback             64228                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            31700                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq          17261                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp           12098                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            137709                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           137266                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave      2382666                       # Packet count per connected master and slave (bytes)
+system.membus.throughput                     60005732                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq             7703348                       # Transaction distribution
+system.membus.trans_dist::ReadResp            7703348                       # Transaction distribution
+system.membus.trans_dist::WriteReq             767581                       # Transaction distribution
+system.membus.trans_dist::WriteResp            767581                       # Transaction distribution
+system.membus.trans_dist::Writeback             64019                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq            31325                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq          17234                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp           12079                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            137481                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           137066                       # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave      2382642                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           34                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        10310                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        10312                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio            4                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio          910                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      1972180                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total      4366104                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio          906                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      1971036                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total      4364934                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port     12976128                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::total     12976128                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total               17342232                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave      2390035                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count::total               17341062                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave      2389989                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port           68                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio        20620                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio        20624                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio            8                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio         1820                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port     17375892                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::total     19788443                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio         1812                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port     17348564                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::total     19761065                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port     51904512                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.iocache.mem_side::total     51904512                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total            71692955                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus               71692955                       # Total data (bytes)
+system.membus.tot_pkt_size::total            71665577                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus               71665577                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy          1224801000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy          1224785500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.1                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy               18000                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             9242500                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             9231500                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer4.occupancy                2500                       # Layer occupancy (ticks)
 system.membus.reqLayer4.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy              784500                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy              778500                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer6.occupancy          9211274000                       # Layer occupancy (ticks)
+system.membus.reqLayer6.occupancy          9212282000                       # Layer occupancy (ticks)
 system.membus.reqLayer6.utilization               0.8                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         5078680829                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         5079172023                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.4                       # Layer utilization (%)
-system.membus.respLayer2.occupancy        16046108250                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy        16050388750                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              1.3                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.l2c.tags.replacements                    69421                       # number of replacements
-system.l2c.tags.tagsinuse                53012.823108                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    1672128                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                   134609                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                    12.422111                       # Average number of references to valid blocks.
+system.l2c.tags.replacements                    69203                       # number of replacements
+system.l2c.tags.tagsinuse                52959.316379                       # Cycle average of tags in use
+system.l2c.tags.total_refs                    1672724                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                   134375                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                    12.448179                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   40185.217534                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker     0.000410                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::writebacks   40136.915421                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.dtb.walker     0.000411                       # Average occupied blocks per requestor
 system.l2c.tags.occ_blocks::cpu0.itb.walker     0.001544                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     3710.755623                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     4242.358437                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker     2.742287                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.itb.walker     0.001689                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst     2808.724549                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data     2063.021033                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.613178                       # Average percentage of cache occupancy
+system.l2c.tags.occ_blocks::cpu0.inst     3716.167205                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     4233.542603                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.dtb.walker     2.741623                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.itb.walker     0.001622                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst     2809.362324                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data     2060.583626                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.612441                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000000                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu0.itb.walker     0.000000                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.056622                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.064733                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst       0.056704                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data       0.064599                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000042                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu1.itb.walker     0.000000                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.042858                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.031479                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.808911                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.042867                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data       0.031442                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.808095                       # Average percentage of cache occupancy
 system.l2c.tags.occ_task_id_blocks::1023            5                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024        65183                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1024        65167                       # Occupied blocks per task id
 system.l2c.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
 system.l2c.tags.age_task_id_blocks_1023::4            4                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0           22                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1           39                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         1920                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         8039                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        55163                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0           20                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1           29                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2         1911                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3         8176                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        55031                       # Occupied blocks per task id
 system.l2c.tags.occ_task_id_percent::1023     0.000076                       # Percentage of cache occupancy per task id
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-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.808163                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.867030                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.832173                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.721584                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.818493                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.762985                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.543772                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.579302                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.561669                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker     0.000262                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker     0.001149                       # miss rate for demand accesses
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-system.l2c.overall_miss_rate::cpu0.dtb.walker     0.000262                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker     0.001149                       # miss rate for overall accesses
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-system.l2c.overall_miss_rate::cpu1.dtb.walker     0.000726                       # miss rate for overall accesses
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-system.l2c.overall_miss_rate::cpu1.inst      0.010784                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.279898                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.106784                       # miss rate for overall accesses
+system.l2c.overall_miss_latency::cpu0.inst    405931250                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.data   5050826913                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.dtb.walker       320500                       # number of overall miss cycles
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+system.l2c.overall_miss_latency::cpu1.inst    360408000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.data   5500430891                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total    11318174054                       # number of overall miss cycles
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+system.l2c.Writeback_accesses::writebacks       570720                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total           570720                       # number of Writeback accesses(hits+misses)
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+system.l2c.SCUpgradeReq_accesses::cpu0.data          781                       # number of SCUpgradeReq accesses(hits+misses)
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+system.l2c.overall_accesses::cpu0.dtb.walker         3945                       # number of overall (read+write) accesses
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+system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.000253                       # miss rate for ReadReq accesses
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+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.790047                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.877431                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.825845                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.725992                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.829525                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.769630                       # miss rate for SCUpgradeReq accesses
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+system.l2c.ReadExReq_miss_rate::cpu1.data     0.578753                       # miss rate for ReadExReq accesses
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 system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker        32000                       # average ReadReq miss latency
 system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker        74750                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.inst 70553.695955                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.data 73731.021399                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker        83625                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker        74500                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.inst 71431.468324                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.data 76496.609466                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 72838.350123                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  2723.417576                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  3282.117004                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total  2960.838871                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  3006.065487                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  5247.682008                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total  4033.383509                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 66977.414915                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 72375.831689                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 69782.089355                       # average ReadExReq miss latency
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+system.l2c.ReadReq_avg_miss_latency::cpu1.data 76605.779867                       # average ReadReq miss latency
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+system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  2640.272952                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  3222.485043                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total  2893.679377                       # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  3111.858907                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  5223.292373                       # average SCUpgradeReq miss latency
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 system.l2c.demand_avg_miss_latency::cpu0.dtb.walker        32000                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::cpu0.itb.walker        74750                       # average overall miss latency
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-system.l2c.demand_avg_miss_latency::cpu1.inst 71431.468324                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 72571.219688                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 70202.356341                       # average overall miss latency
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+system.l2c.demand_avg_miss_latency::cpu1.inst 71396.196513                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 72332.214126                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 69968.497067                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu0.dtb.walker        32000                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu0.itb.walker        74750                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 70553.695955                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 67684.589880                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.dtb.walker        83625                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.itb.walker        74500                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 71431.468324                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 72571.219688                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 70202.356341                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.inst 70707.411601                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data 67416.269527                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.dtb.walker        80125                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.itb.walker        75000                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 71396.196513                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 72332.214126                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 69968.497067                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -624,8 +625,8 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks               64228                       # number of writebacks
-system.l2c.writebacks::total                    64228                       # number of writebacks
+system.l2c.writebacks::writebacks               64019                       # number of writebacks
+system.l2c.writebacks::total                    64019                       # number of writebacks
 system.l2c.ReadReq_mshr_hits::cpu0.inst             1                       # number of ReadReq MSHR hits
 system.l2c.ReadReq_mshr_hits::total                 1                       # number of ReadReq MSHR hits
 system.l2c.demand_mshr_hits::cpu0.inst              1                       # number of demand (read+write) MSHR hits
@@ -634,161 +635,161 @@ system.l2c.overall_mshr_hits::cpu0.inst             1                       # nu
 system.l2c.overall_mshr_hits::total                 1                       # number of overall MSHR hits
 system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker            1                       # number of ReadReq MSHR misses
 system.l2c.ReadReq_mshr_misses::cpu0.itb.walker            2                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.inst         5735                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.data         7851                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu0.inst         5740                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu0.data         7844                       # number of ReadReq MSHR misses
 system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker            4                       # number of ReadReq MSHR misses
 system.l2c.ReadReq_mshr_misses::cpu1.itb.walker            1                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.inst         5067                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.data         3613                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total           22274                       # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0.data         4950                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data         3658                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total         8608                       # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          565                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu1.data          478                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::total         1043                       # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu0.data        67127                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data        72586                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total        139713                       # number of ReadExReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.inst         5048                       # number of ReadReq MSHR misses
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+system.l2c.UpgradeReq_mshr_misses::cpu0.data         4858                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.data         3744                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total         8602                       # number of UpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          567                       # number of SCUpgradeReq MSHR misses
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 system.l2c.demand_mshr_misses::cpu0.dtb.walker            1                       # number of demand (read+write) MSHR misses
 system.l2c.demand_mshr_misses::cpu0.itb.walker            2                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.inst         5735                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.data        74978                       # number of demand (read+write) MSHR misses
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+system.l2c.demand_mshr_misses::cpu0.data        74920                       # number of demand (read+write) MSHR misses
 system.l2c.demand_mshr_misses::cpu1.dtb.walker            4                       # number of demand (read+write) MSHR misses
 system.l2c.demand_mshr_misses::cpu1.itb.walker            1                       # number of demand (read+write) MSHR misses
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+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 58734.350238                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 64144.911504                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 60422.020983                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10006.865377                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10020.762019                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10012.913857                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10015.109347                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10009.472458                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10012.548604                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 53749.881836                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 59393.523292                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 56679.960281                       # average ReadExReq mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker        20000                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker        62500                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 57887.227550                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 54855.081624                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker        71125                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 58039.547038                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 54565.083729                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker        67500                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker        62500                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 58768.354056                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 59868.024895                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 57443.266676                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 58734.350238                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 59619.458537                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 57194.817495                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker        20000                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker        62500                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 57887.227550                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 54855.081624                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker        71125                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 58039.547038                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 54565.083729                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker        67500                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker        62500                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 58768.354056                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 59868.024895                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 57443.266676                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 58734.350238                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 59619.458537                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 57194.817495                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
@@ -809,64 +810,64 @@ system.cf0.dma_read_txs                             0                       # Nu
 system.cf0.dma_write_full_pages                     0                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                          0                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
-system.toL2Bus.throughput                   119513329                       # Throughput (bytes/s)
-system.toL2Bus.trans_dist::ReadReq            2535217                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           2535217                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq            767582                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp           767582                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback           570869                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq           30989                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq         17585                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp          48574                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           260651                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          260651                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side       863496                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      1226215                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side         6137                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        12691                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side       940498                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side      4601530                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side         6236                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side        15421                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               7672224                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     27215456                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     41348685                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side         6964                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        15244                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side     30072692                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side     39622266                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side         7640                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side        22032                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size::total          138310979                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.data_through_bus             138310979                       # Total data (bytes)
-system.toL2Bus.snoop_data_through_bus         4620420                       # Total snoop data (bytes)
-system.toL2Bus.reqLayer0.occupancy         4758868690                       # Layer occupancy (ticks)
+system.toL2Bus.throughput                   119643708                       # Throughput (bytes/s)
+system.toL2Bus.trans_dist::ReadReq            2534658                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp           2534658                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq            767581                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp           767581                       # Transaction distribution
+system.toL2Bus.trans_dist::Writeback           570720                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq           30701                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq         17545                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp          48246                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq           260694                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp          260694                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side       864108                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      1226294                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side         6184                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        12819                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side       939372                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side      4600756                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side         6173                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side        15243                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total               7670949                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     27234976                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     41362613                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side         7152                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        15780                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side     30036788                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side     39599456                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side         7388                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side        21348                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size::total          138285501                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.data_through_bus             138285501                       # Total data (bytes)
+system.toL2Bus.snoop_data_through_bus         4606436                       # Total snoop data (bytes)
+system.toL2Bus.reqLayer0.occupancy         4757764712                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.4                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy        1923485226                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy        1924888432                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.2                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy        1752589322                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy        1752701680                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy           4396000                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy           4396499                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy           8880000                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy           8876994                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer6.occupancy        2117887474                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer6.occupancy        2115350205                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer6.utilization             0.2                       # Layer utilization (%)
-system.toL2Bus.respLayer7.occupancy        2927028338                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer7.occupancy        2925844707                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer7.utilization             0.2                       # Layer utilization (%)
 system.toL2Bus.respLayer8.occupancy           4326000                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer8.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer9.occupancy           9913999                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer9.occupancy           9906999                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer9.utilization             0.0                       # Layer utilization (%)
-system.iobus.throughput                      45398856                       # Throughput (bytes/s)
-system.iobus.trans_dist::ReadReq              7671434                       # Transaction distribution
-system.iobus.trans_dist::ReadResp             7671434                       # Transaction distribution
-system.iobus.trans_dist::WriteReq                7963                       # Transaction distribution
-system.iobus.trans_dist::WriteResp               7963                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        30550                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio         8060                       # Packet count per connected master and slave (bytes)
+system.iobus.throughput                      45460895                       # Throughput (bytes/s)
+system.iobus.trans_dist::ReadReq              7671423                       # Transaction distribution
+system.iobus.trans_dist::ReadResp             7671423                       # Transaction distribution
+system.iobus.trans_dist::WriteReq                7962                       # Transaction distribution
+system.iobus.trans_dist::WriteResp               7962                       # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        30548                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio         8040                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio          742                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio          740                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio           36                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          496                       # Packet count per connected master and slave (bytes)
@@ -886,14 +887,14 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total      2382666                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total      2382642                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side     12976128                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.clcd.dma::total     12976128                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                15358794                       # Packet count per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio        40319                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio        16120                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count::total                15358770                       # Packet count per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio        40317                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio        16080                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio         1484                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio         1480                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio           72                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio          272                       # Cumulative packet size per connected master and slave (bytes)
@@ -913,18 +914,18 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::total      2390035                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::total      2389989                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side     51904512                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.realview.clcd.dma::total     51904512                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::total             54294547                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.data_through_bus                54294547                       # Total data (bytes)
-system.iobus.reqLayer0.occupancy             21418000                       # Layer occupancy (ticks)
+system.iobus.tot_pkt_size::total             54294501                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.data_through_bus                54294501                       # Total data (bytes)
+system.iobus.reqLayer0.occupancy             21416000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy              4036000                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy              4026000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer2.occupancy                34000                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy               377000                       # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy               376000                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer4.occupancy                27000                       # Layer occupancy (ticks)
 system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
@@ -966,9 +967,9 @@ system.iobus.reqLayer23.occupancy                8000                       # La
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer25.occupancy          6488064000                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.5                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy          2374703000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy          2374680000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.2                       # Layer utilization (%)
-system.iobus.respLayer1.occupancy         16368811750                       # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy         16364250250                       # Layer occupancy (ticks)
 system.iobus.respLayer1.utilization               1.4                       # Layer utilization (%)
 system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
@@ -993,25 +994,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # D
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                     7064335                       # DTB read hits
-system.cpu0.dtb.read_misses                      3758                       # DTB read misses
-system.cpu0.dtb.write_hits                    5649339                       # DTB write hits
-system.cpu0.dtb.write_misses                      802                       # DTB write misses
+system.cpu0.dtb.read_hits                     6063582                       # DTB read hits
+system.cpu0.dtb.read_misses                      3748                       # DTB read misses
+system.cpu0.dtb.write_hits                    5648980                       # DTB write hits
+system.cpu0.dtb.write_misses                      807                       # DTB write misses
 system.cpu0.dtb.flush_tlb                           4                       # Number of times complete TLB was flushed
 system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
 system.cpu0.dtb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.dtb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                    1711                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.flush_entries                    1709                       # Number of entries that have been flushed from TLB
 system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                   143                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.prefetch_faults                   140                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu0.dtb.perms_faults                      204                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                 7068093                       # DTB read accesses
-system.cpu0.dtb.write_accesses                5650141                       # DTB write accesses
+system.cpu0.dtb.read_accesses                 6067330                       # DTB read accesses
+system.cpu0.dtb.write_accesses                5649787                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                         12713674                       # DTB hits
-system.cpu0.dtb.misses                           4560                       # DTB misses
-system.cpu0.dtb.accesses                     12718234                       # DTB accesses
+system.cpu0.dtb.hits                         11712562                       # DTB hits
+system.cpu0.dtb.misses                           4555                       # DTB misses
+system.cpu0.dtb.accesses                     11717117                       # DTB accesses
 system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -1033,7 +1034,7 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.inst_hits                    29562995                       # ITB inst hits
+system.cpu0.itb.inst_hits                    29557926                       # ITB inst hits
 system.cpu0.itb.inst_misses                      2205                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
@@ -1050,123 +1051,125 @@ system.cpu0.itb.domain_faults                       0                       # Nu
 system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses                29565200                       # ITB inst accesses
-system.cpu0.itb.hits                         29562995                       # DTB hits
+system.cpu0.itb.inst_accesses                29560131                       # ITB inst accesses
+system.cpu0.itb.hits                         29557926                       # DTB hits
 system.cpu0.itb.misses                           2205                       # DTB misses
-system.cpu0.itb.accesses                     29565200                       # DTB accesses
-system.cpu0.numCycles                      2391890520                       # number of cpu cycles simulated
+system.cpu0.itb.accesses                     29560131                       # DTB accesses
+system.cpu0.numCycles                      2388624356                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                   28864889                       # Number of instructions committed
-system.cpu0.committedOps                     37190899                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses             33115613                       # Number of integer alu accesses
+system.cpu0.committedInsts                   28859743                       # Number of instructions committed
+system.cpu0.committedOps                     34624628                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses             30439288                       # Number of integer alu accesses
 system.cpu0.num_fp_alu_accesses                  3860                       # Number of float alu accesses
-system.cpu0.num_func_calls                    1241798                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts      4372441                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                    33115613                       # number of integer instructions
+system.cpu0.num_func_calls                    1241573                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts      4174263                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                    30439288                       # number of integer instructions
 system.cpu0.num_fp_insts                         3860                       # number of float instructions
-system.cpu0.num_int_register_reads          192173380                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes          36248506                       # number of times the integer registers were written
+system.cpu0.num_int_register_reads           53589242                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes          19764786                       # number of times the integer registers were written
 system.cpu0.num_fp_register_reads                3022                       # number of times the floating registers were read
 system.cpu0.num_fp_register_writes                840                       # number of times the floating registers were written
-system.cpu0.num_mem_refs                     13380838                       # number of memory refs
-system.cpu0.num_load_insts                    7401595                       # Number of load instructions
-system.cpu0.num_store_insts                   5979243                       # Number of store instructions
-system.cpu0.num_idle_cycles              2246179687.500122                       # Number of idle cycles
-system.cpu0.num_busy_cycles              145710832.499878                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.060919                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.939081                       # Percentage of idle cycles
-system.cpu0.Branches                          5600259                       # Number of branches fetched
-system.cpu0.op_class::No_OpClass                14567      0.04%      0.04% # Class of executed instruction
-system.cpu0.op_class::IntAlu                 24478507     64.56%     64.59% # Class of executed instruction
-system.cpu0.op_class::IntMult                   43773      0.12%     64.71% # Class of executed instruction
-system.cpu0.op_class::IntDiv                        0      0.00%     64.71% # Class of executed instruction
-system.cpu0.op_class::FloatAdd                      0      0.00%     64.71% # Class of executed instruction
-system.cpu0.op_class::FloatCmp                      0      0.00%     64.71% # Class of executed instruction
-system.cpu0.op_class::FloatCvt                      0      0.00%     64.71% # Class of executed instruction
-system.cpu0.op_class::FloatMult                     0      0.00%     64.71% # Class of executed instruction
-system.cpu0.op_class::FloatDiv                      0      0.00%     64.71% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt                     0      0.00%     64.71% # Class of executed instruction
-system.cpu0.op_class::SimdAdd                       0      0.00%     64.71% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc                    0      0.00%     64.71% # Class of executed instruction
-system.cpu0.op_class::SimdAlu                       0      0.00%     64.71% # Class of executed instruction
-system.cpu0.op_class::SimdCmp                       0      0.00%     64.71% # Class of executed instruction
-system.cpu0.op_class::SimdCvt                       0      0.00%     64.71% # Class of executed instruction
-system.cpu0.op_class::SimdMisc                      0      0.00%     64.71% # Class of executed instruction
-system.cpu0.op_class::SimdMult                      0      0.00%     64.71% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc                   0      0.00%     64.71% # Class of executed instruction
-system.cpu0.op_class::SimdShift                     0      0.00%     64.71% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc                  0      0.00%     64.71% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt                      0      0.00%     64.71% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd                  0      0.00%     64.71% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu                  0      0.00%     64.71% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp                  0      0.00%     64.71% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt                  0      0.00%     64.71% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv                  0      0.00%     64.71% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc               694      0.00%     64.71% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult                 0      0.00%     64.71% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     64.71% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     64.71% # Class of executed instruction
-system.cpu0.op_class::MemRead                 7401595     19.52%     84.23% # Class of executed instruction
-system.cpu0.op_class::MemWrite                5979243     15.77%    100.00% # Class of executed instruction
+system.cpu0.num_cc_register_reads           123695766                       # number of times the CC registers were read
+system.cpu0.num_cc_register_writes           15045730                       # number of times the CC registers were written
+system.cpu0.num_mem_refs                     12225186                       # number of memory refs
+system.cpu0.num_load_insts                    6245915                       # Number of load instructions
+system.cpu0.num_store_insts                   5979271                       # Number of store instructions
+system.cpu0.num_idle_cycles              2246427873.598119                       # Number of idle cycles
+system.cpu0.num_busy_cycles              142196482.401881                       # Number of busy cycles
+system.cpu0.not_idle_fraction                0.059531                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                    0.940469                       # Percentage of idle cycles
+system.cpu0.Branches                          5599312                       # Number of branches fetched
+system.cpu0.op_class::No_OpClass                14563      0.04%      0.04% # Class of executed instruction
+system.cpu0.op_class::IntAlu                 22957352     65.14%     65.18% # Class of executed instruction
+system.cpu0.op_class::IntMult                   43755      0.12%     65.31% # Class of executed instruction
+system.cpu0.op_class::IntDiv                        0      0.00%     65.31% # Class of executed instruction
+system.cpu0.op_class::FloatAdd                      0      0.00%     65.31% # Class of executed instruction
+system.cpu0.op_class::FloatCmp                      0      0.00%     65.31% # Class of executed instruction
+system.cpu0.op_class::FloatCvt                      0      0.00%     65.31% # Class of executed instruction
+system.cpu0.op_class::FloatMult                     0      0.00%     65.31% # Class of executed instruction
+system.cpu0.op_class::FloatDiv                      0      0.00%     65.31% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt                     0      0.00%     65.31% # Class of executed instruction
+system.cpu0.op_class::SimdAdd                       0      0.00%     65.31% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc                    0      0.00%     65.31% # Class of executed instruction
+system.cpu0.op_class::SimdAlu                       0      0.00%     65.31% # Class of executed instruction
+system.cpu0.op_class::SimdCmp                       0      0.00%     65.31% # Class of executed instruction
+system.cpu0.op_class::SimdCvt                       0      0.00%     65.31% # Class of executed instruction
+system.cpu0.op_class::SimdMisc                      0      0.00%     65.31% # Class of executed instruction
+system.cpu0.op_class::SimdMult                      0      0.00%     65.31% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc                   0      0.00%     65.31% # Class of executed instruction
+system.cpu0.op_class::SimdShift                     0      0.00%     65.31% # Class of executed instruction
+system.cpu0.op_class::SimdShiftAcc                  0      0.00%     65.31% # Class of executed instruction
+system.cpu0.op_class::SimdSqrt                      0      0.00%     65.31% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAdd                  0      0.00%     65.31% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAlu                  0      0.00%     65.31% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCmp                  0      0.00%     65.31% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCvt                  0      0.00%     65.31% # Class of executed instruction
+system.cpu0.op_class::SimdFloatDiv                  0      0.00%     65.31% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc               692      0.00%     65.31% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMult                 0      0.00%     65.31% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     65.31% # Class of executed instruction
+system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     65.31% # Class of executed instruction
+system.cpu0.op_class::MemRead                 6245915     17.72%     83.03% # Class of executed instruction
+system.cpu0.op_class::MemWrite                5979271     16.97%    100.00% # Class of executed instruction
 system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu0.op_class::total                  37918379                       # Class of executed instruction
+system.cpu0.op_class::total                  35241548                       # Class of executed instruction
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                   46956                       # number of quiesce instructions executed
-system.cpu0.icache.tags.replacements           424861                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          509.353809                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs           29137604                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs           425373                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            68.498950                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle      76246574000                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   509.353809                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.994832                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.994832                       # Average percentage of cache occupancy
+system.cpu0.kern.inst.quiesce                   47055                       # number of quiesce instructions executed
+system.cpu0.icache.tags.replacements           425168                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          509.375466                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs           29132228                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs           425680                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            68.436920                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle      75988011000                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   509.375466                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.994874                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.994874                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0           39                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          229                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2          233                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::3           11                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0           41                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1          188                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2          269                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::3           14                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses         29988352                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses        29988352                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst     29137604                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total       29137604                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst     29137604                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total        29137604                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst     29137604                       # number of overall hits
-system.cpu0.icache.overall_hits::total       29137604                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst       425374                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total       425374                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst       425374                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total        425374                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst       425374                       # number of overall misses
-system.cpu0.icache.overall_misses::total       425374                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst   5893447476                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total   5893447476                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst   5893447476                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total   5893447476                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst   5893447476                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total   5893447476                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst     29562978                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total     29562978                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst     29562978                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total     29562978                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst     29562978                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total     29562978                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.014389                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.014389                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.014389                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.014389                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.014389                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.014389                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13854.743064                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 13854.743064                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13854.743064                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 13854.743064                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13854.743064                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 13854.743064                       # average overall miss latency
+system.cpu0.icache.tags.tag_accesses         29983590                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses        29983590                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst     29132228                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total       29132228                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst     29132228                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total        29132228                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst     29132228                       # number of overall hits
+system.cpu0.icache.overall_hits::total       29132228                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst       425681                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total       425681                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst       425681                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total        425681                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst       425681                       # number of overall misses
+system.cpu0.icache.overall_misses::total       425681                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst   5899766682                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total   5899766682                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst   5899766682                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total   5899766682                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst   5899766682                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total   5899766682                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst     29557909                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total     29557909                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst     29557909                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total     29557909                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst     29557909                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total     29557909                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.014402                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.014402                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.014402                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.014402                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.014402                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.014402                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13859.595993                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 13859.595993                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13859.595993                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 13859.595993                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13859.595993                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 13859.595993                       # average overall miss latency
 system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1175,128 +1178,136 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       425374                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total       425374                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst       425374                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total       425374                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst       425374                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total       425374                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   5040497524                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total   5040497524                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   5040497524                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total   5040497524                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   5040497524                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total   5040497524                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    442131250                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total    442131250                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    442131250                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::total    442131250                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.014389                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.014389                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.014389                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.014389                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.014389                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.014389                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11849.566556                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11849.566556                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11849.566556                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 11849.566556                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11849.566556                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 11849.566556                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       425681                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total       425681                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst       425681                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total       425681                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst       425681                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total       425681                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   5046160318                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total   5046160318                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   5046160318                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total   5046160318                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   5046160318                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total   5046160318                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    442165750                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total    442165750                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    442165750                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::total    442165750                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.014402                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.014402                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.014402                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.014402                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.014402                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.014402                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11854.323585                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11854.323585                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11854.323585                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 11854.323585                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11854.323585                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 11854.323585                       # average overall mshr miss latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.dcache.tags.replacements           329701                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          455.940244                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           12258862                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs           330213                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            37.124105                       # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle        671876250                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   455.940244                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.890508                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.890508                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.replacements           329792                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          452.041842                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs           11239100                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs           330304                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            34.026533                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.warmup_cycle        671364250                       # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   452.041842                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.882894                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.882894                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0           72                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          340                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           98                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0           75                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          342                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           94                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses         50852546                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses        50852546                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data      6594319                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total        6594319                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data      5344510                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total       5344510                       # number of WriteReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       148000                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       148000                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       149609                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       149609                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data     11938829                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        11938829                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data     11938829                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       11938829                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data       227548                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total       227548                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data       141421                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total       141421                       # number of WriteReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         9358                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total         9358                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data         7517                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total         7517                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data       368969                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total        368969                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data       368969                       # number of overall misses
-system.cpu0.dcache.overall_misses::total       368969                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   3297192496                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total   3297192496                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data   5650617511                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total   5650617511                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data     92814250                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total     92814250                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data     44512065                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total     44512065                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data   8947810007                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total   8947810007                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data   8947810007                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total   8947810007                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data      6821867                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total      6821867                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data      5485931                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total      5485931                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       157358                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       157358                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       157126                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       157126                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data     12307798                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     12307798                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data     12307798                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     12307798                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.033356                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.033356                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.025779                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.025779                       # miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.059469                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.059469                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.047841                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.047841                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.029978                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.029978                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.029978                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.029978                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14490.096577                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 14490.096577                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 39956.000247                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 39956.000247                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data  9918.171618                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total  9918.171618                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data  5921.519888                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total  5921.519888                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 24250.844941                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 24250.844941                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 24250.844941                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 24250.844941                       # average overall miss latency
+system.cpu0.dcache.tags.tag_accesses         46848154                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses        46848154                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data      5514035                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total        5514035                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data      5340154                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total       5340154                       # number of WriteReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu0.data        64966                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::total        64966                       # number of SoftPFReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       148024                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       148024                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data       149636                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       149636                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data     10854189                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total        10854189                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data     10919155                       # number of overall hits
+system.cpu0.dcache.overall_hits::total       10919155                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data       179189                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total       179189                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data       145422                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total       145422                       # number of WriteReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu0.data        62829                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::total        62829                       # number of SoftPFReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         9439                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total         9439                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data         7485                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total         7485                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data       324611                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total        324611                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data       387440                       # number of overall misses
+system.cpu0.dcache.overall_misses::total       387440                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   2350643732                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total   2350643732                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data   5817567140                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total   5817567140                       # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data     94706749                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total     94706749                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data     44450567                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total     44450567                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data   8168210872                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total   8168210872                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data   8168210872                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total   8168210872                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data      5693224                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total      5693224                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data      5485576                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total      5485576                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       127795                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total       127795                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       157463                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       157463                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       157121                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       157121                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data     11178800                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     11178800                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data     11306595                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     11306595                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.031474                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.031474                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.026510                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.026510                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.491639                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.491639                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.059944                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.059944                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.047638                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.047638                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.029038                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.029038                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.034267                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.034267                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13118.236789                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 13118.236789                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40004.725145                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 40004.725145                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10033.557474                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10033.557474                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data  5938.619506                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total  5938.619506                       # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 25163.074794                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 25163.074794                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 21082.518253                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 21082.518253                       # average overall miss latency
 system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1305,62 +1316,78 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       305583                       # number of writebacks
-system.cpu0.dcache.writebacks::total           305583                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       227548                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       227548                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       141421                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       141421                       # number of WriteReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         9358                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total         9358                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data         7515                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total         7515                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data       368969                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total       368969                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data       368969                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total       368969                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   2840145504                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total   2840145504                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   5338354489                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total   5338354489                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     74046750                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     74046750                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data     29480935                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total     29480935                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   8178499993                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total   8178499993                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data   8178499993                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total   8178499993                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data  13564071000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total  13564071000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   1170919500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   1170919500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data  14734990500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total  14734990500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.033356                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.033356                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.025779                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.025779                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.059469                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.059469                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.047828                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.047828                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.029978                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.029978                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.029978                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.029978                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12481.522597                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12481.522597                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37747.961682                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37747.961682                       # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data  7912.668305                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total  7912.668305                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data  3922.945442                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total  3922.945442                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22165.818790                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 22165.818790                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22165.818790                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22165.818790                       # average overall mshr miss latency
+system.cpu0.dcache.writebacks::writebacks       305747                       # number of writebacks
+system.cpu0.dcache.writebacks::total           305747                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data          276                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total          276                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data         4042                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total         4042                       # number of WriteReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data         4318                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total         4318                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data         4318                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total         4318                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       178913                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total       178913                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       141380                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       141380                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data        48508                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total        48508                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         9439                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total         9439                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data         7483                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total         7483                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data       320293                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total       320293                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data       368801                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total       368801                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   1988652518                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total   1988652518                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   5320324110                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total   5320324110                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data    853626758                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total    853626758                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     75777251                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     75777251                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data     29483433                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total     29483433                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   7308976628                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total   7308976628                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data   8162603386                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total   8162603386                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data  13564535750                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total  13564535750                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   1170801000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   1170801000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data  14735336750                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total  14735336750                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.031426                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.031426                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.025773                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.025773                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.379577                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.379577                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.059944                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.059944                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.047626                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.047626                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.028652                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.028652                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.032618                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.032618                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11115.192960                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11115.192960                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37631.377210                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37631.377210                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 17597.649006                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 17597.649006                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data  8028.101600                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total  8028.101600                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data  3940.055192                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total  3940.055192                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22819.657713                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 22819.657713                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22132.812509                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22132.812509                       # average overall mshr miss latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
@@ -1391,25 +1418,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # D
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                     8317790                       # DTB read hits
-system.cpu1.dtb.read_misses                      3645                       # DTB read misses
-system.cpu1.dtb.write_hits                    5833574                       # DTB write hits
-system.cpu1.dtb.write_misses                     1433                       # DTB write misses
+system.cpu1.dtb.read_hits                     7408792                       # DTB read hits
+system.cpu1.dtb.read_misses                      3640                       # DTB read misses
+system.cpu1.dtb.write_hits                    5825509                       # DTB write hits
+system.cpu1.dtb.write_misses                     1435                       # DTB write misses
 system.cpu1.dtb.flush_tlb                           4                       # Number of times complete TLB was flushed
 system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
 system.cpu1.dtb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.dtb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                    1863                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.flush_entries                    1866                       # Number of entries that have been flushed from TLB
 system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                   144                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.prefetch_faults                   141                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu1.dtb.perms_faults                      248                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                 8321435                       # DTB read accesses
-system.cpu1.dtb.write_accesses                5835007                       # DTB write accesses
+system.cpu1.dtb.read_accesses                 7412432                       # DTB read accesses
+system.cpu1.dtb.write_accesses                5826944                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                         14151364                       # DTB hits
-system.cpu1.dtb.misses                           5078                       # DTB misses
-system.cpu1.dtb.accesses                     14156442                       # DTB accesses
+system.cpu1.dtb.hits                         13234301                       # DTB hits
+system.cpu1.dtb.misses                           5075                       # DTB misses
+system.cpu1.dtb.accesses                     13239376                       # DTB accesses
 system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -1431,7 +1458,7 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.inst_hits                    33205963                       # ITB inst hits
+system.cpu1.itb.inst_hits                    33190882                       # ITB inst hits
 system.cpu1.itb.inst_misses                      2171                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
@@ -1448,122 +1475,123 @@ system.cpu1.itb.domain_faults                       0                       # Nu
 system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses                33208134                       # ITB inst accesses
-system.cpu1.itb.hits                         33205963                       # DTB hits
+system.cpu1.itb.inst_accesses                33193053                       # ITB inst accesses
+system.cpu1.itb.hits                         33190882                       # DTB hits
 system.cpu1.itb.misses                           2171                       # DTB misses
-system.cpu1.itb.accesses                     33208134                       # DTB accesses
-system.cpu1.numCycles                      2390414629                       # number of cpu cycles simulated
+system.cpu1.itb.accesses                     33193053                       # DTB accesses
+system.cpu1.numCycles                      2387219429                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                   32594861                       # Number of instructions committed
-system.cpu1.committedOps                     41116735                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses             37639270                       # Number of integer alu accesses
+system.cpu1.committedInsts                   32579955                       # Number of instructions committed
+system.cpu1.committedOps                     38765002                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses             35167643                       # Number of integer alu accesses
 system.cpu1.num_fp_alu_accesses                  6793                       # Number of float alu accesses
-system.cpu1.num_func_calls                     962738                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts      3734786                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                    37639270                       # number of integer instructions
+system.cpu1.num_func_calls                     962341                       # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts      3529676                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                    35167643                       # number of integer instructions
 system.cpu1.num_fp_insts                         6793                       # number of float instructions
-system.cpu1.num_int_register_reads          218315433                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes          39777331                       # number of times the integer registers were written
+system.cpu1.num_int_register_reads           64976079                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes          23977665                       # number of times the integer registers were written
 system.cpu1.num_fp_register_reads                4535                       # number of times the floating registers were read
 system.cpu1.num_fp_register_writes               2260                       # number of times the floating registers were written
-system.cpu1.num_mem_refs                     14690124                       # number of memory refs
-system.cpu1.num_load_insts                    8639728                       # Number of load instructions
-system.cpu1.num_store_insts                   6050396                       # Number of store instructions
-system.cpu1.num_idle_cycles              1874297798.309079                       # Number of idle cycles
-system.cpu1.num_busy_cycles              516116830.690921                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.215911                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.784089                       # Percentage of idle cycles
-system.cpu1.Branches                          4947313                       # Number of branches fetched
-system.cpu1.op_class::No_OpClass                14267      0.03%      0.03% # Class of executed instruction
-system.cpu1.op_class::IntAlu                 26968126     64.63%     64.67% # Class of executed instruction
-system.cpu1.op_class::IntMult                   50231      0.12%     64.79% # Class of executed instruction
-system.cpu1.op_class::IntDiv                        0      0.00%     64.79% # Class of executed instruction
-system.cpu1.op_class::FloatAdd                      0      0.00%     64.79% # Class of executed instruction
-system.cpu1.op_class::FloatCmp                      0      0.00%     64.79% # Class of executed instruction
-system.cpu1.op_class::FloatCvt                      0      0.00%     64.79% # Class of executed instruction
-system.cpu1.op_class::FloatMult                     0      0.00%     64.79% # Class of executed instruction
-system.cpu1.op_class::FloatDiv                      0      0.00%     64.79% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt                     0      0.00%     64.79% # Class of executed instruction
-system.cpu1.op_class::SimdAdd                       0      0.00%     64.79% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc                    0      0.00%     64.79% # Class of executed instruction
-system.cpu1.op_class::SimdAlu                       0      0.00%     64.79% # Class of executed instruction
-system.cpu1.op_class::SimdCmp                       0      0.00%     64.79% # Class of executed instruction
-system.cpu1.op_class::SimdCvt                       0      0.00%     64.79% # Class of executed instruction
-system.cpu1.op_class::SimdMisc                      0      0.00%     64.79% # Class of executed instruction
-system.cpu1.op_class::SimdMult                      0      0.00%     64.79% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc                   0      0.00%     64.79% # Class of executed instruction
-system.cpu1.op_class::SimdShift                     0      0.00%     64.79% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc                  0      0.00%     64.79% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt                      0      0.00%     64.79% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd                  0      0.00%     64.79% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu                  0      0.00%     64.79% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp                  0      0.00%     64.79% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt                  0      0.00%     64.79% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv                  0      0.00%     64.79% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc              1470      0.00%     64.79% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult                 0      0.00%     64.79% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     64.79% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     64.79% # Class of executed instruction
-system.cpu1.op_class::MemRead                 8639728     20.71%     85.50% # Class of executed instruction
-system.cpu1.op_class::MemWrite                6050396     14.50%    100.00% # Class of executed instruction
+system.cpu1.num_cc_register_reads           139669414                       # number of times the CC registers were read
+system.cpu1.num_cc_register_writes           14465628                       # number of times the CC registers were written
+system.cpu1.num_mem_refs                     13620676                       # number of memory refs
+system.cpu1.num_load_insts                    7578910                       # Number of load instructions
+system.cpu1.num_store_insts                   6041766                       # Number of store instructions
+system.cpu1.num_idle_cycles              1873842319.884373                       # Number of idle cycles
+system.cpu1.num_busy_cycles              513377109.115627                       # Number of busy cycles
+system.cpu1.not_idle_fraction                0.215052                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                    0.784948                       # Percentage of idle cycles
+system.cpu1.Branches                          4944984                       # Number of branches fetched
+system.cpu1.op_class::No_OpClass                14265      0.04%      0.04% # Class of executed instruction
+system.cpu1.op_class::IntAlu                 25564023     65.13%     65.17% # Class of executed instruction
+system.cpu1.op_class::IntMult                   50133      0.13%     65.29% # Class of executed instruction
+system.cpu1.op_class::IntDiv                        0      0.00%     65.29% # Class of executed instruction
+system.cpu1.op_class::FloatAdd                      0      0.00%     65.29% # Class of executed instruction
+system.cpu1.op_class::FloatCmp                      0      0.00%     65.29% # Class of executed instruction
+system.cpu1.op_class::FloatCvt                      0      0.00%     65.29% # Class of executed instruction
+system.cpu1.op_class::FloatMult                     0      0.00%     65.29% # Class of executed instruction
+system.cpu1.op_class::FloatDiv                      0      0.00%     65.29% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt                     0      0.00%     65.29% # Class of executed instruction
+system.cpu1.op_class::SimdAdd                       0      0.00%     65.29% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc                    0      0.00%     65.29% # Class of executed instruction
+system.cpu1.op_class::SimdAlu                       0      0.00%     65.29% # Class of executed instruction
+system.cpu1.op_class::SimdCmp                       0      0.00%     65.29% # Class of executed instruction
+system.cpu1.op_class::SimdCvt                       0      0.00%     65.29% # Class of executed instruction
+system.cpu1.op_class::SimdMisc                      0      0.00%     65.29% # Class of executed instruction
+system.cpu1.op_class::SimdMult                      0      0.00%     65.29% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc                   0      0.00%     65.29% # Class of executed instruction
+system.cpu1.op_class::SimdShift                     0      0.00%     65.29% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc                  0      0.00%     65.29% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt                      0      0.00%     65.29% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd                  0      0.00%     65.29% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu                  0      0.00%     65.29% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp                  0      0.00%     65.29% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt                  0      0.00%     65.29% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv                  0      0.00%     65.29% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc              1482      0.00%     65.30% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult                 0      0.00%     65.30% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     65.30% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     65.30% # Class of executed instruction
+system.cpu1.op_class::MemRead                 7578910     19.31%     84.61% # Class of executed instruction
+system.cpu1.op_class::MemWrite                6041766     15.39%    100.00% # Class of executed instruction
 system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu1.op_class::total                  41724218                       # Class of executed instruction
+system.cpu1.op_class::total                  39250579                       # Class of executed instruction
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                   44363                       # number of quiesce instructions executed
-system.cpu1.icache.tags.replacements           469889                       # number of replacements
-system.cpu1.icache.tags.tagsinuse          478.549875                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs           32735558                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs           470401                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs            69.590749                       # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle      93998064500                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst   478.549875                       # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst     0.934668                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total     0.934668                       # Average percentage of cache occupancy
+system.cpu1.kern.inst.quiesce                   44258                       # number of quiesce instructions executed
+system.cpu1.icache.tags.replacements           469324                       # number of replacements
+system.cpu1.icache.tags.tagsinuse          478.642267                       # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs           32721042                       # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs           469836                       # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs            69.643539                       # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle      93149552500                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tags.occ_blocks::cpu1.inst   478.642267                       # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst     0.934848                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total     0.934848                       # Average percentage of cache occupancy
 system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::2          448                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::3           63                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::4            1                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::2          456                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::3           56                       # Occupied blocks per task id
 system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses         33676360                       # Number of tag accesses
-system.cpu1.icache.tags.data_accesses        33676360                       # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst     32735558                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total       32735558                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst     32735558                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total        32735558                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst     32735558                       # number of overall hits
-system.cpu1.icache.overall_hits::total       32735558                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst       470401                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total       470401                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst       470401                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total        470401                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst       470401                       # number of overall misses
-system.cpu1.icache.overall_misses::total       470401                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   6443025224                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total   6443025224                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst   6443025224                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total   6443025224                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst   6443025224                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total   6443025224                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst     33205959                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total     33205959                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst     33205959                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total     33205959                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst     33205959                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total     33205959                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.014166                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.014166                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.014166                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.014166                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.014166                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.014166                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13696.878246                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 13696.878246                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13696.878246                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 13696.878246                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13696.878246                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 13696.878246                       # average overall miss latency
+system.cpu1.icache.tags.tag_accesses         33660714                       # Number of tag accesses
+system.cpu1.icache.tags.data_accesses        33660714                       # Number of data accesses
+system.cpu1.icache.ReadReq_hits::cpu1.inst     32721042                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total       32721042                       # number of ReadReq hits
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+system.cpu1.icache.demand_hits::total        32721042                       # number of demand (read+write) hits
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+system.cpu1.icache.overall_hits::total       32721042                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst       469836                       # number of ReadReq misses
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+system.cpu1.icache.demand_misses::cpu1.inst       469836                       # number of demand (read+write) misses
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+system.cpu1.icache.overall_misses::cpu1.inst       469836                       # number of overall misses
+system.cpu1.icache.overall_misses::total       469836                       # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   6435695955                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total   6435695955                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst   6435695955                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total   6435695955                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst   6435695955                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total   6435695955                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst     33190878                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total     33190878                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst     33190878                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total     33190878                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst     33190878                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total     33190878                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.014156                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.014156                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.014156                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.014156                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.014156                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.014156                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13697.749757                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 13697.749757                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13697.749757                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 13697.749757                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13697.749757                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 13697.749757                       # average overall miss latency
 system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1572,190 +1600,214 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       470401                       # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total       470401                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst       470401                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total       470401                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst       470401                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total       470401                       # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   5500320776                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total   5500320776                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   5500320776                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total   5500320776                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   5500320776                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total   5500320776                       # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      7094750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      7094750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      7094750                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::total      7094750                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.014166                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.014166                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.014166                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.014166                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.014166                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.014166                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11692.833935                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11692.833935                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11692.833935                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 11692.833935                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11692.833935                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 11692.833935                       # average overall mshr miss latency
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       469836                       # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total       469836                       # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst       469836                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total       469836                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst       469836                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total       469836                       # number of overall MSHR misses
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   5494111045                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total   5494111045                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   5494111045                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total   5494111045                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   5494111045                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total   5494111045                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      6835750                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      6835750                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      6835750                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::total      6835750                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.014156                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.014156                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.014156                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total     0.014156                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.014156                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total     0.014156                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11693.678315                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11693.678315                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11693.678315                       # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total 11693.678315                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11693.678315                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total 11693.678315                       # average overall mshr miss latency
 system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
 system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.dcache.tags.replacements           292396                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse          471.340913                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs           11973732                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs           292744                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs            40.901716                       # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle      85301409250                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data   471.340913                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data     0.920588                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total     0.920588                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024          348                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2          333                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::3           15                       # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024     0.679688                       # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses         49486795                       # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses        49486795                       # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data      6952689                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total        6952689                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data      4832965                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total       4832965                       # number of WriteReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        82012                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total        82012                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data        82761                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total        82761                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data     11785654                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total        11785654                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data     11785654                       # number of overall hits
-system.cpu1.dcache.overall_hits::total       11785654                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data       170655                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total       170655                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data       150219                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total       150219                       # number of WriteReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        11301                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total        11301                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data        10073                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total        10073                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data       320874                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total        320874                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data       320874                       # number of overall misses
-system.cpu1.dcache.overall_misses::total       320874                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   2212742497                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total   2212742497                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   6365695527                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total   6365695527                       # number of WriteReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data     97206750                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total     97206750                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data     52182477                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total     52182477                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data   8578438024                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total   8578438024                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data   8578438024                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total   8578438024                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data      7123344                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total      7123344                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data      4983184                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total      4983184                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        93313                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total        93313                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        92834                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total        92834                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data     12106528                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total     12106528                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data     12106528                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total     12106528                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.023957                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.023957                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.030145                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.030145                       # miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.121109                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.121109                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.108506                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total     0.108506                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.026504                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.026504                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.026504                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.026504                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12966.174428                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 12966.174428                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 42376.101072                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 42376.101072                       # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data  8601.606053                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total  8601.606053                       # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data  5180.430557                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total  5180.430557                       # average StoreCondReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 26734.599949                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 26734.599949                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 26734.599949                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 26734.599949                       # average overall miss latency
-system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu1.dcache.tags.replacements           292234                       # number of replacements
+system.cpu1.dcache.tags.tagsinuse          471.923930                       # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs           11040887                       # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs           292603                       # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs            37.733335                       # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle      84705826250                       # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.occ_blocks::cpu1.data   471.923930                       # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data     0.921726                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total     0.921726                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_task_id_blocks::1024          369                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2          356                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::3           13                       # Occupied blocks per task id
+system.cpu1.dcache.tags.occ_task_id_percent::1024     0.720703                       # Percentage of cache occupancy per task id
+system.cpu1.dcache.tags.tag_accesses         45818347                       # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses        45818347                       # Number of data accesses
+system.cpu1.dcache.ReadReq_hits::cpu1.data      6006097                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total        6006097                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data      4823101                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total       4823101                       # number of WriteReq hits
+system.cpu1.dcache.SoftPFReq_hits::cpu1.data        22483                       # number of SoftPFReq hits
+system.cpu1.dcache.SoftPFReq_hits::total        22483                       # number of SoftPFReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        81936                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total        81936                       # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data        82707                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total        82707                       # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data     10829198                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total        10829198                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data     10851681                       # number of overall hits
+system.cpu1.dcache.overall_hits::total       10851681                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data       144053                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total       144053                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data       152082                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total       152082                       # number of WriteReq misses
+system.cpu1.dcache.SoftPFReq_misses::cpu1.data        41875                       # number of SoftPFReq misses
+system.cpu1.dcache.SoftPFReq_misses::total        41875                       # number of SoftPFReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        11222                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total        11222                       # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data        10064                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total        10064                       # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data       296135                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total        296135                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data       338010                       # number of overall misses
+system.cpu1.dcache.overall_misses::total       338010                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   1718496498                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total   1718496498                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   6437170330                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total   6437170330                       # number of WriteReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data     96291249                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total     96291249                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data     52005971                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total     52005971                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data   8155666828                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total   8155666828                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data   8155666828                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total   8155666828                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data      6150150                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total      6150150                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data      4975183                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total      4975183                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::cpu1.data        64358                       # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::total        64358                       # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        93158                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total        93158                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        92771                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total        92771                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data     11125333                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total     11125333                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data     11189691                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total     11189691                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.023423                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.023423                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.030568                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.030568                       # miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.650657                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::total     0.650657                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.120462                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.120462                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.108482                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total     0.108482                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.026618                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.026618                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.030207                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.030207                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 11929.612698                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 11929.612698                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 42326.970516                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 42326.970516                       # average WriteReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data  8580.578239                       # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total  8580.578239                       # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data  5167.524940                       # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total  5167.524940                       # average StoreCondReq miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 27540.367832                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 27540.367832                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 24128.477939                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 24128.477939                       # average overall miss latency
+system.cpu1.dcache.blocked_cycles::no_mshrs           57                       # number of cycles access was blocked
 system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_mshrs                1                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_mshrs           57                       # average number of cycles each access was blocked
 system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks       265286                       # number of writebacks
-system.cpu1.dcache.writebacks::total           265286                       # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       170655                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total       170655                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data       150219                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total       150219                       # number of WriteReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data        11301                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total        11301                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        10070                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total        10070                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data       320874                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total       320874                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data       320874                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total       320874                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   1870737503                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1870737503                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   6042583473                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total   6042583473                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     74594250                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     74594250                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data     32041523                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total     32041523                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   7913320976                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total   7913320976                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   7913320976                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total   7913320976                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168608523750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168608523750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data  25187494163                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total  25187494163                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 193796017913                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total 193796017913                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.023957                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.023957                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.030145                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.030145                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.121109                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.121109                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.108473                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.108473                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.026504                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.026504                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.026504                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.026504                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10962.101919                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10962.101919                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 40225.161085                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 40225.161085                       # average WriteReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data  6600.676931                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total  6600.676931                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data  3181.879146                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total  3181.879146                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 24661.770589                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 24661.770589                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 24661.770589                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 24661.770589                       # average overall mshr miss latency
+system.cpu1.dcache.writebacks::writebacks       264973                       # number of writebacks
+system.cpu1.dcache.writebacks::total           264973                       # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data          379                       # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total          379                       # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data         2067                       # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total         2067                       # number of WriteReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data         2446                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total         2446                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data         2446                       # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total         2446                       # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       143674                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total       143674                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data       150015                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total       150015                       # number of WriteReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data        26855                       # number of SoftPFReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::total        26855                       # number of SoftPFReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data        11222                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total        11222                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        10062                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total        10062                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data       293689                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total       293689                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data       320544                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total       320544                       # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   1427169251                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1427169251                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   6022199670                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total   6022199670                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    445093004                       # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total    445093004                       # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     73834751                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     73834751                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data     31881029                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total     31881029                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   7449368921                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total   7449368921                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   7894461925                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total   7894461925                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168604609000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168604609000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data  25187299088                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total  25187299088                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 193791908088                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total 193791908088                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.023361                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.023361                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.030153                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.030153                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.417275                       # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.417275                       # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.120462                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.120462                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.108461                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.108461                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.026398                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total     0.026398                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.028646                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total     0.028646                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data  9933.385658                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total  9933.385658                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 40143.983402                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 40143.983402                       # average WriteReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16573.934239                       # average SoftPFReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16573.934239                       # average SoftPFReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data  6579.464534                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total  6579.464534                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data  3168.458458                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total  3168.458458                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 25364.821022                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 25364.821022                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 24628.325363                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 24628.325363                       # average overall mshr miss latency
 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
@@ -1779,10 +1831,10 @@ system.iocache.avg_blocked_cycles::no_mshrs          nan                       #
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 745373562750                       # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 745373562750                       # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 745373562750                       # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 745373562750                       # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 745112259250                       # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 745112259250                       # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 745112259250                       # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 745112259250                       # number of overall MSHR uncacheable cycles
 system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average ReadReq mshr uncacheable latency
 system.iocache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average overall mshr uncacheable latency
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
index 41f066b07..563f1978d 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
@@ -1,146 +1,134 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.616230                       # Number of seconds simulated
-sim_ticks                                2616229847000                       # Number of ticks simulated
-final_tick                               2616229847000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.614581                       # Number of seconds simulated
+sim_ticks                                2614581252500                       # Number of ticks simulated
+final_tick                               2614581252500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 375445                       # Simulator instruction rate (inst/s)
-host_op_rate                                   477768                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            16316419265                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 464828                       # Number of bytes of host memory used
-host_seconds                                   160.34                       # Real time elapsed on the host
-sim_insts                                    60200042                       # Number of instructions simulated
-sim_ops                                      76606857                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 331710                       # Simulator instruction rate (inst/s)
+host_op_rate                                   396174                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            14409825510                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 433940                       # Number of bytes of host memory used
+host_seconds                                   181.44                       # Real time elapsed on the host
+sim_insts                                    60186875                       # Number of instructions simulated
+sim_ops                                      71883476                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.realview.nvmem.bytes_read::cpu.inst           20                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total            20                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu.inst           20                       # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total           20                       # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu.inst            5                       # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total              5                       # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu.inst             8                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total                8                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu.inst            8                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total            8                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu.inst            8                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total               8                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bytes_read::realview.clcd    122683392                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.dtb.walker          320                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.itb.walker          128                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst            703560                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           9089944                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            132477344                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       703560                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          703560                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      3706304                       # Number of bytes written to this memory
+system.physmem.bytes_read::cpu.inst            704520                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           9109080                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            132497440                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       704520                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          704520                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      3720512                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu.data        3016072                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           6722376                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           6736584                       # Number of bytes written to this memory
 system.physmem.num_reads::realview.clcd      15335424                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.dtb.walker            5                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.itb.walker            2                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst              17205                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             142066                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total              15494702                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           57911                       # Number of write requests responded to by this memory
+system.physmem.num_reads::cpu.inst              17220                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             142355                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total              15495006                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           58133                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu.data            754018                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               811929                       # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd        46893201                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total               812151                       # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd        46922769                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu.dtb.walker            122                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu.itb.walker             49                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               268921                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              3474444                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                50636737                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          268921                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             268921                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1416658                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data             1152831                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2569490                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1416658                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd       46893201                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               269458                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              3483954                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                50676352                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          269458                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             269458                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1422986                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data             1153558                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                2576544                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1422986                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd       46922769                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.dtb.walker           122                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.itb.walker            49                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              268921                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             4627275                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               53206227                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                      15494702                       # Number of read requests accepted
-system.physmem.writeReqs                       811929                       # Number of write requests accepted
-system.physmem.readBursts                    15494702                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     811929                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                991533248                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                    127680                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   6729728                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                 132477344                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                6722376                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                     1995                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                  706751                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs           4516                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0              967982                       # Per bank write bursts
-system.physmem.perBankRdBursts::1              967715                       # Per bank write bursts
-system.physmem.perBankRdBursts::2              967669                       # Per bank write bursts
-system.physmem.perBankRdBursts::3              967754                       # Per bank write bursts
-system.physmem.perBankRdBursts::4              974564                       # Per bank write bursts
-system.physmem.perBankRdBursts::5              968184                       # Per bank write bursts
-system.physmem.perBankRdBursts::6              967779                       # Per bank write bursts
-system.physmem.perBankRdBursts::7              967692                       # Per bank write bursts
-system.physmem.perBankRdBursts::8              968544                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              968137                       # Per bank write bursts
-system.physmem.perBankRdBursts::10             967949                       # Per bank write bursts
-system.physmem.perBankRdBursts::11             967746                       # Per bank write bursts
-system.physmem.perBankRdBursts::12             967851                       # Per bank write bursts
-system.physmem.perBankRdBursts::13             967741                       # Per bank write bursts
-system.physmem.perBankRdBursts::14             967800                       # Per bank write bursts
-system.physmem.perBankRdBursts::15             967600                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                6503                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                6305                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                6309                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                6231                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                6800                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                6982                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                6786                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                6777                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                7080                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                6733                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               6548                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               6441                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               6486                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               6281                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               6425                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               6465                       # Per bank write bursts
+system.physmem.bw_total::cpu.inst              269458                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             4637512                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               53252896                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                      15495006                       # Number of read requests accepted
+system.physmem.writeReqs                       812151                       # Number of write requests accepted
+system.physmem.readBursts                    15495006                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     812151                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                991553920                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                    126464                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   6744512                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                 132497440                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                6736584                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                     1976                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                  706747                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs           4511                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0              968147                       # Per bank write bursts
+system.physmem.perBankRdBursts::1              967810                       # Per bank write bursts
+system.physmem.perBankRdBursts::2              967673                       # Per bank write bursts
+system.physmem.perBankRdBursts::3              967915                       # Per bank write bursts
+system.physmem.perBankRdBursts::4              974375                       # Per bank write bursts
+system.physmem.perBankRdBursts::5              968054                       # Per bank write bursts
+system.physmem.perBankRdBursts::6              967653                       # Per bank write bursts
+system.physmem.perBankRdBursts::7              967480                       # Per bank write bursts
+system.physmem.perBankRdBursts::8              968459                       # Per bank write bursts
+system.physmem.perBankRdBursts::9              968209                       # Per bank write bursts
+system.physmem.perBankRdBursts::10             967967                       # Per bank write bursts
+system.physmem.perBankRdBursts::11             967960                       # Per bank write bursts
+system.physmem.perBankRdBursts::12             967929                       # Per bank write bursts
+system.physmem.perBankRdBursts::13             967878                       # Per bank write bursts
+system.physmem.perBankRdBursts::14             967953                       # Per bank write bursts
+system.physmem.perBankRdBursts::15             967568                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                6652                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                6388                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                6319                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                6364                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                6622                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                6858                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                6646                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                6573                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                7007                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                6769                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               6571                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               6647                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               6565                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               6381                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               6555                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               6466                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    2616225486000                       # Total gap between requests
+system.physmem.totGap                    2614576987500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::2                    6664                       # Read request sizes (log2)
-system.physmem.readPktSize::3                15335424                       # Read request sizes (log2)
+system.physmem.readPktSize::2                    6644                       # Read request sizes (log2)
+system.physmem.readPktSize::3                15335434                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  152614                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  152928                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                 754018                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                  57911                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                   1126567                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    970563                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                    976518                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                   1090618                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                    986596                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                   1051326                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                   2724005                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                   2632042                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                   3421723                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                    136210                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                   113171                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                   104737                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                   101252                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                    19730                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                    18895                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                    18668                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                       86                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                  58133                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                   1126497                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    970808                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                    976433                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                   1092616                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                    986699                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                   1053397                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                   2722203                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                   2628336                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                   3415970                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                    138177                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                   115073                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                   106569                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                   103082                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                    19658                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                    18818                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                    18605                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                       89                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
@@ -171,24 +159,24 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     3804                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     3835                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     6081                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     6095                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     6100                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     6096                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     6099                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     6095                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     6098                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     6095                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     6095                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     6095                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     6101                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     6096                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     6095                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     6094                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     6095                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     6094                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     3716                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     3737                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     6110                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     6121                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     6124                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     6122                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     6122                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     6122                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     6123                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     6121                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     6120                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     6124                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     6124                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     6121                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     6120                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     6121                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     6120                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     6121                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
@@ -220,124 +208,136 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples      1027354                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      971.683544                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     905.447521                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     204.224200                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          22943      2.23%      2.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        22460      2.19%      4.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         8461      0.82%      5.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         2563      0.25%      5.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2504      0.24%      5.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1783      0.17%      5.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         8706      0.85%      6.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          969      0.09%      6.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151       956965     93.15%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total        1027354                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          6094                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean      2542.286675                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev    118884.715097                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-524287         6090     99.93%     99.93% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::524288-1.04858e+06            2      0.03%     99.97% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2.09715e+06-2.62144e+06            1      0.02%     99.98% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples      1027240                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      971.825895                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     905.842120                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     203.903622                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          22776      2.22%      2.22% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        22448      2.19%      4.40% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         8450      0.82%      5.23% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         2555      0.25%      5.47% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2575      0.25%      5.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1819      0.18%      5.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         8664      0.84%      6.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          942      0.09%      6.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151       957011     93.16%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total        1027240                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          6120                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean      2531.539869                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev    116318.280129                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-524287         6115     99.92%     99.92% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::524288-1.04858e+06            3      0.05%     99.97% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1.04858e+06-1.57286e+06            1      0.02%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::8.38861e+06-8.9129e+06            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            6094                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          6094                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        17.255005                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       17.227328                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        0.967528                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16               2261     37.10%     37.10% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17                 29      0.48%     37.58% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18               3794     62.26%     99.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19                  9      0.15%     99.98% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total            6120                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          6120                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.219444                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       17.191199                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        0.977796                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               2386     38.99%     38.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17                 19      0.31%     39.30% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18               3702     60.49%     99.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19                 12      0.20%     99.98% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::20                  1      0.02%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            6094                       # Writes before turning the bus around for reads
-system.physmem.totQLat                   400062590250                       # Total ticks spent queuing
-system.physmem.totMemAccLat              690550846500                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                  77463535000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       25822.64                       # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::total            6120                       # Writes before turning the bus around for reads
+system.physmem.totQLat                   400457727500                       # Total ticks spent queuing
+system.physmem.totMemAccLat              690952040000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                  77465150000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       25847.61                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  44572.64                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         378.99                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           2.57                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       50.64                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        2.57                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  44597.61                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         379.24                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           2.58                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       50.68                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        2.58                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           2.98                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       2.96                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         6.59                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        24.10                       # Average write queue length when enqueuing
-system.physmem.readRowHits                   14482119                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     88386                       # Number of row buffer hits during writes
+system.physmem.avgRdQLen                         6.67                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        26.38                       # Average write queue length when enqueuing
+system.physmem.readRowHits                   14482583                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     88590                       # Number of row buffer hits during writes
 system.physmem.readRowHitRate                   93.48                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  84.03                       # Row buffer hit rate for writes
-system.physmem.avgGap                       160439.36                       # Average gap between requests
+system.physmem.writeRowHitRate                  84.05                       # Row buffer hit rate for writes
+system.physmem.avgGap                       160333.10                       # Average gap between requests
 system.physmem.pageHitRate                      93.41                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE     2245273695250                       # Time in different power states
-system.physmem.memoryStateTime::REF       87361560000                       # Time in different power states
+system.physmem.memoryStateTime::IDLE     2239817846000                       # Time in different power states
+system.physmem.memoryStateTime::REF       87306440000                       # Time in different power states
 system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT      283591722250                       # Time in different power states
+system.physmem.memoryStateTime::ACT      287452006500                       # Time in different power states
 system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.membus.throughput                     54122917                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq            16546592                       # Transaction distribution
-system.membus.trans_dist::ReadResp           16546592                       # Transaction distribution
-system.membus.trans_dist::WriteReq             763385                       # Transaction distribution
-system.membus.trans_dist::WriteResp            763385                       # Transaction distribution
-system.membus.trans_dist::Writeback             57911                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             4516                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp            4516                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            132219                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           132219                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave      2383090                       # Packet count per connected master and slave (bytes)
+system.realview.nvmem.bytes_read::cpu.inst           20                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total            20                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu.inst           20                       # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total           20                       # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu.inst            5                       # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total              5                       # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu.inst             8                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total                8                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu.inst            8                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total            8                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu.inst            8                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total               8                       # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput                     54170150                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq            16546653                       # Transaction distribution
+system.membus.trans_dist::ReadResp           16546653                       # Transaction distribution
+system.membus.trans_dist::WriteReq             763381                       # Transaction distribution
+system.membus.trans_dist::WriteResp            763381                       # Transaction distribution
+system.membus.trans_dist::Writeback             58133                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq             4511                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp            4511                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            132457                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           132457                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave      2383082                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           10                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         3850                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         3840                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio            2                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1893535                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total      4280487                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1894355                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total      4281289                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port     30670848                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::total     30670848                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total               34951335                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave      2390546                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count::total               34952137                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave      2390530                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port           20                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio         7700                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio         7680                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio            4                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     16516328                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total     18914598                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     16550632                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total     18948866                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port    122683392                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.iocache.mem_side::total    122683392                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total           141597990                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus              141597990                       # Total data (bytes)
+system.membus.tot_pkt_size::total           141632258                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus              141632258                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy          1206224000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy          1207280500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy                5000                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             3616500                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             3534000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer4.occupancy                1000                       # Layer occupancy (ticks)
 system.membus.reqLayer4.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer6.occupancy         17911182500                       # Layer occupancy (ticks)
+system.membus.reqLayer6.occupancy         17916889500                       # Layer occupancy (ticks)
 system.membus.reqLayer6.utilization               0.7                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         4951111812                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         4952195664                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
-system.membus.respLayer2.occupancy        37928474750                       # Layer occupancy (ticks)
-system.membus.respLayer2.utilization              1.4                       # Layer utilization (%)
+system.membus.respLayer2.occupancy        37921268500                       # Layer occupancy (ticks)
+system.membus.respLayer2.utilization              1.5                       # Layer utilization (%)
 system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
 system.cf0.dma_read_bytes                           0                       # Number of bytes transfered via DMA reads (not PRD).
 system.cf0.dma_read_txs                             0                       # Number of DMA read transactions (not PRD).
 system.cf0.dma_write_full_pages                     0                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                          0                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
-system.iobus.throughput                      47806938                       # Throughput (bytes/s)
-system.iobus.trans_dist::ReadReq             16518786                       # Transaction distribution
-system.iobus.trans_dist::ReadResp            16518786                       # Transaction distribution
-system.iobus.trans_dist::WriteReq                8183                       # Transaction distribution
-system.iobus.trans_dist::WriteResp               8183                       # Transaction distribution
+system.iobus.throughput                      47837076                       # Throughput (bytes/s)
+system.iobus.trans_dist::ReadReq             16518783                       # Transaction distribution
+system.iobus.trans_dist::ReadResp            16518783                       # Transaction distribution
+system.iobus.trans_dist::WriteReq                8182                       # Transaction distribution
+system.iobus.trans_dist::WriteResp               8182                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        30038                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio         7946                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio          534                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio         1042                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio         7942                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio          532                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio         1040                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio           36                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          746                       # Packet count per connected master and slave (bytes)
@@ -357,14 +357,14 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total      2383090                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total      2383082                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side     30670848                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.clcd.dma::total     30670848                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                33053938                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                33053930                       # Packet count per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio        39333                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio        15892                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio         1068                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio         2084                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio        15884                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio         1064                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio         2080                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio           72                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio          397                       # Cumulative packet size per connected master and slave (bytes)
@@ -384,18 +384,18 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::total      2390546                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::total      2390530                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side    122683392                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.realview.clcd.dma::total    122683392                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::total            125073938                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.data_through_bus               125073938                       # Total data (bytes)
+system.iobus.tot_pkt_size::total            125073922                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.data_through_bus               125073922                       # Total data (bytes)
 system.iobus.reqLayer0.occupancy             21111000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy              3978000                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy              3976000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy               534000                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy               532000                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy               527000                       # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy               526000                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer4.occupancy                27000                       # Layer occupancy (ticks)
 system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
@@ -437,9 +437,9 @@ system.iobus.reqLayer23.occupancy                8000                       # La
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer25.occupancy         15335424000                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.6                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy          2374907000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy          2374900000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.1                       # Layer utilization (%)
-system.iobus.respLayer1.occupancy         38686102250                       # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy         38692913500                       # Layer occupancy (ticks)
 system.iobus.respLayer1.utilization               1.5                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
@@ -465,25 +465,25 @@ system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DT
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.read_hits                     14996190                       # DTB read hits
-system.cpu.dtb.read_misses                       7339                       # DTB read misses
-system.cpu.dtb.write_hits                    11230344                       # DTB write hits
-system.cpu.dtb.write_misses                      2214                       # DTB write misses
+system.cpu.dtb.read_hits                     13160128                       # DTB read hits
+system.cpu.dtb.read_misses                       7329                       # DTB read misses
+system.cpu.dtb.write_hits                    11227968                       # DTB write hits
+system.cpu.dtb.write_misses                      2212                       # DTB write misses
 system.cpu.dtb.flush_tlb                            2                       # Number of times complete TLB was flushed
 system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
 system.cpu.dtb.flush_tlb_mva_asid                1439                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.dtb.flush_tlb_asid                      63                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries                     3405                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.flush_entries                     3401                       # Number of entries that have been flushed from TLB
 system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults                    192                       # Number of TLB faults due to prefetch
+system.cpu.dtb.prefetch_faults                    189                       # Number of TLB faults due to prefetch
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
 system.cpu.dtb.perms_faults                       452                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses                 15003529                       # DTB read accesses
-system.cpu.dtb.write_accesses                11232558                       # DTB write accesses
+system.cpu.dtb.read_accesses                 13167457                       # DTB read accesses
+system.cpu.dtb.write_accesses                11230180                       # DTB write accesses
 system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.hits                          26226534                       # DTB hits
-system.cpu.dtb.misses                            9553                       # DTB misses
-system.cpu.dtb.accesses                      26236087                       # DTB accesses
+system.cpu.dtb.hits                          24388096                       # DTB hits
+system.cpu.dtb.misses                            9541                       # DTB misses
+system.cpu.dtb.accesses                      24397637                       # DTB accesses
 system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -505,7 +505,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.inst_hits                     61493913                       # ITB inst hits
+system.cpu.itb.inst_hits                     61480692                       # ITB inst hits
 system.cpu.itb.inst_misses                       4471                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
@@ -522,123 +522,125 @@ system.cpu.itb.domain_faults                        0                       # Nu
 system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
 system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.inst_accesses                 61498384                       # ITB inst accesses
-system.cpu.itb.hits                          61493913                       # DTB hits
+system.cpu.itb.inst_accesses                 61485163                       # ITB inst accesses
+system.cpu.itb.hits                          61480692                       # DTB hits
 system.cpu.itb.misses                            4471                       # DTB misses
-system.cpu.itb.accesses                      61498384                       # DTB accesses
-system.cpu.numCycles                       5232459694                       # number of cpu cycles simulated
+system.cpu.itb.accesses                      61485163                       # DTB accesses
+system.cpu.numCycles                       5229162505                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                    60200042                       # Number of instructions committed
-system.cpu.committedOps                      76606857                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses              69208585                       # Number of integer alu accesses
+system.cpu.committedInsts                    60186875                       # Number of instructions committed
+system.cpu.committedOps                      71883476                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses              64248071                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                  10269                       # Number of float alu accesses
-system.cpu.num_func_calls                     2140468                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts      7948679                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                     69208585                       # number of integer instructions
+system.cpu.num_func_calls                     2139776                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts      7549008                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                     64248071                       # number of integer instructions
 system.cpu.num_fp_insts                         10269                       # number of float instructions
-system.cpu.num_int_register_reads           401368270                       # number of times the integer registers were read
-system.cpu.num_int_register_writes           74518872                       # number of times the integer registers were written
+system.cpu.num_int_register_reads           116109819                       # number of times the integer registers were read
+system.cpu.num_int_register_writes           42862791                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                 7493                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                2780                       # number of times the floating registers were written
-system.cpu.num_mem_refs                      27394017                       # number of memory refs
-system.cpu.num_load_insts                    15660224                       # Number of load instructions
-system.cpu.num_store_insts                   11733793                       # Number of store instructions
-system.cpu.num_idle_cycles               4581582300.610249                       # Number of idle cycles
-system.cpu.num_busy_cycles               650877393.389751                       # Number of busy cycles
-system.cpu.not_idle_fraction                 0.124392                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                     0.875608                       # Percentage of idle cycles
-system.cpu.Branches                          10308802                       # Number of branches fetched
+system.cpu.num_cc_register_reads            257767219                       # number of times the CC registers were read
+system.cpu.num_cc_register_writes            28995131                       # number of times the CC registers were written
+system.cpu.num_mem_refs                      25244051                       # number of memory refs
+system.cpu.num_load_insts                    13512687                       # Number of load instructions
+system.cpu.num_store_insts                   11731364                       # Number of store instructions
+system.cpu.num_idle_cycles               4584182254.578246                       # Number of idle cycles
+system.cpu.num_busy_cycles               644980250.421753                       # Number of busy cycles
+system.cpu.not_idle_fraction                 0.123343                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                     0.876657                       # Percentage of idle cycles
+system.cpu.Branches                          10306559                       # Number of branches fetched
 system.cpu.op_class::No_OpClass                 28518      0.04%      0.04% # Class of executed instruction
-system.cpu.op_class::IntAlu                  50389316     64.68%     64.72% # Class of executed instruction
-system.cpu.op_class::IntMult                    87585      0.11%     64.83% # Class of executed instruction
-system.cpu.op_class::IntDiv                         0      0.00%     64.83% # Class of executed instruction
-system.cpu.op_class::FloatAdd                       0      0.00%     64.83% # Class of executed instruction
-system.cpu.op_class::FloatCmp                       0      0.00%     64.83% # Class of executed instruction
-system.cpu.op_class::FloatCvt                       0      0.00%     64.83% # Class of executed instruction
-system.cpu.op_class::FloatMult                      0      0.00%     64.83% # Class of executed instruction
-system.cpu.op_class::FloatDiv                       0      0.00%     64.83% # Class of executed instruction
-system.cpu.op_class::FloatSqrt                      0      0.00%     64.83% # Class of executed instruction
-system.cpu.op_class::SimdAdd                        0      0.00%     64.83% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc                     0      0.00%     64.83% # Class of executed instruction
-system.cpu.op_class::SimdAlu                        0      0.00%     64.83% # Class of executed instruction
-system.cpu.op_class::SimdCmp                        0      0.00%     64.83% # Class of executed instruction
-system.cpu.op_class::SimdCvt                        0      0.00%     64.83% # Class of executed instruction
-system.cpu.op_class::SimdMisc                       0      0.00%     64.83% # Class of executed instruction
-system.cpu.op_class::SimdMult                       0      0.00%     64.83% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc                    0      0.00%     64.83% # Class of executed instruction
-system.cpu.op_class::SimdShift                      0      0.00%     64.83% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc                   0      0.00%     64.83% # Class of executed instruction
-system.cpu.op_class::SimdSqrt                       0      0.00%     64.83% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd                   0      0.00%     64.83% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu                   0      0.00%     64.83% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp                   0      0.00%     64.83% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt                   0      0.00%     64.83% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv                   0      0.00%     64.83% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc               2109      0.00%     64.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult                  0      0.00%     64.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc               0      0.00%     64.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt                  0      0.00%     64.84% # Class of executed instruction
-system.cpu.op_class::MemRead                 15660224     20.10%     84.94% # Class of executed instruction
-system.cpu.op_class::MemWrite                11733793     15.06%    100.00% # Class of executed instruction
+system.cpu.op_class::IntAlu                  47576706     65.23%     65.27% # Class of executed instruction
+system.cpu.op_class::IntMult                    87551      0.12%     65.39% # Class of executed instruction
+system.cpu.op_class::IntDiv                         0      0.00%     65.39% # Class of executed instruction
+system.cpu.op_class::FloatAdd                       0      0.00%     65.39% # Class of executed instruction
+system.cpu.op_class::FloatCmp                       0      0.00%     65.39% # Class of executed instruction
+system.cpu.op_class::FloatCvt                       0      0.00%     65.39% # Class of executed instruction
+system.cpu.op_class::FloatMult                      0      0.00%     65.39% # Class of executed instruction
+system.cpu.op_class::FloatDiv                       0      0.00%     65.39% # Class of executed instruction
+system.cpu.op_class::FloatSqrt                      0      0.00%     65.39% # Class of executed instruction
+system.cpu.op_class::SimdAdd                        0      0.00%     65.39% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc                     0      0.00%     65.39% # Class of executed instruction
+system.cpu.op_class::SimdAlu                        0      0.00%     65.39% # Class of executed instruction
+system.cpu.op_class::SimdCmp                        0      0.00%     65.39% # Class of executed instruction
+system.cpu.op_class::SimdCvt                        0      0.00%     65.39% # Class of executed instruction
+system.cpu.op_class::SimdMisc                       0      0.00%     65.39% # Class of executed instruction
+system.cpu.op_class::SimdMult                       0      0.00%     65.39% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc                    0      0.00%     65.39% # Class of executed instruction
+system.cpu.op_class::SimdShift                      0      0.00%     65.39% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc                   0      0.00%     65.39% # Class of executed instruction
+system.cpu.op_class::SimdSqrt                       0      0.00%     65.39% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd                   0      0.00%     65.39% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu                   0      0.00%     65.39% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp                   0      0.00%     65.39% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt                   0      0.00%     65.39% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv                   0      0.00%     65.39% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc               2109      0.00%     65.39% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult                  0      0.00%     65.39% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc               0      0.00%     65.39% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt                  0      0.00%     65.39% # Class of executed instruction
+system.cpu.op_class::MemRead                 13512687     18.53%     83.92% # Class of executed instruction
+system.cpu.op_class::MemWrite                11731364     16.08%    100.00% # Class of executed instruction
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::total                   77901545                       # Class of executed instruction
+system.cpu.op_class::total                   72938935                       # Class of executed instruction
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.quiesce                    83017                       # number of quiesce instructions executed
-system.cpu.icache.tags.replacements            856351                       # number of replacements
-system.cpu.icache.tags.tagsinuse           510.866135                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            60637050                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs            856863                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             70.766330                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle       20005377250                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   510.866135                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.997785                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.997785                       # Average percentage of cache occupancy
+system.cpu.kern.inst.quiesce                    83001                       # number of quiesce instructions executed
+system.cpu.icache.tags.replacements            855859                       # number of replacements
+system.cpu.icache.tags.tagsinuse           510.877209                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            60624321                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs            856371                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             70.792123                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle       19627747250                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   510.877209                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.997807                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.997807                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           44                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          193                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          269                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3            6                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           45                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          194                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          266                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3            7                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          62350776                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         62350776                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     60637050                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        60637050                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      60637050                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         60637050                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     60637050                       # number of overall hits
-system.cpu.icache.overall_hits::total        60637050                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst       856863                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total        856863                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst       856863                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total         856863                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst       856863                       # number of overall misses
-system.cpu.icache.overall_misses::total        856863                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  11766560750                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  11766560750                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  11766560750                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  11766560750                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  11766560750                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  11766560750                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     61493913                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     61493913                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     61493913                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     61493913                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     61493913                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     61493913                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.013934                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.013934                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.013934                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.013934                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.013934                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.013934                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13732.137751                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13732.137751                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13732.137751                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13732.137751                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13732.137751                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13732.137751                       # average overall miss latency
+system.cpu.icache.tags.tag_accesses          62337063                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         62337063                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     60624321                       # number of ReadReq hits
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+system.cpu.icache.overall_misses::total        856371                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  11763954000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  11763954000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  11763954000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  11763954000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  11763954000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  11763954000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     61480692                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     61480692                       # number of ReadReq accesses(hits+misses)
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+system.cpu.icache.demand_accesses::total     61480692                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     61480692                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     61480692                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.013929                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.013929                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.013929                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.013929                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.013929                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.013929                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13736.983153                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13736.983153                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13736.983153                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13736.983153                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13736.983153                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13736.983153                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -647,186 +649,186 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst       856863                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total       856863                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst       856863                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total       856863                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst       856863                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total       856863                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  10048829250                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  10048829250                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst  10048829250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total  10048829250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst  10048829250                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total  10048829250                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst    441046000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::total    441046000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst    441046000                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::total    441046000                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.013934                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.013934                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.013934                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.013934                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.013934                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.013934                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11727.463142                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11727.463142                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11727.463142                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 11727.463142                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11727.463142                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 11727.463142                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst       856371                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total       856371                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst       856371                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total       856371                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst       856371                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total       856371                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  10047194000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total  10047194000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst  10047194000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total  10047194000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst  10047194000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total  10047194000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst    440846250                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_uncacheable_latency::total    440846250                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst    440846250                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_latency::total    440846250                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.013929                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.013929                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.013929                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.013929                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.013929                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.013929                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11732.291262                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11732.291262                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11732.291262                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 11732.291262                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11732.291262                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 11732.291262                       # average overall mshr miss latency
 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements            62506                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        50753.322403                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            1682121                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           127886                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            13.153285                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle     2565374310000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 37717.253716                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker     3.884318                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.000703                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  6993.225103                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  6038.958564                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.575520                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.replacements            62821                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        50750.711022                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            1678966                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           128205                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            13.095948                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle     2564782857000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 37685.579713                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker     3.884636                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.000702                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  6996.394812                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  6064.851159                       # Average occupied blocks per requestor
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-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           27                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1           22                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2163                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         6647                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        56517                       # Occupied blocks per task id
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-system.cpu.l2cache.Writeback_hits::writebacks       595396                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total       595396                       # number of Writeback hits
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+system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000642                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.012394                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.229809                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.103597                       # miss rate for overall accesses
 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker        61050                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker        75000                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70312.151432                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74379.039657                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 72266.315273                       # average ReadReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data   161.950379                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total   161.950379                       # average UpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69277.426987                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69277.426987                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70551.208231                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74798.404255                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 72597.088564                       # average ReadReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data   121.714434                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total   121.714434                       # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69464.309364                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69464.309364                       # average ReadExReq miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker        61050                       # average overall miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker        75000                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70312.151432                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69625.805029                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 69672.675429                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70551.208231                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69830.064436                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 69879.282044                       # average overall miss latency
 system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker        61050                       # average overall miss latency
 system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker        75000                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70312.151432                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69625.805029                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 69672.675429                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70551.208231                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69830.064436                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 69879.282044                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -835,92 +837,92 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        57911                       # number of writebacks
-system.cpu.l2cache.writebacks::total            57911                       # number of writebacks
+system.cpu.l2cache.writebacks::writebacks        58133                       # number of writebacks
+system.cpu.l2cache.writebacks::total            58133                       # number of writebacks
 system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker            5                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker            2                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        10579                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data         9809                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total        20395                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         2902                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total         2902                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       133833                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       133833                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        10594                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data         9870                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total        20471                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         2896                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total         2896                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       134072                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       134072                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker            5                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            2                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst        10579                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       143642                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       154228                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst        10594                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       143942                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       154543                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker            5                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            2                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst        10579                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       143642                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       154228                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst        10594                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       143942                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       154543                       # number of overall MSHR misses
 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker       242750                       # number of ReadReq MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker       125000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    611350250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data    606711500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1218429500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     29025902                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     29025902                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   7597036114                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   7597036114                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    614859500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data    614969250                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1230196500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     28966896                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     28966896                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   7636042115                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   7636042115                       # number of ReadExReq MSHR miss cycles
 system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker       242750                       # number of demand (read+write) MSHR miss cycles
 system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       125000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    611350250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   8203747614                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total   8815465614                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    614859500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   8251011365                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total   8866238615                       # number of demand (read+write) MSHR miss cycles
 system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker       242750                       # number of overall MSHR miss cycles
 system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       125000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    611350250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   8203747614                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total   8815465614                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst    349718500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166664427750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167014146250                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data  16706100672                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total  16706100672                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst    349718500                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 183370528422                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total 183720246922                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000574                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000565                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.012370                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.025840                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.016354                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.991120                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.991120                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.541332                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.541332                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000574                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000565                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.012370                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.229155                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.103210                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000574                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000565                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.012370                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.229155                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.103210                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    614859500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   8251011365                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total   8866238615                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst    349507750                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166664674250                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167014182000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data  16705839575                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total  16705839575                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst    349507750                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 183370513825                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total 183720021575                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000663                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000642                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.012394                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.026055                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.016453                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.991102                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.991102                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.541620                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.541620                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000663                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000642                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.012394                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.229809                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.103597                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000663                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000642                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.012394                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.229809                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.103597                       # mshr miss rate for overall accesses
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker        48550                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker        62500                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57789.039607                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61852.533388                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59741.578818                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10002.033770                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10002.033770                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56765.043853                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56765.043853                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58038.465169                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62306.914894                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60094.597235                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10002.381215                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10002.381215                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56954.786346                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56954.786346                       # average ReadExReq mshr miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker        48550                       # average overall mshr miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker        62500                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57789.039607                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57112.457457                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57158.658700                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58038.465169                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57321.777973                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57370.690455                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker        48550                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker        62500                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57789.039607                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57112.457457                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57158.658700                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58038.465169                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57321.777973                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57370.690455                       # average overall mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -930,143 +932,166 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements            626320                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.875633                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            23655948                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs            626832                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             37.738897                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         669376250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.875633                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.replacements            625842                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.875658                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            21786000                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            626354                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             34.782248                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle         668864250                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.875658                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.999757                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.999757                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           73                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          333                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2          105                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           77                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          319                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          116                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          97757952                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         97757952                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     13196101                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        13196101                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      9972757                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        9972757                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data       236378                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       236378                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data       247784                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total       247784                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      23168858                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         23168858                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     23168858                       # number of overall hits
-system.cpu.dcache.overall_hits::total        23168858                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       368196                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        368196                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       250157                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       250157                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data        11407                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total        11407                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data       618353                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total         618353                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data       618353                       # number of overall misses
-system.cpu.dcache.overall_misses::total        618353                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data   5410361250                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total   5410361250                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  11271639016                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  11271639016                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    158326750                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total    158326750                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  16682000266                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  16682000266                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  16682000266                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  16682000266                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     13564297                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     13564297                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data     10222914                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total     10222914                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data       247785                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total       247785                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data       247784                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total       247784                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     23787211                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     23787211                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     23787211                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     23787211                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.027144                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.027144                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.024470                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.024470                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.046036                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.046036                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.025995                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.025995                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.025995                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.025995                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14694.242333                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 14694.242333                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45058.259477                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 45058.259477                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13879.788726                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13879.788726                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 26978.118107                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 26978.118107                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 26978.118107                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 26978.118107                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.tags.tag_accesses          90403758                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         90403758                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     11249339                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        11249339                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      9965366                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        9965366                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data        84253                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total         84253                       # number of SoftPFReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data       236457                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total       236457                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data       247663                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total       247663                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data      21214705                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         21214705                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     21298958                       # number of overall hits
+system.cpu.dcache.overall_hits::total        21298958                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       294663                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        294663                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       255297                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       255297                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data       100106                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total       100106                       # number of SoftPFReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data        11207                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total        11207                       # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data       549960                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total         549960                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data       650066                       # number of overall misses
+system.cpu.dcache.overall_misses::total        650066                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data   4040384999                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total   4040384999                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  11533122261                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  11533122261                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    155182000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total    155182000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  15573507260                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  15573507260                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  15573507260                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  15573507260                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     11544002                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     11544002                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data     10220663                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total     10220663                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data       184359                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total       184359                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data       247664                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total       247664                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data       247663                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total       247663                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     21764665                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     21764665                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     21949024                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     21949024                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.025525                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.025525                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.024979                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.024979                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.542995                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.542995                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.045251                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.045251                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.025268                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.025268                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.029617                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.029617                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13711.884421                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 13711.884421                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45175.314481                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 45175.314481                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13846.881413                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13846.881413                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 28317.527202                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 28317.527202                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 23956.809401                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 23956.809401                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs           58                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 1                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs           58                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       595396                       # number of writebacks
-system.cpu.dcache.writebacks::total            595396                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       368196                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       368196                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       250157                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       250157                       # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        11407                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total        11407                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       618353                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       618353                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       618353                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       618353                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   4671668750                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   4671668750                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  10721268984                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  10721268984                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    135458250                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    135458250                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  15392937734                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  15392937734                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  15392937734                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  15392937734                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182058578250                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182058578250                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data  26242925328                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total  26242925328                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 208301503578                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total 208301503578                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.027144                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.027144                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.024470                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.024470                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.046036                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.046036                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.025995                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.025995                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.025995                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.025995                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12687.994302                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12687.994302                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42858.161011                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42858.161011                       # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11875.010958                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11875.010958                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24893.447164                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 24893.447164                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24893.447164                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 24893.447164                       # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks       594981                       # number of writebacks
+system.cpu.dcache.writebacks::total            594981                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data          534                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total          534                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data         4836                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total         4836                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data         5370                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total         5370                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data         5370                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total         5370                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       294129                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       294129                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       250461                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       250461                       # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data        73479                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total        73479                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        11207                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total        11207                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       544590                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       544590                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       618069                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       618069                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   3445567250                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   3445567250                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  10763005489                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  10763005489                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   1228271500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   1228271500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    132710000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    132710000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  14208572739                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  14208572739                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  15436844239                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  15436844239                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182058544250                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182058544250                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data  26242551425                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total  26242551425                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 208301095675                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total 208301095675                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.025479                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.025479                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.024505                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.024505                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.398565                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.398565                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.045251                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.045251                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.025022                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.025022                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.028159                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.028159                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11714.476471                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11714.476471                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42972.780149                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42972.780149                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16715.952857                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16715.952857                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11841.706077                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11841.706077                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26090.403311                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 26090.403311                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24975.923787                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 24975.923787                       # average overall mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
@@ -1074,37 +1099,37 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.throughput                52982138                       # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq        2454896                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       2454896                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteReq        763385                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteResp       763385                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback       595396                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq         2928                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp         2928                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       247229                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       247229                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1725354                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      5749970                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        12465                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side        27449                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           7515238                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     54761180                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     83637066                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        14156                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side        34872                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total      138447274                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus         138447274                       # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus       166176                       # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy     3009006000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.throughput                52981595                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq        2453579                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       2453579                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteReq        763381                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteResp       763381                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback       594981                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq         2922                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp         2922                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       247539                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       247539                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1724389                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      5748549                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        12041                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side        26252                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           7511231                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     54730908                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     83579878                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        12460                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side        30172                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total      138353418                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus         138353418                       # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus       171268                       # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy     3007873000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy    1295477750                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy    1294746250                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    2533767938                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    2533153086                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer2.occupancy       8926000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy      18731500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy      18709500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
 system.iocache.tags.replacements                    0                       # number of replacements
 system.iocache.tags.tagsinuse                       0                       # Cycle average of tags in use
@@ -1122,10 +1147,10 @@ system.iocache.avg_blocked_cycles::no_mshrs          nan                       #
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1759698189250                       # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1759698189250                       # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1759698189250                       # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1759698189250                       # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1760059764500                       # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1760059764500                       # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1760059764500                       # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1760059764500                       # number of overall MSHR uncacheable cycles
 system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average ReadReq mshr uncacheable latency
 system.iocache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average overall mshr uncacheable latency
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt
index 203fb6e65..a9cd1b1ac 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt
@@ -1,18 +1,69 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.332812                       # Number of seconds simulated
-sim_ticks                                2332811899500                       # Number of ticks simulated
-final_tick                               2332811899500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.321351                       # Number of seconds simulated
+sim_ticks                                2321351025500                       # Number of ticks simulated
+final_tick                               2321351025500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 860450                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1106481                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            33226597982                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 465868                       # Number of bytes of host memory used
-host_seconds                                    70.21                       # Real time elapsed on the host
-sim_insts                                    60411489                       # Number of instructions simulated
-sim_ops                                      77685090                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 709541                       # Simulator instruction rate (inst/s)
+host_op_rate                                   854435                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            27266672116                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 431868                       # Number of bytes of host memory used
+host_seconds                                    85.14                       # Real time elapsed on the host
+sim_insts                                    60406834                       # Number of instructions simulated
+sim_ops                                      72742429                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
+system.physmem.bytes_read::realview.clcd    110100480                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.dtb.walker          128                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker          192                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst           508168                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data          5844952                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           197248                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data          3227072                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            119878240                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       508168                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       197248                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          705416                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      3703808                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0.data       1462736                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1.data       1553080                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           6719624                       # Number of bytes written to this memory
+system.physmem.num_reads::realview.clcd      13762560                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.dtb.walker            2                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker            3                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             14152                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data             91353                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst              3082                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data             50423                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total              13921575                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           57872                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0.data           365684                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu1.data           388270                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               811826                       # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd        47429483                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.dtb.walker            55                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker            83                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst              218910                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data             2517910                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               84971                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data             1390170                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                51641582                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         218910                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          84971                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             303882                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1595540                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data             630123                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1.data             669041                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                2894704                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1595540                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd       47429483                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker           55                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker           83                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             218910                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data            3148032                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              84971                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data            2059211                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               54536286                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bytes_read::cpu0.inst           20                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total            20                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_inst_read::cpu0.inst           20                       # Number of instructions bytes read from this memory
@@ -25,218 +76,167 @@ system.realview.nvmem.bw_inst_read::cpu0.inst            9
 system.realview.nvmem.bw_inst_read::total            9                       # Instruction read bandwidth from this memory (bytes/s)
 system.realview.nvmem.bw_total::cpu0.inst            9                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::total               9                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bytes_read::realview.clcd    111673344                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.dtb.walker          128                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker          192                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst           492808                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data          6490264                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           212352                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data          2581696                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            121450784                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       492808                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       212352                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          705160                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      3703360                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0.data       1405780                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1.data       1610036                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           6719176                       # Number of bytes written to this memory
-system.physmem.num_reads::realview.clcd      13959168                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.dtb.walker            2                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker            3                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             13912                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data            101446                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              3318                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data             40339                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total              14118188                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           57865                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0.data           351445                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1.data           402509                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               811819                       # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd        47870702                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.dtb.walker            55                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker            82                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst              211251                       # Total read bandwidth from this memory (bytes/s)
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-system.physmem.bw_total::cpu0.data            3384775                       # Total bandwidth to/from this memory (bytes/s)
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-system.physmem.bw_total::total               54942261                       # Total bandwidth to/from this memory (bytes/s)
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 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
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-system.l2c.UpgradeReq_hits::cpu1.data              14                       # number of UpgradeReq hits
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 system.l2c.UpgradeReq_hits::total                  26                       # number of UpgradeReq hits
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-system.l2c.overall_miss_rate::cpu0.inst      0.015168                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.281967                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.008989                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.157360                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.103151                       # miss rate for overall accesses
+system.l2c.overall_misses::cpu0.inst             7526                       # number of overall misses
+system.l2c.overall_misses::cpu0.data            92158                       # number of overall misses
+system.l2c.overall_misses::cpu1.inst             3082                       # number of overall misses
+system.l2c.overall_misses::cpu1.data            51191                       # number of overall misses
+system.l2c.overall_misses::total               153962                       # number of overall misses
+system.l2c.ReadReq_accesses::cpu0.dtb.walker         8777                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.itb.walker         3266                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.inst         459281                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.data         195045                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.dtb.walker         5151                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.itb.walker         2105                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.inst         390120                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.data         181611                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total            1245356                       # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks       592686                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total           592686                       # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data         1521                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data         1422                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total            2943                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data       148092                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data        99093                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           247185                       # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.dtb.walker         8777                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.itb.walker         3266                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst          459281                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data          343137                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.dtb.walker         5151                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.itb.walker         2105                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst          390120                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data          280704                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total             1492541                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker         8777                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.itb.walker         3266                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst         459281                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data         343137                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.dtb.walker         5151                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.itb.walker         2105                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst         390120                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data         280704                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            1492541                       # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.000228                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000919                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.inst      0.016386                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.data      0.031244                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.inst      0.007900                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.data      0.020803                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.016449                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.989481                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.992968                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.991165                       # miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.581152                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.478470                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.539988                       # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker     0.000228                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker     0.000919                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.016386                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.268575                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.007900                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.182366                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.103154                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker     0.000228                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker     0.000919                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.016386                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.268575                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.007900                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.182366                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.103154                       # miss rate for overall accesses
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -245,8 +245,8 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks               57865                       # number of writebacks
-system.l2c.writebacks::total                    57865                       # number of writebacks
+system.l2c.writebacks::writebacks               57872                       # number of writebacks
+system.l2c.writebacks::total                    57872                       # number of writebacks
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
 system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
 system.cf0.dma_read_bytes                           0                       # Number of bytes transfered via DMA reads (not PRD).
@@ -254,11 +254,11 @@ system.cf0.dma_read_txs                             0                       # Nu
 system.cf0.dma_write_full_pages                     0                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                          0                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
-system.toL2Bus.throughput                    59119724                       # Throughput (bytes/s)
-system.toL2Bus.data_through_bus             137915195                       # Total data (bytes)
+system.toL2Bus.throughput                    59409488                       # Throughput (bytes/s)
+system.toL2Bus.data_through_bus             137910275                       # Total data (bytes)
 system.toL2Bus.snoop_data_through_bus               0                       # Total snoop data (bytes)
-system.iobus.throughput                      48895283                       # Throughput (bytes/s)
-system.iobus.data_through_bus               114063499                       # Total data (bytes)
+system.iobus.throughput                      48459111                       # Throughput (bytes/s)
+system.iobus.data_through_bus               112490607                       # Total data (bytes)
 system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -282,25 +282,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # D
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                     7929658                       # DTB read hits
-system.cpu0.dtb.read_misses                      6455                       # DTB read misses
-system.cpu0.dtb.write_hits                    6435419                       # DTB write hits
-system.cpu0.dtb.write_misses                     1929                       # DTB write misses
-system.cpu0.dtb.flush_tlb                        2334                       # Number of times complete TLB was flushed
+system.cpu0.dtb.read_hits                     6811742                       # DTB read hits
+system.cpu0.dtb.read_misses                      6183                       # DTB read misses
+system.cpu0.dtb.write_hits                    6269363                       # DTB write hits
+system.cpu0.dtb.write_misses                     2047                       # DTB write misses
+system.cpu0.dtb.flush_tlb                        2324                       # Number of times complete TLB was flushed
 system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid                753                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid                     32                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                    5575                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.flush_tlb_mva_asid                763                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid                     33                       # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries                    5527                       # Number of entries that have been flushed from TLB
 system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                   137                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.prefetch_faults                   117                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                      240                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                 7936113                       # DTB read accesses
-system.cpu0.dtb.write_accesses                6437348                       # DTB write accesses
+system.cpu0.dtb.perms_faults                      235                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses                 6817925                       # DTB read accesses
+system.cpu0.dtb.write_accesses                6271410                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                         14365077                       # DTB hits
-system.cpu0.dtb.misses                           8384                       # DTB misses
-system.cpu0.dtb.accesses                     14373461                       # DTB accesses
+system.cpu0.dtb.hits                         13081105                       # DTB hits
+system.cpu0.dtb.misses                           8230                       # DTB misses
+system.cpu0.dtb.accesses                     13089335                       # DTB accesses
 system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -322,141 +322,143 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.inst_hits                    32541992                       # ITB inst hits
-system.cpu0.itb.inst_misses                      3717                       # ITB inst misses
+system.cpu0.itb.inst_hits                    32133466                       # ITB inst hits
+system.cpu0.itb.inst_misses                      3581                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
 system.cpu0.itb.write_misses                        0                       # DTB write misses
-system.cpu0.itb.flush_tlb                        2334                       # Number of times complete TLB was flushed
+system.cpu0.itb.flush_tlb                        2324                       # Number of times complete TLB was flushed
 system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid                753                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid                     32                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                    2674                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_tlb_mva_asid                763                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid                     33                       # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries                    2662                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses                32545709                       # ITB inst accesses
-system.cpu0.itb.hits                         32541992                       # DTB hits
-system.cpu0.itb.misses                           3717                       # DTB misses
-system.cpu0.itb.accesses                     32545709                       # DTB accesses
-system.cpu0.numCycles                      4625561989                       # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses                32137047                       # ITB inst accesses
+system.cpu0.itb.hits                         32133466                       # DTB hits
+system.cpu0.itb.misses                           3581                       # DTB misses
+system.cpu0.itb.accesses                     32137047                       # DTB accesses
+system.cpu0.numCycles                      4608021079                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                   31996828                       # Number of instructions committed
-system.cpu0.committedOps                     41898003                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses             37241416                       # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses                  5364                       # Number of float alu accesses
-system.cpu0.num_func_calls                    1207166                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts      4285035                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                    37241416                       # number of integer instructions
-system.cpu0.num_fp_insts                         5364                       # number of float instructions
-system.cpu0.num_int_register_reads          192512823                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes          39713188                       # number of times the integer registers were written
-system.cpu0.num_fp_register_reads                3938                       # number of times the floating registers were read
-system.cpu0.num_fp_register_writes               1428                       # number of times the floating registers were written
-system.cpu0.num_mem_refs                     15011832                       # number of memory refs
-system.cpu0.num_load_insts                    8305325                       # Number of load instructions
-system.cpu0.num_store_insts                   6706507                       # Number of store instructions
-system.cpu0.num_idle_cycles              4549718927.235470                       # Number of idle cycles
-system.cpu0.num_busy_cycles              75843061.764530                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.016397                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.983603                       # Percentage of idle cycles
-system.cpu0.Branches                          5613326                       # Number of branches fetched
-system.cpu0.op_class::No_OpClass                16463      0.04%      0.04% # Class of executed instruction
-system.cpu0.op_class::IntAlu                 26898614     64.08%     64.12% # Class of executed instruction
-system.cpu0.op_class::IntMult                   45874      0.11%     64.23% # Class of executed instruction
-system.cpu0.op_class::IntDiv                        0      0.00%     64.23% # Class of executed instruction
-system.cpu0.op_class::FloatAdd                      0      0.00%     64.23% # Class of executed instruction
-system.cpu0.op_class::FloatCmp                      0      0.00%     64.23% # Class of executed instruction
-system.cpu0.op_class::FloatCvt                      0      0.00%     64.23% # Class of executed instruction
-system.cpu0.op_class::FloatMult                     0      0.00%     64.23% # Class of executed instruction
-system.cpu0.op_class::FloatDiv                      0      0.00%     64.23% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt                     0      0.00%     64.23% # Class of executed instruction
-system.cpu0.op_class::SimdAdd                       0      0.00%     64.23% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc                    0      0.00%     64.23% # Class of executed instruction
-system.cpu0.op_class::SimdAlu                       0      0.00%     64.23% # Class of executed instruction
-system.cpu0.op_class::SimdCmp                       0      0.00%     64.23% # Class of executed instruction
-system.cpu0.op_class::SimdCvt                       0      0.00%     64.23% # Class of executed instruction
-system.cpu0.op_class::SimdMisc                      0      0.00%     64.23% # Class of executed instruction
-system.cpu0.op_class::SimdMult                      0      0.00%     64.23% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc                   0      0.00%     64.23% # Class of executed instruction
-system.cpu0.op_class::SimdShift                     0      0.00%     64.23% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc                  0      0.00%     64.23% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt                      0      0.00%     64.23% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd                  0      0.00%     64.23% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu                  0      0.00%     64.23% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp                  0      0.00%     64.23% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt                  0      0.00%     64.23% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv                  0      0.00%     64.23% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc              1340      0.00%     64.24% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult                 0      0.00%     64.24% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     64.24% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     64.24% # Class of executed instruction
-system.cpu0.op_class::MemRead                 8305325     19.79%     84.02% # Class of executed instruction
-system.cpu0.op_class::MemWrite                6706507     15.98%    100.00% # Class of executed instruction
+system.cpu0.committedInsts                   31639227                       # Number of instructions committed
+system.cpu0.committedOps                     38587883                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses             34004805                       # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses                  5482                       # Number of float alu accesses
+system.cpu0.num_func_calls                    1192523                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts      4010781                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                    34004805                       # number of integer instructions
+system.cpu0.num_fp_insts                         5482                       # number of float instructions
+system.cpu0.num_int_register_reads           62290177                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes          22551825                       # number of times the integer registers were written
+system.cpu0.num_fp_register_reads                3925                       # number of times the floating registers were read
+system.cpu0.num_fp_register_writes               1558                       # number of times the floating registers were written
+system.cpu0.num_cc_register_reads           115496065                       # number of times the CC registers were read
+system.cpu0.num_cc_register_writes           15262729                       # number of times the CC registers were written
+system.cpu0.num_mem_refs                     13528824                       # number of memory refs
+system.cpu0.num_load_insts                    6988108                       # Number of load instructions
+system.cpu0.num_store_insts                   6540716                       # Number of store instructions
+system.cpu0.num_idle_cycles              4534732444.570566                       # Number of idle cycles
+system.cpu0.num_busy_cycles              73288634.429434                       # Number of busy cycles
+system.cpu0.not_idle_fraction                0.015905                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                    0.984095                       # Percentage of idle cycles
+system.cpu0.Branches                          5541899                       # Number of branches fetched
+system.cpu0.op_class::No_OpClass                16090      0.04%      0.04% # Class of executed instruction
+system.cpu0.op_class::IntAlu                 25070156     64.84%     64.89% # Class of executed instruction
+system.cpu0.op_class::IntMult                   45827      0.12%     65.00% # Class of executed instruction
+system.cpu0.op_class::IntDiv                        0      0.00%     65.00% # Class of executed instruction
+system.cpu0.op_class::FloatAdd                      0      0.00%     65.00% # Class of executed instruction
+system.cpu0.op_class::FloatCmp                      0      0.00%     65.00% # Class of executed instruction
+system.cpu0.op_class::FloatCvt                      0      0.00%     65.00% # Class of executed instruction
+system.cpu0.op_class::FloatMult                     0      0.00%     65.00% # Class of executed instruction
+system.cpu0.op_class::FloatDiv                      0      0.00%     65.00% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt                     0      0.00%     65.00% # Class of executed instruction
+system.cpu0.op_class::SimdAdd                       0      0.00%     65.00% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc                    0      0.00%     65.00% # Class of executed instruction
+system.cpu0.op_class::SimdAlu                       0      0.00%     65.00% # Class of executed instruction
+system.cpu0.op_class::SimdCmp                       0      0.00%     65.00% # Class of executed instruction
+system.cpu0.op_class::SimdCvt                       0      0.00%     65.00% # Class of executed instruction
+system.cpu0.op_class::SimdMisc                      0      0.00%     65.00% # Class of executed instruction
+system.cpu0.op_class::SimdMult                      0      0.00%     65.00% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc                   0      0.00%     65.00% # Class of executed instruction
+system.cpu0.op_class::SimdShift                     0      0.00%     65.00% # Class of executed instruction
+system.cpu0.op_class::SimdShiftAcc                  0      0.00%     65.00% # Class of executed instruction
+system.cpu0.op_class::SimdSqrt                      0      0.00%     65.00% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAdd                  0      0.00%     65.00% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAlu                  0      0.00%     65.00% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCmp                  0      0.00%     65.00% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCvt                  0      0.00%     65.00% # Class of executed instruction
+system.cpu0.op_class::SimdFloatDiv                  0      0.00%     65.00% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc              1368      0.00%     65.01% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMult                 0      0.00%     65.01% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     65.01% # Class of executed instruction
+system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     65.01% # Class of executed instruction
+system.cpu0.op_class::MemRead                 6988108     18.07%     83.08% # Class of executed instruction
+system.cpu0.op_class::MemWrite                6540716     16.92%    100.00% # Class of executed instruction
 system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu0.op_class::total                  41974123                       # Class of executed instruction
+system.cpu0.op_class::total                  38662265                       # Class of executed instruction
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                   82795                       # number of quiesce instructions executed
-system.cpu0.icache.tags.replacements           850590                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.678462                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs           60586338                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs           851102                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            71.185754                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle       5711018500                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   444.500524                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu1.inst    67.177938                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.868165                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu1.inst     0.131207                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.999372                       # Average percentage of cache occupancy
+system.cpu0.kern.inst.quiesce                   82781                       # number of quiesce instructions executed
+system.cpu0.icache.tags.replacements           850515                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.689593                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs           60581740                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs           851027                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            71.186625                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle       5455017500                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   446.344221                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu1.inst    65.345372                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.871766                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu1.inst     0.127628                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.999394                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0          177                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1           78                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2          255                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0          200                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1           62                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2          249                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses         62288542                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses        62288542                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst     32063555                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu1.inst     28522783                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total       60586338                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst     32063555                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu1.inst     28522783                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total        60586338                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst     32063555                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu1.inst     28522783                       # number of overall hits
-system.cpu0.icache.overall_hits::total       60586338                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst       481227                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu1.inst       369875                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total       851102                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst       481227                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu1.inst       369875                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total        851102                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst       481227                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu1.inst       369875                       # number of overall misses
-system.cpu0.icache.overall_misses::total       851102                       # number of overall misses
-system.cpu0.icache.ReadReq_accesses::cpu0.inst     32544782                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu1.inst     28892658                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total     61437440                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst     32544782                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu1.inst     28892658                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total     61437440                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst     32544782                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu1.inst     28892658                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total     61437440                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.014787                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.012802                       # miss rate for ReadReq accesses
+system.cpu0.icache.tags.tag_accesses         62283794                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses        62283794                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst     31676072                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu1.inst     28905668                       # number of ReadReq hits
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+system.cpu0.icache.demand_hits::total        60581740                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst     31676072                       # number of overall hits
+system.cpu0.icache.overall_hits::cpu1.inst     28905668                       # number of overall hits
+system.cpu0.icache.overall_hits::total       60581740                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst       460107                       # number of ReadReq misses
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+system.cpu0.icache.demand_misses::cpu1.inst       390920                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total        851027                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst       460107                       # number of overall misses
+system.cpu0.icache.overall_misses::cpu1.inst       390920                       # number of overall misses
+system.cpu0.icache.overall_misses::total       851027                       # number of overall misses
+system.cpu0.icache.ReadReq_accesses::cpu0.inst     32136179                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu1.inst     29296588                       # number of ReadReq accesses(hits+misses)
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+system.cpu0.icache.demand_accesses::cpu1.inst     29296588                       # number of demand (read+write) accesses
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+system.cpu0.icache.overall_accesses::cpu0.inst     32136179                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu1.inst     29296588                       # number of overall (read+write) accesses
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+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.014317                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.013344                       # miss rate for ReadReq accesses
 system.cpu0.icache.ReadReq_miss_rate::total     0.013853                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.014787                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu1.inst     0.012802                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.014317                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu1.inst     0.013344                       # miss rate for demand accesses
 system.cpu0.icache.demand_miss_rate::total     0.013853                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.014787                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu1.inst     0.012802                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.014317                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu1.inst     0.013344                       # miss rate for overall accesses
 system.cpu0.icache.overall_miss_rate::total     0.013853                       # miss rate for overall accesses
 system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
@@ -467,90 +469,102 @@ system.cpu0.icache.avg_blocked_cycles::no_targets          nan
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.dcache.tags.replacements           623343                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          511.997030                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           23628961                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs           623855                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            37.875726                       # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle         21768000                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   451.291422                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu1.data    60.705608                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.881429                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu1.data     0.118566                       # Average percentage of cache occupancy
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+system.cpu0.dcache.tags.tagsinuse          511.997018                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs           21798515                       # Total number of references to valid blocks.
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+system.cpu0.dcache.tags.warmup_cycle         21757000                       # Cycle when the warmup percentage was hit.
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+system.cpu0.dcache.tags.occ_blocks::cpu1.data    58.022582                       # Average occupied blocks per requestor
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 system.cpu0.dcache.tags.occ_percent::total     0.999994                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0          278                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          208                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           26                       # Occupied blocks per task id
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 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
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-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       139339                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu1.data        96699                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       236038                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       145986                       # number of StoreCondReq hits
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-system.cpu0.dcache.StoreCondReq_hits::total       247221                       # number of StoreCondReq hits
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-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.027270                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.026650                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.026979                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.027172                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.020780                       # miss rate for WriteReq accesses
+system.cpu0.dcache.tags.tag_accesses         90313265                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses        90313265                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data      5835707                       # number of ReadReq hits
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+system.cpu0.dcache.SoftPFReq_hits::cpu0.data        52098                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu1.data        58749                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::total       110847                       # number of SoftPFReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       136238                       # number of LoadLockedReq hits
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+system.cpu0.dcache.ReadReq_misses::cpu0.data       155593                       # number of ReadReq misses
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+system.cpu0.dcache.ReadReq_misses::total       292045                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data       149613                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu1.data       100515                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total       250128                       # number of WriteReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu0.data        32922                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu1.data        40499                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::total        73421                       # number of SoftPFReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         6530                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu1.data         4660                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total        11190                       # number of LoadLockedReq misses
+system.cpu0.dcache.demand_misses::cpu0.data       305206                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu1.data       236967                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total        542173                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data       338128                       # number of overall misses
+system.cpu0.dcache.overall_misses::cpu1.data       277466                       # number of overall misses
+system.cpu0.dcache.overall_misses::total       615594                       # number of overall misses
+system.cpu0.dcache.ReadReq_accesses::cpu0.data      5991300                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu1.data      5540956                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total     11532256                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data      5759891                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu1.data      4451548                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total     10211439                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu0.data        85020                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu1.data        99248                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total       184268                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       142768                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data       104429                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       247197                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       142767                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu1.data       104429                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       247196                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data     11751191                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu1.data      9992504                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     21743695                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data     11836211                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu1.data     10091752                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     21927963                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.025970                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.024626                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.025324                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.025975                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.022580                       # miss rate for WriteReq accesses
 system.cpu0.dcache.WriteReq_miss_rate::total     0.024495                       # miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.045538                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.044807                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.045239                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.027225                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu1.data     0.024289                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.025912                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.027225                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu1.data     0.024289                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.025912                       # miss rate for overall accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.387227                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.408059                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.398447                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.045739                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.044624                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.045268                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.025972                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu1.data     0.023714                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.024935                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.028567                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu1.data     0.027494                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.028073                       # miss rate for overall accesses
 system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -559,8 +573,8 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       592692                       # number of writebacks
-system.cpu0.dcache.writebacks::total           592692                       # number of writebacks
+system.cpu0.dcache.writebacks::writebacks       592686                       # number of writebacks
+system.cpu0.dcache.writebacks::total           592686                       # number of writebacks
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
@@ -585,25 +599,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # D
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                     7038699                       # DTB read hits
-system.cpu1.dtb.read_misses                      4194                       # DTB read misses
-system.cpu1.dtb.write_hits                    4780763                       # DTB write hits
-system.cpu1.dtb.write_misses                     1254                       # DTB write misses
-system.cpu1.dtb.flush_tlb                        2332                       # Number of times complete TLB was flushed
+system.cpu1.dtb.read_hits                     6327054                       # DTB read hits
+system.cpu1.dtb.read_misses                      4532                       # DTB read misses
+system.cpu1.dtb.write_hits                    4945852                       # DTB write hits
+system.cpu1.dtb.write_misses                     1126                       # DTB write misses
+system.cpu1.dtb.flush_tlb                        2320                       # Number of times complete TLB was flushed
 system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid                686                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid                     31                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                    2928                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.flush_tlb_mva_asid                676                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid                     30                       # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries                    3028                       # Number of entries that have been flushed from TLB
 system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                    88                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.prefetch_faults                    87                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                      212                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                 7042893                       # DTB read accesses
-system.cpu1.dtb.write_accesses                4782017                       # DTB write accesses
+system.cpu1.dtb.perms_faults                      217                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses                 6331586                       # DTB read accesses
+system.cpu1.dtb.write_accesses                4946978                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                         11819462                       # DTB hits
-system.cpu1.dtb.misses                           5448                       # DTB misses
-system.cpu1.dtb.accesses                     11824910                       # DTB accesses
+system.cpu1.dtb.hits                         11272906                       # DTB hits
+system.cpu1.dtb.misses                           5658                       # DTB misses
+system.cpu1.dtb.accesses                     11278564                       # DTB accesses
 system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -625,85 +639,87 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.inst_hits                    28890998                       # ITB inst hits
-system.cpu1.itb.inst_misses                      2444                       # ITB inst misses
+system.cpu1.itb.inst_hits                    29294834                       # ITB inst hits
+system.cpu1.itb.inst_misses                      2597                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
 system.cpu1.itb.write_misses                        0                       # DTB write misses
-system.cpu1.itb.flush_tlb                        2332                       # Number of times complete TLB was flushed
+system.cpu1.itb.flush_tlb                        2320                       # Number of times complete TLB was flushed
 system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid                686                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid                     31                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                    1642                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_tlb_mva_asid                676                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid                     30                       # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries                    1660                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses                28893442                       # ITB inst accesses
-system.cpu1.itb.hits                         28890998                       # DTB hits
-system.cpu1.itb.misses                           2444                       # DTB misses
-system.cpu1.itb.accesses                     28893442                       # DTB accesses
-system.cpu1.numCycles                      4282034895                       # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses                29297431                       # ITB inst accesses
+system.cpu1.itb.hits                         29294834                       # DTB hits
+system.cpu1.itb.misses                           2597                       # DTB misses
+system.cpu1.itb.accesses                     29297431                       # DTB accesses
+system.cpu1.numCycles                       141054432                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                   28414661                       # Number of instructions committed
-system.cpu1.committedOps                     35787087                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses             31892138                       # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses                  4905                       # Number of float alu accesses
-system.cpu1.num_func_calls                     928912                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts      3657531                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                    31892138                       # number of integer instructions
-system.cpu1.num_fp_insts                         4905                       # number of float instructions
-system.cpu1.num_int_register_reads          163397724                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes          34729085                       # number of times the integer registers were written
-system.cpu1.num_fp_register_reads                3555                       # number of times the floating registers were read
-system.cpu1.num_fp_register_writes               1352                       # number of times the floating registers were written
-system.cpu1.num_mem_refs                     12350589                       # number of memory refs
-system.cpu1.num_load_insts                    7334763                       # Number of load instructions
-system.cpu1.num_store_insts                   5015826                       # Number of store instructions
-system.cpu1.num_idle_cycles              4212351630.069436                       # Number of idle cycles
-system.cpu1.num_busy_cycles              69683264.930565                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.016273                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.983727                       # Percentage of idle cycles
-system.cpu1.Branches                          4685935                       # Number of branches fetched
-system.cpu1.op_class::No_OpClass                12055      0.03%      0.03% # Class of executed instruction
-system.cpu1.op_class::IntAlu                 23438937     65.39%     65.42% # Class of executed instruction
-system.cpu1.op_class::IntMult                   41906      0.12%     65.54% # Class of executed instruction
-system.cpu1.op_class::IntDiv                        0      0.00%     65.54% # Class of executed instruction
-system.cpu1.op_class::FloatAdd                      0      0.00%     65.54% # Class of executed instruction
-system.cpu1.op_class::FloatCmp                      0      0.00%     65.54% # Class of executed instruction
-system.cpu1.op_class::FloatCvt                      0      0.00%     65.54% # Class of executed instruction
-system.cpu1.op_class::FloatMult                     0      0.00%     65.54% # Class of executed instruction
-system.cpu1.op_class::FloatDiv                      0      0.00%     65.54% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt                     0      0.00%     65.54% # Class of executed instruction
-system.cpu1.op_class::SimdAdd                       0      0.00%     65.54% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc                    0      0.00%     65.54% # Class of executed instruction
-system.cpu1.op_class::SimdAlu                       0      0.00%     65.54% # Class of executed instruction
-system.cpu1.op_class::SimdCmp                       0      0.00%     65.54% # Class of executed instruction
-system.cpu1.op_class::SimdCvt                       0      0.00%     65.54% # Class of executed instruction
-system.cpu1.op_class::SimdMisc                      0      0.00%     65.54% # Class of executed instruction
-system.cpu1.op_class::SimdMult                      0      0.00%     65.54% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc                   0      0.00%     65.54% # Class of executed instruction
-system.cpu1.op_class::SimdShift                     0      0.00%     65.54% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc                  0      0.00%     65.54% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt                      0      0.00%     65.54% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd                  0      0.00%     65.54% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu                  0      0.00%     65.54% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp                  0      0.00%     65.54% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt                  0      0.00%     65.54% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv                  0      0.00%     65.54% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc               777      0.00%     65.54% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult                 0      0.00%     65.54% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     65.54% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     65.54% # Class of executed instruction
-system.cpu1.op_class::MemRead                 7334763     20.46%     86.01% # Class of executed instruction
-system.cpu1.op_class::MemWrite                5015826     13.99%    100.00% # Class of executed instruction
+system.cpu1.committedInsts                   28767607                       # Number of instructions committed
+system.cpu1.committedOps                     34154546                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses             30186625                       # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses                  4787                       # Number of float alu accesses
+system.cpu1.num_func_calls                     943239                       # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts      3534203                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                    30186625                       # number of integer instructions
+system.cpu1.num_fp_insts                         4787                       # number of float instructions
+system.cpu1.num_int_register_reads           54137170                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes          20266282                       # number of times the integer registers were written
+system.cpu1.num_fp_register_reads                3568                       # number of times the floating registers were read
+system.cpu1.num_fp_register_writes               1222                       # number of times the floating registers were written
+system.cpu1.num_cc_register_reads           102073939                       # number of times the CC registers were read
+system.cpu1.num_cc_register_writes           13715012                       # number of times the CC registers were written
+system.cpu1.num_mem_refs                     11692450                       # number of memory refs
+system.cpu1.num_load_insts                    6511829                       # Number of load instructions
+system.cpu1.num_store_insts                   5180621                       # Number of store instructions
+system.cpu1.num_idle_cycles              138966556.858503                       # Number of idle cycles
+system.cpu1.num_busy_cycles              2087875.141497                       # Number of busy cycles
+system.cpu1.not_idle_fraction                0.014802                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                    0.985198                       # Percentage of idle cycles
+system.cpu1.Branches                          4756618                       # Number of branches fetched
+system.cpu1.op_class::No_OpClass                12428      0.04%      0.04% # Class of executed instruction
+system.cpu1.op_class::IntAlu                 22465876     65.66%     65.70% # Class of executed instruction
+system.cpu1.op_class::IntMult                   41944      0.12%     65.82% # Class of executed instruction
+system.cpu1.op_class::IntDiv                        0      0.00%     65.82% # Class of executed instruction
+system.cpu1.op_class::FloatAdd                      0      0.00%     65.82% # Class of executed instruction
+system.cpu1.op_class::FloatCmp                      0      0.00%     65.82% # Class of executed instruction
+system.cpu1.op_class::FloatCvt                      0      0.00%     65.82% # Class of executed instruction
+system.cpu1.op_class::FloatMult                     0      0.00%     65.82% # Class of executed instruction
+system.cpu1.op_class::FloatDiv                      0      0.00%     65.82% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt                     0      0.00%     65.82% # Class of executed instruction
+system.cpu1.op_class::SimdAdd                       0      0.00%     65.82% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc                    0      0.00%     65.82% # Class of executed instruction
+system.cpu1.op_class::SimdAlu                       0      0.00%     65.82% # Class of executed instruction
+system.cpu1.op_class::SimdCmp                       0      0.00%     65.82% # Class of executed instruction
+system.cpu1.op_class::SimdCvt                       0      0.00%     65.82% # Class of executed instruction
+system.cpu1.op_class::SimdMisc                      0      0.00%     65.82% # Class of executed instruction
+system.cpu1.op_class::SimdMult                      0      0.00%     65.82% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc                   0      0.00%     65.82% # Class of executed instruction
+system.cpu1.op_class::SimdShift                     0      0.00%     65.82% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc                  0      0.00%     65.82% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt                      0      0.00%     65.82% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd                  0      0.00%     65.82% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu                  0      0.00%     65.82% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp                  0      0.00%     65.82% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt                  0      0.00%     65.82% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv                  0      0.00%     65.82% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc               745      0.00%     65.82% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult                 0      0.00%     65.82% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     65.82% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     65.82% # Class of executed instruction
+system.cpu1.op_class::MemRead                 6511829     19.03%     84.86% # Class of executed instruction
+system.cpu1.op_class::MemWrite                5180621     15.14%    100.00% # Class of executed instruction
 system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu1.op_class::total                  35844264                       # Class of executed instruction
+system.cpu1.op_class::total                  34213443                       # Class of executed instruction
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
 system.iocache.tags.replacements                    0                       # number of replacements
diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt
index 07ebe167c..b0c415fa9 100644
--- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt
@@ -1,63 +1,66 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  5.112126                       # Number of seconds simulated
-sim_ticks                                5112126264500                       # Number of ticks simulated
-final_tick                               5112126264500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                5112125984500                       # Number of ticks simulated
+final_tick                               5112125984500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1285356                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2631685                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            32866027497                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 626676                       # Number of bytes of host memory used
-host_seconds                                   155.54                       # Real time elapsed on the host
-sim_insts                                   199929810                       # Number of instructions simulated
-sim_ops                                     409343850                       # Number of ops (including micro ops) simulated
+host_inst_rate                                1274105                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2608650                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            32578287771                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 593532                       # Number of bytes of host memory used
+host_seconds                                   156.92                       # Real time elapsed on the host
+sim_insts                                   199930130                       # Number of instructions simulated
+sim_ops                                     409344539                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::pc.south_bridge.ide      2421184                       # Number of bytes read from this memory
+system.physmem.bytes_read::pc.south_bridge.ide        28352                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.dtb.walker           64                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.itb.walker          320                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst            852736                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          10609344                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             13883648                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       852736                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          852736                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      9268672                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           9268672                       # Number of bytes written to this memory
-system.physmem.num_reads::pc.south_bridge.ide        37831                       # Number of read requests responded to by this memory
+system.physmem.bytes_read::cpu.inst            852800                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          10650880                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             11532416                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       852800                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          852800                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      6281856                       # Number of bytes written to this memory
+system.physmem.bytes_written::pc.south_bridge.ide      2990080                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           9271936                       # Number of bytes written to this memory
+system.physmem.num_reads::pc.south_bridge.ide          443                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.dtb.walker            1                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.itb.walker            5                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst              13324                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             165771                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                216932                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          144823                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               144823                       # Number of write requests responded to by this memory
-system.physmem.bw_read::pc.south_bridge.ide       473616                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_reads::cpu.inst              13325                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             166420                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                180194                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           98154                       # Number of write requests responded to by this memory
+system.physmem.num_writes::pc.south_bridge.ide        46720                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               144874                       # Number of write requests responded to by this memory
+system.physmem.bw_read::pc.south_bridge.ide         5546                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu.dtb.walker             13                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu.itb.walker             63                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               166807                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              2075329                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 2715827                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          166807                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             166807                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1813076                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1813076                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1813076                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::pc.south_bridge.ide       473616                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               166819                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              2083454                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 2255894                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          166819                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             166819                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1228815                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::pc.south_bridge.ide       584900                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                1813714                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1228815                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::pc.south_bridge.ide       590446                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.dtb.walker            13                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.itb.walker            63                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              166807                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             2075329                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                4528902                       # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput                      9634332                       # Throughput (bytes/s)
-system.membus.data_through_bus               49251923                       # Total data (bytes)
+system.physmem.bw_total::cpu.inst              166819                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             2083454                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                4069609                       # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput                      9050072                       # Throughput (bytes/s)
+system.membus.data_through_bus               46265107                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
 system.iocache.tags.replacements                47569                       # number of replacements
-system.iocache.tags.tagsinuse                0.042448                       # Cycle average of tags in use
+system.iocache.tags.tagsinuse                0.042447                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs                47585                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
 system.iocache.tags.warmup_cycle         4994846763009                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::pc.south_bridge.ide     0.042448                       # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::pc.south_bridge.ide     0.042447                       # Average occupied blocks per requestor
 system.iocache.tags.occ_percent::pc.south_bridge.ide     0.002653                       # Average percentage of cache occupancy
 system.iocache.tags.occ_percent::total       0.002653                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
@@ -65,26 +68,24 @@ system.iocache.tags.age_task_id_blocks_1023::2           16
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
 system.iocache.tags.tag_accesses               428616                       # Number of tag accesses
 system.iocache.tags.data_accesses              428616                       # Number of data accesses
+system.iocache.WriteInvalidateReq_hits::pc.south_bridge.ide        46720                       # number of WriteInvalidateReq hits
+system.iocache.WriteInvalidateReq_hits::total        46720                       # number of WriteInvalidateReq hits
 system.iocache.ReadReq_misses::pc.south_bridge.ide          904                       # number of ReadReq misses
 system.iocache.ReadReq_misses::total              904                       # number of ReadReq misses
-system.iocache.WriteReq_misses::pc.south_bridge.ide        46720                       # number of WriteReq misses
-system.iocache.WriteReq_misses::total           46720                       # number of WriteReq misses
-system.iocache.demand_misses::pc.south_bridge.ide        47624                       # number of demand (read+write) misses
-system.iocache.demand_misses::total             47624                       # number of demand (read+write) misses
-system.iocache.overall_misses::pc.south_bridge.ide        47624                       # number of overall misses
-system.iocache.overall_misses::total            47624                       # number of overall misses
+system.iocache.demand_misses::pc.south_bridge.ide          904                       # number of demand (read+write) misses
+system.iocache.demand_misses::total               904                       # number of demand (read+write) misses
+system.iocache.overall_misses::pc.south_bridge.ide          904                       # number of overall misses
+system.iocache.overall_misses::total              904                       # number of overall misses
 system.iocache.ReadReq_accesses::pc.south_bridge.ide          904                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            904                       # number of ReadReq accesses(hits+misses)
-system.iocache.WriteReq_accesses::pc.south_bridge.ide        46720                       # number of WriteReq accesses(hits+misses)
-system.iocache.WriteReq_accesses::total         46720                       # number of WriteReq accesses(hits+misses)
-system.iocache.demand_accesses::pc.south_bridge.ide        47624                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total           47624                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::pc.south_bridge.ide        47624                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total          47624                       # number of overall (read+write) accesses
+system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide        46720                       # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::total        46720                       # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.demand_accesses::pc.south_bridge.ide          904                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total             904                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::pc.south_bridge.ide          904                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total            904                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
-system.iocache.WriteReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for WriteReq accesses
-system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
 system.iocache.demand_miss_rate::pc.south_bridge.ide            1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::pc.south_bridge.ide            1                       # miss rate for overall accesses
@@ -95,10 +96,8 @@ system.iocache.blocked::no_mshrs                    0                       # nu
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
 system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.fast_writes                          0                       # number of fast writes performed
+system.iocache.fast_writes                      46720                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.writebacks::writebacks           46667                       # number of writebacks
-system.iocache.writebacks::total                46667                       # number of writebacks
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
 system.pc.south_bridge.ide.disks0.dma_read_bytes        34816                       # Number of bytes transfered via DMA reads (not PRD).
@@ -116,34 +115,34 @@ system.iobus.throughput                       2555207                       # Th
 system.iobus.data_through_bus                13062542                       # Total data (bytes)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
-system.cpu.numCycles                      10224253904                       # number of cpu cycles simulated
+system.cpu.numCycles                      10224253344                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                   199929810                       # Number of instructions committed
-system.cpu.committedOps                     409343850                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses             374364636                       # Number of integer alu accesses
+system.cpu.committedInsts                   199930130                       # Number of instructions committed
+system.cpu.committedOps                     409344539                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses             374365317                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                      0                       # Number of float alu accesses
-system.cpu.num_func_calls                     2307717                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts     39976328                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                    374364636                       # number of integer instructions
+system.cpu.num_func_calls                     2307745                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts     39976374                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                    374365317                       # number of integer instructions
 system.cpu.num_fp_insts                             0                       # number of float instructions
-system.cpu.num_int_register_reads           682285475                       # number of times the integer registers were read
-system.cpu.num_int_register_writes          323369236                       # number of times the integer registers were written
+system.cpu.num_int_register_reads           682286798                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          323369753                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                    0                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
-system.cpu.num_cc_register_reads            233715040                       # number of times the CC registers were read
-system.cpu.num_cc_register_writes           157233555                       # number of times the CC registers were written
-system.cpu.num_mem_refs                      35660913                       # number of memory refs
-system.cpu.num_load_insts                    27238816                       # Number of load instructions
-system.cpu.num_store_insts                    8422097                       # Number of store instructions
-system.cpu.num_idle_cycles               9770518213.691833                       # Number of idle cycles
-system.cpu.num_busy_cycles               453735690.308166                       # Number of busy cycles
+system.cpu.num_cc_register_reads            233715334                       # number of times the CC registers were read
+system.cpu.num_cc_register_writes           157233726                       # number of times the CC registers were written
+system.cpu.num_mem_refs                      35661072                       # number of memory refs
+system.cpu.num_load_insts                    27238907                       # Number of load instructions
+system.cpu.num_store_insts                    8422165                       # Number of store instructions
+system.cpu.num_idle_cycles               9770516870.697727                       # Number of idle cycles
+system.cpu.num_busy_cycles               453736473.302274                       # Number of busy cycles
 system.cpu.not_idle_fraction                 0.044378                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                     0.955622                       # Percentage of idle cycles
-system.cpu.Branches                          43125514                       # Number of branches fetched
-system.cpu.op_class::No_OpClass                175310      0.04%      0.04% # Class of executed instruction
-system.cpu.op_class::IntAlu                 373241321     91.18%     91.22% # Class of executed instruction
-system.cpu.op_class::IntMult                   144368      0.04%     91.26% # Class of executed instruction
+system.cpu.Branches                          43125613                       # Number of branches fetched
+system.cpu.op_class::No_OpClass                175318      0.04%      0.04% # Class of executed instruction
+system.cpu.op_class::IntAlu                 373241846     91.18%     91.22% # Class of executed instruction
+system.cpu.op_class::IntMult                   144365      0.04%     91.26% # Class of executed instruction
 system.cpu.op_class::IntDiv                    122968      0.03%     91.29% # Class of executed instruction
 system.cpu.op_class::FloatAdd                       0      0.00%     91.29% # Class of executed instruction
 system.cpu.op_class::FloatCmp                       0      0.00%     91.29% # Class of executed instruction
@@ -171,18 +170,18 @@ system.cpu.op_class::SimdFloatMisc                  0      0.00%     91.29% # Cl
 system.cpu.op_class::SimdFloatMult                  0      0.00%     91.29% # Class of executed instruction
 system.cpu.op_class::SimdFloatMultAcc               0      0.00%     91.29% # Class of executed instruction
 system.cpu.op_class::SimdFloatSqrt                  0      0.00%     91.29% # Class of executed instruction
-system.cpu.op_class::MemRead                 27238816      6.65%     97.94% # Class of executed instruction
-system.cpu.op_class::MemWrite                 8422097      2.06%    100.00% # Class of executed instruction
+system.cpu.op_class::MemRead                 27238907      6.65%     97.94% # Class of executed instruction
+system.cpu.op_class::MemWrite                 8422165      2.06%    100.00% # Class of executed instruction
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::total                  409344880                       # Class of executed instruction
+system.cpu.op_class::total                  409345569                       # Class of executed instruction
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
 system.cpu.kern.inst.quiesce                        0                       # number of quiesce instructions executed
-system.cpu.icache.tags.replacements            790558                       # number of replacements
+system.cpu.icache.tags.replacements            790679                       # number of replacements
 system.cpu.icache.tags.tagsinuse           510.665021                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           243525778                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs            791070                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs            307.843526                       # Average number of references to valid blocks.
+system.cpu.icache.tags.total_refs           243526070                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs            791191                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs            307.796815                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle      148848615500                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.tags.occ_blocks::cpu.inst   510.665021                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.997393                       # Average percentage of cache occupancy
@@ -192,26 +191,26 @@ system.cpu.icache.tags.age_task_id_blocks_1024::0           87
 system.cpu.icache.tags.age_task_id_blocks_1024::1          134                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::2          291                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         245107932                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        245107932                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    243525778                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       243525778                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     243525778                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        243525778                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    243525778                       # number of overall hits
-system.cpu.icache.overall_hits::total       243525778                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst       791077                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total        791077                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst       791077                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total         791077                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst       791077                       # number of overall misses
-system.cpu.icache.overall_misses::total        791077                       # number of overall misses
-system.cpu.icache.ReadReq_accesses::cpu.inst    244316855                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    244316855                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    244316855                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    244316855                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    244316855                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    244316855                       # number of overall (read+write) accesses
+system.cpu.icache.tags.tag_accesses         245108466                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        245108466                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    243526070                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       243526070                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     243526070                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        243526070                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    243526070                       # number of overall hits
+system.cpu.icache.overall_hits::total       243526070                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst       791198                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total        791198                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst       791198                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total         791198                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst       791198                       # number of overall misses
+system.cpu.icache.overall_misses::total        791198                       # number of overall misses
+system.cpu.icache.ReadReq_accesses::cpu.inst    244317268                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    244317268                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    244317268                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    244317268                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    244317268                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    244317268                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.003238                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.003238                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.003238                       # miss rate for demand accesses
@@ -228,12 +227,12 @@ system.cpu.icache.fast_writes                       0                       # nu
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.itb_walker_cache.tags.replacements         3477                       # number of replacements
-system.cpu.itb_walker_cache.tags.tagsinuse     3.026303                       # Cycle average of tags in use
+system.cpu.itb_walker_cache.tags.tagsinuse     3.026310                       # Cycle average of tags in use
 system.cpu.itb_walker_cache.tags.total_refs         7886                       # Total number of references to valid blocks.
 system.cpu.itb_walker_cache.tags.sampled_refs         3489                       # Sample count of references to valid blocks.
 system.cpu.itb_walker_cache.tags.avg_refs     2.260246                       # Average number of references to valid blocks.
-system.cpu.itb_walker_cache.tags.warmup_cycle 5102116468000                       # Cycle when the warmup percentage was hit.
-system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker     3.026303                       # Average occupied blocks per requestor
+system.cpu.itb_walker_cache.tags.warmup_cycle 5102111082500                       # Cycle when the warmup percentage was hit.
+system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker     3.026310                       # Average occupied blocks per requestor
 system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker     0.189144                       # Average percentage of cache occupancy
 system.cpu.itb_walker_cache.tags.occ_percent::total     0.189144                       # Average percentage of cache occupancy
 system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024           12                       # Occupied blocks per task id
@@ -283,12 +282,12 @@ system.cpu.itb_walker_cache.writebacks::writebacks          526
 system.cpu.itb_walker_cache.writebacks::total          526                       # number of writebacks
 system.cpu.itb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
 system.cpu.dtb_walker_cache.tags.replacements         7632                       # number of replacements
-system.cpu.dtb_walker_cache.tags.tagsinuse     5.014181                       # Cycle average of tags in use
-system.cpu.dtb_walker_cache.tags.total_refs        12955                       # Total number of references to valid blocks.
+system.cpu.dtb_walker_cache.tags.tagsinuse     5.014183                       # Cycle average of tags in use
+system.cpu.dtb_walker_cache.tags.total_refs        12951                       # Total number of references to valid blocks.
 system.cpu.dtb_walker_cache.tags.sampled_refs         7644                       # Sample count of references to valid blocks.
-system.cpu.dtb_walker_cache.tags.avg_refs     1.694793                       # Average number of references to valid blocks.
-system.cpu.dtb_walker_cache.tags.warmup_cycle 5100462243000                       # Cycle when the warmup percentage was hit.
-system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker     5.014181                       # Average occupied blocks per requestor
+system.cpu.dtb_walker_cache.tags.avg_refs     1.694270                       # Average number of references to valid blocks.
+system.cpu.dtb_walker_cache.tags.warmup_cycle 5100459675500                       # Cycle when the warmup percentage was hit.
+system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker     5.014183                       # Average occupied blocks per requestor
 system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker     0.313386                       # Average percentage of cache occupancy
 system.cpu.dtb_walker_cache.tags.occ_percent::total     0.313386                       # Average percentage of cache occupancy
 system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024           12                       # Occupied blocks per task id
@@ -296,32 +295,32 @@ system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0            5
 system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1            2                       # Occupied blocks per task id
 system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2            5                       # Occupied blocks per task id
 system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024     0.750000                       # Percentage of cache occupancy per task id
-system.cpu.dtb_walker_cache.tags.tag_accesses        52398                       # Number of tag accesses
-system.cpu.dtb_walker_cache.tags.data_accesses        52398                       # Number of data accesses
-system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker        12963                       # number of ReadReq hits
-system.cpu.dtb_walker_cache.ReadReq_hits::total        12963                       # number of ReadReq hits
-system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker        12963                       # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.demand_hits::total        12963                       # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker        12963                       # number of overall hits
-system.cpu.dtb_walker_cache.overall_hits::total        12963                       # number of overall hits
+system.cpu.dtb_walker_cache.tags.tag_accesses        52390                       # Number of tag accesses
+system.cpu.dtb_walker_cache.tags.data_accesses        52390                       # Number of data accesses
+system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker        12959                       # number of ReadReq hits
+system.cpu.dtb_walker_cache.ReadReq_hits::total        12959                       # number of ReadReq hits
+system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker        12959                       # number of demand (read+write) hits
+system.cpu.dtb_walker_cache.demand_hits::total        12959                       # number of demand (read+write) hits
+system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker        12959                       # number of overall hits
+system.cpu.dtb_walker_cache.overall_hits::total        12959                       # number of overall hits
 system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker         8824                       # number of ReadReq misses
 system.cpu.dtb_walker_cache.ReadReq_misses::total         8824                       # number of ReadReq misses
 system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker         8824                       # number of demand (read+write) misses
 system.cpu.dtb_walker_cache.demand_misses::total         8824                       # number of demand (read+write) misses
 system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker         8824                       # number of overall misses
 system.cpu.dtb_walker_cache.overall_misses::total         8824                       # number of overall misses
-system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker        21787                       # number of ReadReq accesses(hits+misses)
-system.cpu.dtb_walker_cache.ReadReq_accesses::total        21787                       # number of ReadReq accesses(hits+misses)
-system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker        21787                       # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.demand_accesses::total        21787                       # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker        21787                       # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::total        21787                       # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker     0.405012                       # miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.ReadReq_miss_rate::total     0.405012                       # miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker     0.405012                       # miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::total     0.405012                       # miss rate for demand accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker     0.405012                       # miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::total     0.405012                       # miss rate for overall accesses
+system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker        21783                       # number of ReadReq accesses(hits+misses)
+system.cpu.dtb_walker_cache.ReadReq_accesses::total        21783                       # number of ReadReq accesses(hits+misses)
+system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker        21783                       # number of demand (read+write) accesses
+system.cpu.dtb_walker_cache.demand_accesses::total        21783                       # number of demand (read+write) accesses
+system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker        21783                       # number of overall (read+write) accesses
+system.cpu.dtb_walker_cache.overall_accesses::total        21783                       # number of overall (read+write) accesses
+system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker     0.405087                       # miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.ReadReq_miss_rate::total     0.405087                       # miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker     0.405087                       # miss rate for demand accesses
+system.cpu.dtb_walker_cache.demand_miss_rate::total     0.405087                       # miss rate for demand accesses
+system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker     0.405087                       # miss rate for overall accesses
+system.cpu.dtb_walker_cache.overall_miss_rate::total     0.405087                       # miss rate for overall accesses
 system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dtb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dtb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
@@ -333,11 +332,11 @@ system.cpu.dtb_walker_cache.cache_copies            0                       # nu
 system.cpu.dtb_walker_cache.writebacks::writebacks         2433                       # number of writebacks
 system.cpu.dtb_walker_cache.writebacks::total         2433                       # number of writebacks
 system.cpu.dtb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements           1622097                       # number of replacements
+system.cpu.dcache.tags.replacements           1622084                       # number of replacements
 system.cpu.dcache.tags.tagsinuse           511.999424                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            20175179                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           1622609                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             12.433790                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.total_refs            20175355                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           1622596                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             12.433998                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle           7549500                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.tags.occ_blocks::cpu.data   511.999424                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.999999                       # Average percentage of cache occupancy
@@ -347,40 +346,48 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0          226
 system.cpu.dcache.tags.age_task_id_blocks_1024::1          259                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::2           27                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          88813841                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         88813841                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     12077531                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        12077531                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      8095378                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        8095378                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data      20172909                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         20172909                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     20172909                       # number of overall hits
-system.cpu.dcache.overall_hits::total        20172909                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      1308430                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       1308430                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       316465                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       316465                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data      1624895                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        1624895                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      1624895                       # number of overall misses
-system.cpu.dcache.overall_misses::total       1624895                       # number of overall misses
-system.cpu.dcache.ReadReq_accesses::cpu.data     13385961                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     13385961                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data      8411843                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total      8411843                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     21797804                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     21797804                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     21797804                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     21797804                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.097746                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.097746                       # miss rate for ReadReq accesses
+system.cpu.dcache.tags.tag_accesses          88814480                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         88814480                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     12018728                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        12018728                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      8095451                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        8095451                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data        58906                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total         58906                       # number of SoftPFReq hits
+system.cpu.dcache.demand_hits::cpu.data      20114179                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         20114179                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     20173085                       # number of overall hits
+system.cpu.dcache.overall_hits::total        20173085                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       905666                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        905666                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       316462                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       316462                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data       402754                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total       402754                       # number of SoftPFReq misses
+system.cpu.dcache.demand_misses::cpu.data      1222128                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        1222128                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      1624882                       # number of overall misses
+system.cpu.dcache.overall_misses::total       1624882                       # number of overall misses
+system.cpu.dcache.ReadReq_accesses::cpu.data     12924394                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     12924394                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data      8411913                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total      8411913                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data       461660                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total       461660                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     21336307                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     21336307                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     21797967                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     21797967                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.070074                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.070074                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.037621                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_miss_rate::total     0.037621                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.074544                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.074544                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.074544                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.074544                       # miss rate for overall accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.872404                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.872404                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.057279                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.057279                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.074543                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.074543                       # miss rate for overall accesses
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -389,23 +396,23 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      1535825                       # number of writebacks
-system.cpu.dcache.writebacks::total           1535825                       # number of writebacks
+system.cpu.dcache.writebacks::writebacks      1535815                       # number of writebacks
+system.cpu.dcache.writebacks::total           1535815                       # number of writebacks
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.throughput                54625221                       # Throughput (bytes/s)
-system.cpu.toL2Bus.data_through_bus         279225555                       # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus        25472                       # Total snoop data (bytes)
-system.cpu.l2cache.tags.replacements           105999                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        64822.034013                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            3456623                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           170127                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            20.317898                       # Average number of references to valid blocks.
+system.cpu.toL2Bus.throughput                55211163                       # Throughput (bytes/s)
+system.cpu.toL2Bus.data_through_bus         279231827                       # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus      3014592                       # Total snoop data (bytes)
+system.cpu.l2cache.tags.replacements           105997                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        64822.035422                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            3456726                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           170125                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            20.318742                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 51908.839094                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::writebacks 51908.839631                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker     0.002479                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.132255                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  2490.539598                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 10422.520587                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.132256                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  2490.541573                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 10422.519483                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_percent::writebacks     0.792066                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000000                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000002                       # Average percentage of cache occupancy
@@ -416,32 +423,32 @@ system.cpu.l2cache.tags.occ_task_id_blocks::1024        64128
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0           46                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::1          282                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::2         3455                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3        20892                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        39453                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3        20884                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        39461                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.978516                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         32198887                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        32198887                       # Number of data accesses
+system.cpu.l2cache.tags.tag_accesses         32199668                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        32199668                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker         6504                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.itb.walker         2802                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.inst       777739                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data      1275554                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        2062599                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks      1538784                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      1538784                       # number of Writeback hits
+system.cpu.l2cache.ReadReq_hits::cpu.inst       777860                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data      1275544                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total        2062710                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks      1538774                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total      1538774                       # number of Writeback hits
 system.cpu.l2cache.UpgradeReq_hits::cpu.data           20                       # number of UpgradeReq hits
 system.cpu.l2cache.UpgradeReq_hits::total           20                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       179732                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       179732                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       179729                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       179729                       # number of ReadExReq hits
 system.cpu.l2cache.demand_hits::cpu.dtb.walker         6504                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::cpu.itb.walker         2802                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.inst       777739                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      1455286                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         2242331                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.inst       777860                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data      1455273                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         2242439                       # number of demand (read+write) hits
 system.cpu.l2cache.overall_hits::cpu.dtb.walker         6504                       # number of overall hits
 system.cpu.l2cache.overall_hits::cpu.itb.walker         2802                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.inst       777739                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      1455286                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        2242331                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.inst       777860                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data      1455273                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        2242439                       # number of overall hits
 system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker            1                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_misses::cpu.itb.walker            5                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_misses::cpu.inst        13325                       # number of ReadReq misses
@@ -463,44 +470,44 @@ system.cpu.l2cache.overall_misses::cpu.data       166704                       #
 system.cpu.l2cache.overall_misses::total       180035                       # number of overall misses
 system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker         6505                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker         2807                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.inst       791064                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data      1307800                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total      2108176                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks      1538784                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total      1538784                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.inst       791185                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data      1307790                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total      2108287                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks      1538774                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total      1538774                       # number of Writeback accesses(hits+misses)
 system.cpu.l2cache.UpgradeReq_accesses::cpu.data         1825                       # number of UpgradeReq accesses(hits+misses)
 system.cpu.l2cache.UpgradeReq_accesses::total         1825                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       314190                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       314190                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       314187                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       314187                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.demand_accesses::cpu.dtb.walker         6505                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::cpu.itb.walker         2807                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.inst       791064                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      1621990                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      2422366                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst       791185                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      1621977                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      2422474                       # number of demand (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.dtb.walker         6505                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.itb.walker         2807                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst       791064                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      1621990                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      2422366                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst       791185                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      1621977                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      2422474                       # number of overall (read+write) accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.000154                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.001781                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.016844                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.016842                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.024657                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.021619                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.021618                       # miss rate for ReadReq accesses
 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.989041                       # miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_miss_rate::total     0.989041                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.427951                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.427951                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.427955                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.427955                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.000154                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.001781                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.016844                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.102777                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.074322                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.016842                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.102778                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.074319                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.000154                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.001781                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.016844                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.102777                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.074322                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.016842                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.102778                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.074319                       # miss rate for overall accesses
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -509,8 +516,8 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        98156                       # number of writebacks
-system.cpu.l2cache.writebacks::total            98156                       # number of writebacks
+system.cpu.l2cache.writebacks::writebacks        98154                       # number of writebacks
+system.cpu.l2cache.writebacks::total            98154                       # number of writebacks
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
index 60b3a8779..015764a13 100644
--- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
@@ -1,135 +1,138 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  5.200396                       # Number of seconds simulated
-sim_ticks                                5200396150000                       # Number of ticks simulated
-final_tick                               5200396150000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  5.192526                       # Number of seconds simulated
+sim_ticks                                5192526233000                       # Number of ticks simulated
+final_tick                               5192526233000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 778841                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1501355                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            31560622919                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 627712                       # Number of bytes of host memory used
-host_seconds                                   164.77                       # Real time elapsed on the host
-sim_insts                                   128333376                       # Number of instructions simulated
-sim_ops                                     247385531                       # Number of ops (including micro ops) simulated
+host_inst_rate                                1492668                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2877328                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            60393582039                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 592376                       # Number of bytes of host memory used
+host_seconds                                    85.98                       # Real time elapsed on the host
+sim_insts                                   128336778                       # Number of instructions simulated
+sim_ops                                     247387190                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::pc.south_bridge.ide      2886336                       # Number of bytes read from this memory
+system.physmem.bytes_read::pc.south_bridge.ide        28352                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.dtb.walker           64                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.itb.walker          320                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst            825216                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           8967296                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             12679232                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       825216                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          825216                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      8106560                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           8106560                       # Number of bytes written to this memory
-system.physmem.num_reads::pc.south_bridge.ide        45099                       # Number of read requests responded to by this memory
+system.physmem.bytes_read::cpu.inst            829632                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           9090688                       # Number of bytes read from this memory
+system.physmem.bytes_read::total              9949056                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       829632                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          829632                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      5138240                       # Number of bytes written to this memory
+system.physmem.bytes_written::pc.south_bridge.ide      2990080                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           8128320                       # Number of bytes written to this memory
+system.physmem.num_reads::pc.south_bridge.ide          443                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.dtb.walker            1                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.itb.walker            5                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst              12894                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             140114                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                198113                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          126665                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               126665                       # Number of write requests responded to by this memory
-system.physmem.bw_read::pc.south_bridge.ide       555022                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_reads::cpu.inst              12963                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             142042                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                155454                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           80285                       # Number of write requests responded to by this memory
+system.physmem.num_writes::pc.south_bridge.ide        46720                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               127005                       # Number of write requests responded to by this memory
+system.physmem.bw_read::pc.south_bridge.ide         5460                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu.dtb.walker             12                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu.itb.walker             62                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               158683                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              1724349                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 2438128                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          158683                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             158683                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1558835                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1558835                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1558835                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::pc.south_bridge.ide       555022                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               159774                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              1750725                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 1916034                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          159774                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             159774                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks            989545                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::pc.south_bridge.ide       575843                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                1565388                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks            989545                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::pc.south_bridge.ide       581303                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.dtb.walker            12                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.itb.walker            62                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              158683                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             1724349                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                3996963                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        198113                       # Number of read requests accepted
-system.physmem.writeReqs                       126665                       # Number of write requests accepted
-system.physmem.readBursts                      198113                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     126665                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 12670976                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      8256                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   8105536                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  12679232                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                8106560                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      129                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bw_total::cpu.inst              159774                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             1750725                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                3481422                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        155454                       # Number of read requests accepted
+system.physmem.writeReqs                       127005                       # Number of write requests accepted
+system.physmem.readBursts                      155454                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     127005                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                  9932928                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     16128                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   8126720                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                   9949056                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                8128320                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      252                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs           1623                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               12177                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               12548                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               13053                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               12620                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               12592                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               12288                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               11961                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               12236                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               11972                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               11957                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              12338                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              12177                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              12807                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              12813                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              12433                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              12012                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                7757                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                8145                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                8603                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                8164                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                8201                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                7973                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                7511                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                7789                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                7356                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                7523                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               7874                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               7684                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               8313                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               8300                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               7968                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               7488                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs           1602                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               10234                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                9830                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               10412                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                9937                       # Per bank write bursts
+system.physmem.perBankRdBursts::4                9788                       # Per bank write bursts
+system.physmem.perBankRdBursts::5                9348                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                9238                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                9473                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                9270                       # Per bank write bursts
+system.physmem.perBankRdBursts::9                9085                       # Per bank write bursts
+system.physmem.perBankRdBursts::10               9528                       # Per bank write bursts
+system.physmem.perBankRdBursts::11               9619                       # Per bank write bursts
+system.physmem.perBankRdBursts::12               9707                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              10058                       # Per bank write bursts
+system.physmem.perBankRdBursts::14               9877                       # Per bank write bursts
+system.physmem.perBankRdBursts::15               9798                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                8316                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                7729                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                8212                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                7860                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                8063                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                7657                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                7184                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                7824                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                7616                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                7570                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               7824                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               7928                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               8040                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               8642                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               8420                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               8095                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    5200396086500                       # Total gap between requests
+system.physmem.totGap                    5192526169500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  198113                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  155454                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 126665                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    153621                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      2695                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                      4322                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                      2990                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                      3543                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                      4544                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                      4208                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                      3990                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                      3280                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                      2652                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                     2195                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                     1870                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                     1376                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                     1254                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                     1133                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                     1028                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                     1144                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                      834                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                      668                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                      612                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                       25                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 127005                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    151750                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      3023                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        59                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                        54                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                        34                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                        39                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                        35                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                        32                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                        28                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                        29                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                       29                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                       27                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                       25                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                       25                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                        7                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                        2                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                        2                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                        2                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
@@ -156,274 +159,272 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     1639                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     1812                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     5075                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     5119                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     5161                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     5183                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     5335                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     5509                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     5794                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     5985                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     6651                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     6946                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     6999                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     7260                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     7338                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     7801                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     7668                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     7468                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                     2018                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                     1858                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                     2408                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                     2636                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                     2551                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                     2242                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                     1885                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                     1536                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                     1298                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      897                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      721                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      585                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      277                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      223                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      173                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      132                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      119                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                       94                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                       72                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                       45                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                       44                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                       39                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       21                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                       10                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                        7                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                        6                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                        4                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                        2                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                        2                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                        2                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        59433                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      349.577642                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     202.117781                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     357.932182                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          20505     34.50%     34.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        13774     23.18%     57.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         5765      9.70%     67.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3461      5.82%     73.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2240      3.77%     76.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1591      2.68%     79.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1115      1.88%     81.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          921      1.55%     83.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        10061     16.93%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          59433                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          6976                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        28.380447                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      572.057676                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047           6975     99.99%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::47104-49151            1      0.01%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            6976                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          6976                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        18.154960                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       17.623474                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        5.583584                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-17            4785     68.59%     68.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18-19            1454     20.84%     89.44% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-21              33      0.47%     89.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22-23             125      1.79%     91.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-25              57      0.82%     92.52% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26-27              47      0.67%     93.19% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-29              75      1.08%     94.27% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::30-31              59      0.85%     95.11% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-33              41      0.59%     95.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::34-35              19      0.27%     95.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-37              30      0.43%     96.40% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::38-39              56      0.80%     97.20% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-41             145      2.08%     99.28% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::42-43              17      0.24%     99.53% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-45               4      0.06%     99.58% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::46-47              11      0.16%     99.74% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-49               3      0.04%     99.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::50-51               3      0.04%     99.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-53               2      0.03%     99.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::54-55               2      0.03%     99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-57               1      0.01%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::58-59               1      0.01%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-61               2      0.03%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::62-63               3      0.04%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-69               1      0.01%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            6976                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     5514862500                       # Total ticks spent queuing
-system.physmem.totMemAccLat                9227062500                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    989920000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       27855.09                       # Average queueing delay per DRAM burst
+system.physmem.wrQLenPdf::15                     2439                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     3242                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::60                        9                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                        8                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                        6                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                        2                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        56259                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      321.007910                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     189.347718                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     335.337897                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          20082     35.70%     35.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        13652     24.27%     59.96% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         5681     10.10%     70.06% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3443      6.12%     76.18% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2317      4.12%     80.30% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1632      2.90%     83.20% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1101      1.96%     85.16% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1008      1.79%     86.95% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         7343     13.05%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          56259                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          5896                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        26.315638                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      622.349689                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047           5895     99.98%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::47104-49151            1      0.02%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total            5896                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          5896                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        21.536635                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       19.431893                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       14.049302                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            4860     82.43%     82.43% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23              44      0.75%     83.18% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27              38      0.64%     83.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31             287      4.87%     88.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35             272      4.61%     93.30% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39              20      0.34%     93.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43              25      0.42%     94.06% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47              11      0.19%     94.25% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51              27      0.46%     94.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55               4      0.07%     94.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59               3      0.05%     94.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63               1      0.02%     94.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67             223      3.78%     98.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71               4      0.07%     98.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75               6      0.10%     98.80% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79               3      0.05%     98.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83              20      0.34%     99.19% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87               1      0.02%     99.20% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95               1      0.02%     99.22% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99              10      0.17%     99.39% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             2      0.03%     99.42% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107             2      0.03%     99.46% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111             2      0.03%     99.49% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115             8      0.14%     99.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::116-119             2      0.03%     99.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-123             4      0.07%     99.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131            13      0.22%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135             1      0.02%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143             2      0.03%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            5896                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     1473683250                       # Total ticks spent queuing
+system.physmem.totMemAccLat                4383720750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    776010000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        9495.26                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  46605.09                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           2.44                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           1.56                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        2.44                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        1.56                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  28245.26                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           1.91                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           1.57                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        1.92                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        1.57                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       0.02                       # Data bus utilization in percentage for reads
+system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.01                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        24.98                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     166366                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     98833                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   84.03                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  78.03                       # Row buffer hit rate for writes
-system.physmem.avgGap                     16012156.26                       # Average gap between requests
-system.physmem.pageHitRate                      81.69                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE     4979189621500                       # Time in different power states
-system.physmem.memoryStateTime::REF      173652440000                       # Time in different power states
+system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        22.52                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     127189                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     98733                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   81.95                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  77.74                       # Row buffer hit rate for writes
+system.physmem.avgGap                     18383291.63                       # Average gap between requests
+system.physmem.pageHitRate                      80.06                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE     4971157882750                       # Time in different power states
+system.physmem.memoryStateTime::REF      173389840000                       # Time in different power states
 system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT       47553973500                       # Time in different power states
+system.physmem.memoryStateTime::ACT       47978395250                       # Time in different power states
 system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.membus.throughput                      4356964                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq              623381                       # Transaction distribution
-system.membus.trans_dist::ReadResp             623381                       # Transaction distribution
-system.membus.trans_dist::WriteReq              13777                       # Transaction distribution
-system.membus.trans_dist::WriteResp             13777                       # Transaction distribution
-system.membus.trans_dist::Writeback            126665                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             2155                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp            1641                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            159285                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           159285                       # Transaction distribution
-system.membus.trans_dist::MessageReq             1656                       # Transaction distribution
-system.membus.trans_dist::MessageResp            1656                       # Transaction distribution
-system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave         3312                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.apicbridge.master::total         3312                       # Packet count per connected master and slave (bytes)
+system.membus.throughput                      3808612                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq              623901                       # Transaction distribution
+system.membus.trans_dist::ReadResp             623901                       # Transaction distribution
+system.membus.trans_dist::WriteReq              13773                       # Transaction distribution
+system.membus.trans_dist::WriteResp             13773                       # Transaction distribution
+system.membus.trans_dist::Writeback             80285                       # Transaction distribution
+system.membus.trans_dist::WriteInvalidateReq        46720                       # Transaction distribution
+system.membus.trans_dist::WriteInvalidateResp        46720                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq             2146                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp            1602                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            113400                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           113400                       # Transaction distribution
+system.membus.trans_dist::MessageReq             1654                       # Transaction distribution
+system.membus.trans_dist::MessageResp            1654                       # Transaction distribution
+system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave         3308                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.apicbridge.master::total         3308                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       480328                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio       710118                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       390454                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1580900                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       139322                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       139322                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1723534                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave         6624                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.apicbridge.master::total         6624                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio       710110                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       394055                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1584493                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        94727                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total        94727                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                1682528                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave         6616                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.apicbridge.master::total         6616                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       246444                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio      1420233                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     14912768                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total     16579445                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port      5873024                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::total      5873024                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total            22459093                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus               22459093                       # Total data (bytes)
-system.membus.snoop_data_through_bus           198848                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy           256797000                       # Layer occupancy (ticks)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio      1420217                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     15058944                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total     16725605                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port      3018432                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.iocache.mem_side::total      3018432                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total            19750653                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus               19750653                       # Total data (bytes)
+system.membus.snoop_data_through_bus            25664                       # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy           256795500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy           359321500                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             3312000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             3308000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer3.occupancy          1351243000                       # Layer occupancy (ticks)
+system.membus.reqLayer3.occupancy          1309717000                       # Layer occupancy (ticks)
 system.membus.reqLayer3.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer0.occupancy            1656000                       # Layer occupancy (ticks)
+system.membus.respLayer0.occupancy            1654000                       # Layer occupancy (ticks)
 system.membus.respLayer0.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         2609486505                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         2621518398                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.1                       # Layer utilization (%)
-system.membus.respLayer4.occupancy          429020250                       # Layer occupancy (ticks)
+system.membus.respLayer4.occupancy           54330498                       # Layer occupancy (ticks)
 system.membus.respLayer4.utilization              0.0                       # Layer utilization (%)
-system.iocache.tags.replacements                47501                       # number of replacements
-system.iocache.tags.tagsinuse                0.128246                       # Cycle average of tags in use
+system.iocache.tags.replacements                47509                       # number of replacements
+system.iocache.tags.tagsinuse                0.112613                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs                47517                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs                47525                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         5049779388000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::pc.south_bridge.ide     0.128246                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::pc.south_bridge.ide     0.008015                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.008015                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         5045777659000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::pc.south_bridge.ide     0.112613                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::pc.south_bridge.ide     0.007038                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.007038                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses               428004                       # Number of tag accesses
-system.iocache.tags.data_accesses              428004                       # Number of data accesses
-system.iocache.ReadReq_misses::pc.south_bridge.ide          836                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total              836                       # number of ReadReq misses
-system.iocache.WriteReq_misses::pc.south_bridge.ide        46720                       # number of WriteReq misses
-system.iocache.WriteReq_misses::total           46720                       # number of WriteReq misses
-system.iocache.demand_misses::pc.south_bridge.ide        47556                       # number of demand (read+write) misses
-system.iocache.demand_misses::total             47556                       # number of demand (read+write) misses
-system.iocache.overall_misses::pc.south_bridge.ide        47556                       # number of overall misses
-system.iocache.overall_misses::total            47556                       # number of overall misses
-system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    140309686                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total    140309686                       # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency::pc.south_bridge.ide  12229393602                       # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_latency::total  12229393602                       # number of WriteReq miss cycles
-system.iocache.demand_miss_latency::pc.south_bridge.ide  12369703288                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total  12369703288                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::pc.south_bridge.ide  12369703288                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total  12369703288                       # number of overall miss cycles
-system.iocache.ReadReq_accesses::pc.south_bridge.ide          836                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total            836                       # number of ReadReq accesses(hits+misses)
-system.iocache.WriteReq_accesses::pc.south_bridge.ide        46720                       # number of WriteReq accesses(hits+misses)
-system.iocache.WriteReq_accesses::total         46720                       # number of WriteReq accesses(hits+misses)
-system.iocache.demand_accesses::pc.south_bridge.ide        47556                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total           47556                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::pc.south_bridge.ide        47556                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total          47556                       # number of overall (read+write) accesses
+system.iocache.tags.tag_accesses               428076                       # Number of tag accesses
+system.iocache.tags.data_accesses              428076                       # Number of data accesses
+system.iocache.WriteInvalidateReq_hits::pc.south_bridge.ide        46720                       # number of WriteInvalidateReq hits
+system.iocache.WriteInvalidateReq_hits::total        46720                       # number of WriteInvalidateReq hits
+system.iocache.ReadReq_misses::pc.south_bridge.ide          844                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total              844                       # number of ReadReq misses
+system.iocache.demand_misses::pc.south_bridge.ide          844                       # number of demand (read+write) misses
+system.iocache.demand_misses::total               844                       # number of demand (read+write) misses
+system.iocache.overall_misses::pc.south_bridge.ide          844                       # number of overall misses
+system.iocache.overall_misses::total              844                       # number of overall misses
+system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    141199186                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total    141199186                       # number of ReadReq miss cycles
+system.iocache.demand_miss_latency::pc.south_bridge.ide    141199186                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total    141199186                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::pc.south_bridge.ide    141199186                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total    141199186                       # number of overall miss cycles
+system.iocache.ReadReq_accesses::pc.south_bridge.ide          844                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total            844                       # number of ReadReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide        46720                       # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::total        46720                       # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.demand_accesses::pc.south_bridge.ide          844                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total             844                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::pc.south_bridge.ide          844                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total            844                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
-system.iocache.WriteReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for WriteReq accesses
-system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
 system.iocache.demand_miss_rate::pc.south_bridge.ide            1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::pc.south_bridge.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 167834.552632                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 167834.552632                       # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 261759.280865                       # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total 261759.280865                       # average WriteReq miss latency
-system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 260108.152242                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 260108.152242                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 260108.152242                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 260108.152242                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs        207651                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 167297.613744                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 167297.613744                       # average ReadReq miss latency
+system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 167297.613744                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 167297.613744                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 167297.613744                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 167297.613744                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs           471                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                17427                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                   39                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs    11.915476                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs    12.076923                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.fast_writes                          0                       # number of fast writes performed
+system.iocache.fast_writes                      46720                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.writebacks::writebacks           46667                       # number of writebacks
-system.iocache.writebacks::total                46667                       # number of writebacks
-system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          836                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total          836                       # number of ReadReq MSHR misses
-system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide        46720                       # number of WriteReq MSHR misses
-system.iocache.WriteReq_mshr_misses::total        46720                       # number of WriteReq MSHR misses
-system.iocache.demand_mshr_misses::pc.south_bridge.ide        47556                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total        47556                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::pc.south_bridge.ide        47556                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total        47556                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide     96812686                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     96812686                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide   9797946102                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::total   9797946102                       # number of WriteReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide   9894758788                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   9894758788                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide   9894758788                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   9894758788                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          844                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total          844                       # number of ReadReq MSHR misses
+system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide        46720                       # number of WriteInvalidateReq MSHR misses
+system.iocache.WriteInvalidateReq_mshr_misses::total        46720                       # number of WriteInvalidateReq MSHR misses
+system.iocache.demand_mshr_misses::pc.south_bridge.ide          844                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total          844                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::pc.south_bridge.ide          844                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total          844                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide     97286186                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     97286186                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide   2834928162                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::total   2834928162                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide     97286186                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total     97286186                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide     97286186                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total     97286186                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
-system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for WriteReq accesses
-system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
+system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteInvalidateReq accesses
 system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for demand accesses
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 115804.648325                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 115804.648325                       # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 209716.312115                       # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total 209716.312115                       # average WriteReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 208065.413155                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 208065.413155                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 208065.413155                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 208065.413155                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 115267.992891                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 115267.992891                       # average ReadReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 60679.113057                       # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60679.113057                       # average WriteInvalidateReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 115267.992891                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 115267.992891                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 115267.992891                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 115267.992891                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
 system.pc.south_bridge.ide.disks0.dma_read_bytes        34816                       # Number of bytes transfered via DMA reads (not PRD).
@@ -437,13 +438,13 @@ system.pc.south_bridge.ide.disks1.dma_read_txs            0
 system.pc.south_bridge.ide.disks1.dma_write_full_pages            1                       # Number of full page size DMA writes.
 system.pc.south_bridge.ide.disks1.dma_write_bytes         4096                       # Number of bytes transfered via DMA writes.
 system.pc.south_bridge.ide.disks1.dma_write_txs            1                       # Number of DMA write transactions.
-system.iobus.throughput                        630779                       # Throughput (bytes/s)
-system.iobus.trans_dist::ReadReq               230141                       # Transaction distribution
-system.iobus.trans_dist::ReadResp              230141                       # Transaction distribution
+system.iobus.throughput                        631746                       # Throughput (bytes/s)
+system.iobus.trans_dist::ReadReq               230149                       # Transaction distribution
+system.iobus.trans_dist::ReadResp              230149                       # Transaction distribution
 system.iobus.trans_dist::WriteReq               57579                       # Transaction distribution
 system.iobus.trans_dist::WriteResp              57579                       # Transaction distribution
-system.iobus.trans_dist::MessageReq              1656                       # Transaction distribution
-system.iobus.trans_dist::MessageResp             1656                       # Transaction distribution
+system.iobus.trans_dist::MessageReq              1654                       # Transaction distribution
+system.iobus.trans_dist::MessageResp             1654                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio           44                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio            6                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio        11088                       # Packet count per connected master and slave (bytes)
@@ -463,11 +464,11 @@ system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio
 system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio           10                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio         2128                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::total       480328                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side        95112                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total        95112                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         3312                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total         3312                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  578752                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side        95128                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total        95128                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         3308                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total         3308                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  578764                       # Packet count per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio           22                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio            3                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio         6686                       # Cumulative packet size per connected master and slave (bytes)
@@ -487,13 +488,13 @@ system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_4.pio
 system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_floppy.pio            5                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio         4256                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::total       246444                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side      3027232                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total      3027232                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         6624                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total         6624                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::total              3280300                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.data_through_bus                 3280300                       # Total data (bytes)
-system.iobus.reqLayer0.occupancy              3954900                       # Layer occupancy (ticks)
+system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side      3027296                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total      3027296                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         6616                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total         6616                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::total              3280356                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.data_through_bus                 3280356                       # Total data (bytes)
+system.iobus.reqLayer0.occupancy              3944816                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy                34000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
@@ -529,47 +530,47 @@ system.iobus.reqLayer16.occupancy                9000                       # La
 system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer17.occupancy               10000                       # Layer occupancy (ticks)
 system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer18.occupancy           424640038                       # Layer occupancy (ticks)
+system.iobus.reqLayer18.occupancy           421898846                       # Layer occupancy (ticks)
 system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer19.occupancy             1064000                       # Layer occupancy (ticks)
 system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy           469469000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer1.occupancy            53686750                       # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy            52228502                       # Layer occupancy (ticks)
 system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer2.occupancy             1656000                       # Layer occupancy (ticks)
+system.iobus.respLayer2.occupancy             1654000                       # Layer occupancy (ticks)
 system.iobus.respLayer2.utilization               0.0                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
-system.cpu.numCycles                      10400792300                       # number of cpu cycles simulated
+system.cpu.numCycles                      10385052466                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                   128333376                       # Number of instructions committed
-system.cpu.committedOps                     247385531                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses             231978349                       # Number of integer alu accesses
+system.cpu.committedInsts                   128336778                       # Number of instructions committed
+system.cpu.committedOps                     247387190                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses             231979854                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                      0                       # Number of float alu accesses
-system.cpu.num_func_calls                     2299991                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts     23168967                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                    231978349                       # number of integer instructions
+system.cpu.num_func_calls                     2299861                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts     23168822                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                    231979854                       # number of integer instructions
 system.cpu.num_fp_insts                             0                       # number of float instructions
-system.cpu.num_int_register_reads           434511356                       # number of times the integer registers were read
-system.cpu.num_int_register_writes          197852349                       # number of times the integer registers were written
+system.cpu.num_int_register_reads           434516750                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          197854064                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                    0                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
-system.cpu.num_cc_register_reads            132811982                       # number of times the CC registers were read
-system.cpu.num_cc_register_writes            95533715                       # number of times the CC registers were written
-system.cpu.num_mem_refs                      22244872                       # number of memory refs
-system.cpu.num_load_insts                    13879055                       # Number of load instructions
-system.cpu.num_store_insts                    8365817                       # Number of store instructions
-system.cpu.num_idle_cycles               9793794512.998117                       # Number of idle cycles
-system.cpu.num_busy_cycles               606997787.001883                       # Number of busy cycles
-system.cpu.not_idle_fraction                 0.058361                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                     0.941639                       # Percentage of idle cycles
-system.cpu.Branches                          26307123                       # Number of branches fetched
-system.cpu.op_class::No_OpClass                174810      0.07%      0.07% # Class of executed instruction
-system.cpu.op_class::IntAlu                 224704553     90.83%     90.90% # Class of executed instruction
-system.cpu.op_class::IntMult                   139755      0.06%     90.96% # Class of executed instruction
-system.cpu.op_class::IntDiv                    123089      0.05%     91.01% # Class of executed instruction
+system.cpu.num_cc_register_reads            132811657                       # number of times the CC registers were read
+system.cpu.num_cc_register_writes            95534544                       # number of times the CC registers were written
+system.cpu.num_mem_refs                      22246380                       # number of memory refs
+system.cpu.num_load_insts                    13880618                       # Number of load instructions
+system.cpu.num_store_insts                    8365762                       # Number of store instructions
+system.cpu.num_idle_cycles               9788359567.998116                       # Number of idle cycles
+system.cpu.num_busy_cycles               596692898.001885                       # Number of busy cycles
+system.cpu.not_idle_fraction                 0.057457                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                     0.942543                       # Percentage of idle cycles
+system.cpu.Branches                          26306776                       # Number of branches fetched
+system.cpu.op_class::No_OpClass                174693      0.07%      0.07% # Class of executed instruction
+system.cpu.op_class::IntAlu                 224704760     90.83%     90.90% # Class of executed instruction
+system.cpu.op_class::IntMult                   139946      0.06%     90.96% # Class of executed instruction
+system.cpu.op_class::IntDiv                    122983      0.05%     91.01% # Class of executed instruction
 system.cpu.op_class::FloatAdd                       0      0.00%     91.01% # Class of executed instruction
 system.cpu.op_class::FloatCmp                       0      0.00%     91.01% # Class of executed instruction
 system.cpu.op_class::FloatCvt                       0      0.00%     91.01% # Class of executed instruction
@@ -596,66 +597,66 @@ system.cpu.op_class::SimdFloatMisc                  0      0.00%     91.01% # Cl
 system.cpu.op_class::SimdFloatMult                  0      0.00%     91.01% # Class of executed instruction
 system.cpu.op_class::SimdFloatMultAcc               0      0.00%     91.01% # Class of executed instruction
 system.cpu.op_class::SimdFloatSqrt                  0      0.00%     91.01% # Class of executed instruction
-system.cpu.op_class::MemRead                 13879055      5.61%     96.62% # Class of executed instruction
-system.cpu.op_class::MemWrite                 8365817      3.38%    100.00% # Class of executed instruction
+system.cpu.op_class::MemRead                 13880618      5.61%     96.62% # Class of executed instruction
+system.cpu.op_class::MemWrite                 8365762      3.38%    100.00% # Class of executed instruction
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::total                  247387079                       # Class of executed instruction
+system.cpu.op_class::total                  247388762                       # Class of executed instruction
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
 system.cpu.kern.inst.quiesce                        0                       # number of quiesce instructions executed
-system.cpu.icache.tags.replacements            791030                       # number of replacements
-system.cpu.icache.tags.tagsinuse           510.352813                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           144579864                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs            791542                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs            182.655960                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle      161437750250                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   510.352813                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.996783                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.996783                       # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements            794564                       # number of replacements
+system.cpu.icache.tags.tagsinuse           510.353610                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           144580687                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs            795076                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs            181.845115                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle      161037642250                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   510.353610                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.996784                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.996784                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           51                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          154                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          298                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3            9                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           53                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          159                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          295                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3            5                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         146162962                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        146162962                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    144579864                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       144579864                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     144579864                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        144579864                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    144579864                       # number of overall hits
-system.cpu.icache.overall_hits::total       144579864                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst       791549                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total        791549                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst       791549                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total         791549                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst       791549                       # number of overall misses
-system.cpu.icache.overall_misses::total        791549                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  11108553755                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  11108553755                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  11108553755                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  11108553755                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  11108553755                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  11108553755                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    145371413                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    145371413                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    145371413                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    145371413                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    145371413                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    145371413                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.005445                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.005445                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.005445                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.005445                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.005445                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.005445                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14033.943262                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 14033.943262                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 14033.943262                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 14033.943262                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 14033.943262                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 14033.943262                       # average overall miss latency
+system.cpu.icache.tags.tag_accesses         146170853                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        146170853                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    144580687                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       144580687                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     144580687                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        144580687                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    144580687                       # number of overall hits
+system.cpu.icache.overall_hits::total       144580687                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst       795083                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total        795083                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst       795083                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total         795083                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst       795083                       # number of overall misses
+system.cpu.icache.overall_misses::total        795083                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  11158319369                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  11158319369                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  11158319369                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  11158319369                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  11158319369                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  11158319369                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    145375770                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    145375770                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    145375770                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    145375770                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    145375770                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    145375770                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.005469                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.005469                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.005469                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.005469                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.005469                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.005469                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14034.156647                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 14034.156647                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 14034.156647                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 14034.156647                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 14034.156647                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 14034.156647                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -664,88 +665,87 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst       791549                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total       791549                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst       791549                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total       791549                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst       791549                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total       791549                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   9520697745                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total   9520697745                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst   9520697745                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total   9520697745                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst   9520697745                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total   9520697745                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.005445                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.005445                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.005445                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.005445                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.005445                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.005445                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12027.932251                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12027.932251                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12027.932251                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 12027.932251                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12027.932251                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 12027.932251                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst       795083                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total       795083                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst       795083                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total       795083                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst       795083                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total       795083                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   9563233631                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total   9563233631                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst   9563233631                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total   9563233631                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst   9563233631                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total   9563233631                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.005469                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.005469                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.005469                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.005469                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.005469                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.005469                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12027.968943                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12027.968943                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12027.968943                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 12027.968943                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12027.968943                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 12027.968943                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.itb_walker_cache.tags.replacements         3407                       # number of replacements
-system.cpu.itb_walker_cache.tags.tagsinuse     3.079507                       # Cycle average of tags in use
-system.cpu.itb_walker_cache.tags.total_refs         7935                       # Total number of references to valid blocks.
-system.cpu.itb_walker_cache.tags.sampled_refs         3418                       # Sample count of references to valid blocks.
-system.cpu.itb_walker_cache.tags.avg_refs     2.321533                       # Average number of references to valid blocks.
-system.cpu.itb_walker_cache.tags.warmup_cycle 5169623666000                       # Cycle when the warmup percentage was hit.
-system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker     3.079507                       # Average occupied blocks per requestor
-system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker     0.192469                       # Average percentage of cache occupancy
-system.cpu.itb_walker_cache.tags.occ_percent::total     0.192469                       # Average percentage of cache occupancy
-system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024           11                       # Occupied blocks per task id
-system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0            3                       # Occupied blocks per task id
-system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1            2                       # Occupied blocks per task id
+system.cpu.itb_walker_cache.tags.replacements         3511                       # number of replacements
+system.cpu.itb_walker_cache.tags.tagsinuse     3.067889                       # Cycle average of tags in use
+system.cpu.itb_walker_cache.tags.total_refs         7844                       # Total number of references to valid blocks.
+system.cpu.itb_walker_cache.tags.sampled_refs         3523                       # Sample count of references to valid blocks.
+system.cpu.itb_walker_cache.tags.avg_refs     2.226511                       # Average number of references to valid blocks.
+system.cpu.itb_walker_cache.tags.warmup_cycle 5164932679000                       # Cycle when the warmup percentage was hit.
+system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker     3.067889                       # Average occupied blocks per requestor
+system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker     0.191743                       # Average percentage of cache occupancy
+system.cpu.itb_walker_cache.tags.occ_percent::total     0.191743                       # Average percentage of cache occupancy
+system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024           12                       # Occupied blocks per task id
+system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0            4                       # Occupied blocks per task id
+system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1            3                       # Occupied blocks per task id
 system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2            5                       # Occupied blocks per task id
-system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
-system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024     0.687500                       # Percentage of cache occupancy per task id
-system.cpu.itb_walker_cache.tags.tag_accesses        28718                       # Number of tag accesses
-system.cpu.itb_walker_cache.tags.data_accesses        28718                       # Number of data accesses
-system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker         7937                       # number of ReadReq hits
-system.cpu.itb_walker_cache.ReadReq_hits::total         7937                       # number of ReadReq hits
+system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024     0.750000                       # Percentage of cache occupancy per task id
+system.cpu.itb_walker_cache.tags.tag_accesses        28837                       # Number of tag accesses
+system.cpu.itb_walker_cache.tags.data_accesses        28837                       # Number of data accesses
+system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker         7845                       # number of ReadReq hits
+system.cpu.itb_walker_cache.ReadReq_hits::total         7845                       # number of ReadReq hits
 system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker            2                       # number of WriteReq hits
 system.cpu.itb_walker_cache.WriteReq_hits::total            2                       # number of WriteReq hits
-system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker         7939                       # number of demand (read+write) hits
-system.cpu.itb_walker_cache.demand_hits::total         7939                       # number of demand (read+write) hits
-system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker         7939                       # number of overall hits
-system.cpu.itb_walker_cache.overall_hits::total         7939                       # number of overall hits
-system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker         4280                       # number of ReadReq misses
-system.cpu.itb_walker_cache.ReadReq_misses::total         4280                       # number of ReadReq misses
-system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker         4280                       # number of demand (read+write) misses
-system.cpu.itb_walker_cache.demand_misses::total         4280                       # number of demand (read+write) misses
-system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker         4280                       # number of overall misses
-system.cpu.itb_walker_cache.overall_misses::total         4280                       # number of overall misses
-system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker     42457500                       # number of ReadReq miss cycles
-system.cpu.itb_walker_cache.ReadReq_miss_latency::total     42457500                       # number of ReadReq miss cycles
-system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker     42457500                       # number of demand (read+write) miss cycles
-system.cpu.itb_walker_cache.demand_miss_latency::total     42457500                       # number of demand (read+write) miss cycles
-system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker     42457500                       # number of overall miss cycles
-system.cpu.itb_walker_cache.overall_miss_latency::total     42457500                       # number of overall miss cycles
-system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker        12217                       # number of ReadReq accesses(hits+misses)
-system.cpu.itb_walker_cache.ReadReq_accesses::total        12217                       # number of ReadReq accesses(hits+misses)
+system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker         7847                       # number of demand (read+write) hits
+system.cpu.itb_walker_cache.demand_hits::total         7847                       # number of demand (read+write) hits
+system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker         7847                       # number of overall hits
+system.cpu.itb_walker_cache.overall_hits::total         7847                       # number of overall hits
+system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker         4381                       # number of ReadReq misses
+system.cpu.itb_walker_cache.ReadReq_misses::total         4381                       # number of ReadReq misses
+system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker         4381                       # number of demand (read+write) misses
+system.cpu.itb_walker_cache.demand_misses::total         4381                       # number of demand (read+write) misses
+system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker         4381                       # number of overall misses
+system.cpu.itb_walker_cache.overall_misses::total         4381                       # number of overall misses
+system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker     43773750                       # number of ReadReq miss cycles
+system.cpu.itb_walker_cache.ReadReq_miss_latency::total     43773750                       # number of ReadReq miss cycles
+system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker     43773750                       # number of demand (read+write) miss cycles
+system.cpu.itb_walker_cache.demand_miss_latency::total     43773750                       # number of demand (read+write) miss cycles
+system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker     43773750                       # number of overall miss cycles
+system.cpu.itb_walker_cache.overall_miss_latency::total     43773750                       # number of overall miss cycles
+system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker        12226                       # number of ReadReq accesses(hits+misses)
+system.cpu.itb_walker_cache.ReadReq_accesses::total        12226                       # number of ReadReq accesses(hits+misses)
 system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker            2                       # number of WriteReq accesses(hits+misses)
 system.cpu.itb_walker_cache.WriteReq_accesses::total            2                       # number of WriteReq accesses(hits+misses)
-system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker        12219                       # number of demand (read+write) accesses
-system.cpu.itb_walker_cache.demand_accesses::total        12219                       # number of demand (read+write) accesses
-system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker        12219                       # number of overall (read+write) accesses
-system.cpu.itb_walker_cache.overall_accesses::total        12219                       # number of overall (read+write) accesses
-system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker     0.350332                       # miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.ReadReq_miss_rate::total     0.350332                       # miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker     0.350274                       # miss rate for demand accesses
-system.cpu.itb_walker_cache.demand_miss_rate::total     0.350274                       # miss rate for demand accesses
-system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker     0.350274                       # miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_miss_rate::total     0.350274                       # miss rate for overall accesses
-system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker  9919.976636                       # average ReadReq miss latency
-system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total  9919.976636                       # average ReadReq miss latency
-system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker  9919.976636                       # average overall miss latency
-system.cpu.itb_walker_cache.demand_avg_miss_latency::total  9919.976636                       # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker  9919.976636                       # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_miss_latency::total  9919.976636                       # average overall miss latency
+system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker        12228                       # number of demand (read+write) accesses
+system.cpu.itb_walker_cache.demand_accesses::total        12228                       # number of demand (read+write) accesses
+system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker        12228                       # number of overall (read+write) accesses
+system.cpu.itb_walker_cache.overall_accesses::total        12228                       # number of overall (read+write) accesses
+system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker     0.358335                       # miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.ReadReq_miss_rate::total     0.358335                       # miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker     0.358276                       # miss rate for demand accesses
+system.cpu.itb_walker_cache.demand_miss_rate::total     0.358276                       # miss rate for demand accesses
+system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker     0.358276                       # miss rate for overall accesses
+system.cpu.itb_walker_cache.overall_miss_rate::total     0.358276                       # miss rate for overall accesses
+system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker  9991.725633                       # average ReadReq miss latency
+system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total  9991.725633                       # average ReadReq miss latency
+system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker  9991.725633                       # average overall miss latency
+system.cpu.itb_walker_cache.demand_avg_miss_latency::total  9991.725633                       # average overall miss latency
+system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker  9991.725633                       # average overall miss latency
+system.cpu.itb_walker_cache.overall_avg_miss_latency::total  9991.725633                       # average overall miss latency
 system.cpu.itb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.itb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.itb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
@@ -754,86 +754,86 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.itb_walker_cache.fast_writes             0                       # number of fast writes performed
 system.cpu.itb_walker_cache.cache_copies            0                       # number of cache copies performed
-system.cpu.itb_walker_cache.writebacks::writebacks          704                       # number of writebacks
-system.cpu.itb_walker_cache.writebacks::total          704                       # number of writebacks
-system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker         4280                       # number of ReadReq MSHR misses
-system.cpu.itb_walker_cache.ReadReq_mshr_misses::total         4280                       # number of ReadReq MSHR misses
-system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker         4280                       # number of demand (read+write) MSHR misses
-system.cpu.itb_walker_cache.demand_mshr_misses::total         4280                       # number of demand (read+write) MSHR misses
-system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker         4280                       # number of overall MSHR misses
-system.cpu.itb_walker_cache.overall_mshr_misses::total         4280                       # number of overall MSHR misses
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker     33895500                       # number of ReadReq MSHR miss cycles
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total     33895500                       # number of ReadReq MSHR miss cycles
-system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker     33895500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.itb_walker_cache.demand_mshr_miss_latency::total     33895500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker     33895500                       # number of overall MSHR miss cycles
-system.cpu.itb_walker_cache.overall_mshr_miss_latency::total     33895500                       # number of overall MSHR miss cycles
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.350332                       # mshr miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total     0.350332                       # mshr miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker     0.350274                       # mshr miss rate for demand accesses
-system.cpu.itb_walker_cache.demand_mshr_miss_rate::total     0.350274                       # mshr miss rate for demand accesses
-system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker     0.350274                       # mshr miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_mshr_miss_rate::total     0.350274                       # mshr miss rate for overall accesses
-system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker  7919.509346                       # average ReadReq mshr miss latency
-system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total  7919.509346                       # average ReadReq mshr miss latency
-system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker  7919.509346                       # average overall mshr miss latency
-system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total  7919.509346                       # average overall mshr miss latency
-system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker  7919.509346                       # average overall mshr miss latency
-system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total  7919.509346                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.writebacks::writebacks          771                       # number of writebacks
+system.cpu.itb_walker_cache.writebacks::total          771                       # number of writebacks
+system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker         4381                       # number of ReadReq MSHR misses
+system.cpu.itb_walker_cache.ReadReq_mshr_misses::total         4381                       # number of ReadReq MSHR misses
+system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker         4381                       # number of demand (read+write) MSHR misses
+system.cpu.itb_walker_cache.demand_mshr_misses::total         4381                       # number of demand (read+write) MSHR misses
+system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker         4381                       # number of overall MSHR misses
+system.cpu.itb_walker_cache.overall_mshr_misses::total         4381                       # number of overall MSHR misses
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker     35010250                       # number of ReadReq MSHR miss cycles
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total     35010250                       # number of ReadReq MSHR miss cycles
+system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker     35010250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.itb_walker_cache.demand_mshr_miss_latency::total     35010250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker     35010250                       # number of overall MSHR miss cycles
+system.cpu.itb_walker_cache.overall_mshr_miss_latency::total     35010250                       # number of overall MSHR miss cycles
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.358335                       # mshr miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total     0.358335                       # mshr miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker     0.358276                       # mshr miss rate for demand accesses
+system.cpu.itb_walker_cache.demand_mshr_miss_rate::total     0.358276                       # mshr miss rate for demand accesses
+system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker     0.358276                       # mshr miss rate for overall accesses
+system.cpu.itb_walker_cache.overall_mshr_miss_rate::total     0.358276                       # mshr miss rate for overall accesses
+system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker  7991.383246                       # average ReadReq mshr miss latency
+system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total  7991.383246                       # average ReadReq mshr miss latency
+system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker  7991.383246                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total  7991.383246                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker  7991.383246                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total  7991.383246                       # average overall mshr miss latency
 system.cpu.itb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
-system.cpu.dtb_walker_cache.tags.replacements         7502                       # number of replacements
-system.cpu.dtb_walker_cache.tags.tagsinuse     5.061351                       # Cycle average of tags in use
-system.cpu.dtb_walker_cache.tags.total_refs        13282                       # Total number of references to valid blocks.
-system.cpu.dtb_walker_cache.tags.sampled_refs         7516                       # Sample count of references to valid blocks.
-system.cpu.dtb_walker_cache.tags.avg_refs     1.767163                       # Average number of references to valid blocks.
-system.cpu.dtb_walker_cache.tags.warmup_cycle 5167976228000                       # Cycle when the warmup percentage was hit.
-system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker     5.061351                       # Average occupied blocks per requestor
-system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker     0.316334                       # Average percentage of cache occupancy
-system.cpu.dtb_walker_cache.tags.occ_percent::total     0.316334                       # Average percentage of cache occupancy
+system.cpu.dtb_walker_cache.tags.replacements         7447                       # number of replacements
+system.cpu.dtb_walker_cache.tags.tagsinuse     5.051866                       # Cycle average of tags in use
+system.cpu.dtb_walker_cache.tags.total_refs        13273                       # Total number of references to valid blocks.
+system.cpu.dtb_walker_cache.tags.sampled_refs         7461                       # Sample count of references to valid blocks.
+system.cpu.dtb_walker_cache.tags.avg_refs     1.778984                       # Average number of references to valid blocks.
+system.cpu.dtb_walker_cache.tags.warmup_cycle 5163481853000                       # Cycle when the warmup percentage was hit.
+system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker     5.051866                       # Average occupied blocks per requestor
+system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker     0.315742                       # Average percentage of cache occupancy
+system.cpu.dtb_walker_cache.tags.occ_percent::total     0.315742                       # Average percentage of cache occupancy
 system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024           14                       # Occupied blocks per task id
-system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0            2                       # Occupied blocks per task id
-system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1            7                       # Occupied blocks per task id
+system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0            3                       # Occupied blocks per task id
+system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1            5                       # Occupied blocks per task id
 system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2            4                       # Occupied blocks per task id
-system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
+system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
 system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024     0.875000                       # Percentage of cache occupancy per task id
-system.cpu.dtb_walker_cache.tags.tag_accesses        52668                       # Number of tag accesses
-system.cpu.dtb_walker_cache.tags.data_accesses        52668                       # Number of data accesses
-system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker        13284                       # number of ReadReq hits
-system.cpu.dtb_walker_cache.ReadReq_hits::total        13284                       # number of ReadReq hits
-system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker        13284                       # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.demand_hits::total        13284                       # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker        13284                       # number of overall hits
-system.cpu.dtb_walker_cache.overall_hits::total        13284                       # number of overall hits
-system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker         8700                       # number of ReadReq misses
-system.cpu.dtb_walker_cache.ReadReq_misses::total         8700                       # number of ReadReq misses
-system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker         8700                       # number of demand (read+write) misses
-system.cpu.dtb_walker_cache.demand_misses::total         8700                       # number of demand (read+write) misses
-system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker         8700                       # number of overall misses
-system.cpu.dtb_walker_cache.overall_misses::total         8700                       # number of overall misses
-system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker     92345000                       # number of ReadReq miss cycles
-system.cpu.dtb_walker_cache.ReadReq_miss_latency::total     92345000                       # number of ReadReq miss cycles
-system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker     92345000                       # number of demand (read+write) miss cycles
-system.cpu.dtb_walker_cache.demand_miss_latency::total     92345000                       # number of demand (read+write) miss cycles
-system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker     92345000                       # number of overall miss cycles
-system.cpu.dtb_walker_cache.overall_miss_latency::total     92345000                       # number of overall miss cycles
-system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker        21984                       # number of ReadReq accesses(hits+misses)
-system.cpu.dtb_walker_cache.ReadReq_accesses::total        21984                       # number of ReadReq accesses(hits+misses)
-system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker        21984                       # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.demand_accesses::total        21984                       # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker        21984                       # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::total        21984                       # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker     0.395742                       # miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.ReadReq_miss_rate::total     0.395742                       # miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker     0.395742                       # miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::total     0.395742                       # miss rate for demand accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker     0.395742                       # miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::total     0.395742                       # miss rate for overall accesses
-system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10614.367816                       # average ReadReq miss latency
-system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10614.367816                       # average ReadReq miss latency
-system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10614.367816                       # average overall miss latency
-system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10614.367816                       # average overall miss latency
-system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10614.367816                       # average overall miss latency
-system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10614.367816                       # average overall miss latency
+system.cpu.dtb_walker_cache.tags.tag_accesses        52546                       # Number of tag accesses
+system.cpu.dtb_walker_cache.tags.data_accesses        52546                       # Number of data accesses
+system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker        13289                       # number of ReadReq hits
+system.cpu.dtb_walker_cache.ReadReq_hits::total        13289                       # number of ReadReq hits
+system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker        13289                       # number of demand (read+write) hits
+system.cpu.dtb_walker_cache.demand_hits::total        13289                       # number of demand (read+write) hits
+system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker        13289                       # number of overall hits
+system.cpu.dtb_walker_cache.overall_hits::total        13289                       # number of overall hits
+system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker         8656                       # number of ReadReq misses
+system.cpu.dtb_walker_cache.ReadReq_misses::total         8656                       # number of ReadReq misses
+system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker         8656                       # number of demand (read+write) misses
+system.cpu.dtb_walker_cache.demand_misses::total         8656                       # number of demand (read+write) misses
+system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker         8656                       # number of overall misses
+system.cpu.dtb_walker_cache.overall_misses::total         8656                       # number of overall misses
+system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker     91979000                       # number of ReadReq miss cycles
+system.cpu.dtb_walker_cache.ReadReq_miss_latency::total     91979000                       # number of ReadReq miss cycles
+system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker     91979000                       # number of demand (read+write) miss cycles
+system.cpu.dtb_walker_cache.demand_miss_latency::total     91979000                       # number of demand (read+write) miss cycles
+system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker     91979000                       # number of overall miss cycles
+system.cpu.dtb_walker_cache.overall_miss_latency::total     91979000                       # number of overall miss cycles
+system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker        21945                       # number of ReadReq accesses(hits+misses)
+system.cpu.dtb_walker_cache.ReadReq_accesses::total        21945                       # number of ReadReq accesses(hits+misses)
+system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker        21945                       # number of demand (read+write) accesses
+system.cpu.dtb_walker_cache.demand_accesses::total        21945                       # number of demand (read+write) accesses
+system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker        21945                       # number of overall (read+write) accesses
+system.cpu.dtb_walker_cache.overall_accesses::total        21945                       # number of overall (read+write) accesses
+system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker     0.394441                       # miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.ReadReq_miss_rate::total     0.394441                       # miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker     0.394441                       # miss rate for demand accesses
+system.cpu.dtb_walker_cache.demand_miss_rate::total     0.394441                       # miss rate for demand accesses
+system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker     0.394441                       # miss rate for overall accesses
+system.cpu.dtb_walker_cache.overall_miss_rate::total     0.394441                       # miss rate for overall accesses
+system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10626.039741                       # average ReadReq miss latency
+system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10626.039741                       # average ReadReq miss latency
+system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10626.039741                       # average overall miss latency
+system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10626.039741                       # average overall miss latency
+system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10626.039741                       # average overall miss latency
+system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10626.039741                       # average overall miss latency
 system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dtb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dtb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
@@ -842,146 +842,170 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dtb_walker_cache.fast_writes             0                       # number of fast writes performed
 system.cpu.dtb_walker_cache.cache_copies            0                       # number of cache copies performed
-system.cpu.dtb_walker_cache.writebacks::writebacks         3054                       # number of writebacks
-system.cpu.dtb_walker_cache.writebacks::total         3054                       # number of writebacks
-system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker         8700                       # number of ReadReq MSHR misses
-system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total         8700                       # number of ReadReq MSHR misses
-system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker         8700                       # number of demand (read+write) MSHR misses
-system.cpu.dtb_walker_cache.demand_mshr_misses::total         8700                       # number of demand (read+write) MSHR misses
-system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker         8700                       # number of overall MSHR misses
-system.cpu.dtb_walker_cache.overall_mshr_misses::total         8700                       # number of overall MSHR misses
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker     74944500                       # number of ReadReq MSHR miss cycles
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total     74944500                       # number of ReadReq MSHR miss cycles
-system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker     74944500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total     74944500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker     74944500                       # number of overall MSHR miss cycles
-system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total     74944500                       # number of overall MSHR miss cycles
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.395742                       # mshr miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total     0.395742                       # mshr miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker     0.395742                       # mshr miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total     0.395742                       # mshr miss rate for demand accesses
-system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker     0.395742                       # mshr miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total     0.395742                       # mshr miss rate for overall accesses
-system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker  8614.310345                       # average ReadReq mshr miss latency
-system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total  8614.310345                       # average ReadReq mshr miss latency
-system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker  8614.310345                       # average overall mshr miss latency
-system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total  8614.310345                       # average overall mshr miss latency
-system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker  8614.310345                       # average overall mshr miss latency
-system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total  8614.310345                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.writebacks::writebacks         2980                       # number of writebacks
+system.cpu.dtb_walker_cache.writebacks::total         2980                       # number of writebacks
+system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker         8656                       # number of ReadReq MSHR misses
+system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total         8656                       # number of ReadReq MSHR misses
+system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker         8656                       # number of demand (read+write) MSHR misses
+system.cpu.dtb_walker_cache.demand_mshr_misses::total         8656                       # number of demand (read+write) MSHR misses
+system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker         8656                       # number of overall MSHR misses
+system.cpu.dtb_walker_cache.overall_mshr_misses::total         8656                       # number of overall MSHR misses
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker     74666500                       # number of ReadReq MSHR miss cycles
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total     74666500                       # number of ReadReq MSHR miss cycles
+system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker     74666500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total     74666500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker     74666500                       # number of overall MSHR miss cycles
+system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total     74666500                       # number of overall MSHR miss cycles
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.394441                       # mshr miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total     0.394441                       # mshr miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker     0.394441                       # mshr miss rate for demand accesses
+system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total     0.394441                       # mshr miss rate for demand accesses
+system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker     0.394441                       # mshr miss rate for overall accesses
+system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total     0.394441                       # mshr miss rate for overall accesses
+system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker  8625.981978                       # average ReadReq mshr miss latency
+system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total  8625.981978                       # average ReadReq mshr miss latency
+system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker  8625.981978                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total  8625.981978                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker  8625.981978                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total  8625.981978                       # average overall mshr miss latency
 system.cpu.dtb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements           1620643                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.997078                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            20036158                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           1621155                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             12.359187                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.replacements           1620883                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.997130                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            20027756                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           1621395                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             12.352176                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle          51171250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.997078                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.997130                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.999994                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.999994                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          101                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          329                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2           81                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           97                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          312                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          102                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          88250512                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         88250512                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     11993410                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        11993410                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      8040535                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        8040535                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data      20033945                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         20033945                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     20033945                       # number of overall hits
-system.cpu.dcache.overall_hits::total        20033945                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      1308416                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       1308416                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       314973                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       314973                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data      1623389                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        1623389                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      1623389                       # number of overall misses
-system.cpu.dcache.overall_misses::total       1623389                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  18840132304                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  18840132304                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  10814294936                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  10814294936                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  29654427240                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  29654427240                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  29654427240                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  29654427240                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     13301826                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     13301826                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data      8355508                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total      8355508                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     21657334                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     21657334                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     21657334                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     21657334                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.098364                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.098364                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.037696                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.037696                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.074958                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.074958                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.074958                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.074958                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14399.191315                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 14399.191315                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34334.037952                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 34334.037952                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 18266.987912                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 18266.987912                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 18266.987912                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 18266.987912                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.tags.tag_accesses          88256675                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         88256675                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     11935486                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        11935486                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      8030839                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        8030839                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data        59261                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total         59261                       # number of SoftPFReq hits
+system.cpu.dcache.demand_hits::cpu.data      19966325                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         19966325                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     20025586                       # number of overall hits
+system.cpu.dcache.overall_hits::total        20025586                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       906294                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        906294                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       324617                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       324617                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data       402313                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total       402313                       # number of SoftPFReq misses
+system.cpu.dcache.demand_misses::cpu.data      1230911                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        1230911                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      1633224                       # number of overall misses
+system.cpu.dcache.overall_misses::total       1633224                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  12712957750                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  12712957750                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  11341720828                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  11341720828                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  24054678578                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  24054678578                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  24054678578                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  24054678578                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     12841780                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     12841780                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data      8355456                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total      8355456                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data       461574                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total       461574                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     21197236                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     21197236                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     21658810                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     21658810                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.070574                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.070574                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.038851                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.038851                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.871611                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.871611                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.058069                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.058069                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.075407                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.075407                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14027.410255                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 14027.410255                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34938.776552                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 34938.776552                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 19542.175330                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 19542.175330                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 14728.340128                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 14728.340128                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs         7655                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                73                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs   104.863014                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      1537613                       # number of writebacks
-system.cpu.dcache.writebacks::total           1537613                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1308416                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      1308416                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       314973                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       314973                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      1623389                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      1623389                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      1623389                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      1623389                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  16214330696                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  16214330696                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  10132215064                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  10132215064                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  26346545760                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  26346545760                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  26346545760                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  26346545760                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data  94214672500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total  94214672500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2537738000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2537738000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  96752410500                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total  96752410500                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.098364                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.098364                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.037696                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.037696                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.074958                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.074958                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.074958                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.074958                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12392.335997                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12392.335997                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32168.519410                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32168.519410                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16229.348456                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 16229.348456                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16229.348456                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 16229.348456                       # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks      1537682                       # number of writebacks
+system.cpu.dcache.writebacks::total           1537682                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data          287                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total          287                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data         9297                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total         9297                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data         9584                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total         9584                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data         9584                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total         9584                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       906007                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       906007                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       315320                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       315320                       # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data       402278                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total       402278                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      1221327                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      1221327                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      1623605                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      1623605                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  10893569500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  10893569500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  10209797624                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  10209797624                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   5351981750                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   5351981750                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  21103367124                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  21103367124                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  26455348874                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  26455348874                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data  94214672000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total  94214672000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2537257000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2537257000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  96751929000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total  96751929000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.070552                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.070552                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.037738                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.037738                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.871535                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.871535                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.057617                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.057617                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.074963                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.074963                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12023.714497                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12023.714497                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32379.162831                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32379.162831                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13304.187030                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13304.187030                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17279.047400                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 17279.047400                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16294.202638                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 16294.202638                       # average overall mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
@@ -989,184 +1013,185 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.throughput                49146383                       # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq        2695227                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       2694701                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteReq         13777                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteResp        13777                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      1541371                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq         2213                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp         2213                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       359480                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       312780                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1583085                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      5973901                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side         7764                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side        18139                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           7582889                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     50658304                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    203802165                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       222976                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       604096                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total      255287541                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus         255266421                       # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus       314240                       # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy     3830515500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.throughput                49844829                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq        2698695                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       2698173                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteReq         13773                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteResp        13773                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback      1541433                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteInvalidateReq        46720                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq         2183                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp         2183                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       313150                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       313150                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1590153                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      5974271                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side         8035                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side        18003                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           7590462                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     50884480                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    203815525                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       233856                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       598208                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total      255532069                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus         255511461                       # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus      3309120                       # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy     3832514500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy       495000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.occupancy       483000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy    1189702505                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy    1195084369                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    3051756740                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    3051993102                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy       6421000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.occupancy       6572250                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy      13050250                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy      12984250                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.cpu.l2cache.tags.replacements            86651                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        64733.611120                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            3487942                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           151340                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            23.047060                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements            87211                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        64746.136544                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            3491181                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           151954                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            22.975249                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 50209.763854                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker     0.027833                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.141473                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  3434.458363                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 11089.219598                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.766140                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::writebacks 50332.685507                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker     0.006414                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.141265                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  3220.709839                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 11192.593518                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.768016                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000000                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000002                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.052406                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.169208                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.987757                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        64689                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           26                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          100                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2880                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         4787                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        56896                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.987076                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         32180689                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        32180689                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker         6384                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.itb.walker         2775                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.inst       778641                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data      1279470                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        2067270                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks      1541371                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      1541371                       # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data          305                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total          305                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       199944                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       199944                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.dtb.walker         6384                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.itb.walker         2775                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.inst       778641                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      1479414                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         2267214                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.dtb.walker         6384                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.itb.walker         2775                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.inst       778641                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      1479414                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        2267214                       # number of overall hits
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.049144                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.170785                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.987948                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        64743                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           51                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1           88                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2897                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         4651                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        57056                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.987900                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         32212608                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        32212608                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker         6366                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.itb.walker         2878                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.inst       782107                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data      1278785                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total        2070136                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks      1541433                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total      1541433                       # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data          314                       # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total          314                       # number of UpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       199468                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       199468                       # number of ReadExReq hits
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+system.cpu.l2cache.demand_hits::total         2269604                       # number of demand (read+write) hits
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+system.cpu.l2cache.overall_hits::cpu.inst       782107                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data      1478253                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        2269604                       # number of overall hits
 system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker            1                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_misses::cpu.itb.walker            5                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.inst        12895                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data        28198                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total        41099                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data         1394                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total         1394                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       112812                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       112812                       # number of ReadExReq misses
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 system.cpu.l2cache.demand_misses::cpu.dtb.walker            1                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::cpu.itb.walker            5                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.inst        12895                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       141010                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        153911                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.inst        12963                       # number of demand (read+write) misses
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 system.cpu.l2cache.overall_misses::cpu.dtb.walker            1                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.itb.walker            5                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.inst        12895                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       141010                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       153911                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker        89250                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker       365000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    942725495                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data   2110465196                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total   3053644941                       # number of ReadReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data     16120870                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total     16120870                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   7781341940                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   7781341940                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker        89250                       # number of demand (read+write) miss cycles
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-system.cpu.l2cache.demand_miss_latency::cpu.data   9891807136                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  10834986881                       # number of demand (read+write) miss cycles
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-system.cpu.l2cache.overall_miss_latency::cpu.data   9891807136                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  10834986881                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker         6385                       # number of ReadReq accesses(hits+misses)
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-system.cpu.l2cache.ReadReq_accesses::total      2108369                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks      1541371                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total      1541371                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data         1699                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total         1699                       # number of UpgradeReq accesses(hits+misses)
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-system.cpu.l2cache.overall_accesses::cpu.dtb.walker         6385                       # number of overall (read+write) accesses
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 system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.000157                       # miss rate for ReadReq accesses
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 system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.000157                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.001799                       # miss rate for demand accesses
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 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1175,90 +1200,90 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        79998                       # number of writebacks
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 system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker            1                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker            5                       # number of ReadReq MSHR misses
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 system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker            1                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            5                       # number of demand (read+write) MSHR misses
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 system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker            1                       # number of overall MSHR misses
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 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000157                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.001799                       # mshr miss rate for ReadReq accesses
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-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.019493                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.820483                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.820483                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.360703                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.360703                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.001734                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.016304                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.021907                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.019705                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.808420                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.808420                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.363017                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.363017                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000157                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.001799                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.016291                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.087020                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.063570                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.001734                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.016304                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.087820                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.064039                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000157                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.001799                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.016291                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.087020                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.063570                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker        76250                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker        60300                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60579.682435                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62319.324207                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61773.596900                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10666.338594                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10666.338594                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56470.916746                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56470.916746                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker        76250                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker        60300                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60579.682435                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57640.432338                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57886.896447                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker        76250                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker        60300                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60579.682435                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57640.432338                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57886.896447                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.001734                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.016304                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.087820                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.064039                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker        48750                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker        57550                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60525.341356                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62479.252496                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61869.631828                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10009.679245                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10009.679245                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56692.990024                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56692.990024                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker        48750                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker        57550                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60525.341356                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57857.487595                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58080.123880                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker        48750                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker        57550                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60525.341356                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57857.487595                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58080.123880                       # average overall mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
diff --git a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt
index 8539a1890..403e6b21a 100644
--- a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt
+++ b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.200409                       # Nu
 sim_ticks                                200409284500                       # Number of ticks simulated
 final_tick                               4321214250500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                               14275836                       # Simulator instruction rate (inst/s)
-host_op_rate                                 14275831                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             5462126987                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 513712                       # Number of bytes of host memory used
-host_seconds                                    36.69                       # Real time elapsed on the host
+host_inst_rate                               23274047                       # Simulator instruction rate (inst/s)
+host_op_rate                                 23274036                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             8904961694                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 483300                       # Number of bytes of host memory used
+host_seconds                                    22.51                       # Real time elapsed on the host
 sim_insts                                   523790075                       # Number of instructions simulated
 sim_ops                                     523790075                       # Number of ops (including micro ops) simulated
 testsys.voltage_domain.voltage                      1                       # Voltage in Volts
@@ -114,10 +114,10 @@ testsys.cpu.not_idle_fraction                0.050555                       # Pe
 testsys.cpu.idle_fraction                    0.949445                       # Percentage of idle cycles
 testsys.cpu.Branches                          2929848                       # Number of branches fetched
 testsys.cpu.op_class::No_OpClass               712819      3.52%      3.52% # Class of executed instruction
-testsys.cpu.op_class::IntAlu                 12147340     59.95%     63.47% # Class of executed instruction
+testsys.cpu.op_class::IntAlu                 12147338     59.95%     63.47% # Class of executed instruction
 testsys.cpu.op_class::IntMult                   21654      0.11%     63.58% # Class of executed instruction
 testsys.cpu.op_class::IntDiv                        0      0.00%     63.58% # Class of executed instruction
-testsys.cpu.op_class::FloatAdd                   4653      0.02%     63.60% # Class of executed instruction
+testsys.cpu.op_class::FloatAdd                   4655      0.02%     63.60% # Class of executed instruction
 testsys.cpu.op_class::FloatCmp                      1      0.00%     63.60% # Class of executed instruction
 testsys.cpu.op_class::FloatCvt                      0      0.00%     63.60% # Class of executed instruction
 testsys.cpu.op_class::FloatMult                     0      0.00%     63.60% # Class of executed instruction
@@ -372,10 +372,10 @@ drivesys.cpu.not_idle_fraction               0.023766                       # Pe
 drivesys.cpu.idle_fraction                   0.976234                       # Percentage of idle cycles
 drivesys.cpu.Branches                         2793313                       # Number of branches fetched
 drivesys.cpu.op_class::No_OpClass              623554      3.27%      3.27% # Class of executed instruction
-drivesys.cpu.op_class::IntAlu                11538630     60.57%     63.84% # Class of executed instruction
+drivesys.cpu.op_class::IntAlu                11538627     60.57%     63.84% # Class of executed instruction
 drivesys.cpu.op_class::IntMult                  20663      0.11%     63.95% # Class of executed instruction
 drivesys.cpu.op_class::IntDiv                       0      0.00%     63.95% # Class of executed instruction
-drivesys.cpu.op_class::FloatAdd                   138      0.00%     63.95% # Class of executed instruction
+drivesys.cpu.op_class::FloatAdd                   141      0.00%     63.95% # Class of executed instruction
 drivesys.cpu.op_class::FloatCmp                     0      0.00%     63.95% # Class of executed instruction
 drivesys.cpu.op_class::FloatCvt                     0      0.00%     63.95% # Class of executed instruction
 drivesys.cpu.op_class::FloatMult                    0      0.00%     63.95% # Class of executed instruction
@@ -525,11 +525,11 @@ sim_seconds                                  0.000407                       # Nu
 sim_ticks                                   407341500                       # Number of ticks simulated
 final_tick                               4321621592000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                             7312019890                       # Simulator instruction rate (inst/s)
-host_op_rate                               7310591323                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             5683411932                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 513712                       # Number of bytes of host memory used
-host_seconds                                     0.07                       # Real time elapsed on the host
+host_inst_rate                            11799945954                       # Simulator instruction rate (inst/s)
+host_op_rate                              11797124974                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             9171074905                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 483300                       # Number of bytes of host memory used
+host_seconds                                     0.04                       # Real time elapsed on the host
 sim_insts                                   523862353                       # Number of instructions simulated
 sim_ops                                     523862353                       # Number of ops (including micro ops) simulated
 testsys.voltage_domain.voltage                      1                       # Voltage in Volts
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt
index 1f269f774..f7bb9a203 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000021                       # Number of seconds simulated
-sim_ticks                                    21025000                       # Number of ticks simulated
-final_tick                                   21025000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                    20537500                       # Number of ticks simulated
+final_tick                                   20537500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  63804                       # Simulator instruction rate (inst/s)
-host_op_rate                                    63793                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              210460029                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 221600                       # Number of bytes of host memory used
-host_seconds                                     0.10                       # Real time elapsed on the host
+host_inst_rate                                  46749                       # Simulator instruction rate (inst/s)
+host_op_rate                                    46745                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              150649735                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 236424                       # Number of bytes of host memory used
+host_seconds                                     0.14                       # Real time elapsed on the host
 sim_insts                                        6372                       # Number of instructions simulated
 sim_ops                                          6372                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -21,40 +21,40 @@ system.physmem.bytes_inst_read::total           20032                       # Nu
 system.physmem.num_reads::cpu.inst                313                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data                174                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                   487                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst            952770511                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            529655172                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              1482425684                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst       952770511                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          952770511                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           952770511                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           529655172                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             1482425684                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                           488                       # Number of read requests accepted
+system.physmem.bw_read::cpu.inst            975386488                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            542227632                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              1517614121                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst       975386488                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          975386488                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           975386488                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           542227632                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             1517614121                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                           487                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
-system.physmem.readBursts                         488                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                         487                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                    31232                       # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM                    31168                       # Total number of bytes read from DRAM
 system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
 system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                     31232                       # Total read bytes from the system interface side
+system.physmem.bytesReadSys                     31168                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
 system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
 system.physmem.perBankRdBursts::0                  69                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                  34                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                  33                       # Per bank write bursts
 system.physmem.perBankRdBursts::2                  32                       # Per bank write bursts
 system.physmem.perBankRdBursts::3                  47                       # Per bank write bursts
-system.physmem.perBankRdBursts::4                  43                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                  21                       # Per bank write bursts
+system.physmem.perBankRdBursts::4                  42                       # Per bank write bursts
+system.physmem.perBankRdBursts::5                  20                       # Per bank write bursts
 system.physmem.perBankRdBursts::6                   1                       # Per bank write bursts
 system.physmem.perBankRdBursts::7                   3                       # Per bank write bursts
 system.physmem.perBankRdBursts::8                   0                       # Per bank write bursts
 system.physmem.perBankRdBursts::9                   1                       # Per bank write bursts
 system.physmem.perBankRdBursts::10                 23                       # Per bank write bursts
-system.physmem.perBankRdBursts::11                 24                       # Per bank write bursts
+system.physmem.perBankRdBursts::11                 25                       # Per bank write bursts
 system.physmem.perBankRdBursts::12                 14                       # Per bank write bursts
-system.physmem.perBankRdBursts::13                119                       # Per bank write bursts
+system.physmem.perBankRdBursts::13                120                       # Per bank write bursts
 system.physmem.perBankRdBursts::14                 45                       # Per bank write bursts
 system.physmem.perBankRdBursts::15                 12                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
@@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                        20992000                       # Total gap between requests
+system.physmem.totGap                        20412000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                     488                       # Read request sizes (log2)
+system.physmem.readPktSize::6                     487                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -90,11 +90,11 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                       274                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       144                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                       272                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       142                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::2                        52                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                        13                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                         5                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                        14                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                         7                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
@@ -186,92 +186,92 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples           79                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      351.594937                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     222.888418                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     329.838248                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127             22     27.85%     27.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255           18     22.78%     50.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383           11     13.92%     64.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511            8     10.13%     74.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639            5      6.33%     81.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767            1      1.27%     82.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895            2      2.53%     84.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023            2      2.53%     87.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151           10     12.66%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total             79                       # Bytes accessed per row activation
-system.physmem.totQLat                        4169250                       # Total ticks spent queuing
-system.physmem.totMemAccLat                  13319250                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                      2440000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        8543.55                       # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples           82                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      341.853659                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     204.819475                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     342.253502                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127             28     34.15%     34.15% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255           17     20.73%     54.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383            9     10.98%     65.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511            8      9.76%     75.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639            4      4.88%     80.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767            1      1.22%     81.71% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895            1      1.22%     82.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023            3      3.66%     86.59% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151           11     13.41%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total             82                       # Bytes accessed per row activation
+system.physmem.totQLat                        4551750                       # Total ticks spent queuing
+system.physmem.totMemAccLat                  13683000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                      2435000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        9346.51                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  27293.55                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                        1485.47                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  28096.51                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                        1517.61                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                     1485.47                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                     1517.61                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                          11.61                       # Data bus utilization in percentage
-system.physmem.busUtilRead                      11.61                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                          11.86                       # Data bus utilization in percentage
+system.physmem.busUtilRead                      11.86                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.73                       # Average read queue length when enqueuing
+system.physmem.avgRdQLen                         1.76                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                        394                       # Number of row buffer hits during reads
+system.physmem.readRowHits                        390                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   80.74                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   80.08                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                        43016.39                       # Average gap between requests
-system.physmem.pageHitRate                      80.74                       # Row buffer hit rate, read and write combined
+system.physmem.avgGap                        41913.76                       # Average gap between requests
+system.physmem.pageHitRate                      80.08                       # Row buffer hit rate, read and write combined
 system.physmem.memoryStateTime::IDLE            22000                       # Time in different power states
 system.physmem.memoryStateTime::REF            520000                       # Time in different power states
 system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT          15304250                       # Time in different power states
+system.physmem.memoryStateTime::ACT          15339250                       # Time in different power states
 system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.membus.throughput                   1482425684                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq                 416                       # Transaction distribution
+system.membus.throughput                   1517614121                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq                 415                       # Transaction distribution
 system.membus.trans_dist::ReadResp                415                       # Transaction distribution
 system.membus.trans_dist::ReadExReq                72                       # Transaction distribution
 system.membus.trans_dist::ReadExResp               72                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port          975                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                    975                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port          974                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                    974                       # Packet count per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        31168                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size::total               31168                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.data_through_bus                  31168                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy              617000                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               2.9                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            4554750                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization             21.7                       # Layer utilization (%)
+system.membus.reqLayer0.occupancy              610000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               3.0                       # Layer utilization (%)
+system.membus.respLayer1.occupancy            4554500                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization             22.2                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.branchPred.lookups                    2922                       # Number of BP lookups
-system.cpu.branchPred.condPredicted              1714                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect               512                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups                 2236                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                     763                       # Number of BTB hits
+system.cpu.branchPred.lookups                    2806                       # Number of BP lookups
+system.cpu.branchPred.condPredicted              1662                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect               479                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups                 2112                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                     686                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             34.123435                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                     417                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect                 74                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             32.481061                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                     395                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect                 30                       # Number of incorrect RAS predictions.
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                         2080                       # DTB read hits
-system.cpu.dtb.read_misses                         47                       # DTB read misses
+system.cpu.dtb.read_hits                         2085                       # DTB read hits
+system.cpu.dtb.read_misses                         55                       # DTB read misses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                     2127                       # DTB read accesses
-system.cpu.dtb.write_hits                        1064                       # DTB write hits
-system.cpu.dtb.write_misses                        31                       # DTB write misses
+system.cpu.dtb.read_accesses                     2140                       # DTB read accesses
+system.cpu.dtb.write_hits                        1069                       # DTB write hits
+system.cpu.dtb.write_misses                        30                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses                    1095                       # DTB write accesses
-system.cpu.dtb.data_hits                         3144                       # DTB hits
-system.cpu.dtb.data_misses                         78                       # DTB misses
+system.cpu.dtb.write_accesses                    1099                       # DTB write accesses
+system.cpu.dtb.data_hits                         3154                       # DTB hits
+system.cpu.dtb.data_misses                         85                       # DTB misses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                     3222                       # DTB accesses
-system.cpu.itb.fetch_hits                        2403                       # ITB hits
-system.cpu.itb.fetch_misses                        39                       # ITB misses
+system.cpu.dtb.data_accesses                     3239                       # DTB accesses
+system.cpu.itb.fetch_hits                        2196                       # ITB hits
+system.cpu.itb.fetch_misses                        38                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                    2442                       # ITB accesses
+system.cpu.itb.fetch_accesses                    2234                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -285,238 +285,237 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                   17                       # Number of system calls
-system.cpu.numCycles                            42051                       # number of cpu cycles simulated
+system.cpu.numCycles                            41076                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles               8528                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                          16754                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                        2922                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches               1180                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                          2995                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                    1927                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles                   1100                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.icacheStallCycles               8744                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                          16221                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                        2806                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches               1081                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                          4165                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                    1040                       # Number of cycles fetch has spent squashing
 system.cpu.fetch.MiscStallCycles                   25                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles           747                       # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines                      2403                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                   389                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples              14718                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.138334                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.533627                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.PendingTrapStallCycles           801                       # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines                      2196                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                   338                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples              14255                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.137917                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.547719                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                    11723     79.65%     79.65% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                      324      2.20%     81.85% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                      234      1.59%     83.44% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                      214      1.45%     84.90% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                      255      1.73%     86.63% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                      243      1.65%     88.28% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                      264      1.79%     90.07% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                      187      1.27%     91.34% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                     1274      8.66%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                    11405     80.01%     80.01% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                      289      2.03%     82.03% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                      215      1.51%     83.54% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                      201      1.41%     84.95% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                      243      1.70%     86.66% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                      210      1.47%     88.13% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                      240      1.68%     89.81% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                      179      1.26%     91.07% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                     1273      8.93%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total                14718                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.069487                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.398421                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                     9297                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles                  1311                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                      2827                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles                    41                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                   1242                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved                  247                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                    86                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts                  15491                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                   223                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                   1242                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                     9496                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                     220                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles            554                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                      2672                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles                   534                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts                  14802                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                    11                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                      9                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                      4                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                    481                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands               11114                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups                 18470                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups            18461                       # Number of integer rename lookups
+system.cpu.fetch.rateDist::total                14255                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.068312                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.394902                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                     8821                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles                  2387                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                      2410                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles                   194                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                    443                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved                  229                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                    82                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts                  14785                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                   224                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                    443                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                     8987                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                    1032                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles            429                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                      2422                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles                   942                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts                  14195                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                    24                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                      7                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                     42                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents                    850                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands               10723                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups                 17814                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups            17805                       # Number of integer rename lookups
 system.cpu.rename.fp_rename_lookups                 8                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps                  4570                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                     6544                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts                 31                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts             25                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                       484                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads                 2790                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores                1358                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads                 4                       # Number of conflicting loads.
+system.cpu.rename.UndoneMaps                     6153                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts                 32                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts             24                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                       504                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads                 2660                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores                1309                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads                 5                       # Number of conflicting loads.
 system.cpu.memDep0.conflictingStores                0                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                      13092                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                  29                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                     10822                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued                61                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined            6316                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined         3704                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved             12                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples         14718                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.735290                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.419888                       # Number of insts issued each cycle
+system.cpu.iq.iqInstsAdded                      12882                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                  28                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                     10718                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued                21                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined            6142                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined         3483                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved             11                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples         14255                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.751877                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.485144                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0               10506     71.38%     71.38% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1                1362      9.25%     80.64% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2                 966      6.56%     87.20% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3                 797      5.42%     92.61% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4                 583      3.96%     96.58% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5                 288      1.96%     98.53% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6                 161      1.09%     99.63% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7                  41      0.28%     99.90% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8                  14      0.10%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0               10249     71.90%     71.90% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1                1278      8.97%     80.86% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2                 900      6.31%     87.18% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3                 686      4.81%     91.99% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4                 522      3.66%     95.65% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                 330      2.31%     97.97% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6                 212      1.49%     99.45% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7                  52      0.36%     99.82% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8                  26      0.18%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total           14718                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total           14255                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                      18     15.38%     15.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%     15.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     15.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     15.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     15.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     15.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     15.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     15.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     15.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     15.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     15.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     15.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     15.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     15.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     15.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     15.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     15.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     15.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     15.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     15.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     15.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     15.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     15.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     15.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     15.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     15.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     15.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     15.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     15.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                     61     52.14%     67.52% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                    38     32.48%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                      30     20.69%     20.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%     20.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     20.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     20.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     20.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     20.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     20.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     20.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     20.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     20.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     20.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     20.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     20.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     20.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     20.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     20.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     20.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     20.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     20.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     20.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     20.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     20.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     20.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     20.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     20.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     20.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     20.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     20.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     20.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                     73     50.34%     71.03% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                    42     28.97%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 2      0.02%      0.02% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu                  7283     67.30%     67.32% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                    1      0.01%     67.33% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     67.33% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   2      0.02%     67.34% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     67.34% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     67.34% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     67.34% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     67.34% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     67.34% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     67.34% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     67.34% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     67.34% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     67.34% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     67.34% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     67.34% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     67.34% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     67.34% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     67.34% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     67.34% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     67.34% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     67.34% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     67.34% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     67.34% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     67.34% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     67.34% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     67.34% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.34% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.34% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.34% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead                 2401     22.19%     89.53% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite                1133     10.47%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu                  7258     67.72%     67.74% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                    1      0.01%     67.75% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     67.75% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   2      0.02%     67.76% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     67.76% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     67.76% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     67.76% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     67.76% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     67.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     67.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     67.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     67.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     67.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     67.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     67.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     67.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     67.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     67.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     67.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     67.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     67.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     67.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     67.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     67.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     67.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     67.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.76% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead                 2331     21.75%     89.51% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite                1124     10.49%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total                  10822                       # Type of FU issued
-system.cpu.iq.rate                           0.257354                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                         117                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.010811                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads              36519                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes             19441                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses         9646                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total                  10718                       # Type of FU issued
+system.cpu.iq.rate                           0.260931                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                         145                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.013529                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads              35836                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes             19060                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses         9783                       # Number of integer instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_reads                  21                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_writes                 10                       # Number of floating instruction queue writes
 system.cpu.iq.fp_inst_queue_wakeup_accesses           10                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses                  10926                       # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses                  10850                       # Number of integer alu accesses
 system.cpu.iq.fp_alu_accesses                      11                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads               74                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads               73                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads         1607                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses            3                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation           16                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores          493                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads         1477                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses            0                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation           20                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores          444                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu.iew.lsq.thread0.rescheduledLoads            1                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked           138                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.cacheBlocked            70                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                   1242                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                     105                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                    37                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts               13210                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts               174                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts                  2790                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts                 1358                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts                 29                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                      2                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                    36                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents             16                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect            123                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect          383                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts                  506                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts                 10117                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts                  2138                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts               705                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                    443                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                    1002                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                    13                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts               12999                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts               102                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts                  2660                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts                 1309                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts                 28                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                      1                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                    10                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents             20                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect             79                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect          391                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts                  470                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts                 10224                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts                  2143                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts               494                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                            89                       # number of nop insts executed
-system.cpu.iew.exec_refs                         3235                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                     1594                       # Number of branches executed
-system.cpu.iew.exec_stores                       1097                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.240589                       # Inst execution rate
-system.cpu.iew.wb_sent                           9800                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                          9656                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                      5168                       # num instructions producing a value
-system.cpu.iew.wb_consumers                      7004                       # num instructions consuming a value
+system.cpu.iew.exec_refs                         3244                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                     1603                       # Number of branches executed
+system.cpu.iew.exec_stores                       1101                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.248904                       # Inst execution rate
+system.cpu.iew.wb_sent                           9953                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                          9793                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                      5300                       # num instructions producing a value
+system.cpu.iew.wb_consumers                      7279                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.229626                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.737864                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       0.238412                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.728122                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts            6822                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts            6609                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls              17                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts               431                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples        13476                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.474102                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.366169                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts               402                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples        13051                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.489541                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.404135                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0        10977     81.46%     81.46% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1         1202      8.92%     90.38% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2          500      3.71%     94.09% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3          222      1.65%     95.73% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4          141      1.05%     96.78% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5           79      0.59%     97.37% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6           99      0.73%     98.10% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7           80      0.59%     98.69% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8          176      1.31%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0        10600     81.22%     81.22% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1         1162      8.90%     90.12% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2          501      3.84%     93.96% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3          211      1.62%     95.58% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4          133      1.02%     96.60% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5           75      0.57%     97.17% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6           89      0.68%     97.85% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7           89      0.68%     98.54% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8          191      1.46%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total        13476                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total        13051                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts                 6389                       # Number of instructions committed
 system.cpu.commit.committedOps                   6389                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -562,94 +561,94 @@ system.cpu.commit.op_class_0::MemWrite            865     13.54%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total              6389                       # Class of committed instruction
-system.cpu.commit.bw_lim_events                   176                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events                   191                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                        26160                       # The number of ROB reads
-system.cpu.rob.rob_writes                       27673                       # The number of ROB writes
-system.cpu.timesIdled                             280                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           27333                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads                        25507                       # The number of ROB reads
+system.cpu.rob.rob_writes                       27214                       # The number of ROB writes
+system.cpu.timesIdled                             272                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           26821                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                        6372                       # Number of Instructions Simulated
 system.cpu.committedOps                          6372                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               6.599341                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         6.599341                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.151530                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.151530                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                    12844                       # number of integer regfile reads
-system.cpu.int_regfile_writes                    7306                       # number of integer regfile writes
+system.cpu.cpi                               6.446328                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         6.446328                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.155127                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.155127                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                    12991                       # number of integer regfile reads
+system.cpu.int_regfile_writes                    7455                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                         8                       # number of floating regfile reads
 system.cpu.fp_regfile_writes                        2                       # number of floating regfile writes
 system.cpu.misc_regfile_reads                       1                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
-system.cpu.toL2Bus.throughput              1485469679                       # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq            417                       # Transaction distribution
+system.cpu.toL2Bus.throughput              1520730371                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq            416                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadResp           416                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq           72                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp           72                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          629                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          628                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          348                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total               977                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total               976                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        20096                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side        11136                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.tot_pkt_size::total          31232                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.data_through_bus             31232                       # Total data (bytes)
 system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy         244500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.occupancy         244000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          1.2                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy        529000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          2.5                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy        276750                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy        528500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization          2.6                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy        276000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          1.3                       # Layer utilization (%)
 system.cpu.icache.tags.replacements                 0                       # number of replacements
-system.cpu.icache.tags.tagsinuse           159.493349                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs                1913                       # Total number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse           158.374396                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs                1718                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs               314                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs              6.092357                       # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs              5.471338                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   159.493349                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.077878                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.077878                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst   158.374396                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.077331                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.077331                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          314                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          144                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          170                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          150                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          164                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.153320                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses              5120                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses             5120                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst         1913                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total            1913                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst          1913                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total             1913                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst         1913                       # number of overall hits
-system.cpu.icache.overall_hits::total            1913                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst          490                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total           490                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst          490                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total            490                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst          490                       # number of overall misses
-system.cpu.icache.overall_misses::total           490                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     31404750                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     31404750                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     31404750                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     31404750                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     31404750                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     31404750                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst         2403                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total         2403                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst         2403                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total         2403                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst         2403                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total         2403                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.203912                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.203912                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.203912                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.203912                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.203912                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.203912                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 64091.326531                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 64091.326531                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 64091.326531                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 64091.326531                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 64091.326531                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 64091.326531                       # average overall miss latency
+system.cpu.icache.tags.tag_accesses              4706                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses             4706                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst         1718                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total            1718                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst          1718                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total             1718                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst         1718                       # number of overall hits
+system.cpu.icache.overall_hits::total            1718                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          478                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           478                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          478                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            478                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          478                       # number of overall misses
+system.cpu.icache.overall_misses::total           478                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     31723500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     31723500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     31723500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     31723500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     31723500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     31723500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst         2196                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total         2196                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst         2196                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total         2196                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst         2196                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total         2196                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.217668                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.217668                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.217668                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.217668                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.217668                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.217668                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66367.154812                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 66367.154812                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 66367.154812                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 66367.154812                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 66367.154812                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 66367.154812                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -658,115 +657,115 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst          175                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total          175                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst          175                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total          175                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst          175                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total          175                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst          315                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total          315                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst          315                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total          315                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst          315                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total          315                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     22044500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     22044500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     22044500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     22044500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     22044500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     22044500                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.131086                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.131086                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.131086                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.131086                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.131086                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.131086                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69982.539683                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69982.539683                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69982.539683                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 69982.539683                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69982.539683                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 69982.539683                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst          164                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total          164                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst          164                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total          164                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst          164                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total          164                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          314                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          314                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          314                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          314                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          314                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total          314                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     22315500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     22315500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     22315500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     22315500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     22315500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     22315500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.142987                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.142987                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.142987                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.142987                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.142987                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.142987                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71068.471338                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71068.471338                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71068.471338                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 71068.471338                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71068.471338                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 71068.471338                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse          219.991091                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse          218.773509                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs                  1                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs              415                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs             0.002410                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   159.576725                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data    60.414366                       # Average occupied blocks per requestor
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-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          232                       # Occupied blocks per task id
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-system.cpu.l2cache.tags.tag_accesses             4399                       # Number of tag accesses
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-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     21718500                       # number of ReadReq miss cycles
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 system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.997955                       # miss rate for overall accesses
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-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76465.686275                       # average ReadReq miss latency
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-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74843.750000                       # average ReadExReq miss latency
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-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75794.540230                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 71530.225410                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69167.197452                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75794.540230                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 71530.225410                       # average overall miss latency
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+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77605.392157                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 72063.253012                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75121.527778                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75121.527778                       # average ReadExReq miss latency
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+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70257.188498                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76577.586207                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 72515.400411                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -775,130 +774,130 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          314                       # number of ReadReq MSHR misses
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 system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          102                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total          416                       # number of ReadReq MSHR misses
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 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           72                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total           72                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst          314                       # number of demand (read+write) MSHR misses
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 system.cpu.l2cache.demand_mshr_misses::cpu.data          174                       # number of demand (read+write) MSHR misses
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 system.cpu.l2cache.overall_mshr_misses::cpu.data          174                       # number of overall MSHR misses
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-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     17765000                       # number of ReadReq MSHR miss cycles
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 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.997602                       # mshr miss rate for ReadReq accesses
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 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
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-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.996825                       # mshr miss rate for demand accesses
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 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.997955                       # mshr miss rate for demand accesses
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 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.997955                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56576.433121                       # average ReadReq mshr miss latency
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-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62579.861111                       # average ReadExReq mshr miss latency
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-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63518.678161                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59051.741803                       # average overall mshr miss latency
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-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63518.678161                       # average overall mshr miss latency
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+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57645.367412                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64275.862069                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60014.373717                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.dcache.tags.replacements                 0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           107.281632                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs                2231                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse           107.148001                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs                2314                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs               174                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             12.821839                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             13.298851                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   107.281632                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.026192                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.026192                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data   107.148001                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.026159                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.026159                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          174                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           50                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          124                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           55                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          119                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024     0.042480                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses              5696                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses             5696                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data         1725                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total            1725                       # number of ReadReq hits
+system.cpu.dcache.tags.tag_accesses              5846                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses             5846                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data         1808                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total            1808                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data          506                       # number of WriteReq hits
 system.cpu.dcache.WriteReq_hits::total            506                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data          2231                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total             2231                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data         2231                       # number of overall hits
-system.cpu.dcache.overall_hits::total            2231                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data          171                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total           171                       # number of ReadReq misses
+system.cpu.dcache.demand_hits::cpu.data          2314                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total             2314                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data         2314                       # number of overall hits
+system.cpu.dcache.overall_hits::total            2314                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data          163                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total           163                       # number of ReadReq misses
 system.cpu.dcache.WriteReq_misses::cpu.data          359                       # number of WriteReq misses
 system.cpu.dcache.WriteReq_misses::total          359                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data          530                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total            530                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data          530                       # number of overall misses
-system.cpu.dcache.overall_misses::total           530                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data     11477000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     11477000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data     23139722                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total     23139722                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     34616722                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     34616722                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     34616722                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     34616722                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data         1896                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total         1896                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data          522                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total            522                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data          522                       # number of overall misses
+system.cpu.dcache.overall_misses::total           522                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data     11503750                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     11503750                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data     22566471                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total     22566471                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     34070221                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     34070221                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     34070221                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     34070221                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data         1971                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total         1971                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data          865                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total          865                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data         2761                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total         2761                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data         2761                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total         2761                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.090190                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.090190                       # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data         2836                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total         2836                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data         2836                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total         2836                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.082699                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.082699                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.415029                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_miss_rate::total     0.415029                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.191959                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.191959                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.191959                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.191959                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67116.959064                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 67116.959064                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64456.050139                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 64456.050139                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 65314.569811                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 65314.569811                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 65314.569811                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 65314.569811                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs         1676                       # number of cycles access was blocked
+system.cpu.dcache.demand_miss_rate::cpu.data     0.184062                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.184062                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.184062                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.184062                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70575.153374                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 70575.153374                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62859.250696                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 62859.250696                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 65268.622605                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 65268.622605                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 65268.622605                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 65268.622605                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs         1879                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                40                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                42                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    41.900000                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    44.738095                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data           69                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total           69                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data           61                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total           61                       # number of ReadReq MSHR hits
 system.cpu.dcache.WriteReq_mshr_hits::cpu.data          287                       # number of WriteReq MSHR hits
 system.cpu.dcache.WriteReq_mshr_hits::total          287                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data          356                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total          356                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data          356                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total          356                       # number of overall MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data          348                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total          348                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data          348                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total          348                       # number of overall MSHR hits
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data          102                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total          102                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data           72                       # number of WriteReq MSHR misses
@@ -907,30 +906,30 @@ system.cpu.dcache.demand_mshr_misses::cpu.data          174
 system.cpu.dcache.demand_mshr_misses::total          174                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data          174                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total          174                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      7909000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      7909000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      5463750                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      5463750                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data     13372750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total     13372750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data     13372750                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total     13372750                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.053797                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.053797                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      8025750                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      8025750                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      5483750                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      5483750                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data     13509500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total     13509500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data     13509500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total     13509500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.051750                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.051750                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.083237                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.083237                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.063021                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.063021                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.063021                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.063021                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77539.215686                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77539.215686                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75885.416667                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75885.416667                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76854.885057                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 76854.885057                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76854.885057                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 76854.885057                       # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.061354                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.061354                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.061354                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.061354                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78683.823529                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78683.823529                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76163.194444                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76163.194444                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77640.804598                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 77640.804598                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77640.804598                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 77640.804598                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt
index 477ffe800..a87953c0f 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,42 +1,42 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000012                       # Number of seconds simulated
-sim_ticks                                    11975500                       # Number of ticks simulated
-final_tick                                   11975500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                    11765500                       # Number of ticks simulated
+final_tick                                   11765500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  10130                       # Simulator instruction rate (inst/s)
-host_op_rate                                    10129                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               50814142                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 221260                       # Number of bytes of host memory used
-host_seconds                                     0.24                       # Real time elapsed on the host
+host_inst_rate                                  45706                       # Simulator instruction rate (inst/s)
+host_op_rate                                    45696                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              225189511                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 236100                       # Number of bytes of host memory used
+host_seconds                                     0.05                       # Real time elapsed on the host
 sim_insts                                        2387                       # Number of instructions simulated
 sim_ops                                          2387                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst             12032                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst             11968                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data              5440                       # Number of bytes read from this memory
-system.physmem.bytes_read::total                17472                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        12032                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           12032                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst                188                       # Number of read requests responded to by this memory
+system.physmem.bytes_read::total                17408                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        11968                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           11968                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst                187                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data                 85                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                   273                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst           1004717966                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            454260782                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              1458978748                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst      1004717966                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total         1004717966                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst          1004717966                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           454260782                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             1458978748                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                           273                       # Number of read requests accepted
+system.physmem.num_reads::total                   272                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst           1017211338                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            462368790                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              1479580128                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst      1017211338                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total         1017211338                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst          1017211338                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           462368790                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             1479580128                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                           272                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
-system.physmem.readBursts                         273                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                         272                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                    17472                       # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM                    17408                       # Total number of bytes read from DRAM
 system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
 system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                     17472                       # Total read bytes from the system interface side
+system.physmem.bytesReadSys                     17408                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
 system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
@@ -49,12 +49,12 @@ system.physmem.perBankRdBursts::4                  18                       # Pe
 system.physmem.perBankRdBursts::5                   0                       # Per bank write bursts
 system.physmem.perBankRdBursts::6                  24                       # Per bank write bursts
 system.physmem.perBankRdBursts::7                  37                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                  61                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                  60                       # Per bank write bursts
 system.physmem.perBankRdBursts::9                   2                       # Per bank write bursts
-system.physmem.perBankRdBursts::10                 14                       # Per bank write bursts
+system.physmem.perBankRdBursts::10                 15                       # Per bank write bursts
 system.physmem.perBankRdBursts::11                  9                       # Per bank write bursts
 system.physmem.perBankRdBursts::12                 17                       # Per bank write bursts
-system.physmem.perBankRdBursts::13                 51                       # Per bank write bursts
+system.physmem.perBankRdBursts::13                 50                       # Per bank write bursts
 system.physmem.perBankRdBursts::14                 12                       # Per bank write bursts
 system.physmem.perBankRdBursts::15                  1                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
@@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                        11886000                       # Total gap between requests
+system.physmem.totGap                        11676000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                     273                       # Read request sizes (log2)
+system.physmem.readPktSize::6                     272                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -90,11 +90,11 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                       158                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                        84                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        25                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                       156                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                        83                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        26                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         6                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
@@ -186,92 +186,92 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples           38                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      387.368421                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     224.223359                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     366.580725                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127             14     36.84%     36.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255            5     13.16%     50.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383            4     10.53%     60.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511            2      5.26%     65.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639            2      5.26%     71.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767            2      5.26%     76.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895            2      5.26%     81.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023            1      2.63%     84.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151            6     15.79%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total             38                       # Bytes accessed per row activation
-system.physmem.totQLat                        2067500                       # Total ticks spent queuing
-system.physmem.totMemAccLat                   7186250                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                      1365000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        7573.26                       # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples           39                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      379.076923                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     220.895953                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     363.044972                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127             13     33.33%     33.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255            7     17.95%     51.28% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383            3      7.69%     58.97% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511            3      7.69%     66.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639            2      5.13%     71.79% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767            3      7.69%     79.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895            1      2.56%     82.05% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023            1      2.56%     84.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151            6     15.38%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total             39                       # Bytes accessed per row activation
+system.physmem.totQLat                        1710500                       # Total ticks spent queuing
+system.physmem.totMemAccLat                   6810500                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                      1360000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        6288.60                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  26323.26                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                        1458.98                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  25038.60                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                        1479.58                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                     1458.98                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                     1479.58                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                          11.40                       # Data bus utilization in percentage
-system.physmem.busUtilRead                      11.40                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                          11.56                       # Data bus utilization in percentage
+system.physmem.busUtilRead                      11.56                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.70                       # Average read queue length when enqueuing
+system.physmem.avgRdQLen                         1.69                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                        225                       # Number of row buffer hits during reads
+system.physmem.readRowHits                        223                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   82.42                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   81.99                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                        43538.46                       # Average gap between requests
-system.physmem.pageHitRate                      82.42                       # Row buffer hit rate, read and write combined
+system.physmem.avgGap                        42926.47                       # Average gap between requests
+system.physmem.pageHitRate                      81.99                       # Row buffer hit rate, read and write combined
 system.physmem.memoryStateTime::IDLE            22000                       # Time in different power states
 system.physmem.memoryStateTime::REF            260000                       # Time in different power states
 system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT           7796750                       # Time in different power states
+system.physmem.memoryStateTime::ACT           7778000                       # Time in different power states
 system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.membus.throughput                   1458978748                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq                 249                       # Transaction distribution
-system.membus.trans_dist::ReadResp                249                       # Transaction distribution
+system.membus.throughput                   1479580128                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq                 248                       # Transaction distribution
+system.membus.trans_dist::ReadResp                248                       # Transaction distribution
 system.membus.trans_dist::ReadExReq                24                       # Transaction distribution
 system.membus.trans_dist::ReadExResp               24                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port          546                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                    546                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        17472                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total               17472                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus                  17472                       # Total data (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port          544                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                    544                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        17408                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total               17408                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus                  17408                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy              344000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy              339500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               2.9                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            2554750                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization             21.3                       # Layer utilization (%)
+system.membus.respLayer1.occupancy            2545000                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization             21.6                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.branchPred.lookups                    1179                       # Number of BP lookups
-system.cpu.branchPred.condPredicted               620                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect               258                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups                  806                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                     254                       # Number of BTB hits
+system.cpu.branchPred.lookups                    1090                       # Number of BP lookups
+system.cpu.branchPred.condPredicted               548                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect               231                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups                  734                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                     202                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             31.513648                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                     212                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect                 37                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             27.520436                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                     199                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect                  9                       # Number of incorrect RAS predictions.
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                          712                       # DTB read hits
-system.cpu.dtb.read_misses                         31                       # DTB read misses
+system.cpu.dtb.read_hits                          689                       # DTB read hits
+system.cpu.dtb.read_misses                         23                       # DTB read misses
 system.cpu.dtb.read_acv                             1                       # DTB read access violations
-system.cpu.dtb.read_accesses                      743                       # DTB read accesses
-system.cpu.dtb.write_hits                         368                       # DTB write hits
-system.cpu.dtb.write_misses                        20                       # DTB write misses
+system.cpu.dtb.read_accesses                      712                       # DTB read accesses
+system.cpu.dtb.write_hits                         352                       # DTB write hits
+system.cpu.dtb.write_misses                        18                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses                     388                       # DTB write accesses
-system.cpu.dtb.data_hits                         1080                       # DTB hits
-system.cpu.dtb.data_misses                         51                       # DTB misses
+system.cpu.dtb.write_accesses                     370                       # DTB write accesses
+system.cpu.dtb.data_hits                         1041                       # DTB hits
+system.cpu.dtb.data_misses                         41                       # DTB misses
 system.cpu.dtb.data_acv                             1                       # DTB access violations
-system.cpu.dtb.data_accesses                     1131                       # DTB accesses
-system.cpu.itb.fetch_hits                        1070                       # ITB hits
-system.cpu.itb.fetch_misses                        30                       # ITB misses
+system.cpu.dtb.data_accesses                     1082                       # DTB accesses
+system.cpu.itb.fetch_hits                         938                       # ITB hits
+system.cpu.itb.fetch_misses                        26                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                    1100                       # ITB accesses
+system.cpu.itb.fetch_accesses                     964                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -285,237 +285,236 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                    4                       # Number of system calls
-system.cpu.numCycles                            23952                       # number of cpu cycles simulated
+system.cpu.numCycles                            23532                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles               4349                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                           7041                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                        1179                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches                466                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                          1215                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                     872                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles                    516                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.icacheStallCycles               4442                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                           6549                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                        1090                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches                401                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                          1376                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                     508                       # Number of cycles fetch has spent squashing
 system.cpu.fetch.MiscStallCycles                   18                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles          1022                       # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingTrapStallCycles          1110                       # Number of stall cycles due to pending traps
 system.cpu.fetch.IcacheWaitRetryStallCycles           11                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                      1070                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                   187                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples               7706                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              0.913704                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.320621                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.CacheLines                       938                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                   155                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples               7211                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              0.908196                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.330561                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                     6491     84.23%     84.23% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                       53      0.69%     84.92% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                      117      1.52%     86.44% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                       96      1.25%     87.68% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                      176      2.28%     89.97% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                       76      0.99%     90.96% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                       64      0.83%     91.79% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                       66      0.86%     92.64% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                      567      7.36%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                     6093     84.50%     84.50% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                       49      0.68%     85.18% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                      123      1.71%     86.88% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                       84      1.16%     88.05% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                      131      1.82%     89.86% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                       58      0.80%     90.67% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                       67      0.93%     91.60% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                       62      0.86%     92.46% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                      544      7.54%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total                 7706                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.049223                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.293963                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                     5479                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles                   562                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                      1164                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles                     4                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                    497                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved                  166                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                    81                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts                   6225                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                   292                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                    497                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                     5576                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                     257                       # Number of cycles rename is blocking
+system.cpu.fetch.rateDist::total                 7211                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.046320                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.278302                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                     5244                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles                   757                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                       975                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles                    55                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                    180                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved                  156                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                    76                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts                   5674                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                   276                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                    180                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                     5327                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                     452                       # Number of cycles rename is blocking
 system.cpu.rename.serializeStallCycles            280                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                      1068                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles                    28                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts                   5913                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                     1                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                     20                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.RenamedOperands                4287                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups                  6690                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups             6683                       # Number of integer rename lookups
+system.cpu.rename.RunCycles                       942                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles                    30                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts                   5438                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                     2                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                     18                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.RenamedOperands                3913                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups                  6138                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups             6131                       # Number of integer rename lookups
 system.cpu.rename.fp_rename_lookups                 6                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps                  1768                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                     2519                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.UndoneMaps                     2145                       # Number of HB maps that are undone due to squashing
 system.cpu.rename.serializingInsts                  8                       # count of serializing insts renamed
 system.cpu.rename.tempSerializingInsts              6                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                        93                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads                  957                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores                 470                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads                 3                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores                3                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                       4974                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.rename.skidInsts                       115                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads                  883                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores                 455                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads                 2                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores                2                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                       4685                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqNonSpecInstsAdded                   6                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                      4048                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued                54                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined            2349                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined         1396                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqInstsIssued                      3891                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued                14                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined            2057                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined         1216                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu.iq.iqSquashedNonSpecRemoved              2                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples          7706                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.525305                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.241065                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples          7211                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.539592                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.280898                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0                6082     78.93%     78.93% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1                 565      7.33%     86.26% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2                 401      5.20%     91.46% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3                 263      3.41%     94.87% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4                 198      2.57%     97.44% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5                 121      1.57%     99.01% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6                  48      0.62%     99.64% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7                  17      0.22%     99.86% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8                  11      0.14%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0                5712     79.21%     79.21% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1                 492      6.82%     86.04% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2                 353      4.90%     90.93% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3                 253      3.51%     94.44% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4                 197      2.73%     97.17% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                 121      1.68%     98.85% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6                  52      0.72%     99.57% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7                  19      0.26%     99.83% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8                  12      0.17%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total            7706                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total            7211                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                       3      6.82%      6.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%      6.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      6.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      6.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      6.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      6.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      6.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      6.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      6.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      6.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      6.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      6.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      6.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      6.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      6.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      6.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      6.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      6.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      6.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      6.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      6.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      6.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      6.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      6.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      6.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      6.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      6.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      6.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      6.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                     19     43.18%     50.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                    22     50.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                       6     11.76%     11.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%     11.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     11.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     11.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     11.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     11.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     11.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     11.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     11.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     11.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     11.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     11.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     11.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     11.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     11.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     11.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     11.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     11.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     11.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     11.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     11.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     11.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     11.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     11.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     11.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     11.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     11.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     11.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     11.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                     22     43.14%     54.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                    23     45.10%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu                  2866     70.80%     70.80% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                    1      0.02%     70.83% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     70.83% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     70.83% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     70.83% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     70.83% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     70.83% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     70.83% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     70.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     70.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     70.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     70.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     70.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     70.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     70.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     70.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     70.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     70.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     70.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     70.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     70.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     70.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     70.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     70.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     70.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     70.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     70.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     70.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     70.83% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead                  786     19.42%     90.24% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite                 395      9.76%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu                  2776     71.34%     71.34% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                    1      0.03%     71.37% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     71.37% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     71.37% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     71.37% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     71.37% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     71.37% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     71.37% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     71.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     71.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     71.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     71.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     71.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     71.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     71.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     71.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     71.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     71.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     71.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     71.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     71.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     71.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     71.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     71.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     71.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     71.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     71.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     71.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     71.37% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead                  739     18.99%     90.36% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite                 375      9.64%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total                   4048                       # Type of FU issued
-system.cpu.iq.rate                           0.169005                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                          44                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.010870                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads              15887                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes              7327                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses         3655                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total                   3891                       # Type of FU issued
+system.cpu.iq.rate                           0.165349                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                          51                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.013107                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads              15045                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes              6745                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses         3580                       # Number of integer instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_reads                  13                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_writes                  6                       # Number of floating instruction queue writes
 system.cpu.iq.fp_inst_queue_wakeup_accesses            6                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses                   4085                       # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses                   3935                       # Number of integer alu accesses
 system.cpu.iq.fp_alu_accesses                       7                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads               33                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads               32                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads          542                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses            1                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.squashedLoads          468                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses            0                       # Number of memory responses ignored because the instruction is squashed
 system.cpu.iew.lsq.thread0.memOrderViolation            4                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores          176                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedStores          161                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked            16                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.cacheBlocked            24                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                    497                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                     231                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                     3                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts                5316                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts               162                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts                   957                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts                  470                       # Number of dispatched store instructions
+system.cpu.iew.iewSquashCycles                    180                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                     393                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                     5                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts                5027                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts                28                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts                   883                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts                  455                       # Number of dispatched store instructions
 system.cpu.iew.iewDispNonSpecInsts                  6                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                      2                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewIQFullEvents                      3                       # Number of times the IQ has become full, causing a stall
 system.cpu.iew.iewLSQFullEvents                     0                       # Number of times the LSQ has become full, causing a stall
 system.cpu.iew.memOrderViolationEvents              4                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect             53                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect          162                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts                  215                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts                  3860                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts                   744                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts               188                       # Number of squashed instructions skipped in execute
+system.cpu.iew.predictedTakenIncorrect             22                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect          169                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts                  191                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts                  3755                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts                   713                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts               136                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                           336                       # number of nop insts executed
-system.cpu.iew.exec_refs                         1132                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                      644                       # Number of branches executed
-system.cpu.iew.exec_stores                        388                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.161156                       # Inst execution rate
-system.cpu.iew.wb_sent                           3742                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                          3661                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                      1713                       # num instructions producing a value
-system.cpu.iew.wb_consumers                      2215                       # num instructions consuming a value
+system.cpu.iew.exec_refs                         1083                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                      638                       # Number of branches executed
+system.cpu.iew.exec_stores                        370                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.159570                       # Inst execution rate
+system.cpu.iew.wb_sent                           3650                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                          3586                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                      1711                       # num instructions producing a value
+system.cpu.iew.wb_consumers                      2190                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.152847                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.773363                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       0.152388                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.781279                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts            2734                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts            2437                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls               4                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts               180                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples         7209                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.357331                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.199884                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts               157                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples         6757                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.381234                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.252230                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0         6340     87.95%     87.95% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1          204      2.83%     90.78% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2          308      4.27%     95.05% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3          114      1.58%     96.63% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4           72      1.00%     97.63% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5           51      0.71%     98.34% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6           32      0.44%     98.78% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7           25      0.35%     99.13% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8           63      0.87%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0         5909     87.45%     87.45% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1          193      2.86%     90.31% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2          297      4.40%     94.70% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3          108      1.60%     96.30% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4           72      1.07%     97.37% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5           53      0.78%     98.15% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6           33      0.49%     98.64% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7           22      0.33%     98.96% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8           70      1.04%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total         7209                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total         6757                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts                 2576                       # Number of instructions committed
 system.cpu.commit.committedOps                   2576                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -561,182 +560,182 @@ system.cpu.commit.op_class_0::MemWrite            294     11.41%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total              2576                       # Class of committed instruction
-system.cpu.commit.bw_lim_events                    63                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events                    70                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                        12209                       # The number of ROB reads
-system.cpu.rob.rob_writes                       11130                       # The number of ROB writes
-system.cpu.timesIdled                             157                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           16246                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads                        11453                       # The number of ROB reads
+system.cpu.rob.rob_writes                       10498                       # The number of ROB writes
+system.cpu.timesIdled                             160                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           16321                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                        2387                       # Number of Instructions Simulated
 system.cpu.committedOps                          2387                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                              10.034353                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                        10.034353                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.099658                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.099658                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                     4675                       # number of integer regfile reads
-system.cpu.int_regfile_writes                    2829                       # number of integer regfile writes
+system.cpu.cpi                               9.858400                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         9.858400                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.101436                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.101436                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                     4543                       # number of integer regfile reads
+system.cpu.int_regfile_writes                    2774                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                         6                       # number of floating regfile reads
 system.cpu.misc_regfile_reads                       1                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
-system.cpu.toL2Bus.throughput              1458978748                       # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq            249                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp           249                       # Transaction distribution
+system.cpu.toL2Bus.throughput              1479580128                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq            248                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp           248                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq           24                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp           24                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          376                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          374                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          170                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total               546                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        12032                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total               544                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        11968                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         5440                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total          17472                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus             17472                       # Total data (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total          17408                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus             17408                       # Total data (bytes)
 system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy         136500                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          1.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy        316750                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          2.6                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy        133500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.occupancy         136000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          1.2                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy        314250                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization          2.7                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy        133250                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          1.1                       # Layer utilization (%)
 system.cpu.icache.tags.replacements                 0                       # number of replacements
-system.cpu.icache.tags.tagsinuse            93.052678                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs                 820                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs               188                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs              4.361702                       # Average number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse            92.065177                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs                 685                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs               187                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs              3.663102                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst    93.052678                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.045436                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.045436                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024          188                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          161                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1           27                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.091797                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses              2328                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses             2328                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst          820                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total             820                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst           820                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total              820                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst          820                       # number of overall hits
-system.cpu.icache.overall_hits::total             820                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst          250                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total           250                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst          250                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total            250                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst          250                       # number of overall misses
-system.cpu.icache.overall_misses::total           250                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     17505249                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     17505249                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     17505249                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     17505249                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     17505249                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     17505249                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst         1070                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total         1070                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst         1070                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total         1070                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst         1070                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total         1070                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.233645                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.233645                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.233645                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.233645                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.233645                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.233645                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70020.996000                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 70020.996000                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 70020.996000                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 70020.996000                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 70020.996000                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 70020.996000                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs          112                       # number of cycles access was blocked
+system.cpu.icache.tags.occ_blocks::cpu.inst    92.065177                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.044954                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.044954                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          187                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          163                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           24                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.091309                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses              2063                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses             2063                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst          685                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total             685                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst           685                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total              685                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst          685                       # number of overall hits
+system.cpu.icache.overall_hits::total             685                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          253                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           253                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          253                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            253                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          253                       # number of overall misses
+system.cpu.icache.overall_misses::total           253                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     17329249                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     17329249                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     17329249                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     17329249                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     17329249                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     17329249                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst          938                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total          938                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst          938                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total          938                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst          938                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total          938                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.269723                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.269723                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.269723                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.269723                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.269723                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.269723                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68495.055336                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 68495.055336                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 68495.055336                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 68495.055336                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 68495.055336                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 68495.055336                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs          110                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 2                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs           56                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs           55                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst           62                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total           62                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst           62                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total           62                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst           62                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total           62                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst          188                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total          188                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst          188                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total          188                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst          188                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total          188                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     13109499                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     13109499                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     13109499                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     13109499                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     13109499                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     13109499                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.175701                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.175701                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.175701                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.175701                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.175701                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.175701                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69731.377660                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69731.377660                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69731.377660                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 69731.377660                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69731.377660                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 69731.377660                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst           66                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total           66                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst           66                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total           66                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst           66                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total           66                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          187                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          187                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          187                       # number of demand (read+write) MSHR misses
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+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     12893999                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     12893999                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     12893999                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     12893999                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     12893999                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     12893999                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.199360                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.199360                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.199360                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.199360                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.199360                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.199360                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68951.866310                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68951.866310                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68951.866310                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 68951.866310                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68951.866310                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 68951.866310                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse          121.888470                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse          121.503793                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs                  0                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs              249                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs              248                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs                    0                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst    93.250833                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data    28.637638                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.002846                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.000874                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.003720                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024          249                       # Occupied blocks per task id
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-system.cpu.l2cache.tags.age_task_id_blocks_1024::1           38                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.007599                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses             2457                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses            2457                       # Number of data accesses
-system.cpu.l2cache.ReadReq_misses::cpu.inst          188                       # number of ReadReq misses
+system.cpu.l2cache.tags.occ_blocks::cpu.inst    92.265551                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data    29.238242                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.002816                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.000892                       # Average percentage of cache occupancy
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+system.cpu.l2cache.tags.age_task_id_blocks_1024::1           34                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.007568                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses             2448                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses            2448                       # Number of data accesses
+system.cpu.l2cache.ReadReq_misses::cpu.inst          187                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_misses::cpu.data           61                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total          249                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total          248                       # number of ReadReq misses
 system.cpu.l2cache.ReadExReq_misses::cpu.data           24                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total           24                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst          188                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.inst          187                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::cpu.data           85                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total           273                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst          188                       # number of overall misses
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 system.cpu.l2cache.overall_misses::cpu.data           85                       # number of overall misses
-system.cpu.l2cache.overall_misses::total          273                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     12920750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data      4652000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total     17572750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      1688000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total      1688000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     12920750                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data      6340000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     19260750                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     12920750                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data      6340000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     19260750                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst          188                       # number of ReadReq accesses(hits+misses)
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+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     12706250                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data      4451500                       # number of ReadReq miss cycles
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+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      1692250                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total      1692250                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     12706250                       # number of demand (read+write) miss cycles
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+system.cpu.l2cache.overall_miss_latency::cpu.inst     12706250                       # number of overall miss cycles
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+system.cpu.l2cache.overall_miss_latency::total     18850000                       # number of overall miss cycles
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 system.cpu.l2cache.ReadReq_accesses::cpu.data           61                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total          249                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total          248                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data           24                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total           24                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst          188                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst          187                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::cpu.data           85                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total          273                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst          188                       # number of overall (read+write) accesses
+system.cpu.l2cache.demand_accesses::total          272                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst          187                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.data           85                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total          273                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total          272                       # number of overall (read+write) accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst            1                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.data            1                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_miss_rate::total            1                       # miss rate for ReadReq accesses
@@ -748,17 +747,17 @@ system.cpu.l2cache.demand_miss_rate::total            1                       #
 system.cpu.l2cache.overall_miss_rate::cpu.inst            1                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total            1                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68727.393617                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76262.295082                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 70573.293173                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70333.333333                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70333.333333                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68727.393617                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74588.235294                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 70552.197802                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68727.393617                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74588.235294                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 70552.197802                       # average overall miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67947.860963                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72975.409836                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 69184.475806                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70510.416667                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70510.416667                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67947.860963                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72279.411765                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 69301.470588                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67947.860963                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72279.411765                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 69301.470588                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -767,28 +766,28 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          188                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          187                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadReq_mshr_misses::cpu.data           61                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total          249                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total          248                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           24                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total           24                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst          188                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          187                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.data           85                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total          273                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst          188                       # number of overall MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total          272                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          187                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data           85                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total          273                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     10547750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      3905000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     14452750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      1393500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      1393500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     10547750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      5298500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     15846250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     10547750                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      5298500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     15846250                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_misses::total          272                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     10348750                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      3702000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total     14050750                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      1398750                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      1398750                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     10348750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      5100750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     15449500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     10348750                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      5100750                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     15449500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
@@ -800,97 +799,97 @@ system.cpu.l2cache.demand_mshr_miss_rate::total            1
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56105.053191                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64016.393443                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58043.172691                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58062.500000                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58062.500000                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56105.053191                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62335.294118                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58044.871795                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56105.053191                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62335.294118                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58044.871795                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55340.909091                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60688.524590                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56656.250000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58281.250000                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58281.250000                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55340.909091                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60008.823529                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56799.632353                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55340.909091                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60008.823529                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56799.632353                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.dcache.tags.replacements                 0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse            45.583444                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs                 761                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse            46.118379                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs                 729                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs                85                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs              8.952941                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs              8.576471                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data    45.583444                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.011129                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.011129                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data    46.118379                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.011259                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.011259                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024           85                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           67                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1           18                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           69                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           16                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024     0.020752                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses              1999                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses             1999                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data          548                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total             548                       # number of ReadReq hits
+system.cpu.dcache.tags.tag_accesses              1939                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses             1939                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data          516                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total             516                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data          213                       # number of WriteReq hits
 system.cpu.dcache.WriteReq_hits::total            213                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data           761                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total              761                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data          761                       # number of overall hits
-system.cpu.dcache.overall_hits::total             761                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data          115                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total           115                       # number of ReadReq misses
+system.cpu.dcache.demand_hits::cpu.data           729                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total              729                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data          729                       # number of overall hits
+system.cpu.dcache.overall_hits::total             729                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data          117                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total           117                       # number of ReadReq misses
 system.cpu.dcache.WriteReq_misses::cpu.data           81                       # number of WriteReq misses
 system.cpu.dcache.WriteReq_misses::total           81                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data          196                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total            196                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data          196                       # number of overall misses
-system.cpu.dcache.overall_misses::total           196                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data      7876750                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total      7876750                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data      5302250                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total      5302250                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     13179000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     13179000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     13179000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     13179000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data          663                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total          663                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data          198                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total            198                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data          198                       # number of overall misses
+system.cpu.dcache.overall_misses::total           198                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data      7443000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total      7443000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data      5304000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total      5304000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     12747000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     12747000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     12747000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     12747000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data          633                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total          633                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data          294                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total          294                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data          957                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total          957                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data          957                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total          957                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.173454                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.173454                       # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data          927                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total          927                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data          927                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total          927                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.184834                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.184834                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.275510                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_miss_rate::total     0.275510                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.204807                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.204807                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.204807                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.204807                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68493.478261                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 68493.478261                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65459.876543                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 65459.876543                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 67239.795918                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 67239.795918                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 67239.795918                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 67239.795918                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs          145                       # number of cycles access was blocked
+system.cpu.dcache.demand_miss_rate::cpu.data     0.213592                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.213592                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.213592                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.213592                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63615.384615                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 63615.384615                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65481.481481                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 65481.481481                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 64378.787879                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 64378.787879                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 64378.787879                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 64378.787879                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs          131                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                 4                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 2                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    36.250000                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    65.500000                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data           54                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total           54                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data           56                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total           56                       # number of ReadReq MSHR hits
 system.cpu.dcache.WriteReq_mshr_hits::cpu.data           57                       # number of WriteReq MSHR hits
 system.cpu.dcache.WriteReq_mshr_hits::total           57                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data          111                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total          111                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data          111                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total          111                       # number of overall MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data          113                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total          113                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data          113                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total          113                       # number of overall MSHR hits
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data           61                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total           61                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data           24                       # number of WriteReq MSHR misses
@@ -899,30 +898,30 @@ system.cpu.dcache.demand_mshr_misses::cpu.data           85
 system.cpu.dcache.demand_mshr_misses::total           85                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data           85                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total           85                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      4713000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      4713000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      1713500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      1713500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data      6426500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total      6426500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data      6426500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total      6426500                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.092006                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.092006                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      4512500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      4512500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      1717750                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      1717750                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data      6230250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total      6230250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data      6230250                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total      6230250                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.096367                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.096367                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.081633                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.081633                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.088819                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.088819                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.088819                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.088819                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77262.295082                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77262.295082                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71395.833333                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71395.833333                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75605.882353                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 75605.882353                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75605.882353                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 75605.882353                       # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.091694                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.091694                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.091694                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.091694                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 73975.409836                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 73975.409836                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71572.916667                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71572.916667                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73297.058824                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 73297.058824                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73297.058824                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 73297.058824                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt
index e6065a0ab..65ff8dd3e 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt
@@ -1,532 +1,51 @@
 
 ---------- Begin Simulation Statistics ----------
-final_tick                                   27963000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-host_inst_rate                                  75358                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 292860                       # Number of bytes of host memory used
-host_op_rate                                    93985                       # Simulator op (including micro ops) rate (op/s)
-host_seconds                                     0.06                       # Real time elapsed on the host
-host_tick_rate                              457698243                       # Simulator tick rate (ticks/s)
+sim_seconds                                  0.000028                       # Number of seconds simulated
+sim_ticks                                    27911000                       # Number of ticks simulated
+final_tick                                   27911000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                  66829                       # Simulator instruction rate (inst/s)
+host_op_rate                                    78212                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              404876453                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 278412                       # Number of bytes of host memory used
+host_seconds                                     0.07                       # Real time elapsed on the host
 sim_insts                                        4604                       # Number of instructions simulated
-sim_ops                                          5742                       # Number of ops (including micro ops) simulated
-sim_seconds                                  0.000028                       # Number of seconds simulated
-sim_ticks                                    27963000                       # Number of ticks simulated
+sim_ops                                          5390                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             21.219512                       # BTB Hit Percentage
-system.cpu.branchPred.BTBHits                     348                       # Number of BTB hits
-system.cpu.branchPred.BTBLookups                 1640                       # Number of BTB lookups
-system.cpu.branchPred.RASInCorrect                 16                       # Number of incorrect RAS predictions.
-system.cpu.branchPred.condIncorrect               349                       # Number of conditional branches incorrect
-system.cpu.branchPred.condPredicted              1370                       # Number of conditional branches predicted
-system.cpu.branchPred.lookups                    2005                       # Number of BP lookups
-system.cpu.branchPred.usedRAS                     202                       # Number of times the RAS was used to get a target.
-system.cpu.committedInsts                        4604                       # Number of instructions committed
-system.cpu.committedOps                          5742                       # Number of ops (including micro ops) committed
-system.cpu.cpi                              12.147263                       # CPI: cycles per instruction
-system.cpu.dcache.LoadLockedReq_accesses::cpu.inst           11                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total           11                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_hits::cpu.inst           11                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total           11                       # number of LoadLockedReq hits
-system.cpu.dcache.ReadReq_accesses::cpu.inst         1318                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total         1318                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 60367.304348                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 60367.304348                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 60667.563107                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60667.563107                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits::cpu.inst         1203                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total            1203                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency::cpu.inst      6942240                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total      6942240                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate::cpu.inst     0.087253                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.087253                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses::cpu.inst          115                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total           115                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits::cpu.inst           12                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total           12                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst      6248759                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      6248759                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst     0.078149                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.078149                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses::cpu.inst          103                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total          103                       # number of ReadReq MSHR misses
-system.cpu.dcache.StoreCondReq_accesses::cpu.inst           11                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total           11                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_hits::cpu.inst           11                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total           11                       # number of StoreCondReq hits
-system.cpu.dcache.WriteReq_accesses::cpu.inst          913                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total          913                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 68664.179104                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 68664.179104                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 66843.023256                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66843.023256                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits::cpu.inst          846                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total            846                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency::cpu.inst      4600500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total      4600500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate::cpu.inst     0.073384                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.073384                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses::cpu.inst           67                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total           67                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits::cpu.inst           24                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total           24                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst      2874250                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      2874250                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst     0.047097                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.047097                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.inst           43                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total           43                       # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.demand_accesses::cpu.inst         2231                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total         2231                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency::cpu.inst 63421.648352                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 63421.648352                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 62486.363014                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 62486.363014                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits::cpu.inst          2049                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total             2049                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency::cpu.inst     11542740                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     11542740                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate::cpu.inst     0.081578                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.081578                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses::cpu.inst          182                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total            182                       # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits::cpu.inst           36                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total           36                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency::cpu.inst      9123009                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total      9123009                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate::cpu.inst     0.065442                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.065442                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses::cpu.inst          146                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total          146                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses::cpu.inst         2231                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total         2231                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency::cpu.inst 63421.648352                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 63421.648352                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 62486.363014                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 62486.363014                       # average overall mshr miss latency
-system.cpu.dcache.overall_hits::cpu.inst         2049                       # number of overall hits
-system.cpu.dcache.overall_hits::total            2049                       # number of overall hits
-system.cpu.dcache.overall_miss_latency::cpu.inst     11542740                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     11542740                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate::cpu.inst     0.081578                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.081578                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses::cpu.inst          182                       # number of overall misses
-system.cpu.dcache.overall_misses::total           182                       # number of overall misses
-system.cpu.dcache.overall_mshr_hits::cpu.inst           36                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total           36                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency::cpu.inst      9123009                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total      9123009                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate::cpu.inst     0.065442                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.065442                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses::cpu.inst          146                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total          146                       # number of overall MSHR misses
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           38                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          108                       # Occupied blocks per task id
-system.cpu.dcache.tags.avg_refs             14.184932                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.data_accesses             4652                       # Number of data accesses
-system.cpu.dcache.tags.occ_blocks::cpu.inst    86.831207                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.inst     0.021199                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.021199                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024          146                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024     0.035645                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.replacements                 0                       # number of replacements
-system.cpu.dcache.tags.sampled_refs               146                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.tag_accesses              4652                       # Number of tag accesses
-system.cpu.dcache.tags.tagsinuse            86.831207                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs                2071                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.discardedOps                          1297                       # Number of ops (including micro ops) which were discarded before commit
-system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
-system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
-system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
-system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
-system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
-system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
-system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
-system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
-system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
-system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
-system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
-system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
-system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
-system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
-system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
-system.cpu.dtb.accesses                             0                       # DTB accesses
-system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.hits                                 0                       # DTB hits
-system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.inst_hits                            0                       # ITB inst hits
-system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.misses                               0                       # DTB misses
-system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
-system.cpu.dtb.read_accesses                        0                       # DTB read accesses
-system.cpu.dtb.read_hits                            0                       # DTB read hits
-system.cpu.dtb.read_misses                          0                       # DTB read misses
-system.cpu.dtb.write_accesses                       0                       # DTB write accesses
-system.cpu.dtb.write_hits                           0                       # DTB write hits
-system.cpu.dtb.write_misses                         0                       # DTB write misses
-system.cpu.icache.ReadReq_accesses::cpu.inst         2307                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total         2307                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66806.250000                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 66806.250000                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 64396.875000                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 64396.875000                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits::cpu.inst         1987                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total            1987                       # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     21378000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     21378000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.138708                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.138708                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses::cpu.inst          320                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total           320                       # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     20607000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     20607000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.138708                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.138708                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst          320                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total          320                       # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.demand_accesses::cpu.inst         2307                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total         2307                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 66806.250000                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 66806.250000                       # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 64396.875000                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 64396.875000                       # average overall mshr miss latency
-system.cpu.icache.demand_hits::cpu.inst          1987                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total             1987                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency::cpu.inst     21378000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     21378000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate::cpu.inst     0.138708                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.138708                       # miss rate for demand accesses
-system.cpu.icache.demand_misses::cpu.inst          320                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total            320                       # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     20607000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     20607000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.138708                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.138708                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses::cpu.inst          320                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total          320                       # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses::cpu.inst         2307                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total         2307                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 66806.250000                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 66806.250000                       # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 64396.875000                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 64396.875000                       # average overall mshr miss latency
-system.cpu.icache.overall_hits::cpu.inst         1987                       # number of overall hits
-system.cpu.icache.overall_hits::total            1987                       # number of overall hits
-system.cpu.icache.overall_miss_latency::cpu.inst     21378000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     21378000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_rate::cpu.inst     0.138708                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.138708                       # miss rate for overall accesses
-system.cpu.icache.overall_misses::cpu.inst          320                       # number of overall misses
-system.cpu.icache.overall_misses::total           320                       # number of overall misses
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     20607000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     20607000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.138708                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.138708                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses::cpu.inst          320                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total          320                       # number of overall MSHR misses
-system.cpu.icache.tags.age_task_id_blocks_1024::0          114                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          203                       # Occupied blocks per task id
-system.cpu.icache.tags.avg_refs              6.209375                       # Average number of references to valid blocks.
-system.cpu.icache.tags.data_accesses             4934                       # Number of data accesses
-system.cpu.icache.tags.occ_blocks::cpu.inst   161.718196                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.078964                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.078964                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024          317                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.154785                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.replacements                 3                       # number of replacements
-system.cpu.icache.tags.sampled_refs               320                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.tag_accesses              4934                       # Number of tag accesses
-system.cpu.icache.tags.tagsinuse           161.718196                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs                1987                       # Total number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.idleCycles                           44980                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.ipc                               0.082323                       # IPC: instructions per cycle
-system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
-system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
-system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
-system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
-system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
-system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
-system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
-system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
-system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
-system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
-system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
-system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
-system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
-system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
-system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
-system.cpu.itb.accesses                             0                       # DTB accesses
-system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
-system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.hits                                 0                       # DTB hits
-system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.itb.inst_hits                            0                       # ITB inst hits
-system.cpu.itb.inst_misses                          0                       # ITB inst misses
-system.cpu.itb.misses                               0                       # DTB misses
-system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
-system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
-system.cpu.itb.read_accesses                        0                       # DTB read accesses
-system.cpu.itb.read_hits                            0                       # DTB read hits
-system.cpu.itb.read_misses                          0                       # DTB read misses
-system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.write_hits                           0                       # DTB write hits
-system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.l2cache.ReadExReq_accesses::cpu.inst           43                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total           43                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 65831.395349                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65831.395349                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 53308.139535                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 53308.139535                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst      2830750                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total      2830750                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst            1                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses::cpu.inst           43                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total           43                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst      2292250                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      2292250                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst           43                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total           43                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses::cpu.inst          423                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total          423                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67507.124352                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 67507.124352                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55150.530504                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55150.530504                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits::cpu.inst           37                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total             37                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     26057750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total     26057750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.912530                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.912530                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses::cpu.inst          386                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total          386                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            9                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total            9                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     20791750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     20791750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.891253                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.891253                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          377                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total          377                       # number of ReadReq MSHR misses
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.demand_accesses::cpu.inst          466                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total          466                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67339.160839                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 67339.160839                       # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54961.904762                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54961.904762                       # average overall mshr miss latency
-system.cpu.l2cache.demand_hits::cpu.inst           37                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total              37                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency::cpu.inst     28888500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     28888500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.920601                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.920601                       # miss rate for demand accesses
-system.cpu.l2cache.demand_misses::cpu.inst          429                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total           429                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_mshr_hits::cpu.inst            9                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total            9                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     23084000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     23084000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.901288                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.901288                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst          420                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total          420                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses::cpu.inst          466                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total          466                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67339.160839                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 67339.160839                       # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54961.904762                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54961.904762                       # average overall mshr miss latency
-system.cpu.l2cache.overall_hits::cpu.inst           37                       # number of overall hits
-system.cpu.l2cache.overall_hits::total             37                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency::cpu.inst     28888500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     28888500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.920601                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.920601                       # miss rate for overall accesses
-system.cpu.l2cache.overall_misses::cpu.inst          429                       # number of overall misses
-system.cpu.l2cache.overall_misses::total          429                       # number of overall misses
-system.cpu.l2cache.overall_mshr_hits::cpu.inst            9                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total            9                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     23084000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     23084000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.901288                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.901288                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst          420                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total          420                       # number of overall MSHR misses
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          132                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          245                       # Occupied blocks per task id
-system.cpu.l2cache.tags.avg_refs             0.098143                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.data_accesses            4148                       # Number of data accesses
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   195.926239                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.005979                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.005979                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024          377                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.011505                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.sampled_refs              377                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.tag_accesses             4148                       # Number of tag accesses
-system.cpu.l2cache.tags.tagsinuse          195.926239                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs                 37                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.numCycles                            55926                       # number of cpu cycles simulated
-system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.tickCycles                           10946                       # Number of cycles that the CPU actually ticked
-system.cpu.toL2Bus.data_through_bus             29824                       # Total data (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          640                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          292                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total               932                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy         233000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          0.8                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy        545500                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          2.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy        234491                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          0.8                       # Layer utilization (%)
-system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
-system.cpu.toL2Bus.throughput              1066552230                       # Throughput (bytes/s)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        20480                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         9344                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total          29824                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.trans_dist::ReadReq            423                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp           423                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq           43                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp           43                       # Transaction distribution
-system.cpu.workload.num_syscalls                   13                       # Number of system calls
-system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.membus.data_through_bus                  26880                       # Total data (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port          840                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                    840                       # Packet count per connected master and slave (bytes)
-system.membus.reqLayer0.occupancy              485500                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               1.7                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            3923500                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization             14.0                       # Layer utilization (%)
-system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.throughput                    961270250                       # Throughput (bytes/s)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        26880                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total               26880                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.trans_dist::ReadReq                 377                       # Transaction distribution
-system.membus.trans_dist::ReadResp                377                       # Transaction distribution
-system.membus.trans_dist::ReadExReq                43                       # Transaction distribution
-system.membus.trans_dist::ReadExResp               43                       # Transaction distribution
-system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgGap                        66375.00                       # Average gap between requests
-system.physmem.avgMemAccLat                  24369.64                       # Average memory access latency per DRAM burst
-system.physmem.avgQLat                        5619.64                       # Average queueing delay per DRAM burst
-system.physmem.avgRdBW                         961.27                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgRdBWSys                      961.27                       # Average system read bandwidth in MiByte/s
-system.physmem.avgRdQLen                         1.21                       # Average read queue length when enqueuing
-system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
-system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.busUtil                           7.51                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       7.51                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.bw_inst_read::cpu.inst       695776562                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          695776562                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst            961270250                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               961270250                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           961270250                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              961270250                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bytesPerActivate::samples           65                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      389.907692                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     267.054058                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     328.238562                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127             11     16.92%     16.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255           17     26.15%     43.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383           12     18.46%     61.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511            7     10.77%     72.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639            3      4.62%     76.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767            2      3.08%     80.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895            3      4.62%     84.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151           10     15.38%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total             65                       # Bytes accessed per row activation
+system.physmem.bytes_read::cpu.inst             26880                       # Number of bytes read from this memory
+system.physmem.bytes_read::total                26880                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        19456                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           19456                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst                420                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                   420                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst            963061159                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               963061159                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst       697072839                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          697072839                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           963061159                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              963061159                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                           420                       # Number of read requests accepted
+system.physmem.writeReqs                            0                       # Number of write requests accepted
+system.physmem.readBursts                         420                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
 system.physmem.bytesReadDRAM                    26880                       # Total number of bytes read from DRAM
-system.physmem.bytesReadSys                     26880                       # Total read bytes from the system interface side
 system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
 system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                     26880                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
-system.physmem.bytes_inst_read::cpu.inst        19456                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           19456                       # Number of instructions bytes read from this memory
-system.physmem.bytes_read::cpu.inst             26880                       # Number of bytes read from this memory
-system.physmem.bytes_read::total                26880                       # Number of bytes read from this memory
-system.physmem.memoryStateTime::IDLE            12000                       # Time in different power states
-system.physmem.memoryStateTime::REF            780000                       # Time in different power states
-system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT          22869500                       # Time in different power states
-system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
+system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.num_reads::cpu.inst                420                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                   420                       # Number of read requests responded to by this memory
-system.physmem.pageHitRate                      82.62                       # Row buffer hit rate, read and write combined
-system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.perBankRdBursts::0                  91                       # Per bank write bursts
 system.physmem.perBankRdBursts::1                  51                       # Per bank write bursts
 system.physmem.perBankRdBursts::2                  20                       # Per bank write bursts
 system.physmem.perBankRdBursts::3                  42                       # Per bank write bursts
-system.physmem.perBankRdBursts::4                  22                       # Per bank write bursts
+system.physmem.perBankRdBursts::4                  23                       # Per bank write bursts
 system.physmem.perBankRdBursts::5                  41                       # Per bank write bursts
 system.physmem.perBankRdBursts::6                  36                       # Per bank write bursts
 system.physmem.perBankRdBursts::7                  12                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                   6                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                   5                       # Per bank write bursts
 system.physmem.perBankRdBursts::9                   6                       # Per bank write bursts
 system.physmem.perBankRdBursts::10                 27                       # Per bank write bursts
 system.physmem.perBankRdBursts::11                 42                       # Per bank write bursts
@@ -550,8 +69,25 @@ system.physmem.perBankWrBursts::12                  0                       # Pe
 system.physmem.perBankWrBursts::13                  0                       # Per bank write bursts
 system.physmem.perBankWrBursts::14                  0                       # Per bank write bursts
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
-system.physmem.rdQLenPdf::0                       347                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                        65                       # What read queue length does an incoming req see
+system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
+system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
+system.physmem.totGap                        27825500                       # Total gap between requests
+system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
+system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
+system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
+system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
+system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
+system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
+system.physmem.readPktSize::6                     420                       # Read request sizes (log2)
+system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
+system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
+system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
+system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
+system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
+system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
+system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                       345                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                        67                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::2                         8                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
@@ -582,22 +118,6 @@ system.physmem.rdQLenPdf::28                        0                       # Wh
 system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.readBursts                         420                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                     420                       # Read request sizes (log2)
-system.physmem.readReqs                           420                       # Number of read requests accepted
-system.physmem.readRowHitRate                   82.62                       # Row buffer hit rate for reads
-system.physmem.readRowHits                        347                       # Number of row buffer hits during reads
-system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.totBusLat                      2100000                       # Total ticks spent in databus transfers
-system.physmem.totGap                        27877500                       # Total gap between requests
-system.physmem.totMemAccLat                  10235250                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totQLat                        2360250                       # Total ticks spent queuing
 system.physmem.wrQLenPdf::0                         0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::1                         0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::2                         0                       # What write queue length does an incoming req see
@@ -662,17 +182,497 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.writeReqs                            0                       # Number of write requests accepted
-system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
+system.physmem.bytesPerActivate::samples           64                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean             396                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     274.035894                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     327.902425                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127             10     15.62%     15.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255           17     26.56%     42.19% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383           12     18.75%     60.94% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511            7     10.94%     71.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639            3      4.69%     76.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767            2      3.12%     79.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895            3      4.69%     84.38% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151           10     15.62%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total             64                       # Bytes accessed per row activation
+system.physmem.totQLat                        2525000                       # Total ticks spent queuing
+system.physmem.totMemAccLat                  10400000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                      2100000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        6011.90                       # Average queueing delay per DRAM burst
+system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
+system.physmem.avgMemAccLat                  24761.90                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         963.06                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                      963.06                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
+system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
+system.physmem.busUtil                           7.52                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       7.52                       # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen                         1.22                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
+system.physmem.readRowHits                        348                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.physmem.readRowHitRate                   82.86                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
+system.physmem.avgGap                        66251.19                       # Average gap between requests
+system.physmem.pageHitRate                      82.86                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE            12000                       # Time in different power states
+system.physmem.memoryStateTime::REF            780000                       # Time in different power states
+system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
+system.physmem.memoryStateTime::ACT          22840500                       # Time in different power states
+system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
+system.membus.throughput                    963061159                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq                 377                       # Transaction distribution
+system.membus.trans_dist::ReadResp                377                       # Transaction distribution
+system.membus.trans_dist::ReadExReq                43                       # Transaction distribution
+system.membus.trans_dist::ReadExResp               43                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port          840                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                    840                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        26880                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total               26880                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus                  26880                       # Total data (bytes)
+system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy              484000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               1.7                       # Layer utilization (%)
+system.membus.respLayer1.occupancy            3924000                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization             14.1                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.cpu.branchPred.lookups                    1905                       # Number of BP lookups
+system.cpu.branchPred.condPredicted              1139                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect               341                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups                 1574                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                     325                       # Number of BTB hits
+system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.branchPred.BTBHitPct             20.648030                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                     223                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect                 16                       # Number of incorrect RAS predictions.
+system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
+system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
+system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
+system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
+system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
+system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
+system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
+system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
+system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
+system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
+system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
+system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
+system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
+system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
+system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
+system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
+system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.dtb.inst_hits                            0                       # ITB inst hits
+system.cpu.dtb.inst_misses                          0                       # ITB inst misses
+system.cpu.dtb.read_hits                            0                       # DTB read hits
+system.cpu.dtb.read_misses                          0                       # DTB read misses
+system.cpu.dtb.write_hits                           0                       # DTB write hits
+system.cpu.dtb.write_misses                         0                       # DTB write misses
+system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                        0                       # DTB read accesses
+system.cpu.dtb.write_accesses                       0                       # DTB write accesses
+system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.dtb.hits                                 0                       # DTB hits
+system.cpu.dtb.misses                               0                       # DTB misses
+system.cpu.dtb.accesses                             0                       # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
+system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
+system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
+system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
+system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
+system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
+system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
+system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
+system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
+system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
+system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
+system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
+system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
+system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
+system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
+system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
+system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.itb.inst_hits                            0                       # ITB inst hits
+system.cpu.itb.inst_misses                          0                       # ITB inst misses
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
+system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.itb.hits                                 0                       # DTB hits
+system.cpu.itb.misses                               0                       # DTB misses
+system.cpu.itb.accesses                             0                       # DTB accesses
+system.cpu.workload.num_syscalls                   13                       # Number of system calls
+system.cpu.numCycles                            55822                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.committedInsts                        4604                       # Number of instructions committed
+system.cpu.committedOps                          5390                       # Number of ops (including micro ops) committed
+system.cpu.discardedOps                          1208                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
+system.cpu.cpi                              12.124674                       # CPI: cycles per instruction
+system.cpu.ipc                               0.082476                       # IPC: instructions per cycle
+system.cpu.tickCycles                           10535                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                           45287                       # Total number of cycles that the object has spent stopped
+system.cpu.icache.tags.replacements                 3                       # number of replacements
+system.cpu.icache.tags.tagsinuse           162.198888                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs                1923                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs               321                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs              5.990654                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   162.198888                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.079199                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.079199                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          318                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          114                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          204                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.155273                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses              4809                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses             4809                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst         1923                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total            1923                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst          1923                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total             1923                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst         1923                       # number of overall hits
+system.cpu.icache.overall_hits::total            1923                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          321                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           321                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          321                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            321                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          321                       # number of overall misses
+system.cpu.icache.overall_misses::total           321                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     21494250                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     21494250                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     21494250                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     21494250                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     21494250                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     21494250                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst         2244                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total         2244                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst         2244                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total         2244                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst         2244                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total         2244                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.143048                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.143048                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.143048                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.143048                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.143048                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.143048                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66960.280374                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 66960.280374                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 66960.280374                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 66960.280374                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 66960.280374                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 66960.280374                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          321                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          321                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          321                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          321                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          321                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total          321                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     20721750                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     20721750                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     20721750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     20721750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     20721750                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     20721750                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.143048                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.143048                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.143048                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.143048                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.143048                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.143048                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 64553.738318                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 64553.738318                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 64553.738318                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 64553.738318                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 64553.738318                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 64553.738318                       # average overall mshr miss latency
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.toL2Bus.throughput              1070832288                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq            424                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp           424                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq           43                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp           43                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          642                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          292                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total               934                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        20544                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         9344                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total          29888                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus             29888                       # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy         233500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          0.8                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy        546750                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization          2.0                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy        234242                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization          0.8                       # Layer utilization (%)
+system.cpu.l2cache.tags.replacements                0                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse          195.954343                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs                 39                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs              377                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             0.103448                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   195.954343                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.005980                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.005980                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024          377                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          132                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          245                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.011505                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses             4156                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses            4156                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.inst           39                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total             39                       # number of ReadReq hits
+system.cpu.l2cache.demand_hits::cpu.inst           39                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total              39                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst           39                       # number of overall hits
+system.cpu.l2cache.overall_hits::total             39                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst          385                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total          385                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.inst           43                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total           43                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst          428                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total           428                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst          428                       # number of overall misses
+system.cpu.l2cache.overall_misses::total          428                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     26168000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total     26168000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst      2824000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total      2824000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     28992000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     28992000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     28992000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     28992000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst          424                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total          424                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.inst           43                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total           43                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst          467                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total          467                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst          467                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total          467                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.908019                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.908019                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst            1                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.916488                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.916488                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.916488                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.916488                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67968.831169                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 67968.831169                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 65674.418605                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65674.418605                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67738.317757                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 67738.317757                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67738.317757                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 67738.317757                       # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
+system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            8                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total            8                       # number of ReadReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst            8                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total            8                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst            8                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total            8                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          377                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total          377                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst           43                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total           43                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          420                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total          420                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          420                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total          420                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     20973000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total     20973000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst      2284000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      2284000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     23257000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     23257000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     23257000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     23257000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.889151                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.889151                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.899358                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.899358                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.899358                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.899358                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55631.299735                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55631.299735                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 53116.279070                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 53116.279070                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55373.809524                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55373.809524                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55373.809524                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55373.809524                       # average overall mshr miss latency
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu.dcache.tags.replacements                 0                       # number of replacements
+system.cpu.dcache.tags.tagsinuse            86.663656                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs                1919                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs               146                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             13.143836                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.inst    86.663656                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.inst     0.021158                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.021158                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024          146                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           38                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          108                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024     0.035645                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses              4348                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses             4348                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.inst         1051                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total            1051                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.inst          846                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total            846                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.inst           11                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total           11                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.inst           11                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total           11                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.inst          1897                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total             1897                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.inst         1897                       # number of overall hits
+system.cpu.dcache.overall_hits::total            1897                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.inst          115                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total           115                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.inst           67                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total           67                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.inst          182                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total            182                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.inst          182                       # number of overall misses
+system.cpu.dcache.overall_misses::total           182                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.inst      6958741                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total      6958741                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.inst      4586500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total      4586500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.inst     11545241                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     11545241                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.inst     11545241                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     11545241                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.inst         1166                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total         1166                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.inst          913                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total          913                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.inst           11                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total           11                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.inst           11                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total           11                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.inst         2079                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total         2079                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.inst         2079                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total         2079                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.inst     0.098628                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.098628                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.inst     0.073384                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.073384                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.inst     0.087542                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.087542                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.inst     0.087542                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.087542                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 60510.791304                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 60510.791304                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 68455.223881                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 68455.223881                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.inst 63435.390110                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 63435.390110                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.inst 63435.390110                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 63435.390110                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.ReadReq_mshr_hits::cpu.inst           12                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total           12                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.inst           24                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total           24                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.inst           36                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total           36                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.inst           36                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total           36                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.inst          103                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total          103                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.inst           43                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total           43                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.inst          146                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total          146                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.inst          146                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total          146                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst      6265258                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      6265258                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst      2867000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      2867000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.inst      9132258                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total      9132258                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.inst      9132258                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total      9132258                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst     0.088336                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.088336                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst     0.047097                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.047097                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.inst     0.070226                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.070226                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.inst     0.070226                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.070226                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 60827.747573                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60827.747573                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 66674.418605                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66674.418605                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 62549.712329                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 62549.712329                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 62549.712329                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 62549.712329                       # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt
index d39b9c7ba..a4baa9644 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt
@@ -1,52 +1,52 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000017                       # Number of seconds simulated
-sim_ticks                                    16786000                       # Number of ticks simulated
-final_tick                                   16786000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.000016                       # Number of seconds simulated
+sim_ticks                                    16223000                       # Number of ticks simulated
+final_tick                                   16223000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  36444                       # Simulator instruction rate (inst/s)
-host_op_rate                                    45472                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              133219523                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 259336                       # Number of bytes of host memory used
-host_seconds                                     0.13                       # Real time elapsed on the host
+host_inst_rate                                  32617                       # Simulator instruction rate (inst/s)
+host_op_rate                                    38195                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              115221437                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 253076                       # Number of bytes of host memory used
+host_seconds                                     0.14                       # Real time elapsed on the host
 sim_insts                                        4591                       # Number of instructions simulated
-sim_ops                                          5729                       # Number of ops (including micro ops) simulated
+sim_ops                                          5377                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst             17280                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst             17600                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data              7808                       # Number of bytes read from this memory
-system.physmem.bytes_read::total                25088                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        17280                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           17280                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst                270                       # Number of read requests responded to by this memory
+system.physmem.bytes_read::total                25408                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        17600                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           17600                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst                275                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data                122                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                   392                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst           1029429286                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            465149529                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              1494578816                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst      1029429286                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total         1029429286                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst          1029429286                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           465149529                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             1494578816                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                           392                       # Number of read requests accepted
+system.physmem.num_reads::total                   397                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst           1084879492                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            481291993                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              1566171485                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst      1084879492                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total         1084879492                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst          1084879492                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           481291993                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             1566171485                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                           397                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
-system.physmem.readBursts                         392                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                         397                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                    25088                       # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM                    25408                       # Total number of bytes read from DRAM
 system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
 system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                     25088                       # Total read bytes from the system interface side
+system.physmem.bytesReadSys                     25408                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
 system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                  86                       # Per bank write bursts
+system.physmem.perBankRdBursts::0                  90                       # Per bank write bursts
 system.physmem.perBankRdBursts::1                  46                       # Per bank write bursts
 system.physmem.perBankRdBursts::2                  20                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                  42                       # Per bank write bursts
-system.physmem.perBankRdBursts::4                  17                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                  33                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                  43                       # Per bank write bursts
+system.physmem.perBankRdBursts::4                  18                       # Per bank write bursts
+system.physmem.perBankRdBursts::5                  32                       # Per bank write bursts
 system.physmem.perBankRdBursts::6                  35                       # Per bank write bursts
 system.physmem.perBankRdBursts::7                  10                       # Per bank write bursts
 system.physmem.perBankRdBursts::8                   4                       # Per bank write bursts
@@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                        16721500                       # Total gap between requests
+system.physmem.totGap                        16156000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                     392                       # Read request sizes (log2)
+system.physmem.readPktSize::6                     397                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -90,13 +90,13 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                       208                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       121                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        42                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                        15                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                         4                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                       210                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       119                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        51                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                        14                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                         3                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
@@ -186,72 +186,71 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples           62                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      396.387097                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     264.062800                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     334.835382                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127             11     17.74%     17.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255           17     27.42%     45.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383            8     12.90%     58.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511            7     11.29%     69.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639            2      3.23%     72.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767            3      4.84%     77.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895            5      8.06%     85.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023            1      1.61%     87.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151            8     12.90%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total             62                       # Bytes accessed per row activation
-system.physmem.totQLat                        3300000                       # Total ticks spent queuing
-system.physmem.totMemAccLat                  10650000                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                      1960000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        8418.37                       # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples           63                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      396.190476                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     265.364013                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     334.900990                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127             12     19.05%     19.05% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255           16     25.40%     44.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383            8     12.70%     57.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511            9     14.29%     71.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639            3      4.76%     76.19% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767            2      3.17%     79.37% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895            3      4.76%     84.13% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151           10     15.87%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total             63                       # Bytes accessed per row activation
+system.physmem.totQLat                        2970000                       # Total ticks spent queuing
+system.physmem.totMemAccLat                  10413750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                      1985000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        7481.11                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  27168.37                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                        1494.58                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  26231.11                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                        1566.17                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                     1494.58                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                     1566.17                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                          11.68                       # Data bus utilization in percentage
-system.physmem.busUtilRead                      11.68                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                          12.24                       # Data bus utilization in percentage
+system.physmem.busUtilRead                      12.24                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.85                       # Average read queue length when enqueuing
+system.physmem.avgRdQLen                         1.84                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                        326                       # Number of row buffer hits during reads
+system.physmem.readRowHits                        331                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   83.16                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   83.38                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                        42656.89                       # Average gap between requests
-system.physmem.pageHitRate                      83.16                       # Row buffer hit rate, read and write combined
+system.physmem.avgGap                        40695.21                       # Average gap between requests
+system.physmem.pageHitRate                      83.38                       # Row buffer hit rate, read and write combined
 system.physmem.memoryStateTime::IDLE            11000                       # Time in different power states
 system.physmem.memoryStateTime::REF            520000                       # Time in different power states
 system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
 system.physmem.memoryStateTime::ACT          15315250                       # Time in different power states
 system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.membus.throughput                   1494578816                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq                 350                       # Transaction distribution
-system.membus.trans_dist::ReadResp                350                       # Transaction distribution
+system.membus.throughput                   1566171485                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq                 355                       # Transaction distribution
+system.membus.trans_dist::ReadResp                355                       # Transaction distribution
 system.membus.trans_dist::ReadExReq                42                       # Transaction distribution
 system.membus.trans_dist::ReadExResp               42                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port          784                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                    784                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        25088                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total               25088                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus                  25088                       # Total data (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port          794                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                    794                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        25408                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total               25408                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus                  25408                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy              479500                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               2.9                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            3655500                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization             21.8                       # Layer utilization (%)
+system.membus.reqLayer0.occupancy              494500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               3.0                       # Layer utilization (%)
+system.membus.respLayer1.occupancy            3699500                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization             22.8                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.branchPred.lookups                    2517                       # Number of BP lookups
-system.cpu.branchPred.condPredicted              1805                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect               482                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups                 2002                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                     714                       # Number of BTB hits
+system.cpu.branchPred.lookups                    2638                       # Number of BP lookups
+system.cpu.branchPred.condPredicted              1635                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect               480                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups                 2101                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                     783                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             35.664336                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                     294                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect                 71                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             37.267968                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                     354                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect                 68                       # Number of incorrect RAS predictions.
 system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.checker.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -337,7 +336,7 @@ system.cpu.checker.itb.hits                         0                       # DT
 system.cpu.checker.itb.misses                       0                       # DTB misses
 system.cpu.checker.itb.accesses                     0                       # DTB accesses
 system.cpu.workload.num_syscalls                   13                       # Number of system calls
-system.cpu.checker.numCycles                     5742                       # number of cpu cycles simulated
+system.cpu.checker.numCycles                     5390                       # number of cpu cycles simulated
 system.cpu.checker.numWorkItemsStarted              0                       # number of work items this cpu started
 system.cpu.checker.numWorkItemsCompleted            0                       # number of work items this cpu completed
 system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
@@ -424,489 +423,491 @@ system.cpu.itb.inst_accesses                        0                       # IT
 system.cpu.itb.hits                                 0                       # DTB hits
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
-system.cpu.numCycles                            33573                       # number of cpu cycles simulated
+system.cpu.numCycles                            32447                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles               6921                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                          12073                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                        2517                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches               1008                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                          2659                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                    1630                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles                   2378                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.PendingTrapStallCycles             7                       # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines                      1968                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                   288                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples              13089                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.162808                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.572483                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles               7786                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                          12484                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                        2638                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches               1137                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                          4850                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                    1010                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles                    3                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles           259                       # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles           30                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                      2068                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                   320                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples              13433                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.098935                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.478489                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                    10430     79.69%     79.69% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                      226      1.73%     81.41% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                      203      1.55%     82.96% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                      238      1.82%     84.78% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                      231      1.76%     86.55% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                      269      2.06%     88.60% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                       93      0.71%     89.31% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                      145      1.11%     90.42% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                     1254      9.58%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                    10743     79.97%     79.97% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                      265      1.97%     81.95% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                      241      1.79%     83.74% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                      235      1.75%     85.49% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                      238      1.77%     87.26% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                      291      2.17%     89.43% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                      141      1.05%     90.48% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                      175      1.30%     91.78% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                     1104      8.22%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total                13089                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.074971                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.359604                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                     6910                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles                  2688                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                      2492                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles                    31                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                    968                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved                  385                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                   160                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts                  13358                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                   539                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                    968                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                     7139                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                     151                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles           2277                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                      2296                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles                   258                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts                  12614                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                     4                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                     32                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                     27                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                    195                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands               12625                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups                 57590                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups            52228                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups                47                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps                  5673                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                     6952                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts                 41                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts             38                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                       329                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads                 2826                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores                1583                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads                38                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores               13                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                      11316                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                  49                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                      8961                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued               149                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined            5288                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined        14803                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved             12                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples         13089                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.684621                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.402607                       # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total                13433                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.081302                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.384751                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                     6529                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles                  4272                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                      2145                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles                   138                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                    349                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved                  390                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                   163                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts                  12118                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                   476                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                    349                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                     6736                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                     846                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles           2304                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                      2064                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles                  1134                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts                  11483                       # Number of instructions processed by rename
+system.cpu.rename.IQFullEvents                    163                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                    117                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents                    963                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands               11820                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups                 52846                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups            12757                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups                88                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps                  5494                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                     6326                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts                 43                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts             37                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                       443                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads                 2313                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores                1639                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads                32                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores               28                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                      10354                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                  46                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                      8358                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued                56                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined            4760                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined        12835                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved              9                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples         13433                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.622199                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.376807                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0                9594     73.30%     73.30% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1                1210      9.24%     82.54% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2                 823      6.29%     88.83% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3                 494      3.77%     92.60% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4                 479      3.66%     96.26% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5                 298      2.28%     98.54% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6                 131      1.00%     99.54% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7                  49      0.37%     99.92% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8                  11      0.08%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0               10179     75.78%     75.78% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1                1183      8.81%     84.58% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2                 748      5.57%     90.15% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3                 453      3.37%     93.52% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4                 362      2.69%     96.22% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                 286      2.13%     98.35% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6                 135      1.00%     99.35% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7                  64      0.48%     99.83% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8                  23      0.17%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total           13089                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total           13433                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                       6      2.71%      2.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%      2.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      2.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      2.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      2.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      2.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      2.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      2.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      2.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      2.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      2.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      2.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      2.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      2.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      2.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      2.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      2.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      2.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      2.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      2.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      2.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      2.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      2.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      2.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      2.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      2.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      2.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      2.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      2.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                    138     62.44%     65.16% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                    77     34.84%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                       9      5.33%      5.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      5.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      5.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      5.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      5.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      5.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      5.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      5.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      5.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      5.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      5.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      5.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      5.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      5.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      5.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      5.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      5.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      5.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      5.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      5.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      5.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      5.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      5.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      5.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      5.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      5.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      5.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      5.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      5.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                     80     47.34%     52.66% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                    80     47.34%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu                  5369     59.92%     59.92% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                    9      0.10%     60.02% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     60.02% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     60.02% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     60.02% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     60.02% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     60.02% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     60.02% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     60.02% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     60.02% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     60.02% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     60.02% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     60.02% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     60.02% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     60.02% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     60.02% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     60.02% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     60.02% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     60.02% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     60.02% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     60.02% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     60.02% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     60.02% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     60.02% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     60.02% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              3      0.03%     60.05% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     60.05% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     60.05% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     60.05% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead                 2357     26.30%     86.35% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite                1223     13.65%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu                  5041     60.31%     60.31% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                    6      0.07%     60.39% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     60.39% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     60.39% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     60.39% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     60.39% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     60.39% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     60.39% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     60.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     60.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     60.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     60.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     60.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     60.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     60.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     60.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     60.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     60.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     60.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     60.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     60.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     60.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     60.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     60.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     60.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              3      0.04%     60.42% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     60.42% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     60.42% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     60.42% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead                 2009     24.04%     84.46% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite                1299     15.54%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total                   8961                       # Type of FU issued
-system.cpu.iq.rate                           0.266911                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                         221                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.024662                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads              31345                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes             16624                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses         8077                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads                  36                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes                 48                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses           16                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses                   9162                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                      20                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads               60                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total                   8358                       # Type of FU issued
+system.cpu.iq.rate                           0.257589                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                         169                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.020220                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads              30275                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes             15052                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses         7570                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads                  99                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes                128                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses           31                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses                   8484                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                      43                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads               25                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads         1626                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.squashedLoads         1286                       # Number of loads squashed
 system.cpu.iew.lsq.thread0.ignoredResponses            0                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation           21                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores          645                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.memOrderViolation           20                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores          701                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked             3                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads           39                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked             8                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                    968                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                     113                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                    19                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts               11366                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts               115                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts                  2826                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts                 1583                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts                 37                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                      9                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles                    349                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                     800                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                    25                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts               10411                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts               110                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts                  2313                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts                 1639                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts                 34                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                     13                       # Number of times the IQ has become full, causing a stall
 system.cpu.iew.iewLSQFullEvents                    10                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents             21                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect            110                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect          266                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts                  376                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts                  8568                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts                  2160                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts               393                       # Number of squashed instructions skipped in execute
+system.cpu.iew.memOrderViolationEvents             20                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect            112                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect          252                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts                  364                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts                  8063                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts                  1908                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts               295                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                             1                       # number of nop insts executed
-system.cpu.iew.exec_refs                         3332                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                     1443                       # Number of branches executed
-system.cpu.iew.exec_stores                       1172                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.255205                       # Inst execution rate
-system.cpu.iew.wb_sent                           8256                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                          8093                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                      3919                       # num instructions producing a value
-system.cpu.iew.wb_consumers                      8062                       # num instructions consuming a value
+system.cpu.iew.exec_nop                            11                       # number of nop insts executed
+system.cpu.iew.exec_refs                         3148                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                     1457                       # Number of branches executed
+system.cpu.iew.exec_stores                       1240                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.248498                       # Inst execution rate
+system.cpu.iew.wb_sent                           7735                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                          7601                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                      3572                       # num instructions producing a value
+system.cpu.iew.wb_consumers                      6998                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.241057                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.486108                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       0.234259                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.510432                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts            5642                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts            5037                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls              37                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts               326                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples        12121                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.472651                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.325156                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts               324                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples        12552                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.428378                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.273949                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0         9924     81.87%     81.87% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1          978      8.07%     89.94% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2          402      3.32%     93.26% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3          224      1.85%     95.11% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4          175      1.44%     96.55% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5          212      1.75%     98.30% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6           50      0.41%     98.71% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7           33      0.27%     98.99% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8          123      1.01%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0        10495     83.61%     83.61% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1          893      7.11%     90.73% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2          426      3.39%     94.12% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3          211      1.68%     95.80% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4          111      0.88%     96.69% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5          212      1.69%     98.37% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6           50      0.40%     98.77% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7           37      0.29%     99.07% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8          117      0.93%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total        12121                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total        12552                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts                 4591                       # Number of instructions committed
-system.cpu.commit.committedOps                   5729                       # Number of ops (including micro ops) committed
+system.cpu.commit.committedOps                   5377                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                           2138                       # Number of memory references committed
-system.cpu.commit.loads                          1200                       # Number of loads committed
+system.cpu.commit.refs                           1965                       # Number of memory references committed
+system.cpu.commit.loads                          1027                       # Number of loads committed
 system.cpu.commit.membars                          12                       # Number of memory barriers committed
 system.cpu.commit.branches                       1007                       # Number of branches committed
 system.cpu.commit.fp_insts                         16                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                      4976                       # Number of committed integer instructions.
+system.cpu.commit.int_insts                      4624                       # Number of committed integer instructions.
 system.cpu.commit.function_calls                   82                       # Number of function calls committed.
 system.cpu.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu             3584     62.56%     62.56% # Class of committed instruction
-system.cpu.commit.op_class_0::IntMult               4      0.07%     62.63% # Class of committed instruction
-system.cpu.commit.op_class_0::IntDiv                0      0.00%     62.63% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatAdd              0      0.00%     62.63% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatCmp              0      0.00%     62.63% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatCvt              0      0.00%     62.63% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMult             0      0.00%     62.63% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatDiv              0      0.00%     62.63% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     62.63% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAdd               0      0.00%     62.63% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     62.63% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAlu               0      0.00%     62.63% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdCmp               0      0.00%     62.63% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdCvt               0      0.00%     62.63% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMisc              0      0.00%     62.63% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMult              0      0.00%     62.63% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     62.63% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdShift             0      0.00%     62.63% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     62.63% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     62.63% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     62.63% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     62.63% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     62.63% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     62.63% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     62.63% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMisc            3      0.05%     62.68% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     62.68% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     62.68% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     62.68% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead            1200     20.95%     83.63% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite            938     16.37%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu             3405     63.33%     63.33% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult               4      0.07%     63.40% # Class of committed instruction
+system.cpu.commit.op_class_0::IntDiv                0      0.00%     63.40% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatAdd              0      0.00%     63.40% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCmp              0      0.00%     63.40% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCvt              0      0.00%     63.40% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatMult             0      0.00%     63.40% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatDiv              0      0.00%     63.40% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     63.40% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAdd               0      0.00%     63.40% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     63.40% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAlu               0      0.00%     63.40% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCmp               0      0.00%     63.40% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCvt               0      0.00%     63.40% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMisc              0      0.00%     63.40% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMult              0      0.00%     63.40% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     63.40% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShift             0      0.00%     63.40% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     63.40% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     63.40% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     63.40% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     63.40% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     63.40% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     63.40% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     63.40% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMisc            3      0.06%     63.46% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     63.46% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     63.46% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     63.46% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead            1027     19.10%     82.56% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite            938     17.44%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total              5729                       # Class of committed instruction
-system.cpu.commit.bw_lim_events                   123                       # number cycles where commit BW limit reached
+system.cpu.commit.op_class_0::total              5377                       # Class of committed instruction
+system.cpu.commit.bw_lim_events                   117                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                        23212                       # The number of ROB reads
-system.cpu.rob.rob_writes                       23723                       # The number of ROB writes
-system.cpu.timesIdled                             215                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           20484                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads                        22692                       # The number of ROB reads
+system.cpu.rob.rob_writes                       21719                       # The number of ROB writes
+system.cpu.timesIdled                             209                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           19014                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                        4591                       # Number of Instructions Simulated
-system.cpu.committedOps                          5729                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               7.312786                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         7.312786                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.136747                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.136747                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                    39407                       # number of integer regfile reads
-system.cpu.int_regfile_writes                    7992                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                        16                       # number of floating regfile reads
-system.cpu.misc_regfile_reads                    3253                       # number of misc regfile reads
+system.cpu.committedOps                          5377                       # Number of Ops (including micro ops) Simulated
+system.cpu.cpi                               7.067523                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         7.067523                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.141492                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.141492                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                     7944                       # number of integer regfile reads
+system.cpu.int_regfile_writes                    4420                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                        31                       # number of floating regfile reads
+system.cpu.cc_regfile_reads                     28734                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                     3302                       # number of cc regfile writes
+system.cpu.misc_regfile_reads                    3189                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                     24                       # number of misc regfile writes
-system.cpu.toL2Bus.throughput              1662337662                       # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq            395                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp           394                       # Transaction distribution
+system.cpu.toL2Bus.throughput              1735807187                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq            399                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp           398                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq           42                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp           42                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          577                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          588                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          293                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total               870                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        18368                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total               881                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        18816                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         9344                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total          27712                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus             27712                       # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus          192                       # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy         218500                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          1.3                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy        480500                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          2.9                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy        229495                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.tot_pkt_size::total          28160                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus             28160                       # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy         220500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          1.4                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy        488250                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization          3.0                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy        228495                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          1.4                       # Layer utilization (%)
 system.cpu.icache.tags.replacements                 1                       # number of replacements
-system.cpu.icache.tags.tagsinuse           148.488883                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs                1601                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs               290                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs              5.520690                       # Average number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse           150.758993                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs                1666                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs               294                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs              5.666667                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   148.488883                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.072504                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.072504                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024          289                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          170                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          119                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.141113                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses              4226                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses             4226                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst         1601                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total            1601                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst          1601                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total             1601                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst         1601                       # number of overall hits
-system.cpu.icache.overall_hits::total            1601                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst          367                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total           367                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst          367                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total            367                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst          367                       # number of overall misses
-system.cpu.icache.overall_misses::total           367                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     23960000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     23960000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     23960000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     23960000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     23960000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     23960000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst         1968                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total         1968                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst         1968                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total         1968                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst         1968                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total         1968                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.186484                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.186484                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.186484                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.186484                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.186484                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.186484                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 65286.103542                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 65286.103542                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 65286.103542                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 65286.103542                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 65286.103542                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 65286.103542                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs          107                       # number of cycles access was blocked
+system.cpu.icache.tags.occ_blocks::cpu.inst   150.758993                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.073613                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.073613                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          293                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          173                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          120                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.143066                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses              4430                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses             4430                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst         1666                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total            1666                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst          1666                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total             1666                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst         1666                       # number of overall hits
+system.cpu.icache.overall_hits::total            1666                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          402                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           402                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          402                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            402                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          402                       # number of overall misses
+system.cpu.icache.overall_misses::total           402                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     25574000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     25574000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     25574000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     25574000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     25574000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     25574000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst         2068                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total         2068                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst         2068                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total         2068                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst         2068                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total         2068                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.194391                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.194391                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.194391                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.194391                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.194391                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.194391                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 63616.915423                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 63616.915423                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 63616.915423                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 63616.915423                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 63616.915423                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 63616.915423                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs          298                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                 2                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 5                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    53.500000                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    59.600000                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst           77                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total           77                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst           77                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total           77                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst           77                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total           77                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst          290                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total          290                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst          290                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total          290                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst          290                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total          290                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     19152500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     19152500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     19152500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     19152500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     19152500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     19152500                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.147358                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.147358                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.147358                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.147358                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.147358                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.147358                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66043.103448                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66043.103448                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66043.103448                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 66043.103448                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66043.103448                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 66043.103448                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst          108                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total          108                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst          108                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total          108                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst          108                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total          108                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          294                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          294                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          294                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          294                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          294                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total          294                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     19742750                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     19742750                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     19742750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     19742750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     19742750                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     19742750                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.142166                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.142166                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.142166                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.142166                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.142166                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.142166                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67152.210884                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67152.210884                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67152.210884                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 67152.210884                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67152.210884                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 67152.210884                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse          185.364644                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs                 37                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs              350                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             0.105714                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.tagsinuse          188.170247                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs                 39                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs              355                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             0.109859                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   138.907401                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data    46.457243                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.004239                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.001418                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.005657                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024          350                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          194                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          156                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.010681                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses             3864                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses            3864                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst           17                       # number of ReadReq hits
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   141.371533                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data    46.798714                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.004314                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.001428                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.005743                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024          355                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          198                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          157                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.010834                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses             3925                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses            3925                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.inst           19                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data           20                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total             37                       # number of ReadReq hits
-system.cpu.l2cache.demand_hits::cpu.inst           17                       # number of demand (read+write) hits
+system.cpu.l2cache.ReadReq_hits::total             39                       # number of ReadReq hits
+system.cpu.l2cache.demand_hits::cpu.inst           19                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::cpu.data           20                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total              37                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst           17                       # number of overall hits
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+system.cpu.l2cache.overall_hits::cpu.inst           19                       # number of overall hits
 system.cpu.l2cache.overall_hits::cpu.data           20                       # number of overall hits
-system.cpu.l2cache.overall_hits::total             37                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst          270                       # number of ReadReq misses
+system.cpu.l2cache.overall_hits::total             39                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst          275                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_misses::cpu.data           85                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total          355                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total          360                       # number of ReadReq misses
 system.cpu.l2cache.ReadExReq_misses::cpu.data           42                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total           42                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst          270                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.inst          275                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::cpu.data          127                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total           397                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst          270                       # number of overall misses
+system.cpu.l2cache.demand_misses::total           402                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst          275                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data          127                       # number of overall misses
-system.cpu.l2cache.overall_misses::total          397                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     18683000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data      6637250                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total     25320250                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      3108750                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total      3108750                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     18683000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data      9746000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     28429000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     18683000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data      9746000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     28429000                       # number of overall miss cycles
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+system.cpu.l2cache.demand_miss_latency::cpu.inst     19251250                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data      9112500                       # number of demand (read+write) miss cycles
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+system.cpu.l2cache.overall_miss_latency::cpu.inst     19251250                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data      9112500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     28363750                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst          294                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::cpu.data          105                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total          392                       # number of ReadReq accesses(hits+misses)
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 system.cpu.l2cache.ReadExReq_accesses::cpu.data           42                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total           42                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst          287                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst          294                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::cpu.data          147                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total          434                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst          287                       # number of overall (read+write) accesses
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 system.cpu.l2cache.overall_accesses::cpu.data          147                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total          434                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.940767                       # miss rate for ReadReq accesses
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+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.935374                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.809524                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.905612                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.902256                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.940767                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.935374                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.data     0.863946                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.914747                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.940767                       # miss rate for overall accesses
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+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.935374                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.863946                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.914747                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69196.296296                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78085.294118                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 71324.647887                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74017.857143                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74017.857143                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69196.296296                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76740.157480                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 71609.571788                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69196.296296                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76740.157480                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 71609.571788                       # average overall miss latency
+system.cpu.l2cache.overall_miss_rate::total     0.911565                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70004.545455                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70714.705882                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 70172.222222                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73851.190476                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73851.190476                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70004.545455                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71751.968504                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 70556.592040                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70004.545455                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71751.968504                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 70556.592040                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -921,148 +922,148 @@ system.cpu.l2cache.demand_mshr_hits::cpu.data            5
 system.cpu.l2cache.demand_mshr_hits::total            5                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.overall_mshr_hits::cpu.data            5                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::total            5                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          270                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          275                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadReq_mshr_misses::cpu.data           80                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total          350                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total          355                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           42                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total           42                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst          270                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          275                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.data          122                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total          392                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst          270                       # number of overall MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total          397                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          275                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data          122                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total          392                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     15291000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      5345250                       # number of ReadReq MSHR miss cycles
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-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      2596250                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      2596250                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     15291000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      7941500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     23232500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     15291000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      7941500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     23232500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.940767                       # mshr miss rate for ReadReq accesses
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+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     15797750                       # number of ReadReq MSHR miss cycles
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+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     15797750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      7325250                       # number of demand (read+write) MSHR miss cycles
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 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.761905                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.892857                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.889724                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.940767                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.935374                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.829932                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.903226                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.940767                       # mshr miss rate for overall accesses
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 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.829932                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.903226                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56633.333333                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66815.625000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58960.714286                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61815.476190                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61815.476190                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56633.333333                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65094.262295                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59266.581633                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56633.333333                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65094.262295                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59266.581633                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.900227                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57446.363636                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data        59200                       # average ReadReq mshr miss latency
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+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61648.809524                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61648.809524                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57446.363636                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60043.032787                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58244.332494                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57446.363636                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60043.032787                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58244.332494                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.dcache.tags.replacements                 0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse            87.019573                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs                2400                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse            87.133302                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs                2168                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs               146                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             16.438356                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             14.849315                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data    87.019573                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.021245                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.021245                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data    87.133302                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.021273                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.021273                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          146                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           61                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1           85                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           67                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           79                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024     0.035645                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses              5964                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses             5964                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data         1782                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total            1782                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data          596                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total            596                       # number of WriteReq hits
+system.cpu.dcache.tags.tag_accesses              5528                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses             5528                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data         1551                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total            1551                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data          595                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total            595                       # number of WriteReq hits
 system.cpu.dcache.LoadLockedReq_hits::cpu.data           11                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total           11                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data           11                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total           11                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data          2378                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total             2378                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data         2378                       # number of overall hits
-system.cpu.dcache.overall_hits::total            2378                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data          190                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total           190                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data          317                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total          317                       # number of WriteReq misses
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+system.cpu.dcache.WriteReq_misses::total          318                       # number of WriteReq misses
 system.cpu.dcache.LoadLockedReq_misses::cpu.data            2                       # number of LoadLockedReq misses
 system.cpu.dcache.LoadLockedReq_misses::total            2                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data          507                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total            507                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data          507                       # number of overall misses
-system.cpu.dcache.overall_misses::total           507                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data     11613493                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     11613493                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data     20684250                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total     20684250                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       130000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total       130000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     32297743                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     32297743                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     32297743                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     32297743                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data         1972                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total         1972                       # number of ReadReq accesses(hits+misses)
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+system.cpu.dcache.ReadReq_miss_latency::total     11351493                       # number of ReadReq miss cycles
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+system.cpu.dcache.WriteReq_miss_latency::total     20745500                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       130500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total       130500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     32096993                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     32096993                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     32096993                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     32096993                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data         1754                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total         1754                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data          913                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total          913                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::cpu.data           13                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::total           13                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data           11                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total           11                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data         2885                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total         2885                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data         2885                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total         2885                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.096349                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.096349                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.347207                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.347207                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_accesses::cpu.data         2667                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total         2667                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data         2667                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total         2667                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.115735                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.115735                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.348302                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.348302                       # miss rate for WriteReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.153846                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::total     0.153846                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.175737                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.175737                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.175737                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.175737                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 61123.647368                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 61123.647368                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data        65250                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total        65250                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        65000                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        65000                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 63703.635108                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 63703.635108                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 63703.635108                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 63703.635108                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs          118                       # number of cycles access was blocked
+system.cpu.dcache.demand_miss_rate::cpu.data     0.195351                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.195351                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.195351                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.195351                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55918.684729                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 55918.684729                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65237.421384                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 65237.421384                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        65250                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        65250                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 61606.512476                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 61606.512476                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 61606.512476                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 61606.512476                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs          105                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                 3                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 4                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    39.333333                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    26.250000                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data           85                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total           85                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data          275                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total          275                       # number of WriteReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data           98                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total           98                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data          276                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total          276                       # number of WriteReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            2                       # number of LoadLockedReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::total            2                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data          360                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total          360                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data          360                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total          360                       # number of overall MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data          374                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total          374                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data          374                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total          374                       # number of overall MSHR hits
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data          105                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total          105                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data           42                       # number of WriteReq MSHR misses
@@ -1071,30 +1072,30 @@ system.cpu.dcache.demand_mshr_misses::cpu.data          147
 system.cpu.dcache.demand_mshr_misses::total          147                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data          147                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total          147                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      6871755                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      6871755                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      3151750                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      3151750                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data     10023505                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total     10023505                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data     10023505                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total     10023505                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.053245                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.053245                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      6245255                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      6245255                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      3144750                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      3144750                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data      9390005                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total      9390005                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data      9390005                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total      9390005                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.059863                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.059863                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.046002                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.046002                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.050953                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.050953                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.050953                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.050953                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 65445.285714                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 65445.285714                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75041.666667                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75041.666667                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68187.108844                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 68187.108844                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68187.108844                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 68187.108844                       # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.055118                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.055118                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.055118                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.055118                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 59478.619048                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 59478.619048                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data        74875                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total        74875                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 63877.585034                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 63877.585034                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 63877.585034                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 63877.585034                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt
index 4a87577c2..adfd7b504 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt
@@ -1,52 +1,52 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000017                       # Number of seconds simulated
-sim_ticks                                    16786000                       # Number of ticks simulated
-final_tick                                   16786000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.000016                       # Number of seconds simulated
+sim_ticks                                    16223000                       # Number of ticks simulated
+final_tick                                   16223000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  42967                       # Simulator instruction rate (inst/s)
-host_op_rate                                    53611                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              157060125                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 258920                       # Number of bytes of host memory used
-host_seconds                                     0.11                       # Real time elapsed on the host
+host_inst_rate                                  35590                       # Simulator instruction rate (inst/s)
+host_op_rate                                    41676                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              125719954                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 252016                       # Number of bytes of host memory used
+host_seconds                                     0.13                       # Real time elapsed on the host
 sim_insts                                        4591                       # Number of instructions simulated
-sim_ops                                          5729                       # Number of ops (including micro ops) simulated
+sim_ops                                          5377                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst             17280                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst             17600                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data              7808                       # Number of bytes read from this memory
-system.physmem.bytes_read::total                25088                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        17280                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           17280                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst                270                       # Number of read requests responded to by this memory
+system.physmem.bytes_read::total                25408                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        17600                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           17600                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst                275                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data                122                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                   392                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst           1029429286                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            465149529                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              1494578816                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst      1029429286                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total         1029429286                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst          1029429286                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           465149529                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             1494578816                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                           392                       # Number of read requests accepted
+system.physmem.num_reads::total                   397                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst           1084879492                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            481291993                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              1566171485                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst      1084879492                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total         1084879492                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst          1084879492                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           481291993                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             1566171485                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                           397                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
-system.physmem.readBursts                         392                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                         397                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                    25088                       # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM                    25408                       # Total number of bytes read from DRAM
 system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
 system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                     25088                       # Total read bytes from the system interface side
+system.physmem.bytesReadSys                     25408                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
 system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                  86                       # Per bank write bursts
+system.physmem.perBankRdBursts::0                  90                       # Per bank write bursts
 system.physmem.perBankRdBursts::1                  46                       # Per bank write bursts
 system.physmem.perBankRdBursts::2                  20                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                  42                       # Per bank write bursts
-system.physmem.perBankRdBursts::4                  17                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                  33                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                  43                       # Per bank write bursts
+system.physmem.perBankRdBursts::4                  18                       # Per bank write bursts
+system.physmem.perBankRdBursts::5                  32                       # Per bank write bursts
 system.physmem.perBankRdBursts::6                  35                       # Per bank write bursts
 system.physmem.perBankRdBursts::7                  10                       # Per bank write bursts
 system.physmem.perBankRdBursts::8                   4                       # Per bank write bursts
@@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                        16721500                       # Total gap between requests
+system.physmem.totGap                        16156000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                     392                       # Read request sizes (log2)
+system.physmem.readPktSize::6                     397                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -90,13 +90,13 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                       208                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       121                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        42                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                        15                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                         4                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                       210                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       119                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        51                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                        14                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                         3                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
@@ -186,72 +186,71 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples           62                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      396.387097                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     264.062800                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     334.835382                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127             11     17.74%     17.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255           17     27.42%     45.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383            8     12.90%     58.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511            7     11.29%     69.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639            2      3.23%     72.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767            3      4.84%     77.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895            5      8.06%     85.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023            1      1.61%     87.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151            8     12.90%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total             62                       # Bytes accessed per row activation
-system.physmem.totQLat                        3300000                       # Total ticks spent queuing
-system.physmem.totMemAccLat                  10650000                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                      1960000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        8418.37                       # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples           63                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      396.190476                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     265.364013                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     334.900990                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127             12     19.05%     19.05% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255           16     25.40%     44.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383            8     12.70%     57.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511            9     14.29%     71.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639            3      4.76%     76.19% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767            2      3.17%     79.37% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895            3      4.76%     84.13% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151           10     15.87%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total             63                       # Bytes accessed per row activation
+system.physmem.totQLat                        2970000                       # Total ticks spent queuing
+system.physmem.totMemAccLat                  10413750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                      1985000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        7481.11                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  27168.37                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                        1494.58                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  26231.11                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                        1566.17                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                     1494.58                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                     1566.17                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                          11.68                       # Data bus utilization in percentage
-system.physmem.busUtilRead                      11.68                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                          12.24                       # Data bus utilization in percentage
+system.physmem.busUtilRead                      12.24                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.85                       # Average read queue length when enqueuing
+system.physmem.avgRdQLen                         1.84                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                        326                       # Number of row buffer hits during reads
+system.physmem.readRowHits                        331                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   83.16                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   83.38                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                        42656.89                       # Average gap between requests
-system.physmem.pageHitRate                      83.16                       # Row buffer hit rate, read and write combined
+system.physmem.avgGap                        40695.21                       # Average gap between requests
+system.physmem.pageHitRate                      83.38                       # Row buffer hit rate, read and write combined
 system.physmem.memoryStateTime::IDLE            11000                       # Time in different power states
 system.physmem.memoryStateTime::REF            520000                       # Time in different power states
 system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
 system.physmem.memoryStateTime::ACT          15315250                       # Time in different power states
 system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.membus.throughput                   1494578816                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq                 350                       # Transaction distribution
-system.membus.trans_dist::ReadResp                350                       # Transaction distribution
+system.membus.throughput                   1566171485                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq                 355                       # Transaction distribution
+system.membus.trans_dist::ReadResp                355                       # Transaction distribution
 system.membus.trans_dist::ReadExReq                42                       # Transaction distribution
 system.membus.trans_dist::ReadExResp               42                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port          784                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                    784                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        25088                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total               25088                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus                  25088                       # Total data (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port          794                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                    794                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        25408                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total               25408                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus                  25408                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy              479500                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               2.9                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            3655500                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization             21.8                       # Layer utilization (%)
+system.membus.reqLayer0.occupancy              494500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               3.0                       # Layer utilization (%)
+system.membus.respLayer1.occupancy            3699500                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization             22.8                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.branchPred.lookups                    2517                       # Number of BP lookups
-system.cpu.branchPred.condPredicted              1805                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect               482                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups                 2002                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                     714                       # Number of BTB hits
+system.cpu.branchPred.lookups                    2638                       # Number of BP lookups
+system.cpu.branchPred.condPredicted              1635                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect               480                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups                 2101                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                     783                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             35.664336                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                     294                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect                 71                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             37.267968                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                     354                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect                 68                       # Number of incorrect RAS predictions.
 system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -337,489 +336,491 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                   13                       # Number of system calls
-system.cpu.numCycles                            33573                       # number of cpu cycles simulated
+system.cpu.numCycles                            32447                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles               6921                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                          12073                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                        2517                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches               1008                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                          2659                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                    1630                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles                   2378                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.PendingTrapStallCycles             7                       # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines                      1968                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                   288                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples              13089                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.162808                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.572483                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles               7786                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                          12484                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                        2638                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches               1137                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                          4850                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                    1010                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles                    3                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles           259                       # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles           30                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                      2068                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                   320                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples              13433                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.098935                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.478489                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                    10430     79.69%     79.69% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                      226      1.73%     81.41% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                      203      1.55%     82.96% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                      238      1.82%     84.78% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                      231      1.76%     86.55% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                      269      2.06%     88.60% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                       93      0.71%     89.31% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                      145      1.11%     90.42% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                     1254      9.58%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                    10743     79.97%     79.97% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                      265      1.97%     81.95% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                      241      1.79%     83.74% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                      235      1.75%     85.49% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                      238      1.77%     87.26% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                      291      2.17%     89.43% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                      141      1.05%     90.48% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                      175      1.30%     91.78% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                     1104      8.22%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total                13089                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.074971                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.359604                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                     6910                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles                  2688                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                      2492                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles                    31                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                    968                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved                  385                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                   160                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts                  13358                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                   539                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                    968                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                     7139                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                     151                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles           2277                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                      2296                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles                   258                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts                  12614                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                     4                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                     32                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                     27                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                    195                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands               12625                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups                 57590                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups            52228                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups                47                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps                  5673                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                     6952                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts                 41                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts             38                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                       329                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads                 2826                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores                1583                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads                38                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores               13                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                      11316                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                  49                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                      8961                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued               149                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined            5288                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined        14803                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved             12                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples         13089                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.684621                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.402607                       # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total                13433                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.081302                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.384751                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                     6529                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles                  4272                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                      2145                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles                   138                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                    349                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved                  390                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                   163                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts                  12118                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                   476                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                    349                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                     6736                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                     846                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles           2304                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                      2064                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles                  1134                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts                  11483                       # Number of instructions processed by rename
+system.cpu.rename.IQFullEvents                    163                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                    117                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents                    963                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands               11820                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups                 52846                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups            12757                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups                88                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps                  5494                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                     6326                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts                 43                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts             37                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                       443                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads                 2313                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores                1639                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads                32                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores               28                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                      10354                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                  46                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                      8358                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued                56                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined            4760                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined        12835                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved              9                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples         13433                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.622199                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.376807                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0                9594     73.30%     73.30% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1                1210      9.24%     82.54% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2                 823      6.29%     88.83% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3                 494      3.77%     92.60% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4                 479      3.66%     96.26% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5                 298      2.28%     98.54% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6                 131      1.00%     99.54% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7                  49      0.37%     99.92% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8                  11      0.08%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0               10179     75.78%     75.78% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1                1183      8.81%     84.58% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2                 748      5.57%     90.15% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3                 453      3.37%     93.52% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4                 362      2.69%     96.22% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                 286      2.13%     98.35% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6                 135      1.00%     99.35% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7                  64      0.48%     99.83% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8                  23      0.17%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total           13089                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total           13433                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                       6      2.71%      2.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%      2.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      2.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      2.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      2.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      2.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      2.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      2.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      2.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      2.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      2.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      2.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      2.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      2.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      2.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      2.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      2.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      2.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      2.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      2.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      2.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      2.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      2.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      2.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      2.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      2.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      2.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      2.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      2.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                    138     62.44%     65.16% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                    77     34.84%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                       9      5.33%      5.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      5.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      5.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      5.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      5.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      5.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      5.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      5.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      5.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      5.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      5.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      5.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      5.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      5.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      5.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      5.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      5.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      5.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      5.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      5.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      5.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      5.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      5.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      5.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      5.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      5.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      5.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      5.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      5.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                     80     47.34%     52.66% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                    80     47.34%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu                  5369     59.92%     59.92% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                    9      0.10%     60.02% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     60.02% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     60.02% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     60.02% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     60.02% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     60.02% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     60.02% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     60.02% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     60.02% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     60.02% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     60.02% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     60.02% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     60.02% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     60.02% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     60.02% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     60.02% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     60.02% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     60.02% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     60.02% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     60.02% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     60.02% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     60.02% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     60.02% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     60.02% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              3      0.03%     60.05% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     60.05% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     60.05% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     60.05% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead                 2357     26.30%     86.35% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite                1223     13.65%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu                  5041     60.31%     60.31% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                    6      0.07%     60.39% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     60.39% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     60.39% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     60.39% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     60.39% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     60.39% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     60.39% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     60.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     60.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     60.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     60.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     60.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     60.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     60.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     60.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     60.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     60.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     60.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     60.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     60.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     60.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     60.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     60.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     60.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              3      0.04%     60.42% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     60.42% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     60.42% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     60.42% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead                 2009     24.04%     84.46% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite                1299     15.54%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total                   8961                       # Type of FU issued
-system.cpu.iq.rate                           0.266911                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                         221                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.024662                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads              31345                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes             16624                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses         8077                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads                  36                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes                 48                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses           16                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses                   9162                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                      20                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads               60                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total                   8358                       # Type of FU issued
+system.cpu.iq.rate                           0.257589                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                         169                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.020220                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads              30275                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes             15052                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses         7570                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads                  99                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes                128                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses           31                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses                   8484                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                      43                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads               25                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads         1626                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.squashedLoads         1286                       # Number of loads squashed
 system.cpu.iew.lsq.thread0.ignoredResponses            0                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation           21                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores          645                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.memOrderViolation           20                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores          701                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked             3                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads           39                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked             8                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                    968                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                     113                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                    19                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts               11366                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts               115                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts                  2826                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts                 1583                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts                 37                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                      9                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles                    349                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                     800                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                    25                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts               10411                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts               110                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts                  2313                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts                 1639                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts                 34                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                     13                       # Number of times the IQ has become full, causing a stall
 system.cpu.iew.iewLSQFullEvents                    10                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents             21                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect            110                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect          266                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts                  376                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts                  8568                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts                  2160                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts               393                       # Number of squashed instructions skipped in execute
+system.cpu.iew.memOrderViolationEvents             20                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect            112                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect          252                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts                  364                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts                  8063                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts                  1908                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts               295                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                             1                       # number of nop insts executed
-system.cpu.iew.exec_refs                         3332                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                     1443                       # Number of branches executed
-system.cpu.iew.exec_stores                       1172                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.255205                       # Inst execution rate
-system.cpu.iew.wb_sent                           8256                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                          8093                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                      3919                       # num instructions producing a value
-system.cpu.iew.wb_consumers                      8062                       # num instructions consuming a value
+system.cpu.iew.exec_nop                            11                       # number of nop insts executed
+system.cpu.iew.exec_refs                         3148                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                     1457                       # Number of branches executed
+system.cpu.iew.exec_stores                       1240                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.248498                       # Inst execution rate
+system.cpu.iew.wb_sent                           7735                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                          7601                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                      3572                       # num instructions producing a value
+system.cpu.iew.wb_consumers                      6998                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.241057                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.486108                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       0.234259                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.510432                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts            5642                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts            5037                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls              37                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts               326                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples        12121                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.472651                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.325156                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts               324                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples        12552                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.428378                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.273949                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0         9924     81.87%     81.87% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1          978      8.07%     89.94% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2          402      3.32%     93.26% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3          224      1.85%     95.11% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4          175      1.44%     96.55% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5          212      1.75%     98.30% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6           50      0.41%     98.71% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7           33      0.27%     98.99% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8          123      1.01%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0        10495     83.61%     83.61% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1          893      7.11%     90.73% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2          426      3.39%     94.12% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3          211      1.68%     95.80% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4          111      0.88%     96.69% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5          212      1.69%     98.37% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6           50      0.40%     98.77% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7           37      0.29%     99.07% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8          117      0.93%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total        12121                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total        12552                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts                 4591                       # Number of instructions committed
-system.cpu.commit.committedOps                   5729                       # Number of ops (including micro ops) committed
+system.cpu.commit.committedOps                   5377                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                           2138                       # Number of memory references committed
-system.cpu.commit.loads                          1200                       # Number of loads committed
+system.cpu.commit.refs                           1965                       # Number of memory references committed
+system.cpu.commit.loads                          1027                       # Number of loads committed
 system.cpu.commit.membars                          12                       # Number of memory barriers committed
 system.cpu.commit.branches                       1007                       # Number of branches committed
 system.cpu.commit.fp_insts                         16                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                      4976                       # Number of committed integer instructions.
+system.cpu.commit.int_insts                      4624                       # Number of committed integer instructions.
 system.cpu.commit.function_calls                   82                       # Number of function calls committed.
 system.cpu.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu             3584     62.56%     62.56% # Class of committed instruction
-system.cpu.commit.op_class_0::IntMult               4      0.07%     62.63% # Class of committed instruction
-system.cpu.commit.op_class_0::IntDiv                0      0.00%     62.63% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatAdd              0      0.00%     62.63% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatCmp              0      0.00%     62.63% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatCvt              0      0.00%     62.63% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMult             0      0.00%     62.63% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatDiv              0      0.00%     62.63% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     62.63% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAdd               0      0.00%     62.63% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     62.63% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAlu               0      0.00%     62.63% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdCmp               0      0.00%     62.63% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdCvt               0      0.00%     62.63% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMisc              0      0.00%     62.63% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMult              0      0.00%     62.63% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     62.63% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdShift             0      0.00%     62.63% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     62.63% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     62.63% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     62.63% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     62.63% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     62.63% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     62.63% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     62.63% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMisc            3      0.05%     62.68% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     62.68% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     62.68% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     62.68% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead            1200     20.95%     83.63% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite            938     16.37%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu             3405     63.33%     63.33% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult               4      0.07%     63.40% # Class of committed instruction
+system.cpu.commit.op_class_0::IntDiv                0      0.00%     63.40% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatAdd              0      0.00%     63.40% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCmp              0      0.00%     63.40% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCvt              0      0.00%     63.40% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatMult             0      0.00%     63.40% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatDiv              0      0.00%     63.40% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     63.40% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAdd               0      0.00%     63.40% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     63.40% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAlu               0      0.00%     63.40% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCmp               0      0.00%     63.40% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCvt               0      0.00%     63.40% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMisc              0      0.00%     63.40% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMult              0      0.00%     63.40% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     63.40% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShift             0      0.00%     63.40% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     63.40% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     63.40% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     63.40% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     63.40% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     63.40% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     63.40% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     63.40% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMisc            3      0.06%     63.46% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     63.46% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     63.46% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     63.46% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead            1027     19.10%     82.56% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite            938     17.44%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total              5729                       # Class of committed instruction
-system.cpu.commit.bw_lim_events                   123                       # number cycles where commit BW limit reached
+system.cpu.commit.op_class_0::total              5377                       # Class of committed instruction
+system.cpu.commit.bw_lim_events                   117                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                        23212                       # The number of ROB reads
-system.cpu.rob.rob_writes                       23723                       # The number of ROB writes
-system.cpu.timesIdled                             215                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           20484                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads                        22692                       # The number of ROB reads
+system.cpu.rob.rob_writes                       21719                       # The number of ROB writes
+system.cpu.timesIdled                             209                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           19014                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                        4591                       # Number of Instructions Simulated
-system.cpu.committedOps                          5729                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               7.312786                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         7.312786                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.136747                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.136747                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                    39407                       # number of integer regfile reads
-system.cpu.int_regfile_writes                    7992                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                        16                       # number of floating regfile reads
-system.cpu.misc_regfile_reads                    3253                       # number of misc regfile reads
+system.cpu.committedOps                          5377                       # Number of Ops (including micro ops) Simulated
+system.cpu.cpi                               7.067523                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         7.067523                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.141492                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.141492                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                     7944                       # number of integer regfile reads
+system.cpu.int_regfile_writes                    4420                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                        31                       # number of floating regfile reads
+system.cpu.cc_regfile_reads                     28734                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                     3302                       # number of cc regfile writes
+system.cpu.misc_regfile_reads                    3189                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                     24                       # number of misc regfile writes
-system.cpu.toL2Bus.throughput              1662337662                       # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq            395                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp           394                       # Transaction distribution
+system.cpu.toL2Bus.throughput              1735807187                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq            399                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp           398                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq           42                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp           42                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          577                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          588                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          293                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total               870                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        18368                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total               881                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        18816                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         9344                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total          27712                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus             27712                       # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus          192                       # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy         218500                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          1.3                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy        480500                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          2.9                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy        229495                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.tot_pkt_size::total          28160                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus             28160                       # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy         220500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          1.4                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy        488250                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization          3.0                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy        228495                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          1.4                       # Layer utilization (%)
 system.cpu.icache.tags.replacements                 1                       # number of replacements
-system.cpu.icache.tags.tagsinuse           148.488883                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs                1601                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs               290                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs              5.520690                       # Average number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse           150.758993                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs                1666                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs               294                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs              5.666667                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   148.488883                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.072504                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.072504                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024          289                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          170                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          119                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.141113                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses              4226                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses             4226                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst         1601                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total            1601                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst          1601                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total             1601                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst         1601                       # number of overall hits
-system.cpu.icache.overall_hits::total            1601                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst          367                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total           367                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst          367                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total            367                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst          367                       # number of overall misses
-system.cpu.icache.overall_misses::total           367                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     23960000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     23960000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     23960000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     23960000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     23960000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     23960000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst         1968                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total         1968                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst         1968                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total         1968                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst         1968                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total         1968                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.186484                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.186484                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.186484                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.186484                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.186484                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.186484                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 65286.103542                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 65286.103542                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 65286.103542                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 65286.103542                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 65286.103542                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 65286.103542                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs          107                       # number of cycles access was blocked
+system.cpu.icache.tags.occ_blocks::cpu.inst   150.758993                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.073613                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.073613                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          293                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          173                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          120                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.143066                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses              4430                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses             4430                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst         1666                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total            1666                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst          1666                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total             1666                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst         1666                       # number of overall hits
+system.cpu.icache.overall_hits::total            1666                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          402                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           402                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          402                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            402                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          402                       # number of overall misses
+system.cpu.icache.overall_misses::total           402                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     25574000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     25574000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     25574000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     25574000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     25574000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     25574000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst         2068                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total         2068                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst         2068                       # number of demand (read+write) accesses
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+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.194391                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.194391                       # miss rate for ReadReq accesses
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+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 63616.915423                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 63616.915423                       # average ReadReq miss latency
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+system.cpu.icache.demand_avg_miss_latency::total 63616.915423                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 63616.915423                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 63616.915423                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs          298                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                 2                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 5                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    53.500000                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    59.600000                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst           77                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total           77                       # number of ReadReq MSHR hits
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-system.cpu.icache.demand_mshr_hits::total           77                       # number of demand (read+write) MSHR hits
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-system.cpu.icache.overall_mshr_hits::total           77                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst          290                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total          290                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst          290                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total          290                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst          290                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total          290                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     19152500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     19152500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     19152500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     19152500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     19152500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     19152500                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.147358                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.147358                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.147358                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.147358                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.147358                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.147358                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66043.103448                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66043.103448                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66043.103448                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 66043.103448                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66043.103448                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 66043.103448                       # average overall mshr miss latency
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+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.142166                       # mshr miss rate for ReadReq accesses
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+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67152.210884                       # average ReadReq mshr miss latency
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+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67152.210884                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 67152.210884                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse          185.364644                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs                 37                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs              350                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             0.105714                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.tagsinuse          188.170247                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs                 39                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs              355                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             0.109859                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   138.907401                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data    46.457243                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.004239                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.001418                       # Average percentage of cache occupancy
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-system.cpu.l2cache.tags.occ_task_id_blocks::1024          350                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          194                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          156                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.010681                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses             3864                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses            3864                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst           17                       # number of ReadReq hits
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   141.371533                       # Average occupied blocks per requestor
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+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.010834                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses             3925                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses            3925                       # Number of data accesses
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 system.cpu.l2cache.ReadReq_hits::cpu.data           20                       # number of ReadReq hits
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 system.cpu.l2cache.overall_hits::cpu.data           20                       # number of overall hits
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 system.cpu.l2cache.ReadExReq_misses::cpu.data           42                       # number of ReadExReq misses
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 system.cpu.l2cache.overall_misses::cpu.data          127                       # number of overall misses
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 system.cpu.l2cache.overall_accesses::cpu.data          147                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total          434                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.940767                       # miss rate for ReadReq accesses
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 system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.809524                       # miss rate for ReadReq accesses
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 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
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 system.cpu.l2cache.demand_miss_rate::cpu.data     0.863946                       # miss rate for demand accesses
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 system.cpu.l2cache.overall_miss_rate::cpu.data     0.863946                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.914747                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69196.296296                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78085.294118                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 71324.647887                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74017.857143                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74017.857143                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69196.296296                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76740.157480                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 71609.571788                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69196.296296                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76740.157480                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 71609.571788                       # average overall miss latency
+system.cpu.l2cache.overall_miss_rate::total     0.911565                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70004.545455                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70714.705882                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 70172.222222                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73851.190476                       # average ReadExReq miss latency
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+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70004.545455                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71751.968504                       # average overall miss latency
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+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70004.545455                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71751.968504                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 70556.592040                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -834,148 +835,148 @@ system.cpu.l2cache.demand_mshr_hits::cpu.data            5
 system.cpu.l2cache.demand_mshr_hits::total            5                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.overall_mshr_hits::cpu.data            5                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::total            5                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          270                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          275                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadReq_mshr_misses::cpu.data           80                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total          350                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total          355                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           42                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total           42                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst          270                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          275                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.data          122                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total          392                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst          270                       # number of overall MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total          397                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          275                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data          122                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total          392                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     15291000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      5345250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     20636250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      2596250                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      2596250                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     15291000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      7941500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     23232500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     15291000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      7941500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     23232500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.940767                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.overall_mshr_misses::total          397                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     15797750                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      4736000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total     20533750                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      2589250                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      2589250                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     15797750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      7325250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     23123000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     15797750                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      7325250                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     23123000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.935374                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.761905                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.892857                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.889724                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.940767                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.935374                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.829932                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.903226                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.940767                       # mshr miss rate for overall accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.900227                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.935374                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.829932                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.903226                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56633.333333                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66815.625000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58960.714286                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61815.476190                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61815.476190                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56633.333333                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65094.262295                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59266.581633                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56633.333333                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65094.262295                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59266.581633                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.900227                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57446.363636                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data        59200                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57841.549296                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61648.809524                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61648.809524                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57446.363636                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60043.032787                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58244.332494                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57446.363636                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60043.032787                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58244.332494                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.dcache.tags.replacements                 0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse            87.019573                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs                2400                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse            87.133302                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs                2168                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs               146                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             16.438356                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             14.849315                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data    87.019573                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.021245                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.021245                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data    87.133302                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.021273                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.021273                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          146                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           61                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1           85                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           67                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           79                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024     0.035645                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses              5964                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses             5964                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data         1782                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total            1782                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data          596                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total            596                       # number of WriteReq hits
+system.cpu.dcache.tags.tag_accesses              5528                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses             5528                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data         1551                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total            1551                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data          595                       # number of WriteReq hits
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 system.cpu.dcache.LoadLockedReq_hits::cpu.data           11                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total           11                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data           11                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total           11                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data          2378                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total             2378                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data         2378                       # number of overall hits
-system.cpu.dcache.overall_hits::total            2378                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data          190                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total           190                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data          317                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total          317                       # number of WriteReq misses
+system.cpu.dcache.demand_hits::cpu.data          2146                       # number of demand (read+write) hits
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+system.cpu.dcache.overall_hits::total            2146                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data          203                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total           203                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data          318                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total          318                       # number of WriteReq misses
 system.cpu.dcache.LoadLockedReq_misses::cpu.data            2                       # number of LoadLockedReq misses
 system.cpu.dcache.LoadLockedReq_misses::total            2                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data          507                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total            507                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data          507                       # number of overall misses
-system.cpu.dcache.overall_misses::total           507                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data     11613493                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     11613493                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data     20684250                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total     20684250                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       130000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total       130000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     32297743                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     32297743                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     32297743                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     32297743                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data         1972                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total         1972                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data          521                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total            521                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data          521                       # number of overall misses
+system.cpu.dcache.overall_misses::total           521                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data     11351493                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     11351493                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data     20745500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total     20745500                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       130500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total       130500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     32096993                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     32096993                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     32096993                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     32096993                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data         1754                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total         1754                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data          913                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total          913                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::cpu.data           13                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::total           13                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data           11                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total           11                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data         2885                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total         2885                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data         2885                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total         2885                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.096349                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.096349                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.347207                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.347207                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_accesses::cpu.data         2667                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total         2667                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data         2667                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total         2667                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.115735                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.115735                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.348302                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.348302                       # miss rate for WriteReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.153846                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::total     0.153846                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.175737                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.175737                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.175737                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.175737                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 61123.647368                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 61123.647368                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data        65250                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total        65250                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        65000                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        65000                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 63703.635108                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 63703.635108                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 63703.635108                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 63703.635108                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs          118                       # number of cycles access was blocked
+system.cpu.dcache.demand_miss_rate::cpu.data     0.195351                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.195351                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.195351                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.195351                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55918.684729                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 55918.684729                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65237.421384                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 65237.421384                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        65250                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        65250                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 61606.512476                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 61606.512476                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 61606.512476                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 61606.512476                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs          105                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                 3                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 4                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    39.333333                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    26.250000                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data           85                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total           85                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data          275                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total          275                       # number of WriteReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data           98                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total           98                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data          276                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total          276                       # number of WriteReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            2                       # number of LoadLockedReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::total            2                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data          360                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total          360                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data          360                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total          360                       # number of overall MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data          374                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total          374                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data          374                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total          374                       # number of overall MSHR hits
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data          105                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total          105                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data           42                       # number of WriteReq MSHR misses
@@ -984,30 +985,30 @@ system.cpu.dcache.demand_mshr_misses::cpu.data          147
 system.cpu.dcache.demand_mshr_misses::total          147                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data          147                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total          147                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      6871755                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      6871755                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      3151750                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      3151750                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data     10023505                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total     10023505                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data     10023505                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total     10023505                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.053245                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.053245                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      6245255                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      6245255                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      3144750                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      3144750                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data      9390005                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total      9390005                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data      9390005                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total      9390005                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.059863                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.059863                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.046002                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.046002                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.050953                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.050953                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.050953                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.050953                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 65445.285714                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 65445.285714                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75041.666667                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75041.666667                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68187.108844                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 68187.108844                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68187.108844                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 68187.108844                       # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.055118                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.055118                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.055118                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.055118                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 59478.619048                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 59478.619048                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data        74875                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total        74875                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 63877.585034                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 63877.585034                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 63877.585034                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 63877.585034                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt
index fe7b25846..f5795e533 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt
@@ -1,16 +1,16 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000003                       # Number of seconds simulated
-sim_ticks                                     2870500                       # Number of ticks simulated
-final_tick                                    2870500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                     2694500                       # Number of ticks simulated
+final_tick                                    2694500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 790734                       # Simulator instruction rate (inst/s)
-host_op_rate                                   984195                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              492029482                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 297624                       # Number of bytes of host memory used
-host_seconds                                     0.01                       # Real time elapsed on the host
+host_inst_rate                                 109620                       # Simulator instruction rate (inst/s)
+host_op_rate                                   128318                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               64270947                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 268656                       # Number of bytes of host memory used
+host_seconds                                     0.04                       # Real time elapsed on the host
 sim_insts                                        4591                       # Number of instructions simulated
-sim_ops                                          5729                       # Number of ops (including micro ops) simulated
+sim_ops                                          5377                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst             18416                       # Number of bytes read from this memory
@@ -21,21 +21,21 @@ system.physmem.bytes_inst_read::total           18416                       # Nu
 system.physmem.bytes_written::cpu.data           3648                       # Number of bytes written to this memory
 system.physmem.bytes_written::total              3648                       # Number of bytes written to this memory
 system.physmem.num_reads::cpu.inst               4604                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data               1157                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                  5761                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data               1003                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                  5607                       # Number of read requests responded to by this memory
 system.physmem.num_writes::cpu.data               924                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total                  924                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst           6415607037                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data           1564535795                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              7980142832                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst      6415607037                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total         6415607037                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data          1270858735                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total             1270858735                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst          6415607037                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data          2835394531                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             9251001568                       # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput                   9251001568                       # Throughput (bytes/s)
+system.physmem.bw_read::cpu.inst           6834663203                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data           1666728521                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              8501391724                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst      6834663203                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total         6834663203                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data          1353868992                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total             1353868992                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst          6834663203                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data          3020597513                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             9855260716                       # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput                   9855260716                       # Throughput (bytes/s)
 system.membus.data_through_bus                  26555                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
@@ -211,63 +211,65 @@ system.cpu.itb.inst_accesses                        0                       # IT
 system.cpu.itb.hits                                 0                       # DTB hits
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
-system.cpu.numCycles                             5742                       # number of cpu cycles simulated
+system.cpu.numCycles                             5390                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                        4591                       # Number of instructions committed
-system.cpu.committedOps                          5729                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses                  4976                       # Number of integer alu accesses
+system.cpu.committedOps                          5377                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses                  4624                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                     16                       # Number of float alu accesses
 system.cpu.num_func_calls                         203                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts          792                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                         4976                       # number of integer instructions
+system.cpu.num_conditional_control_insts          722                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                         4624                       # number of integer instructions
 system.cpu.num_fp_insts                            16                       # number of float instructions
-system.cpu.num_int_register_reads               25360                       # number of times the integer registers were read
-system.cpu.num_int_register_writes               5334                       # number of times the integer registers were written
+system.cpu.num_int_register_reads                7607                       # number of times the integer registers were read
+system.cpu.num_int_register_writes               2728                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                   16                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
-system.cpu.num_mem_refs                          2138                       # number of memory refs
-system.cpu.num_load_insts                        1200                       # Number of load instructions
+system.cpu.num_cc_register_reads                16172                       # number of times the CC registers were read
+system.cpu.num_cc_register_writes                2432                       # number of times the CC registers were written
+system.cpu.num_mem_refs                          1965                       # number of memory refs
+system.cpu.num_load_insts                        1027                       # Number of load instructions
 system.cpu.num_store_insts                        938                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                       5742                       # Number of busy cycles
+system.cpu.num_busy_cycles                       5390                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                              1007                       # Number of branches fetched
 system.cpu.op_class::No_OpClass                     0      0.00%      0.00% # Class of executed instruction
-system.cpu.op_class::IntAlu                      3597     62.64%     62.64% # Class of executed instruction
-system.cpu.op_class::IntMult                        4      0.07%     62.71% # Class of executed instruction
-system.cpu.op_class::IntDiv                         0      0.00%     62.71% # Class of executed instruction
-system.cpu.op_class::FloatAdd                       0      0.00%     62.71% # Class of executed instruction
-system.cpu.op_class::FloatCmp                       0      0.00%     62.71% # Class of executed instruction
-system.cpu.op_class::FloatCvt                       0      0.00%     62.71% # Class of executed instruction
-system.cpu.op_class::FloatMult                      0      0.00%     62.71% # Class of executed instruction
-system.cpu.op_class::FloatDiv                       0      0.00%     62.71% # Class of executed instruction
-system.cpu.op_class::FloatSqrt                      0      0.00%     62.71% # Class of executed instruction
-system.cpu.op_class::SimdAdd                        0      0.00%     62.71% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc                     0      0.00%     62.71% # Class of executed instruction
-system.cpu.op_class::SimdAlu                        0      0.00%     62.71% # Class of executed instruction
-system.cpu.op_class::SimdCmp                        0      0.00%     62.71% # Class of executed instruction
-system.cpu.op_class::SimdCvt                        0      0.00%     62.71% # Class of executed instruction
-system.cpu.op_class::SimdMisc                       0      0.00%     62.71% # Class of executed instruction
-system.cpu.op_class::SimdMult                       0      0.00%     62.71% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc                    0      0.00%     62.71% # Class of executed instruction
-system.cpu.op_class::SimdShift                      0      0.00%     62.71% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc                   0      0.00%     62.71% # Class of executed instruction
-system.cpu.op_class::SimdSqrt                       0      0.00%     62.71% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd                   0      0.00%     62.71% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu                   0      0.00%     62.71% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp                   0      0.00%     62.71% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt                   0      0.00%     62.71% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv                   0      0.00%     62.71% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc                  3      0.05%     62.77% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult                  0      0.00%     62.77% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc               0      0.00%     62.77% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt                  0      0.00%     62.77% # Class of executed instruction
-system.cpu.op_class::MemRead                     1200     20.90%     83.66% # Class of executed instruction
-system.cpu.op_class::MemWrite                     938     16.34%    100.00% # Class of executed instruction
+system.cpu.op_class::IntAlu                      3418     63.41%     63.41% # Class of executed instruction
+system.cpu.op_class::IntMult                        4      0.07%     63.49% # Class of executed instruction
+system.cpu.op_class::IntDiv                         0      0.00%     63.49% # Class of executed instruction
+system.cpu.op_class::FloatAdd                       0      0.00%     63.49% # Class of executed instruction
+system.cpu.op_class::FloatCmp                       0      0.00%     63.49% # Class of executed instruction
+system.cpu.op_class::FloatCvt                       0      0.00%     63.49% # Class of executed instruction
+system.cpu.op_class::FloatMult                      0      0.00%     63.49% # Class of executed instruction
+system.cpu.op_class::FloatDiv                       0      0.00%     63.49% # Class of executed instruction
+system.cpu.op_class::FloatSqrt                      0      0.00%     63.49% # Class of executed instruction
+system.cpu.op_class::SimdAdd                        0      0.00%     63.49% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc                     0      0.00%     63.49% # Class of executed instruction
+system.cpu.op_class::SimdAlu                        0      0.00%     63.49% # Class of executed instruction
+system.cpu.op_class::SimdCmp                        0      0.00%     63.49% # Class of executed instruction
+system.cpu.op_class::SimdCvt                        0      0.00%     63.49% # Class of executed instruction
+system.cpu.op_class::SimdMisc                       0      0.00%     63.49% # Class of executed instruction
+system.cpu.op_class::SimdMult                       0      0.00%     63.49% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc                    0      0.00%     63.49% # Class of executed instruction
+system.cpu.op_class::SimdShift                      0      0.00%     63.49% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc                   0      0.00%     63.49% # Class of executed instruction
+system.cpu.op_class::SimdSqrt                       0      0.00%     63.49% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd                   0      0.00%     63.49% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu                   0      0.00%     63.49% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp                   0      0.00%     63.49% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt                   0      0.00%     63.49% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv                   0      0.00%     63.49% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc                  3      0.06%     63.54% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult                  0      0.00%     63.54% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc               0      0.00%     63.54% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt                  0      0.00%     63.54% # Class of executed instruction
+system.cpu.op_class::MemRead                     1027     19.05%     82.60% # Class of executed instruction
+system.cpu.op_class::MemWrite                     938     17.40%    100.00% # Class of executed instruction
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::total                       5742                       # Class of executed instruction
+system.cpu.op_class::total                       5390                       # Class of executed instruction
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt
index 2a0a91e3f..efe28c206 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt
@@ -1,16 +1,16 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000003                       # Number of seconds simulated
-sim_ticks                                     2870500                       # Number of ticks simulated
-final_tick                                    2870500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                     2694500                       # Number of ticks simulated
+final_tick                                    2694500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 770690                       # Simulator instruction rate (inst/s)
-host_op_rate                                   959471                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              479615706                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 296608                       # Number of bytes of host memory used
-host_seconds                                     0.01                       # Real time elapsed on the host
+host_inst_rate                                 133655                       # Simulator instruction rate (inst/s)
+host_op_rate                                   156442                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               78348823                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 267596                       # Number of bytes of host memory used
+host_seconds                                     0.03                       # Real time elapsed on the host
 sim_insts                                        4591                       # Number of instructions simulated
-sim_ops                                          5729                       # Number of ops (including micro ops) simulated
+sim_ops                                          5377                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst             18416                       # Number of bytes read from this memory
@@ -21,21 +21,21 @@ system.physmem.bytes_inst_read::total           18416                       # Nu
 system.physmem.bytes_written::cpu.data           3648                       # Number of bytes written to this memory
 system.physmem.bytes_written::total              3648                       # Number of bytes written to this memory
 system.physmem.num_reads::cpu.inst               4604                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data               1157                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                  5761                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data               1003                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                  5607                       # Number of read requests responded to by this memory
 system.physmem.num_writes::cpu.data               924                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total                  924                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst           6415607037                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data           1564535795                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              7980142832                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst      6415607037                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total         6415607037                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data          1270858735                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total             1270858735                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst          6415607037                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data          2835394531                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             9251001568                       # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput                   9251001568                       # Throughput (bytes/s)
+system.physmem.bw_read::cpu.inst           6834663203                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data           1666728521                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              8501391724                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst      6834663203                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total         6834663203                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data          1353868992                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total             1353868992                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst          6834663203                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data          3020597513                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             9855260716                       # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput                   9855260716                       # Throughput (bytes/s)
 system.membus.data_through_bus                  26555                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
@@ -124,63 +124,65 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                   13                       # Number of system calls
-system.cpu.numCycles                             5742                       # number of cpu cycles simulated
+system.cpu.numCycles                             5390                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                        4591                       # Number of instructions committed
-system.cpu.committedOps                          5729                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses                  4976                       # Number of integer alu accesses
+system.cpu.committedOps                          5377                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses                  4624                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                     16                       # Number of float alu accesses
 system.cpu.num_func_calls                         203                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts          792                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                         4976                       # number of integer instructions
+system.cpu.num_conditional_control_insts          722                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                         4624                       # number of integer instructions
 system.cpu.num_fp_insts                            16                       # number of float instructions
-system.cpu.num_int_register_reads               25360                       # number of times the integer registers were read
-system.cpu.num_int_register_writes               5334                       # number of times the integer registers were written
+system.cpu.num_int_register_reads                7607                       # number of times the integer registers were read
+system.cpu.num_int_register_writes               2728                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                   16                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
-system.cpu.num_mem_refs                          2138                       # number of memory refs
-system.cpu.num_load_insts                        1200                       # Number of load instructions
+system.cpu.num_cc_register_reads                16172                       # number of times the CC registers were read
+system.cpu.num_cc_register_writes                2432                       # number of times the CC registers were written
+system.cpu.num_mem_refs                          1965                       # number of memory refs
+system.cpu.num_load_insts                        1027                       # Number of load instructions
 system.cpu.num_store_insts                        938                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                       5742                       # Number of busy cycles
+system.cpu.num_busy_cycles                       5390                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                              1007                       # Number of branches fetched
 system.cpu.op_class::No_OpClass                     0      0.00%      0.00% # Class of executed instruction
-system.cpu.op_class::IntAlu                      3597     62.64%     62.64% # Class of executed instruction
-system.cpu.op_class::IntMult                        4      0.07%     62.71% # Class of executed instruction
-system.cpu.op_class::IntDiv                         0      0.00%     62.71% # Class of executed instruction
-system.cpu.op_class::FloatAdd                       0      0.00%     62.71% # Class of executed instruction
-system.cpu.op_class::FloatCmp                       0      0.00%     62.71% # Class of executed instruction
-system.cpu.op_class::FloatCvt                       0      0.00%     62.71% # Class of executed instruction
-system.cpu.op_class::FloatMult                      0      0.00%     62.71% # Class of executed instruction
-system.cpu.op_class::FloatDiv                       0      0.00%     62.71% # Class of executed instruction
-system.cpu.op_class::FloatSqrt                      0      0.00%     62.71% # Class of executed instruction
-system.cpu.op_class::SimdAdd                        0      0.00%     62.71% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc                     0      0.00%     62.71% # Class of executed instruction
-system.cpu.op_class::SimdAlu                        0      0.00%     62.71% # Class of executed instruction
-system.cpu.op_class::SimdCmp                        0      0.00%     62.71% # Class of executed instruction
-system.cpu.op_class::SimdCvt                        0      0.00%     62.71% # Class of executed instruction
-system.cpu.op_class::SimdMisc                       0      0.00%     62.71% # Class of executed instruction
-system.cpu.op_class::SimdMult                       0      0.00%     62.71% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc                    0      0.00%     62.71% # Class of executed instruction
-system.cpu.op_class::SimdShift                      0      0.00%     62.71% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc                   0      0.00%     62.71% # Class of executed instruction
-system.cpu.op_class::SimdSqrt                       0      0.00%     62.71% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd                   0      0.00%     62.71% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu                   0      0.00%     62.71% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp                   0      0.00%     62.71% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt                   0      0.00%     62.71% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv                   0      0.00%     62.71% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc                  3      0.05%     62.77% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult                  0      0.00%     62.77% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc               0      0.00%     62.77% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt                  0      0.00%     62.77% # Class of executed instruction
-system.cpu.op_class::MemRead                     1200     20.90%     83.66% # Class of executed instruction
-system.cpu.op_class::MemWrite                     938     16.34%    100.00% # Class of executed instruction
+system.cpu.op_class::IntAlu                      3418     63.41%     63.41% # Class of executed instruction
+system.cpu.op_class::IntMult                        4      0.07%     63.49% # Class of executed instruction
+system.cpu.op_class::IntDiv                         0      0.00%     63.49% # Class of executed instruction
+system.cpu.op_class::FloatAdd                       0      0.00%     63.49% # Class of executed instruction
+system.cpu.op_class::FloatCmp                       0      0.00%     63.49% # Class of executed instruction
+system.cpu.op_class::FloatCvt                       0      0.00%     63.49% # Class of executed instruction
+system.cpu.op_class::FloatMult                      0      0.00%     63.49% # Class of executed instruction
+system.cpu.op_class::FloatDiv                       0      0.00%     63.49% # Class of executed instruction
+system.cpu.op_class::FloatSqrt                      0      0.00%     63.49% # Class of executed instruction
+system.cpu.op_class::SimdAdd                        0      0.00%     63.49% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc                     0      0.00%     63.49% # Class of executed instruction
+system.cpu.op_class::SimdAlu                        0      0.00%     63.49% # Class of executed instruction
+system.cpu.op_class::SimdCmp                        0      0.00%     63.49% # Class of executed instruction
+system.cpu.op_class::SimdCvt                        0      0.00%     63.49% # Class of executed instruction
+system.cpu.op_class::SimdMisc                       0      0.00%     63.49% # Class of executed instruction
+system.cpu.op_class::SimdMult                       0      0.00%     63.49% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc                    0      0.00%     63.49% # Class of executed instruction
+system.cpu.op_class::SimdShift                      0      0.00%     63.49% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc                   0      0.00%     63.49% # Class of executed instruction
+system.cpu.op_class::SimdSqrt                       0      0.00%     63.49% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd                   0      0.00%     63.49% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu                   0      0.00%     63.49% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp                   0      0.00%     63.49% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt                   0      0.00%     63.49% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv                   0      0.00%     63.49% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc                  3      0.06%     63.54% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult                  0      0.00%     63.54% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc               0      0.00%     63.54% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt                  0      0.00%     63.54% # Class of executed instruction
+system.cpu.op_class::MemRead                     1027     19.05%     82.60% # Class of executed instruction
+system.cpu.op_class::MemWrite                     938     17.40%    100.00% # Class of executed instruction
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::total                       5742                       # Class of executed instruction
+system.cpu.op_class::total                       5390                       # Class of executed instruction
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt
index ba11ac8e8..f26a07dcf 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt
@@ -1,16 +1,16 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000026                       # Number of seconds simulated
-sim_ticks                                    25969000                       # Number of ticks simulated
-final_tick                                   25969000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                    25815000                       # Number of ticks simulated
+final_tick                                   25815000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 376681                       # Simulator instruction rate (inst/s)
-host_op_rate                                   467447                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2137718143                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 306356                       # Number of bytes of host memory used
-host_seconds                                     0.01                       # Real time elapsed on the host
+host_inst_rate                                  85918                       # Simulator instruction rate (inst/s)
+host_op_rate                                   100276                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              485659481                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 277384                       # Number of bytes of host memory used
+host_seconds                                     0.05                       # Real time elapsed on the host
 sim_insts                                        4565                       # Number of instructions simulated
-sim_ops                                          5672                       # Number of ops (including micro ops) simulated
+sim_ops                                          5329                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst             14400                       # Number of bytes read from this memory
@@ -21,15 +21,15 @@ system.physmem.bytes_inst_read::total           14400                       # Nu
 system.physmem.num_reads::cpu.inst                225                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data                125                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                   350                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst            554507297                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            308059610                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               862566907                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst       554507297                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          554507297                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           554507297                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           308059610                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              862566907                       # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput                    862566907                       # Throughput (bytes/s)
+system.physmem.bw_read::cpu.inst            557815224                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            309897347                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               867712570                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst       557815224                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          557815224                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           557815224                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           309897347                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              867712570                       # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput                    867712570                       # Throughput (bytes/s)
 system.membus.trans_dist::ReadReq                 307                       # Transaction distribution
 system.membus.trans_dist::ReadResp                307                       # Transaction distribution
 system.membus.trans_dist::ReadExReq                43                       # Transaction distribution
@@ -40,10 +40,10 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port
 system.membus.tot_pkt_size::total               22400                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.data_through_bus                  22400                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy              350000                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               1.3                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            3150000                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization             12.1                       # Layer utilization (%)
+system.membus.reqLayer0.occupancy              355000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               1.4                       # Layer utilization (%)
+system.membus.respLayer1.occupancy            3155000                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization             12.2                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
@@ -130,73 +130,75 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                   13                       # Number of system calls
-system.cpu.numCycles                            51938                       # number of cpu cycles simulated
+system.cpu.numCycles                            51630                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                        4565                       # Number of instructions committed
-system.cpu.committedOps                          5672                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses                  4976                       # Number of integer alu accesses
+system.cpu.committedOps                          5329                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses                  4624                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                     16                       # Number of float alu accesses
 system.cpu.num_func_calls                         203                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts          792                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                         4976                       # number of integer instructions
+system.cpu.num_conditional_control_insts          722                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                         4624                       # number of integer instructions
 system.cpu.num_fp_insts                            16                       # number of float instructions
-system.cpu.num_int_register_reads               28821                       # number of times the integer registers were read
-system.cpu.num_int_register_writes               5334                       # number of times the integer registers were written
+system.cpu.num_int_register_reads                7573                       # number of times the integer registers were read
+system.cpu.num_int_register_writes               2728                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                   16                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
-system.cpu.num_mem_refs                          2138                       # number of memory refs
-system.cpu.num_load_insts                        1200                       # Number of load instructions
+system.cpu.num_cc_register_reads                19184                       # number of times the CC registers were read
+system.cpu.num_cc_register_writes                2432                       # number of times the CC registers were written
+system.cpu.num_mem_refs                          1965                       # number of memory refs
+system.cpu.num_load_insts                        1027                       # Number of load instructions
 system.cpu.num_store_insts                        938                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                      51938                       # Number of busy cycles
+system.cpu.num_busy_cycles                      51630                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                              1007                       # Number of branches fetched
 system.cpu.op_class::No_OpClass                     0      0.00%      0.00% # Class of executed instruction
-system.cpu.op_class::IntAlu                      3597     62.64%     62.64% # Class of executed instruction
-system.cpu.op_class::IntMult                        4      0.07%     62.71% # Class of executed instruction
-system.cpu.op_class::IntDiv                         0      0.00%     62.71% # Class of executed instruction
-system.cpu.op_class::FloatAdd                       0      0.00%     62.71% # Class of executed instruction
-system.cpu.op_class::FloatCmp                       0      0.00%     62.71% # Class of executed instruction
-system.cpu.op_class::FloatCvt                       0      0.00%     62.71% # Class of executed instruction
-system.cpu.op_class::FloatMult                      0      0.00%     62.71% # Class of executed instruction
-system.cpu.op_class::FloatDiv                       0      0.00%     62.71% # Class of executed instruction
-system.cpu.op_class::FloatSqrt                      0      0.00%     62.71% # Class of executed instruction
-system.cpu.op_class::SimdAdd                        0      0.00%     62.71% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc                     0      0.00%     62.71% # Class of executed instruction
-system.cpu.op_class::SimdAlu                        0      0.00%     62.71% # Class of executed instruction
-system.cpu.op_class::SimdCmp                        0      0.00%     62.71% # Class of executed instruction
-system.cpu.op_class::SimdCvt                        0      0.00%     62.71% # Class of executed instruction
-system.cpu.op_class::SimdMisc                       0      0.00%     62.71% # Class of executed instruction
-system.cpu.op_class::SimdMult                       0      0.00%     62.71% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc                    0      0.00%     62.71% # Class of executed instruction
-system.cpu.op_class::SimdShift                      0      0.00%     62.71% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc                   0      0.00%     62.71% # Class of executed instruction
-system.cpu.op_class::SimdSqrt                       0      0.00%     62.71% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd                   0      0.00%     62.71% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu                   0      0.00%     62.71% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp                   0      0.00%     62.71% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt                   0      0.00%     62.71% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv                   0      0.00%     62.71% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc                  3      0.05%     62.77% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult                  0      0.00%     62.77% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc               0      0.00%     62.77% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt                  0      0.00%     62.77% # Class of executed instruction
-system.cpu.op_class::MemRead                     1200     20.90%     83.66% # Class of executed instruction
-system.cpu.op_class::MemWrite                     938     16.34%    100.00% # Class of executed instruction
+system.cpu.op_class::IntAlu                      3418     63.41%     63.41% # Class of executed instruction
+system.cpu.op_class::IntMult                        4      0.07%     63.49% # Class of executed instruction
+system.cpu.op_class::IntDiv                         0      0.00%     63.49% # Class of executed instruction
+system.cpu.op_class::FloatAdd                       0      0.00%     63.49% # Class of executed instruction
+system.cpu.op_class::FloatCmp                       0      0.00%     63.49% # Class of executed instruction
+system.cpu.op_class::FloatCvt                       0      0.00%     63.49% # Class of executed instruction
+system.cpu.op_class::FloatMult                      0      0.00%     63.49% # Class of executed instruction
+system.cpu.op_class::FloatDiv                       0      0.00%     63.49% # Class of executed instruction
+system.cpu.op_class::FloatSqrt                      0      0.00%     63.49% # Class of executed instruction
+system.cpu.op_class::SimdAdd                        0      0.00%     63.49% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc                     0      0.00%     63.49% # Class of executed instruction
+system.cpu.op_class::SimdAlu                        0      0.00%     63.49% # Class of executed instruction
+system.cpu.op_class::SimdCmp                        0      0.00%     63.49% # Class of executed instruction
+system.cpu.op_class::SimdCvt                        0      0.00%     63.49% # Class of executed instruction
+system.cpu.op_class::SimdMisc                       0      0.00%     63.49% # Class of executed instruction
+system.cpu.op_class::SimdMult                       0      0.00%     63.49% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc                    0      0.00%     63.49% # Class of executed instruction
+system.cpu.op_class::SimdShift                      0      0.00%     63.49% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc                   0      0.00%     63.49% # Class of executed instruction
+system.cpu.op_class::SimdSqrt                       0      0.00%     63.49% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd                   0      0.00%     63.49% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu                   0      0.00%     63.49% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp                   0      0.00%     63.49% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt                   0      0.00%     63.49% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv                   0      0.00%     63.49% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc                  3      0.06%     63.54% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult                  0      0.00%     63.54% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc               0      0.00%     63.54% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt                  0      0.00%     63.54% # Class of executed instruction
+system.cpu.op_class::MemRead                     1027     19.05%     82.60% # Class of executed instruction
+system.cpu.op_class::MemWrite                     938     17.40%    100.00% # Class of executed instruction
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::total                       5742                       # Class of executed instruction
+system.cpu.op_class::total                       5390                       # Class of executed instruction
 system.cpu.icache.tags.replacements                 1                       # number of replacements
-system.cpu.icache.tags.tagsinuse           114.614391                       # Cycle average of tags in use
+system.cpu.icache.tags.tagsinuse           114.428477                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs                4364                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs               241                       # Sample count of references to valid blocks.
 system.cpu.icache.tags.avg_refs             18.107884                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   114.614391                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.055964                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.055964                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst   114.428477                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.055873                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.055873                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          240                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0          107                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1          133                       # Occupied blocks per task id
@@ -215,12 +217,12 @@ system.cpu.icache.demand_misses::cpu.inst          241                       # n
 system.cpu.icache.demand_misses::total            241                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst          241                       # number of overall misses
 system.cpu.icache.overall_misses::total           241                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     12583000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     12583000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     12583000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     12583000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     12583000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     12583000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     12588000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     12588000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     12588000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     12588000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     12588000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     12588000                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst         4605                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total         4605                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst         4605                       # number of demand (read+write) accesses
@@ -233,12 +235,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.052334
 system.cpu.icache.demand_miss_rate::total     0.052334                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.052334                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.052334                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52211.618257                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 52211.618257                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 52211.618257                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 52211.618257                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 52211.618257                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 52211.618257                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52232.365145                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 52232.365145                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 52232.365145                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 52232.365145                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 52232.365145                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 52232.365145                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -253,36 +255,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst          241
 system.cpu.icache.demand_mshr_misses::total          241                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          241                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          241                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     12101000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     12101000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     12101000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     12101000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     12101000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     12101000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     12106000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     12106000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     12106000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     12106000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     12106000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     12106000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.052334                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.052334                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.052334                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.052334                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.052334                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.052334                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50211.618257                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50211.618257                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50211.618257                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 50211.618257                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50211.618257                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 50211.618257                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50232.365145                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50232.365145                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50232.365145                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 50232.365145                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50232.365145                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 50232.365145                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse          154.071129                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse          153.844437                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs                 32                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs              307                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs             0.104235                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   105.889758                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data    48.181371                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.003231                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.001470                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.004702                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   105.714938                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data    48.129500                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.003226                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.001469                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.004695                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024          307                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0          128                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::1          179                       # Occupied blocks per task id
@@ -309,17 +311,17 @@ system.cpu.l2cache.demand_misses::total           350                       # nu
 system.cpu.l2cache.overall_misses::cpu.inst          225                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data          125                       # number of overall misses
 system.cpu.l2cache.overall_misses::total          350                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     11700000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     11705000                       # number of ReadReq miss cycles
 system.cpu.l2cache.ReadReq_miss_latency::cpu.data      4264000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total     15964000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total     15969000                       # number of ReadReq miss cycles
 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      2236000                       # number of ReadExReq miss cycles
 system.cpu.l2cache.ReadExReq_miss_latency::total      2236000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     11700000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     11705000                       # number of demand (read+write) miss cycles
 system.cpu.l2cache.demand_miss_latency::cpu.data      6500000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     18200000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     11700000                       # number of overall miss cycles
+system.cpu.l2cache.demand_miss_latency::total     18205000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     11705000                       # number of overall miss cycles
 system.cpu.l2cache.overall_miss_latency::cpu.data      6500000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     18200000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     18205000                       # number of overall miss cycles
 system.cpu.l2cache.ReadReq_accesses::cpu.inst          241                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::cpu.data           98                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::total          339                       # number of ReadReq accesses(hits+misses)
@@ -342,17 +344,17 @@ system.cpu.l2cache.demand_miss_rate::total     0.916230                       #
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.933610                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.886525                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.916230                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52022.222222                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data        52000                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 52016.286645                       # average ReadReq miss latency
 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        52000                       # average ReadExReq miss latency
 system.cpu.l2cache.ReadExReq_avg_miss_latency::total        52000                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52022.222222                       # average overall miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.data        52000                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total        52000                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 52014.285714                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52022.222222                       # average overall miss latency
 system.cpu.l2cache.overall_avg_miss_latency::cpu.data        52000                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 52014.285714                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -407,32 +409,32 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40000
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total        40000                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.dcache.tags.replacements                 0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse            83.000387                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs                1940                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse            82.900177                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs                1786                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs               141                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             13.758865                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             12.666667                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data    83.000387                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.020264                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.020264                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data    82.900177                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.020239                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.020239                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          141                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           40                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          101                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           41                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          100                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024     0.034424                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses              4303                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses             4303                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data         1048                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total            1048                       # number of ReadReq hits
+system.cpu.dcache.tags.tag_accesses              3995                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses             3995                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data          894                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total             894                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data          870                       # number of WriteReq hits
 system.cpu.dcache.WriteReq_hits::total            870                       # number of WriteReq hits
 system.cpu.dcache.LoadLockedReq_hits::cpu.data           11                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total           11                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data           11                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total           11                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data          1918                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total             1918                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data         1918                       # number of overall hits
-system.cpu.dcache.overall_hits::total            1918                       # number of overall hits
+system.cpu.dcache.demand_hits::cpu.data          1764                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total             1764                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data         1764                       # number of overall hits
+system.cpu.dcache.overall_hits::total            1764                       # number of overall hits
 system.cpu.dcache.ReadReq_misses::cpu.data           98                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_misses::total            98                       # number of ReadReq misses
 system.cpu.dcache.WriteReq_misses::cpu.data           43                       # number of WriteReq misses
@@ -449,26 +451,26 @@ system.cpu.dcache.demand_miss_latency::cpu.data      7083000
 system.cpu.dcache.demand_miss_latency::total      7083000                       # number of demand (read+write) miss cycles
 system.cpu.dcache.overall_miss_latency::cpu.data      7083000                       # number of overall miss cycles
 system.cpu.dcache.overall_miss_latency::total      7083000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data         1146                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total         1146                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::cpu.data          992                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total          992                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data          913                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total          913                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::cpu.data           11                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::total           11                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data           11                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total           11                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data         2059                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total         2059                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data         2059                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total         2059                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.085515                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.085515                       # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data         1905                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total         1905                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data         1905                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total         1905                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.098790                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.098790                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.047097                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_miss_rate::total     0.047097                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.068480                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.068480                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.068480                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.068480                       # miss rate for overall accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.074016                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.074016                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.074016                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.074016                       # miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48142.857143                       # average ReadReq miss latency
 system.cpu.dcache.ReadReq_avg_miss_latency::total 48142.857143                       # average ReadReq miss latency
 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data        55000                       # average WriteReq miss latency
@@ -501,14 +503,14 @@ system.cpu.dcache.demand_mshr_miss_latency::cpu.data      6801000
 system.cpu.dcache.demand_mshr_miss_latency::total      6801000                       # number of demand (read+write) MSHR miss cycles
 system.cpu.dcache.overall_mshr_miss_latency::cpu.data      6801000                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_miss_latency::total      6801000                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.085515                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.085515                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.098790                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.098790                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.047097                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.047097                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.068480                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.068480                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.068480                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.068480                       # mshr miss rate for overall accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.074016                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.074016                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.074016                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.074016                       # mshr miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46142.857143                       # average ReadReq mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46142.857143                       # average ReadReq mshr miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data        53000                       # average WriteReq mshr miss latency
@@ -518,7 +520,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 48234.042553
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48234.042553                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 48234.042553                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.throughput               941430167                       # Throughput (bytes/s)
+system.cpu.toL2Bus.throughput               947046291                       # Throughput (bytes/s)
 system.cpu.toL2Bus.trans_dist::ReadReq            339                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadResp           339                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq           43                       # Transaction distribution
diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt
index 46dc5a264..8c5d2b15c 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt
@@ -1,42 +1,42 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000022                       # Number of seconds simulated
-sim_ticks                                    21842500                       # Number of ticks simulated
-final_tick                                   21842500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                    21611500                       # Number of ticks simulated
+final_tick                                   21611500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  54203                       # Simulator instruction rate (inst/s)
-host_op_rate                                    54195                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              229554116                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 222444                       # Number of bytes of host memory used
-host_seconds                                     0.10                       # Real time elapsed on the host
+host_inst_rate                                  39362                       # Simulator instruction rate (inst/s)
+host_op_rate                                    39354                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              164927772                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 235848                       # Number of bytes of host memory used
+host_seconds                                     0.13                       # Real time elapsed on the host
 sim_insts                                        5156                       # Number of instructions simulated
 sim_ops                                          5156                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst             21440                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data              9024                       # Number of bytes read from this memory
-system.physmem.bytes_read::total                30464                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        21440                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           21440                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst                335                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data                141                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                   476                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst            981572622                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            413139522                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              1394712144                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst       981572622                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          981572622                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           981572622                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           413139522                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             1394712144                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                           476                       # Number of read requests accepted
+system.physmem.bytes_read::cpu.inst             21568                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data              9088                       # Number of bytes read from this memory
+system.physmem.bytes_read::total                30656                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        21568                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           21568                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst                337                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data                142                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                   479                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst            997987183                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            420516854                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              1418504037                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst       997987183                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          997987183                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           997987183                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           420516854                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             1418504037                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                           479                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
-system.physmem.readBursts                         476                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                         479                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                    30464                       # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM                    30656                       # Total number of bytes read from DRAM
 system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
 system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                     30464                       # Total read bytes from the system interface side
+system.physmem.bytesReadSys                     30656                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
 system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
@@ -49,13 +49,13 @@ system.physmem.perBankRdBursts::4                   7                       # Pe
 system.physmem.perBankRdBursts::5                   3                       # Per bank write bursts
 system.physmem.perBankRdBursts::6                  13                       # Per bank write bursts
 system.physmem.perBankRdBursts::7                  54                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                  63                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                  64                       # Per bank write bursts
 system.physmem.perBankRdBursts::9                  77                       # Per bank write bursts
-system.physmem.perBankRdBursts::10                 44                       # Per bank write bursts
+system.physmem.perBankRdBursts::10                 43                       # Per bank write bursts
 system.physmem.perBankRdBursts::11                 20                       # Per bank write bursts
 system.physmem.perBankRdBursts::12                 51                       # Per bank write bursts
 system.physmem.perBankRdBursts::13                 29                       # Per bank write bursts
-system.physmem.perBankRdBursts::14                 77                       # Per bank write bursts
+system.physmem.perBankRdBursts::14                 80                       # Per bank write bursts
 system.physmem.perBankRdBursts::15                  7                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
 system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
@@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                        21770000                       # Total gap between requests
+system.physmem.totGap                        21538500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                     476                       # Read request sizes (log2)
+system.physmem.readPktSize::6                     479                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -92,8 +92,8 @@ system.physmem.writePktSize::5                      0                       # Wr
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
 system.physmem.rdQLenPdf::0                       284                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::1                       132                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        41                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                        14                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        42                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                        16                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         5                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
@@ -186,72 +186,71 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples          108                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      255.407407                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     175.497802                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     250.634672                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127             31     28.70%     28.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255           39     36.11%     64.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383           16     14.81%     79.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511            8      7.41%     87.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639            4      3.70%     90.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767            1      0.93%     91.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895            3      2.78%     94.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023            1      0.93%     95.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151            5      4.63%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total            108                       # Bytes accessed per row activation
-system.physmem.totQLat                        4718000                       # Total ticks spent queuing
-system.physmem.totMemAccLat                  13643000                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                      2380000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        9911.76                       # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples          109                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      255.412844                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     174.780194                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     251.892291                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127             32     29.36%     29.36% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255           38     34.86%     64.22% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383           15     13.76%     77.98% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511           11     10.09%     88.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639            3      2.75%     90.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895            3      2.75%     93.58% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023            2      1.83%     95.41% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151            5      4.59%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total            109                       # Bytes accessed per row activation
+system.physmem.totQLat                        5548500                       # Total ticks spent queuing
+system.physmem.totMemAccLat                  14529750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                      2395000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       11583.51                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  28661.76                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                        1394.71                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  30333.51                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                        1418.50                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                     1394.71                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                     1418.50                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                          10.90                       # Data bus utilization in percentage
-system.physmem.busUtilRead                      10.90                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                          11.08                       # Data bus utilization in percentage
+system.physmem.busUtilRead                      11.08                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.70                       # Average read queue length when enqueuing
+system.physmem.avgRdQLen                         1.76                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                        358                       # Number of row buffer hits during reads
+system.physmem.readRowHits                        360                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   75.21                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   75.16                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                        45735.29                       # Average gap between requests
-system.physmem.pageHitRate                      75.21                       # Row buffer hit rate, read and write combined
+system.physmem.avgGap                        44965.55                       # Average gap between requests
+system.physmem.pageHitRate                      75.16                       # Row buffer hit rate, read and write combined
 system.physmem.memoryStateTime::IDLE            11000                       # Time in different power states
 system.physmem.memoryStateTime::REF            520000                       # Time in different power states
 system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT          15316000                       # Time in different power states
+system.physmem.memoryStateTime::ACT          15315250                       # Time in different power states
 system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.membus.throughput                   1394712144                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq                 425                       # Transaction distribution
-system.membus.trans_dist::ReadResp                425                       # Transaction distribution
+system.membus.throughput                   1418504037                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq                 428                       # Transaction distribution
+system.membus.trans_dist::ReadResp                428                       # Transaction distribution
 system.membus.trans_dist::ReadExReq                51                       # Transaction distribution
 system.membus.trans_dist::ReadExResp               51                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port          952                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                    952                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        30464                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total               30464                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus                  30464                       # Total data (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port          958                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                    958                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        30656                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total               30656                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus                  30656                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy              605000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy              605500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               2.8                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            4464750                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization             20.4                       # Layer utilization (%)
+system.membus.respLayer1.occupancy            4492750                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization             20.8                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.branchPred.lookups                    2178                       # Number of BP lookups
-system.cpu.branchPred.condPredicted              1497                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect               438                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups                 1659                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                     491                       # Number of BTB hits
+system.cpu.branchPred.lookups                    2196                       # Number of BP lookups
+system.cpu.branchPred.condPredicted              1454                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect               435                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups                 1700                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                     564                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             29.596142                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                     258                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect                 66                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             33.176471                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                     277                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect                 69                       # Number of incorrect RAS predictions.
 system.cpu.dtb.read_hits                            0                       # DTB read hits
 system.cpu.dtb.read_misses                          0                       # DTB read misses
 system.cpu.dtb.read_accesses                        0                       # DTB read accesses
@@ -271,236 +270,236 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                    8                       # Number of system calls
-system.cpu.numCycles                            43686                       # number of cpu cycles simulated
+system.cpu.numCycles                            43224                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles               8839                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                          13190                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                        2178                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches                749                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                          3214                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                    1378                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles                   1314                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.PendingTrapStallCycles           143                       # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines                      1971                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                   279                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples              14424                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              0.914448                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.226738                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles               9138                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                          13312                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                        2196                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches                841                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                          4920                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                     886                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.PendingTrapStallCycles           202                       # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines                      2068                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                   269                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples              14703                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              0.905393                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.198604                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                    11210     77.72%     77.72% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                     1316      9.12%     86.84% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                      106      0.73%     87.58% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                      131      0.91%     88.48% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                      305      2.11%     90.60% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                      113      0.78%     91.38% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                      150      1.04%     92.42% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                      160      1.11%     93.53% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                      933      6.47%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                    11282     76.73%     76.73% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                     1513     10.29%     87.02% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                      130      0.88%     87.91% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                      159      1.08%     88.99% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                      291      1.98%     90.97% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                       99      0.67%     91.64% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                      152      1.03%     92.67% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                      125      0.85%     93.53% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                      952      6.47%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total                14424                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.049856                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.301927                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                     8852                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles                  1624                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                      3059                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles                    17                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                    872                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved                  158                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                    43                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts                  12284                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                   174                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                    872                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                     9006                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                     365                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles            973                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                      2923                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles                   285                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts                  11879                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                     5                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                      8                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.SQFullEvents                    266                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands                7180                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups                 14112                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups            13884                       # Number of integer rename lookups
+system.cpu.fetch.rateDist::total                14703                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.050805                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.307977                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                     8679                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles                  2634                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                      2860                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles                   130                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                    400                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved                  179                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                    47                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts                  12297                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                   180                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                    400                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                     8850                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                     502                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles            975                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                      2807                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles                  1169                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts                  11801                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                     4                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                      2                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                    281                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents                    868                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands                7107                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups                 13927                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups            13678                       # Number of integer rename lookups
 system.cpu.rename.fp_rename_lookups                 3                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps                  3398                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                     3782                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.UndoneMaps                     3709                       # Number of HB maps that are undone due to squashing
 system.cpu.rename.serializingInsts                 16                       # count of serializing insts renamed
 system.cpu.rename.tempSerializingInsts             10                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                       151                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads                 2468                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores                1195                       # Number of stores inserted to the mem dependence unit.
+system.cpu.rename.skidInsts                       307                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads                 2543                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores                1213                       # Number of stores inserted to the mem dependence unit.
 system.cpu.memDep0.conflictingLoads                 1                       # Number of conflicting loads.
 system.cpu.memDep0.conflictingStores                1                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                       9223                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsAdded                       9299                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqNonSpecInstsAdded                  12                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                      8300                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued                47                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined            3436                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined         2075                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqInstsIssued                      8548                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued                29                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined            3486                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined         1874                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu.iq.iqSquashedNonSpecRemoved              2                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples         14424                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.575430                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.252383                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples         14703                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.581378                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.331585                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0               10895     75.53%     75.53% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1                1375      9.53%     85.07% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2                 844      5.85%     90.92% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3                 571      3.96%     94.88% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4                 375      2.60%     97.48% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5                 225      1.56%     99.04% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6                  91      0.63%     99.67% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7                  31      0.21%     99.88% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8                  17      0.12%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0               11282     76.73%     76.73% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1                1346      9.15%     85.89% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2                 761      5.18%     91.06% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3                 427      2.90%     93.97% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4                 364      2.48%     96.44% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                 316      2.15%     98.59% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6                 114      0.78%     99.37% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7                  65      0.44%     99.81% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8                  28      0.19%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total           14424                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total           14703                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                       5      3.09%      3.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%      3.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      3.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      3.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      3.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      3.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      3.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      3.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      3.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      3.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      3.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      3.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      3.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      3.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      3.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      3.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      3.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      3.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      3.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      3.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      3.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      3.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      3.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      3.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      3.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      3.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      3.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      3.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      3.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                    102     62.96%     66.05% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                    55     33.95%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                       8      3.96%      3.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      3.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      3.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      3.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      3.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      3.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      3.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      3.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      3.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      3.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      3.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      3.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      3.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      3.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      3.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      3.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      3.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      3.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      3.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      3.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      3.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      3.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      3.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      3.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      3.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      3.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      3.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      3.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      3.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                    135     66.83%     70.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                    59     29.21%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu                  4936     59.47%     59.47% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                    5      0.06%     59.53% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     2      0.02%     59.55% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   2      0.02%     59.58% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     59.58% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     59.58% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     59.58% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     59.58% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     59.58% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     59.58% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     59.58% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     59.58% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     59.58% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     59.58% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     59.58% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     59.58% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     59.58% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     59.58% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     59.58% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     59.58% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     59.58% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     59.58% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     59.58% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     59.58% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     59.58% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     59.58% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     59.58% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     59.58% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     59.58% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead                 2249     27.10%     86.67% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite                1106     13.33%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu                  5034     58.89%     58.89% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                    5      0.06%     58.95% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     2      0.02%     58.97% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   2      0.02%     59.00% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     59.00% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     59.00% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     59.00% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     59.00% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     59.00% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     59.00% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     59.00% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     59.00% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     59.00% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     59.00% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     59.00% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     59.00% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     59.00% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     59.00% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     59.00% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     59.00% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     59.00% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     59.00% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     59.00% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     59.00% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     59.00% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     59.00% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     59.00% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     59.00% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     59.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead                 2396     28.03%     87.03% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite                1109     12.97%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total                   8300                       # Type of FU issued
-system.cpu.iq.rate                           0.189992                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                         162                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.019518                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads              31229                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes             12679                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses         7467                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total                   8548                       # Type of FU issued
+system.cpu.iq.rate                           0.197761                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                         202                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.023631                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads              32026                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes             12803                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses         7708                       # Number of integer instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_reads                   4                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_writes                  2                       # Number of floating instruction queue writes
 system.cpu.iq.fp_inst_queue_wakeup_accesses            2                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses                   8460                       # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses                   8748                       # Number of integer alu accesses
 system.cpu.iq.fp_alu_accesses                       2                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads               68                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads               86                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads         1305                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses            7                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.squashedLoads         1380                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses            5                       # Number of memory responses ignored because the instruction is squashed
 system.cpu.iew.lsq.thread0.memOrderViolation           10                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores          270                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedStores          288                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked            32                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.cacheBlocked            25                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                    872                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                     287                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                     5                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts               10750                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts                86                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts                  2468                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts                 1195                       # Number of dispatched store instructions
+system.cpu.iew.iewSquashCycles                    400                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                     479                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                     9                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts               10879                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts               152                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts                  2543                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts                 1213                       # Number of dispatched store instructions
 system.cpu.iew.iewDispNonSpecInsts                 12                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                      4                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                     0                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewIQFullEvents                      0                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                    10                       # Number of times the LSQ has become full, causing a stall
 system.cpu.iew.memOrderViolationEvents             10                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect            100                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect          365                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts                  465                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts                  7921                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts                  2110                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts               379                       # Number of squashed instructions skipped in execute
+system.cpu.iew.predictedTakenIncorrect            105                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect          359                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts                  464                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts                  8213                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts                  2257                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts               335                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                          1515                       # number of nop insts executed
-system.cpu.iew.exec_refs                         3187                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                     1350                       # Number of branches executed
-system.cpu.iew.exec_stores                       1077                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.181317                       # Inst execution rate
-system.cpu.iew.wb_sent                           7554                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                          7469                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                      2985                       # num instructions producing a value
-system.cpu.iew.wb_consumers                      4341                       # num instructions consuming a value
+system.cpu.iew.exec_nop                          1568                       # number of nop insts executed
+system.cpu.iew.exec_refs                         3348                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                     1425                       # Number of branches executed
+system.cpu.iew.exec_stores                       1091                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.190010                       # Inst execution rate
+system.cpu.iew.wb_sent                           7817                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                          7710                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                      2989                       # num instructions producing a value
+system.cpu.iew.wb_consumers                      4523                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.170970                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.687630                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       0.178373                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.660845                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts            4930                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts            5063                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls              10                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts               396                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples        13552                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.428940                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.213640                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts               392                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples        13824                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.420501                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.238844                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0        11200     82.64%     82.64% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1          943      6.96%     89.60% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2          594      4.38%     93.99% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3          344      2.54%     96.52% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4          162      1.20%     97.72% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5           97      0.72%     98.44% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6           69      0.51%     98.94% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7           41      0.30%     99.25% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8          102      0.75%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0        11590     83.84%     83.84% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1          886      6.41%     90.25% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2          537      3.88%     94.13% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3          260      1.88%     96.01% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4          148      1.07%     97.08% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5          189      1.37%     98.45% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6           68      0.49%     98.94% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7           40      0.29%     99.23% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8          106      0.77%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total        13552                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total        13824                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts                 5813                       # Number of instructions committed
 system.cpu.commit.committedOps                   5813                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -546,98 +545,98 @@ system.cpu.commit.op_class_0::MemWrite            925     15.91%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total              5813                       # Class of committed instruction
-system.cpu.commit.bw_lim_events                   102                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events                   106                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                        24180                       # The number of ROB reads
-system.cpu.rob.rob_writes                       22370                       # The number of ROB writes
-system.cpu.timesIdled                             295                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           29262                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads                        24581                       # The number of ROB reads
+system.cpu.rob.rob_writes                       22642                       # The number of ROB writes
+system.cpu.timesIdled                             280                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           28521                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                        5156                       # Number of Instructions Simulated
 system.cpu.committedOps                          5156                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               8.472847                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         8.472847                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.118024                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.118024                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                    10764                       # number of integer regfile reads
-system.cpu.int_regfile_writes                    5241                       # number of integer regfile writes
+system.cpu.cpi                               8.383243                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         8.383243                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.119286                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.119286                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                    11114                       # number of integer regfile reads
+system.cpu.int_regfile_writes                    5412                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                         3                       # number of floating regfile reads
 system.cpu.fp_regfile_writes                        1                       # number of floating regfile writes
-system.cpu.misc_regfile_reads                     148                       # number of misc regfile reads
-system.cpu.toL2Bus.throughput              1403502346                       # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq            428                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp           428                       # Transaction distribution
+system.cpu.misc_regfile_reads                     164                       # number of misc regfile reads
+system.cpu.toL2Bus.throughput              1427388196                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq            431                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp           431                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq           51                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp           51                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          676                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          282                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total               958                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        21632                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         9024                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total          30656                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus             30656                       # Total data (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          680                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          284                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total               964                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        21760                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         9088                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total          30848                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus             30848                       # Total data (bytes)
 system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy         239500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.occupancy         241000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          1.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy        571750                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          2.6                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy        226500                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          1.0                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy        575000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization          2.7                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy        228250                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization          1.1                       # Layer utilization (%)
 system.cpu.icache.tags.replacements                17                       # number of replacements
-system.cpu.icache.tags.tagsinuse           161.396825                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs                1520                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs               338                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs              4.497041                       # Average number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse           161.374264                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs                1615                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs               340                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs              4.750000                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   161.396825                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.078807                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.078807                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024          321                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          149                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          172                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.156738                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses              4280                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses             4280                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst         1520                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total            1520                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst          1520                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total             1520                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst         1520                       # number of overall hits
-system.cpu.icache.overall_hits::total            1520                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst          451                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total           451                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst          451                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total            451                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst          451                       # number of overall misses
-system.cpu.icache.overall_misses::total           451                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     31166000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     31166000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     31166000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     31166000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     31166000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     31166000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst         1971                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total         1971                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst         1971                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total         1971                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst         1971                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total         1971                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.228818                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.228818                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.228818                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.228818                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.228818                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.228818                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69104.212860                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 69104.212860                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 69104.212860                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 69104.212860                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 69104.212860                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 69104.212860                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs           47                       # number of cycles access was blocked
+system.cpu.icache.tags.occ_blocks::cpu.inst   161.374264                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.078796                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.078796                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          323                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          154                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          169                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.157715                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses              4476                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses             4476                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst         1615                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total            1615                       # number of ReadReq hits
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+system.cpu.icache.demand_hits::total             1615                       # number of demand (read+write) hits
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+system.cpu.icache.ReadReq_misses::cpu.inst          453                       # number of ReadReq misses
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+system.cpu.icache.overall_misses::cpu.inst          453                       # number of overall misses
+system.cpu.icache.overall_misses::total           453                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     31448500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     31448500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     31448500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     31448500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     31448500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     31448500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst         2068                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total         2068                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst         2068                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total         2068                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst         2068                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total         2068                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.219052                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.219052                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.219052                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.219052                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.219052                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.219052                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69422.737307                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 69422.737307                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 69422.737307                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 69422.737307                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 69422.737307                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 69422.737307                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs           48                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 1                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs           47                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs           48                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
@@ -647,109 +646,109 @@ system.cpu.icache.demand_mshr_hits::cpu.inst          113
 system.cpu.icache.demand_mshr_hits::total          113                       # number of demand (read+write) MSHR hits
 system.cpu.icache.overall_mshr_hits::cpu.inst          113                       # number of overall MSHR hits
 system.cpu.icache.overall_mshr_hits::total          113                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst          338                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total          338                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst          338                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total          338                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst          338                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total          338                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     24162750                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     24162750                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     24162750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     24162750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     24162750                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     24162750                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.171487                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.171487                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.171487                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.171487                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.171487                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.171487                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71487.426036                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71487.426036                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71487.426036                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 71487.426036                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71487.426036                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 71487.426036                       # average overall mshr miss latency
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+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.164410                       # mshr miss rate for ReadReq accesses
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+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst        72425                       # average ReadReq mshr miss latency
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+system.cpu.icache.overall_avg_mshr_miss_latency::total        72425                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse          221.498533                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse          222.300532                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs                  3                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs              425                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             0.007059                       # Average number of references to valid blocks.
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 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   163.688333                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data    57.810199                       # Average occupied blocks per requestor
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-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.012970                       # Percentage of cache occupancy per task id
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 system.cpu.l2cache.ReadReq_hits::cpu.inst            3                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total              3                       # number of ReadReq hits
 system.cpu.l2cache.demand_hits::cpu.inst            3                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::total               3                       # number of demand (read+write) hits
 system.cpu.l2cache.overall_hits::cpu.inst            3                       # number of overall hits
 system.cpu.l2cache.overall_hits::total              3                       # number of overall hits
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 system.cpu.l2cache.ReadExReq_misses::cpu.data           51                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total           51                       # number of ReadExReq misses
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 system.cpu.l2cache.ReadExReq_accesses::cpu.data           51                       # number of ReadExReq accesses(hits+misses)
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-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.991124                       # miss rate for ReadReq accesses
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 system.cpu.l2cache.ReadReq_miss_rate::cpu.data            1                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.992991                       # miss rate for ReadReq accesses
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 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.991124                       # miss rate for demand accesses
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 system.cpu.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
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 system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.993737                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71029.104478                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77619.444444                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 72424.705882                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74044.117647                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74044.117647                       # average ReadExReq miss latency
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-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76326.241135                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 72598.214286                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71029.104478                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76326.241135                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 72598.214286                       # average overall miss latency
+system.cpu.l2cache.overall_miss_rate::total     0.993776                       # miss rate for overall accesses
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+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71971.810089                       # average overall miss latency
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+system.cpu.l2cache.overall_avg_miss_latency::total 74323.068894                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -758,162 +757,162 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          335                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data           90                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total          425                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          337                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data           91                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total          428                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           51                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total           51                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst          335                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data          141                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total          476                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst          335                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data          141                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total          476                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     19559250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      5880750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     25440000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      3144250                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      3144250                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     19559250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      9025000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     28584250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     19559250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      9025000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     28584250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.991124                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          337                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data          142                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total          479                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          337                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data          142                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total          479                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     19999000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      6168250                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total     26167250                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      3423500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      3423500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     19999000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      9591750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     29590750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     19999000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      9591750                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     29590750                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.991176                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.992991                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.993039                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.991124                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.991176                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.993737                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.991124                       # mshr miss rate for overall accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.993776                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.991176                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.993737                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58385.820896                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65341.666667                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59858.823529                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61651.960784                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61651.960784                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58385.820896                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64007.092199                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60050.945378                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58385.820896                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64007.092199                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60050.945378                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.993776                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59344.213650                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67782.967033                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61138.434579                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67127.450980                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67127.450980                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59344.213650                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67547.535211                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61776.096033                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59344.213650                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67547.535211                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61776.096033                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.dcache.tags.replacements                 0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse            91.608220                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs                2400                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs               141                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             17.021277                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse            92.430317                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs                2508                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs               142                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             17.661972                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data    91.608220                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.022365                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.022365                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024          141                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_blocks::cpu.data    92.430317                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.022566                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.022566                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024          142                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           38                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          103                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024     0.034424                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses              5965                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses             5965                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data         1837                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total            1837                       # number of ReadReq hits
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          104                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024     0.034668                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses              6220                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses             6220                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data         1945                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total            1945                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data          563                       # number of WriteReq hits
 system.cpu.dcache.WriteReq_hits::total            563                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data          2400                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total             2400                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data         2400                       # number of overall hits
-system.cpu.dcache.overall_hits::total            2400                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data          150                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total           150                       # number of ReadReq misses
+system.cpu.dcache.demand_hits::cpu.data          2508                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total             2508                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data         2508                       # number of overall hits
+system.cpu.dcache.overall_hits::total            2508                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data          169                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total           169                       # number of ReadReq misses
 system.cpu.dcache.WriteReq_misses::cpu.data          362                       # number of WriteReq misses
 system.cpu.dcache.WriteReq_misses::total          362                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data          512                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total            512                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data          512                       # number of overall misses
-system.cpu.dcache.overall_misses::total           512                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data     10436500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     10436500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data     22532249                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total     22532249                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     32968749                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     32968749                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     32968749                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     32968749                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data         1987                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total         1987                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data          531                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total            531                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data          531                       # number of overall misses
+system.cpu.dcache.overall_misses::total           531                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data     11709000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     11709000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data     23266249                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total     23266249                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     34975249                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     34975249                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     34975249                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     34975249                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data         2114                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total         2114                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data          925                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total          925                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data         2912                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total         2912                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data         2912                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total         2912                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.075491                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.075491                       # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data         3039                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total         3039                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data         3039                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total         3039                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.079943                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.079943                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.391351                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_miss_rate::total     0.391351                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.175824                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.175824                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.175824                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.175824                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 69576.666667                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 69576.666667                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62243.781768                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 62243.781768                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 64392.087891                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 64392.087891                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 64392.087891                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 64392.087891                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs          611                       # number of cycles access was blocked
+system.cpu.dcache.demand_miss_rate::cpu.data     0.174729                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.174729                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.174729                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.174729                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 69284.023669                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 69284.023669                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64271.406077                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 64271.406077                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 65866.758945                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 65866.758945                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 65866.758945                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 65866.758945                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs          573                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                11                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    55.545455                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    52.090909                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data           60                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total           60                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data           78                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total           78                       # number of ReadReq MSHR hits
 system.cpu.dcache.WriteReq_mshr_hits::cpu.data          311                       # number of WriteReq MSHR hits
 system.cpu.dcache.WriteReq_mshr_hits::total          311                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data          371                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total          371                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data          371                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total          371                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data           90                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total           90                       # number of ReadReq MSHR misses
+system.cpu.dcache.demand_mshr_hits::cpu.data          389                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total          389                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data          389                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total          389                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data           91                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total           91                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data           51                       # number of WriteReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::total           51                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data          141                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total          141                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data          141                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total          141                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      7079250                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      7079250                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      3828249                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      3828249                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data     10907499                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total     10907499                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data     10907499                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total     10907499                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.045294                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.045294                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.demand_mshr_misses::cpu.data          142                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total          142                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data          142                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total          142                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      7382750                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      7382750                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      4109999                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      4109999                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data     11492749                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total     11492749                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data     11492749                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total     11492749                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.043046                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.043046                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.055135                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.055135                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.048420                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.048420                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.048420                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.048420                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78658.333333                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78658.333333                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75063.705882                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75063.705882                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77358.148936                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 77358.148936                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77358.148936                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 77358.148936                       # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.046726                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.046726                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.046726                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.046726                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 81129.120879                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 81129.120879                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80588.215686                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80588.215686                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 80934.852113                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 80934.852113                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 80934.852113                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 80934.852113                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt
index ca8bce664..895c59829 100644
--- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt
@@ -1,57 +1,57 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000019                       # Number of seconds simulated
-sim_ticks                                    19030500                       # Number of ticks simulated
-final_tick                                   19030500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                    18857500                       # Number of ticks simulated
+final_tick                                   18857500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  17395                       # Simulator instruction rate (inst/s)
-host_op_rate                                    17394                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               57147442                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 218304                       # Number of bytes of host memory used
-host_seconds                                     0.33                       # Real time elapsed on the host
+host_inst_rate                                  41326                       # Simulator instruction rate (inst/s)
+host_op_rate                                    41320                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              134509153                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 232584                       # Number of bytes of host memory used
+host_seconds                                     0.14                       # Real time elapsed on the host
 sim_insts                                        5792                       # Number of instructions simulated
 sim_ops                                          5792                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst             22080                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst             21952                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data              6464                       # Number of bytes read from this memory
-system.physmem.bytes_read::total                28544                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        22080                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           22080                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst                345                       # Number of read requests responded to by this memory
+system.physmem.bytes_read::total                28416                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        21952                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           21952                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst                343                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data                101                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                   446                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst           1160242768                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            339665274                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              1499908042                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst      1160242768                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total         1160242768                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst          1160242768                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           339665274                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             1499908042                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                           446                       # Number of read requests accepted
+system.physmem.num_reads::total                   444                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst           1164099165                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            342781387                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              1506880552                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst      1164099165                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total         1164099165                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst          1164099165                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           342781387                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             1506880552                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                           444                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
-system.physmem.readBursts                         446                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                         444                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                    28544                       # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM                    28416                       # Total number of bytes read from DRAM
 system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
 system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                     28544                       # Total read bytes from the system interface side
+system.physmem.bytesReadSys                     28416                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
 system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                  70                       # Per bank write bursts
+system.physmem.perBankRdBursts::0                  71                       # Per bank write bursts
 system.physmem.perBankRdBursts::1                  42                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                  54                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                  59                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                  55                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                  58                       # Per bank write bursts
 system.physmem.perBankRdBursts::4                  53                       # Per bank write bursts
 system.physmem.perBankRdBursts::5                  61                       # Per bank write bursts
 system.physmem.perBankRdBursts::6                  52                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                  13                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                   8                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                  10                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                   9                       # Per bank write bursts
 system.physmem.perBankRdBursts::9                  28                       # Per bank write bursts
-system.physmem.perBankRdBursts::10                  2                       # Per bank write bursts
+system.physmem.perBankRdBursts::10                  1                       # Per bank write bursts
 system.physmem.perBankRdBursts::11                  0                       # Per bank write bursts
 system.physmem.perBankRdBursts::12                  0                       # Per bank write bursts
 system.physmem.perBankRdBursts::13                  0                       # Per bank write bursts
@@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                        18902000                       # Total gap between requests
+system.physmem.totGap                        18724000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                     446                       # Read request sizes (log2)
+system.physmem.readPktSize::6                     444                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -90,11 +90,11 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                       245                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       146                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                       240                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       144                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::2                        41                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                        10                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                         3                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                        14                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                         4                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
@@ -186,71 +186,72 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples           77                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      342.441558                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     199.719469                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     351.121005                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127             27     35.06%     35.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255           18     23.38%     58.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383            6      7.79%     66.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511            5      6.49%     72.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639            5      6.49%     79.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767            2      2.60%     81.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023            3      3.90%     85.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151           11     14.29%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total             77                       # Bytes accessed per row activation
-system.physmem.totQLat                        3354000                       # Total ticks spent queuing
-system.physmem.totMemAccLat                  11716500                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                      2230000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        7520.18                       # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples           79                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      333.772152                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     192.283764                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     349.893315                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127             30     37.97%     37.97% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255           17     21.52%     59.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383            8     10.13%     69.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511            4      5.06%     74.68% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639            3      3.80%     78.48% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767            2      2.53%     81.01% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895            1      1.27%     82.28% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023            3      3.80%     86.08% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151           11     13.92%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total             79                       # Bytes accessed per row activation
+system.physmem.totQLat                        3609000                       # Total ticks spent queuing
+system.physmem.totMemAccLat                  11934000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                      2220000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        8128.38                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  26270.18                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                        1499.91                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  26878.38                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                        1506.88                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                     1499.91                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                     1506.88                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                          11.72                       # Data bus utilization in percentage
-system.physmem.busUtilRead                      11.72                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                          11.77                       # Data bus utilization in percentage
+system.physmem.busUtilRead                      11.77                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.80                       # Average read queue length when enqueuing
+system.physmem.avgRdQLen                         1.82                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                        358                       # Number of row buffer hits during reads
+system.physmem.readRowHits                        356                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   80.27                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   80.18                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                        42381.17                       # Average gap between requests
-system.physmem.pageHitRate                      80.27                       # Row buffer hit rate, read and write combined
+system.physmem.avgGap                        42171.17                       # Average gap between requests
+system.physmem.pageHitRate                      80.18                       # Row buffer hit rate, read and write combined
 system.physmem.memoryStateTime::IDLE            11000                       # Time in different power states
 system.physmem.memoryStateTime::REF            520000                       # Time in different power states
 system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
 system.physmem.memoryStateTime::ACT          15315250                       # Time in different power states
 system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.membus.throughput                   1499908042                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq                 399                       # Transaction distribution
-system.membus.trans_dist::ReadResp                399                       # Transaction distribution
+system.membus.throughput                   1506880552                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq                 397                       # Transaction distribution
+system.membus.trans_dist::ReadResp                397                       # Transaction distribution
 system.membus.trans_dist::ReadExReq                47                       # Transaction distribution
 system.membus.trans_dist::ReadExResp               47                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port          892                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                    892                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        28544                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total               28544                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus                  28544                       # Total data (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port          888                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                    888                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        28416                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total               28416                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus                  28416                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy              559000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy              555500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               2.9                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            4177750                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization             22.0                       # Layer utilization (%)
+system.membus.respLayer1.occupancy            4160750                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization             22.1                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.branchPred.lookups                    2252                       # Number of BP lookups
-system.cpu.branchPred.condPredicted              1816                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect               419                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups                 1865                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                     610                       # Number of BTB hits
+system.cpu.branchPred.lookups                    2332                       # Number of BP lookups
+system.cpu.branchPred.condPredicted              1883                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect               415                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups                 1931                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                     661                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             32.707775                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                     199                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect                 32                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             34.230968                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                     219                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect                 31                       # Number of incorrect RAS predictions.
 system.cpu.dtb.read_hits                            0                       # DTB read hits
 system.cpu.dtb.read_misses                          0                       # DTB read misses
 system.cpu.dtb.read_accesses                        0                       # DTB read accesses
@@ -270,235 +271,237 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                    9                       # Number of system calls
-system.cpu.numCycles                            38062                       # number of cpu cycles simulated
+system.cpu.numCycles                            37716                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles               7462                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                          13226                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                        2252                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches                809                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                          2276                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                    1296                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles                    871                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.CacheLines                      1823                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                   310                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples              11476                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.152492                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.564431                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles               7977                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                          13500                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                        2332                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches                880                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                          3710                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                     864                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles                    3                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles           159                       # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles           22                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                      1829                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                   300                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples              12303                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.097293                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.503786                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                     9200     80.17%     80.17% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                      178      1.55%     81.72% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                      178      1.55%     83.27% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                      145      1.26%     84.53% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                      228      1.99%     86.52% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                      133      1.16%     87.68% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                      261      2.27%     89.95% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                      110      0.96%     90.91% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                     1043      9.09%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                     9940     80.79%     80.79% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                      189      1.54%     82.33% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                      216      1.76%     84.09% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                      152      1.24%     85.32% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                      247      2.01%     87.33% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                      139      1.13%     88.46% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                      253      2.06%     90.51% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                      114      0.93%     91.44% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                     1053      8.56%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total                11476                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.059167                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.347486                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                     7479                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles                  1089                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                      2174                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles                    20                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                    714                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved                  342                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                   154                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts                  11804                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                   436                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                    714                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                     7660                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                     212                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles            446                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                      2016                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles                   428                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts                  11368                       # Number of instructions processed by rename
-system.cpu.rename.IQFullEvents                      4                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                    165                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                    241                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands                9753                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups                 18286                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups            18260                       # Number of integer rename lookups
+system.cpu.fetch.rateDist::total                12303                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.061831                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.357938                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                     7389                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles                  2550                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                      1951                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles                   130                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                    283                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved                  336                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                   150                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts                  11555                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                   471                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                    283                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                     7548                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                     922                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles            607                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                      1916                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles                  1027                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts                  11189                       # Number of instructions processed by rename
+system.cpu.rename.IQFullEvents                     12                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                     25                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents                    968                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands                9624                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups                 18111                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups            18085                       # Number of integer rename lookups
 system.cpu.rename.fp_rename_lookups                26                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps                  4998                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                     4755                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.UndoneMaps                     4626                       # Number of HB maps that are undone due to squashing
 system.cpu.rename.serializingInsts                 27                       # count of serializing insts renamed
 system.cpu.rename.tempSerializingInsts             27                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                       259                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads                 2025                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores                1841                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads                53                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores               33                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                      10356                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                  57                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                      8929                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued               241                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined            4296                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined         3542                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved             41                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples         11476                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.778059                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.545863                       # Number of insts issued each cycle
+system.cpu.rename.skidInsts                       351                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads                 2013                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores                1831                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads                52                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores               29                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                      10314                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                  63                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                      9108                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued                73                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined            4178                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined         3333                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved             47                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples         12303                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.740307                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.567670                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0                8265     72.02%     72.02% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1                1011      8.81%     80.83% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2                 683      5.95%     86.78% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3                 469      4.09%     90.87% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4                 473      4.12%     94.99% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5                 313      2.73%     97.72% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6                 182      1.59%     99.30% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7                  44      0.38%     99.69% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8                  36      0.31%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0                9185     74.66%     74.66% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1                 929      7.55%     82.21% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2                 638      5.19%     87.39% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3                 470      3.82%     91.21% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4                 430      3.50%     94.71% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                 294      2.39%     97.10% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6                 241      1.96%     99.06% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7                  71      0.58%     99.63% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8                  45      0.37%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total           11476                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total           12303                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                      11      6.21%      6.21% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%      6.21% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      6.21% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      6.21% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      6.21% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      6.21% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      6.21% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      6.21% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      6.21% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      6.21% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      6.21% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      6.21% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      6.21% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      6.21% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      6.21% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      6.21% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      6.21% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      6.21% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      6.21% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      6.21% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      6.21% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      6.21% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      6.21% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      6.21% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      6.21% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      6.21% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      6.21% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      6.21% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      6.21% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                     75     42.37%     48.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                    91     51.41%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                      10      3.98%      3.98% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      3.98% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      3.98% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      3.98% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      3.98% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      3.98% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      3.98% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      3.98% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      3.98% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      3.98% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      3.98% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      3.98% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      3.98% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      3.98% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      3.98% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      3.98% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      3.98% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      3.98% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      3.98% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      3.98% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      3.98% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      3.98% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      3.98% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      3.98% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      3.98% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      3.98% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      3.98% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      3.98% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      3.98% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                    122     48.61%     52.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                   119     47.41%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu                  5495     61.54%     61.54% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                    0      0.00%     61.54% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     61.54% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   2      0.02%     61.56% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     61.56% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     61.56% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     61.56% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     61.56% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     61.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     61.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     61.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     61.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     61.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     61.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     61.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     61.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     61.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     61.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     61.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     61.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     61.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     61.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     61.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     61.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     61.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     61.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     61.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     61.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     61.56% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead                 1798     20.14%     81.70% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite                1634     18.30%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu                  5539     60.81%     60.81% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                    0      0.00%     60.81% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     60.81% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   2      0.02%     60.84% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     60.84% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     60.84% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     60.84% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     60.84% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     60.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     60.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     60.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     60.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     60.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     60.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     60.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     60.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     60.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     60.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     60.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     60.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     60.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     60.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     60.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     60.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     60.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     60.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     60.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     60.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     60.84% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead                 1909     20.96%     81.80% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite                1658     18.20%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total                   8929                       # Type of FU issued
-system.cpu.iq.rate                           0.234591                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                         177                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.019823                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads              29690                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes             14680                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses         8151                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total                   9108                       # Type of FU issued
+system.cpu.iq.rate                           0.241489                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                         251                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.027558                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads              30781                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes             14531                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses         8273                       # Number of integer instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_reads                  62                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes                 36                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_writes                 31                       # Number of floating instruction queue writes
 system.cpu.iq.fp_inst_queue_wakeup_accesses           27                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses                   9072                       # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses                   9325                       # Number of integer alu accesses
 system.cpu.iq.fp_alu_accesses                      34                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads               78                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads               79                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads         1064                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses            1                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.squashedLoads         1052                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses            2                       # Number of memory responses ignored because the instruction is squashed
 system.cpu.iew.lsq.thread0.memOrderViolation            7                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores          795                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedStores          785                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu.iew.lsq.thread0.rescheduledLoads            1                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked             9                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.cacheBlocked             8                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                    714                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                     160                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                    48                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts               10413                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts                54                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts                  2025                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts                 1841                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts                 48                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                      9                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                    38                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles                    283                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                     835                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                    80                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts               10377                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts                18                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts                  2013                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts                 1831                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts                 54                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                     11                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                    70                       # Number of times the LSQ has become full, causing a stall
 system.cpu.iew.memOrderViolationEvents              7                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect             66                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect          262                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts                  328                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts                  8526                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts                  1682                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts               403                       # Number of squashed instructions skipped in execute
+system.cpu.iew.predictedTakenIncorrect             69                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect          277                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts                  346                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts                  8702                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts                  1775                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts               406                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                             0                       # number of nop insts executed
-system.cpu.iew.exec_refs                         3211                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                     1353                       # Number of branches executed
-system.cpu.iew.exec_stores                       1529                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.224003                       # Inst execution rate
-system.cpu.iew.wb_sent                           8294                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                          8178                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                      4388                       # num instructions producing a value
-system.cpu.iew.wb_consumers                      6958                       # num instructions consuming a value
+system.cpu.iew.exec_refs                         3329                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                     1361                       # Number of branches executed
+system.cpu.iew.exec_stores                       1554                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.230724                       # Inst execution rate
+system.cpu.iew.wb_sent                           8430                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                          8300                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                      4483                       # num instructions producing a value
+system.cpu.iew.wb_consumers                      7102                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.214860                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.630641                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       0.220066                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.631231                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts            4620                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts            4587                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls              16                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts               266                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples        10762                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.538190                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.389247                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts               277                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples        11593                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.499612                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.370164                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0         8538     79.33%     79.33% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1          887      8.24%     87.58% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2          552      5.13%     92.71% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3          240      2.23%     94.94% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4          177      1.64%     96.58% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5           96      0.89%     97.47% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6          118      1.10%     98.57% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7           47      0.44%     99.01% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8          107      0.99%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0         9440     81.43%     81.43% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1          839      7.24%     88.67% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2          524      4.52%     93.19% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3          224      1.93%     95.12% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4          167      1.44%     96.56% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5          112      0.97%     97.52% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6          115      0.99%     98.52% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7           61      0.53%     99.04% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8          111      0.96%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total        10762                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total        11593                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts                 5792                       # Number of instructions committed
 system.cpu.commit.committedOps                   5792                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -544,148 +547,148 @@ system.cpu.commit.op_class_0::MemWrite           1046     18.06%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total              5792                       # Class of committed instruction
-system.cpu.commit.bw_lim_events                   107                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events                   111                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                        21067                       # The number of ROB reads
-system.cpu.rob.rob_writes                       21539                       # The number of ROB writes
-system.cpu.timesIdled                             248                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           26586                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads                        21861                       # The number of ROB reads
+system.cpu.rob.rob_writes                       21469                       # The number of ROB writes
+system.cpu.timesIdled                             245                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           25413                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                        5792                       # Number of Instructions Simulated
 system.cpu.committedOps                          5792                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               6.571478                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         6.571478                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.152173                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.152173                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                    13502                       # number of integer regfile reads
-system.cpu.int_regfile_writes                    7065                       # number of integer regfile writes
+system.cpu.cpi                               6.511740                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         6.511740                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.153569                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.153569                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                    13743                       # number of integer regfile reads
+system.cpu.int_regfile_writes                    7176                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                        25                       # number of floating regfile reads
 system.cpu.fp_regfile_writes                        2                       # number of floating regfile writes
-system.cpu.toL2Bus.throughput              1523449200                       # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq            406                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp           406                       # Transaction distribution
+system.cpu.toL2Bus.throughput              1530637677                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq            405                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp           404                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq           47                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp           47                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          702                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          699                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          204                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total               906                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        22464                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total               903                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        22336                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         6528                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total          28992                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus             28992                       # Total data (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total          28864                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus             28864                       # Total data (bytes)
 system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy         226500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.occupancy         226000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          1.2                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy        588250                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy        584250                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          3.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy        162000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy        162500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.9                       # Layer utilization (%)
 system.cpu.icache.tags.replacements                 0                       # number of replacements
-system.cpu.icache.tags.tagsinuse           169.076059                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs                1380                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs               351                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs              3.931624                       # Average number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse           170.472010                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs                1391                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs               349                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs              3.985673                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   169.076059                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.082557                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.082557                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024          351                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          196                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_blocks::cpu.inst   170.472010                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.083238                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.083238                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          349                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          194                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1          155                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.171387                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses              3997                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses             3997                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst         1380                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total            1380                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst          1380                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total             1380                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst         1380                       # number of overall hits
-system.cpu.icache.overall_hits::total            1380                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst          443                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total           443                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst          443                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total            443                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst          443                       # number of overall misses
-system.cpu.icache.overall_misses::total           443                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     29586250                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     29586250                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     29586250                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     29586250                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     29586250                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     29586250                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst         1823                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total         1823                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst         1823                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total         1823                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst         1823                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total         1823                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.243006                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.243006                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.243006                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.243006                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.243006                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.243006                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66786.117381                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 66786.117381                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 66786.117381                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 66786.117381                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 66786.117381                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 66786.117381                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs          460                       # number of cycles access was blocked
+system.cpu.icache.tags.occ_task_id_percent::1024     0.170410                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses              4007                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses             4007                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst         1391                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total            1391                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst          1391                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total             1391                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst         1391                       # number of overall hits
+system.cpu.icache.overall_hits::total            1391                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          438                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           438                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          438                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            438                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          438                       # number of overall misses
+system.cpu.icache.overall_misses::total           438                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     29787250                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     29787250                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     29787250                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     29787250                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     29787250                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     29787250                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst         1829                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total         1829                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst         1829                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total         1829                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst         1829                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total         1829                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.239475                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.239475                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.239475                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.239475                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.239475                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.239475                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68007.420091                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 68007.420091                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 68007.420091                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 68007.420091                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 68007.420091                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 68007.420091                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs          404                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                 6                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 5                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    76.666667                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    80.800000                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst           92                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total           92                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst           92                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total           92                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst           92                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total           92                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst          351                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total          351                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst          351                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total          351                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst          351                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total          351                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     24098750                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     24098750                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     24098750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     24098750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     24098750                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     24098750                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.192540                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.192540                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.192540                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.192540                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.192540                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.192540                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68657.407407                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68657.407407                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68657.407407                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 68657.407407                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68657.407407                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 68657.407407                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst           88                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total           88                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst           88                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total           88                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst           88                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total           88                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          350                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          350                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          350                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          350                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          350                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total          350                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     24058750                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     24058750                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     24058750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     24058750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     24058750                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     24058750                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.191361                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.191361                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.191361                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.191361                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.191361                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.191361                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68739.285714                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68739.285714                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68739.285714                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 68739.285714                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68739.285714                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 68739.285714                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse          199.437860                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse          201.157905                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs                  7                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs              399                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             0.017544                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs              397                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             0.017632                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   167.936913                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data    31.500947                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.005125                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.000961                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.006086                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024          399                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          215                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   169.317933                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data    31.839972                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.005167                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.000972                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.006139                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024          397                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          213                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::1          184                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.012177                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses             4070                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses            4070                       # Number of data accesses
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.012115                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses             4060                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses            4060                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.inst            6                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data            1                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total              7                       # number of ReadReq hits
@@ -695,61 +698,61 @@ system.cpu.l2cache.demand_hits::total               7                       # nu
 system.cpu.l2cache.overall_hits::cpu.inst            6                       # number of overall hits
 system.cpu.l2cache.overall_hits::cpu.data            1                       # number of overall hits
 system.cpu.l2cache.overall_hits::total              7                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst          345                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.inst          344                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_misses::cpu.data           54                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total          399                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total          398                       # number of ReadReq misses
 system.cpu.l2cache.ReadExReq_misses::cpu.data           47                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total           47                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst          345                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.inst          344                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::cpu.data          101                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total           446                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst          345                       # number of overall misses
+system.cpu.l2cache.demand_misses::total           445                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst          344                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data          101                       # number of overall misses
-system.cpu.l2cache.overall_misses::total          446                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     23687250                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data      4073750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total     27761000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      3627250                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total      3627250                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     23687250                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data      7701000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     31388250                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     23687250                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data      7701000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     31388250                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst          351                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.overall_misses::total          445                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     23649250                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data      4137750                       # number of ReadReq miss cycles
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+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      3745250                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total      3745250                       # number of ReadExReq miss cycles
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+system.cpu.l2cache.demand_miss_latency::cpu.data      7883000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     31532250                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     23649250                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data      7883000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     31532250                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst          350                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::cpu.data           55                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total          406                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total          405                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data           47                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total           47                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst          351                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst          350                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::cpu.data          102                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total          453                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst          351                       # number of overall (read+write) accesses
+system.cpu.l2cache.demand_accesses::total          452                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst          350                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.data          102                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total          453                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.982906                       # miss rate for ReadReq accesses
+system.cpu.l2cache.overall_accesses::total          452                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.982857                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.981818                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.982759                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.982716                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.982906                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.982857                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.data     0.990196                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.984547                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.982906                       # miss rate for overall accesses
+system.cpu.l2cache.demand_miss_rate::total     0.984513                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.982857                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.990196                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.984547                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68658.695652                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75439.814815                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 69576.441103                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77175.531915                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77175.531915                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68658.695652                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76247.524752                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 70377.242152                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68658.695652                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76247.524752                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 70377.242152                       # average overall miss latency
+system.cpu.l2cache.overall_miss_rate::total     0.984513                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68747.819767                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data        76625                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 69816.582915                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79686.170213                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79686.170213                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68747.819767                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78049.504950                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 70858.988764                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68747.819767                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78049.504950                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 70858.988764                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -758,130 +761,130 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          345                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          344                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadReq_mshr_misses::cpu.data           54                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total          399                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total          398                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           47                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total           47                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst          345                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          344                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.data          101                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total          446                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst          345                       # number of overall MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total          445                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          344                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data          101                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total          446                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     19339750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      3409250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     22749000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      3052750                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      3052750                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     19339750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      6462000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     25801750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     19339750                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      6462000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     25801750                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.982906                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.overall_mshr_misses::total          445                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     19325250                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      3474750                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total     22800000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      3169250                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      3169250                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     19325250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      6644000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     25969250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     19325250                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      6644000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     25969250                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.982857                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.981818                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.982759                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.982716                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.982906                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.982857                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.990196                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.984547                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.982906                       # mshr miss rate for overall accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.984513                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.982857                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.990196                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.984547                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56057.246377                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63134.259259                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57015.037594                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64952.127660                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64952.127660                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56057.246377                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63980.198020                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57851.457399                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56057.246377                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63980.198020                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57851.457399                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.984513                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56178.052326                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64347.222222                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57286.432161                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67430.851064                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67430.851064                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56178.052326                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65782.178218                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58357.865169                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56178.052326                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65782.178218                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58357.865169                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.dcache.tags.replacements                 0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse            63.722947                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs                2180                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse            64.061622                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs                2261                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs               102                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             21.372549                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             22.166667                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data    63.722947                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.015557                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.015557                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data    64.061622                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.015640                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.015640                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          102                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           37                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1           65                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           38                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           64                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024     0.024902                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses              5332                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses             5332                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data         1465                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total            1465                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data          715                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total            715                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data          2180                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total             2180                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data         2180                       # number of overall hits
-system.cpu.dcache.overall_hits::total            2180                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data          104                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total           104                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data          331                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total          331                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data          435                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total            435                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data          435                       # number of overall misses
-system.cpu.dcache.overall_misses::total           435                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data      7380250                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total      7380250                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data     21128996                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total     21128996                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     28509246                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     28509246                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     28509246                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     28509246                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data         1569                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total         1569                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.tags.tag_accesses              5528                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses             5528                       # Number of data accesses
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+system.cpu.dcache.ReadReq_hits::total            1554                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data          707                       # number of WriteReq hits
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+system.cpu.dcache.overall_hits::total            2261                       # number of overall hits
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+system.cpu.dcache.ReadReq_misses::total           113                       # number of ReadReq misses
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+system.cpu.dcache.WriteReq_misses::total          339                       # number of WriteReq misses
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+system.cpu.dcache.WriteReq_miss_latency::total     22327496                       # number of WriteReq miss cycles
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+system.cpu.dcache.overall_miss_latency::total     30449746                       # number of overall miss cycles
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+system.cpu.dcache.ReadReq_accesses::total         1667                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data         1046                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total         1046                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data         2615                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total         2615                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data         2615                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total         2615                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.066284                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.066284                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.316444                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.316444                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.166348                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.166348                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.166348                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.166348                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70963.942308                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 70963.942308                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63833.824773                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 63833.824773                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 65538.496552                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 65538.496552                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 65538.496552                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 65538.496552                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs          492                       # number of cycles access was blocked
+system.cpu.dcache.demand_accesses::cpu.data         2713                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total         2713                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data         2713                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total         2713                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.067786                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.067786                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.324092                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.324092                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.166605                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.166605                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.166605                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.166605                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71878.318584                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 71878.318584                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65862.820059                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 65862.820059                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 67366.694690                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 67366.694690                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 67366.694690                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 67366.694690                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs          597                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                 5                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 6                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    98.400000                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    99.500000                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data           49                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total           49                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data          284                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total          284                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data          333                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total          333                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data          333                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total          333                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data           58                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total           58                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data          292                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total          292                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data          350                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total          350                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data          350                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total          350                       # number of overall MSHR hits
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data           55                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total           55                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data           47                       # number of WriteReq MSHR misses
@@ -890,30 +893,30 @@ system.cpu.dcache.demand_mshr_misses::cpu.data          102
 system.cpu.dcache.demand_mshr_misses::total          102                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data          102                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total          102                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      4139250                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      4139250                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      3677248                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      3677248                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data      7816498                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total      7816498                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data      7816498                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total      7816498                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.035054                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.035054                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      4203250                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      4203250                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      3795248                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      3795248                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data      7998498                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total      7998498                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data      7998498                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total      7998498                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.032993                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.032993                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.044933                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.044933                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.039006                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.039006                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.039006                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.039006                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 75259.090909                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75259.090909                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78239.319149                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78239.319149                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76632.333333                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 76632.333333                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76632.333333                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 76632.333333                       # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.037597                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.037597                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.037597                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.037597                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76422.727273                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76422.727273                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80749.957447                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80749.957447                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78416.647059                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 78416.647059                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78416.647059                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 78416.647059                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt
index be2005774..f7173c445 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt
@@ -1,34 +1,34 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000020                       # Number of seconds simulated
-sim_ticks                                    19813000                       # Number of ticks simulated
-final_tick                                   19813000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                    19744000                       # Number of ticks simulated
+final_tick                                   19744000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  35950                       # Simulator instruction rate (inst/s)
-host_op_rate                                    65125                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              132368943                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 240140                       # Number of bytes of host memory used
-host_seconds                                     0.15                       # Real time elapsed on the host
+host_inst_rate                                  27433                       # Simulator instruction rate (inst/s)
+host_op_rate                                    49695                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              100653274                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 249652                       # Number of bytes of host memory used
+host_seconds                                     0.20                       # Real time elapsed on the host
 sim_insts                                        5380                       # Number of instructions simulated
 sim_ops                                          9747                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst             17536                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data              9088                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst             17600                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data              9024                       # Number of bytes read from this memory
 system.physmem.bytes_read::total                26624                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        17536                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           17536                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst                274                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data                142                       # Number of read requests responded to by this memory
+system.physmem.bytes_inst_read::cpu.inst        17600                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           17600                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst                275                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data                141                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                   416                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst            885075456                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            458688740                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              1343764195                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst       885075456                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          885075456                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           885075456                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           458688740                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             1343764195                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst            891410049                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            457050243                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              1348460292                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst       891410049                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          891410049                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           891410049                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           457050243                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             1348460292                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.readReqs                           417                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
 system.physmem.readBursts                         417                       # Number of DRAM read bursts, including those serviced by the write queue
@@ -46,11 +46,11 @@ system.physmem.perBankRdBursts::1                   1                       # Pe
 system.physmem.perBankRdBursts::2                   6                       # Per bank write bursts
 system.physmem.perBankRdBursts::3                   8                       # Per bank write bursts
 system.physmem.perBankRdBursts::4                  50                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                  44                       # Per bank write bursts
+system.physmem.perBankRdBursts::5                  45                       # Per bank write bursts
 system.physmem.perBankRdBursts::6                  21                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                  36                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                  34                       # Per bank write bursts
 system.physmem.perBankRdBursts::8                  22                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                  73                       # Per bank write bursts
+system.physmem.perBankRdBursts::9                  74                       # Per bank write bursts
 system.physmem.perBankRdBursts::10                 63                       # Per bank write bursts
 system.physmem.perBankRdBursts::11                 17                       # Per bank write bursts
 system.physmem.perBankRdBursts::12                  2                       # Per bank write bursts
@@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                        19764000                       # Total gap between requests
+system.physmem.totGap                        19695500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
@@ -90,11 +90,11 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                       248                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       129                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        35                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                         5                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                       243                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       127                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        37                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                         7                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                         3                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
@@ -186,50 +186,50 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples           97                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      250.721649                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     163.075563                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     270.532528                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127             33     34.02%     34.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255           36     37.11%     71.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383            9      9.28%     80.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511            5      5.15%     85.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767            6      6.19%     91.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023            3      3.09%     94.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151            5      5.15%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total             97                       # Bytes accessed per row activation
-system.physmem.totQLat                        3851250                       # Total ticks spent queuing
-system.physmem.totMemAccLat                  11670000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.bytesPerActivate::samples           98                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      242.285714                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     159.132678                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     257.193096                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127             35     35.71%     35.71% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255           32     32.65%     68.37% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383           12     12.24%     80.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511            6      6.12%     86.73% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767            6      6.12%     92.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023            4      4.08%     96.94% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151            3      3.06%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total             98                       # Bytes accessed per row activation
+system.physmem.totQLat                        4076000                       # Total ticks spent queuing
+system.physmem.totMemAccLat                  11894750                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                      2085000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        9235.61                       # Average queueing delay per DRAM burst
+system.physmem.avgQLat                        9774.58                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  27985.61                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                        1346.99                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  28524.58                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                        1351.70                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                     1346.99                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                     1351.70                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                          10.52                       # Data bus utilization in percentage
-system.physmem.busUtilRead                      10.52                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                          10.56                       # Data bus utilization in percentage
+system.physmem.busUtilRead                      10.56                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.61                       # Average read queue length when enqueuing
+system.physmem.avgRdQLen                         1.64                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                        310                       # Number of row buffer hits during reads
+system.physmem.readRowHits                        309                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   74.34                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   74.10                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                        47395.68                       # Average gap between requests
-system.physmem.pageHitRate                      74.34                       # Row buffer hit rate, read and write combined
+system.physmem.avgGap                        47231.41                       # Average gap between requests
+system.physmem.pageHitRate                      74.10                       # Row buffer hit rate, read and write combined
 system.physmem.memoryStateTime::IDLE            11000                       # Time in different power states
 system.physmem.memoryStateTime::REF            520000                       # Time in different power states
 system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT          15315750                       # Time in different power states
+system.physmem.memoryStateTime::ACT          15315250                       # Time in different power states
 system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.membus.throughput                   1343764195                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq                 340                       # Transaction distribution
-system.membus.trans_dist::ReadResp                339                       # Transaction distribution
-system.membus.trans_dist::ReadExReq                77                       # Transaction distribution
-system.membus.trans_dist::ReadExResp               77                       # Transaction distribution
+system.membus.throughput                   1348460292                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq                 339                       # Transaction distribution
+system.membus.trans_dist::ReadResp                338                       # Transaction distribution
+system.membus.trans_dist::ReadExReq                78                       # Transaction distribution
+system.membus.trans_dist::ReadExResp               78                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port          833                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::total          833                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count::total                    833                       # Packet count per connected master and slave (bytes)
@@ -238,250 +238,250 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total        26624
 system.membus.tot_pkt_size::total               26624                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.data_through_bus                  26624                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy              508000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy              505000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               2.6                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            3892500                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization             19.6                       # Layer utilization (%)
+system.membus.respLayer1.occupancy            3897000                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization             19.7                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.branchPred.lookups                    3151                       # Number of BP lookups
-system.cpu.branchPred.condPredicted              3151                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect               538                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups                 2362                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                     784                       # Number of BTB hits
+system.cpu.branchPred.lookups                    3423                       # Number of BP lookups
+system.cpu.branchPred.condPredicted              3423                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect               535                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups                 2544                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                     864                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             33.192210                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                     213                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect                 80                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             33.962264                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                     247                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect                 76                       # Number of incorrect RAS predictions.
 system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
 system.cpu.workload.num_syscalls                   11                       # Number of system calls
-system.cpu.numCycles                            39627                       # number of cpu cycles simulated
+system.cpu.numCycles                            39489                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles              10249                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                          14342                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                        3151                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches                997                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                          4009                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                    2516                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles                   5030                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                   61                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles           499                       # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines                      2013                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                   271                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples              21739                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.176503                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.686230                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles              10915                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                          15528                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                        3423                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches               1111                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                          9222                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                    1202                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles                   54                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles          1088                       # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles           13                       # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.CacheLines                      2168                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                   278                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples              21893                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.270406                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.764504                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                    17828     82.01%     82.01% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                      213      0.98%     82.99% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                      156      0.72%     83.71% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                      227      1.04%     84.75% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                      194      0.89%     85.64% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                      208      0.96%     86.60% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                      291      1.34%     87.94% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                      168      0.77%     88.71% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                     2454     11.29%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                    17618     80.47%     80.47% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                      236      1.08%     81.55% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                      174      0.79%     82.35% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                      259      1.18%     83.53% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                      208      0.95%     84.48% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                      227      1.04%     85.52% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                      339      1.55%     87.06% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                      205      0.94%     88.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                     2627     12.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total                21739                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.079516                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.361925                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                    11168                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles                  4895                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                      3648                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles                   137                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                   1891                       # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts                  24503                       # Number of instructions handled by decode
-system.cpu.rename.SquashCycles                   1891                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                    11399                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                     477                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles            595                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                      3548                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles                  3829                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts                  23145                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                    10                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                     51                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.SQFullEvents                   3750                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands               25950                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups                 56380                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups            31990                       # Number of integer rename lookups
+system.cpu.fetch.rateDist::total                21893                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.086682                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.393223                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                    10660                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles                  6840                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                      3336                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles                   456                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                    601                       # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts                  25755                       # Number of instructions handled by decode
+system.cpu.rename.SquashCycles                    601                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                    10929                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                    2194                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles            719                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                      3480                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles                  3970                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts                  24219                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                    12                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                     93                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.SQFullEvents                   3820                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands               27591                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups                 59364                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups            33558                       # Number of integer rename lookups
 system.cpu.rename.fp_rename_lookups                 4                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps                 11063                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                    14887                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts                 33                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts             33                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                      1258                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads                 2293                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores                1619                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads                15                       # Number of conflicting loads.
+system.cpu.rename.UndoneMaps                    16528                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts                 29                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts             29                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                      1503                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads                 2441                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores                1612                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads                22                       # Number of conflicting loads.
 system.cpu.memDep0.conflictingStores                6                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                      20529                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                  28                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                     17116                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued               311                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined           10025                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined        14683                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved             16                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples         21739                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.787341                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.689074                       # Number of insts issued each cycle
+system.cpu.iq.iqInstsAdded                      21443                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                  25                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                     17897                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued                80                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined           11052                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined        16525                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved             13                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples         21893                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.817476                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.773238                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0               16539     76.08%     76.08% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1                1246      5.73%     81.81% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2                 983      4.52%     86.33% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3                 694      3.19%     89.53% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4                 782      3.60%     93.12% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5                 618      2.84%     95.97% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6                 580      2.67%     98.63% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7                 252      1.16%     99.79% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8                  45      0.21%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0               16772     76.61%     76.61% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1                1137      5.19%     81.80% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2                 886      4.05%     85.85% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3                 636      2.91%     88.75% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4                 833      3.80%     92.56% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                 590      2.69%     95.25% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6                 599      2.74%     97.99% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7                 316      1.44%     99.43% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8                 124      0.57%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total           21739                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total           21893                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                     136     76.40%     76.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%     76.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     76.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     76.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     76.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     76.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     76.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     76.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     76.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     76.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     76.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     76.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     76.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     76.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     76.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     76.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     76.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     76.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     76.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     76.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     76.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     76.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     76.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     76.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     76.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     76.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     76.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     76.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     76.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                     26     14.61%     91.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                    16      8.99%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                     174     77.68%     77.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%     77.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     77.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     77.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     77.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     77.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     77.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     77.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     77.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     77.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     77.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     77.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     77.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     77.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     77.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     77.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     77.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     77.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     77.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     77.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     77.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     77.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     77.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     77.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     77.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     77.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     77.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     77.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     77.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                     31     13.84%     91.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                    19      8.48%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 3      0.02%      0.02% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu                 13738     80.26%     80.28% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                    5      0.03%     80.31% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     7      0.04%     80.35% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     80.35% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     80.35% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     80.35% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     80.35% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     80.35% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     80.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     80.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     80.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     80.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     80.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     80.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     80.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     80.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     80.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     80.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     80.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     80.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     80.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     80.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     80.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     80.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     80.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     80.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     80.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     80.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     80.35% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead                 1970     11.51%     91.86% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite                1393      8.14%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu                 14382     80.36%     80.38% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                    4      0.02%     80.40% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     7      0.04%     80.44% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     80.44% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     80.44% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     80.44% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     80.44% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     80.44% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     80.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     80.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     80.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     80.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     80.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     80.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     80.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     80.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     80.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     80.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     80.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     80.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     80.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     80.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     80.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     80.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     80.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     80.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     80.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     80.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     80.44% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead                 2122     11.86%     92.29% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite                1379      7.71%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total                  17116                       # Type of FU issued
-system.cpu.iq.rate                           0.431928                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                         178                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.010400                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads              56452                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes             30591                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses        15728                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total                  17897                       # Type of FU issued
+system.cpu.iq.rate                           0.453215                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                         224                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.012516                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads              57983                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes             32531                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses        16370                       # Number of integer instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_reads                   8                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_writes                  4                       # Number of floating instruction queue writes
 system.cpu.iq.fp_inst_queue_wakeup_accesses            4                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses                  17287                       # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses                  18114                       # Number of integer alu accesses
 system.cpu.iq.fp_alu_accesses                       4                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads              197                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads              228                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads         1240                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.squashedLoads         1388                       # Number of loads squashed
 system.cpu.iew.lsq.thread0.ignoredResponses           11                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation           14                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores          684                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.memOrderViolation           16                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores          677                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked            21                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.cacheBlocked            18                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                   1891                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                     262                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                    29                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts               20557                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts                31                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts                  2293                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts                 1619                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts                 28                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                      4                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                    22                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents             14                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect            124                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect          573                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts                  697                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts                 16214                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts                  1838                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts               902                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                    601                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                    1862                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                    54                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts               21468                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts                32                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts                  2441                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts                 1612                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts                 25                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                      6                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                    46                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents             16                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect            125                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect          570                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts                  695                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts                 16926                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts                  1969                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts               971                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                             0                       # number of nop insts executed
-system.cpu.iew.exec_refs                         3129                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                     1636                       # Number of branches executed
-system.cpu.iew.exec_stores                       1291                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.409165                       # Inst execution rate
-system.cpu.iew.wb_sent                          15955                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                         15732                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                     10485                       # num instructions producing a value
-system.cpu.iew.wb_consumers                     16294                       # num instructions consuming a value
+system.cpu.iew.exec_refs                         3251                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                     1662                       # Number of branches executed
+system.cpu.iew.exec_stores                       1282                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.428626                       # Inst execution rate
+system.cpu.iew.wb_sent                          16636                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                         16374                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                     11006                       # num instructions producing a value
+system.cpu.iew.wb_consumers                     17135                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.397002                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.643488                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       0.414647                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.642311                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts           10809                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts           11720                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls              12                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts               599                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples        19848                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.491082                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.377621                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts               588                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples        19925                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.489184                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.394250                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0        16557     83.42%     83.42% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1         1016      5.12%     88.54% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2          561      2.83%     91.36% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3          767      3.86%     95.23% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4          387      1.95%     97.18% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5          137      0.69%     97.87% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6          118      0.59%     98.46% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7           73      0.37%     98.83% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8          232      1.17%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0        16685     83.74%     83.74% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1         1003      5.03%     88.77% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2          547      2.75%     91.52% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3          737      3.70%     95.22% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4          365      1.83%     97.05% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5          142      0.71%     97.76% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6          113      0.57%     98.33% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7           73      0.37%     98.70% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8          260      1.30%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total        19848                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total        19925                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts                 5380                       # Number of instructions committed
 system.cpu.commit.committedOps                   9747                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -527,95 +527,95 @@ system.cpu.commit.op_class_0::MemWrite            935      9.59%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total              9747                       # Class of committed instruction
-system.cpu.commit.bw_lim_events                   232                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events                   260                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                        40172                       # The number of ROB reads
-system.cpu.rob.rob_writes                       43025                       # The number of ROB writes
-system.cpu.timesIdled                             166                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           17888                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads                        41132                       # The number of ROB reads
+system.cpu.rob.rob_writes                       44928                       # The number of ROB writes
+system.cpu.timesIdled                             158                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           17596                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                        5380                       # Number of Instructions Simulated
 system.cpu.committedOps                          9747                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               7.365613                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         7.365613                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.135766                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.135766                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                    20766                       # number of integer regfile reads
-system.cpu.int_regfile_writes                   12432                       # number of integer regfile writes
+system.cpu.cpi                               7.339963                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         7.339963                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.136240                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.136240                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                    21340                       # number of integer regfile reads
+system.cpu.int_regfile_writes                   13120                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                         4                       # number of floating regfile reads
-system.cpu.cc_regfile_reads                      8051                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                     4869                       # number of cc regfile writes
-system.cpu.misc_regfile_reads                    7177                       # number of misc regfile reads
+system.cpu.cc_regfile_reads                      8069                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                     5036                       # number of cc regfile writes
+system.cpu.misc_regfile_reads                    7491                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
-system.cpu.toL2Bus.throughput              1346994398                       # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq            341                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp           340                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq           77                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp           77                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          550                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          285                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.throughput              1351701783                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq            340                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp           339                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq           78                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp           78                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          552                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          283                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count::total               835                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        17600                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         9088                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        17664                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         9024                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.tot_pkt_size::total          26688                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.data_through_bus             26688                       # Total data (bytes)
 system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
 system.cpu.toL2Bus.reqLayer0.occupancy         209000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          1.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy        461000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy        462750                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          2.3                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy        236000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy        234250                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          1.2                       # Layer utilization (%)
 system.cpu.icache.tags.replacements                 0                       # number of replacements
-system.cpu.icache.tags.tagsinuse           131.410773                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs                1641                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs               275                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs              5.967273                       # Average number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse           131.753616                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs                1800                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs               276                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs              6.521739                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   131.410773                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.064165                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.064165                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024          275                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          152                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          123                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.134277                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses              4301                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses             4301                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst         1641                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total            1641                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst          1641                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total             1641                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst         1641                       # number of overall hits
-system.cpu.icache.overall_hits::total            1641                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst          372                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total           372                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst          372                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total            372                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst          372                       # number of overall misses
-system.cpu.icache.overall_misses::total           372                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     25012250                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     25012250                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     25012250                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     25012250                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     25012250                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     25012250                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst         2013                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total         2013                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst         2013                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total         2013                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst         2013                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total         2013                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.184799                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.184799                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.184799                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.184799                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.184799                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.184799                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67237.231183                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 67237.231183                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 67237.231183                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 67237.231183                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 67237.231183                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 67237.231183                       # average overall miss latency
+system.cpu.icache.tags.occ_blocks::cpu.inst   131.753616                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.064333                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.064333                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          276                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          155                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          121                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.134766                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses              4612                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses             4612                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst         1800                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total            1800                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst          1800                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total             1800                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst         1800                       # number of overall hits
+system.cpu.icache.overall_hits::total            1800                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          368                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           368                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          368                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            368                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          368                       # number of overall misses
+system.cpu.icache.overall_misses::total           368                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     25386000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     25386000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     25386000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     25386000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     25386000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     25386000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst         2168                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total         2168                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst         2168                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total         2168                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst         2168                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total         2168                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.169742                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.169742                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.169742                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.169742                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.169742                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.169742                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68983.695652                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 68983.695652                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 68983.695652                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 68983.695652                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 68983.695652                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 68983.695652                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -624,52 +624,52 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst           97                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total           97                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst           97                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total           97                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst           97                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total           97                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst          275                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total          275                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst          275                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total          275                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst          275                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total          275                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     19562000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     19562000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     19562000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     19562000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     19562000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     19562000                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.136612                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.136612                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.136612                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.136612                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.136612                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.136612                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71134.545455                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71134.545455                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71134.545455                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 71134.545455                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71134.545455                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 71134.545455                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst           92                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total           92                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst           92                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total           92                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst           92                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total           92                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          276                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          276                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          276                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          276                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          276                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total          276                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     19887250                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     19887250                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     19887250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     19887250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     19887250                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     19887250                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.127306                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.127306                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.127306                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.127306                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.127306                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.127306                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72055.253623                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72055.253623                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72055.253623                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 72055.253623                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72055.253623                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 72055.253623                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse          164.472388                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse          163.478116                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs                  1                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs              339                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             0.002950                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs              338                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             0.002959                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   131.481156                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data    32.991232                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.004012                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.001007                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.005019                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024          339                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          185                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          154                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.010345                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   131.827183                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data    31.650934                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.004023                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.000966                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.004989                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024          338                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          189                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          149                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.010315                       # Percentage of cache occupancy per task id
 system.cpu.l2cache.tags.tag_accesses             3760                       # Number of tag accesses
 system.cpu.l2cache.tags.data_accesses            3760                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.inst            1                       # number of ReadReq hits
@@ -678,61 +678,61 @@ system.cpu.l2cache.demand_hits::cpu.inst            1                       # nu
 system.cpu.l2cache.demand_hits::total               1                       # number of demand (read+write) hits
 system.cpu.l2cache.overall_hits::cpu.inst            1                       # number of overall hits
 system.cpu.l2cache.overall_hits::total              1                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst          274                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data           66                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total          340                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data           77                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total           77                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst          274                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data          143                       # number of demand (read+write) misses
+system.cpu.l2cache.ReadReq_misses::cpu.inst          275                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data           64                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total          339                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data           78                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total           78                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst          275                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data          142                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::total           417                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst          274                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data          143                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.inst          275                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data          142                       # number of overall misses
 system.cpu.l2cache.overall_misses::total          417                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     19276500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data      5050250                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total     24326750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      5454250                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total      5454250                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     19276500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data     10504500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     29781000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     19276500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data     10504500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     29781000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst          275                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data           66                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total          341                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data           77                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total           77                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst          275                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data          143                       # number of demand (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     19600750                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data      4946500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total     24547250                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      5508750                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total      5508750                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     19600750                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data     10455250                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     30056000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     19600750                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data     10455250                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     30056000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst          276                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data           64                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total          340                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data           78                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total           78                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst          276                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data          142                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::total          418                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst          275                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data          143                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst          276                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data          142                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::total          418                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.996364                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.996377                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.data            1                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.997067                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.997059                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.996364                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.996377                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::total     0.997608                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.996364                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.996377                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.997608                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70352.189781                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76518.939394                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 71549.264706                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70834.415584                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70834.415584                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70352.189781                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73458.041958                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 71417.266187                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70352.189781                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73458.041958                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 71417.266187                       # average overall miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71275.454545                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77289.062500                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 72410.766962                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        70625                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total        70625                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71275.454545                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73628.521127                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 72076.738609                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71275.454545                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73628.521127                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 72076.738609                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -741,160 +741,160 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          274                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data           66                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total          340                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           77                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total           77                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst          274                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data          143                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          275                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data           64                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total          339                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           78                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total           78                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          275                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data          142                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::total          417                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst          274                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data          143                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          275                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data          142                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total          417                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     15837000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      4238250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     20075250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      4493750                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      4493750                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     15837000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      8732000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     24569000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     15837000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      8732000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     24569000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.996364                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     16144250                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      4156000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total     20300250                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      4539250                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      4539250                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     16144250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      8695250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     24839500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     16144250                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      8695250                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     24839500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.996377                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.997067                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.997059                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.996364                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.996377                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::total     0.997608                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.996364                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.996377                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.997608                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57799.270073                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64215.909091                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59044.852941                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58360.389610                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58360.389610                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57799.270073                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61062.937063                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58918.465228                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57799.270073                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61062.937063                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58918.465228                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58706.363636                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64937.500000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59882.743363                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58195.512821                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58195.512821                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58706.363636                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61234.154930                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59567.146283                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58706.363636                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61234.154930                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59567.146283                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.dcache.tags.replacements                 0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse            83.263820                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs                2308                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs               142                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             16.253521                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse            82.450988                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs                2400                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs               141                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             17.021277                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data    83.263820                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.020328                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.020328                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024          142                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           53                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1           89                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024     0.034668                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses              5178                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses             5178                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data         1450                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total            1450                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data          858                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total            858                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data          2308                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total             2308                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data         2308                       # number of overall hits
-system.cpu.dcache.overall_hits::total            2308                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data          133                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total           133                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data           77                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total           77                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data          210                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total            210                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data          210                       # number of overall misses
-system.cpu.dcache.overall_misses::total           210                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data      9474500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total      9474500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data      5711750                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total      5711750                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     15186250                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     15186250                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     15186250                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     15186250                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data         1583                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total         1583                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.tags.occ_blocks::cpu.data    82.450988                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.020130                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.020130                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024          141                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           54                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           87                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024     0.034424                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses              5369                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses             5369                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data         1543                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total            1543                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data          857                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total            857                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data          2400                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total             2400                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data         2400                       # number of overall hits
+system.cpu.dcache.overall_hits::total            2400                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data          136                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total           136                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data           78                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total           78                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data          214                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total            214                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data          214                       # number of overall misses
+system.cpu.dcache.overall_misses::total           214                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data      9815500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total      9815500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data      5769250                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total      5769250                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     15584750                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     15584750                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     15584750                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     15584750                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data         1679                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total         1679                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data          935                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total          935                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data         2518                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total         2518                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data         2518                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total         2518                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.084018                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.084018                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.082353                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.082353                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.083400                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.083400                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.083400                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.083400                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71236.842105                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 71236.842105                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74178.571429                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 74178.571429                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 72315.476190                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 72315.476190                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 72315.476190                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 72315.476190                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs          183                       # number of cycles access was blocked
+system.cpu.dcache.demand_accesses::cpu.data         2614                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total         2614                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data         2614                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total         2614                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.081001                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.081001                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.083422                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.083422                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.081867                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.081867                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.081867                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.081867                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72172.794118                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 72172.794118                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73964.743590                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 73964.743590                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 72825.934579                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 72825.934579                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 72825.934579                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 72825.934579                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs          201                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                 4                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 5                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    45.750000                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    40.200000                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data           67                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total           67                       # number of ReadReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data           67                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total           67                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data           67                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total           67                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data           66                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total           66                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data           77                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total           77                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data          143                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total          143                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data          143                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total          143                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      5115250                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      5115250                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      5531250                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      5531250                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data     10646500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total     10646500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data     10646500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total     10646500                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.041693                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.041693                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.082353                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.082353                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.056791                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.056791                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.056791                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.056791                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77503.787879                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77503.787879                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71834.415584                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71834.415584                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74451.048951                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 74451.048951                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74451.048951                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 74451.048951                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data           72                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total           72                       # number of ReadReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data           72                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total           72                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data           72                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total           72                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data           64                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total           64                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data           78                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total           78                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data          142                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total          142                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data          142                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total          142                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      5009500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      5009500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      5586750                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      5586750                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data     10596250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total     10596250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data     10596250                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total     10596250                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.038118                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.038118                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.083422                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.083422                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.054323                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.054323                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.054323                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.054323                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78273.437500                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78273.437500                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data        71625                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total        71625                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74621.478873                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 74621.478873                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74621.478873                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 74621.478873                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt
index c6213fa68..921de5f0b 100644
--- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt
+++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt
@@ -1,62 +1,62 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000025                       # Number of seconds simulated
-sim_ticks                                    24521000                       # Number of ticks simulated
-final_tick                                   24521000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.000023                       # Number of seconds simulated
+sim_ticks                                    23170000                       # Number of ticks simulated
+final_tick                                   23170000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  36221                       # Simulator instruction rate (inst/s)
-host_op_rate                                    36219                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               69681363                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 222160                       # Number of bytes of host memory used
-host_seconds                                     0.35                       # Real time elapsed on the host
-sim_insts                                       12745                       # Number of instructions simulated
-sim_ops                                         12745                       # Number of ops (including micro ops) simulated
+host_inst_rate                                  44420                       # Simulator instruction rate (inst/s)
+host_op_rate                                    44416                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               80747825                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 237048                       # Number of bytes of host memory used
+host_seconds                                     0.29                       # Real time elapsed on the host
+sim_insts                                       12744                       # Number of instructions simulated
+sim_ops                                         12744                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst             40128                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data             22400                       # Number of bytes read from this memory
-system.physmem.bytes_read::total                62528                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        40128                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           40128                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst                627                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data                350                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                   977                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst           1636474858                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            913502712                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              2549977570                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst      1636474858                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total         1636474858                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst          1636474858                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           913502712                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             2549977570                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                           977                       # Number of read requests accepted
+system.physmem.bytes_read::cpu.inst             40384                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data             22272                       # Number of bytes read from this memory
+system.physmem.bytes_read::total                62656                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        40384                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           40384                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst                631                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data                348                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                   979                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst           1742943461                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            961242987                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              2704186448                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst      1742943461                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total         1742943461                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst          1742943461                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           961242987                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             2704186448                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                           979                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
-system.physmem.readBursts                         977                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                         979                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                    62528                       # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM                    62656                       # Total number of bytes read from DRAM
 system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
 system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                     62528                       # Total read bytes from the system interface side
+system.physmem.bytesReadSys                     62656                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
 system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                  83                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                 153                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                  77                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                  59                       # Per bank write bursts
-system.physmem.perBankRdBursts::4                  87                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                  49                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                  32                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                  50                       # Per bank write bursts
+system.physmem.perBankRdBursts::0                  84                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                 151                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                  78                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                  58                       # Per bank write bursts
+system.physmem.perBankRdBursts::4                  88                       # Per bank write bursts
+system.physmem.perBankRdBursts::5                  48                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                  33                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                  51                       # Per bank write bursts
 system.physmem.perBankRdBursts::8                  42                       # Per bank write bursts
 system.physmem.perBankRdBursts::9                  39                       # Per bank write bursts
 system.physmem.perBankRdBursts::10                 31                       # Per bank write bursts
-system.physmem.perBankRdBursts::11                 33                       # Per bank write bursts
+system.physmem.perBankRdBursts::11                 34                       # Per bank write bursts
 system.physmem.perBankRdBursts::12                 15                       # Per bank write bursts
-system.physmem.perBankRdBursts::13                121                       # Per bank write bursts
+system.physmem.perBankRdBursts::13                120                       # Per bank write bursts
 system.physmem.perBankRdBursts::14                 70                       # Per bank write bursts
-system.physmem.perBankRdBursts::15                 36                       # Per bank write bursts
+system.physmem.perBankRdBursts::15                 37                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
 system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
 system.physmem.perBankWrBursts::2                   0                       # Per bank write bursts
@@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                        24370500                       # Total gap between requests
+system.physmem.totGap                        23015000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                     977                       # Read request sizes (log2)
+system.physmem.readPktSize::6                     979                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -90,12 +90,12 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                       339                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       353                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       183                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                        70                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                       351                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       324                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       193                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                        75                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                        24                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                         8                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                        12                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
@@ -186,92 +186,92 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples          216                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      282.666667                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     175.603788                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     291.640046                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127             78     36.11%     36.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255           56     25.93%     62.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383           23     10.65%     72.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511           15      6.94%     79.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639            8      3.70%     83.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767           13      6.02%     89.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895            4      1.85%     91.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023            6      2.78%     93.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151           13      6.02%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total            216                       # Bytes accessed per row activation
-system.physmem.totQLat                       13158000                       # Total ticks spent queuing
-system.physmem.totMemAccLat                  31476750                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                      4885000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       13467.76                       # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples          196                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      289.959184                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     186.164854                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     288.512504                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127             61     31.12%     31.12% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255           60     30.61%     61.73% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383           22     11.22%     72.96% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511            9      4.59%     77.55% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639           16      8.16%     85.71% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767            6      3.06%     88.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895            5      2.55%     91.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023            4      2.04%     93.37% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151           13      6.63%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total            196                       # Bytes accessed per row activation
+system.physmem.totQLat                       11386250                       # Total ticks spent queuing
+system.physmem.totMemAccLat                  29742500                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                      4895000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       11630.49                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  32217.76                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                        2549.98                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  30380.49                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                        2704.19                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                     2549.98                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                     2704.19                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                          19.92                       # Data bus utilization in percentage
-system.physmem.busUtilRead                      19.92                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                          21.13                       # Data bus utilization in percentage
+system.physmem.busUtilRead                      21.13                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         2.45                       # Average read queue length when enqueuing
+system.physmem.avgRdQLen                         2.40                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                        752                       # Number of row buffer hits during reads
+system.physmem.readRowHits                        767                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   76.97                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   78.35                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                        24944.22                       # Average gap between requests
-system.physmem.pageHitRate                      76.97                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE            22000                       # Time in different power states
-system.physmem.memoryStateTime::REF            780000                       # Time in different power states
+system.physmem.avgGap                        23508.68                       # Average gap between requests
+system.physmem.pageHitRate                      78.35                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE            25750                       # Time in different power states
+system.physmem.memoryStateTime::REF            520000                       # Time in different power states
 system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT          22830500                       # Time in different power states
+system.physmem.memoryStateTime::ACT          15300500                       # Time in different power states
 system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.membus.throughput                   2549977570                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq                 832                       # Transaction distribution
-system.membus.trans_dist::ReadResp                832                       # Transaction distribution
-system.membus.trans_dist::ReadExReq               145                       # Transaction distribution
-system.membus.trans_dist::ReadExResp              145                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port         1954                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                   1954                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        62528                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total               62528                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus                  62528                       # Total data (bytes)
+system.membus.throughput                   2704186448                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq                 833                       # Transaction distribution
+system.membus.trans_dist::ReadResp                833                       # Transaction distribution
+system.membus.trans_dist::ReadExReq               146                       # Transaction distribution
+system.membus.trans_dist::ReadExResp              146                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port         1958                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                   1958                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        62656                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total               62656                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus                  62656                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy             1224000                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               5.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            9060500                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization             36.9                       # Layer utilization (%)
+system.membus.reqLayer0.occupancy             1208500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               5.2                       # Layer utilization (%)
+system.membus.respLayer1.occupancy            9081250                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization             39.2                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.branchPred.lookups                    7716                       # Number of BP lookups
-system.cpu.branchPred.condPredicted              4270                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect              1557                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups                 5587                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                    1032                       # Number of BTB hits
+system.cpu.branchPred.lookups                    7166                       # Number of BP lookups
+system.cpu.branchPred.condPredicted              4000                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect              1467                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups                 5305                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                     908                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             18.471452                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                     986                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect                191                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             17.115928                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                     981                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect                 74                       # Number of incorrect RAS predictions.
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                         4952                       # DTB read hits
-system.cpu.dtb.read_misses                         97                       # DTB read misses
+system.cpu.dtb.read_hits                         4855                       # DTB read hits
+system.cpu.dtb.read_misses                         98                       # DTB read misses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                     5049                       # DTB read accesses
-system.cpu.dtb.write_hits                        2131                       # DTB write hits
-system.cpu.dtb.write_misses                        85                       # DTB write misses
+system.cpu.dtb.read_accesses                     4953                       # DTB read accesses
+system.cpu.dtb.write_hits                        2092                       # DTB write hits
+system.cpu.dtb.write_misses                        62                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses                    2216                       # DTB write accesses
-system.cpu.dtb.data_hits                         7083                       # DTB hits
-system.cpu.dtb.data_misses                        182                       # DTB misses
+system.cpu.dtb.write_accesses                    2154                       # DTB write accesses
+system.cpu.dtb.data_hits                         6947                       # DTB hits
+system.cpu.dtb.data_misses                        160                       # DTB misses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                     7265                       # DTB accesses
-system.cpu.itb.fetch_hits                        5823                       # ITB hits
-system.cpu.itb.fetch_misses                        63                       # ITB misses
+system.cpu.dtb.data_accesses                     7107                       # DTB accesses
+system.cpu.itb.fetch_hits                        5289                       # ITB hits
+system.cpu.itb.fetch_misses                        59                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                    5886                       # ITB accesses
+system.cpu.itb.fetch_accesses                    5348                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -286,324 +286,324 @@ system.cpu.itb.data_acv                             0                       # DT
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload0.num_syscalls                  17                       # Number of system calls
 system.cpu.workload1.num_syscalls                  17                       # Number of system calls
-system.cpu.numCycles                            49043                       # number of cpu cycles simulated
+system.cpu.numCycles                            46341                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles               1643                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                          42292                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                        7716                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches               2018                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                          7014                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                    1937                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles                  504                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.CacheLines                      5823                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                   939                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples              28717                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.472717                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.866777                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles               1308                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                          39806                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                        7166                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches               1889                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                         11048                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                    1548                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles                  233                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.CacheLines                      5289                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                   806                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples              28474                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.397977                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.796585                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                    21703     75.58%     75.58% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                      628      2.19%     77.76% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                      370      1.29%     79.05% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                      488      1.70%     80.75% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                      478      1.66%     82.41% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                      438      1.53%     83.94% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                      544      1.89%     85.83% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                      450      1.57%     87.40% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                     3618     12.60%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                    21786     76.51%     76.51% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                      553      1.94%     78.45% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                      412      1.45%     79.90% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                      526      1.85%     81.75% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                      512      1.80%     83.55% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                      421      1.48%     85.02% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                      497      1.75%     86.77% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                      420      1.48%     88.25% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                     3347     11.75%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total                28717                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.157331                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.862345                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                    40485                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles                  6963                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                      6425                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles                   184                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                   3240                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved                  753                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                   442                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts                  37312                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                   851                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                   3240                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                    41162                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                    2710                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles           1573                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                      5916                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles                  2696                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts                  34656                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                    78                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                    211                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                    347                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                   1943                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands               26052                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups                 42763                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups            42745                       # Number of integer rename lookups
+system.cpu.fetch.rateDist::total                28474                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.154636                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.858980                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                    37975                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles                 11845                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                      5079                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles                   648                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                   1147                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved                  634                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                   427                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts                  32375                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                   893                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                   1147                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                    38612                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                    4919                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles           1229                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                      5110                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles                  5677                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts                  30348                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                    40                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                    343                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                    655                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents                   4509                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands               22899                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups                 37890                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups            37872                       # Number of integer rename lookups
 system.cpu.rename.fp_rename_lookups                16                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps                  9140                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                    16912                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts                 53                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts             41                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                      1929                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads                 3424                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores                1551                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads                 2                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores                0                       # Number of conflicting stores.
-system.cpu.memDep1.insertedLoads                 3264                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep1.insertedStores                1487                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep1.conflictingLoads                43                       # Number of conflicting loads.
-system.cpu.memDep1.conflictingStores                4                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                      29904                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                  80                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                     23616                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued               291                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined           16167                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined        10244                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved             46                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples         28717                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.822370                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.487550                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                    13759                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts                 60                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts             48                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                      2110                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads                 2877                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores                1488                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads                42                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores               28                       # Number of conflicting stores.
+system.cpu.memDep1.insertedLoads                 2903                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep1.insertedStores                1354                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep1.conflictingLoads                 6                       # Number of conflicting loads.
+system.cpu.memDep1.conflictingStores                0                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                      27058                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                  53                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                     22518                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued                66                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined           13496                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined         7946                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved             19                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples         28474                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.790827                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.507053                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0               19680     68.53%     68.53% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1                2792      9.72%     78.25% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2                2104      7.33%     85.58% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3                1715      5.97%     91.55% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4                1290      4.49%     96.04% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5                 654      2.28%     98.32% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6                 354      1.23%     99.55% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7                 107      0.37%     99.93% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8                  21      0.07%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0               20065     70.47%     70.47% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1                2633      9.25%     79.71% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2                1896      6.66%     86.37% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3                1407      4.94%     91.31% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4                1291      4.53%     95.85% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                 643      2.26%     98.11% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6                 327      1.15%     99.26% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7                 165      0.58%     99.83% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8                  47      0.17%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total           28717                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total           28474                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                      15      7.43%      7.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%      7.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      7.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      7.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      7.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      7.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      7.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      7.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      7.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      7.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      7.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      7.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      7.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      7.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      7.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      7.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      7.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      7.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      7.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      7.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      7.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      7.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      7.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      7.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      7.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      7.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      7.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      7.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      7.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                    116     57.43%     64.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                    71     35.15%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                      21      6.95%      6.95% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      6.95% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      6.95% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      6.95% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      6.95% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      6.95% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      6.95% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      6.95% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      6.95% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      6.95% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      6.95% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      6.95% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      6.95% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      6.95% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      6.95% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      6.95% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      6.95% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      6.95% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      6.95% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      6.95% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      6.95% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      6.95% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      6.95% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      6.95% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      6.95% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      6.95% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      6.95% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      6.95% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      6.95% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                    199     65.89%     72.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                    82     27.15%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 2      0.02%      0.02% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu                  7921     66.06%     66.08% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                    1      0.01%     66.09% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     66.09% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   2      0.02%     66.11% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     66.11% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     66.11% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     66.11% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     66.11% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     66.11% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     66.11% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     66.11% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     66.11% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     66.11% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     66.11% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     66.11% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     66.11% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     66.11% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     66.11% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     66.11% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     66.11% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     66.11% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     66.11% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     66.11% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     66.11% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     66.11% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     66.11% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     66.11% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     66.11% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     66.11% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead                 2841     23.69%     89.80% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite                1223     10.20%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu                  7409     65.93%     65.95% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                    1      0.01%     65.95% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     65.95% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   2      0.02%     65.97% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     65.97% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     65.97% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     65.97% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     65.97% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     65.97% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     65.97% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     65.97% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     65.97% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     65.97% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     65.97% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     65.97% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     65.97% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     65.97% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     65.97% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     65.97% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     65.97% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     65.97% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     65.97% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     65.97% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     65.97% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     65.97% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     65.97% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     65.97% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     65.97% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     65.97% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead                 2656     23.63%     89.61% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite                1168     10.39%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total                  11990                       # Type of FU issued
+system.cpu.iq.FU_type_0::total                  11238                       # Type of FU issued
 system.cpu.iq.FU_type_1::No_OpClass                 2      0.02%      0.02% # Type of FU issued
-system.cpu.iq.FU_type_1::IntAlu                  7753     66.69%     66.70% # Type of FU issued
-system.cpu.iq.FU_type_1::IntMult                    1      0.01%     66.71% # Type of FU issued
-system.cpu.iq.FU_type_1::IntDiv                     0      0.00%     66.71% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatAdd                   2      0.02%     66.73% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatCmp                   0      0.00%     66.73% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatCvt                   0      0.00%     66.73% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatMult                  0      0.00%     66.73% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatDiv                   0      0.00%     66.73% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatSqrt                  0      0.00%     66.73% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdAdd                    0      0.00%     66.73% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdAddAcc                 0      0.00%     66.73% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdAlu                    0      0.00%     66.73% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdCmp                    0      0.00%     66.73% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdCvt                    0      0.00%     66.73% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdMisc                   0      0.00%     66.73% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdMult                   0      0.00%     66.73% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdMultAcc                0      0.00%     66.73% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdShift                  0      0.00%     66.73% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdShiftAcc               0      0.00%     66.73% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdSqrt                   0      0.00%     66.73% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatAdd               0      0.00%     66.73% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatAlu               0      0.00%     66.73% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatCmp               0      0.00%     66.73% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatCvt               0      0.00%     66.73% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatDiv               0      0.00%     66.73% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatMisc              0      0.00%     66.73% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatMult              0      0.00%     66.73% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatMultAcc            0      0.00%     66.73% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatSqrt              0      0.00%     66.73% # Type of FU issued
-system.cpu.iq.FU_type_1::MemRead                 2675     23.01%     89.74% # Type of FU issued
-system.cpu.iq.FU_type_1::MemWrite                1193     10.26%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_1::IntAlu                  7461     66.14%     66.16% # Type of FU issued
+system.cpu.iq.FU_type_1::IntMult                    1      0.01%     66.17% # Type of FU issued
+system.cpu.iq.FU_type_1::IntDiv                     0      0.00%     66.17% # Type of FU issued
+system.cpu.iq.FU_type_1::FloatAdd                   2      0.02%     66.19% # Type of FU issued
+system.cpu.iq.FU_type_1::FloatCmp                   0      0.00%     66.19% # Type of FU issued
+system.cpu.iq.FU_type_1::FloatCvt                   0      0.00%     66.19% # Type of FU issued
+system.cpu.iq.FU_type_1::FloatMult                  0      0.00%     66.19% # Type of FU issued
+system.cpu.iq.FU_type_1::FloatDiv                   0      0.00%     66.19% # Type of FU issued
+system.cpu.iq.FU_type_1::FloatSqrt                  0      0.00%     66.19% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdAdd                    0      0.00%     66.19% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdAddAcc                 0      0.00%     66.19% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdAlu                    0      0.00%     66.19% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdCmp                    0      0.00%     66.19% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdCvt                    0      0.00%     66.19% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdMisc                   0      0.00%     66.19% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdMult                   0      0.00%     66.19% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdMultAcc                0      0.00%     66.19% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdShift                  0      0.00%     66.19% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdShiftAcc               0      0.00%     66.19% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdSqrt                   0      0.00%     66.19% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatAdd               0      0.00%     66.19% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatAlu               0      0.00%     66.19% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatCmp               0      0.00%     66.19% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatCvt               0      0.00%     66.19% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatDiv               0      0.00%     66.19% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatMisc              0      0.00%     66.19% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatMult              0      0.00%     66.19% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatMultAcc            0      0.00%     66.19% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatSqrt              0      0.00%     66.19% # Type of FU issued
+system.cpu.iq.FU_type_1::MemRead                 2675     23.71%     89.90% # Type of FU issued
+system.cpu.iq.FU_type_1::MemWrite                1139     10.10%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_1::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_1::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_1::total                  11626                       # Type of FU issued
-system.cpu.iq.FU_type::total                    23616      0.00%      0.00% # Type of FU issued
-system.cpu.iq.rate                           0.481537                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt::0                      102                       # FU busy when requested
-system.cpu.iq.fu_busy_cnt::1                      100                       # FU busy when requested
-system.cpu.iq.fu_busy_cnt::total                  202                       # FU busy when requested
-system.cpu.iq.fu_busy_rate::0                0.004319                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.fu_busy_rate::1                0.004234                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.fu_busy_rate::total            0.008554                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads              76400                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes             46161                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses        20401                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_1::total                  11280                       # Type of FU issued
+system.cpu.iq.FU_type::total                    22518      0.00%      0.00% # Type of FU issued
+system.cpu.iq.rate                           0.485920                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt::0                      151                       # FU busy when requested
+system.cpu.iq.fu_busy_cnt::1                      151                       # FU busy when requested
+system.cpu.iq.fu_busy_cnt::total                  302                       # FU busy when requested
+system.cpu.iq.fu_busy_rate::0                0.006706                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.fu_busy_rate::1                0.006706                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.fu_busy_rate::total            0.013411                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads              73836                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes             40624                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses        19843                       # Number of integer instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_reads                  42                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_writes                 20                       # Number of floating instruction queue writes
 system.cpu.iq.fp_inst_queue_wakeup_accesses           20                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses                  23792                       # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses                  22794                       # Number of integer alu accesses
 system.cpu.iq.fp_alu_accesses                      22                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads               93                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads               70                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads         2241                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses            5                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation           15                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores          686                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads         1694                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses            2                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation           18                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores          623                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu.iew.lsq.thread0.rescheduledLoads            1                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked           422                       # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread1.forwLoads               68                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.cacheBlocked           321                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread1.forwLoads               81                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread1.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread1.squashedLoads         2081                       # Number of loads squashed
-system.cpu.iew.lsq.thread1.ignoredResponses            3                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread1.memOrderViolation           17                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread1.squashedStores          622                       # Number of stores squashed
+system.cpu.iew.lsq.thread1.squashedLoads         1720                       # Number of loads squashed
+system.cpu.iew.lsq.thread1.ignoredResponses            2                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread1.memOrderViolation           21                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread1.squashedStores          489                       # Number of stores squashed
 system.cpu.iew.lsq.thread1.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread1.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu.iew.lsq.thread1.rescheduledLoads            1                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread1.cacheBlocked           310                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread1.cacheBlocked           265                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                   3240                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                     336                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                   485                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts               30193                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts               379                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts                  6688                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts                 3038                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts                 80                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewSquashCycles                   1147                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                    2751                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                   416                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts               27257                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts               298                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts                  5780                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts                 2842                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts                 53                       # Number of dispatched non-speculative instructions
 system.cpu.iew.iewIQFullEvents                     25                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                   461                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents             32                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect            265                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect         1140                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts                 1405                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts                 21973                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts::0               2613                       # Number of load instructions executed
-system.cpu.iew.iewExecLoadInsts::1               2460                       # Number of load instructions executed
-system.cpu.iew.iewExecLoadInsts::total           5073                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts              1643                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewLSQFullEvents                   391                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents             39                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect            140                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect         1160                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts                 1300                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts                 21263                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts::0               2485                       # Number of load instructions executed
+system.cpu.iew.iewExecLoadInsts::1               2477                       # Number of load instructions executed
+system.cpu.iew.iewExecLoadInsts::total           4962                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts              1255                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp::0                          0                       # number of swp insts executed
 system.cpu.iew.exec_swp::1                          0                       # number of swp insts executed
 system.cpu.iew.exec_swp::total                      0                       # number of swp insts executed
-system.cpu.iew.exec_nop::0                        117                       # number of nop insts executed
-system.cpu.iew.exec_nop::1                         92                       # number of nop insts executed
-system.cpu.iew.exec_nop::total                    209                       # number of nop insts executed
-system.cpu.iew.exec_refs::0                      3756                       # number of memory reference insts executed
-system.cpu.iew.exec_refs::1                      3554                       # number of memory reference insts executed
-system.cpu.iew.exec_refs::total                  7310                       # number of memory reference insts executed
-system.cpu.iew.exec_branches::0                  1740                       # Number of branches executed
-system.cpu.iew.exec_branches::1                  1743                       # Number of branches executed
-system.cpu.iew.exec_branches::total              3483                       # Number of branches executed
-system.cpu.iew.exec_stores::0                    1143                       # Number of stores executed
-system.cpu.iew.exec_stores::1                    1094                       # Number of stores executed
-system.cpu.iew.exec_stores::total                2237                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.448035                       # Inst execution rate
-system.cpu.iew.wb_sent::0                       10504                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_sent::1                       10265                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_sent::total                   20769                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count::0                      10336                       # cumulative count of insts written-back
-system.cpu.iew.wb_count::1                      10085                       # cumulative count of insts written-back
-system.cpu.iew.wb_count::total                  20421                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers::0                   5409                       # num instructions producing a value
-system.cpu.iew.wb_producers::1                   5311                       # num instructions producing a value
-system.cpu.iew.wb_producers::total              10720                       # num instructions producing a value
-system.cpu.iew.wb_consumers::0                   7242                       # num instructions consuming a value
-system.cpu.iew.wb_consumers::1                   7116                       # num instructions consuming a value
-system.cpu.iew.wb_consumers::total              14358                       # num instructions consuming a value
+system.cpu.iew.exec_nop::0                         73                       # number of nop insts executed
+system.cpu.iew.exec_nop::1                         73                       # number of nop insts executed
+system.cpu.iew.exec_nop::total                    146                       # number of nop insts executed
+system.cpu.iew.exec_refs::0                      3579                       # number of memory reference insts executed
+system.cpu.iew.exec_refs::1                      3558                       # number of memory reference insts executed
+system.cpu.iew.exec_refs::total                  7137                       # number of memory reference insts executed
+system.cpu.iew.exec_branches::0                  1685                       # Number of branches executed
+system.cpu.iew.exec_branches::1                  1728                       # Number of branches executed
+system.cpu.iew.exec_branches::total              3413                       # Number of branches executed
+system.cpu.iew.exec_stores::0                    1094                       # Number of stores executed
+system.cpu.iew.exec_stores::1                    1081                       # Number of stores executed
+system.cpu.iew.exec_stores::total                2175                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.458838                       # Inst execution rate
+system.cpu.iew.wb_sent::0                       10071                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_sent::1                       10174                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_sent::total                   20245                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count::0                       9887                       # cumulative count of insts written-back
+system.cpu.iew.wb_count::1                       9976                       # cumulative count of insts written-back
+system.cpu.iew.wb_count::total                  19863                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers::0                   5227                       # num instructions producing a value
+system.cpu.iew.wb_producers::1                   5224                       # num instructions producing a value
+system.cpu.iew.wb_producers::total              10451                       # num instructions producing a value
+system.cpu.iew.wb_consumers::0                   6995                       # num instructions consuming a value
+system.cpu.iew.wb_consumers::1                   6944                       # num instructions consuming a value
+system.cpu.iew.wb_consumers::total              13939                       # num instructions consuming a value
 system.cpu.iew.wb_penalized::0                      0                       # number of instrctions required to write to 'other' IQ
 system.cpu.iew.wb_penalized::1                      0                       # number of instrctions required to write to 'other' IQ
 system.cpu.iew.wb_penalized::total                  0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate::0                    0.210754                       # insts written-back per cycle
-system.cpu.iew.wb_rate::1                    0.205636                       # insts written-back per cycle
-system.cpu.iew.wb_rate::total                0.416390                       # insts written-back per cycle
-system.cpu.iew.wb_fanout::0                  0.746893                       # average fanout of values written-back
-system.cpu.iew.wb_fanout::1                  0.746346                       # average fanout of values written-back
-system.cpu.iew.wb_fanout::total              0.746622                       # average fanout of values written-back
+system.cpu.iew.wb_rate::0                    0.213353                       # insts written-back per cycle
+system.cpu.iew.wb_rate::1                    0.215274                       # insts written-back per cycle
+system.cpu.iew.wb_rate::total                0.428627                       # insts written-back per cycle
+system.cpu.iew.wb_fanout::0                  0.747248                       # average fanout of values written-back
+system.cpu.iew.wb_fanout::1                  0.752304                       # average fanout of values written-back
+system.cpu.iew.wb_fanout::total              0.749767                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate::0                 0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu.iew.wb_penalized_rate::1                 0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu.iew.wb_penalized_rate::total             0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts           17385                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts           14469                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls              34                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts              1147                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples        28645                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.446116                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.297173                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts              1066                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples        28402                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.449898                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.318202                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0        23444     81.84%     81.84% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1         2590      9.04%     90.88% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2         1028      3.59%     94.47% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3          428      1.49%     95.97% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4          310      1.08%     97.05% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5          198      0.69%     97.74% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6          191      0.67%     98.41% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7          175      0.61%     99.02% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8          281      0.98%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0        23341     82.18%     82.18% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1         2401      8.45%     90.63% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2         1094      3.85%     94.49% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3          390      1.37%     95.86% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4          322      1.13%     96.99% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5          184      0.65%     97.64% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6          208      0.73%     98.37% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7          133      0.47%     98.84% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8          329      1.16%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total        28645                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total        28402                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts::0              6389                       # Number of instructions committed
-system.cpu.commit.committedInsts::1              6390                       # Number of instructions committed
-system.cpu.commit.committedInsts::total         12779                       # Number of instructions committed
+system.cpu.commit.committedInsts::1              6389                       # Number of instructions committed
+system.cpu.commit.committedInsts::total         12778                       # Number of instructions committed
 system.cpu.commit.committedOps::0                6389                       # Number of ops (including micro ops) committed
-system.cpu.commit.committedOps::1                6390                       # Number of ops (including micro ops) committed
-system.cpu.commit.committedOps::total           12779                       # Number of ops (including micro ops) committed
+system.cpu.commit.committedOps::1                6389                       # Number of ops (including micro ops) committed
+system.cpu.commit.committedOps::total           12778                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count::0                      0                       # Number of s/w prefetches committed
 system.cpu.commit.swp_count::1                      0                       # Number of s/w prefetches committed
 system.cpu.commit.swp_count::total                  0                       # Number of s/w prefetches committed
@@ -664,258 +664,258 @@ system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Cl
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total              6389                       # Class of committed instruction
 system.cpu.commit.op_class_1::No_OpClass           19      0.30%      0.30% # Class of committed instruction
-system.cpu.commit.op_class_1::IntAlu             4320     67.61%     67.90% # Class of committed instruction
-system.cpu.commit.op_class_1::IntMult               1      0.02%     67.92% # Class of committed instruction
-system.cpu.commit.op_class_1::IntDiv                0      0.00%     67.92% # Class of committed instruction
-system.cpu.commit.op_class_1::FloatAdd              2      0.03%     67.95% # Class of committed instruction
-system.cpu.commit.op_class_1::FloatCmp              0      0.00%     67.95% # Class of committed instruction
-system.cpu.commit.op_class_1::FloatCvt              0      0.00%     67.95% # Class of committed instruction
-system.cpu.commit.op_class_1::FloatMult             0      0.00%     67.95% # Class of committed instruction
-system.cpu.commit.op_class_1::FloatDiv              0      0.00%     67.95% # Class of committed instruction
-system.cpu.commit.op_class_1::FloatSqrt             0      0.00%     67.95% # Class of committed instruction
-system.cpu.commit.op_class_1::SimdAdd               0      0.00%     67.95% # Class of committed instruction
-system.cpu.commit.op_class_1::SimdAddAcc            0      0.00%     67.95% # Class of committed instruction
-system.cpu.commit.op_class_1::SimdAlu               0      0.00%     67.95% # Class of committed instruction
-system.cpu.commit.op_class_1::SimdCmp               0      0.00%     67.95% # Class of committed instruction
-system.cpu.commit.op_class_1::SimdCvt               0      0.00%     67.95% # Class of committed instruction
-system.cpu.commit.op_class_1::SimdMisc              0      0.00%     67.95% # Class of committed instruction
-system.cpu.commit.op_class_1::SimdMult              0      0.00%     67.95% # Class of committed instruction
-system.cpu.commit.op_class_1::SimdMultAcc            0      0.00%     67.95% # Class of committed instruction
-system.cpu.commit.op_class_1::SimdShift             0      0.00%     67.95% # Class of committed instruction
-system.cpu.commit.op_class_1::SimdShiftAcc            0      0.00%     67.95% # Class of committed instruction
-system.cpu.commit.op_class_1::SimdSqrt              0      0.00%     67.95% # Class of committed instruction
-system.cpu.commit.op_class_1::SimdFloatAdd            0      0.00%     67.95% # Class of committed instruction
-system.cpu.commit.op_class_1::SimdFloatAlu            0      0.00%     67.95% # Class of committed instruction
-system.cpu.commit.op_class_1::SimdFloatCmp            0      0.00%     67.95% # Class of committed instruction
-system.cpu.commit.op_class_1::SimdFloatCvt            0      0.00%     67.95% # Class of committed instruction
-system.cpu.commit.op_class_1::SimdFloatDiv            0      0.00%     67.95% # Class of committed instruction
-system.cpu.commit.op_class_1::SimdFloatMisc            0      0.00%     67.95% # Class of committed instruction
-system.cpu.commit.op_class_1::SimdFloatMult            0      0.00%     67.95% # Class of committed instruction
-system.cpu.commit.op_class_1::SimdFloatMultAcc            0      0.00%     67.95% # Class of committed instruction
-system.cpu.commit.op_class_1::SimdFloatSqrt            0      0.00%     67.95% # Class of committed instruction
-system.cpu.commit.op_class_1::MemRead            1183     18.51%     86.46% # Class of committed instruction
+system.cpu.commit.op_class_1::IntAlu             4319     67.60%     67.90% # Class of committed instruction
+system.cpu.commit.op_class_1::IntMult               1      0.02%     67.91% # Class of committed instruction
+system.cpu.commit.op_class_1::IntDiv                0      0.00%     67.91% # Class of committed instruction
+system.cpu.commit.op_class_1::FloatAdd              2      0.03%     67.94% # Class of committed instruction
+system.cpu.commit.op_class_1::FloatCmp              0      0.00%     67.94% # Class of committed instruction
+system.cpu.commit.op_class_1::FloatCvt              0      0.00%     67.94% # Class of committed instruction
+system.cpu.commit.op_class_1::FloatMult             0      0.00%     67.94% # Class of committed instruction
+system.cpu.commit.op_class_1::FloatDiv              0      0.00%     67.94% # Class of committed instruction
+system.cpu.commit.op_class_1::FloatSqrt             0      0.00%     67.94% # Class of committed instruction
+system.cpu.commit.op_class_1::SimdAdd               0      0.00%     67.94% # Class of committed instruction
+system.cpu.commit.op_class_1::SimdAddAcc            0      0.00%     67.94% # Class of committed instruction
+system.cpu.commit.op_class_1::SimdAlu               0      0.00%     67.94% # Class of committed instruction
+system.cpu.commit.op_class_1::SimdCmp               0      0.00%     67.94% # Class of committed instruction
+system.cpu.commit.op_class_1::SimdCvt               0      0.00%     67.94% # Class of committed instruction
+system.cpu.commit.op_class_1::SimdMisc              0      0.00%     67.94% # Class of committed instruction
+system.cpu.commit.op_class_1::SimdMult              0      0.00%     67.94% # Class of committed instruction
+system.cpu.commit.op_class_1::SimdMultAcc            0      0.00%     67.94% # Class of committed instruction
+system.cpu.commit.op_class_1::SimdShift             0      0.00%     67.94% # Class of committed instruction
+system.cpu.commit.op_class_1::SimdShiftAcc            0      0.00%     67.94% # Class of committed instruction
+system.cpu.commit.op_class_1::SimdSqrt              0      0.00%     67.94% # Class of committed instruction
+system.cpu.commit.op_class_1::SimdFloatAdd            0      0.00%     67.94% # Class of committed instruction
+system.cpu.commit.op_class_1::SimdFloatAlu            0      0.00%     67.94% # Class of committed instruction
+system.cpu.commit.op_class_1::SimdFloatCmp            0      0.00%     67.94% # Class of committed instruction
+system.cpu.commit.op_class_1::SimdFloatCvt            0      0.00%     67.94% # Class of committed instruction
+system.cpu.commit.op_class_1::SimdFloatDiv            0      0.00%     67.94% # Class of committed instruction
+system.cpu.commit.op_class_1::SimdFloatMisc            0      0.00%     67.94% # Class of committed instruction
+system.cpu.commit.op_class_1::SimdFloatMult            0      0.00%     67.94% # Class of committed instruction
+system.cpu.commit.op_class_1::SimdFloatMultAcc            0      0.00%     67.94% # Class of committed instruction
+system.cpu.commit.op_class_1::SimdFloatSqrt            0      0.00%     67.94% # Class of committed instruction
+system.cpu.commit.op_class_1::MemRead            1183     18.52%     86.46% # Class of committed instruction
 system.cpu.commit.op_class_1::MemWrite            865     13.54%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_1::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_1::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu.commit.op_class_1::total              6390                       # Class of committed instruction
-system.cpu.commit.op_class::total               12779      0.00%      0.00% # Class of committed instruction
-system.cpu.commit.bw_lim_events                   281                       # number cycles where commit BW limit reached
+system.cpu.commit.op_class_1::total              6389                       # Class of committed instruction
+system.cpu.commit.op_class::total               12778      0.00%      0.00% # Class of committed instruction
+system.cpu.commit.bw_lim_events                   329                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited::0                     0                       # number of insts not committed due to BW limits
 system.cpu.commit.bw_limited::1                     0                       # number of insts not committed due to BW limits
 system.cpu.commit.bw_limited::total                 0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                       140714                       # The number of ROB reads
-system.cpu.rob.rob_writes                       63601                       # The number of ROB writes
-system.cpu.timesIdled                             392                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           20326                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads                       131970                       # The number of ROB reads
+system.cpu.rob.rob_writes                       57167                       # The number of ROB writes
+system.cpu.timesIdled                             413                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           17867                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts::0                     6372                       # Number of Instructions Simulated
-system.cpu.committedInsts::1                     6373                       # Number of Instructions Simulated
-system.cpu.committedInsts::total                12745                       # Number of Instructions Simulated
+system.cpu.committedInsts::1                     6372                       # Number of Instructions Simulated
+system.cpu.committedInsts::total                12744                       # Number of Instructions Simulated
 system.cpu.committedOps::0                       6372                       # Number of Ops (including micro ops) Simulated
-system.cpu.committedOps::1                       6373                       # Number of Ops (including micro ops) Simulated
-system.cpu.committedOps::total                  12745                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi::0                            7.696642                       # CPI: Cycles Per Instruction
-system.cpu.cpi::1                            7.695434                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         3.848019                       # CPI: Total CPI of All Threads
-system.cpu.ipc::0                            0.129927                       # IPC: Instructions Per Cycle
-system.cpu.ipc::1                            0.129947                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.259874                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                    27593                       # number of integer regfile reads
-system.cpu.int_regfile_writes                   15533                       # number of integer regfile writes
+system.cpu.committedOps::1                       6372                       # Number of Ops (including micro ops) Simulated
+system.cpu.committedOps::total                  12744                       # Number of Ops (including micro ops) Simulated
+system.cpu.cpi::0                            7.272599                       # CPI: Cycles Per Instruction
+system.cpu.cpi::1                            7.272599                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         3.636299                       # CPI: Total CPI of All Threads
+system.cpu.ipc::0                            0.137502                       # IPC: Instructions Per Cycle
+system.cpu.ipc::1                            0.137502                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.275005                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                    26712                       # number of integer regfile reads
+system.cpu.int_regfile_writes                   15170                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                        16                       # number of floating regfile reads
 system.cpu.fp_regfile_writes                        4                       # number of floating regfile writes
 system.cpu.misc_regfile_reads                       2                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                      2                       # number of misc regfile writes
-system.cpu.toL2Bus.throughput              2555197586                       # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq            834                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp           834                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq          145                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp          145                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1258                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          700                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total              1958                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        40256                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side        22400                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total          62656                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus             62656                       # Total data (bytes)
+system.cpu.toL2Bus.throughput              2709710833                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq            835                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp           835                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq          146                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp          146                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1266                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          696                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total              1962                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        40512                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side        22272                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total          62784                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus             62784                       # Total data (bytes)
 system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy         489500                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          2.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy       1029000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          4.2                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy        559500                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          2.3                       # Layer utilization (%)
-system.cpu.icache.tags.replacements::0              8                       # number of replacements
+system.cpu.toL2Bus.reqLayer0.occupancy         490500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          2.1                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy       1042000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization          4.5                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy        550750                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization          2.4                       # Layer utilization (%)
+system.cpu.icache.tags.replacements::0              7                       # number of replacements
 system.cpu.icache.tags.replacements::1              0                       # number of replacements
-system.cpu.icache.tags.replacements::total            8                       # number of replacements
-system.cpu.icache.tags.tagsinuse           316.348744                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs                4766                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs               629                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs              7.577107                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements::total            7                       # number of replacements
+system.cpu.icache.tags.tagsinuse           316.397057                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs                4348                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs               633                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs              6.868878                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   316.348744                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.154467                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.154467                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024          621                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          253                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          368                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.303223                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses             12259                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses            12259                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst         4766                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total            4766                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst          4766                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total             4766                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst         4766                       # number of overall hits
-system.cpu.icache.overall_hits::total            4766                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst         1049                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total          1049                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst         1049                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total           1049                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst         1049                       # number of overall misses
-system.cpu.icache.overall_misses::total          1049                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     70831996                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     70831996                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     70831996                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     70831996                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     70831996                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     70831996                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst         5815                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total         5815                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst         5815                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total         5815                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst         5815                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total         5815                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.180396                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.180396                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.180396                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.180396                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.180396                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.180396                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67523.351764                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 67523.351764                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 67523.351764                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 67523.351764                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 67523.351764                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 67523.351764                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs         2854                       # number of cycles access was blocked
+system.cpu.icache.tags.occ_blocks::cpu.inst   316.397057                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.154491                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.154491                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          626                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          275                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          351                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.305664                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses             11201                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses            11201                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst         4348                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total            4348                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst          4348                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total             4348                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst         4348                       # number of overall hits
+system.cpu.icache.overall_hits::total            4348                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          936                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           936                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          936                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            936                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          936                       # number of overall misses
+system.cpu.icache.overall_misses::total           936                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     64563991                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     64563991                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     64563991                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     64563991                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     64563991                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     64563991                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst         5284                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total         5284                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst         5284                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total         5284                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst         5284                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total         5284                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.177139                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.177139                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.177139                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.177139                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.177139                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.177139                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68978.622863                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 68978.622863                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 68978.622863                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 68978.622863                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 68978.622863                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 68978.622863                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs         3153                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                69                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                83                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    41.362319                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    37.987952                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst          420                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total          420                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst          420                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total          420                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst          420                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total          420                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst          629                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total          629                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst          629                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total          629                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst          629                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total          629                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     47492998                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     47492998                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     47492998                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     47492998                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     47492998                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     47492998                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.108169                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.108169                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.108169                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.108169                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.108169                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.108169                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75505.561208                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75505.561208                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75505.561208                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 75505.561208                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75505.561208                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 75505.561208                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst          303                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total          303                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst          303                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total          303                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst          303                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total          303                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          633                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          633                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          633                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          633                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          633                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total          633                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     46517493                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     46517493                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     46517493                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     46517493                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     46517493                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     46517493                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.119796                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.119796                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.119796                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.119796                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.119796                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.119796                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73487.350711                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73487.350711                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73487.350711                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 73487.350711                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73487.350711                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 73487.350711                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements::0             0                       # number of replacements
 system.cpu.l2cache.tags.replacements::1             0                       # number of replacements
 system.cpu.l2cache.tags.replacements::total            0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse          437.665813                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse          435.916526                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs                  2                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs              832                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             0.002404                       # Average number of references to valid blocks.
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+system.cpu.l2cache.tags.avg_refs             0.002401                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   317.125803                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   120.540010                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.009678                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.003679                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.013357                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024          832                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          324                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          508                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.025391                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses             8809                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses            8809                       # Number of data accesses
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   317.007070                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data   118.909455                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.009674                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.003629                       # Average percentage of cache occupancy
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+system.cpu.l2cache.tags.occ_task_id_blocks::1024          833                       # Occupied blocks per task id
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+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.025421                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses             8827                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses            8827                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.inst            2                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total              2                       # number of ReadReq hits
 system.cpu.l2cache.demand_hits::cpu.inst            2                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::total               2                       # number of demand (read+write) hits
 system.cpu.l2cache.overall_hits::cpu.inst            2                       # number of overall hits
 system.cpu.l2cache.overall_hits::total              2                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst          627                       # number of ReadReq misses
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-system.cpu.l2cache.ReadReq_misses::total          832                       # number of ReadReq misses
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-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     46839000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data     17030000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total     63869000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data     11685500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total     11685500                       # number of ReadExReq miss cycles
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-system.cpu.l2cache.demand_miss_latency::cpu.data     28715500                       # number of demand (read+write) miss cycles
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-system.cpu.l2cache.overall_miss_latency::cpu.data     28715500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     75554500                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst          629                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data          205                       # number of ReadReq accesses(hits+misses)
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-system.cpu.l2cache.overall_accesses::cpu.data          350                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total          979                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.996820                       # miss rate for ReadReq accesses
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 system.cpu.l2cache.ReadReq_miss_rate::cpu.data            1                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.997602                       # miss rate for ReadReq accesses
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 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
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-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.996820                       # miss rate for demand accesses
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 system.cpu.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
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 system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.997957                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74703.349282                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 83073.170732                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 76765.625000                       # average ReadReq miss latency
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-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80589.655172                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74703.349282                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82044.285714                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 77333.162743                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74703.349282                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82044.285714                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 77333.162743                       # average overall miss latency
+system.cpu.l2cache.overall_miss_rate::total     0.997961                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72673.534073                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 80819.306931                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 74648.859544                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81145.547945                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81145.547945                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72673.534073                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80956.178161                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 75617.722165                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72673.534073                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80956.178161                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 75617.722165                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -924,164 +924,164 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          627                       # number of ReadReq MSHR misses
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-system.cpu.l2cache.demand_mshr_misses::cpu.data          350                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total          977                       # number of demand (read+write) MSHR misses
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-system.cpu.l2cache.overall_mshr_misses::cpu.data          350                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total          977                       # number of overall MSHR misses
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-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     14504000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     53543000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      9900000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      9900000                       # number of ReadExReq MSHR miss cycles
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-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     24404000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     63443000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.996820                       # mshr miss rate for ReadReq accesses
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 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.997602                       # mshr miss rate for ReadReq accesses
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 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.996820                       # mshr miss rate for demand accesses
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 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.997957                       # mshr miss rate for demand accesses
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 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
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-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70751.219512                       # average ReadReq mshr miss latency
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-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68275.862069                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68275.862069                       # average ReadExReq mshr miss latency
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-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69725.714286                       # average overall mshr miss latency
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-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62263.157895                       # average overall mshr miss latency
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+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60191.759113                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68556.930693                       # average ReadReq mshr miss latency
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+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68909.246575                       # average ReadExReq mshr miss latency
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+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68704.741379                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63217.824311                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.dcache.tags.replacements::0              0                       # number of replacements
 system.cpu.dcache.tags.replacements::1              0                       # number of replacements
 system.cpu.dcache.tags.replacements::total            0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           213.554041                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs                4807                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs               350                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             13.734286                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse           212.136486                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs                4920                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs               348                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             14.137931                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   213.554041                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.052137                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.052137                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024          350                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           93                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          257                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024     0.085449                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses             12052                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses            12052                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data         3785                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total            3785                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data         1022                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total           1022                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data          4807                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total             4807                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data         4807                       # number of overall hits
-system.cpu.dcache.overall_hits::total            4807                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data          336                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total           336                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data          708                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total          708                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data         1044                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total           1044                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data         1044                       # number of overall misses
-system.cpu.dcache.overall_misses::total          1044                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data     24770500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     24770500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data     51632692                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total     51632692                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     76403192                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     76403192                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     76403192                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     76403192                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data         4121                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total         4121                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.tags.occ_blocks::cpu.data   212.136486                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.051791                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.051791                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024          348                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           97                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          251                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024     0.084961                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses             12242                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses            12242                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data         3896                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total            3896                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data         1024                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total           1024                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data          4920                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total             4920                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data         4920                       # number of overall hits
+system.cpu.dcache.overall_hits::total            4920                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data          321                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total           321                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data          706                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total          706                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data         1027                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total           1027                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data         1027                       # number of overall misses
+system.cpu.dcache.overall_misses::total          1027                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data     23379250                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     23379250                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data     51507169                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total     51507169                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     74886419                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     74886419                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     74886419                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     74886419                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data         4217                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total         4217                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data         1730                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total         1730                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data         5851                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total         5851                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data         5851                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total         5851                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.081534                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.081534                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.409249                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.409249                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.178431                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.178431                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.178431                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.178431                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73721.726190                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 73721.726190                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 72927.531073                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 72927.531073                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 73183.134100                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 73183.134100                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 73183.134100                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 73183.134100                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs         4134                       # number of cycles access was blocked
+system.cpu.dcache.demand_accesses::cpu.data         5947                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total         5947                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data         5947                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total         5947                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.076120                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.076120                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.408092                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.408092                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.172692                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.172692                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.172692                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.172692                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72832.554517                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 72832.554517                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 72956.330028                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 72956.330028                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 72917.642648                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 72917.642648                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 72917.642648                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 72917.642648                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs         5674                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs               118                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs               139                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    35.033898                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    40.820144                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data          131                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total          131                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data          563                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total          563                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data          694                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total          694                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data          694                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total          694                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data          205                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total          205                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data          145                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total          145                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data          350                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total          350                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data          350                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total          350                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     17244500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total     17244500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data     11834247                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total     11834247                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data     29078747                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total     29078747                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data     29078747                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total     29078747                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.049745                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.049745                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.083815                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.083815                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.059819                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.059819                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.059819                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.059819                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 84119.512195                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 84119.512195                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 81615.496552                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 81615.496552                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 83082.134286                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 83082.134286                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 83082.134286                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 83082.134286                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data          119                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total          119                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data          560                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total          560                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data          679                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total          679                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data          679                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total          679                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data          202                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total          202                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data          146                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total          146                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data          348                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total          348                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data          348                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total          348                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     16537500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     16537500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data     11999490                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total     11999490                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data     28536990                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total     28536990                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data     28536990                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total     28536990                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.047901                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.047901                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.084393                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.084393                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.058517                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.058517                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.058517                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.058517                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 81868.811881                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 81868.811881                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 82188.287671                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 82188.287671                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 82002.844828                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 82002.844828                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 82002.844828                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 82002.844828                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt
index d600e3436..07c326366 100644
--- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt
@@ -1,62 +1,62 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000027                       # Number of seconds simulated
-sim_ticks                                    26706500                       # Number of ticks simulated
-final_tick                                   26706500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.000026                       # Number of seconds simulated
+sim_ticks                                    25944000                       # Number of ticks simulated
+final_tick                                   25944000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  22395                       # Simulator instruction rate (inst/s)
-host_op_rate                                    22394                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               41428038                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 228784                       # Number of bytes of host memory used
-host_seconds                                     0.64                       # Real time elapsed on the host
+host_inst_rate                                  14664                       # Simulator instruction rate (inst/s)
+host_op_rate                                    14664                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               26353337                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 237548                       # Number of bytes of host memory used
+host_seconds                                     0.98                       # Real time elapsed on the host
 sim_insts                                       14436                       # Number of instructions simulated
 sim_ops                                         14436                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst             21504                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data              9408                       # Number of bytes read from this memory
-system.physmem.bytes_read::total                30912                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        21504                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           21504                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst                336                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data                147                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                   483                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst            805197237                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            352273791                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              1157471028                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst       805197237                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          805197237                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           805197237                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           352273791                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             1157471028                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                           483                       # Number of read requests accepted
+system.physmem.bytes_read::cpu.inst             22016                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data              9472                       # Number of bytes read from this memory
+system.physmem.bytes_read::total                31488                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        22016                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           22016                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst                344                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data                148                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                   492                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst            848596978                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            365094049                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              1213691027                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst       848596978                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          848596978                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           848596978                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           365094049                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             1213691027                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                           492                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
-system.physmem.readBursts                         483                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                         492                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                    30912                       # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM                    31488                       # Total number of bytes read from DRAM
 system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
 system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                     30912                       # Total read bytes from the system interface side
+system.physmem.bytesReadSys                     31488                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
 system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                 102                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                  29                       # Per bank write bursts
+system.physmem.perBankRdBursts::0                 107                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                  28                       # Per bank write bursts
 system.physmem.perBankRdBursts::2                  51                       # Per bank write bursts
 system.physmem.perBankRdBursts::3                  24                       # Per bank write bursts
-system.physmem.perBankRdBursts::4                  19                       # Per bank write bursts
+system.physmem.perBankRdBursts::4                  20                       # Per bank write bursts
 system.physmem.perBankRdBursts::5                   0                       # Per bank write bursts
 system.physmem.perBankRdBursts::6                  32                       # Per bank write bursts
 system.physmem.perBankRdBursts::7                  35                       # Per bank write bursts
 system.physmem.perBankRdBursts::8                   4                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                   1                       # Per bank write bursts
+system.physmem.perBankRdBursts::9                   2                       # Per bank write bursts
 system.physmem.perBankRdBursts::10                  1                       # Per bank write bursts
 system.physmem.perBankRdBursts::11                  0                       # Per bank write bursts
 system.physmem.perBankRdBursts::12                 57                       # Per bank write bursts
 system.physmem.perBankRdBursts::13                 31                       # Per bank write bursts
 system.physmem.perBankRdBursts::14                 61                       # Per bank write bursts
-system.physmem.perBankRdBursts::15                 36                       # Per bank write bursts
+system.physmem.perBankRdBursts::15                 39                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
 system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
 system.physmem.perBankWrBursts::2                   0                       # Per bank write bursts
@@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                        26545500                       # Total gap between requests
+system.physmem.totGap                        25892500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                     483                       # Read request sizes (log2)
+system.physmem.readPktSize::6                     492                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -90,10 +90,10 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                       281                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       136                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        55                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                         7                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                       288                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       137                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        53                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                        10                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         3                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
@@ -186,299 +186,299 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples           70                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      404.114286                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     265.832819                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     348.256092                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127             12     17.14%     17.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255           22     31.43%     48.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383            9     12.86%     61.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511            3      4.29%     65.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639            4      5.71%     71.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767            3      4.29%     75.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895            5      7.14%     82.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023            2      2.86%     85.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151           10     14.29%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total             70                       # Bytes accessed per row activation
-system.physmem.totQLat                        2649500                       # Total ticks spent queuing
-system.physmem.totMemAccLat                  11705750                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                      2415000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        5485.51                       # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples           72                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      404.444444                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     264.526762                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     350.678412                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127             12     16.67%     16.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255           24     33.33%     50.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383            7      9.72%     59.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511            4      5.56%     65.28% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639            4      5.56%     70.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767            3      4.17%     75.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895            6      8.33%     83.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023            1      1.39%     84.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151           11     15.28%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total             72                       # Bytes accessed per row activation
+system.physmem.totQLat                        2648500                       # Total ticks spent queuing
+system.physmem.totMemAccLat                  11873500                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                      2460000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        5383.13                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  24235.51                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                        1157.47                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  24133.13                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                        1213.69                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                     1157.47                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                     1213.69                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           9.04                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       9.04                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                           9.48                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       9.48                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.52                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                        404                       # Number of row buffer hits during reads
+system.physmem.readRowHits                        411                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   83.64                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   83.54                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                        54959.63                       # Average gap between requests
-system.physmem.pageHitRate                      83.64                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE          1553250                       # Time in different power states
+system.physmem.avgGap                        52627.03                       # Average gap between requests
+system.physmem.pageHitRate                      83.54                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE           279250                       # Time in different power states
 system.physmem.memoryStateTime::REF            780000                       # Time in different power states
 system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT          21299250                       # Time in different power states
+system.physmem.memoryStateTime::ACT          22761250                       # Time in different power states
 system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.membus.throughput                   1157471028                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq                 400                       # Transaction distribution
-system.membus.trans_dist::ReadResp                400                       # Transaction distribution
+system.membus.throughput                   1211224175                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq                 409                       # Transaction distribution
+system.membus.trans_dist::ReadResp                408                       # Transaction distribution
 system.membus.trans_dist::ReadExReq                83                       # Transaction distribution
 system.membus.trans_dist::ReadExResp               83                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port          966                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                    966                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        30912                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total               30912                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus                  30912                       # Total data (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port          983                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                    983                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        31424                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total               31424                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus                  31424                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy              603000                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               2.3                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            4506000                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization             16.9                       # Layer utilization (%)
+system.membus.reqLayer0.occupancy              611000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               2.4                       # Layer utilization (%)
+system.membus.respLayer1.occupancy            4586750                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization             17.7                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.branchPred.lookups                    6723                       # Number of BP lookups
-system.cpu.branchPred.condPredicted              4462                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect              1076                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups                 5029                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                    2435                       # Number of BTB hits
+system.cpu.branchPred.lookups                    8578                       # Number of BP lookups
+system.cpu.branchPred.condPredicted              5479                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect              1058                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups                 6011                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                    3046                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             48.419169                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                     444                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect                168                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             50.673765                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                     607                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect                166                       # Number of incorrect RAS predictions.
 system.cpu.workload.num_syscalls                   18                       # Number of system calls
-system.cpu.numCycles                            53414                       # number of cpu cycles simulated
+system.cpu.numCycles                            51889                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles              12428                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                          31151                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                        6723                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches               2879                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                          9139                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                    3047                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles                   8960                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                    4                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles           921                       # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines                      5380                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                   470                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples              33327                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              0.934708                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.127415                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles              14152                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                          40300                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                        8578                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches               3653                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                         16187                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                    2310                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles                    5                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles          1000                       # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles           11                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                      6453                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                   567                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples              32510                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.239619                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.385650                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                    24188     72.58%     72.58% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                     4512     13.54%     86.12% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                      474      1.42%     87.54% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                      392      1.18%     88.71% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                      683      2.05%     90.76% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                      706      2.12%     92.88% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                      235      0.71%     93.59% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                      253      0.76%     94.35% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                     1884      5.65%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                    20972     64.51%     64.51% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                     5490     16.89%     81.40% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                      661      2.03%     83.43% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                      508      1.56%     84.99% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                      826      2.54%     87.53% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                      909      2.80%     90.33% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                      334      1.03%     91.36% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                      369      1.14%     92.49% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                     2441      7.51%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total                33327                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.125866                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.583199                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                    12851                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles                 10052                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                      8399                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles                   150                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                   1875                       # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts                  29050                       # Number of instructions handled by decode
-system.cpu.rename.SquashCycles                   1875                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                    13476                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                     163                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles           9186                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                      7977                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles                   650                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts                  26689                       # Number of instructions processed by rename
-system.cpu.rename.IQFullEvents                      2                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.SQFullEvents                    339                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands               23975                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups                 49504                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups            40958                       # Number of integer rename lookups
+system.cpu.fetch.rateDist::total                32510                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.165314                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.776658                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                    11331                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles                 12526                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                      6844                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles                   654                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                   1155                       # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts                  30561                       # Number of instructions handled by decode
+system.cpu.rename.SquashCycles                   1155                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                    11931                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                    1436                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles          10087                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                      6918                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles                   983                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts                  27740                       # Number of instructions processed by rename
+system.cpu.rename.IQFullEvents                      4                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.SQFullEvents                    585                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands               25096                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups                 51799                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups            42923                       # Number of integer rename lookups
 system.cpu.rename.CommittedMaps                 13819                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                    10156                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts                691                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts            694                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                      2667                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads                 3529                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores                2291                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads                 4                       # Number of conflicting loads.
+system.cpu.rename.UndoneMaps                    11277                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts                768                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts            786                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                      3783                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads                 3676                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores                2348                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads                 7                       # Number of conflicting loads.
 system.cpu.memDep0.conflictingStores                0                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                      22544                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                 655                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                     21140                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued                97                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined            7925                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined         5519                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved            180                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples         33327                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.634321                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.264898                       # Number of insts issued each cycle
+system.cpu.iq.iqInstsAdded                      23657                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                 726                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                     21921                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued                57                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined            9156                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined         6522                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved            251                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples         32510                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.674285                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.426342                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0               24173     72.53%     72.53% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1                3454     10.36%     82.90% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2                2274      6.82%     89.72% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3                1733      5.20%     94.92% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4                 917      2.75%     97.67% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5                 470      1.41%     99.08% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6                 241      0.72%     99.80% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7                  45      0.14%     99.94% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8                  20      0.06%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0               24124     74.20%     74.20% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1                3065      9.43%     83.63% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2                1561      4.80%     88.43% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3                1482      4.56%     92.99% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4                 945      2.91%     95.90% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                 726      2.23%     98.13% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6                 412      1.27%     99.40% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7                 154      0.47%     99.87% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8                  41      0.13%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total           33327                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total           32510                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                      46     31.29%     31.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%     31.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     31.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     31.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     31.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     31.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     31.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     31.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     31.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     31.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     31.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     31.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     31.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     31.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     31.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     31.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     31.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     31.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     31.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     31.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     31.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     31.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     31.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     31.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     31.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     31.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     31.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     31.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     31.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                     26     17.69%     48.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                    75     51.02%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                     112     49.56%     49.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%     49.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     49.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     49.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     49.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     49.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     49.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     49.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     49.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     49.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     49.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     49.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     49.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     49.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     49.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     49.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     49.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     49.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     49.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     49.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     49.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     49.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     49.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     49.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     49.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     49.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     49.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     49.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     49.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                     49     21.68%     71.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                    65     28.76%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu                 15664     74.10%     74.10% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                    0      0.00%     74.10% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     74.10% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     74.10% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     74.10% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     74.10% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     74.10% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     74.10% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     74.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     74.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     74.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     74.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     74.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     74.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     74.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     74.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     74.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     74.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     74.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     74.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     74.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     74.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     74.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     74.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     74.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     74.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     74.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     74.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     74.10% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead                 3362     15.90%     90.00% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite                2114     10.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu                 16292     74.32%     74.32% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                    0      0.00%     74.32% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     74.32% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     74.32% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     74.32% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     74.32% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     74.32% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     74.32% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     74.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     74.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     74.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     74.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     74.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     74.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     74.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     74.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     74.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     74.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     74.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     74.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     74.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     74.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     74.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     74.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     74.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     74.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     74.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     74.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     74.32% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead                 3506     15.99%     90.32% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite                2123      9.68%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total                  21140                       # Type of FU issued
-system.cpu.iq.rate                           0.395776                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                         147                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.006954                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads              75851                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes             31150                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses        19533                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total                  21921                       # Type of FU issued
+system.cpu.iq.rate                           0.422459                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                         226                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.010310                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads              76635                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes             33566                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses        20237                       # Number of integer instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_reads                   0                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_writes                  0                       # Number of floating instruction queue writes
 system.cpu.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses                  21287                       # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses                  22147                       # Number of integer alu accesses
 system.cpu.iq.fp_alu_accesses                       0                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads               29                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads               34                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads         1304                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses            3                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation           26                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores          843                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads         1451                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses            4                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation           27                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores          900                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu.iew.lsq.thread0.rescheduledLoads            1                       # Number of loads that were rescheduled
 system.cpu.iew.lsq.thread0.cacheBlocked            28                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                   1875                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                     148                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                     5                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts               24333                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts               388                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts                  3529                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts                 2291                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts                655                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewSquashCycles                   1155                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                    1122                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                   322                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts               25510                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts               207                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts                  3676                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts                 2348                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts                726                       # Number of dispatched non-speculative instructions
 system.cpu.iew.iewIQFullEvents                      3                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                     0                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents             26                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect            264                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect          947                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts                 1211                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts                 20085                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts                  3202                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts              1055                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewLSQFullEvents                   318                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents             27                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect            259                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect          934                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts                 1193                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts                 20909                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts                  3349                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts              1012                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                          1134                       # number of nop insts executed
-system.cpu.iew.exec_refs                         5227                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                     4240                       # Number of branches executed
-system.cpu.iew.exec_stores                       2025                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.376025                       # Inst execution rate
-system.cpu.iew.wb_sent                          19760                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                         19533                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                      9201                       # num instructions producing a value
-system.cpu.iew.wb_consumers                     11404                       # num instructions consuming a value
+system.cpu.iew.exec_nop                          1127                       # number of nop insts executed
+system.cpu.iew.exec_refs                         5373                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                     4425                       # Number of branches executed
+system.cpu.iew.exec_stores                       2024                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.402956                       # Inst execution rate
+system.cpu.iew.wb_sent                          20494                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                         20237                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                      9846                       # num instructions producing a value
+system.cpu.iew.wb_consumers                     12767                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.365691                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.806822                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       0.390006                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.771207                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts            9073                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts           10297                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls             475                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts              1076                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples        31452                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.482068                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.184176                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts              1058                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples        30446                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.497996                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.310786                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0        24226     77.03%     77.03% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1         3950     12.56%     89.58% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2         1330      4.23%     93.81% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3          819      2.60%     96.42% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4          349      1.11%     97.53% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5          271      0.86%     98.39% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6          322      1.02%     99.41% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7           68      0.22%     99.63% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8          117      0.37%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0        23926     78.59%     78.59% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1         3430     11.27%     89.85% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2         1163      3.82%     93.67% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3          612      2.01%     95.68% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4          344      1.13%     96.81% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5          240      0.79%     97.60% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6          396      1.30%     98.90% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7           62      0.20%     99.10% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8          273      0.90%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total        31452                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total        30446                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts                15162                       # Number of instructions committed
 system.cpu.commit.committedOps                  15162                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -524,209 +524,209 @@ system.cpu.commit.op_class_0::MemWrite           1448      9.55%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total             15162                       # Class of committed instruction
-system.cpu.commit.bw_lim_events                   117                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events                   273                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                        54747                       # The number of ROB reads
-system.cpu.rob.rob_writes                       50353                       # The number of ROB writes
-system.cpu.timesIdled                             213                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           20087                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads                        54809                       # The number of ROB reads
+system.cpu.rob.rob_writes                       52996                       # The number of ROB writes
+system.cpu.timesIdled                             204                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           19379                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                       14436                       # Number of Instructions Simulated
 system.cpu.committedOps                         14436                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               3.700055                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         3.700055                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.270266                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.270266                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                    32058                       # number of integer regfile reads
-system.cpu.int_regfile_writes                   17849                       # number of integer regfile writes
-system.cpu.misc_regfile_reads                    6922                       # number of misc regfile reads
+system.cpu.cpi                               3.594417                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         3.594417                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.278209                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.278209                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                    33400                       # number of integer regfile reads
+system.cpu.int_regfile_writes                   18599                       # number of integer regfile writes
+system.cpu.misc_regfile_reads                    7136                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                    569                       # number of misc regfile writes
-system.cpu.toL2Bus.throughput              1162263868                       # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq            402                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp           402                       # Transaction distribution
+system.cpu.toL2Bus.throughput              1216157879                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq            411                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp           410                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq           83                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp           83                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          676                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          294                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total               970                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        21632                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          692                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          295                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total               987                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        22144                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         9408                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total          31040                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus             31040                       # Total data (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total          31552                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus             31552                       # Total data (bytes)
 system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy         242500                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          0.9                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy        566000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          2.1                       # Layer utilization (%)
+system.cpu.toL2Bus.reqLayer0.occupancy         247000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          1.0                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy        579250                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization          2.2                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy        233000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.9                       # Layer utilization (%)
 system.cpu.icache.tags.replacements                 0                       # number of replacements
-system.cpu.icache.tags.tagsinuse           188.199882                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs                4872                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs               338                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             14.414201                       # Average number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse           192.510615                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs                5925                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs               346                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             17.124277                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   188.199882                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.091894                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.091894                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024          338                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           92                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          246                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.165039                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses             11098                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses            11098                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst         4872                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total            4872                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst          4872                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total             4872                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst         4872                       # number of overall hits
-system.cpu.icache.overall_hits::total            4872                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst          508                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total           508                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst          508                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total            508                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst          508                       # number of overall misses
-system.cpu.icache.overall_misses::total           508                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     31702750                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     31702750                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     31702750                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     31702750                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     31702750                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     31702750                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst         5380                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total         5380                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst         5380                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total         5380                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst         5380                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total         5380                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.094424                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.094424                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.094424                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.094424                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.094424                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.094424                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62406.988189                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 62406.988189                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 62406.988189                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 62406.988189                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 62406.988189                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 62406.988189                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.icache.tags.occ_blocks::cpu.inst   192.510615                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.093999                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.093999                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          346                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           93                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          253                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.168945                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses             13252                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses            13252                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst         5925                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total            5925                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst          5925                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total             5925                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst         5925                       # number of overall hits
+system.cpu.icache.overall_hits::total            5925                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          528                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           528                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          528                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            528                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          528                       # number of overall misses
+system.cpu.icache.overall_misses::total           528                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     32454000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     32454000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     32454000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     32454000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     32454000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     32454000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst         6453                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total         6453                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst         6453                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total         6453                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst         6453                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total         6453                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.081822                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.081822                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.081822                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.081822                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.081822                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.081822                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61465.909091                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 61465.909091                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 61465.909091                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 61465.909091                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 61465.909091                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 61465.909091                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs           42                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 1                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs           42                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst          170                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total          170                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst          170                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total          170                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst          170                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total          170                       # number of overall MSHR hits
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 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
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 system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
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 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -735,166 +735,166 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
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+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      5131500                       # number of ReadExReq MSHR miss cycles
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+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      9012000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     27368250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     18356250                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      9012000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     27368250                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.994220                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.995025                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.995134                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.994083                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.994220                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.995876                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.994083                       # mshr miss rate for overall accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.995951                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.994220                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.995876                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53571.428571                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60183.593750                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54629.375000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60966.867470                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60966.867470                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53571.428571                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60625.850340                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55718.426501                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53571.428571                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60625.850340                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55718.426501                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.995951                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53361.191860                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data        59700                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54368.581907                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61825.301205                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61825.301205                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53361.191860                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60891.891892                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55626.524390                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53361.191860                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60891.891892                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55626.524390                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.dcache.tags.replacements                 0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse            99.055513                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs                4001                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse            98.823641                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs                4124                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs               147                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             27.217687                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             28.054422                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data    99.055513                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.024183                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.024183                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data    98.823641                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.024127                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.024127                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          147                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           23                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          124                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           22                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          125                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024     0.035889                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses              9219                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses             9219                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data         2962                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total            2962                       # number of ReadReq hits
+system.cpu.dcache.tags.tag_accesses              9491                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses             9491                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data         3085                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total            3085                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data         1033                       # number of WriteReq hits
 system.cpu.dcache.WriteReq_hits::total           1033                       # number of WriteReq hits
 system.cpu.dcache.SwapReq_hits::cpu.data            6                       # number of SwapReq hits
 system.cpu.dcache.SwapReq_hits::total               6                       # number of SwapReq hits
-system.cpu.dcache.demand_hits::cpu.data          3995                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total             3995                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data         3995                       # number of overall hits
-system.cpu.dcache.overall_hits::total            3995                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data          126                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total           126                       # number of ReadReq misses
+system.cpu.dcache.demand_hits::cpu.data          4118                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total             4118                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data         4118                       # number of overall hits
+system.cpu.dcache.overall_hits::total            4118                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data          139                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total           139                       # number of ReadReq misses
 system.cpu.dcache.WriteReq_misses::cpu.data          409                       # number of WriteReq misses
 system.cpu.dcache.WriteReq_misses::total          409                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data          535                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total            535                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data          535                       # number of overall misses
-system.cpu.dcache.overall_misses::total           535                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data      7969250                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total      7969250                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data     25782224                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total     25782224                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     33751474                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     33751474                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     33751474                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     33751474                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data         3088                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total         3088                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data          548                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total            548                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data          548                       # number of overall misses
+system.cpu.dcache.overall_misses::total           548                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data      8661750                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total      8661750                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data     26093224                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total     26093224                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     34754974                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     34754974                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     34754974                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     34754974                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data         3224                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total         3224                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data         1442                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total         1442                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.SwapReq_accesses::cpu.data            6                       # number of SwapReq accesses(hits+misses)
 system.cpu.dcache.SwapReq_accesses::total            6                       # number of SwapReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data         4530                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total         4530                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data         4530                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total         4530                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.040803                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.040803                       # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data         4666                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total         4666                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data         4666                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total         4666                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.043114                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.043114                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.283634                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_miss_rate::total     0.283634                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.118102                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.118102                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.118102                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.118102                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63248.015873                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 63248.015873                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63037.222494                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 63037.222494                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 63086.867290                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 63086.867290                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 63086.867290                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 63086.867290                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs          851                       # number of cycles access was blocked
+system.cpu.dcache.demand_miss_rate::cpu.data     0.117445                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.117445                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.117445                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.117445                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62314.748201                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 62314.748201                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63797.613692                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 63797.613692                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 63421.485401                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 63421.485401                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 63421.485401                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 63421.485401                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs          955                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                28                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                30                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    30.392857                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    31.833333                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data           62                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total           62                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data           74                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total           74                       # number of ReadReq MSHR hits
 system.cpu.dcache.WriteReq_mshr_hits::cpu.data          326                       # number of WriteReq MSHR hits
 system.cpu.dcache.WriteReq_mshr_hits::total          326                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data          388                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total          388                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data          388                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total          388                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data           64                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total           64                       # number of ReadReq MSHR misses
+system.cpu.dcache.demand_mshr_hits::cpu.data          400                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total          400                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data          400                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total          400                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data           65                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total           65                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data           83                       # number of WriteReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::total           83                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data          147                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total          147                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data          147                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total          147                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      4701750                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      4701750                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      6159250                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      6159250                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data     10861000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total     10861000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data     10861000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total     10861000                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.020725                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.020725                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.demand_mshr_misses::cpu.data          148                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total          148                       # number of demand (read+write) MSHR misses
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+system.cpu.dcache.overall_mshr_misses::total          148                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      4732000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      4732000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      6235500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      6235500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data     10967500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total     10967500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data     10967500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total     10967500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.020161                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.020161                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.057559                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.057559                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.032450                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.032450                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.032450                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.032450                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 73464.843750                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 73464.843750                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74207.831325                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74207.831325                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73884.353741                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 73884.353741                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73884.353741                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 73884.353741                       # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.031719                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.031719                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.031719                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.031719                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data        72800                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total        72800                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75126.506024                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75126.506024                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74104.729730                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 74104.729730                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74104.729730                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 74104.729730                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
index f14e8cf51..3dcd489a6 100644
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
@@ -1,92 +1,92 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000111                       # Number of seconds simulated
-sim_ticks                                   110970500                       # Number of ticks simulated
-final_tick                                  110970500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.000106                       # Number of seconds simulated
+sim_ticks                                   105639000                       # Number of ticks simulated
+final_tick                                  105639000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 128659                       # Simulator instruction rate (inst/s)
-host_op_rate                                   128659                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               13699808                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 244656                       # Number of bytes of host memory used
-host_seconds                                     8.10                       # Real time elapsed on the host
-sim_insts                                     1042156                       # Number of instructions simulated
-sim_ops                                       1042156                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 115016                       # Simulator instruction rate (inst/s)
+host_op_rate                                   115016                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               12246117                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 253808                       # Number of bytes of host memory used
+host_seconds                                     8.63                       # Real time elapsed on the host
+sim_insts                                      992165                       # Number of instructions simulated
+sim_ops                                        992165                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu0.inst            22784                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst            23104                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.data            10752                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst              832                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst              768                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu1.data              832                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.inst             4608                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.inst             4928                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu2.data             1280                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu3.inst              256                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu3.data              832                       # Number of bytes read from this memory
-system.physmem.bytes_read::total                42176                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst        22784                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst          832                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu2.inst         4608                       # Number of instructions bytes read from this memory
+system.physmem.bytes_read::total                42752                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst        23104                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst          768                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu2.inst         4928                       # Number of instructions bytes read from this memory
 system.physmem.bytes_inst_read::cpu3.inst          256                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           28480                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu0.inst               356                       # Number of read requests responded to by this memory
+system.physmem.bytes_inst_read::total           29056                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu0.inst               361                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu0.data               168                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst                13                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst                12                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu1.data                13                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.inst                72                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.inst                77                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu2.data                20                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu3.inst                 4                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu3.data                13                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                   659                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu0.inst           205315827                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data            96890615                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst             7497488                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data             7497488                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst            41524549                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data            11534597                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.inst             2306919                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.data             7497488                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               380064972                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst      205315827                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst        7497488                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst       41524549                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu3.inst        2306919                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          256644784                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst          205315827                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data           96890615                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst            7497488                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data            7497488                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst           41524549                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data           11534597                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.inst            2306919                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.data            7497488                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              380064972                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                           660                       # Number of read requests accepted
+system.physmem.num_reads::total                   668                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu0.inst           218707106                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data           101780592                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst             7270042                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data             7875879                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.inst            46649438                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.data            12116737                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.inst             2423347                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.data             7875879                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               404699022                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst      218707106                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst        7270042                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu2.inst       46649438                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu3.inst        2423347                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          275049934                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst          218707106                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data          101780592                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst            7270042                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data            7875879                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.inst           46649438                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.data           12116737                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.inst            2423347                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.data            7875879                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              404699022                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                           669                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
-system.physmem.readBursts                         660                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                         669                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                    42240                       # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM                    42816                       # Total number of bytes read from DRAM
 system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
 system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                     42240                       # Total read bytes from the system interface side
+system.physmem.bytesReadSys                     42816                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
 system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs             77                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                 115                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                  39                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                  29                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs             78                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0                 114                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                  42                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                  30                       # Per bank write bursts
 system.physmem.perBankRdBursts::3                  60                       # Per bank write bursts
 system.physmem.perBankRdBursts::4                  65                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                  27                       # Per bank write bursts
+system.physmem.perBankRdBursts::5                  28                       # Per bank write bursts
 system.physmem.perBankRdBursts::6                  18                       # Per bank write bursts
 system.physmem.perBankRdBursts::7                  24                       # Per bank write bursts
 system.physmem.perBankRdBursts::8                   7                       # Per bank write bursts
 system.physmem.perBankRdBursts::9                  28                       # Per bank write bursts
 system.physmem.perBankRdBursts::10                 23                       # Per bank write bursts
-system.physmem.perBankRdBursts::11                 12                       # Per bank write bursts
-system.physmem.perBankRdBursts::12                 60                       # Per bank write bursts
+system.physmem.perBankRdBursts::11                 13                       # Per bank write bursts
+system.physmem.perBankRdBursts::12                 65                       # Per bank write bursts
 system.physmem.perBankRdBursts::13                 38                       # Per bank write bursts
 system.physmem.perBankRdBursts::14                 17                       # Per bank write bursts
-system.physmem.perBankRdBursts::15                 98                       # Per bank write bursts
+system.physmem.perBankRdBursts::15                 97                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
 system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
 system.physmem.perBankWrBursts::2                   0                       # Per bank write bursts
@@ -105,14 +105,14 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                       110942500                       # Total gap between requests
+system.physmem.totGap                       105611000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                     660                       # Read request sizes (log2)
+system.physmem.readPktSize::6                     669                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -121,11 +121,11 @@ system.physmem.writePktSize::4                      0                       # Wr
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
 system.physmem.rdQLenPdf::0                       400                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       194                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        54                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                        10                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                         2                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       193                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        59                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                        13                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                         3                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
@@ -216,305 +216,305 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples          148                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      274.594595                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     184.768834                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     255.591879                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127             47     31.76%     31.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255           39     26.35%     58.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383           23     15.54%     73.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511           12      8.11%     81.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639           10      6.76%     88.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767            5      3.38%     91.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895            5      3.38%     95.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023            1      0.68%     95.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151            6      4.05%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total            148                       # Bytes accessed per row activation
-system.physmem.totQLat                        5904750                       # Total ticks spent queuing
-system.physmem.totMemAccLat                  18279750                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                      3300000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        8946.59                       # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples          144                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      278.222222                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     188.203281                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     257.152031                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127             43     29.86%     29.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255           39     27.08%     56.94% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383           24     16.67%     73.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511           13      9.03%     82.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639            6      4.17%     86.81% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767            6      4.17%     90.97% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895            6      4.17%     95.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023            2      1.39%     96.53% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151            5      3.47%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total            144                       # Bytes accessed per row activation
+system.physmem.totQLat                        6117250                       # Total ticks spent queuing
+system.physmem.totMemAccLat                  18661000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                      3345000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        9143.87                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  27696.59                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         380.64                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  27893.87                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         405.30                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                      380.64                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                      405.30                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           2.97                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       2.97                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                           3.17                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       3.17                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.22                       # Average read queue length when enqueuing
+system.physmem.avgRdQLen                         1.23                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                        505                       # Number of row buffer hits during reads
+system.physmem.readRowHits                        514                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   76.52                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   76.83                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                       168094.70                       # Average gap between requests
-system.physmem.pageHitRate                      76.52                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE         48408000                       # Time in different power states
-system.physmem.memoryStateTime::REF           3640000                       # Time in different power states
+system.physmem.avgGap                       157863.98                       # Average gap between requests
+system.physmem.pageHitRate                      76.83                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE         46009250                       # Time in different power states
+system.physmem.memoryStateTime::REF           3380000                       # Time in different power states
 system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT          57233250                       # Time in different power states
+system.physmem.memoryStateTime::ACT          52645250                       # Time in different power states
 system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.membus.throughput                    380064972                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq                 529                       # Transaction distribution
-system.membus.trans_dist::ReadResp                528                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq              287                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp              77                       # Transaction distribution
-system.membus.trans_dist::ReadExReq               162                       # Transaction distribution
+system.membus.throughput                    404699022                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq                 538                       # Transaction distribution
+system.membus.trans_dist::ReadResp                537                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq              272                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp              78                       # Transaction distribution
+system.membus.trans_dist::ReadExReq               182                       # Transaction distribution
 system.membus.trans_dist::ReadExResp              131                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port         1714                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                   1714                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port        42176                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total               42176                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus                  42176                       # Total data (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port         1738                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                   1738                       # Packet count per connected master and slave (bytes)
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 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy              921500                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               0.8                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            6294424                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              5.7                       # Layer utilization (%)
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+system.membus.reqLayer0.utilization               0.9                       # Layer utilization (%)
+system.membus.respLayer1.occupancy            6389922                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization              6.0                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.l2c.tags.replacements                        0                       # number of replacements
-system.l2c.tags.tagsinuse                  416.952741                       # Cycle average of tags in use
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-system.l2c.tags.sampled_refs                      526                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                     2.741445                       # Average number of references to valid blocks.
+system.l2c.tags.tagsinuse                  424.251527                       # Cycle average of tags in use
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 system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
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 system.l2c.ReadExReq_accesses::cpu1.data           12                       # number of ReadExReq accesses(hits+misses)
 system.l2c.ReadExReq_accesses::cpu2.data           13                       # number of ReadExReq accesses(hits+misses)
 system.l2c.ReadExReq_accesses::cpu3.data           12                       # number of ReadExReq accesses(hits+misses)
 system.l2c.ReadExReq_accesses::total              131                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.inst             588                       # number of demand (read+write) accesses
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-system.l2c.demand_accesses::cpu2.inst             424                       # number of demand (read+write) accesses
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-system.l2c.demand_accesses::cpu3.inst             430                       # number of demand (read+write) accesses
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-system.l2c.demand_accesses::total                2116                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst            588                       # number of overall (read+write) accesses
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 system.l2c.overall_accesses::cpu0.data            173                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst            428                       # number of overall (read+write) accesses
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-system.l2c.overall_accesses::cpu2.inst            424                       # number of overall (read+write) accesses
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 system.l2c.overall_accesses::cpu2.data             25                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu3.inst            430                       # number of overall (read+write) accesses
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 system.l2c.overall_accesses::cpu3.data             24                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total               2116                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst      0.610544                       # miss rate for ReadReq accesses
+system.l2c.overall_accesses::total               2339                       # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu0.inst      0.592170                       # miss rate for ReadReq accesses
 system.l2c.ReadReq_miss_rate::cpu0.data      0.936709                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst      0.044393                       # miss rate for ReadReq accesses
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 system.l2c.ReadReq_miss_rate::cpu1.data      0.083333                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.inst      0.176887                       # miss rate for ReadReq accesses
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 system.l2c.ReadReq_miss_rate::cpu2.data      0.583333                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu3.inst      0.016279                       # miss rate for ReadReq accesses
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 system.l2c.ReadReq_miss_rate::cpu3.data      0.083333                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.273552                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.880000                       # miss rate for UpgradeReq accesses
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-system.l2c.demand_miss_rate::cpu0.inst       0.610544                       # miss rate for demand accesses
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 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -523,1201 +523,1204 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
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 system.l2c.ReadReq_mshr_hits::cpu3.inst             3                       # number of ReadReq MSHR hits
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-system.toL2Bus.throughput                  1688665006                       # Throughput (bytes/s)
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-system.toL2Bus.trans_dist::ReadResp              2535                       # Transaction distribution
+system.toL2Bus.throughput                  1921108681                       # Throughput (bytes/s)
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 system.toL2Bus.trans_dist::Writeback                1                       # Transaction distribution
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-system.toL2Bus.trans_dist::UpgradeResp            290                       # Transaction distribution
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-system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side          367                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side          860                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side          358                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total                  5414                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side        37568                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.trans_dist::UpgradeReq             275                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp            275                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq              413                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp             413                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side         1225                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side          584                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side          994                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side          361                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side          980                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side          365                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side          986                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side          371                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total                  5866                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side        39168                       # Cumulative packet size per connected master and slave (bytes)
 system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side        11136                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side        27392                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side        31808                       # Cumulative packet size per connected master and slave (bytes)
 system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side         1536                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side        27136                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side        31360                       # Cumulative packet size per connected master and slave (bytes)
 system.toL2Bus.tot_pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side         1600                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side        27520                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side        31552                       # Cumulative packet size per connected master and slave (bytes)
 system.toL2Bus.tot_pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side         1536                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size::total             135424                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.data_through_bus                135424                       # Total data (bytes)
-system.toL2Bus.snoop_data_through_bus           51968                       # Total snoop data (bytes)
-system.toL2Bus.reqLayer0.occupancy            1625975                       # Layer occupancy (ticks)
-system.toL2Bus.reqLayer0.utilization              1.5                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy           2708248                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer0.utilization             2.4                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy           1463019                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer1.utilization             1.3                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy           1929745                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer2.utilization             1.7                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy           1153498                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer3.utilization             1.0                       # Layer utilization (%)
-system.toL2Bus.respLayer4.occupancy           1921995                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer4.utilization             1.7                       # Layer utilization (%)
-system.toL2Bus.respLayer5.occupancy           1183735                       # Layer occupancy (ticks)
+system.toL2Bus.tot_pkt_size::total             149696                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.data_through_bus                149696                       # Total data (bytes)
+system.toL2Bus.snoop_data_through_bus           53248                       # Total snoop data (bytes)
+system.toL2Bus.reqLayer0.occupancy            1733986                       # Layer occupancy (ticks)
+system.toL2Bus.reqLayer0.utilization              1.6                       # Layer utilization (%)
+system.toL2Bus.respLayer0.occupancy           2820249                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.utilization             2.7                       # Layer utilization (%)
+system.toL2Bus.respLayer1.occupancy           1469763                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.utilization             1.4                       # Layer utilization (%)
+system.toL2Bus.respLayer2.occupancy           2240244                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.utilization             2.1                       # Layer utilization (%)
+system.toL2Bus.respLayer3.occupancy           1184253                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.utilization             1.1                       # Layer utilization (%)
+system.toL2Bus.respLayer4.occupancy           2220245                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer4.utilization             2.1                       # Layer utilization (%)
+system.toL2Bus.respLayer5.occupancy           1188993                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer5.utilization             1.1                       # Layer utilization (%)
-system.toL2Bus.respLayer6.occupancy           1936494                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer6.utilization             1.7                       # Layer utilization (%)
-system.toL2Bus.respLayer7.occupancy           1159999                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer7.utilization             1.0                       # Layer utilization (%)
-system.cpu0.branchPred.lookups                  83070                       # Number of BP lookups
-system.cpu0.branchPred.condPredicted            80870                       # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect             1218                       # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups               80399                       # Number of BTB lookups
-system.cpu0.branchPred.BTBHits                  78350                       # Number of BTB hits
+system.toL2Bus.respLayer6.occupancy           2220246                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer6.utilization             2.1                       # Layer utilization (%)
+system.toL2Bus.respLayer7.occupancy           1196995                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer7.utilization             1.1                       # Layer utilization (%)
+system.cpu0.branchPred.lookups                  81365                       # Number of BP lookups
+system.cpu0.branchPred.condPredicted            78481                       # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect             1187                       # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups               78090                       # Number of BTB lookups
+system.cpu0.branchPred.BTBHits                  75342                       # Number of BTB hits
 system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct            97.451461                       # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS                    512                       # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect               132                       # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct            96.480983                       # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS                    733                       # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect               128                       # Number of incorrect RAS predictions.
 system.cpu0.workload.num_syscalls                  89                       # Number of system calls
-system.cpu0.numCycles                          221942                       # number of cpu cycles simulated
+system.cpu0.numCycles                          211279                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles             17233                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts                        493008                       # Number of instructions fetch has processed
-system.cpu0.fetch.Branches                      83070                       # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches             78862                       # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles                       161826                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles                   3812                       # Number of cycles fetch has spent squashing
-system.cpu0.fetch.BlockedCycles                 13755                       # Number of cycles fetch has spent blocked
-system.cpu0.fetch.MiscStallCycles                   5                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingTrapStallCycles         1482                       # Number of stall cycles due to pending traps
-system.cpu0.fetch.CacheLines                     5835                       # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes                  491                       # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.rateDist::samples            196747                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean             2.505797                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev            2.214858                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.icacheStallCycles             20058                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts                        480743                       # Number of instructions fetch has processed
+system.cpu0.fetch.Branches                      81365                       # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches             76075                       # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles                       164045                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles                   2674                       # Number of cycles fetch has spent squashing
+system.cpu0.fetch.MiscStallCycles                   3                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingTrapStallCycles         1880                       # Number of stall cycles due to pending traps
+system.cpu0.fetch.CacheLines                     7123                       # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes                  658                       # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.rateDist::samples            187323                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean             2.566385                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev            2.225399                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0                   34921     17.75%     17.75% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1                   80152     40.74%     58.49% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2                     578      0.29%     58.78% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3                     974      0.50%     59.28% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4                     477      0.24%     59.52% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5                   76267     38.76%     98.28% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6                     570      0.29%     98.57% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::7                     349      0.18%     98.75% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::8                    2459      1.25%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0                   30153     16.10%     16.10% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1                   77599     41.43%     57.52% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2                     823      0.44%     57.96% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3                    1078      0.58%     58.54% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4                     624      0.33%     58.87% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5                   72927     38.93%     97.80% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6                     691      0.37%     98.17% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::7                     437      0.23%     98.40% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::8                    2991      1.60%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total              196747                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate                 0.374287                       # Number of branch fetches per cycle
-system.cpu0.fetch.rate                       2.221337                       # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles                   17711                       # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles                15452                       # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles                   160920                       # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles                  218                       # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles                  2446                       # Number of cycles decode is squashing
-system.cpu0.decode.DecodedInsts                490118                       # Number of instructions handled by decode
-system.cpu0.rename.SquashCycles                  2446                       # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles                   18323                       # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles                    441                       # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles         14289                       # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles                   160585                       # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles                  663                       # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts                487271                       # Number of instructions processed by rename
-system.cpu0.rename.SQFullEvents                   294                       # Number of times rename has blocked due to SQ full
-system.cpu0.rename.RenamedOperands             333181                       # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups               971741                       # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups          733988                       # Number of integer rename lookups
-system.cpu0.rename.CommittedMaps               320207                       # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps                   12974                       # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts               868                       # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts           890                       # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts                     3239                       # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads              155891                       # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores              78785                       # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads            76033                       # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores           75852                       # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded                    407472                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded                912                       # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued                   404753                       # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued              136                       # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined          10781                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined         9726                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved           353                       # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples       196747                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean        2.057226                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev       1.098946                       # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total              187323                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate                 0.385107                       # Number of branch fetches per cycle
+system.cpu0.fetch.rate                       2.275394                       # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles                   15731                       # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles                17849                       # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles                   151731                       # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles                  675                       # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles                  1337                       # Number of cycles decode is squashing
+system.cpu0.decode.DecodedInsts                468882                       # Number of instructions handled by decode
+system.cpu0.rename.SquashCycles                  1337                       # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles                   16349                       # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles                   2025                       # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles         14605                       # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles                   151742                       # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles                 1265                       # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts                465427                       # Number of instructions processed by rename
+system.cpu0.rename.IQFullEvents                    17                       # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LQFullEvents                    18                       # Number of times rename has blocked due to LQ full
+system.cpu0.rename.SQFullEvents                   756                       # Number of times rename has blocked due to SQ full
+system.cpu0.rename.RenamedOperands             318792                       # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups               928161                       # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups          701504                       # Number of integer rename lookups
+system.cpu0.rename.CommittedMaps               304835                       # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps                   13957                       # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts               896                       # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts           905                       # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts                     4588                       # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads              148468                       # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores              75131                       # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads            72391                       # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores           72142                       # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded                    389496                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded                964                       # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued                   386182                       # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued               23                       # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined          12213                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined        11099                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved           405                       # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples       187323                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean        2.061583                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev       1.125394                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0              34174     17.37%     17.37% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1               4673      2.38%     19.74% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2              77781     39.53%     59.28% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3              77469     39.37%     98.65% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4               1629      0.83%     99.48% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5                654      0.33%     99.81% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::6                260      0.13%     99.95% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::7                 91      0.05%     99.99% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::8                 16      0.01%    100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0              33109     17.67%     17.67% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1               4301      2.30%     19.97% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2              73576     39.28%     59.25% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3              73130     39.04%     98.29% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4               1662      0.89%     99.18% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5                894      0.48%     99.65% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::6                408      0.22%     99.87% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::7                171      0.09%     99.96% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::8                 72      0.04%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total         196747                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total         187323                       # Number of insts issued each cycle
 system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu                     60     26.43%     26.43% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult                     0      0.00%     26.43% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv                      0      0.00%     26.43% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     26.43% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     26.43% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     26.43% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult                   0      0.00%     26.43% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     26.43% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     26.43% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     26.43% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     26.43% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     26.43% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     26.43% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     26.43% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     26.43% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult                    0      0.00%     26.43% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     26.43% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift                   0      0.00%     26.43% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     26.43% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     26.43% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     26.43% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     26.43% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     26.43% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     26.43% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     26.43% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     26.43% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     26.43% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     26.43% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     26.43% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead                    55     24.23%     50.66% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite                  112     49.34%    100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu                     97     34.15%     34.15% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult                     0      0.00%     34.15% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv                      0      0.00%     34.15% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     34.15% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     34.15% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     34.15% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult                   0      0.00%     34.15% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     34.15% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     34.15% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     34.15% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     34.15% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     34.15% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     34.15% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     34.15% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     34.15% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult                    0      0.00%     34.15% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     34.15% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift                   0      0.00%     34.15% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     34.15% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     34.15% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     34.15% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     34.15% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     34.15% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     34.15% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     34.15% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     34.15% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     34.15% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     34.15% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     34.15% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead                    84     29.58%     63.73% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite                  103     36.27%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
 system.cpu0.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu               171127     42.28%     42.28% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult                   0      0.00%     42.28% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     42.28% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     42.28% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     42.28% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     42.28% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     42.28% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     42.28% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     42.28% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     42.28% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     42.28% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     42.28% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     42.28% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     42.28% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     42.28% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     42.28% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     42.28% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     42.28% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     42.28% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     42.28% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     42.28% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     42.28% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     42.28% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     42.28% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     42.28% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc             0      0.00%     42.28% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     42.28% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     42.28% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     42.28% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead              155427     38.40%     80.68% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite              78199     19.32%    100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu               163788     42.41%     42.41% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult                   0      0.00%     42.41% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     42.41% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     42.41% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     42.41% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     42.41% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     42.41% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     42.41% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     42.41% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     42.41% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     42.41% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     42.41% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     42.41% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     42.41% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     42.41% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     42.41% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     42.41% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     42.41% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     42.41% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     42.41% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     42.41% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     42.41% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     42.41% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     42.41% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     42.41% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc             0      0.00%     42.41% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     42.41% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     42.41% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     42.41% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead              147930     38.31%     80.72% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite              74464     19.28%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total                404753                       # Type of FU issued
-system.cpu0.iq.rate                          1.823688                       # Inst issue rate
-system.cpu0.iq.fu_busy_cnt                        227                       # FU busy when requested
-system.cpu0.iq.fu_busy_rate                  0.000561                       # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads           1006616                       # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes           419219                       # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses       402934                       # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.FU_type_0::total                386182                       # Type of FU issued
+system.cpu0.iq.rate                          1.827830                       # Inst issue rate
+system.cpu0.iq.fu_busy_cnt                        284                       # FU busy when requested
+system.cpu0.iq.fu_busy_rate                  0.000735                       # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads            959994                       # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes           402726                       # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses       384333                       # Number of integer instruction queue wakeup accesses
 system.cpu0.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
 system.cpu0.iq.fp_inst_queue_writes                 0                       # Number of floating instruction queue writes
 system.cpu0.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses                404980                       # Number of integer alu accesses
+system.cpu0.iq.int_alu_accesses                386466                       # Number of integer alu accesses
 system.cpu0.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads           75562                       # Number of loads that had data forwarded from stores
+system.cpu0.iew.lsq.thread0.forwLoads           71762                       # Number of loads that had data forwarded from stores
 system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads         2198                       # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses            4                       # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.squashedLoads         2461                       # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses            3                       # Number of memory responses ignored because the instruction is squashed
 system.cpu0.iew.lsq.thread0.memOrderViolation           54                       # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores         1432                       # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedStores         1621                       # Number of stores squashed
 system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu0.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked           18                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.cacheBlocked           12                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles                  2446                       # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles                    397                       # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles                   44                       # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts             484968                       # Number of instructions dispatched to IQ
-system.cpu0.iew.iewDispSquashedInsts              314                       # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts               155891                       # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts               78785                       # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts               800                       # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents                    40                       # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents                    9                       # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.iewSquashCycles                  1337                       # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles                   1986                       # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles                   48                       # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts             463277                       # Number of instructions dispatched to IQ
+system.cpu0.iew.iewDispSquashedInsts              160                       # Number of squashed instructions skipped by dispatch
+system.cpu0.iew.iewDispLoadInsts               148468                       # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts               75131                       # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts               843                       # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents                    43                       # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents                   10                       # Number of times the LSQ has become full, causing a stall
 system.cpu0.iew.memOrderViolationEvents            54                       # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect           343                       # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect         1106                       # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts                1449                       # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts               403684                       # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts               155095                       # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts             1069                       # Number of squashed instructions skipped in execute
+system.cpu0.iew.predictedTakenIncorrect           323                       # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect         1099                       # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts                1422                       # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts               385174                       # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts               147630                       # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts             1008                       # Number of squashed instructions skipped in execute
 system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu0.iew.exec_nop                        76584                       # number of nop insts executed
-system.cpu0.iew.exec_refs                      233191                       # number of memory reference insts executed
-system.cpu0.iew.exec_branches                   80195                       # Number of branches executed
-system.cpu0.iew.exec_stores                     78096                       # Number of stores executed
-system.cpu0.iew.exec_rate                    1.818872                       # Inst execution rate
-system.cpu0.iew.wb_sent                        403263                       # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count                       402934                       # cumulative count of insts written-back
-system.cpu0.iew.wb_producers                   238926                       # num instructions producing a value
-system.cpu0.iew.wb_consumers                   241439                       # num instructions consuming a value
+system.cpu0.iew.exec_nop                        72817                       # number of nop insts executed
+system.cpu0.iew.exec_refs                      221956                       # number of memory reference insts executed
+system.cpu0.iew.exec_branches                   76403                       # Number of branches executed
+system.cpu0.iew.exec_stores                     74326                       # Number of stores executed
+system.cpu0.iew.exec_rate                    1.823059                       # Inst execution rate
+system.cpu0.iew.wb_sent                        384701                       # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count                       384333                       # cumulative count of insts written-back
+system.cpu0.iew.wb_producers                   227933                       # num instructions producing a value
+system.cpu0.iew.wb_consumers                   231165                       # num instructions consuming a value
 system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu0.iew.wb_rate                      1.815492                       # insts written-back per cycle
-system.cpu0.iew.wb_fanout                    0.989592                       # average fanout of values written-back
+system.cpu0.iew.wb_rate                      1.819078                       # insts written-back per cycle
+system.cpu0.iew.wb_fanout                    0.986019                       # average fanout of values written-back
 system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.commit.commitSquashedInsts          12279                       # The number of squashed insts skipped by commit
+system.cpu0.commit.commitSquashedInsts          13622                       # The number of squashed insts skipped by commit
 system.cpu0.commit.commitNonSpecStalls            559                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts             1218                       # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples       194301                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean     2.432628                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev     2.139595                       # Number of insts commited each cycle
+system.cpu0.commit.branchMispredicts             1187                       # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples       184699                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean     2.434252                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev     2.147591                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0        34596     17.81%     17.81% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1        79813     41.08%     58.88% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2         2261      1.16%     60.05% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3          671      0.35%     60.39% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4          526      0.27%     60.66% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5        75370     38.79%     99.45% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6          456      0.23%     99.69% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7          240      0.12%     99.81% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8          368      0.19%    100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0        33306     18.03%     18.03% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1        75499     40.88%     58.91% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2         2011      1.09%     60.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3          643      0.35%     60.35% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4          527      0.29%     60.63% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5        71457     38.69%     99.32% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6          519      0.28%     99.60% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7          249      0.13%     99.74% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8          488      0.26%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total       194301                       # Number of insts commited each cycle
-system.cpu0.commit.committedInsts              472662                       # Number of instructions committed
-system.cpu0.commit.committedOps                472662                       # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total       184699                       # Number of insts commited each cycle
+system.cpu0.commit.committedInsts              449604                       # Number of instructions committed
+system.cpu0.commit.committedOps                449604                       # Number of ops (including micro ops) committed
 system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu0.commit.refs                        231046                       # Number of memory references committed
-system.cpu0.commit.loads                       153693                       # Number of loads committed
+system.cpu0.commit.refs                        219517                       # Number of memory references committed
+system.cpu0.commit.loads                       146007                       # Number of loads committed
 system.cpu0.commit.membars                         84                       # Number of memory barriers committed
-system.cpu0.commit.branches                     79240                       # Number of branches committed
+system.cpu0.commit.branches                     75397                       # Number of branches committed
 system.cpu0.commit.fp_insts                         0                       # Number of committed floating point instructions.
-system.cpu0.commit.int_insts                   318538                       # Number of committed integer instructions.
+system.cpu0.commit.int_insts                   303166                       # Number of committed integer instructions.
 system.cpu0.commit.function_calls                 223                       # Number of function calls committed.
-system.cpu0.commit.op_class_0::No_OpClass        75972     16.07%     16.07% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntAlu          165560     35.03%     51.10% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntMult              0      0.00%     51.10% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntDiv               0      0.00%     51.10% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     51.10% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     51.10% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     51.10% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatMult            0      0.00%     51.10% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     51.10% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     51.10% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     51.10% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     51.10% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     51.10% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     51.10% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     51.10% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     51.10% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMult             0      0.00%     51.10% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     51.10% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShift            0      0.00%     51.10% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     51.10% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     51.10% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     51.10% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     51.10% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     51.10% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     51.10% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     51.10% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMisc            0      0.00%     51.10% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     51.10% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     51.10% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     51.10% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemRead         153777     32.53%     83.63% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemWrite         77353     16.37%    100.00% # Class of committed instruction
+system.cpu0.commit.op_class_0::No_OpClass        72129     16.04%     16.04% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntAlu          157874     35.11%     51.16% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntMult              0      0.00%     51.16% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntDiv               0      0.00%     51.16% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     51.16% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     51.16% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     51.16% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatMult            0      0.00%     51.16% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     51.16% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     51.16% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     51.16% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     51.16% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     51.16% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     51.16% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     51.16% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     51.16% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMult             0      0.00%     51.16% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     51.16% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShift            0      0.00%     51.16% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     51.16% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     51.16% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     51.16% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     51.16% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     51.16% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     51.16% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     51.16% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMisc            0      0.00%     51.16% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     51.16% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     51.16% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     51.16% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemRead         146091     32.49%     83.65% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemWrite         73510     16.35%    100.00% # Class of committed instruction
 system.cpu0.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::total           472662                       # Class of committed instruction
-system.cpu0.commit.bw_lim_events                  368                       # number cycles where commit BW limit reached
+system.cpu0.commit.op_class_0::total           449604                       # Class of committed instruction
+system.cpu0.commit.bw_lim_events                  488                       # number cycles where commit BW limit reached
 system.cpu0.commit.bw_limited                       0                       # number of insts not committed due to BW limits
-system.cpu0.rob.rob_reads                      677713                       # The number of ROB reads
-system.cpu0.rob.rob_writes                     972345                       # The number of ROB writes
-system.cpu0.timesIdled                            334                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles                          25195                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.committedInsts                     396606                       # Number of Instructions Simulated
-system.cpu0.committedOps                       396606                       # Number of Ops (including micro ops) Simulated
-system.cpu0.cpi                              0.559603                       # CPI: Cycles Per Instruction
-system.cpu0.cpi_total                        0.559603                       # CPI: Total CPI of All Threads
-system.cpu0.ipc                              1.786980                       # IPC: Instructions Per Cycle
-system.cpu0.ipc_total                        1.786980                       # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads                  722190                       # number of integer regfile reads
-system.cpu0.int_regfile_writes                 325483                       # number of integer regfile writes
+system.cpu0.rob.rob_reads                      646276                       # The number of ROB reads
+system.cpu0.rob.rob_writes                     929096                       # The number of ROB writes
+system.cpu0.timesIdled                            317                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.idleCycles                          23956                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.committedInsts                     377391                       # Number of Instructions Simulated
+system.cpu0.committedOps                       377391                       # Number of Ops (including micro ops) Simulated
+system.cpu0.cpi                              0.559841                       # CPI: Cycles Per Instruction
+system.cpu0.cpi_total                        0.559841                       # CPI: Total CPI of All Threads
+system.cpu0.ipc                              1.786221                       # IPC: Instructions Per Cycle
+system.cpu0.ipc_total                        1.786221                       # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads                  688854                       # number of integer regfile reads
+system.cpu0.int_regfile_writes                 310766                       # number of integer regfile writes
 system.cpu0.fp_regfile_reads                      192                       # number of floating regfile reads
-system.cpu0.misc_regfile_reads                 235015                       # number of misc regfile reads
+system.cpu0.misc_regfile_reads                 223843                       # number of misc regfile reads
 system.cpu0.misc_regfile_writes                   564                       # number of misc regfile writes
-system.cpu0.icache.tags.replacements              297                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          241.252317                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs               5079                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs              587                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs             8.652470                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.replacements              322                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          240.566848                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs               6326                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs              612                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            10.336601                       # Average number of references to valid blocks.
 system.cpu0.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   241.252317                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.471196                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.471196                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   240.566848                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.469857                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.469857                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          290                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0           60                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          145                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2           85                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0           58                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1          188                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2           44                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024     0.566406                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses             6422                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses            6422                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst         5079                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total           5079                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst         5079                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total            5079                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst         5079                       # number of overall hits
-system.cpu0.icache.overall_hits::total           5079                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst          756                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total          756                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst          756                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total           756                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst          756                       # number of overall misses
-system.cpu0.icache.overall_misses::total          756                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst     35519995                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total     35519995                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst     35519995                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total     35519995                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst     35519995                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total     35519995                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst         5835                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total         5835                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst         5835                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total         5835                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst         5835                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total         5835                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.129563                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.129563                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.129563                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.129563                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.129563                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.129563                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 46984.120370                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 46984.120370                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 46984.120370                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 46984.120370                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 46984.120370                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 46984.120370                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu0.icache.tags.tag_accesses             7735                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses            7735                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst         6326                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total           6326                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst         6326                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total            6326                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst         6326                       # number of overall hits
+system.cpu0.icache.overall_hits::total           6326                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst          797                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total          797                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst          797                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total           797                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst          797                       # number of overall misses
+system.cpu0.icache.overall_misses::total          797                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst     36681496                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total     36681496                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst     36681496                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total     36681496                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst     36681496                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total     36681496                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst         7123                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total         7123                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst         7123                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total         7123                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst         7123                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total         7123                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.111891                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.111891                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.111891                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.111891                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.111891                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.111891                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 46024.461731                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 46024.461731                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 46024.461731                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 46024.461731                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 46024.461731                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 46024.461731                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs           22                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs                1                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs           22                       # average number of cycles each access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst          168                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total          168                       # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu0.inst          168                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total          168                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu0.inst          168                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total          168                       # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst          588                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total          588                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst          588                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total          588                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst          588                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total          588                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst     27366252                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total     27366252                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst     27366252                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total     27366252                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst     27366252                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total     27366252                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.100771                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.100771                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.100771                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.100771                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.100771                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.100771                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 46541.244898                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 46541.244898                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 46541.244898                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 46541.244898                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 46541.244898                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 46541.244898                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst          184                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total          184                       # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu0.inst          184                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total          184                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu0.inst          184                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total          184                       # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst          613                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total          613                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst          613                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total          613                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst          613                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total          613                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst     28176251                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total     28176251                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst     28176251                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total     28176251                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst     28176251                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total     28176251                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.086059                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.086059                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.086059                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.086059                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.086059                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.086059                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 45964.520392                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 45964.520392                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 45964.520392                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 45964.520392                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 45964.520392                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 45964.520392                       # average overall mshr miss latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu0.dcache.tags.replacements                2                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          141.985956                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs             155741                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.tagsinuse          141.515257                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs             148145                       # Total number of references to valid blocks.
 system.cpu0.dcache.tags.sampled_refs              170                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs           916.123529                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs           871.441176                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   141.985956                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.277316                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.277316                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   141.515257                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.276397                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.276397                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          168                       # Occupied blocks per task id
 system.cpu0.dcache.tags.age_task_id_blocks_1024::0           17                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1           52                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           99                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          105                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           46                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024     0.328125                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses           627612                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses          627612                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data        79059                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total          79059                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data        76768                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total         76768                       # number of WriteReq hits
-system.cpu0.dcache.SwapReq_hits::cpu0.data           21                       # number of SwapReq hits
-system.cpu0.dcache.SwapReq_hits::total             21                       # number of SwapReq hits
-system.cpu0.dcache.demand_hits::cpu0.data       155827                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total          155827                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data       155827                       # number of overall hits
-system.cpu0.dcache.overall_hits::total         155827                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data          413                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total          413                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data          543                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total          543                       # number of WriteReq misses
-system.cpu0.dcache.SwapReq_misses::cpu0.data           21                       # number of SwapReq misses
-system.cpu0.dcache.SwapReq_misses::total           21                       # number of SwapReq misses
-system.cpu0.dcache.demand_misses::cpu0.data          956                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total           956                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data          956                       # number of overall misses
-system.cpu0.dcache.overall_misses::total          956                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data     12955987                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total     12955987                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data     33432506                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total     33432506                       # number of WriteReq miss cycles
-system.cpu0.dcache.SwapReq_miss_latency::cpu0.data       404750                       # number of SwapReq miss cycles
-system.cpu0.dcache.SwapReq_miss_latency::total       404750                       # number of SwapReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data     46388493                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total     46388493                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data     46388493                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total     46388493                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data        79472                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total        79472                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data        77311                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total        77311                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.tags.tag_accesses           597526                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses          597526                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data        75309                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total          75309                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data        72924                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total         72924                       # number of WriteReq hits
+system.cpu0.dcache.SwapReq_hits::cpu0.data           20                       # number of SwapReq hits
+system.cpu0.dcache.SwapReq_hits::total             20                       # number of SwapReq hits
+system.cpu0.dcache.demand_hits::cpu0.data       148233                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total          148233                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data       148233                       # number of overall hits
+system.cpu0.dcache.overall_hits::total         148233                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data          484                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total          484                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data          544                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total          544                       # number of WriteReq misses
+system.cpu0.dcache.SwapReq_misses::cpu0.data           22                       # number of SwapReq misses
+system.cpu0.dcache.SwapReq_misses::total           22                       # number of SwapReq misses
+system.cpu0.dcache.demand_misses::cpu0.data         1028                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total          1028                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data         1028                       # number of overall misses
+system.cpu0.dcache.overall_misses::total         1028                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data     15258131                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total     15258131                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data     32871763                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total     32871763                       # number of WriteReq miss cycles
+system.cpu0.dcache.SwapReq_miss_latency::cpu0.data       427750                       # number of SwapReq miss cycles
+system.cpu0.dcache.SwapReq_miss_latency::total       427750                       # number of SwapReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data     48129894                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total     48129894                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data     48129894                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total     48129894                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data        75793                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total        75793                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data        73468                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total        73468                       # number of WriteReq accesses(hits+misses)
 system.cpu0.dcache.SwapReq_accesses::cpu0.data           42                       # number of SwapReq accesses(hits+misses)
 system.cpu0.dcache.SwapReq_accesses::total           42                       # number of SwapReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data       156783                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total       156783                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data       156783                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total       156783                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.005197                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.005197                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.007024                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.007024                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SwapReq_miss_rate::cpu0.data     0.500000                       # miss rate for SwapReq accesses
-system.cpu0.dcache.SwapReq_miss_rate::total     0.500000                       # miss rate for SwapReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.006098                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.006098                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.006098                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.006098                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 31370.428571                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 31370.428571                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 61569.992634                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 61569.992634                       # average WriteReq miss latency
-system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 19273.809524                       # average SwapReq miss latency
-system.cpu0.dcache.SwapReq_avg_miss_latency::total 19273.809524                       # average SwapReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 48523.528243                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 48523.528243                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 48523.528243                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 48523.528243                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs          692                       # number of cycles access was blocked
+system.cpu0.dcache.demand_accesses::cpu0.data       149261                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total       149261                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data       149261                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total       149261                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.006386                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.006386                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.007405                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.007405                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SwapReq_miss_rate::cpu0.data     0.523810                       # miss rate for SwapReq accesses
+system.cpu0.dcache.SwapReq_miss_rate::total     0.523810                       # miss rate for SwapReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.006887                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.006887                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.006887                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.006887                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 31525.064050                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 31525.064050                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 60426.034926                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 60426.034926                       # average WriteReq miss latency
+system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 19443.181818                       # average SwapReq miss latency
+system.cpu0.dcache.SwapReq_avg_miss_latency::total 19443.181818                       # average SwapReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 46818.963035                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 46818.963035                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 46818.963035                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 46818.963035                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs          754                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs               24                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs               27                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs    28.833333                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs    27.925926                       # average number of cycles each access was blocked
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
 system.cpu0.dcache.writebacks::writebacks            1                       # number of writebacks
 system.cpu0.dcache.writebacks::total                1                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data          226                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total          226                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data          368                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total          368                       # number of WriteReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data          594                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total          594                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data          594                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total          594                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data          187                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total          187                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data          175                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total          175                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data           21                       # number of SwapReq MSHR misses
-system.cpu0.dcache.SwapReq_mshr_misses::total           21                       # number of SwapReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data          301                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total          301                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data          365                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total          365                       # number of WriteReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data          666                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total          666                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data          666                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total          666                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data          183                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total          183                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data          179                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total          179                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data           22                       # number of SwapReq MSHR misses
+system.cpu0.dcache.SwapReq_mshr_misses::total           22                       # number of SwapReq MSHR misses
 system.cpu0.dcache.demand_mshr_misses::cpu0.data          362                       # number of demand (read+write) MSHR misses
 system.cpu0.dcache.demand_mshr_misses::total          362                       # number of demand (read+write) MSHR misses
 system.cpu0.dcache.overall_mshr_misses::cpu0.data          362                       # number of overall MSHR misses
 system.cpu0.dcache.overall_mshr_misses::total          362                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data      5995003                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total      5995003                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data      7531728                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total      7531728                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data       361250                       # number of SwapReq MSHR miss cycles
-system.cpu0.dcache.SwapReq_mshr_miss_latency::total       361250                       # number of SwapReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data     13526731                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total     13526731                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data     13526731                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total     13526731                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.002353                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.002353                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.002264                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.002264                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data     0.500000                       # mshr miss rate for SwapReq accesses
-system.cpu0.dcache.SwapReq_mshr_miss_rate::total     0.500000                       # mshr miss rate for SwapReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.002309                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.002309                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.002309                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.002309                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 32058.839572                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 32058.839572                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 43038.445714                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43038.445714                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 17202.380952                       # average SwapReq mshr miss latency
-system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 17202.380952                       # average SwapReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 37366.660221                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 37366.660221                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 37366.660221                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 37366.660221                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data      6274260                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total      6274260                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data      7393227                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total      7393227                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data       382250                       # number of SwapReq MSHR miss cycles
+system.cpu0.dcache.SwapReq_mshr_miss_latency::total       382250                       # number of SwapReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data     13667487                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total     13667487                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data     13667487                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total     13667487                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.002414                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.002414                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.002436                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.002436                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data     0.523810                       # mshr miss rate for SwapReq accesses
+system.cpu0.dcache.SwapReq_mshr_miss_rate::total     0.523810                       # mshr miss rate for SwapReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.002425                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.002425                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.002425                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.002425                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 34285.573770                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 34285.573770                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 41302.944134                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 41302.944134                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data        17375                       # average SwapReq mshr miss latency
+system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total        17375                       # average SwapReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 37755.488950                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 37755.488950                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 37755.488950                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 37755.488950                       # average overall mshr miss latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.branchPred.lookups                  52187                       # Number of BP lookups
-system.cpu1.branchPred.condPredicted            49510                       # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect             1259                       # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups               46153                       # Number of BTB lookups
-system.cpu1.branchPred.BTBHits                  45385                       # Number of BTB hits
+system.cpu1.branchPred.lookups                  54588                       # Number of BP lookups
+system.cpu1.branchPred.condPredicted            51200                       # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect             1286                       # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups               47257                       # Number of BTB lookups
+system.cpu1.branchPred.BTBHits                  46317                       # Number of BTB hits
 system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct            98.335969                       # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS                    643                       # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect               232                       # Number of incorrect RAS predictions.
-system.cpu1.numCycles                          177799                       # number of cpu cycles simulated
+system.cpu1.branchPred.BTBHitPct            98.010877                       # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS                    875                       # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect               231                       # Number of incorrect RAS predictions.
+system.cpu1.numCycles                          167979                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles             28925                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts                        291186                       # Number of instructions fetch has processed
-system.cpu1.fetch.Branches                      52187                       # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches             46028                       # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles                       103264                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles                   3653                       # Number of cycles fetch has spent squashing
-system.cpu1.fetch.BlockedCycles                 32544                       # Number of cycles fetch has spent blocked
-system.cpu1.fetch.MiscStallCycles                   5                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.NoActiveThreadStallCycles         7803                       # Number of stall cycles due to no active thread to fetch from
-system.cpu1.fetch.PendingTrapStallCycles          785                       # Number of stall cycles due to pending traps
-system.cpu1.fetch.CacheLines                    20583                       # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes                  266                       # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.rateDist::samples            175643                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean             1.657829                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev            2.130344                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.icacheStallCycles             29917                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts                        303462                       # Number of instructions fetch has processed
+system.cpu1.fetch.Branches                      54588                       # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches             47192                       # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles                       126841                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles                   2730                       # Number of cycles fetch has spent squashing
+system.cpu1.fetch.MiscStallCycles                   3                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.NoActiveThreadStallCycles         7060                       # Number of stall cycles due to no active thread to fetch from
+system.cpu1.fetch.PendingTrapStallCycles         1096                       # Number of stall cycles due to pending traps
+system.cpu1.fetch.CacheLines                    21062                       # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes                  421                       # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.rateDist::samples            166282                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean             1.824984                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev            2.191628                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0                   72379     41.21%     41.21% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1                   52711     30.01%     71.22% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2                    6570      3.74%     74.96% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3                    3206      1.83%     76.78% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4                     681      0.39%     77.17% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5                   34861     19.85%     97.02% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6                    1219      0.69%     97.71% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7                     754      0.43%     98.14% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8                    3262      1.86%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0                   60365     36.30%     36.30% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1                   53424     32.13%     68.43% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2                    6309      3.79%     72.23% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3                    3483      2.09%     74.32% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4                    1022      0.61%     74.93% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5                   35711     21.48%     96.41% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6                    1327      0.80%     97.21% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7                     762      0.46%     97.67% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8                    3879      2.33%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total              175643                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate                 0.293517                       # Number of branch fetches per cycle
-system.cpu1.fetch.rate                       1.637726                       # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles                   34549                       # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles                28563                       # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles                    96884                       # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles                 5527                       # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles                  2317                       # Number of cycles decode is squashing
-system.cpu1.decode.DecodedInsts                287488                       # Number of instructions handled by decode
-system.cpu1.rename.SquashCycles                  2317                       # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles                   35238                       # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles                  16093                       # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles         11725                       # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles                    91623                       # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles                10844                       # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts                285400                       # Number of instructions processed by rename
-system.cpu1.rename.IQFullEvents                     4                       # Number of times rename has blocked due to IQ full
-system.cpu1.rename.RenamedOperands             199084                       # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups               545686                       # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups          424083                       # Number of integer rename lookups
-system.cpu1.rename.CommittedMaps               186368                       # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps                   12716                       # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts              1090                       # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts          1211                       # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts                    13408                       # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads               80706                       # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores              38119                       # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads            38742                       # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores           33075                       # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded                    236041                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded               6768                       # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued                   238678                       # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued               59                       # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined          10581                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined        10451                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved           572                       # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples       175643                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean        1.358881                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev       1.308073                       # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::total              166282                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate                 0.324969                       # Number of branch fetches per cycle
+system.cpu1.fetch.rate                       1.806547                       # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles                   17455                       # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles                52641                       # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles                    84496                       # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles                 3265                       # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles                  1365                       # Number of cycles decode is squashing
+system.cpu1.decode.DecodedInsts                289136                       # Number of instructions handled by decode
+system.cpu1.rename.SquashCycles                  1365                       # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles                   18178                       # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles                  24205                       # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles         12371                       # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles                    85331                       # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles                17772                       # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts                285586                       # Number of instructions processed by rename
+system.cpu1.rename.IQFullEvents                 15350                       # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LQFullEvents                    25                       # Number of times rename has blocked due to LQ full
+system.cpu1.rename.FullRegisterEvents               3                       # Number of times there has been no free registers
+system.cpu1.rename.RenamedOperands             200979                       # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups               548958                       # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups          426905                       # Number of integer rename lookups
+system.cpu1.rename.CommittedMaps               186309                       # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps                   14670                       # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts              1186                       # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts          1247                       # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts                    22653                       # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads               80668                       # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores              38514                       # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads            38418                       # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores           33330                       # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded                    237514                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded               6089                       # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued                   238789                       # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued               33                       # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined          12748                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined        11558                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved           612                       # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples       166282                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean        1.436048                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev       1.378738                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0              69713     39.69%     39.69% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1              23816     13.56%     53.25% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2              38346     21.83%     75.08% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3              38982     22.19%     97.28% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4               3247      1.85%     99.12% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5               1165      0.66%     99.79% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::6                266      0.15%     99.94% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::7                 49      0.03%     99.97% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::8                 59      0.03%    100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0              63923     38.44%     38.44% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1              20825     12.52%     50.97% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2              37813     22.74%     73.71% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3              37389     22.49%     96.19% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4               3420      2.06%     98.25% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5               1614      0.97%     99.22% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::6                862      0.52%     99.74% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::7                239      0.14%     99.88% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::8                197      0.12%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total         175643                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total         166282                       # Number of insts issued each cycle
 system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu                     17      6.42%      6.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult                     0      0.00%      6.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv                      0      0.00%      6.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      6.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      6.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      6.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult                   0      0.00%      6.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      6.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      6.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      6.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      6.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      6.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      6.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      6.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      6.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult                    0      0.00%      6.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      6.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift                   0      0.00%      6.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      6.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      6.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      6.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      6.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      6.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      6.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      6.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      6.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      6.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      6.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      6.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead                    38     14.34%     20.75% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite                  210     79.25%    100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu                     89     25.65%     25.65% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult                     0      0.00%     25.65% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv                      0      0.00%     25.65% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd                    0      0.00%     25.65% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp                    0      0.00%     25.65% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt                    0      0.00%     25.65% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult                   0      0.00%     25.65% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv                    0      0.00%     25.65% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%     25.65% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd                     0      0.00%     25.65% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%     25.65% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu                     0      0.00%     25.65% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp                     0      0.00%     25.65% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt                     0      0.00%     25.65% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc                    0      0.00%     25.65% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult                    0      0.00%     25.65% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%     25.65% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift                   0      0.00%     25.65% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%     25.65% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%     25.65% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%     25.65% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%     25.65% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%     25.65% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%     25.65% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%     25.65% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%     25.65% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%     25.65% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%     25.65% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%     25.65% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead                    49     14.12%     39.77% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite                  209     60.23%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
 system.cpu1.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu               115728     48.49%     48.49% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult                   0      0.00%     48.49% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     48.49% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     48.49% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     48.49% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     48.49% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     48.49% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     48.49% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     48.49% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     48.49% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     48.49% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     48.49% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     48.49% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     48.49% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     48.49% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     48.49% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     48.49% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     48.49% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     48.49% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     48.49% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     48.49% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     48.49% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     48.49% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     48.49% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     48.49% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc             0      0.00%     48.49% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     48.49% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     48.49% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     48.49% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead               85517     35.83%     84.32% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite              37433     15.68%    100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu               116312     48.71%     48.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult                   0      0.00%     48.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     48.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     48.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     48.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     48.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     48.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     48.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     48.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     48.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     48.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     48.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     48.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     48.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     48.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     48.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     48.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     48.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     48.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     48.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     48.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     48.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     48.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     48.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     48.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc             0      0.00%     48.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     48.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     48.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     48.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead               84679     35.46%     84.17% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite              37798     15.83%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total                238678                       # Type of FU issued
-system.cpu1.iq.rate                          1.342404                       # Inst issue rate
-system.cpu1.iq.fu_busy_cnt                        265                       # FU busy when requested
-system.cpu1.iq.fu_busy_rate                  0.001110                       # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads            653323                       # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes           253430                       # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses       236861                       # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.FU_type_0::total                238789                       # Type of FU issued
+system.cpu1.iq.rate                          1.421541                       # Inst issue rate
+system.cpu1.iq.fu_busy_cnt                        347                       # FU busy when requested
+system.cpu1.iq.fu_busy_rate                  0.001453                       # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads            644240                       # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes           256392                       # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses       237045                       # Number of integer instruction queue wakeup accesses
 system.cpu1.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
 system.cpu1.iq.fp_inst_queue_writes                 0                       # Number of floating instruction queue writes
 system.cpu1.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses                238943                       # Number of integer alu accesses
+system.cpu1.iq.int_alu_accesses                239136                       # Number of integer alu accesses
 system.cpu1.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads           32850                       # Number of loads that had data forwarded from stores
+system.cpu1.iew.lsq.thread0.forwLoads           33095                       # Number of loads that had data forwarded from stores
 system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads         2336                       # Number of loads squashed
+system.cpu1.iew.lsq.thread0.squashedLoads         2693                       # Number of loads squashed
 system.cpu1.iew.lsq.thread0.ignoredResponses            3                       # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation           40                       # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores         1422                       # Number of stores squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation           41                       # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores         1647                       # Number of stores squashed
 system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu1.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
 system.cpu1.iew.lsq.thread0.cacheBlocked            0                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles                  2317                       # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles                    666                       # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles                   39                       # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts             282498                       # Number of instructions dispatched to IQ
-system.cpu1.iew.iewDispSquashedInsts              328                       # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts                80706                       # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts               38119                       # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts              1050                       # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents                    38                       # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewSquashCycles                  1365                       # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles                   6579                       # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles                   55                       # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts             282823                       # Number of instructions dispatched to IQ
+system.cpu1.iew.iewDispSquashedInsts              167                       # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispLoadInsts                80668                       # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts               38514                       # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts              1105                       # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents                    37                       # Number of times the IQ has become full, causing a stall
 system.cpu1.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents            40                       # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect           465                       # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect          907                       # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts                1372                       # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts               237512                       # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts                79760                       # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts             1166                       # Number of squashed instructions skipped in execute
+system.cpu1.iew.memOrderViolationEvents            41                       # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect           470                       # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect         1037                       # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts                1507                       # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts               237631                       # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts                79596                       # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts             1158                       # Number of squashed instructions skipped in execute
 system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu1.iew.exec_nop                        39689                       # number of nop insts executed
-system.cpu1.iew.exec_refs                      117113                       # number of memory reference insts executed
-system.cpu1.iew.exec_branches                   48963                       # Number of branches executed
-system.cpu1.iew.exec_stores                     37353                       # Number of stores executed
-system.cpu1.iew.exec_rate                    1.335846                       # Inst execution rate
-system.cpu1.iew.wb_sent                        237151                       # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count                       236861                       # cumulative count of insts written-back
-system.cpu1.iew.wb_producers                   133843                       # num instructions producing a value
-system.cpu1.iew.wb_consumers                   138503                       # num instructions consuming a value
+system.cpu1.iew.exec_nop                        39220                       # number of nop insts executed
+system.cpu1.iew.exec_refs                      117284                       # number of memory reference insts executed
+system.cpu1.iew.exec_branches                   48640                       # Number of branches executed
+system.cpu1.iew.exec_stores                     37688                       # Number of stores executed
+system.cpu1.iew.exec_rate                    1.414647                       # Inst execution rate
+system.cpu1.iew.wb_sent                        237349                       # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count                       237045                       # cumulative count of insts written-back
+system.cpu1.iew.wb_producers                   134973                       # num instructions producing a value
+system.cpu1.iew.wb_consumers                   141559                       # num instructions consuming a value
 system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu1.iew.wb_rate                      1.332184                       # insts written-back per cycle
-system.cpu1.iew.wb_fanout                    0.966355                       # average fanout of values written-back
+system.cpu1.iew.wb_rate                      1.411159                       # insts written-back per cycle
+system.cpu1.iew.wb_fanout                    0.953475                       # average fanout of values written-back
 system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.commit.commitSquashedInsts          12124                       # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls           6196                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts             1259                       # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples       165523                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean     1.633344                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev     2.016153                       # Number of insts commited each cycle
+system.cpu1.commit.commitSquashedInsts          14310                       # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls           5477                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts             1286                       # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples       156616                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean     1.714129                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev     2.075319                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0        67946     41.05%     41.05% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1        47096     28.45%     69.50% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2         6082      3.67%     73.18% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3         7142      4.31%     77.49% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4         1575      0.95%     78.44% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5        33355     20.15%     98.59% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6          510      0.31%     98.90% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7         1001      0.60%     99.51% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8          816      0.49%    100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0        61979     39.57%     39.57% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1        45369     28.97%     68.54% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2         5243      3.35%     71.89% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3         6285      4.01%     75.90% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4         1549      0.99%     76.89% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5        33128     21.15%     98.04% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6          818      0.52%     98.57% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7          954      0.61%     99.18% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8         1291      0.82%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total       165523                       # Number of insts commited each cycle
-system.cpu1.commit.committedInsts              270356                       # Number of instructions committed
-system.cpu1.commit.committedOps                270356                       # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total       156616                       # Number of insts commited each cycle
+system.cpu1.commit.committedInsts              268460                       # Number of instructions committed
+system.cpu1.commit.committedOps                268460                       # Number of ops (including micro ops) committed
 system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu1.commit.refs                        115067                       # Number of memory references committed
-system.cpu1.commit.loads                        78370                       # Number of loads committed
-system.cpu1.commit.membars                       5484                       # Number of memory barriers committed
-system.cpu1.commit.branches                     48146                       # Number of branches committed
+system.cpu1.commit.refs                        114842                       # Number of memory references committed
+system.cpu1.commit.loads                        77975                       # Number of loads committed
+system.cpu1.commit.membars                       4761                       # Number of memory barriers committed
+system.cpu1.commit.branches                     47591                       # Number of branches committed
 system.cpu1.commit.fp_insts                         0                       # Number of committed floating point instructions.
-system.cpu1.commit.int_insts                   185335                       # Number of committed integer instructions.
+system.cpu1.commit.int_insts                   184553                       # Number of committed integer instructions.
 system.cpu1.commit.function_calls                 322                       # Number of function calls committed.
-system.cpu1.commit.op_class_0::No_OpClass        38938     14.40%     14.40% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntAlu          110867     41.01%     55.41% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntMult              0      0.00%     55.41% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntDiv               0      0.00%     55.41% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     55.41% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     55.41% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     55.41% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatMult            0      0.00%     55.41% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     55.41% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     55.41% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     55.41% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     55.41% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     55.41% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     55.41% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     55.41% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     55.41% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMult             0      0.00%     55.41% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     55.41% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShift            0      0.00%     55.41% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     55.41% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     55.41% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     55.41% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     55.41% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     55.41% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     55.41% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     55.41% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMisc            0      0.00%     55.41% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     55.41% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     55.41% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     55.41% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemRead          83854     31.02%     86.43% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemWrite         36697     13.57%    100.00% # Class of committed instruction
+system.cpu1.commit.op_class_0::No_OpClass        38379     14.30%     14.30% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntAlu          110478     41.15%     55.45% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntMult              0      0.00%     55.45% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntDiv               0      0.00%     55.45% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     55.45% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     55.45% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     55.45% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatMult            0      0.00%     55.45% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     55.45% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     55.45% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     55.45% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     55.45% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     55.45% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     55.45% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     55.45% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     55.45% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMult             0      0.00%     55.45% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     55.45% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShift            0      0.00%     55.45% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     55.45% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     55.45% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     55.45% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     55.45% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     55.45% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     55.45% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     55.45% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMisc            0      0.00%     55.45% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     55.45% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     55.45% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     55.45% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemRead          82736     30.82%     86.27% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemWrite         36867     13.73%    100.00% # Class of committed instruction
 system.cpu1.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::total           270356                       # Class of committed instruction
-system.cpu1.commit.bw_lim_events                  816                       # number cycles where commit BW limit reached
+system.cpu1.commit.op_class_0::total           268460                       # Class of committed instruction
+system.cpu1.commit.bw_lim_events                 1291                       # number cycles where commit BW limit reached
 system.cpu1.commit.bw_limited                       0                       # number of insts not committed due to BW limits
-system.cpu1.rob.rob_reads                      446600                       # The number of ROB reads
-system.cpu1.rob.rob_writes                     567283                       # The number of ROB writes
-system.cpu1.timesIdled                            213                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles                           2156                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles                       44141                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts                     225934                       # Number of Instructions Simulated
-system.cpu1.committedOps                       225934                       # Number of Ops (including micro ops) Simulated
-system.cpu1.cpi                              0.786951                       # CPI: Cycles Per Instruction
-system.cpu1.cpi_total                        0.786951                       # CPI: Total CPI of All Threads
-system.cpu1.ipc                              1.270727                       # IPC: Instructions Per Cycle
-system.cpu1.ipc_total                        1.270727                       # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads                  409872                       # number of integer regfile reads
-system.cpu1.int_regfile_writes                 191136                       # number of integer regfile writes
+system.cpu1.rob.rob_reads                      437508                       # The number of ROB reads
+system.cpu1.rob.rob_writes                     568153                       # The number of ROB writes
+system.cpu1.timesIdled                            207                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles                           1697                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles                       43298                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.committedInsts                     225320                       # Number of Instructions Simulated
+system.cpu1.committedOps                       225320                       # Number of Ops (including micro ops) Simulated
+system.cpu1.cpi                              0.745513                       # CPI: Cycles Per Instruction
+system.cpu1.cpi_total                        0.745513                       # CPI: Total CPI of All Threads
+system.cpu1.ipc                              1.341358                       # IPC: Instructions Per Cycle
+system.cpu1.ipc_total                        1.341358                       # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads                  411671                       # number of integer regfile reads
+system.cpu1.int_regfile_writes                 192443                       # number of integer regfile writes
 system.cpu1.fp_regfile_writes                      64                       # number of floating regfile writes
-system.cpu1.misc_regfile_reads                 118682                       # number of misc regfile reads
+system.cpu1.misc_regfile_reads                 118908                       # number of misc regfile reads
 system.cpu1.misc_regfile_writes                   648                       # number of misc regfile writes
-system.cpu1.icache.tags.replacements              318                       # number of replacements
-system.cpu1.icache.tags.tagsinuse           79.885573                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs              20107                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs              428                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs            46.978972                       # Average number of references to valid blocks.
+system.cpu1.icache.tags.replacements              388                       # number of replacements
+system.cpu1.icache.tags.tagsinuse           78.688259                       # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs              20497                       # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs              497                       # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs            41.241449                       # Average number of references to valid blocks.
 system.cpu1.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst    79.885573                       # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst     0.156027                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total     0.156027                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_task_id_blocks::1024          110                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::0           10                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::1          100                       # Occupied blocks per task id
-system.cpu1.icache.tags.occ_task_id_percent::1024     0.214844                       # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses            21011                       # Number of tag accesses
-system.cpu1.icache.tags.data_accesses           21011                       # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst        20107                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total          20107                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst        20107                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total           20107                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst        20107                       # number of overall hits
-system.cpu1.icache.overall_hits::total          20107                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst          476                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total          476                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst          476                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total           476                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst          476                       # number of overall misses
-system.cpu1.icache.overall_misses::total          476                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst      7353244                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total      7353244                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst      7353244                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total      7353244                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst      7353244                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total      7353244                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst        20583                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total        20583                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst        20583                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total        20583                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst        20583                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total        20583                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.023126                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.023126                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.023126                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.023126                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.023126                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.023126                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15447.991597                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 15447.991597                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15447.991597                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 15447.991597                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15447.991597                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 15447.991597                       # average overall miss latency
-system.cpu1.icache.blocked_cycles::no_mshrs           26                       # number of cycles access was blocked
+system.cpu1.icache.tags.occ_blocks::cpu1.inst    78.688259                       # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst     0.153688                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total     0.153688                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_task_id_blocks::1024          109                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::0           11                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::1           98                       # Occupied blocks per task id
+system.cpu1.icache.tags.occ_task_id_percent::1024     0.212891                       # Percentage of cache occupancy per task id
+system.cpu1.icache.tags.tag_accesses            21559                       # Number of tag accesses
+system.cpu1.icache.tags.data_accesses           21559                       # Number of data accesses
+system.cpu1.icache.ReadReq_hits::cpu1.inst        20497                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total          20497                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst        20497                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total           20497                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst        20497                       # number of overall hits
+system.cpu1.icache.overall_hits::total          20497                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst          565                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total          565                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst          565                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total           565                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst          565                       # number of overall misses
+system.cpu1.icache.overall_misses::total          565                       # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst      8463744                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total      8463744                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst      8463744                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total      8463744                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst      8463744                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total      8463744                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst        21062                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total        21062                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst        21062                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total        21062                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst        21062                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total        21062                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.026826                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.026826                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.026826                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.026826                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.026826                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.026826                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14980.077876                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 14980.077876                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14980.077876                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 14980.077876                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14980.077876                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 14980.077876                       # average overall miss latency
+system.cpu1.icache.blocked_cycles::no_mshrs            2                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.icache.blocked::no_mshrs                2                       # number of cycles access was blocked
+system.cpu1.icache.blocked::no_mshrs                1                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_mshrs           13                       # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_mshrs            2                       # average number of cycles each access was blocked
 system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst           48                       # number of ReadReq MSHR hits
-system.cpu1.icache.ReadReq_mshr_hits::total           48                       # number of ReadReq MSHR hits
-system.cpu1.icache.demand_mshr_hits::cpu1.inst           48                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.demand_mshr_hits::total           48                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.overall_mshr_hits::cpu1.inst           48                       # number of overall MSHR hits
-system.cpu1.icache.overall_mshr_hits::total           48                       # number of overall MSHR hits
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst          428                       # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total          428                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst          428                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total          428                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst          428                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total          428                       # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst      5927255                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total      5927255                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst      5927255                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total      5927255                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst      5927255                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total      5927255                       # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.020794                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.020794                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.020794                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.020794                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.020794                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.020794                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13848.726636                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13848.726636                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13848.726636                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 13848.726636                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13848.726636                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 13848.726636                       # average overall mshr miss latency
+system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst           68                       # number of ReadReq MSHR hits
+system.cpu1.icache.ReadReq_mshr_hits::total           68                       # number of ReadReq MSHR hits
+system.cpu1.icache.demand_mshr_hits::cpu1.inst           68                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.demand_mshr_hits::total           68                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.overall_mshr_hits::cpu1.inst           68                       # number of overall MSHR hits
+system.cpu1.icache.overall_mshr_hits::total           68                       # number of overall MSHR hits
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst          497                       # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total          497                       # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst          497                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total          497                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst          497                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total          497                       # number of overall MSHR misses
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst      6616756                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total      6616756                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst      6616756                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total      6616756                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst      6616756                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total      6616756                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.023597                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.023597                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.023597                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total     0.023597                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.023597                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total     0.023597                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13313.392354                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13313.392354                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13313.392354                       # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total 13313.392354                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13313.392354                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total 13313.392354                       # average overall mshr miss latency
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.dcache.tags.replacements                0                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse           24.706566                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs              42694                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs               28                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs          1524.785714                       # Average number of references to valid blocks.
+system.cpu1.dcache.tags.tagsinuse           24.399537                       # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs              43036                       # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs               29                       # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs                 1484                       # Average number of references to valid blocks.
 system.cpu1.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data    24.706566                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data     0.048255                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total     0.048255                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024           28                       # Occupied blocks per task id
+system.cpu1.dcache.tags.occ_blocks::cpu1.data    24.399537                       # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data     0.047655                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total     0.047655                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_task_id_blocks::1024           29                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::0            1                       # Occupied blocks per task id
 system.cpu1.dcache.tags.age_task_id_blocks_1024::1           28                       # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024     0.054688                       # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses           334614                       # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses          334614                       # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data        46543                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total          46543                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data        36491                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total         36491                       # number of WriteReq hits
-system.cpu1.dcache.SwapReq_hits::cpu1.data           12                       # number of SwapReq hits
-system.cpu1.dcache.SwapReq_hits::total             12                       # number of SwapReq hits
-system.cpu1.dcache.demand_hits::cpu1.data        83034                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total           83034                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data        83034                       # number of overall hits
-system.cpu1.dcache.overall_hits::total          83034                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data          352                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total          352                       # number of ReadReq misses
+system.cpu1.dcache.tags.occ_task_id_percent::1024     0.056641                       # Percentage of cache occupancy per task id
+system.cpu1.dcache.tags.tag_accesses           333666                       # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses          333666                       # Number of data accesses
+system.cpu1.dcache.ReadReq_hits::cpu1.data        46059                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total          46059                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data        36657                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total         36657                       # number of WriteReq hits
+system.cpu1.dcache.SwapReq_hits::cpu1.data           13                       # number of SwapReq hits
+system.cpu1.dcache.SwapReq_hits::total             13                       # number of SwapReq hits
+system.cpu1.dcache.demand_hits::cpu1.data        82716                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total           82716                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data        82716                       # number of overall hits
+system.cpu1.dcache.overall_hits::total          82716                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data          427                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total          427                       # number of ReadReq misses
 system.cpu1.dcache.WriteReq_misses::cpu1.data          140                       # number of WriteReq misses
 system.cpu1.dcache.WriteReq_misses::total          140                       # number of WriteReq misses
-system.cpu1.dcache.SwapReq_misses::cpu1.data           54                       # number of SwapReq misses
-system.cpu1.dcache.SwapReq_misses::total           54                       # number of SwapReq misses
-system.cpu1.dcache.demand_misses::cpu1.data          492                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total           492                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data          492                       # number of overall misses
-system.cpu1.dcache.overall_misses::total          492                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data      4522597                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total      4522597                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data      3033762                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total      3033762                       # number of WriteReq miss cycles
-system.cpu1.dcache.SwapReq_miss_latency::cpu1.data       535508                       # number of SwapReq miss cycles
-system.cpu1.dcache.SwapReq_miss_latency::total       535508                       # number of SwapReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data      7556359                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total      7556359                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data      7556359                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total      7556359                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data        46895                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total        46895                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data        36631                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total        36631                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.SwapReq_accesses::cpu1.data           66                       # number of SwapReq accesses(hits+misses)
-system.cpu1.dcache.SwapReq_accesses::total           66                       # number of SwapReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data        83526                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total        83526                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data        83526                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total        83526                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.007506                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.007506                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.003822                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.003822                       # miss rate for WriteReq accesses
-system.cpu1.dcache.SwapReq_miss_rate::cpu1.data     0.818182                       # miss rate for SwapReq accesses
-system.cpu1.dcache.SwapReq_miss_rate::total     0.818182                       # miss rate for SwapReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.005890                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.005890                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.005890                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.005890                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12848.286932                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 12848.286932                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21669.728571                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 21669.728571                       # average WriteReq miss latency
-system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data  9916.814815                       # average SwapReq miss latency
-system.cpu1.dcache.SwapReq_avg_miss_latency::total  9916.814815                       # average SwapReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15358.453252                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 15358.453252                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15358.453252                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 15358.453252                       # average overall miss latency
+system.cpu1.dcache.SwapReq_misses::cpu1.data           57                       # number of SwapReq misses
+system.cpu1.dcache.SwapReq_misses::total           57                       # number of SwapReq misses
+system.cpu1.dcache.demand_misses::cpu1.data          567                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total           567                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data          567                       # number of overall misses
+system.cpu1.dcache.overall_misses::total          567                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data      5717104                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total      5717104                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data      2840511                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total      2840511                       # number of WriteReq miss cycles
+system.cpu1.dcache.SwapReq_miss_latency::cpu1.data       466006                       # number of SwapReq miss cycles
+system.cpu1.dcache.SwapReq_miss_latency::total       466006                       # number of SwapReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data      8557615                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total      8557615                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data      8557615                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total      8557615                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data        46486                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total        46486                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data        36797                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total        36797                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.SwapReq_accesses::cpu1.data           70                       # number of SwapReq accesses(hits+misses)
+system.cpu1.dcache.SwapReq_accesses::total           70                       # number of SwapReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data        83283                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total        83283                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data        83283                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total        83283                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.009186                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.009186                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.003805                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.003805                       # miss rate for WriteReq accesses
+system.cpu1.dcache.SwapReq_miss_rate::cpu1.data     0.814286                       # miss rate for SwapReq accesses
+system.cpu1.dcache.SwapReq_miss_rate::total     0.814286                       # miss rate for SwapReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.006808                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.006808                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.006808                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.006808                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13389.002342                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 13389.002342                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20289.364286                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 20289.364286                       # average WriteReq miss latency
+system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data  8175.543860                       # average SwapReq miss latency
+system.cpu1.dcache.SwapReq_avg_miss_latency::total  8175.543860                       # average SwapReq miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15092.795414                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 15092.795414                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15092.795414                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 15092.795414                       # average overall miss latency
 system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1726,517 +1729,519 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data          195                       # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total          195                       # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data           32                       # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total           32                       # number of WriteReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data          227                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total          227                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data          227                       # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total          227                       # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data          157                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total          157                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data          108                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total          108                       # number of WriteReq MSHR misses
-system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data           54                       # number of SwapReq MSHR misses
-system.cpu1.dcache.SwapReq_mshr_misses::total           54                       # number of SwapReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data          265                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total          265                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data          265                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total          265                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data      1099522                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total      1099522                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data      1387488                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total      1387488                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data       427492                       # number of SwapReq MSHR miss cycles
-system.cpu1.dcache.SwapReq_mshr_miss_latency::total       427492                       # number of SwapReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data      2487010                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total      2487010                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data      2487010                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total      2487010                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.003348                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.003348                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.002948                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.002948                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data     0.818182                       # mshr miss rate for SwapReq accesses
-system.cpu1.dcache.SwapReq_mshr_miss_rate::total     0.818182                       # mshr miss rate for SwapReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.003173                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.003173                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.003173                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.003173                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data  7003.324841                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total  7003.324841                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 12847.111111                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 12847.111111                       # average WriteReq mshr miss latency
-system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data  7916.518519                       # average SwapReq mshr miss latency
-system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total  7916.518519                       # average SwapReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data  9384.943396                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total  9384.943396                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data  9384.943396                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total  9384.943396                       # average overall mshr miss latency
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data          269                       # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total          269                       # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data           35                       # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total           35                       # number of WriteReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data          304                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total          304                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data          304                       # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total          304                       # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data          158                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total          158                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data          105                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total          105                       # number of WriteReq MSHR misses
+system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data           57                       # number of SwapReq MSHR misses
+system.cpu1.dcache.SwapReq_mshr_misses::total           57                       # number of SwapReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data          263                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total          263                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data          263                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total          263                       # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data      1020514                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total      1020514                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data      1289239                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total      1289239                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data       351994                       # number of SwapReq MSHR miss cycles
+system.cpu1.dcache.SwapReq_mshr_miss_latency::total       351994                       # number of SwapReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data      2309753                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total      2309753                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data      2309753                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total      2309753                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.003399                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.003399                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.002853                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.002853                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data     0.814286                       # mshr miss rate for SwapReq accesses
+system.cpu1.dcache.SwapReq_mshr_miss_rate::total     0.814286                       # mshr miss rate for SwapReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.003158                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total     0.003158                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.003158                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total     0.003158                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data  6458.949367                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total  6458.949367                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 12278.466667                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 12278.466667                       # average WriteReq mshr miss latency
+system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data  6175.333333                       # average SwapReq mshr miss latency
+system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total  6175.333333                       # average SwapReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data  8782.330798                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total  8782.330798                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data  8782.330798                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total  8782.330798                       # average overall mshr miss latency
 system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu2.branchPred.lookups                  51191                       # Number of BP lookups
-system.cpu2.branchPred.condPredicted            48468                       # Number of conditional branches predicted
-system.cpu2.branchPred.condIncorrect             1308                       # Number of conditional branches incorrect
-system.cpu2.branchPred.BTBLookups               44993                       # Number of BTB lookups
-system.cpu2.branchPred.BTBHits                  44297                       # Number of BTB hits
+system.cpu2.branchPred.lookups                  50591                       # Number of BP lookups
+system.cpu2.branchPred.condPredicted            46824                       # Number of conditional branches predicted
+system.cpu2.branchPred.condIncorrect             1298                       # Number of conditional branches incorrect
+system.cpu2.branchPred.BTBLookups               43166                       # Number of BTB lookups
+system.cpu2.branchPred.BTBHits                  41772                       # Number of BTB hits
 system.cpu2.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu2.branchPred.BTBHitPct            98.453093                       # BTB Hit Percentage
-system.cpu2.branchPred.usedRAS                    684                       # Number of times the RAS was used to get a target.
-system.cpu2.branchPred.RASInCorrect               232                       # Number of incorrect RAS predictions.
-system.cpu2.numCycles                          177434                       # number of cpu cycles simulated
+system.cpu2.branchPred.BTBHitPct            96.770606                       # BTB Hit Percentage
+system.cpu2.branchPred.usedRAS                    904                       # Number of times the RAS was used to get a target.
+system.cpu2.branchPred.RASInCorrect               231                       # Number of incorrect RAS predictions.
+system.cpu2.numCycles                          167617                       # number of cpu cycles simulated
 system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu2.fetch.icacheStallCycles             28865                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu2.fetch.Insts                        285908                       # Number of instructions fetch has processed
-system.cpu2.fetch.Branches                      51191                       # Number of branches that fetch encountered
-system.cpu2.fetch.predictedBranches             44981                       # Number of branches that fetch has predicted taken
-system.cpu2.fetch.Cycles                       100768                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu2.fetch.SquashCycles                   3816                       # Number of cycles fetch has spent squashing
-system.cpu2.fetch.BlockedCycles                 31184                       # Number of cycles fetch has spent blocked
+system.cpu2.fetch.icacheStallCycles             31796                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu2.fetch.Insts                        277876                       # Number of instructions fetch has processed
+system.cpu2.fetch.Branches                      50591                       # Number of branches that fetch encountered
+system.cpu2.fetch.predictedBranches             42676                       # Number of branches that fetch has predicted taken
+system.cpu2.fetch.Cycles                       121192                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu2.fetch.SquashCycles                   2752                       # Number of cycles fetch has spent squashing
 system.cpu2.fetch.MiscStallCycles                   4                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu2.fetch.NoActiveThreadStallCycles         7805                       # Number of stall cycles due to no active thread to fetch from
-system.cpu2.fetch.PendingTrapStallCycles         1366                       # Number of stall cycles due to pending traps
-system.cpu2.fetch.CacheLines                    19788                       # Number of cache lines fetched
-system.cpu2.fetch.IcacheSquashes                  272                       # Number of outstanding Icache misses that were squashed
-system.cpu2.fetch.rateDist::samples            172424                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::mean             1.658168                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::stdev            2.138146                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.NoActiveThreadStallCycles         7062                       # Number of stall cycles due to no active thread to fetch from
+system.cpu2.fetch.PendingTrapStallCycles         1110                       # Number of stall cycles due to pending traps
+system.cpu2.fetch.IcacheWaitRetryStallCycles            3                       # Number of stall cycles due to full MSHR
+system.cpu2.fetch.CacheLines                    22366                       # Number of cache lines fetched
+system.cpu2.fetch.IcacheSquashes                  459                       # Number of outstanding Icache misses that were squashed
+system.cpu2.fetch.rateDist::samples            162543                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::mean             1.709554                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::stdev            2.176994                       # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::0                   71656     41.56%     41.56% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::1                   51257     29.73%     71.29% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::2                    6128      3.55%     74.84% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::3                    3186      1.85%     76.69% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::4                     695      0.40%     77.09% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::5                   34284     19.88%     96.97% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::6                    1167      0.68%     97.65% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::7                     773      0.45%     98.10% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::8                    3278      1.90%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::0                   64711     39.81%     39.81% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::1                   49634     30.54%     70.35% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::2                    6798      4.18%     74.53% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::3                    3442      2.12%     76.65% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::4                     952      0.59%     77.23% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::5                   30771     18.93%     96.16% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::6                    1187      0.73%     96.89% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::7                     849      0.52%     97.42% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::8                    4199      2.58%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::total              172424                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.branchRate                 0.288507                       # Number of branch fetches per cycle
-system.cpu2.fetch.rate                       1.611348                       # Number of inst fetches per cycle
-system.cpu2.decode.IdleCycles                   34386                       # Number of cycles decode is idle
-system.cpu2.decode.BlockedCycles                27902                       # Number of cycles decode is blocked
-system.cpu2.decode.RunCycles                    94859                       # Number of cycles decode is running
-system.cpu2.decode.UnblockCycles                 5040                       # Number of cycles decode is unblocking
-system.cpu2.decode.SquashCycles                  2432                       # Number of cycles decode is squashing
-system.cpu2.decode.DecodedInsts                282267                       # Number of instructions handled by decode
-system.cpu2.rename.SquashCycles                  2432                       # Number of cycles rename is squashing
-system.cpu2.rename.IdleCycles                   35111                       # Number of cycles rename is idle
-system.cpu2.rename.BlockCycles                  14773                       # Number of cycles rename is blocking
-system.cpu2.rename.serializeStallCycles         12374                       # count of cycles rename stalled for serializing inst
-system.cpu2.rename.RunCycles                    90050                       # Number of cycles rename is running
-system.cpu2.rename.UnblockCycles                 9879                       # Number of cycles rename is unblocking
-system.cpu2.rename.RenamedInsts                280008                       # Number of instructions processed by rename
-system.cpu2.rename.IQFullEvents                     4                       # Number of times rename has blocked due to IQ full
-system.cpu2.rename.RenamedOperands             196247                       # Number of destination operands rename has renamed
-system.cpu2.rename.RenameLookups               536665                       # Number of register rename lookups that rename has made
-system.cpu2.rename.int_rename_lookups          417354                       # Number of integer rename lookups
-system.cpu2.rename.CommittedMaps               183125                       # Number of HB maps that are committed
-system.cpu2.rename.UndoneMaps                   13122                       # Number of HB maps that are undone due to squashing
-system.cpu2.rename.serializingInsts              1115                       # count of serializing insts renamed
-system.cpu2.rename.tempSerializingInsts          1240                       # count of temporary serializing insts renamed
-system.cpu2.rename.skidInsts                    12503                       # count of insts added to the skid buffer
-system.cpu2.memDep0.insertedLoads               79020                       # Number of loads inserted to the mem dependence unit.
-system.cpu2.memDep0.insertedStores              37489                       # Number of stores inserted to the mem dependence unit.
-system.cpu2.memDep0.conflictingLoads            37725                       # Number of conflicting loads.
-system.cpu2.memDep0.conflictingStores           32426                       # Number of conflicting stores.
-system.cpu2.iq.iqInstsAdded                    232155                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu2.iq.iqNonSpecInstsAdded               6357                       # Number of non-speculative instructions added to the IQ
-system.cpu2.iq.iqInstsIssued                   234096                       # Number of instructions issued
-system.cpu2.iq.iqSquashedInstsIssued              107                       # Number of squashed instructions issued
-system.cpu2.iq.iqSquashedInstsExamined          11107                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu2.iq.iqSquashedOperandsExamined        11056                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu2.iq.iqSquashedNonSpecRemoved           607                       # Number of squashed non-spec instructions that were removed
-system.cpu2.iq.issued_per_cycle::samples       172424                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::mean        1.357676                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::stdev       1.313193                       # Number of insts issued each cycle
+system.cpu2.fetch.rateDist::total              162543                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.branchRate                 0.301825                       # Number of branch fetches per cycle
+system.cpu2.fetch.rate                       1.657803                       # Number of inst fetches per cycle
+system.cpu2.decode.IdleCycles                   17997                       # Number of cycles decode is idle
+system.cpu2.decode.BlockedCycles                57677                       # Number of cycles decode is blocked
+system.cpu2.decode.RunCycles                    74910                       # Number of cycles decode is running
+system.cpu2.decode.UnblockCycles                 3521                       # Number of cycles decode is unblocking
+system.cpu2.decode.SquashCycles                  1376                       # Number of cycles decode is squashing
+system.cpu2.decode.DecodedInsts                262355                       # Number of instructions handled by decode
+system.cpu2.rename.SquashCycles                  1376                       # Number of cycles rename is squashing
+system.cpu2.rename.IdleCycles                   18679                       # Number of cycles rename is idle
+system.cpu2.rename.BlockCycles                  27128                       # Number of cycles rename is blocking
+system.cpu2.rename.serializeStallCycles         12799                       # count of cycles rename stalled for serializing inst
+system.cpu2.rename.RunCycles                    76466                       # Number of cycles rename is running
+system.cpu2.rename.UnblockCycles                19033                       # Number of cycles rename is unblocking
+system.cpu2.rename.RenamedInsts                259235                       # Number of instructions processed by rename
+system.cpu2.rename.IQFullEvents                 17033                       # Number of times rename has blocked due to IQ full
+system.cpu2.rename.LQFullEvents                    25                       # Number of times rename has blocked due to LQ full
+system.cpu2.rename.FullRegisterEvents               6                       # Number of times there has been no free registers
+system.cpu2.rename.RenamedOperands             182575                       # Number of destination operands rename has renamed
+system.cpu2.rename.RenameLookups               494395                       # Number of register rename lookups that rename has made
+system.cpu2.rename.int_rename_lookups          386046                       # Number of integer rename lookups
+system.cpu2.rename.CommittedMaps               167620                       # Number of HB maps that are committed
+system.cpu2.rename.UndoneMaps                   14955                       # Number of HB maps that are undone due to squashing
+system.cpu2.rename.serializingInsts              1169                       # count of serializing insts renamed
+system.cpu2.rename.tempSerializingInsts          1235                       # count of temporary serializing insts renamed
+system.cpu2.rename.skidInsts                    23554                       # count of insts added to the skid buffer
+system.cpu2.memDep0.insertedLoads               71776                       # Number of loads inserted to the mem dependence unit.
+system.cpu2.memDep0.insertedStores              33725                       # Number of stores inserted to the mem dependence unit.
+system.cpu2.memDep0.conflictingLoads            34298                       # Number of conflicting loads.
+system.cpu2.memDep0.conflictingStores           28594                       # Number of conflicting stores.
+system.cpu2.iq.iqInstsAdded                    214929                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu2.iq.iqNonSpecInstsAdded               6621                       # Number of non-speculative instructions added to the IQ
+system.cpu2.iq.iqInstsIssued                   216336                       # Number of instructions issued
+system.cpu2.iq.iqSquashedInstsIssued               47                       # Number of squashed instructions issued
+system.cpu2.iq.iqSquashedInstsExamined          13228                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu2.iq.iqSquashedOperandsExamined        12296                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu2.iq.iqSquashedNonSpecRemoved           674                       # Number of squashed non-spec instructions that were removed
+system.cpu2.iq.issued_per_cycle::samples       162543                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::mean        1.330946                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::stdev       1.384454                       # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::0              69134     40.10%     40.10% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::1              22467     13.03%     53.13% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::2              37714     21.87%     75.00% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::3              38330     22.23%     97.23% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::4               3239      1.88%     99.11% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::5               1151      0.67%     99.77% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::6                279      0.16%     99.94% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::7                 54      0.03%     99.97% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::8                 56      0.03%    100.00% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::0              68368     42.06%     42.06% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::1              22285     13.71%     55.77% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::2              32950     20.27%     76.04% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::3              32546     20.02%     96.07% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::4               3459      2.13%     98.19% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::5               1594      0.98%     99.17% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::6                888      0.55%     99.72% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::7                245      0.15%     99.87% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::8                208      0.13%    100.00% # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::total         172424                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::total         162543                       # Number of insts issued each cycle
 system.cpu2.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntAlu                     12      4.40%      4.40% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntMult                     0      0.00%      4.40% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntDiv                      0      0.00%      4.40% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatAdd                    0      0.00%      4.40% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCmp                    0      0.00%      4.40% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCvt                    0      0.00%      4.40% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatMult                   0      0.00%      4.40% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatDiv                    0      0.00%      4.40% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%      4.40% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAdd                     0      0.00%      4.40% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%      4.40% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAlu                     0      0.00%      4.40% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCmp                     0      0.00%      4.40% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCvt                     0      0.00%      4.40% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMisc                    0      0.00%      4.40% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMult                    0      0.00%      4.40% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%      4.40% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShift                   0      0.00%      4.40% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%      4.40% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%      4.40% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%      4.40% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%      4.40% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%      4.40% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%      4.40% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%      4.40% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%      4.40% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%      4.40% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%      4.40% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%      4.40% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemRead                    51     18.68%     23.08% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemWrite                  210     76.92%    100.00% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntAlu                     90     24.93%     24.93% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntMult                     0      0.00%     24.93% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntDiv                      0      0.00%     24.93% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatAdd                    0      0.00%     24.93% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCmp                    0      0.00%     24.93% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCvt                    0      0.00%     24.93% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatMult                   0      0.00%     24.93% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatDiv                    0      0.00%     24.93% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%     24.93% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAdd                     0      0.00%     24.93% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%     24.93% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAlu                     0      0.00%     24.93% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCmp                     0      0.00%     24.93% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCvt                     0      0.00%     24.93% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMisc                    0      0.00%     24.93% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMult                    0      0.00%     24.93% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%     24.93% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShift                   0      0.00%     24.93% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%     24.93% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%     24.93% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%     24.93% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%     24.93% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%     24.93% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%     24.93% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%     24.93% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%     24.93% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%     24.93% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%     24.93% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%     24.93% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemRead                    62     17.17%     42.11% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemWrite                  209     57.89%    100.00% # attempts to use FU when none available
 system.cpu2.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu2.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
 system.cpu2.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntAlu               114033     48.71%     48.71% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntMult                   0      0.00%     48.71% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntDiv                    0      0.00%     48.71% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatAdd                  0      0.00%     48.71% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     48.71% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCvt                  0      0.00%     48.71% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     48.71% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatDiv                  0      0.00%     48.71% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     48.71% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     48.71% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     48.71% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     48.71% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     48.71% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     48.71% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMisc                  0      0.00%     48.71% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     48.71% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     48.71% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     48.71% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     48.71% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     48.71% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     48.71% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     48.71% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     48.71% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     48.71% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     48.71% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMisc             0      0.00%     48.71% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     48.71% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     48.71% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     48.71% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemRead               83276     35.57%     84.29% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemWrite              36787     15.71%    100.00% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntAlu               107190     49.55%     49.55% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntMult                   0      0.00%     49.55% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntDiv                    0      0.00%     49.55% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatAdd                  0      0.00%     49.55% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     49.55% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCvt                  0      0.00%     49.55% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     49.55% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatDiv                  0      0.00%     49.55% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     49.55% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     49.55% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     49.55% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     49.55% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     49.55% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     49.55% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMisc                  0      0.00%     49.55% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     49.55% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     49.55% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     49.55% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     49.55% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     49.55% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     49.55% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     49.55% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     49.55% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     49.55% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     49.55% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMisc             0      0.00%     49.55% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     49.55% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     49.55% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     49.55% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemRead               76124     35.19%     84.74% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemWrite              33022     15.26%    100.00% # Type of FU issued
 system.cpu2.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu2.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::total                234096                       # Type of FU issued
-system.cpu2.iq.rate                          1.319341                       # Inst issue rate
-system.cpu2.iq.fu_busy_cnt                        273                       # FU busy when requested
-system.cpu2.iq.fu_busy_rate                  0.001166                       # FU busy rate (busy events/executed inst)
-system.cpu2.iq.int_inst_queue_reads            640996                       # Number of integer instruction queue reads
-system.cpu2.iq.int_inst_queue_writes           249665                       # Number of integer instruction queue writes
-system.cpu2.iq.int_inst_queue_wakeup_accesses       232273                       # Number of integer instruction queue wakeup accesses
+system.cpu2.iq.FU_type_0::total                216336                       # Type of FU issued
+system.cpu2.iq.rate                          1.290657                       # Inst issue rate
+system.cpu2.iq.fu_busy_cnt                        361                       # FU busy when requested
+system.cpu2.iq.fu_busy_rate                  0.001669                       # FU busy rate (busy events/executed inst)
+system.cpu2.iq.int_inst_queue_reads            595623                       # Number of integer instruction queue reads
+system.cpu2.iq.int_inst_queue_writes           234822                       # Number of integer instruction queue writes
+system.cpu2.iq.int_inst_queue_wakeup_accesses       214628                       # Number of integer instruction queue wakeup accesses
 system.cpu2.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
 system.cpu2.iq.fp_inst_queue_writes                 0                       # Number of floating instruction queue writes
 system.cpu2.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
-system.cpu2.iq.int_alu_accesses                234369                       # Number of integer alu accesses
+system.cpu2.iq.int_alu_accesses                216697                       # Number of integer alu accesses
 system.cpu2.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
-system.cpu2.iew.lsq.thread0.forwLoads           32149                       # Number of loads that had data forwarded from stores
+system.cpu2.iew.lsq.thread0.forwLoads           28314                       # Number of loads that had data forwarded from stores
 system.cpu2.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu2.iew.lsq.thread0.squashedLoads         2502                       # Number of loads squashed
+system.cpu2.iew.lsq.thread0.squashedLoads         2909                       # Number of loads squashed
 system.cpu2.iew.lsq.thread0.ignoredResponses            3                       # Number of memory responses ignored because the instruction is squashed
-system.cpu2.iew.lsq.thread0.memOrderViolation           46                       # Number of memory ordering violations
-system.cpu2.iew.lsq.thread0.squashedStores         1485                       # Number of stores squashed
+system.cpu2.iew.lsq.thread0.memOrderViolation           44                       # Number of memory ordering violations
+system.cpu2.iew.lsq.thread0.squashedStores         1648                       # Number of stores squashed
 system.cpu2.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu2.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu2.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
 system.cpu2.iew.lsq.thread0.cacheBlocked            0                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu2.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu2.iew.iewSquashCycles                  2432                       # Number of cycles IEW is squashing
-system.cpu2.iew.iewBlockCycles                    787                       # Number of cycles IEW is blocking
-system.cpu2.iew.iewUnblockCycles                   45                       # Number of cycles IEW is unblocking
-system.cpu2.iew.iewDispatchedInsts             277138                       # Number of instructions dispatched to IQ
-system.cpu2.iew.iewDispSquashedInsts              365                       # Number of squashed instructions skipped by dispatch
-system.cpu2.iew.iewDispLoadInsts                79020                       # Number of dispatched load instructions
-system.cpu2.iew.iewDispStoreInsts               37489                       # Number of dispatched store instructions
-system.cpu2.iew.iewDispNonSpecInsts              1072                       # Number of dispatched non-speculative instructions
-system.cpu2.iew.iewIQFullEvents                    45                       # Number of times the IQ has become full, causing a stall
+system.cpu2.iew.iewSquashCycles                  1376                       # Number of cycles IEW is squashing
+system.cpu2.iew.iewBlockCycles                   7567                       # Number of cycles IEW is blocking
+system.cpu2.iew.iewUnblockCycles                   67                       # Number of cycles IEW is unblocking
+system.cpu2.iew.iewDispatchedInsts             256538                       # Number of instructions dispatched to IQ
+system.cpu2.iew.iewDispSquashedInsts              192                       # Number of squashed instructions skipped by dispatch
+system.cpu2.iew.iewDispLoadInsts                71776                       # Number of dispatched load instructions
+system.cpu2.iew.iewDispStoreInsts               33725                       # Number of dispatched store instructions
+system.cpu2.iew.iewDispNonSpecInsts              1099                       # Number of dispatched non-speculative instructions
+system.cpu2.iew.iewIQFullEvents                    39                       # Number of times the IQ has become full, causing a stall
 system.cpu2.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
-system.cpu2.iew.memOrderViolationEvents            46                       # Number of memory order violations
+system.cpu2.iew.memOrderViolationEvents            44                       # Number of memory order violations
 system.cpu2.iew.predictedTakenIncorrect           464                       # Number of branches that were predicted taken incorrectly
-system.cpu2.iew.predictedNotTakenIncorrect          971                       # Number of branches that were predicted not taken incorrectly
-system.cpu2.iew.branchMispredicts                1435                       # Number of branch mispredicts detected at execute
-system.cpu2.iew.iewExecutedInsts               232944                       # Number of executed instructions
-system.cpu2.iew.iewExecLoadInsts                77967                       # Number of load instructions executed
-system.cpu2.iew.iewExecSquashedInsts             1152                       # Number of squashed instructions skipped in execute
+system.cpu2.iew.predictedNotTakenIncorrect         1069                       # Number of branches that were predicted not taken incorrectly
+system.cpu2.iew.branchMispredicts                1533                       # Number of branch mispredicts detected at execute
+system.cpu2.iew.iewExecutedInsts               215226                       # Number of executed instructions
+system.cpu2.iew.iewExecLoadInsts                70571                       # Number of load instructions executed
+system.cpu2.iew.iewExecSquashedInsts             1110                       # Number of squashed instructions skipped in execute
 system.cpu2.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu2.iew.exec_nop                        38626                       # number of nop insts executed
-system.cpu2.iew.exec_refs                      114664                       # number of memory reference insts executed
-system.cpu2.iew.exec_branches                   47841                       # Number of branches executed
-system.cpu2.iew.exec_stores                     36697                       # Number of stores executed
-system.cpu2.iew.exec_rate                    1.312849                       # Inst execution rate
-system.cpu2.iew.wb_sent                        232563                       # cumulative count of insts sent to commit
-system.cpu2.iew.wb_count                       232273                       # cumulative count of insts written-back
-system.cpu2.iew.wb_producers                   131430                       # num instructions producing a value
-system.cpu2.iew.wb_consumers                   136123                       # num instructions consuming a value
+system.cpu2.iew.exec_nop                        34988                       # number of nop insts executed
+system.cpu2.iew.exec_refs                      103485                       # number of memory reference insts executed
+system.cpu2.iew.exec_branches                   44292                       # Number of branches executed
+system.cpu2.iew.exec_stores                     32914                       # Number of stores executed
+system.cpu2.iew.exec_rate                    1.284034                       # Inst execution rate
+system.cpu2.iew.wb_sent                        214935                       # cumulative count of insts sent to commit
+system.cpu2.iew.wb_count                       214628                       # cumulative count of insts written-back
+system.cpu2.iew.wb_producers                   121102                       # num instructions producing a value
+system.cpu2.iew.wb_consumers                   127756                       # num instructions consuming a value
 system.cpu2.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu2.iew.wb_rate                      1.309067                       # insts written-back per cycle
-system.cpu2.iew.wb_fanout                    0.965524                       # average fanout of values written-back
+system.cpu2.iew.wb_rate                      1.280467                       # insts written-back per cycle
+system.cpu2.iew.wb_fanout                    0.947916                       # average fanout of values written-back
 system.cpu2.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu2.commit.commitSquashedInsts          12771                       # The number of squashed insts skipped by commit
-system.cpu2.commit.commitNonSpecStalls           5750                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu2.commit.branchMispredicts             1308                       # The number of times a branch was mispredicted
-system.cpu2.commit.committed_per_cycle::samples       162187                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::mean     1.630001                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::stdev     2.017893                       # Number of insts commited each cycle
+system.cpu2.commit.commitSquashedInsts          14883                       # The number of squashed insts skipped by commit
+system.cpu2.commit.commitNonSpecStalls           5947                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu2.commit.branchMispredicts             1298                       # The number of times a branch was mispredicted
+system.cpu2.commit.committed_per_cycle::samples       152800                       # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::mean     1.581165                       # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::stdev     2.037167                       # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::0        66847     41.22%     41.22% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::1        46010     28.37%     69.58% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::2         6109      3.77%     73.35% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::3         6666      4.11%     77.46% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::4         1557      0.96%     78.42% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::5        32708     20.17%     98.59% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::6          471      0.29%     98.88% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::7         1007      0.62%     99.50% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::8          812      0.50%    100.00% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::0        66891     43.78%     43.78% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::1        41018     26.84%     70.62% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::2         5166      3.38%     74.00% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::3         6776      4.43%     78.44% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::4         1516      0.99%     79.43% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::5        28304     18.52%     97.95% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::6          869      0.57%     98.52% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::7          954      0.62%     99.15% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::8         1306      0.85%    100.00% # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::total       162187                       # Number of insts commited each cycle
-system.cpu2.commit.committedInsts              264365                       # Number of instructions committed
-system.cpu2.commit.committedOps                264365                       # Number of ops (including micro ops) committed
+system.cpu2.commit.committed_per_cycle::total       152800                       # Number of insts commited each cycle
+system.cpu2.commit.committedInsts              241602                       # Number of instructions committed
+system.cpu2.commit.committedOps                241602                       # Number of ops (including micro ops) committed
 system.cpu2.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu2.commit.refs                        112522                       # Number of memory references committed
-system.cpu2.commit.loads                        76518                       # Number of loads committed
-system.cpu2.commit.membars                       5033                       # Number of memory barriers committed
-system.cpu2.commit.branches                     47000                       # Number of branches committed
+system.cpu2.commit.refs                        100944                       # Number of memory references committed
+system.cpu2.commit.loads                        68867                       # Number of loads committed
+system.cpu2.commit.membars                       5232                       # Number of memory barriers committed
+system.cpu2.commit.branches                     43270                       # Number of branches committed
 system.cpu2.commit.fp_insts                         0                       # Number of committed floating point instructions.
-system.cpu2.commit.int_insts                   181641                       # Number of committed integer instructions.
+system.cpu2.commit.int_insts                   166336                       # Number of committed integer instructions.
 system.cpu2.commit.function_calls                 322                       # Number of function calls committed.
-system.cpu2.commit.op_class_0::No_OpClass        37787     14.29%     14.29% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntAlu          109023     41.24%     55.53% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntMult              0      0.00%     55.53% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntDiv               0      0.00%     55.53% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatAdd             0      0.00%     55.53% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatCmp             0      0.00%     55.53% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatCvt             0      0.00%     55.53% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatMult            0      0.00%     55.53% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatDiv             0      0.00%     55.53% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatSqrt            0      0.00%     55.53% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAdd              0      0.00%     55.53% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAddAcc            0      0.00%     55.53% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAlu              0      0.00%     55.53% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdCmp              0      0.00%     55.53% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdCvt              0      0.00%     55.53% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMisc             0      0.00%     55.53% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMult             0      0.00%     55.53% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMultAcc            0      0.00%     55.53% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdShift            0      0.00%     55.53% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdShiftAcc            0      0.00%     55.53% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdSqrt             0      0.00%     55.53% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatAdd            0      0.00%     55.53% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatAlu            0      0.00%     55.53% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatCmp            0      0.00%     55.53% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatCvt            0      0.00%     55.53% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatDiv            0      0.00%     55.53% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMisc            0      0.00%     55.53% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMult            0      0.00%     55.53% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMultAcc            0      0.00%     55.53% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatSqrt            0      0.00%     55.53% # Class of committed instruction
-system.cpu2.commit.op_class_0::MemRead          81551     30.85%     86.38% # Class of committed instruction
-system.cpu2.commit.op_class_0::MemWrite         36004     13.62%    100.00% # Class of committed instruction
+system.cpu2.commit.op_class_0::No_OpClass        34059     14.10%     14.10% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntAlu          101367     41.96%     56.05% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntMult              0      0.00%     56.05% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntDiv               0      0.00%     56.05% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatAdd             0      0.00%     56.05% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatCmp             0      0.00%     56.05% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatCvt             0      0.00%     56.05% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatMult            0      0.00%     56.05% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatDiv             0      0.00%     56.05% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatSqrt            0      0.00%     56.05% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAdd              0      0.00%     56.05% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAddAcc            0      0.00%     56.05% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAlu              0      0.00%     56.05% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdCmp              0      0.00%     56.05% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdCvt              0      0.00%     56.05% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMisc             0      0.00%     56.05% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMult             0      0.00%     56.05% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMultAcc            0      0.00%     56.05% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdShift            0      0.00%     56.05% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdShiftAcc            0      0.00%     56.05% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdSqrt             0      0.00%     56.05% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatAdd            0      0.00%     56.05% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatAlu            0      0.00%     56.05% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatCmp            0      0.00%     56.05% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatCvt            0      0.00%     56.05% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatDiv            0      0.00%     56.05% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMisc            0      0.00%     56.05% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMult            0      0.00%     56.05% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMultAcc            0      0.00%     56.05% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatSqrt            0      0.00%     56.05% # Class of committed instruction
+system.cpu2.commit.op_class_0::MemRead          74099     30.67%     86.72% # Class of committed instruction
+system.cpu2.commit.op_class_0::MemWrite         32077     13.28%    100.00% # Class of committed instruction
 system.cpu2.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu2.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu2.commit.op_class_0::total           264365                       # Class of committed instruction
-system.cpu2.commit.bw_lim_events                  812                       # number cycles where commit BW limit reached
+system.cpu2.commit.op_class_0::total           241602                       # Class of committed instruction
+system.cpu2.commit.bw_lim_events                 1306                       # number cycles where commit BW limit reached
 system.cpu2.commit.bw_limited                       0                       # number of insts not committed due to BW limits
-system.cpu2.rob.rob_reads                      437924                       # The number of ROB reads
-system.cpu2.rob.rob_writes                     556709                       # The number of ROB writes
-system.cpu2.timesIdled                            223                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu2.idleCycles                           5010                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu2.quiesceCycles                       44506                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu2.committedInsts                     221545                       # Number of Instructions Simulated
-system.cpu2.committedOps                       221545                       # Number of Ops (including micro ops) Simulated
-system.cpu2.cpi                              0.800894                       # CPI: Cycles Per Instruction
-system.cpu2.cpi_total                        0.800894                       # CPI: Total CPI of All Threads
-system.cpu2.ipc                              1.248605                       # IPC: Instructions Per Cycle
-system.cpu2.ipc_total                        1.248605                       # IPC: Total IPC of All Threads
-system.cpu2.int_regfile_reads                  402715                       # number of integer regfile reads
-system.cpu2.int_regfile_writes                 188101                       # number of integer regfile writes
+system.cpu2.rob.rob_reads                      407392                       # The number of ROB reads
+system.cpu2.rob.rob_writes                     515662                       # The number of ROB writes
+system.cpu2.timesIdled                            212                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu2.idleCycles                           5074                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu2.quiesceCycles                       43660                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu2.committedInsts                     202311                       # Number of Instructions Simulated
+system.cpu2.committedOps                       202311                       # Number of Ops (including micro ops) Simulated
+system.cpu2.cpi                              0.828512                       # CPI: Cycles Per Instruction
+system.cpu2.cpi_total                        0.828512                       # CPI: Total CPI of All Threads
+system.cpu2.ipc                              1.206984                       # IPC: Instructions Per Cycle
+system.cpu2.ipc_total                        1.206984                       # IPC: Total IPC of All Threads
+system.cpu2.int_regfile_reads                  370344                       # number of integer regfile reads
+system.cpu2.int_regfile_writes                 173891                       # number of integer regfile writes
 system.cpu2.fp_regfile_writes                      64                       # number of floating regfile writes
-system.cpu2.misc_regfile_reads                 116228                       # number of misc regfile reads
+system.cpu2.misc_regfile_reads                 105089                       # number of misc regfile reads
 system.cpu2.misc_regfile_writes                   648                       # number of misc regfile writes
-system.cpu2.icache.tags.replacements              317                       # number of replacements
-system.cpu2.icache.tags.tagsinuse           81.450670                       # Cycle average of tags in use
-system.cpu2.icache.tags.total_refs              19300                       # Total number of references to valid blocks.
-system.cpu2.icache.tags.sampled_refs              424                       # Sample count of references to valid blocks.
-system.cpu2.icache.tags.avg_refs            45.518868                       # Average number of references to valid blocks.
+system.cpu2.icache.tags.replacements              378                       # number of replacements
+system.cpu2.icache.tags.tagsinuse           84.908829                       # Cycle average of tags in use
+system.cpu2.icache.tags.total_refs              21796                       # Total number of references to valid blocks.
+system.cpu2.icache.tags.sampled_refs              490                       # Sample count of references to valid blocks.
+system.cpu2.icache.tags.avg_refs            44.481633                       # Average number of references to valid blocks.
 system.cpu2.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu2.icache.tags.occ_blocks::cpu2.inst    81.450670                       # Average occupied blocks per requestor
-system.cpu2.icache.tags.occ_percent::cpu2.inst     0.159083                       # Average percentage of cache occupancy
-system.cpu2.icache.tags.occ_percent::total     0.159083                       # Average percentage of cache occupancy
-system.cpu2.icache.tags.occ_task_id_blocks::1024          107                       # Occupied blocks per task id
+system.cpu2.icache.tags.occ_blocks::cpu2.inst    84.908829                       # Average occupied blocks per requestor
+system.cpu2.icache.tags.occ_percent::cpu2.inst     0.165838                       # Average percentage of cache occupancy
+system.cpu2.icache.tags.occ_percent::total     0.165838                       # Average percentage of cache occupancy
+system.cpu2.icache.tags.occ_task_id_blocks::1024          112                       # Occupied blocks per task id
 system.cpu2.icache.tags.age_task_id_blocks_1024::0           11                       # Occupied blocks per task id
-system.cpu2.icache.tags.age_task_id_blocks_1024::1           96                       # Occupied blocks per task id
-system.cpu2.icache.tags.occ_task_id_percent::1024     0.208984                       # Percentage of cache occupancy per task id
-system.cpu2.icache.tags.tag_accesses            20212                       # Number of tag accesses
-system.cpu2.icache.tags.data_accesses           20212                       # Number of data accesses
-system.cpu2.icache.ReadReq_hits::cpu2.inst        19300                       # number of ReadReq hits
-system.cpu2.icache.ReadReq_hits::total          19300                       # number of ReadReq hits
-system.cpu2.icache.demand_hits::cpu2.inst        19300                       # number of demand (read+write) hits
-system.cpu2.icache.demand_hits::total           19300                       # number of demand (read+write) hits
-system.cpu2.icache.overall_hits::cpu2.inst        19300                       # number of overall hits
-system.cpu2.icache.overall_hits::total          19300                       # number of overall hits
-system.cpu2.icache.ReadReq_misses::cpu2.inst          488                       # number of ReadReq misses
-system.cpu2.icache.ReadReq_misses::total          488                       # number of ReadReq misses
-system.cpu2.icache.demand_misses::cpu2.inst          488                       # number of demand (read+write) misses
-system.cpu2.icache.demand_misses::total           488                       # number of demand (read+write) misses
-system.cpu2.icache.overall_misses::cpu2.inst          488                       # number of overall misses
-system.cpu2.icache.overall_misses::total          488                       # number of overall misses
-system.cpu2.icache.ReadReq_miss_latency::cpu2.inst     11534741                       # number of ReadReq miss cycles
-system.cpu2.icache.ReadReq_miss_latency::total     11534741                       # number of ReadReq miss cycles
-system.cpu2.icache.demand_miss_latency::cpu2.inst     11534741                       # number of demand (read+write) miss cycles
-system.cpu2.icache.demand_miss_latency::total     11534741                       # number of demand (read+write) miss cycles
-system.cpu2.icache.overall_miss_latency::cpu2.inst     11534741                       # number of overall miss cycles
-system.cpu2.icache.overall_miss_latency::total     11534741                       # number of overall miss cycles
-system.cpu2.icache.ReadReq_accesses::cpu2.inst        19788                       # number of ReadReq accesses(hits+misses)
-system.cpu2.icache.ReadReq_accesses::total        19788                       # number of ReadReq accesses(hits+misses)
-system.cpu2.icache.demand_accesses::cpu2.inst        19788                       # number of demand (read+write) accesses
-system.cpu2.icache.demand_accesses::total        19788                       # number of demand (read+write) accesses
-system.cpu2.icache.overall_accesses::cpu2.inst        19788                       # number of overall (read+write) accesses
-system.cpu2.icache.overall_accesses::total        19788                       # number of overall (read+write) accesses
-system.cpu2.icache.ReadReq_miss_rate::cpu2.inst     0.024661                       # miss rate for ReadReq accesses
-system.cpu2.icache.ReadReq_miss_rate::total     0.024661                       # miss rate for ReadReq accesses
-system.cpu2.icache.demand_miss_rate::cpu2.inst     0.024661                       # miss rate for demand accesses
-system.cpu2.icache.demand_miss_rate::total     0.024661                       # miss rate for demand accesses
-system.cpu2.icache.overall_miss_rate::cpu2.inst     0.024661                       # miss rate for overall accesses
-system.cpu2.icache.overall_miss_rate::total     0.024661                       # miss rate for overall accesses
-system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 23636.764344                       # average ReadReq miss latency
-system.cpu2.icache.ReadReq_avg_miss_latency::total 23636.764344                       # average ReadReq miss latency
-system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 23636.764344                       # average overall miss latency
-system.cpu2.icache.demand_avg_miss_latency::total 23636.764344                       # average overall miss latency
-system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 23636.764344                       # average overall miss latency
-system.cpu2.icache.overall_avg_miss_latency::total 23636.764344                       # average overall miss latency
-system.cpu2.icache.blocked_cycles::no_mshrs           85                       # number of cycles access was blocked
+system.cpu2.icache.tags.age_task_id_blocks_1024::1          101                       # Occupied blocks per task id
+system.cpu2.icache.tags.occ_task_id_percent::1024     0.218750                       # Percentage of cache occupancy per task id
+system.cpu2.icache.tags.tag_accesses            22856                       # Number of tag accesses
+system.cpu2.icache.tags.data_accesses           22856                       # Number of data accesses
+system.cpu2.icache.ReadReq_hits::cpu2.inst        21796                       # number of ReadReq hits
+system.cpu2.icache.ReadReq_hits::total          21796                       # number of ReadReq hits
+system.cpu2.icache.demand_hits::cpu2.inst        21796                       # number of demand (read+write) hits
+system.cpu2.icache.demand_hits::total           21796                       # number of demand (read+write) hits
+system.cpu2.icache.overall_hits::cpu2.inst        21796                       # number of overall hits
+system.cpu2.icache.overall_hits::total          21796                       # number of overall hits
+system.cpu2.icache.ReadReq_misses::cpu2.inst          570                       # number of ReadReq misses
+system.cpu2.icache.ReadReq_misses::total          570                       # number of ReadReq misses
+system.cpu2.icache.demand_misses::cpu2.inst          570                       # number of demand (read+write) misses
+system.cpu2.icache.demand_misses::total           570                       # number of demand (read+write) misses
+system.cpu2.icache.overall_misses::cpu2.inst          570                       # number of overall misses
+system.cpu2.icache.overall_misses::total          570                       # number of overall misses
+system.cpu2.icache.ReadReq_miss_latency::cpu2.inst     13348494                       # number of ReadReq miss cycles
+system.cpu2.icache.ReadReq_miss_latency::total     13348494                       # number of ReadReq miss cycles
+system.cpu2.icache.demand_miss_latency::cpu2.inst     13348494                       # number of demand (read+write) miss cycles
+system.cpu2.icache.demand_miss_latency::total     13348494                       # number of demand (read+write) miss cycles
+system.cpu2.icache.overall_miss_latency::cpu2.inst     13348494                       # number of overall miss cycles
+system.cpu2.icache.overall_miss_latency::total     13348494                       # number of overall miss cycles
+system.cpu2.icache.ReadReq_accesses::cpu2.inst        22366                       # number of ReadReq accesses(hits+misses)
+system.cpu2.icache.ReadReq_accesses::total        22366                       # number of ReadReq accesses(hits+misses)
+system.cpu2.icache.demand_accesses::cpu2.inst        22366                       # number of demand (read+write) accesses
+system.cpu2.icache.demand_accesses::total        22366                       # number of demand (read+write) accesses
+system.cpu2.icache.overall_accesses::cpu2.inst        22366                       # number of overall (read+write) accesses
+system.cpu2.icache.overall_accesses::total        22366                       # number of overall (read+write) accesses
+system.cpu2.icache.ReadReq_miss_rate::cpu2.inst     0.025485                       # miss rate for ReadReq accesses
+system.cpu2.icache.ReadReq_miss_rate::total     0.025485                       # miss rate for ReadReq accesses
+system.cpu2.icache.demand_miss_rate::cpu2.inst     0.025485                       # miss rate for demand accesses
+system.cpu2.icache.demand_miss_rate::total     0.025485                       # miss rate for demand accesses
+system.cpu2.icache.overall_miss_rate::cpu2.inst     0.025485                       # miss rate for overall accesses
+system.cpu2.icache.overall_miss_rate::total     0.025485                       # miss rate for overall accesses
+system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 23418.410526                       # average ReadReq miss latency
+system.cpu2.icache.ReadReq_avg_miss_latency::total 23418.410526                       # average ReadReq miss latency
+system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 23418.410526                       # average overall miss latency
+system.cpu2.icache.demand_avg_miss_latency::total 23418.410526                       # average overall miss latency
+system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 23418.410526                       # average overall miss latency
+system.cpu2.icache.overall_avg_miss_latency::total 23418.410526                       # average overall miss latency
+system.cpu2.icache.blocked_cycles::no_mshrs          128                       # number of cycles access was blocked
 system.cpu2.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu2.icache.blocked::no_mshrs                1                       # number of cycles access was blocked
+system.cpu2.icache.blocked::no_mshrs                3                       # number of cycles access was blocked
 system.cpu2.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu2.icache.avg_blocked_cycles::no_mshrs           85                       # average number of cycles each access was blocked
+system.cpu2.icache.avg_blocked_cycles::no_mshrs    42.666667                       # average number of cycles each access was blocked
 system.cpu2.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu2.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu2.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst           64                       # number of ReadReq MSHR hits
-system.cpu2.icache.ReadReq_mshr_hits::total           64                       # number of ReadReq MSHR hits
-system.cpu2.icache.demand_mshr_hits::cpu2.inst           64                       # number of demand (read+write) MSHR hits
-system.cpu2.icache.demand_mshr_hits::total           64                       # number of demand (read+write) MSHR hits
-system.cpu2.icache.overall_mshr_hits::cpu2.inst           64                       # number of overall MSHR hits
-system.cpu2.icache.overall_mshr_hits::total           64                       # number of overall MSHR hits
-system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst          424                       # number of ReadReq MSHR misses
-system.cpu2.icache.ReadReq_mshr_misses::total          424                       # number of ReadReq MSHR misses
-system.cpu2.icache.demand_mshr_misses::cpu2.inst          424                       # number of demand (read+write) MSHR misses
-system.cpu2.icache.demand_mshr_misses::total          424                       # number of demand (read+write) MSHR misses
-system.cpu2.icache.overall_mshr_misses::cpu2.inst          424                       # number of overall MSHR misses
-system.cpu2.icache.overall_mshr_misses::total          424                       # number of overall MSHR misses
-system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst      9234505                       # number of ReadReq MSHR miss cycles
-system.cpu2.icache.ReadReq_mshr_miss_latency::total      9234505                       # number of ReadReq MSHR miss cycles
-system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst      9234505                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.icache.demand_mshr_miss_latency::total      9234505                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst      9234505                       # number of overall MSHR miss cycles
-system.cpu2.icache.overall_mshr_miss_latency::total      9234505                       # number of overall MSHR miss cycles
-system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.021427                       # mshr miss rate for ReadReq accesses
-system.cpu2.icache.ReadReq_mshr_miss_rate::total     0.021427                       # mshr miss rate for ReadReq accesses
-system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst     0.021427                       # mshr miss rate for demand accesses
-system.cpu2.icache.demand_mshr_miss_rate::total     0.021427                       # mshr miss rate for demand accesses
-system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst     0.021427                       # mshr miss rate for overall accesses
-system.cpu2.icache.overall_mshr_miss_rate::total     0.021427                       # mshr miss rate for overall accesses
-system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 21779.492925                       # average ReadReq mshr miss latency
-system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 21779.492925                       # average ReadReq mshr miss latency
-system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 21779.492925                       # average overall mshr miss latency
-system.cpu2.icache.demand_avg_mshr_miss_latency::total 21779.492925                       # average overall mshr miss latency
-system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 21779.492925                       # average overall mshr miss latency
-system.cpu2.icache.overall_avg_mshr_miss_latency::total 21779.492925                       # average overall mshr miss latency
+system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst           80                       # number of ReadReq MSHR hits
+system.cpu2.icache.ReadReq_mshr_hits::total           80                       # number of ReadReq MSHR hits
+system.cpu2.icache.demand_mshr_hits::cpu2.inst           80                       # number of demand (read+write) MSHR hits
+system.cpu2.icache.demand_mshr_hits::total           80                       # number of demand (read+write) MSHR hits
+system.cpu2.icache.overall_mshr_hits::cpu2.inst           80                       # number of overall MSHR hits
+system.cpu2.icache.overall_mshr_hits::total           80                       # number of overall MSHR hits
+system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst          490                       # number of ReadReq MSHR misses
+system.cpu2.icache.ReadReq_mshr_misses::total          490                       # number of ReadReq MSHR misses
+system.cpu2.icache.demand_mshr_misses::cpu2.inst          490                       # number of demand (read+write) MSHR misses
+system.cpu2.icache.demand_mshr_misses::total          490                       # number of demand (read+write) MSHR misses
+system.cpu2.icache.overall_mshr_misses::cpu2.inst          490                       # number of overall MSHR misses
+system.cpu2.icache.overall_mshr_misses::total          490                       # number of overall MSHR misses
+system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst     10380255                       # number of ReadReq MSHR miss cycles
+system.cpu2.icache.ReadReq_mshr_miss_latency::total     10380255                       # number of ReadReq MSHR miss cycles
+system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst     10380255                       # number of demand (read+write) MSHR miss cycles
+system.cpu2.icache.demand_mshr_miss_latency::total     10380255                       # number of demand (read+write) MSHR miss cycles
+system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst     10380255                       # number of overall MSHR miss cycles
+system.cpu2.icache.overall_mshr_miss_latency::total     10380255                       # number of overall MSHR miss cycles
+system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.021908                       # mshr miss rate for ReadReq accesses
+system.cpu2.icache.ReadReq_mshr_miss_rate::total     0.021908                       # mshr miss rate for ReadReq accesses
+system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst     0.021908                       # mshr miss rate for demand accesses
+system.cpu2.icache.demand_mshr_miss_rate::total     0.021908                       # mshr miss rate for demand accesses
+system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst     0.021908                       # mshr miss rate for overall accesses
+system.cpu2.icache.overall_mshr_miss_rate::total     0.021908                       # mshr miss rate for overall accesses
+system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 21184.193878                       # average ReadReq mshr miss latency
+system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 21184.193878                       # average ReadReq mshr miss latency
+system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 21184.193878                       # average overall mshr miss latency
+system.cpu2.icache.demand_avg_mshr_miss_latency::total 21184.193878                       # average overall mshr miss latency
+system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 21184.193878                       # average overall mshr miss latency
+system.cpu2.icache.overall_avg_mshr_miss_latency::total 21184.193878                       # average overall mshr miss latency
 system.cpu2.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu2.dcache.tags.replacements                0                       # number of replacements
-system.cpu2.dcache.tags.tagsinuse           26.136002                       # Cycle average of tags in use
-system.cpu2.dcache.tags.total_refs              42041                       # Total number of references to valid blocks.
+system.cpu2.dcache.tags.tagsinuse           25.893249                       # Cycle average of tags in use
+system.cpu2.dcache.tags.total_refs              38186                       # Total number of references to valid blocks.
 system.cpu2.dcache.tags.sampled_refs               28                       # Sample count of references to valid blocks.
-system.cpu2.dcache.tags.avg_refs          1501.464286                       # Average number of references to valid blocks.
+system.cpu2.dcache.tags.avg_refs          1363.785714                       # Average number of references to valid blocks.
 system.cpu2.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu2.dcache.tags.occ_blocks::cpu2.data    26.136002                       # Average occupied blocks per requestor
-system.cpu2.dcache.tags.occ_percent::cpu2.data     0.051047                       # Average percentage of cache occupancy
-system.cpu2.dcache.tags.occ_percent::total     0.051047                       # Average percentage of cache occupancy
+system.cpu2.dcache.tags.occ_blocks::cpu2.data    25.893249                       # Average occupied blocks per requestor
+system.cpu2.dcache.tags.occ_percent::cpu2.data     0.050573                       # Average percentage of cache occupancy
+system.cpu2.dcache.tags.occ_percent::total     0.050573                       # Average percentage of cache occupancy
 system.cpu2.dcache.tags.occ_task_id_blocks::1024           28                       # Occupied blocks per task id
 system.cpu2.dcache.tags.age_task_id_blocks_1024::1           28                       # Occupied blocks per task id
 system.cpu2.dcache.tags.occ_task_id_percent::1024     0.054688                       # Percentage of cache occupancy per task id
-system.cpu2.dcache.tags.tag_accesses           327476                       # Number of tag accesses
-system.cpu2.dcache.tags.data_accesses          327476                       # Number of data accesses
-system.cpu2.dcache.ReadReq_hits::cpu2.data        45457                       # number of ReadReq hits
-system.cpu2.dcache.ReadReq_hits::total          45457                       # number of ReadReq hits
-system.cpu2.dcache.WriteReq_hits::cpu2.data        35794                       # number of WriteReq hits
-system.cpu2.dcache.WriteReq_hits::total         35794                       # number of WriteReq hits
-system.cpu2.dcache.SwapReq_hits::cpu2.data           13                       # number of SwapReq hits
-system.cpu2.dcache.SwapReq_hits::total             13                       # number of SwapReq hits
-system.cpu2.dcache.demand_hits::cpu2.data        81251                       # number of demand (read+write) hits
-system.cpu2.dcache.demand_hits::total           81251                       # number of demand (read+write) hits
-system.cpu2.dcache.overall_hits::cpu2.data        81251                       # number of overall hits
-system.cpu2.dcache.overall_hits::total          81251                       # number of overall hits
-system.cpu2.dcache.ReadReq_misses::cpu2.data          345                       # number of ReadReq misses
-system.cpu2.dcache.ReadReq_misses::total          345                       # number of ReadReq misses
-system.cpu2.dcache.WriteReq_misses::cpu2.data          139                       # number of WriteReq misses
-system.cpu2.dcache.WriteReq_misses::total          139                       # number of WriteReq misses
-system.cpu2.dcache.SwapReq_misses::cpu2.data           58                       # number of SwapReq misses
-system.cpu2.dcache.SwapReq_misses::total           58                       # number of SwapReq misses
-system.cpu2.dcache.demand_misses::cpu2.data          484                       # number of demand (read+write) misses
-system.cpu2.dcache.demand_misses::total           484                       # number of demand (read+write) misses
-system.cpu2.dcache.overall_misses::cpu2.data          484                       # number of overall misses
-system.cpu2.dcache.overall_misses::total          484                       # number of overall misses
-system.cpu2.dcache.ReadReq_miss_latency::cpu2.data      5375808                       # number of ReadReq miss cycles
-system.cpu2.dcache.ReadReq_miss_latency::total      5375808                       # number of ReadReq miss cycles
-system.cpu2.dcache.WriteReq_miss_latency::cpu2.data      3387510                       # number of WriteReq miss cycles
-system.cpu2.dcache.WriteReq_miss_latency::total      3387510                       # number of WriteReq miss cycles
-system.cpu2.dcache.SwapReq_miss_latency::cpu2.data       561006                       # number of SwapReq miss cycles
-system.cpu2.dcache.SwapReq_miss_latency::total       561006                       # number of SwapReq miss cycles
-system.cpu2.dcache.demand_miss_latency::cpu2.data      8763318                       # number of demand (read+write) miss cycles
-system.cpu2.dcache.demand_miss_latency::total      8763318                       # number of demand (read+write) miss cycles
-system.cpu2.dcache.overall_miss_latency::cpu2.data      8763318                       # number of overall miss cycles
-system.cpu2.dcache.overall_miss_latency::total      8763318                       # number of overall miss cycles
-system.cpu2.dcache.ReadReq_accesses::cpu2.data        45802                       # number of ReadReq accesses(hits+misses)
-system.cpu2.dcache.ReadReq_accesses::total        45802                       # number of ReadReq accesses(hits+misses)
-system.cpu2.dcache.WriteReq_accesses::cpu2.data        35933                       # number of WriteReq accesses(hits+misses)
-system.cpu2.dcache.WriteReq_accesses::total        35933                       # number of WriteReq accesses(hits+misses)
-system.cpu2.dcache.SwapReq_accesses::cpu2.data           71                       # number of SwapReq accesses(hits+misses)
-system.cpu2.dcache.SwapReq_accesses::total           71                       # number of SwapReq accesses(hits+misses)
-system.cpu2.dcache.demand_accesses::cpu2.data        81735                       # number of demand (read+write) accesses
-system.cpu2.dcache.demand_accesses::total        81735                       # number of demand (read+write) accesses
-system.cpu2.dcache.overall_accesses::cpu2.data        81735                       # number of overall (read+write) accesses
-system.cpu2.dcache.overall_accesses::total        81735                       # number of overall (read+write) accesses
-system.cpu2.dcache.ReadReq_miss_rate::cpu2.data     0.007532                       # miss rate for ReadReq accesses
-system.cpu2.dcache.ReadReq_miss_rate::total     0.007532                       # miss rate for ReadReq accesses
-system.cpu2.dcache.WriteReq_miss_rate::cpu2.data     0.003868                       # miss rate for WriteReq accesses
-system.cpu2.dcache.WriteReq_miss_rate::total     0.003868                       # miss rate for WriteReq accesses
-system.cpu2.dcache.SwapReq_miss_rate::cpu2.data     0.816901                       # miss rate for SwapReq accesses
-system.cpu2.dcache.SwapReq_miss_rate::total     0.816901                       # miss rate for SwapReq accesses
-system.cpu2.dcache.demand_miss_rate::cpu2.data     0.005922                       # miss rate for demand accesses
-system.cpu2.dcache.demand_miss_rate::total     0.005922                       # miss rate for demand accesses
-system.cpu2.dcache.overall_miss_rate::cpu2.data     0.005922                       # miss rate for overall accesses
-system.cpu2.dcache.overall_miss_rate::total     0.005922                       # miss rate for overall accesses
-system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 15582.052174                       # average ReadReq miss latency
-system.cpu2.dcache.ReadReq_avg_miss_latency::total 15582.052174                       # average ReadReq miss latency
-system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 24370.575540                       # average WriteReq miss latency
-system.cpu2.dcache.WriteReq_avg_miss_latency::total 24370.575540                       # average WriteReq miss latency
-system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data  9672.517241                       # average SwapReq miss latency
-system.cpu2.dcache.SwapReq_avg_miss_latency::total  9672.517241                       # average SwapReq miss latency
-system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 18106.028926                       # average overall miss latency
-system.cpu2.dcache.demand_avg_miss_latency::total 18106.028926                       # average overall miss latency
-system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 18106.028926                       # average overall miss latency
-system.cpu2.dcache.overall_avg_miss_latency::total 18106.028926                       # average overall miss latency
+system.cpu2.dcache.tags.tag_accesses           297518                       # Number of tag accesses
+system.cpu2.dcache.tags.data_accesses          297518                       # Number of data accesses
+system.cpu2.dcache.ReadReq_hits::cpu2.data        41817                       # number of ReadReq hits
+system.cpu2.dcache.ReadReq_hits::total          41817                       # number of ReadReq hits
+system.cpu2.dcache.WriteReq_hits::cpu2.data        31862                       # number of WriteReq hits
+system.cpu2.dcache.WriteReq_hits::total         31862                       # number of WriteReq hits
+system.cpu2.dcache.SwapReq_hits::cpu2.data           14                       # number of SwapReq hits
+system.cpu2.dcache.SwapReq_hits::total             14                       # number of SwapReq hits
+system.cpu2.dcache.demand_hits::cpu2.data        73679                       # number of demand (read+write) hits
+system.cpu2.dcache.demand_hits::total           73679                       # number of demand (read+write) hits
+system.cpu2.dcache.overall_hits::cpu2.data        73679                       # number of overall hits
+system.cpu2.dcache.overall_hits::total          73679                       # number of overall hits
+system.cpu2.dcache.ReadReq_misses::cpu2.data          422                       # number of ReadReq misses
+system.cpu2.dcache.ReadReq_misses::total          422                       # number of ReadReq misses
+system.cpu2.dcache.WriteReq_misses::cpu2.data          146                       # number of WriteReq misses
+system.cpu2.dcache.WriteReq_misses::total          146                       # number of WriteReq misses
+system.cpu2.dcache.SwapReq_misses::cpu2.data           55                       # number of SwapReq misses
+system.cpu2.dcache.SwapReq_misses::total           55                       # number of SwapReq misses
+system.cpu2.dcache.demand_misses::cpu2.data          568                       # number of demand (read+write) misses
+system.cpu2.dcache.demand_misses::total           568                       # number of demand (read+write) misses
+system.cpu2.dcache.overall_misses::cpu2.data          568                       # number of overall misses
+system.cpu2.dcache.overall_misses::total          568                       # number of overall misses
+system.cpu2.dcache.ReadReq_miss_latency::cpu2.data      7291559                       # number of ReadReq miss cycles
+system.cpu2.dcache.ReadReq_miss_latency::total      7291559                       # number of ReadReq miss cycles
+system.cpu2.dcache.WriteReq_miss_latency::cpu2.data      3658011                       # number of WriteReq miss cycles
+system.cpu2.dcache.WriteReq_miss_latency::total      3658011                       # number of WriteReq miss cycles
+system.cpu2.dcache.SwapReq_miss_latency::cpu2.data       499506                       # number of SwapReq miss cycles
+system.cpu2.dcache.SwapReq_miss_latency::total       499506                       # number of SwapReq miss cycles
+system.cpu2.dcache.demand_miss_latency::cpu2.data     10949570                       # number of demand (read+write) miss cycles
+system.cpu2.dcache.demand_miss_latency::total     10949570                       # number of demand (read+write) miss cycles
+system.cpu2.dcache.overall_miss_latency::cpu2.data     10949570                       # number of overall miss cycles
+system.cpu2.dcache.overall_miss_latency::total     10949570                       # number of overall miss cycles
+system.cpu2.dcache.ReadReq_accesses::cpu2.data        42239                       # number of ReadReq accesses(hits+misses)
+system.cpu2.dcache.ReadReq_accesses::total        42239                       # number of ReadReq accesses(hits+misses)
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+system.cpu2.dcache.WriteReq_accesses::total        32008                       # number of WriteReq accesses(hits+misses)
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+system.cpu2.dcache.SwapReq_accesses::total           69                       # number of SwapReq accesses(hits+misses)
+system.cpu2.dcache.demand_accesses::cpu2.data        74247                       # number of demand (read+write) accesses
+system.cpu2.dcache.demand_accesses::total        74247                       # number of demand (read+write) accesses
+system.cpu2.dcache.overall_accesses::cpu2.data        74247                       # number of overall (read+write) accesses
+system.cpu2.dcache.overall_accesses::total        74247                       # number of overall (read+write) accesses
+system.cpu2.dcache.ReadReq_miss_rate::cpu2.data     0.009991                       # miss rate for ReadReq accesses
+system.cpu2.dcache.ReadReq_miss_rate::total     0.009991                       # miss rate for ReadReq accesses
+system.cpu2.dcache.WriteReq_miss_rate::cpu2.data     0.004561                       # miss rate for WriteReq accesses
+system.cpu2.dcache.WriteReq_miss_rate::total     0.004561                       # miss rate for WriteReq accesses
+system.cpu2.dcache.SwapReq_miss_rate::cpu2.data     0.797101                       # miss rate for SwapReq accesses
+system.cpu2.dcache.SwapReq_miss_rate::total     0.797101                       # miss rate for SwapReq accesses
+system.cpu2.dcache.demand_miss_rate::cpu2.data     0.007650                       # miss rate for demand accesses
+system.cpu2.dcache.demand_miss_rate::total     0.007650                       # miss rate for demand accesses
+system.cpu2.dcache.overall_miss_rate::cpu2.data     0.007650                       # miss rate for overall accesses
+system.cpu2.dcache.overall_miss_rate::total     0.007650                       # miss rate for overall accesses
+system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 17278.575829                       # average ReadReq miss latency
+system.cpu2.dcache.ReadReq_avg_miss_latency::total 17278.575829                       # average ReadReq miss latency
+system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 25054.869863                       # average WriteReq miss latency
+system.cpu2.dcache.WriteReq_avg_miss_latency::total 25054.869863                       # average WriteReq miss latency
+system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data  9081.927273                       # average SwapReq miss latency
+system.cpu2.dcache.SwapReq_avg_miss_latency::total  9081.927273                       # average SwapReq miss latency
+system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 19277.411972                       # average overall miss latency
+system.cpu2.dcache.demand_avg_miss_latency::total 19277.411972                       # average overall miss latency
+system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 19277.411972                       # average overall miss latency
+system.cpu2.dcache.overall_avg_miss_latency::total 19277.411972                       # average overall miss latency
 system.cpu2.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu2.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu2.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -2245,404 +2250,405 @@ system.cpu2.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu2.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu2.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu2.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data          184                       # number of ReadReq MSHR hits
-system.cpu2.dcache.ReadReq_mshr_hits::total          184                       # number of ReadReq MSHR hits
-system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data           33                       # number of WriteReq MSHR hits
-system.cpu2.dcache.WriteReq_mshr_hits::total           33                       # number of WriteReq MSHR hits
-system.cpu2.dcache.demand_mshr_hits::cpu2.data          217                       # number of demand (read+write) MSHR hits
-system.cpu2.dcache.demand_mshr_hits::total          217                       # number of demand (read+write) MSHR hits
-system.cpu2.dcache.overall_mshr_hits::cpu2.data          217                       # number of overall MSHR hits
-system.cpu2.dcache.overall_mshr_hits::total          217                       # number of overall MSHR hits
+system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data          261                       # number of ReadReq MSHR hits
+system.cpu2.dcache.ReadReq_mshr_hits::total          261                       # number of ReadReq MSHR hits
+system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data           40                       # number of WriteReq MSHR hits
+system.cpu2.dcache.WriteReq_mshr_hits::total           40                       # number of WriteReq MSHR hits
+system.cpu2.dcache.demand_mshr_hits::cpu2.data          301                       # number of demand (read+write) MSHR hits
+system.cpu2.dcache.demand_mshr_hits::total          301                       # number of demand (read+write) MSHR hits
+system.cpu2.dcache.overall_mshr_hits::cpu2.data          301                       # number of overall MSHR hits
+system.cpu2.dcache.overall_mshr_hits::total          301                       # number of overall MSHR hits
 system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data          161                       # number of ReadReq MSHR misses
 system.cpu2.dcache.ReadReq_mshr_misses::total          161                       # number of ReadReq MSHR misses
 system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data          106                       # number of WriteReq MSHR misses
 system.cpu2.dcache.WriteReq_mshr_misses::total          106                       # number of WriteReq MSHR misses
-system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data           58                       # number of SwapReq MSHR misses
-system.cpu2.dcache.SwapReq_mshr_misses::total           58                       # number of SwapReq MSHR misses
+system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data           55                       # number of SwapReq MSHR misses
+system.cpu2.dcache.SwapReq_mshr_misses::total           55                       # number of SwapReq MSHR misses
 system.cpu2.dcache.demand_mshr_misses::cpu2.data          267                       # number of demand (read+write) MSHR misses
 system.cpu2.dcache.demand_mshr_misses::total          267                       # number of demand (read+write) MSHR misses
 system.cpu2.dcache.overall_mshr_misses::cpu2.data          267                       # number of overall MSHR misses
 system.cpu2.dcache.overall_mshr_misses::total          267                       # number of overall MSHR misses
-system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data      1467781                       # number of ReadReq MSHR miss cycles
-system.cpu2.dcache.ReadReq_mshr_miss_latency::total      1467781                       # number of ReadReq MSHR miss cycles
-system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data      1796490                       # number of WriteReq MSHR miss cycles
-system.cpu2.dcache.WriteReq_mshr_miss_latency::total      1796490                       # number of WriteReq MSHR miss cycles
-system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data       444994                       # number of SwapReq MSHR miss cycles
-system.cpu2.dcache.SwapReq_mshr_miss_latency::total       444994                       # number of SwapReq MSHR miss cycles
-system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data      3264271                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.dcache.demand_mshr_miss_latency::total      3264271                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data      3264271                       # number of overall MSHR miss cycles
-system.cpu2.dcache.overall_mshr_miss_latency::total      3264271                       # number of overall MSHR miss cycles
-system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.003515                       # mshr miss rate for ReadReq accesses
-system.cpu2.dcache.ReadReq_mshr_miss_rate::total     0.003515                       # mshr miss rate for ReadReq accesses
-system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.002950                       # mshr miss rate for WriteReq accesses
-system.cpu2.dcache.WriteReq_mshr_miss_rate::total     0.002950                       # mshr miss rate for WriteReq accesses
-system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data     0.816901                       # mshr miss rate for SwapReq accesses
-system.cpu2.dcache.SwapReq_mshr_miss_rate::total     0.816901                       # mshr miss rate for SwapReq accesses
-system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data     0.003267                       # mshr miss rate for demand accesses
-system.cpu2.dcache.demand_mshr_miss_rate::total     0.003267                       # mshr miss rate for demand accesses
-system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data     0.003267                       # mshr miss rate for overall accesses
-system.cpu2.dcache.overall_mshr_miss_rate::total     0.003267                       # mshr miss rate for overall accesses
-system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data  9116.652174                       # average ReadReq mshr miss latency
-system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total  9116.652174                       # average ReadReq mshr miss latency
-system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 16948.018868                       # average WriteReq mshr miss latency
-system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 16948.018868                       # average WriteReq mshr miss latency
-system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data  7672.310345                       # average SwapReq mshr miss latency
-system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total  7672.310345                       # average SwapReq mshr miss latency
-system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 12225.734082                       # average overall mshr miss latency
-system.cpu2.dcache.demand_avg_mshr_miss_latency::total 12225.734082                       # average overall mshr miss latency
-system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 12225.734082                       # average overall mshr miss latency
-system.cpu2.dcache.overall_avg_mshr_miss_latency::total 12225.734082                       # average overall mshr miss latency
+system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data      1541774                       # number of ReadReq MSHR miss cycles
+system.cpu2.dcache.ReadReq_mshr_miss_latency::total      1541774                       # number of ReadReq MSHR miss cycles
+system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data      1509739                       # number of WriteReq MSHR miss cycles
+system.cpu2.dcache.WriteReq_mshr_miss_latency::total      1509739                       # number of WriteReq MSHR miss cycles
+system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data       389494                       # number of SwapReq MSHR miss cycles
+system.cpu2.dcache.SwapReq_mshr_miss_latency::total       389494                       # number of SwapReq MSHR miss cycles
+system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data      3051513                       # number of demand (read+write) MSHR miss cycles
+system.cpu2.dcache.demand_mshr_miss_latency::total      3051513                       # number of demand (read+write) MSHR miss cycles
+system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data      3051513                       # number of overall MSHR miss cycles
+system.cpu2.dcache.overall_mshr_miss_latency::total      3051513                       # number of overall MSHR miss cycles
+system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.003812                       # mshr miss rate for ReadReq accesses
+system.cpu2.dcache.ReadReq_mshr_miss_rate::total     0.003812                       # mshr miss rate for ReadReq accesses
+system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.003312                       # mshr miss rate for WriteReq accesses
+system.cpu2.dcache.WriteReq_mshr_miss_rate::total     0.003312                       # mshr miss rate for WriteReq accesses
+system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data     0.797101                       # mshr miss rate for SwapReq accesses
+system.cpu2.dcache.SwapReq_mshr_miss_rate::total     0.797101                       # mshr miss rate for SwapReq accesses
+system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data     0.003596                       # mshr miss rate for demand accesses
+system.cpu2.dcache.demand_mshr_miss_rate::total     0.003596                       # mshr miss rate for demand accesses
+system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data     0.003596                       # mshr miss rate for overall accesses
+system.cpu2.dcache.overall_mshr_miss_rate::total     0.003596                       # mshr miss rate for overall accesses
+system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data  9576.236025                       # average ReadReq mshr miss latency
+system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total  9576.236025                       # average ReadReq mshr miss latency
+system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 14242.820755                       # average WriteReq mshr miss latency
+system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 14242.820755                       # average WriteReq mshr miss latency
+system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data  7081.709091                       # average SwapReq mshr miss latency
+system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total  7081.709091                       # average SwapReq mshr miss latency
+system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 11428.887640                       # average overall mshr miss latency
+system.cpu2.dcache.demand_avg_mshr_miss_latency::total 11428.887640                       # average overall mshr miss latency
+system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 11428.887640                       # average overall mshr miss latency
+system.cpu2.dcache.overall_avg_mshr_miss_latency::total 11428.887640                       # average overall mshr miss latency
 system.cpu2.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu3.branchPred.lookups                  47572                       # Number of BP lookups
-system.cpu3.branchPred.condPredicted            44838                       # Number of conditional branches predicted
-system.cpu3.branchPred.condIncorrect             1269                       # Number of conditional branches incorrect
-system.cpu3.branchPred.BTBLookups               41556                       # Number of BTB lookups
-system.cpu3.branchPred.BTBHits                  40675                       # Number of BTB hits
+system.cpu3.branchPred.lookups                  48151                       # Number of BP lookups
+system.cpu3.branchPred.condPredicted            44685                       # Number of conditional branches predicted
+system.cpu3.branchPred.condIncorrect             1287                       # Number of conditional branches incorrect
+system.cpu3.branchPred.BTBLookups               41038                       # Number of BTB lookups
+system.cpu3.branchPred.BTBHits                  39836                       # Number of BTB hits
 system.cpu3.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu3.branchPred.BTBHitPct            97.879969                       # BTB Hit Percentage
-system.cpu3.branchPred.usedRAS                    650                       # Number of times the RAS was used to get a target.
-system.cpu3.branchPred.RASInCorrect               232                       # Number of incorrect RAS predictions.
-system.cpu3.numCycles                          177088                       # number of cpu cycles simulated
+system.cpu3.branchPred.BTBHitPct            97.071007                       # BTB Hit Percentage
+system.cpu3.branchPred.usedRAS                    888                       # Number of times the RAS was used to get a target.
+system.cpu3.branchPred.RASInCorrect               231                       # Number of incorrect RAS predictions.
+system.cpu3.numCycles                          167273                       # number of cpu cycles simulated
 system.cpu3.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu3.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu3.fetch.icacheStallCycles             31611                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu3.fetch.Insts                        260615                       # Number of instructions fetch has processed
-system.cpu3.fetch.Branches                      47572                       # Number of branches that fetch encountered
-system.cpu3.fetch.predictedBranches             41325                       # Number of branches that fetch has predicted taken
-system.cpu3.fetch.Cycles                        95272                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu3.fetch.SquashCycles                   3721                       # Number of cycles fetch has spent squashing
-system.cpu3.fetch.BlockedCycles                 37783                       # Number of cycles fetch has spent blocked
-system.cpu3.fetch.MiscStallCycles                   5                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu3.fetch.NoActiveThreadStallCycles         7803                       # Number of stall cycles due to no active thread to fetch from
-system.cpu3.fetch.PendingTrapStallCycles          790                       # Number of stall cycles due to pending traps
-system.cpu3.fetch.CacheLines                    23344                       # Number of cache lines fetched
-system.cpu3.fetch.IcacheSquashes                  257                       # Number of outstanding Icache misses that were squashed
-system.cpu3.fetch.rateDist::samples            175638                       # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::mean             1.483819                       # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::stdev            2.061741                       # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.icacheStallCycles             33692                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu3.fetch.Insts                        260486                       # Number of instructions fetch has processed
+system.cpu3.fetch.Branches                      48151                       # Number of branches that fetch encountered
+system.cpu3.fetch.predictedBranches             40724                       # Number of branches that fetch has predicted taken
+system.cpu3.fetch.Cycles                       122974                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu3.fetch.SquashCycles                   2726                       # Number of cycles fetch has spent squashing
+system.cpu3.fetch.MiscStallCycles                   3                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu3.fetch.NoActiveThreadStallCycles         7060                       # Number of stall cycles due to no active thread to fetch from
+system.cpu3.fetch.PendingTrapStallCycles         1076                       # Number of stall cycles due to pending traps
+system.cpu3.fetch.CacheLines                    24907                       # Number of cache lines fetched
+system.cpu3.fetch.IcacheSquashes                  418                       # Number of outstanding Icache misses that were squashed
+system.cpu3.fetch.rateDist::samples            166168                       # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::mean             1.567606                       # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::stdev            2.102870                       # Number of instructions fetched each cycle (Total)
 system.cpu3.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::0                   80366     45.76%     45.76% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::1                   49379     28.11%     73.87% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::2                    7947      4.52%     78.40% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::3                    3182      1.81%     80.21% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::4                     669      0.38%     80.59% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::5                   28809     16.40%     96.99% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::6                    1228      0.70%     97.69% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::7                     757      0.43%     98.12% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::8                    3301      1.88%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::0                   71279     42.90%     42.90% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::1                   48852     29.40%     72.29% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::2                    8282      4.98%     77.28% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::3                    3511      2.11%     79.39% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::4                    1059      0.64%     80.03% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::5                   27347     16.46%     96.49% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::6                    1190      0.72%     97.20% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::7                     758      0.46%     97.66% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::8                    3890      2.34%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu3.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu3.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu3.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::total              175638                       # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.branchRate                 0.268635                       # Number of branch fetches per cycle
-system.cpu3.fetch.rate                       1.471669                       # Number of inst fetches per cycle
-system.cpu3.decode.IdleCycles                   38601                       # Number of cycles decode is idle
-system.cpu3.decode.BlockedCycles                32457                       # Number of cycles decode is blocked
-system.cpu3.decode.RunCycles                    87595                       # Number of cycles decode is running
-system.cpu3.decode.UnblockCycles                 6808                       # Number of cycles decode is unblocking
-system.cpu3.decode.SquashCycles                  2374                       # Number of cycles decode is squashing
-system.cpu3.decode.DecodedInsts                256826                       # Number of instructions handled by decode
-system.cpu3.rename.SquashCycles                  2374                       # Number of cycles rename is squashing
-system.cpu3.rename.IdleCycles                   39299                       # Number of cycles rename is idle
-system.cpu3.rename.BlockCycles                  20012                       # Number of cycles rename is blocking
-system.cpu3.rename.serializeStallCycles         11695                       # count of cycles rename stalled for serializing inst
-system.cpu3.rename.RunCycles                    81034                       # Number of cycles rename is running
-system.cpu3.rename.UnblockCycles                13421                       # Number of cycles rename is unblocking
-system.cpu3.rename.RenamedInsts                254587                       # Number of instructions processed by rename
-system.cpu3.rename.IQFullEvents                     1                       # Number of times rename has blocked due to IQ full
-system.cpu3.rename.RenamedOperands             176229                       # Number of destination operands rename has renamed
-system.cpu3.rename.RenameLookups               478476                       # Number of register rename lookups that rename has made
-system.cpu3.rename.int_rename_lookups          373673                       # Number of integer rename lookups
-system.cpu3.rename.CommittedMaps               163264                       # Number of HB maps that are committed
-system.cpu3.rename.UndoneMaps                   12965                       # Number of HB maps that are undone due to squashing
-system.cpu3.rename.serializingInsts              1094                       # count of serializing insts renamed
-system.cpu3.rename.tempSerializingInsts          1216                       # count of temporary serializing insts renamed
-system.cpu3.rename.skidInsts                    16061                       # count of insts added to the skid buffer
-system.cpu3.memDep0.insertedLoads               69948                       # Number of loads inserted to the mem dependence unit.
-system.cpu3.memDep0.insertedStores              32037                       # Number of stores inserted to the mem dependence unit.
-system.cpu3.memDep0.conflictingLoads            34088                       # Number of conflicting loads.
-system.cpu3.memDep0.conflictingStores           26994                       # Number of conflicting stores.
-system.cpu3.iq.iqInstsAdded                    208399                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu3.iq.iqNonSpecInstsAdded               8161                       # Number of non-speculative instructions added to the IQ
-system.cpu3.iq.iqInstsIssued                   212159                       # Number of instructions issued
-system.cpu3.iq.iqSquashedInstsIssued              124                       # Number of squashed instructions issued
-system.cpu3.iq.iqSquashedInstsExamined          10835                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu3.iq.iqSquashedOperandsExamined        11026                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu3.iq.iqSquashedNonSpecRemoved           608                       # Number of squashed non-spec instructions that were removed
-system.cpu3.iq.issued_per_cycle::samples       175638                       # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::mean        1.207933                       # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::stdev       1.292111                       # Number of insts issued each cycle
+system.cpu3.fetch.rateDist::total              166168                       # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.branchRate                 0.287859                       # Number of branch fetches per cycle
+system.cpu3.fetch.rate                       1.557251                       # Number of inst fetches per cycle
+system.cpu3.decode.IdleCycles                   17558                       # Number of cycles decode is idle
+system.cpu3.decode.BlockedCycles                68128                       # Number of cycles decode is blocked
+system.cpu3.decode.RunCycles                    67891                       # Number of cycles decode is running
+system.cpu3.decode.UnblockCycles                 4168                       # Number of cycles decode is unblocking
+system.cpu3.decode.SquashCycles                  1363                       # Number of cycles decode is squashing
+system.cpu3.decode.DecodedInsts                246104                       # Number of instructions handled by decode
+system.cpu3.rename.SquashCycles                  1363                       # Number of cycles rename is squashing
+system.cpu3.rename.IdleCycles                   18233                       # Number of cycles rename is idle
+system.cpu3.rename.BlockCycles                  33368                       # Number of cycles rename is blocking
+system.cpu3.rename.serializeStallCycles         12463                       # count of cycles rename stalled for serializing inst
+system.cpu3.rename.RunCycles                    69060                       # Number of cycles rename is running
+system.cpu3.rename.UnblockCycles                24621                       # Number of cycles rename is unblocking
+system.cpu3.rename.RenamedInsts                242881                       # Number of instructions processed by rename
+system.cpu3.rename.IQFullEvents                 21589                       # Number of times rename has blocked due to IQ full
+system.cpu3.rename.LQFullEvents                    28                       # Number of times rename has blocked due to LQ full
+system.cpu3.rename.FullRegisterEvents               3                       # Number of times there has been no free registers
+system.cpu3.rename.RenamedOperands             169259                       # Number of destination operands rename has renamed
+system.cpu3.rename.RenameLookups               456177                       # Number of register rename lookups that rename has made
+system.cpu3.rename.int_rename_lookups          357242                       # Number of integer rename lookups
+system.cpu3.rename.CommittedMaps               154687                       # Number of HB maps that are committed
+system.cpu3.rename.UndoneMaps                   14572                       # Number of HB maps that are undone due to squashing
+system.cpu3.rename.serializingInsts              1184                       # count of serializing insts renamed
+system.cpu3.rename.tempSerializingInsts          1245                       # count of temporary serializing insts renamed
+system.cpu3.rename.skidInsts                    29195                       # count of insts added to the skid buffer
+system.cpu3.memDep0.insertedLoads               65863                       # Number of loads inserted to the mem dependence unit.
+system.cpu3.memDep0.insertedStores              30140                       # Number of stores inserted to the mem dependence unit.
+system.cpu3.memDep0.conflictingLoads            31966                       # Number of conflicting loads.
+system.cpu3.memDep0.conflictingStores           25009                       # Number of conflicting stores.
+system.cpu3.iq.iqInstsAdded                    199372                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu3.iq.iqNonSpecInstsAdded               7958                       # Number of non-speculative instructions added to the IQ
+system.cpu3.iq.iqInstsIssued                   202308                       # Number of instructions issued
+system.cpu3.iq.iqSquashedInstsIssued               33                       # Number of squashed instructions issued
+system.cpu3.iq.iqSquashedInstsExamined          12859                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu3.iq.iqSquashedOperandsExamined        11887                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu3.iq.iqSquashedNonSpecRemoved           683                       # Number of squashed non-spec instructions that were removed
+system.cpu3.iq.issued_per_cycle::samples       166168                       # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::mean        1.217491                       # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::stdev       1.364227                       # Number of insts issued each cycle
 system.cpu3.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::0              77942     44.38%     44.38% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::1              27771     15.81%     60.19% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::2              32234     18.35%     78.54% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::3              32910     18.74%     97.28% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::4               3253      1.85%     99.13% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::5               1156      0.66%     99.79% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::6                263      0.15%     99.94% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::7                 52      0.03%     99.97% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::8                 57      0.03%    100.00% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::0              75148     45.22%     45.22% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::1              26256     15.80%     61.02% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::2              29417     17.70%     78.73% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::3              29010     17.46%     96.19% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::4               3447      2.07%     98.26% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::5               1582      0.95%     99.21% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::6                873      0.53%     99.74% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::7                228      0.14%     99.88% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::8                207      0.12%    100.00% # Number of insts issued each cycle
 system.cpu3.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu3.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu3.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::total         175638                       # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::total         166168                       # Number of insts issued each cycle
 system.cpu3.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntAlu                     12      4.44%      4.44% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntMult                     0      0.00%      4.44% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntDiv                      0      0.00%      4.44% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatAdd                    0      0.00%      4.44% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatCmp                    0      0.00%      4.44% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatCvt                    0      0.00%      4.44% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatMult                   0      0.00%      4.44% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatDiv                    0      0.00%      4.44% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatSqrt                   0      0.00%      4.44% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdAdd                     0      0.00%      4.44% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdAddAcc                  0      0.00%      4.44% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdAlu                     0      0.00%      4.44% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdCmp                     0      0.00%      4.44% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdCvt                     0      0.00%      4.44% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdMisc                    0      0.00%      4.44% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdMult                    0      0.00%      4.44% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdMultAcc                 0      0.00%      4.44% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdShift                   0      0.00%      4.44% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdShiftAcc                0      0.00%      4.44% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdSqrt                    0      0.00%      4.44% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatAdd                0      0.00%      4.44% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatAlu                0      0.00%      4.44% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatCmp                0      0.00%      4.44% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatCvt                0      0.00%      4.44% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatDiv                0      0.00%      4.44% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatMisc               0      0.00%      4.44% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatMult               0      0.00%      4.44% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatMultAcc            0      0.00%      4.44% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatSqrt               0      0.00%      4.44% # attempts to use FU when none available
-system.cpu3.iq.fu_full::MemRead                    48     17.78%     22.22% # attempts to use FU when none available
-system.cpu3.iq.fu_full::MemWrite                  210     77.78%    100.00% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntAlu                     93     25.83%     25.83% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntMult                     0      0.00%     25.83% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntDiv                      0      0.00%     25.83% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatAdd                    0      0.00%     25.83% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatCmp                    0      0.00%     25.83% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatCvt                    0      0.00%     25.83% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatMult                   0      0.00%     25.83% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatDiv                    0      0.00%     25.83% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatSqrt                   0      0.00%     25.83% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAdd                     0      0.00%     25.83% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAddAcc                  0      0.00%     25.83% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAlu                     0      0.00%     25.83% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdCmp                     0      0.00%     25.83% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdCvt                     0      0.00%     25.83% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMisc                    0      0.00%     25.83% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMult                    0      0.00%     25.83% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMultAcc                 0      0.00%     25.83% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdShift                   0      0.00%     25.83% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdShiftAcc                0      0.00%     25.83% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdSqrt                    0      0.00%     25.83% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatAdd                0      0.00%     25.83% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatAlu                0      0.00%     25.83% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatCmp                0      0.00%     25.83% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatCvt                0      0.00%     25.83% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatDiv                0      0.00%     25.83% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMisc               0      0.00%     25.83% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMult               0      0.00%     25.83% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMultAcc            0      0.00%     25.83% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatSqrt               0      0.00%     25.83% # attempts to use FU when none available
+system.cpu3.iq.fu_full::MemRead                    58     16.11%     41.94% # attempts to use FU when none available
+system.cpu3.iq.fu_full::MemWrite                  209     58.06%    100.00% # attempts to use FU when none available
 system.cpu3.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu3.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
 system.cpu3.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntAlu               104799     49.40%     49.40% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntMult                   0      0.00%     49.40% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntDiv                    0      0.00%     49.40% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatAdd                  0      0.00%     49.40% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatCmp                  0      0.00%     49.40% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatCvt                  0      0.00%     49.40% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatMult                 0      0.00%     49.40% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatDiv                  0      0.00%     49.40% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatSqrt                 0      0.00%     49.40% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdAdd                   0      0.00%     49.40% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdAddAcc                0      0.00%     49.40% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdAlu                   0      0.00%     49.40% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdCmp                   0      0.00%     49.40% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdCvt                   0      0.00%     49.40% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdMisc                  0      0.00%     49.40% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdMult                  0      0.00%     49.40% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdMultAcc               0      0.00%     49.40% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdShift                 0      0.00%     49.40% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdShiftAcc              0      0.00%     49.40% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdSqrt                  0      0.00%     49.40% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatAdd              0      0.00%     49.40% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatAlu              0      0.00%     49.40% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatCmp              0      0.00%     49.40% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatCvt              0      0.00%     49.40% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatDiv              0      0.00%     49.40% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatMisc             0      0.00%     49.40% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatMult             0      0.00%     49.40% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     49.40% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatSqrt             0      0.00%     49.40% # Type of FU issued
-system.cpu3.iq.FU_type_0::MemRead               76027     35.83%     85.23% # Type of FU issued
-system.cpu3.iq.FU_type_0::MemWrite              31333     14.77%    100.00% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntAlu               101290     50.07%     50.07% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntMult                   0      0.00%     50.07% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntDiv                    0      0.00%     50.07% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatAdd                  0      0.00%     50.07% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatCmp                  0      0.00%     50.07% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatCvt                  0      0.00%     50.07% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatMult                 0      0.00%     50.07% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatDiv                  0      0.00%     50.07% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatSqrt                 0      0.00%     50.07% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdAdd                   0      0.00%     50.07% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdAddAcc                0      0.00%     50.07% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdAlu                   0      0.00%     50.07% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdCmp                   0      0.00%     50.07% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdCvt                   0      0.00%     50.07% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdMisc                  0      0.00%     50.07% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdMult                  0      0.00%     50.07% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdMultAcc               0      0.00%     50.07% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdShift                 0      0.00%     50.07% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdShiftAcc              0      0.00%     50.07% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdSqrt                  0      0.00%     50.07% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatAdd              0      0.00%     50.07% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatAlu              0      0.00%     50.07% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatCmp              0      0.00%     50.07% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatCvt              0      0.00%     50.07% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatDiv              0      0.00%     50.07% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatMisc             0      0.00%     50.07% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatMult             0      0.00%     50.07% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     50.07% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatSqrt             0      0.00%     50.07% # Type of FU issued
+system.cpu3.iq.FU_type_0::MemRead               71575     35.38%     85.45% # Type of FU issued
+system.cpu3.iq.FU_type_0::MemWrite              29443     14.55%    100.00% # Type of FU issued
 system.cpu3.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu3.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu3.iq.FU_type_0::total                212159                       # Type of FU issued
-system.cpu3.iq.rate                          1.198043                       # Inst issue rate
-system.cpu3.iq.fu_busy_cnt                        270                       # FU busy when requested
-system.cpu3.iq.fu_busy_rate                  0.001273                       # FU busy rate (busy events/executed inst)
-system.cpu3.iq.int_inst_queue_reads            600350                       # Number of integer instruction queue reads
-system.cpu3.iq.int_inst_queue_writes           227441                       # Number of integer instruction queue writes
-system.cpu3.iq.int_inst_queue_wakeup_accesses       210302                       # Number of integer instruction queue wakeup accesses
+system.cpu3.iq.FU_type_0::total                202308                       # Type of FU issued
+system.cpu3.iq.rate                          1.209448                       # Inst issue rate
+system.cpu3.iq.fu_busy_cnt                        360                       # FU busy when requested
+system.cpu3.iq.fu_busy_rate                  0.001779                       # FU busy rate (busy events/executed inst)
+system.cpu3.iq.int_inst_queue_reads            571177                       # Number of integer instruction queue reads
+system.cpu3.iq.int_inst_queue_writes           220229                       # Number of integer instruction queue writes
+system.cpu3.iq.int_inst_queue_wakeup_accesses       200600                       # Number of integer instruction queue wakeup accesses
 system.cpu3.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
 system.cpu3.iq.fp_inst_queue_writes                 0                       # Number of floating instruction queue writes
 system.cpu3.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
-system.cpu3.iq.int_alu_accesses                212429                       # Number of integer alu accesses
+system.cpu3.iq.int_alu_accesses                202668                       # Number of integer alu accesses
 system.cpu3.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
-system.cpu3.iew.lsq.thread0.forwLoads           26730                       # Number of loads that had data forwarded from stores
+system.cpu3.iew.lsq.thread0.forwLoads           24749                       # Number of loads that had data forwarded from stores
 system.cpu3.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu3.iew.lsq.thread0.squashedLoads         2459                       # Number of loads squashed
+system.cpu3.iew.lsq.thread0.squashedLoads         2800                       # Number of loads squashed
 system.cpu3.iew.lsq.thread0.ignoredResponses            3                       # Number of memory responses ignored because the instruction is squashed
-system.cpu3.iew.lsq.thread0.memOrderViolation           46                       # Number of memory ordering violations
-system.cpu3.iew.lsq.thread0.squashedStores         1447                       # Number of stores squashed
+system.cpu3.iew.lsq.thread0.memOrderViolation           40                       # Number of memory ordering violations
+system.cpu3.iew.lsq.thread0.squashedStores         1627                       # Number of stores squashed
 system.cpu3.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu3.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu3.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
 system.cpu3.iew.lsq.thread0.cacheBlocked            0                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu3.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu3.iew.iewSquashCycles                  2374                       # Number of cycles IEW is squashing
-system.cpu3.iew.iewBlockCycles                    705                       # Number of cycles IEW is blocking
-system.cpu3.iew.iewUnblockCycles                   44                       # Number of cycles IEW is unblocking
-system.cpu3.iew.iewDispatchedInsts             251552                       # Number of instructions dispatched to IQ
-system.cpu3.iew.iewDispSquashedInsts              401                       # Number of squashed instructions skipped by dispatch
-system.cpu3.iew.iewDispLoadInsts                69948                       # Number of dispatched load instructions
-system.cpu3.iew.iewDispStoreInsts               32037                       # Number of dispatched store instructions
-system.cpu3.iew.iewDispNonSpecInsts              1046                       # Number of dispatched non-speculative instructions
-system.cpu3.iew.iewIQFullEvents                    44                       # Number of times the IQ has become full, causing a stall
+system.cpu3.iew.iewSquashCycles                  1363                       # Number of cycles IEW is squashing
+system.cpu3.iew.iewBlockCycles                   8604                       # Number of cycles IEW is blocking
+system.cpu3.iew.iewUnblockCycles                   61                       # Number of cycles IEW is unblocking
+system.cpu3.iew.iewDispatchedInsts             240098                       # Number of instructions dispatched to IQ
+system.cpu3.iew.iewDispSquashedInsts              201                       # Number of squashed instructions skipped by dispatch
+system.cpu3.iew.iewDispLoadInsts                65863                       # Number of dispatched load instructions
+system.cpu3.iew.iewDispStoreInsts               30140                       # Number of dispatched store instructions
+system.cpu3.iew.iewDispNonSpecInsts              1100                       # Number of dispatched non-speculative instructions
+system.cpu3.iew.iewIQFullEvents                    33                       # Number of times the IQ has become full, causing a stall
 system.cpu3.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
-system.cpu3.iew.memOrderViolationEvents            46                       # Number of memory order violations
-system.cpu3.iew.predictedTakenIncorrect           464                       # Number of branches that were predicted taken incorrectly
-system.cpu3.iew.predictedNotTakenIncorrect          910                       # Number of branches that were predicted not taken incorrectly
-system.cpu3.iew.branchMispredicts                1374                       # Number of branch mispredicts detected at execute
-system.cpu3.iew.iewExecutedInsts               210966                       # Number of executed instructions
-system.cpu3.iew.iewExecLoadInsts                68906                       # Number of load instructions executed
-system.cpu3.iew.iewExecSquashedInsts             1193                       # Number of squashed instructions skipped in execute
+system.cpu3.iew.memOrderViolationEvents            40                       # Number of memory order violations
+system.cpu3.iew.predictedTakenIncorrect           473                       # Number of branches that were predicted taken incorrectly
+system.cpu3.iew.predictedNotTakenIncorrect         1038                       # Number of branches that were predicted not taken incorrectly
+system.cpu3.iew.branchMispredicts                1511                       # Number of branch mispredicts detected at execute
+system.cpu3.iew.iewExecutedInsts               201185                       # Number of executed instructions
+system.cpu3.iew.iewExecLoadInsts                64698                       # Number of load instructions executed
+system.cpu3.iew.iewExecSquashedInsts             1123                       # Number of squashed instructions skipped in execute
 system.cpu3.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu3.iew.exec_nop                        34992                       # number of nop insts executed
-system.cpu3.iew.exec_refs                      100151                       # number of memory reference insts executed
-system.cpu3.iew.exec_branches                   44184                       # Number of branches executed
-system.cpu3.iew.exec_stores                     31245                       # Number of stores executed
-system.cpu3.iew.exec_rate                    1.191306                       # Inst execution rate
-system.cpu3.iew.wb_sent                        210604                       # cumulative count of insts sent to commit
-system.cpu3.iew.wb_count                       210302                       # cumulative count of insts written-back
-system.cpu3.iew.wb_producers                   116846                       # num instructions producing a value
-system.cpu3.iew.wb_consumers                   121503                       # num instructions consuming a value
+system.cpu3.iew.exec_nop                        32768                       # number of nop insts executed
+system.cpu3.iew.exec_refs                       94032                       # number of memory reference insts executed
+system.cpu3.iew.exec_branches                   42068                       # Number of branches executed
+system.cpu3.iew.exec_stores                     29334                       # Number of stores executed
+system.cpu3.iew.exec_rate                    1.202734                       # Inst execution rate
+system.cpu3.iew.wb_sent                        200904                       # cumulative count of insts sent to commit
+system.cpu3.iew.wb_count                       200600                       # cumulative count of insts written-back
+system.cpu3.iew.wb_producers                   111689                       # num instructions producing a value
+system.cpu3.iew.wb_consumers                   118263                       # num instructions consuming a value
 system.cpu3.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu3.iew.wb_rate                      1.187556                       # insts written-back per cycle
-system.cpu3.iew.wb_fanout                    0.961672                       # average fanout of values written-back
+system.cpu3.iew.wb_rate                      1.199237                       # insts written-back per cycle
+system.cpu3.iew.wb_fanout                    0.944412                       # average fanout of values written-back
 system.cpu3.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu3.commit.commitSquashedInsts          12453                       # The number of squashed insts skipped by commit
-system.cpu3.commit.commitNonSpecStalls           7553                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu3.commit.branchMispredicts             1269                       # The number of times a branch was mispredicted
-system.cpu3.commit.committed_per_cycle::samples       165461                       # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::mean     1.444927                       # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::stdev     1.940782                       # Number of insts commited each cycle
+system.cpu3.commit.commitSquashedInsts          14520                       # The number of squashed insts skipped by commit
+system.cpu3.commit.commitNonSpecStalls           7275                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu3.commit.branchMispredicts             1287                       # The number of times a branch was mispredicted
+system.cpu3.commit.committed_per_cycle::samples       156480                       # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::mean     1.441238                       # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::stdev     1.976154                       # Number of insts commited each cycle
 system.cpu3.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::0        77418     46.79%     46.79% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::1        42307     25.57%     72.36% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::2         6087      3.68%     76.04% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::3         8486      5.13%     81.17% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::4         1577      0.95%     82.12% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::5        27301     16.50%     98.62% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::6          474      0.29%     98.91% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::7         1005      0.61%     99.51% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::8          806      0.49%    100.00% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::0        74989     47.92%     47.92% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::1        38816     24.81%     72.73% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::2         5199      3.32%     76.05% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::3         8093      5.17%     81.22% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::4         1536      0.98%     82.20% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::5        24757     15.82%     98.03% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::6          830      0.53%     98.56% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::7          957      0.61%     99.17% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::8         1303      0.83%    100.00% # Number of insts commited each cycle
 system.cpu3.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu3.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu3.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::total       165461                       # Number of insts commited each cycle
-system.cpu3.commit.committedInsts              239079                       # Number of instructions committed
-system.cpu3.commit.committedOps                239079                       # Number of ops (including micro ops) committed
+system.cpu3.commit.committed_per_cycle::total       156480                       # Number of insts commited each cycle
+system.cpu3.commit.committedInsts              225525                       # Number of instructions committed
+system.cpu3.commit.committedOps                225525                       # Number of ops (including micro ops) committed
 system.cpu3.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu3.commit.refs                         98079                       # Number of memory references committed
-system.cpu3.commit.loads                        67489                       # Number of loads committed
-system.cpu3.commit.membars                       6836                       # Number of memory barriers committed
-system.cpu3.commit.branches                     43385                       # Number of branches committed
+system.cpu3.commit.refs                         91576                       # Number of memory references committed
+system.cpu3.commit.loads                        63063                       # Number of loads committed
+system.cpu3.commit.membars                       6559                       # Number of memory barriers committed
+system.cpu3.commit.branches                     41035                       # Number of branches committed
 system.cpu3.commit.fp_insts                         0                       # Number of committed floating point instructions.
-system.cpu3.commit.int_insts                   163585                       # Number of committed integer instructions.
+system.cpu3.commit.int_insts                   154730                       # Number of committed integer instructions.
 system.cpu3.commit.function_calls                 322                       # Number of function calls committed.
-system.cpu3.commit.op_class_0::No_OpClass        34172     14.29%     14.29% # Class of committed instruction
-system.cpu3.commit.op_class_0::IntAlu           99992     41.82%     56.12% # Class of committed instruction
-system.cpu3.commit.op_class_0::IntMult              0      0.00%     56.12% # Class of committed instruction
-system.cpu3.commit.op_class_0::IntDiv               0      0.00%     56.12% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatAdd             0      0.00%     56.12% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatCmp             0      0.00%     56.12% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatCvt             0      0.00%     56.12% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatMult            0      0.00%     56.12% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatDiv             0      0.00%     56.12% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatSqrt            0      0.00%     56.12% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdAdd              0      0.00%     56.12% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdAddAcc            0      0.00%     56.12% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdAlu              0      0.00%     56.12% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdCmp              0      0.00%     56.12% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdCvt              0      0.00%     56.12% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdMisc             0      0.00%     56.12% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdMult             0      0.00%     56.12% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdMultAcc            0      0.00%     56.12% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdShift            0      0.00%     56.12% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdShiftAcc            0      0.00%     56.12% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdSqrt             0      0.00%     56.12% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatAdd            0      0.00%     56.12% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatAlu            0      0.00%     56.12% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatCmp            0      0.00%     56.12% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatCvt            0      0.00%     56.12% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatDiv            0      0.00%     56.12% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatMisc            0      0.00%     56.12% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatMult            0      0.00%     56.12% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatMultAcc            0      0.00%     56.12% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatSqrt            0      0.00%     56.12% # Class of committed instruction
-system.cpu3.commit.op_class_0::MemRead          74325     31.09%     87.21% # Class of committed instruction
-system.cpu3.commit.op_class_0::MemWrite         30590     12.79%    100.00% # Class of committed instruction
+system.cpu3.commit.op_class_0::No_OpClass        31823     14.11%     14.11% # Class of committed instruction
+system.cpu3.commit.op_class_0::IntAlu           95567     42.38%     56.49% # Class of committed instruction
+system.cpu3.commit.op_class_0::IntMult              0      0.00%     56.49% # Class of committed instruction
+system.cpu3.commit.op_class_0::IntDiv               0      0.00%     56.49% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatAdd             0      0.00%     56.49% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatCmp             0      0.00%     56.49% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatCvt             0      0.00%     56.49% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatMult            0      0.00%     56.49% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatDiv             0      0.00%     56.49% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatSqrt            0      0.00%     56.49% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdAdd              0      0.00%     56.49% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdAddAcc            0      0.00%     56.49% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdAlu              0      0.00%     56.49% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdCmp              0      0.00%     56.49% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdCvt              0      0.00%     56.49% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdMisc             0      0.00%     56.49% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdMult             0      0.00%     56.49% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdMultAcc            0      0.00%     56.49% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdShift            0      0.00%     56.49% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdShiftAcc            0      0.00%     56.49% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdSqrt             0      0.00%     56.49% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatAdd            0      0.00%     56.49% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatAlu            0      0.00%     56.49% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatCmp            0      0.00%     56.49% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatCvt            0      0.00%     56.49% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatDiv            0      0.00%     56.49% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatMisc            0      0.00%     56.49% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatMult            0      0.00%     56.49% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatMultAcc            0      0.00%     56.49% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatSqrt            0      0.00%     56.49% # Class of committed instruction
+system.cpu3.commit.op_class_0::MemRead          69622     30.87%     87.36% # Class of committed instruction
+system.cpu3.commit.op_class_0::MemWrite         28513     12.64%    100.00% # Class of committed instruction
 system.cpu3.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu3.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu3.commit.op_class_0::total           239079                       # Class of committed instruction
-system.cpu3.commit.bw_lim_events                  806                       # number cycles where commit BW limit reached
+system.cpu3.commit.op_class_0::total           225525                       # Class of committed instruction
+system.cpu3.commit.bw_lim_events                 1303                       # number cycles where commit BW limit reached
 system.cpu3.commit.bw_limited                       0                       # number of insts not committed due to BW limits
-system.cpu3.rob.rob_reads                      415600                       # The number of ROB reads
-system.cpu3.rob.rob_writes                     505444                       # The number of ROB writes
-system.cpu3.timesIdled                            214                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu3.idleCycles                           1450                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu3.quiesceCycles                       44852                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu3.committedInsts                     198071                       # Number of Instructions Simulated
-system.cpu3.committedOps                       198071                       # Number of Ops (including micro ops) Simulated
-system.cpu3.cpi                              0.894063                       # CPI: Cycles Per Instruction
-system.cpu3.cpi_total                        0.894063                       # CPI: Total CPI of All Threads
-system.cpu3.ipc                              1.118489                       # IPC: Instructions Per Cycle
-system.cpu3.ipc_total                        1.118489                       # IPC: Total IPC of All Threads
-system.cpu3.int_regfile_reads                  358875                       # number of integer regfile reads
-system.cpu3.int_regfile_writes                 168004                       # number of integer regfile writes
+system.cpu3.rob.rob_reads                      394635                       # The number of ROB reads
+system.cpu3.rob.rob_writes                     482728                       # The number of ROB writes
+system.cpu3.timesIdled                            203                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu3.idleCycles                           1105                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu3.quiesceCycles                       44004                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu3.committedInsts                     187143                       # Number of Instructions Simulated
+system.cpu3.committedOps                       187143                       # Number of Ops (including micro ops) Simulated
+system.cpu3.cpi                              0.893825                       # CPI: Cycles Per Instruction
+system.cpu3.cpi_total                        0.893825                       # CPI: Total CPI of All Threads
+system.cpu3.ipc                              1.118788                       # IPC: Instructions Per Cycle
+system.cpu3.ipc_total                        1.118788                       # IPC: Total IPC of All Threads
+system.cpu3.int_regfile_reads                  341840                       # number of integer regfile reads
+system.cpu3.int_regfile_writes                 160726                       # number of integer regfile writes
 system.cpu3.fp_regfile_writes                      64                       # number of floating regfile writes
-system.cpu3.misc_regfile_reads                 101700                       # number of misc regfile reads
+system.cpu3.misc_regfile_reads                  95629                       # number of misc regfile reads
 system.cpu3.misc_regfile_writes                   648                       # number of misc regfile writes
-system.cpu3.icache.tags.replacements              319                       # number of replacements
-system.cpu3.icache.tags.tagsinuse           77.082229                       # Cycle average of tags in use
-system.cpu3.icache.tags.total_refs              22869                       # Total number of references to valid blocks.
-system.cpu3.icache.tags.sampled_refs              430                       # Sample count of references to valid blocks.
-system.cpu3.icache.tags.avg_refs            53.183721                       # Average number of references to valid blocks.
+system.cpu3.icache.tags.replacements              380                       # number of replacements
+system.cpu3.icache.tags.tagsinuse           77.789470                       # Cycle average of tags in use
+system.cpu3.icache.tags.total_refs              24352                       # Total number of references to valid blocks.
+system.cpu3.icache.tags.sampled_refs              493                       # Sample count of references to valid blocks.
+system.cpu3.icache.tags.avg_refs            49.395538                       # Average number of references to valid blocks.
 system.cpu3.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu3.icache.tags.occ_blocks::cpu3.inst    77.082229                       # Average occupied blocks per requestor
-system.cpu3.icache.tags.occ_percent::cpu3.inst     0.150551                       # Average percentage of cache occupancy
-system.cpu3.icache.tags.occ_percent::total     0.150551                       # Average percentage of cache occupancy
-system.cpu3.icache.tags.occ_task_id_blocks::1024          111                       # Occupied blocks per task id
+system.cpu3.icache.tags.occ_blocks::cpu3.inst    77.789470                       # Average occupied blocks per requestor
+system.cpu3.icache.tags.occ_percent::cpu3.inst     0.151933                       # Average percentage of cache occupancy
+system.cpu3.icache.tags.occ_percent::total     0.151933                       # Average percentage of cache occupancy
+system.cpu3.icache.tags.occ_task_id_blocks::1024          113                       # Occupied blocks per task id
 system.cpu3.icache.tags.age_task_id_blocks_1024::0           11                       # Occupied blocks per task id
-system.cpu3.icache.tags.age_task_id_blocks_1024::1          100                       # Occupied blocks per task id
-system.cpu3.icache.tags.occ_task_id_percent::1024     0.216797                       # Percentage of cache occupancy per task id
-system.cpu3.icache.tags.tag_accesses            23774                       # Number of tag accesses
-system.cpu3.icache.tags.data_accesses           23774                       # Number of data accesses
-system.cpu3.icache.ReadReq_hits::cpu3.inst        22869                       # number of ReadReq hits
-system.cpu3.icache.ReadReq_hits::total          22869                       # number of ReadReq hits
-system.cpu3.icache.demand_hits::cpu3.inst        22869                       # number of demand (read+write) hits
-system.cpu3.icache.demand_hits::total           22869                       # number of demand (read+write) hits
-system.cpu3.icache.overall_hits::cpu3.inst        22869                       # number of overall hits
-system.cpu3.icache.overall_hits::total          22869                       # number of overall hits
-system.cpu3.icache.ReadReq_misses::cpu3.inst          475                       # number of ReadReq misses
-system.cpu3.icache.ReadReq_misses::total          475                       # number of ReadReq misses
-system.cpu3.icache.demand_misses::cpu3.inst          475                       # number of demand (read+write) misses
-system.cpu3.icache.demand_misses::total           475                       # number of demand (read+write) misses
-system.cpu3.icache.overall_misses::cpu3.inst          475                       # number of overall misses
-system.cpu3.icache.overall_misses::total          475                       # number of overall misses
-system.cpu3.icache.ReadReq_miss_latency::cpu3.inst      6365994                       # number of ReadReq miss cycles
-system.cpu3.icache.ReadReq_miss_latency::total      6365994                       # number of ReadReq miss cycles
-system.cpu3.icache.demand_miss_latency::cpu3.inst      6365994                       # number of demand (read+write) miss cycles
-system.cpu3.icache.demand_miss_latency::total      6365994                       # number of demand (read+write) miss cycles
-system.cpu3.icache.overall_miss_latency::cpu3.inst      6365994                       # number of overall miss cycles
-system.cpu3.icache.overall_miss_latency::total      6365994                       # number of overall miss cycles
-system.cpu3.icache.ReadReq_accesses::cpu3.inst        23344                       # number of ReadReq accesses(hits+misses)
-system.cpu3.icache.ReadReq_accesses::total        23344                       # number of ReadReq accesses(hits+misses)
-system.cpu3.icache.demand_accesses::cpu3.inst        23344                       # number of demand (read+write) accesses
-system.cpu3.icache.demand_accesses::total        23344                       # number of demand (read+write) accesses
-system.cpu3.icache.overall_accesses::cpu3.inst        23344                       # number of overall (read+write) accesses
-system.cpu3.icache.overall_accesses::total        23344                       # number of overall (read+write) accesses
-system.cpu3.icache.ReadReq_miss_rate::cpu3.inst     0.020348                       # miss rate for ReadReq accesses
-system.cpu3.icache.ReadReq_miss_rate::total     0.020348                       # miss rate for ReadReq accesses
-system.cpu3.icache.demand_miss_rate::cpu3.inst     0.020348                       # miss rate for demand accesses
-system.cpu3.icache.demand_miss_rate::total     0.020348                       # miss rate for demand accesses
-system.cpu3.icache.overall_miss_rate::cpu3.inst     0.020348                       # miss rate for overall accesses
-system.cpu3.icache.overall_miss_rate::total     0.020348                       # miss rate for overall accesses
-system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13402.092632                       # average ReadReq miss latency
-system.cpu3.icache.ReadReq_avg_miss_latency::total 13402.092632                       # average ReadReq miss latency
-system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13402.092632                       # average overall miss latency
-system.cpu3.icache.demand_avg_miss_latency::total 13402.092632                       # average overall miss latency
-system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13402.092632                       # average overall miss latency
-system.cpu3.icache.overall_avg_miss_latency::total 13402.092632                       # average overall miss latency
+system.cpu3.icache.tags.age_task_id_blocks_1024::1          102                       # Occupied blocks per task id
+system.cpu3.icache.tags.occ_task_id_percent::1024     0.220703                       # Percentage of cache occupancy per task id
+system.cpu3.icache.tags.tag_accesses            25400                       # Number of tag accesses
+system.cpu3.icache.tags.data_accesses           25400                       # Number of data accesses
+system.cpu3.icache.ReadReq_hits::cpu3.inst        24352                       # number of ReadReq hits
+system.cpu3.icache.ReadReq_hits::total          24352                       # number of ReadReq hits
+system.cpu3.icache.demand_hits::cpu3.inst        24352                       # number of demand (read+write) hits
+system.cpu3.icache.demand_hits::total           24352                       # number of demand (read+write) hits
+system.cpu3.icache.overall_hits::cpu3.inst        24352                       # number of overall hits
+system.cpu3.icache.overall_hits::total          24352                       # number of overall hits
+system.cpu3.icache.ReadReq_misses::cpu3.inst          555                       # number of ReadReq misses
+system.cpu3.icache.ReadReq_misses::total          555                       # number of ReadReq misses
+system.cpu3.icache.demand_misses::cpu3.inst          555                       # number of demand (read+write) misses
+system.cpu3.icache.demand_misses::total           555                       # number of demand (read+write) misses
+system.cpu3.icache.overall_misses::cpu3.inst          555                       # number of overall misses
+system.cpu3.icache.overall_misses::total          555                       # number of overall misses
+system.cpu3.icache.ReadReq_miss_latency::cpu3.inst      7324995                       # number of ReadReq miss cycles
+system.cpu3.icache.ReadReq_miss_latency::total      7324995                       # number of ReadReq miss cycles
+system.cpu3.icache.demand_miss_latency::cpu3.inst      7324995                       # number of demand (read+write) miss cycles
+system.cpu3.icache.demand_miss_latency::total      7324995                       # number of demand (read+write) miss cycles
+system.cpu3.icache.overall_miss_latency::cpu3.inst      7324995                       # number of overall miss cycles
+system.cpu3.icache.overall_miss_latency::total      7324995                       # number of overall miss cycles
+system.cpu3.icache.ReadReq_accesses::cpu3.inst        24907                       # number of ReadReq accesses(hits+misses)
+system.cpu3.icache.ReadReq_accesses::total        24907                       # number of ReadReq accesses(hits+misses)
+system.cpu3.icache.demand_accesses::cpu3.inst        24907                       # number of demand (read+write) accesses
+system.cpu3.icache.demand_accesses::total        24907                       # number of demand (read+write) accesses
+system.cpu3.icache.overall_accesses::cpu3.inst        24907                       # number of overall (read+write) accesses
+system.cpu3.icache.overall_accesses::total        24907                       # number of overall (read+write) accesses
+system.cpu3.icache.ReadReq_miss_rate::cpu3.inst     0.022283                       # miss rate for ReadReq accesses
+system.cpu3.icache.ReadReq_miss_rate::total     0.022283                       # miss rate for ReadReq accesses
+system.cpu3.icache.demand_miss_rate::cpu3.inst     0.022283                       # miss rate for demand accesses
+system.cpu3.icache.demand_miss_rate::total     0.022283                       # miss rate for demand accesses
+system.cpu3.icache.overall_miss_rate::cpu3.inst     0.022283                       # miss rate for overall accesses
+system.cpu3.icache.overall_miss_rate::total     0.022283                       # miss rate for overall accesses
+system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13198.189189                       # average ReadReq miss latency
+system.cpu3.icache.ReadReq_avg_miss_latency::total 13198.189189                       # average ReadReq miss latency
+system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13198.189189                       # average overall miss latency
+system.cpu3.icache.demand_avg_miss_latency::total 13198.189189                       # average overall miss latency
+system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13198.189189                       # average overall miss latency
+system.cpu3.icache.overall_avg_miss_latency::total 13198.189189                       # average overall miss latency
 system.cpu3.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu3.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu3.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -2651,112 +2657,111 @@ system.cpu3.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu3.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu3.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu3.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst           45                       # number of ReadReq MSHR hits
-system.cpu3.icache.ReadReq_mshr_hits::total           45                       # number of ReadReq MSHR hits
-system.cpu3.icache.demand_mshr_hits::cpu3.inst           45                       # number of demand (read+write) MSHR hits
-system.cpu3.icache.demand_mshr_hits::total           45                       # number of demand (read+write) MSHR hits
-system.cpu3.icache.overall_mshr_hits::cpu3.inst           45                       # number of overall MSHR hits
-system.cpu3.icache.overall_mshr_hits::total           45                       # number of overall MSHR hits
-system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst          430                       # number of ReadReq MSHR misses
-system.cpu3.icache.ReadReq_mshr_misses::total          430                       # number of ReadReq MSHR misses
-system.cpu3.icache.demand_mshr_misses::cpu3.inst          430                       # number of demand (read+write) MSHR misses
-system.cpu3.icache.demand_mshr_misses::total          430                       # number of demand (read+write) MSHR misses
-system.cpu3.icache.overall_mshr_misses::cpu3.inst          430                       # number of overall MSHR misses
-system.cpu3.icache.overall_mshr_misses::total          430                       # number of overall MSHR misses
-system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst      5107006                       # number of ReadReq MSHR miss cycles
-system.cpu3.icache.ReadReq_mshr_miss_latency::total      5107006                       # number of ReadReq MSHR miss cycles
-system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst      5107006                       # number of demand (read+write) MSHR miss cycles
-system.cpu3.icache.demand_mshr_miss_latency::total      5107006                       # number of demand (read+write) MSHR miss cycles
-system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst      5107006                       # number of overall MSHR miss cycles
-system.cpu3.icache.overall_mshr_miss_latency::total      5107006                       # number of overall MSHR miss cycles
-system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst     0.018420                       # mshr miss rate for ReadReq accesses
-system.cpu3.icache.ReadReq_mshr_miss_rate::total     0.018420                       # mshr miss rate for ReadReq accesses
-system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst     0.018420                       # mshr miss rate for demand accesses
-system.cpu3.icache.demand_mshr_miss_rate::total     0.018420                       # mshr miss rate for demand accesses
-system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst     0.018420                       # mshr miss rate for overall accesses
-system.cpu3.icache.overall_mshr_miss_rate::total     0.018420                       # mshr miss rate for overall accesses
-system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 11876.758140                       # average ReadReq mshr miss latency
-system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 11876.758140                       # average ReadReq mshr miss latency
-system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 11876.758140                       # average overall mshr miss latency
-system.cpu3.icache.demand_avg_mshr_miss_latency::total 11876.758140                       # average overall mshr miss latency
-system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 11876.758140                       # average overall mshr miss latency
-system.cpu3.icache.overall_avg_mshr_miss_latency::total 11876.758140                       # average overall mshr miss latency
+system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst           62                       # number of ReadReq MSHR hits
+system.cpu3.icache.ReadReq_mshr_hits::total           62                       # number of ReadReq MSHR hits
+system.cpu3.icache.demand_mshr_hits::cpu3.inst           62                       # number of demand (read+write) MSHR hits
+system.cpu3.icache.demand_mshr_hits::total           62                       # number of demand (read+write) MSHR hits
+system.cpu3.icache.overall_mshr_hits::cpu3.inst           62                       # number of overall MSHR hits
+system.cpu3.icache.overall_mshr_hits::total           62                       # number of overall MSHR hits
+system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst          493                       # number of ReadReq MSHR misses
+system.cpu3.icache.ReadReq_mshr_misses::total          493                       # number of ReadReq MSHR misses
+system.cpu3.icache.demand_mshr_misses::cpu3.inst          493                       # number of demand (read+write) MSHR misses
+system.cpu3.icache.demand_mshr_misses::total          493                       # number of demand (read+write) MSHR misses
+system.cpu3.icache.overall_mshr_misses::cpu3.inst          493                       # number of overall MSHR misses
+system.cpu3.icache.overall_mshr_misses::total          493                       # number of overall MSHR misses
+system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst      5824754                       # number of ReadReq MSHR miss cycles
+system.cpu3.icache.ReadReq_mshr_miss_latency::total      5824754                       # number of ReadReq MSHR miss cycles
+system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst      5824754                       # number of demand (read+write) MSHR miss cycles
+system.cpu3.icache.demand_mshr_miss_latency::total      5824754                       # number of demand (read+write) MSHR miss cycles
+system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst      5824754                       # number of overall MSHR miss cycles
+system.cpu3.icache.overall_mshr_miss_latency::total      5824754                       # number of overall MSHR miss cycles
+system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst     0.019794                       # mshr miss rate for ReadReq accesses
+system.cpu3.icache.ReadReq_mshr_miss_rate::total     0.019794                       # mshr miss rate for ReadReq accesses
+system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst     0.019794                       # mshr miss rate for demand accesses
+system.cpu3.icache.demand_mshr_miss_rate::total     0.019794                       # mshr miss rate for demand accesses
+system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst     0.019794                       # mshr miss rate for overall accesses
+system.cpu3.icache.overall_mshr_miss_rate::total     0.019794                       # mshr miss rate for overall accesses
+system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 11814.916836                       # average ReadReq mshr miss latency
+system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 11814.916836                       # average ReadReq mshr miss latency
+system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 11814.916836                       # average overall mshr miss latency
+system.cpu3.icache.demand_avg_mshr_miss_latency::total 11814.916836                       # average overall mshr miss latency
+system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 11814.916836                       # average overall mshr miss latency
+system.cpu3.icache.overall_avg_mshr_miss_latency::total 11814.916836                       # average overall mshr miss latency
 system.cpu3.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu3.dcache.tags.replacements                0                       # number of replacements
-system.cpu3.dcache.tags.tagsinuse           23.636588                       # Cycle average of tags in use
-system.cpu3.dcache.tags.total_refs              36715                       # Total number of references to valid blocks.
-system.cpu3.dcache.tags.sampled_refs               29                       # Sample count of references to valid blocks.
-system.cpu3.dcache.tags.avg_refs          1266.034483                       # Average number of references to valid blocks.
+system.cpu3.dcache.tags.tagsinuse           23.433083                       # Cycle average of tags in use
+system.cpu3.dcache.tags.total_refs              34557                       # Total number of references to valid blocks.
+system.cpu3.dcache.tags.sampled_refs               28                       # Sample count of references to valid blocks.
+system.cpu3.dcache.tags.avg_refs          1234.178571                       # Average number of references to valid blocks.
 system.cpu3.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu3.dcache.tags.occ_blocks::cpu3.data    23.636588                       # Average occupied blocks per requestor
-system.cpu3.dcache.tags.occ_percent::cpu3.data     0.046165                       # Average percentage of cache occupancy
-system.cpu3.dcache.tags.occ_percent::total     0.046165                       # Average percentage of cache occupancy
-system.cpu3.dcache.tags.occ_task_id_blocks::1024           29                       # Occupied blocks per task id
-system.cpu3.dcache.tags.age_task_id_blocks_1024::0            1                       # Occupied blocks per task id
+system.cpu3.dcache.tags.occ_blocks::cpu3.data    23.433083                       # Average occupied blocks per requestor
+system.cpu3.dcache.tags.occ_percent::cpu3.data     0.045768                       # Average percentage of cache occupancy
+system.cpu3.dcache.tags.occ_percent::total     0.045768                       # Average percentage of cache occupancy
+system.cpu3.dcache.tags.occ_task_id_blocks::1024           28                       # Occupied blocks per task id
 system.cpu3.dcache.tags.age_task_id_blocks_1024::1           28                       # Occupied blocks per task id
-system.cpu3.dcache.tags.occ_task_id_percent::1024     0.056641                       # Percentage of cache occupancy per task id
-system.cpu3.dcache.tags.tag_accesses           291244                       # Number of tag accesses
-system.cpu3.dcache.tags.data_accesses          291244                       # Number of data accesses
-system.cpu3.dcache.ReadReq_hits::cpu3.data        41825                       # number of ReadReq hits
-system.cpu3.dcache.ReadReq_hits::total          41825                       # number of ReadReq hits
-system.cpu3.dcache.WriteReq_hits::cpu3.data        30388                       # number of WriteReq hits
-system.cpu3.dcache.WriteReq_hits::total         30388                       # number of WriteReq hits
-system.cpu3.dcache.SwapReq_hits::cpu3.data           15                       # number of SwapReq hits
-system.cpu3.dcache.SwapReq_hits::total             15                       # number of SwapReq hits
-system.cpu3.dcache.demand_hits::cpu3.data        72213                       # number of demand (read+write) hits
-system.cpu3.dcache.demand_hits::total           72213                       # number of demand (read+write) hits
-system.cpu3.dcache.overall_hits::cpu3.data        72213                       # number of overall hits
-system.cpu3.dcache.overall_hits::total          72213                       # number of overall hits
-system.cpu3.dcache.ReadReq_misses::cpu3.data          334                       # number of ReadReq misses
-system.cpu3.dcache.ReadReq_misses::total          334                       # number of ReadReq misses
-system.cpu3.dcache.WriteReq_misses::cpu3.data          131                       # number of WriteReq misses
-system.cpu3.dcache.WriteReq_misses::total          131                       # number of WriteReq misses
-system.cpu3.dcache.SwapReq_misses::cpu3.data           56                       # number of SwapReq misses
-system.cpu3.dcache.SwapReq_misses::total           56                       # number of SwapReq misses
-system.cpu3.dcache.demand_misses::cpu3.data          465                       # number of demand (read+write) misses
-system.cpu3.dcache.demand_misses::total           465                       # number of demand (read+write) misses
-system.cpu3.dcache.overall_misses::cpu3.data          465                       # number of overall misses
-system.cpu3.dcache.overall_misses::total          465                       # number of overall misses
-system.cpu3.dcache.ReadReq_miss_latency::cpu3.data      4213650                       # number of ReadReq miss cycles
-system.cpu3.dcache.ReadReq_miss_latency::total      4213650                       # number of ReadReq miss cycles
-system.cpu3.dcache.WriteReq_miss_latency::cpu3.data      2829011                       # number of WriteReq miss cycles
-system.cpu3.dcache.WriteReq_miss_latency::total      2829011                       # number of WriteReq miss cycles
-system.cpu3.dcache.SwapReq_miss_latency::cpu3.data       511006                       # number of SwapReq miss cycles
-system.cpu3.dcache.SwapReq_miss_latency::total       511006                       # number of SwapReq miss cycles
-system.cpu3.dcache.demand_miss_latency::cpu3.data      7042661                       # number of demand (read+write) miss cycles
-system.cpu3.dcache.demand_miss_latency::total      7042661                       # number of demand (read+write) miss cycles
-system.cpu3.dcache.overall_miss_latency::cpu3.data      7042661                       # number of overall miss cycles
-system.cpu3.dcache.overall_miss_latency::total      7042661                       # number of overall miss cycles
-system.cpu3.dcache.ReadReq_accesses::cpu3.data        42159                       # number of ReadReq accesses(hits+misses)
-system.cpu3.dcache.ReadReq_accesses::total        42159                       # number of ReadReq accesses(hits+misses)
-system.cpu3.dcache.WriteReq_accesses::cpu3.data        30519                       # number of WriteReq accesses(hits+misses)
-system.cpu3.dcache.WriteReq_accesses::total        30519                       # number of WriteReq accesses(hits+misses)
-system.cpu3.dcache.SwapReq_accesses::cpu3.data           71                       # number of SwapReq accesses(hits+misses)
-system.cpu3.dcache.SwapReq_accesses::total           71                       # number of SwapReq accesses(hits+misses)
-system.cpu3.dcache.demand_accesses::cpu3.data        72678                       # number of demand (read+write) accesses
-system.cpu3.dcache.demand_accesses::total        72678                       # number of demand (read+write) accesses
-system.cpu3.dcache.overall_accesses::cpu3.data        72678                       # number of overall (read+write) accesses
-system.cpu3.dcache.overall_accesses::total        72678                       # number of overall (read+write) accesses
-system.cpu3.dcache.ReadReq_miss_rate::cpu3.data     0.007922                       # miss rate for ReadReq accesses
-system.cpu3.dcache.ReadReq_miss_rate::total     0.007922                       # miss rate for ReadReq accesses
-system.cpu3.dcache.WriteReq_miss_rate::cpu3.data     0.004292                       # miss rate for WriteReq accesses
-system.cpu3.dcache.WriteReq_miss_rate::total     0.004292                       # miss rate for WriteReq accesses
-system.cpu3.dcache.SwapReq_miss_rate::cpu3.data     0.788732                       # miss rate for SwapReq accesses
-system.cpu3.dcache.SwapReq_miss_rate::total     0.788732                       # miss rate for SwapReq accesses
-system.cpu3.dcache.demand_miss_rate::cpu3.data     0.006398                       # miss rate for demand accesses
-system.cpu3.dcache.demand_miss_rate::total     0.006398                       # miss rate for demand accesses
-system.cpu3.dcache.overall_miss_rate::cpu3.data     0.006398                       # miss rate for overall accesses
-system.cpu3.dcache.overall_miss_rate::total     0.006398                       # miss rate for overall accesses
-system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 12615.718563                       # average ReadReq miss latency
-system.cpu3.dcache.ReadReq_avg_miss_latency::total 12615.718563                       # average ReadReq miss latency
-system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 21595.503817                       # average WriteReq miss latency
-system.cpu3.dcache.WriteReq_avg_miss_latency::total 21595.503817                       # average WriteReq miss latency
-system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data  9125.107143                       # average SwapReq miss latency
-system.cpu3.dcache.SwapReq_avg_miss_latency::total  9125.107143                       # average SwapReq miss latency
-system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 15145.507527                       # average overall miss latency
-system.cpu3.dcache.demand_avg_miss_latency::total 15145.507527                       # average overall miss latency
-system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 15145.507527                       # average overall miss latency
-system.cpu3.dcache.overall_avg_miss_latency::total 15145.507527                       # average overall miss latency
+system.cpu3.dcache.tags.occ_task_id_percent::1024     0.054688                       # Percentage of cache occupancy per task id
+system.cpu3.dcache.tags.tag_accesses           274000                       # Number of tag accesses
+system.cpu3.dcache.tags.data_accesses          274000                       # Number of data accesses
+system.cpu3.dcache.ReadReq_hits::cpu3.data        39491                       # number of ReadReq hits
+system.cpu3.dcache.ReadReq_hits::total          39491                       # number of ReadReq hits
+system.cpu3.dcache.WriteReq_hits::cpu3.data        28303                       # number of WriteReq hits
+system.cpu3.dcache.WriteReq_hits::total         28303                       # number of WriteReq hits
+system.cpu3.dcache.SwapReq_hits::cpu3.data           13                       # number of SwapReq hits
+system.cpu3.dcache.SwapReq_hits::total             13                       # number of SwapReq hits
+system.cpu3.dcache.demand_hits::cpu3.data        67794                       # number of demand (read+write) hits
+system.cpu3.dcache.demand_hits::total           67794                       # number of demand (read+write) hits
+system.cpu3.dcache.overall_hits::cpu3.data        67794                       # number of overall hits
+system.cpu3.dcache.overall_hits::total          67794                       # number of overall hits
+system.cpu3.dcache.ReadReq_misses::cpu3.data          432                       # number of ReadReq misses
+system.cpu3.dcache.ReadReq_misses::total          432                       # number of ReadReq misses
+system.cpu3.dcache.WriteReq_misses::cpu3.data          140                       # number of WriteReq misses
+system.cpu3.dcache.WriteReq_misses::total          140                       # number of WriteReq misses
+system.cpu3.dcache.SwapReq_misses::cpu3.data           57                       # number of SwapReq misses
+system.cpu3.dcache.SwapReq_misses::total           57                       # number of SwapReq misses
+system.cpu3.dcache.demand_misses::cpu3.data          572                       # number of demand (read+write) misses
+system.cpu3.dcache.demand_misses::total           572                       # number of demand (read+write) misses
+system.cpu3.dcache.overall_misses::cpu3.data          572                       # number of overall misses
+system.cpu3.dcache.overall_misses::total          572                       # number of overall misses
+system.cpu3.dcache.ReadReq_miss_latency::cpu3.data      5736963                       # number of ReadReq miss cycles
+system.cpu3.dcache.ReadReq_miss_latency::total      5736963                       # number of ReadReq miss cycles
+system.cpu3.dcache.WriteReq_miss_latency::cpu3.data      2764512                       # number of WriteReq miss cycles
+system.cpu3.dcache.WriteReq_miss_latency::total      2764512                       # number of WriteReq miss cycles
+system.cpu3.dcache.SwapReq_miss_latency::cpu3.data       515508                       # number of SwapReq miss cycles
+system.cpu3.dcache.SwapReq_miss_latency::total       515508                       # number of SwapReq miss cycles
+system.cpu3.dcache.demand_miss_latency::cpu3.data      8501475                       # number of demand (read+write) miss cycles
+system.cpu3.dcache.demand_miss_latency::total      8501475                       # number of demand (read+write) miss cycles
+system.cpu3.dcache.overall_miss_latency::cpu3.data      8501475                       # number of overall miss cycles
+system.cpu3.dcache.overall_miss_latency::total      8501475                       # number of overall miss cycles
+system.cpu3.dcache.ReadReq_accesses::cpu3.data        39923                       # number of ReadReq accesses(hits+misses)
+system.cpu3.dcache.ReadReq_accesses::total        39923                       # number of ReadReq accesses(hits+misses)
+system.cpu3.dcache.WriteReq_accesses::cpu3.data        28443                       # number of WriteReq accesses(hits+misses)
+system.cpu3.dcache.WriteReq_accesses::total        28443                       # number of WriteReq accesses(hits+misses)
+system.cpu3.dcache.SwapReq_accesses::cpu3.data           70                       # number of SwapReq accesses(hits+misses)
+system.cpu3.dcache.SwapReq_accesses::total           70                       # number of SwapReq accesses(hits+misses)
+system.cpu3.dcache.demand_accesses::cpu3.data        68366                       # number of demand (read+write) accesses
+system.cpu3.dcache.demand_accesses::total        68366                       # number of demand (read+write) accesses
+system.cpu3.dcache.overall_accesses::cpu3.data        68366                       # number of overall (read+write) accesses
+system.cpu3.dcache.overall_accesses::total        68366                       # number of overall (read+write) accesses
+system.cpu3.dcache.ReadReq_miss_rate::cpu3.data     0.010821                       # miss rate for ReadReq accesses
+system.cpu3.dcache.ReadReq_miss_rate::total     0.010821                       # miss rate for ReadReq accesses
+system.cpu3.dcache.WriteReq_miss_rate::cpu3.data     0.004922                       # miss rate for WriteReq accesses
+system.cpu3.dcache.WriteReq_miss_rate::total     0.004922                       # miss rate for WriteReq accesses
+system.cpu3.dcache.SwapReq_miss_rate::cpu3.data     0.814286                       # miss rate for SwapReq accesses
+system.cpu3.dcache.SwapReq_miss_rate::total     0.814286                       # miss rate for SwapReq accesses
+system.cpu3.dcache.demand_miss_rate::cpu3.data     0.008367                       # miss rate for demand accesses
+system.cpu3.dcache.demand_miss_rate::total     0.008367                       # miss rate for demand accesses
+system.cpu3.dcache.overall_miss_rate::cpu3.data     0.008367                       # miss rate for overall accesses
+system.cpu3.dcache.overall_miss_rate::total     0.008367                       # miss rate for overall accesses
+system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 13280.006944                       # average ReadReq miss latency
+system.cpu3.dcache.ReadReq_avg_miss_latency::total 13280.006944                       # average ReadReq miss latency
+system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 19746.514286                       # average WriteReq miss latency
+system.cpu3.dcache.WriteReq_avg_miss_latency::total 19746.514286                       # average WriteReq miss latency
+system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data         9044                       # average SwapReq miss latency
+system.cpu3.dcache.SwapReq_avg_miss_latency::total         9044                       # average SwapReq miss latency
+system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 14862.718531                       # average overall miss latency
+system.cpu3.dcache.demand_avg_miss_latency::total 14862.718531                       # average overall miss latency
+system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 14862.718531                       # average overall miss latency
+system.cpu3.dcache.overall_avg_miss_latency::total 14862.718531                       # average overall miss latency
 system.cpu3.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu3.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu3.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -2765,54 +2770,54 @@ system.cpu3.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu3.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu3.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu3.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data          173                       # number of ReadReq MSHR hits
-system.cpu3.dcache.ReadReq_mshr_hits::total          173                       # number of ReadReq MSHR hits
-system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data           31                       # number of WriteReq MSHR hits
-system.cpu3.dcache.WriteReq_mshr_hits::total           31                       # number of WriteReq MSHR hits
-system.cpu3.dcache.demand_mshr_hits::cpu3.data          204                       # number of demand (read+write) MSHR hits
-system.cpu3.dcache.demand_mshr_hits::total          204                       # number of demand (read+write) MSHR hits
-system.cpu3.dcache.overall_mshr_hits::cpu3.data          204                       # number of overall MSHR hits
-system.cpu3.dcache.overall_mshr_hits::total          204                       # number of overall MSHR hits
-system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data          161                       # number of ReadReq MSHR misses
-system.cpu3.dcache.ReadReq_mshr_misses::total          161                       # number of ReadReq MSHR misses
-system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data          100                       # number of WriteReq MSHR misses
-system.cpu3.dcache.WriteReq_mshr_misses::total          100                       # number of WriteReq MSHR misses
-system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data           56                       # number of SwapReq MSHR misses
-system.cpu3.dcache.SwapReq_mshr_misses::total           56                       # number of SwapReq MSHR misses
-system.cpu3.dcache.demand_mshr_misses::cpu3.data          261                       # number of demand (read+write) MSHR misses
-system.cpu3.dcache.demand_mshr_misses::total          261                       # number of demand (read+write) MSHR misses
-system.cpu3.dcache.overall_mshr_misses::cpu3.data          261                       # number of overall MSHR misses
-system.cpu3.dcache.overall_mshr_misses::total          261                       # number of overall MSHR misses
-system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data      1077518                       # number of ReadReq MSHR miss cycles
-system.cpu3.dcache.ReadReq_mshr_miss_latency::total      1077518                       # number of ReadReq MSHR miss cycles
-system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data      1290489                       # number of WriteReq MSHR miss cycles
-system.cpu3.dcache.WriteReq_mshr_miss_latency::total      1290489                       # number of WriteReq MSHR miss cycles
-system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data       398994                       # number of SwapReq MSHR miss cycles
-system.cpu3.dcache.SwapReq_mshr_miss_latency::total       398994                       # number of SwapReq MSHR miss cycles
-system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data      2368007                       # number of demand (read+write) MSHR miss cycles
-system.cpu3.dcache.demand_mshr_miss_latency::total      2368007                       # number of demand (read+write) MSHR miss cycles
-system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data      2368007                       # number of overall MSHR miss cycles
-system.cpu3.dcache.overall_mshr_miss_latency::total      2368007                       # number of overall MSHR miss cycles
-system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data     0.003819                       # mshr miss rate for ReadReq accesses
-system.cpu3.dcache.ReadReq_mshr_miss_rate::total     0.003819                       # mshr miss rate for ReadReq accesses
-system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data     0.003277                       # mshr miss rate for WriteReq accesses
-system.cpu3.dcache.WriteReq_mshr_miss_rate::total     0.003277                       # mshr miss rate for WriteReq accesses
-system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data     0.788732                       # mshr miss rate for SwapReq accesses
-system.cpu3.dcache.SwapReq_mshr_miss_rate::total     0.788732                       # mshr miss rate for SwapReq accesses
-system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data     0.003591                       # mshr miss rate for demand accesses
-system.cpu3.dcache.demand_mshr_miss_rate::total     0.003591                       # mshr miss rate for demand accesses
-system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data     0.003591                       # mshr miss rate for overall accesses
-system.cpu3.dcache.overall_mshr_miss_rate::total     0.003591                       # mshr miss rate for overall accesses
-system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data  6692.658385                       # average ReadReq mshr miss latency
-system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total  6692.658385                       # average ReadReq mshr miss latency
-system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 12904.890000                       # average WriteReq mshr miss latency
-system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 12904.890000                       # average WriteReq mshr miss latency
-system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data  7124.892857                       # average SwapReq mshr miss latency
-system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total  7124.892857                       # average SwapReq mshr miss latency
-system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data  9072.823755                       # average overall mshr miss latency
-system.cpu3.dcache.demand_avg_mshr_miss_latency::total  9072.823755                       # average overall mshr miss latency
-system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data  9072.823755                       # average overall mshr miss latency
-system.cpu3.dcache.overall_avg_mshr_miss_latency::total  9072.823755                       # average overall mshr miss latency
+system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data          269                       # number of ReadReq MSHR hits
+system.cpu3.dcache.ReadReq_mshr_hits::total          269                       # number of ReadReq MSHR hits
+system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data           33                       # number of WriteReq MSHR hits
+system.cpu3.dcache.WriteReq_mshr_hits::total           33                       # number of WriteReq MSHR hits
+system.cpu3.dcache.demand_mshr_hits::cpu3.data          302                       # number of demand (read+write) MSHR hits
+system.cpu3.dcache.demand_mshr_hits::total          302                       # number of demand (read+write) MSHR hits
+system.cpu3.dcache.overall_mshr_hits::cpu3.data          302                       # number of overall MSHR hits
+system.cpu3.dcache.overall_mshr_hits::total          302                       # number of overall MSHR hits
+system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data          163                       # number of ReadReq MSHR misses
+system.cpu3.dcache.ReadReq_mshr_misses::total          163                       # number of ReadReq MSHR misses
+system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data          107                       # number of WriteReq MSHR misses
+system.cpu3.dcache.WriteReq_mshr_misses::total          107                       # number of WriteReq MSHR misses
+system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data           57                       # number of SwapReq MSHR misses
+system.cpu3.dcache.SwapReq_mshr_misses::total           57                       # number of SwapReq MSHR misses
+system.cpu3.dcache.demand_mshr_misses::cpu3.data          270                       # number of demand (read+write) MSHR misses
+system.cpu3.dcache.demand_mshr_misses::total          270                       # number of demand (read+write) MSHR misses
+system.cpu3.dcache.overall_mshr_misses::cpu3.data          270                       # number of overall MSHR misses
+system.cpu3.dcache.overall_mshr_misses::total          270                       # number of overall MSHR misses
+system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data      1168525                       # number of ReadReq MSHR miss cycles
+system.cpu3.dcache.ReadReq_mshr_miss_latency::total      1168525                       # number of ReadReq MSHR miss cycles
+system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data      1299988                       # number of WriteReq MSHR miss cycles
+system.cpu3.dcache.WriteReq_mshr_miss_latency::total      1299988                       # number of WriteReq MSHR miss cycles
+system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data       401492                       # number of SwapReq MSHR miss cycles
+system.cpu3.dcache.SwapReq_mshr_miss_latency::total       401492                       # number of SwapReq MSHR miss cycles
+system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data      2468513                       # number of demand (read+write) MSHR miss cycles
+system.cpu3.dcache.demand_mshr_miss_latency::total      2468513                       # number of demand (read+write) MSHR miss cycles
+system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data      2468513                       # number of overall MSHR miss cycles
+system.cpu3.dcache.overall_mshr_miss_latency::total      2468513                       # number of overall MSHR miss cycles
+system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data     0.004083                       # mshr miss rate for ReadReq accesses
+system.cpu3.dcache.ReadReq_mshr_miss_rate::total     0.004083                       # mshr miss rate for ReadReq accesses
+system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data     0.003762                       # mshr miss rate for WriteReq accesses
+system.cpu3.dcache.WriteReq_mshr_miss_rate::total     0.003762                       # mshr miss rate for WriteReq accesses
+system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data     0.814286                       # mshr miss rate for SwapReq accesses
+system.cpu3.dcache.SwapReq_mshr_miss_rate::total     0.814286                       # mshr miss rate for SwapReq accesses
+system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data     0.003949                       # mshr miss rate for demand accesses
+system.cpu3.dcache.demand_mshr_miss_rate::total     0.003949                       # mshr miss rate for demand accesses
+system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data     0.003949                       # mshr miss rate for overall accesses
+system.cpu3.dcache.overall_mshr_miss_rate::total     0.003949                       # mshr miss rate for overall accesses
+system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data  7168.865031                       # average ReadReq mshr miss latency
+system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total  7168.865031                       # average ReadReq mshr miss latency
+system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 12149.420561                       # average WriteReq mshr miss latency
+system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 12149.420561                       # average WriteReq mshr miss latency
+system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data  7043.719298                       # average SwapReq mshr miss latency
+system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total  7043.719298                       # average SwapReq mshr miss latency
+system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data  9142.640741                       # average overall mshr miss latency
+system.cpu3.dcache.demand_avg_mshr_miss_latency::total  9142.640741                       # average overall mshr miss latency
+system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data  9142.640741                       # average overall mshr miss latency
+system.cpu3.dcache.overall_avg_mshr_miss_latency::total  9142.640741                       # average overall mshr miss latency
 system.cpu3.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/stats.txt
index 284fa3b0e..61ee516ee 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/stats.txt
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/stats.txt
@@ -1,56 +1,56 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.007260                       # Number of seconds simulated
-sim_ticks                                     7259586                       # Number of ticks simulated
-final_tick                                    7259586                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.007430                       # Number of seconds simulated
+sim_ticks                                     7430292                       # Number of ticks simulated
+final_tick                                    7430292                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_tick_rate                                  53557                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 304720                       # Number of bytes of host memory used
-host_seconds                                   135.55                       # Real time elapsed on the host
+host_tick_rate                                 111636                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 267664                       # Number of bytes of host memory used
+host_seconds                                    66.56                       # Real time elapsed on the host
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                             1                       # Clock period in ticks
 system.ruby.clk_domain.clock                        1                       # Clock period in ticks
 system.ruby.delayHist::bucket_size               1024                       # delay histogram for all message
 system.ruby.delayHist::max_bucket               10239                       # delay histogram for all message
-system.ruby.delayHist::samples                4831117                       # delay histogram for all message
-system.ruby.delayHist::mean                139.352740                       # delay histogram for all message
-system.ruby.delayHist::stdev               395.959906                       # delay histogram for all message
-system.ruby.delayHist                    |     4566883     94.53%     94.53% |      228712      4.73%     99.26% |       33514      0.69%     99.96% |        1886      0.04%    100.00% |          92      0.00%    100.00% |          18      0.00%    100.00% |           9      0.00%    100.00% |           3      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for all message
-system.ruby.delayHist::total                  4831117                       # delay histogram for all message
+system.ruby.delayHist::samples                4929359                       # delay histogram for all message
+system.ruby.delayHist::mean                137.276961                       # delay histogram for all message
+system.ruby.delayHist::stdev               391.112700                       # delay histogram for all message
+system.ruby.delayHist                    |     4668304     94.70%     94.70% |      226078      4.59%     99.29% |       33026      0.67%     99.96% |        1833      0.04%    100.00% |          87      0.00%    100.00% |          19      0.00%    100.00% |           6      0.00%    100.00% |           5      0.00%    100.00% |           1      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for all message
+system.ruby.delayHist::total                  4929359                       # delay histogram for all message
 system.ruby.outstanding_req_hist::bucket_size            2                      
 system.ruby.outstanding_req_hist::max_bucket           19                      
-system.ruby.outstanding_req_hist::samples       608766                      
-system.ruby.outstanding_req_hist::mean      15.998421                      
-system.ruby.outstanding_req_hist::gmean     15.997120                      
-system.ruby.outstanding_req_hist::stdev      0.127650                      
-system.ruby.outstanding_req_hist         |           8      0.00%      0.00% |          16      0.00%      0.00% |          16      0.00%      0.01% |          16      0.00%      0.01% |          16      0.00%      0.01% |          16      0.00%      0.01% |          16      0.00%      0.02% |          17      0.00%      0.02% |      608645     99.98%    100.00% |           0      0.00%    100.00%
-system.ruby.outstanding_req_hist::total        608766                      
+system.ruby.outstanding_req_hist::samples       621693                      
+system.ruby.outstanding_req_hist::mean      15.998454                      
+system.ruby.outstanding_req_hist::gmean     15.997180                      
+system.ruby.outstanding_req_hist::stdev      0.126316                      
+system.ruby.outstanding_req_hist         |           8      0.00%      0.00% |          16      0.00%      0.00% |          16      0.00%      0.01% |          16      0.00%      0.01% |          16      0.00%      0.01% |          16      0.00%      0.01% |          16      0.00%      0.02% |          17      0.00%      0.02% |      621572     99.98%    100.00% |           0      0.00%    100.00%
+system.ruby.outstanding_req_hist::total        621693                      
 system.ruby.latency_hist::bucket_size             512                      
 system.ruby.latency_hist::max_bucket             5119                      
-system.ruby.latency_hist::samples              608638                      
-system.ruby.latency_hist::mean            1526.519325                      
-system.ruby.latency_hist::gmean           1179.356884                      
-system.ruby.latency_hist::stdev            896.379526                      
-system.ruby.latency_hist                 |      103323     16.98%     16.98% |      110835     18.21%     35.19% |       99547     16.36%     51.54% |       97251     15.98%     67.52% |      102045     16.77%     84.29% |       74139     12.18%     96.47% |       20094      3.30%     99.77% |        1390      0.23%    100.00% |          14      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.latency_hist::total                608638                      
+system.ruby.latency_hist::samples              621565                      
+system.ruby.latency_hist::mean            1529.874977                      
+system.ruby.latency_hist::gmean           1159.409755                      
+system.ruby.latency_hist::stdev            924.561318                      
+system.ruby.latency_hist                 |      114606     18.44%     18.44% |      111166     17.88%     36.32% |       93173     14.99%     51.31% |       92857     14.94%     66.25% |      103677     16.68%     82.93% |       81446     13.10%     96.04% |       23108      3.72%     99.75% |        1514      0.24%    100.00% |          18      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.latency_hist::total                621565                      
 system.ruby.hit_latency_hist::bucket_size            1                      
 system.ruby.hit_latency_hist::max_bucket            9                      
-system.ruby.hit_latency_hist::samples               9                      
+system.ruby.hit_latency_hist::samples              12                      
 system.ruby.hit_latency_hist::mean                  3                      
 system.ruby.hit_latency_hist::gmean          3.000000                      
-system.ruby.hit_latency_hist             |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           9    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.hit_latency_hist::total                 9                      
+system.ruby.hit_latency_hist             |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |          12    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.hit_latency_hist::total                12                      
 system.ruby.miss_latency_hist::bucket_size          512                      
 system.ruby.miss_latency_hist::max_bucket         5119                      
-system.ruby.miss_latency_hist::samples         608629                      
-system.ruby.miss_latency_hist::mean       1526.541854                      
-system.ruby.miss_latency_hist::gmean      1179.461074                      
-system.ruby.miss_latency_hist::stdev       896.367007                      
-system.ruby.miss_latency_hist            |      103314     16.97%     16.97% |      110835     18.21%     35.19% |       99547     16.36%     51.54% |       97251     15.98%     67.52% |      102045     16.77%     84.29% |       74139     12.18%     96.47% |       20094      3.30%     99.77% |        1390      0.23%    100.00% |          14      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.miss_latency_hist::total           608629                      
-system.ruby.l1_cntrl4.L1Dcache.demand_hits            1                       # Number of cache demand hits
-system.ruby.l1_cntrl4.L1Dcache.demand_misses        76033                       # Number of cache demand misses
-system.ruby.l1_cntrl4.L1Dcache.demand_accesses        76034                       # Number of cache demand accesses
+system.ruby.miss_latency_hist::samples         621553                      
+system.ruby.miss_latency_hist::mean       1529.904455                      
+system.ruby.miss_latency_hist::gmean      1159.543107                      
+system.ruby.miss_latency_hist::stdev       924.545901                      
+system.ruby.miss_latency_hist            |      114594     18.44%     18.44% |      111166     17.89%     36.32% |       93173     14.99%     51.31% |       92857     14.94%     66.25% |      103677     16.68%     82.93% |       81446     13.10%     96.04% |       23108      3.72%     99.75% |        1514      0.24%    100.00% |          18      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.miss_latency_hist::total           621553                      
+system.ruby.l1_cntrl4.L1Dcache.demand_hits            0                       # Number of cache demand hits
+system.ruby.l1_cntrl4.L1Dcache.demand_misses        77337                       # Number of cache demand misses
+system.ruby.l1_cntrl4.L1Dcache.demand_accesses        77337                       # Number of cache demand accesses
 system.ruby.l1_cntrl4.L1Icache.demand_hits            0                       # Number of cache demand hits
 system.ruby.l1_cntrl4.L1Icache.demand_misses            0                       # Number of cache demand misses
 system.ruby.l1_cntrl4.L1Icache.demand_accesses            0                       # Number of cache demand accesses
@@ -65,8 +65,8 @@ system.ruby.l1_cntrl4.prefetcher.partial_hits            0
 system.ruby.l1_cntrl4.prefetcher.pages_crossed            0                       # number of prefetches across pages
 system.ruby.l1_cntrl4.prefetcher.misses_on_prefetched_blocks            0                       # number of misses for blocks that were prefetched, yet missed
 system.ruby.l1_cntrl5.L1Dcache.demand_hits            1                       # Number of cache demand hits
-system.ruby.l1_cntrl5.L1Dcache.demand_misses        75626                       # Number of cache demand misses
-system.ruby.l1_cntrl5.L1Dcache.demand_accesses        75627                       # Number of cache demand accesses
+system.ruby.l1_cntrl5.L1Dcache.demand_misses        78248                       # Number of cache demand misses
+system.ruby.l1_cntrl5.L1Dcache.demand_accesses        78249                       # Number of cache demand accesses
 system.ruby.l1_cntrl5.L1Icache.demand_hits            0                       # Number of cache demand hits
 system.ruby.l1_cntrl5.L1Icache.demand_misses            0                       # Number of cache demand misses
 system.ruby.l1_cntrl5.L1Icache.demand_accesses            0                       # Number of cache demand accesses
@@ -79,9 +79,9 @@ system.ruby.l1_cntrl5.prefetcher.hits               0                       # nu
 system.ruby.l1_cntrl5.prefetcher.partial_hits            0                       # number of misses observed for a block being prefetched
 system.ruby.l1_cntrl5.prefetcher.pages_crossed            0                       # number of prefetches across pages
 system.ruby.l1_cntrl5.prefetcher.misses_on_prefetched_blocks            0                       # number of misses for blocks that were prefetched, yet missed
-system.ruby.l1_cntrl6.L1Dcache.demand_hits            2                       # Number of cache demand hits
-system.ruby.l1_cntrl6.L1Dcache.demand_misses        75751                       # Number of cache demand misses
-system.ruby.l1_cntrl6.L1Dcache.demand_accesses        75753                       # Number of cache demand accesses
+system.ruby.l1_cntrl6.L1Dcache.demand_hits            3                       # Number of cache demand hits
+system.ruby.l1_cntrl6.L1Dcache.demand_misses        77661                       # Number of cache demand misses
+system.ruby.l1_cntrl6.L1Dcache.demand_accesses        77664                       # Number of cache demand accesses
 system.ruby.l1_cntrl6.L1Icache.demand_hits            0                       # Number of cache demand hits
 system.ruby.l1_cntrl6.L1Icache.demand_misses            0                       # Number of cache demand misses
 system.ruby.l1_cntrl6.L1Icache.demand_accesses            0                       # Number of cache demand accesses
@@ -95,8 +95,8 @@ system.ruby.l1_cntrl6.prefetcher.partial_hits            0
 system.ruby.l1_cntrl6.prefetcher.pages_crossed            0                       # number of prefetches across pages
 system.ruby.l1_cntrl6.prefetcher.misses_on_prefetched_blocks            0                       # number of misses for blocks that were prefetched, yet missed
 system.ruby.l1_cntrl7.L1Dcache.demand_hits            1                       # Number of cache demand hits
-system.ruby.l1_cntrl7.L1Dcache.demand_misses        76551                       # Number of cache demand misses
-system.ruby.l1_cntrl7.L1Dcache.demand_accesses        76552                       # Number of cache demand accesses
+system.ruby.l1_cntrl7.L1Dcache.demand_misses        77688                       # Number of cache demand misses
+system.ruby.l1_cntrl7.L1Dcache.demand_accesses        77689                       # Number of cache demand accesses
 system.ruby.l1_cntrl7.L1Icache.demand_hits            0                       # Number of cache demand hits
 system.ruby.l1_cntrl7.L1Icache.demand_misses            0                       # Number of cache demand misses
 system.ruby.l1_cntrl7.L1Icache.demand_accesses            0                       # Number of cache demand accesses
@@ -109,9 +109,9 @@ system.ruby.l1_cntrl7.prefetcher.hits               0                       # nu
 system.ruby.l1_cntrl7.prefetcher.partial_hits            0                       # number of misses observed for a block being prefetched
 system.ruby.l1_cntrl7.prefetcher.pages_crossed            0                       # number of prefetches across pages
 system.ruby.l1_cntrl7.prefetcher.misses_on_prefetched_blocks            0                       # number of misses for blocks that were prefetched, yet missed
-system.ruby.l1_cntrl0.L1Dcache.demand_hits            1                       # Number of cache demand hits
-system.ruby.l1_cntrl0.L1Dcache.demand_misses        76245                       # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Dcache.demand_accesses        76246                       # Number of cache demand accesses
+system.ruby.l1_cntrl0.L1Dcache.demand_hits            0                       # Number of cache demand hits
+system.ruby.l1_cntrl0.L1Dcache.demand_misses        77618                       # Number of cache demand misses
+system.ruby.l1_cntrl0.L1Dcache.demand_accesses        77618                       # Number of cache demand accesses
 system.ruby.l1_cntrl0.L1Icache.demand_hits            0                       # Number of cache demand hits
 system.ruby.l1_cntrl0.L1Icache.demand_misses            0                       # Number of cache demand misses
 system.ruby.l1_cntrl0.L1Icache.demand_accesses            0                       # Number of cache demand accesses
@@ -124,26 +124,26 @@ system.ruby.l1_cntrl0.prefetcher.hits               0                       # nu
 system.ruby.l1_cntrl0.prefetcher.partial_hits            0                       # number of misses observed for a block being prefetched
 system.ruby.l1_cntrl0.prefetcher.pages_crossed            0                       # number of prefetches across pages
 system.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks            0                       # number of misses for blocks that were prefetched, yet missed
-system.ruby.network.routers00.percent_links_utilized     5.423784                      
-system.ruby.network.routers00.msg_count.Control::0        76245                      
-system.ruby.network.routers00.msg_count.Request_Control::2        73752                      
-system.ruby.network.routers00.msg_count.Response_Data::1        76793                      
-system.ruby.network.routers00.msg_count.Response_Control::1        63355                      
-system.ruby.network.routers00.msg_count.Response_Control::2        75593                      
-system.ruby.network.routers00.msg_count.Writeback_Data::0        14015                      
-system.ruby.network.routers00.msg_count.Writeback_Data::1        49278                      
-system.ruby.network.routers00.msg_count.Writeback_Control::0        25258                      
-system.ruby.network.routers00.msg_bytes.Control::0       609960                      
-system.ruby.network.routers00.msg_bytes.Request_Control::2       590016                      
-system.ruby.network.routers00.msg_bytes.Response_Data::1      5529096                      
-system.ruby.network.routers00.msg_bytes.Response_Control::1       506840                      
-system.ruby.network.routers00.msg_bytes.Response_Control::2       604744                      
-system.ruby.network.routers00.msg_bytes.Writeback_Data::0      1009080                      
-system.ruby.network.routers00.msg_bytes.Writeback_Data::1      3548016                      
-system.ruby.network.routers00.msg_bytes.Writeback_Control::0       202064                      
-system.ruby.l1_cntrl1.L1Dcache.demand_hits            3                       # Number of cache demand hits
-system.ruby.l1_cntrl1.L1Dcache.demand_misses        76099                       # Number of cache demand misses
-system.ruby.l1_cntrl1.L1Dcache.demand_accesses        76102                       # Number of cache demand accesses
+system.ruby.network.routers00.percent_links_utilized     5.388577                      
+system.ruby.network.routers00.msg_count.Control::0        77618                      
+system.ruby.network.routers00.msg_count.Request_Control::2        75225                      
+system.ruby.network.routers00.msg_count.Response_Data::1        78135                      
+system.ruby.network.routers00.msg_count.Response_Control::1        64408                      
+system.ruby.network.routers00.msg_count.Response_Control::2        76967                      
+system.ruby.network.routers00.msg_count.Writeback_Data::0        14088                      
+system.ruby.network.routers00.msg_count.Writeback_Data::1        50186                      
+system.ruby.network.routers00.msg_count.Writeback_Control::0        25649                      
+system.ruby.network.routers00.msg_bytes.Control::0       620944                      
+system.ruby.network.routers00.msg_bytes.Request_Control::2       601800                      
+system.ruby.network.routers00.msg_bytes.Response_Data::1      5625720                      
+system.ruby.network.routers00.msg_bytes.Response_Control::1       515264                      
+system.ruby.network.routers00.msg_bytes.Response_Control::2       615736                      
+system.ruby.network.routers00.msg_bytes.Writeback_Data::0      1014336                      
+system.ruby.network.routers00.msg_bytes.Writeback_Data::1      3613392                      
+system.ruby.network.routers00.msg_bytes.Writeback_Control::0       205192                      
+system.ruby.l1_cntrl1.L1Dcache.demand_hits            2                       # Number of cache demand hits
+system.ruby.l1_cntrl1.L1Dcache.demand_misses        77551                       # Number of cache demand misses
+system.ruby.l1_cntrl1.L1Dcache.demand_accesses        77553                       # Number of cache demand accesses
 system.ruby.l1_cntrl1.L1Icache.demand_hits            0                       # Number of cache demand hits
 system.ruby.l1_cntrl1.L1Icache.demand_misses            0                       # Number of cache demand misses
 system.ruby.l1_cntrl1.L1Icache.demand_accesses            0                       # Number of cache demand accesses
@@ -156,26 +156,26 @@ system.ruby.l1_cntrl1.prefetcher.hits               0                       # nu
 system.ruby.l1_cntrl1.prefetcher.partial_hits            0                       # number of misses observed for a block being prefetched
 system.ruby.l1_cntrl1.prefetcher.pages_crossed            0                       # number of prefetches across pages
 system.ruby.l1_cntrl1.prefetcher.misses_on_prefetched_blocks            0                       # number of misses for blocks that were prefetched, yet missed
-system.ruby.network.routers01.percent_links_utilized     5.417940                      
-system.ruby.network.routers01.msg_count.Control::0        76099                      
-system.ruby.network.routers01.msg_count.Request_Control::2        73821                      
-system.ruby.network.routers01.msg_count.Response_Data::1        76634                      
-system.ruby.network.routers01.msg_count.Response_Control::1        63212                      
-system.ruby.network.routers01.msg_count.Response_Control::2        75499                      
-system.ruby.network.routers01.msg_count.Writeback_Data::0        13920                      
-system.ruby.network.routers01.msg_count.Writeback_Data::1        49382                      
-system.ruby.network.routers01.msg_count.Writeback_Control::0        25225                      
-system.ruby.network.routers01.msg_bytes.Control::0       608792                      
-system.ruby.network.routers01.msg_bytes.Request_Control::2       590568                      
-system.ruby.network.routers01.msg_bytes.Response_Data::1      5517648                      
-system.ruby.network.routers01.msg_bytes.Response_Control::1       505696                      
-system.ruby.network.routers01.msg_bytes.Response_Control::2       603992                      
-system.ruby.network.routers01.msg_bytes.Writeback_Data::0      1002240                      
-system.ruby.network.routers01.msg_bytes.Writeback_Data::1      3555504                      
-system.ruby.network.routers01.msg_bytes.Writeback_Control::0       201800                      
-system.ruby.l1_cntrl2.L1Dcache.demand_hits            0                       # Number of cache demand hits
-system.ruby.l1_cntrl2.L1Dcache.demand_misses        75982                       # Number of cache demand misses
-system.ruby.l1_cntrl2.L1Dcache.demand_accesses        75982                       # Number of cache demand accesses
+system.ruby.network.routers01.percent_links_utilized     5.383194                      
+system.ruby.network.routers01.msg_count.Control::0        77551                      
+system.ruby.network.routers01.msg_count.Request_Control::2        75182                      
+system.ruby.network.routers01.msg_count.Response_Data::1        78051                      
+system.ruby.network.routers01.msg_count.Response_Control::1        64185                      
+system.ruby.network.routers01.msg_count.Response_Control::2        76934                      
+system.ruby.network.routers01.msg_count.Writeback_Data::0        14225                      
+system.ruby.network.routers01.msg_count.Writeback_Data::1        50047                      
+system.ruby.network.routers01.msg_count.Writeback_Control::0        25189                      
+system.ruby.network.routers01.msg_bytes.Control::0       620408                      
+system.ruby.network.routers01.msg_bytes.Request_Control::2       601456                      
+system.ruby.network.routers01.msg_bytes.Response_Data::1      5619672                      
+system.ruby.network.routers01.msg_bytes.Response_Control::1       513480                      
+system.ruby.network.routers01.msg_bytes.Response_Control::2       615472                      
+system.ruby.network.routers01.msg_bytes.Writeback_Data::0      1024200                      
+system.ruby.network.routers01.msg_bytes.Writeback_Data::1      3603384                      
+system.ruby.network.routers01.msg_bytes.Writeback_Control::0       201512                      
+system.ruby.l1_cntrl2.L1Dcache.demand_hits            3                       # Number of cache demand hits
+system.ruby.l1_cntrl2.L1Dcache.demand_misses        77720                       # Number of cache demand misses
+system.ruby.l1_cntrl2.L1Dcache.demand_accesses        77723                       # Number of cache demand accesses
 system.ruby.l1_cntrl2.L1Icache.demand_hits            0                       # Number of cache demand hits
 system.ruby.l1_cntrl2.L1Icache.demand_misses            0                       # Number of cache demand misses
 system.ruby.l1_cntrl2.L1Icache.demand_accesses            0                       # Number of cache demand accesses
@@ -188,26 +188,26 @@ system.ruby.l1_cntrl2.prefetcher.hits               0                       # nu
 system.ruby.l1_cntrl2.prefetcher.partial_hits            0                       # number of misses observed for a block being prefetched
 system.ruby.l1_cntrl2.prefetcher.pages_crossed            0                       # number of prefetches across pages
 system.ruby.l1_cntrl2.prefetcher.misses_on_prefetched_blocks            0                       # number of misses for blocks that were prefetched, yet missed
-system.ruby.network.routers02.percent_links_utilized     5.406755                      
-system.ruby.network.routers02.msg_count.Control::0        75982                      
-system.ruby.network.routers02.msg_count.Request_Control::2        73694                      
-system.ruby.network.routers02.msg_count.Response_Data::1        76434                      
-system.ruby.network.routers02.msg_count.Response_Control::1        63174                      
-system.ruby.network.routers02.msg_count.Response_Control::2        75307                      
-system.ruby.network.routers02.msg_count.Writeback_Data::0        13836                      
-system.ruby.network.routers02.msg_count.Writeback_Data::1        49347                      
-system.ruby.network.routers02.msg_count.Writeback_Control::0        25322                      
-system.ruby.network.routers02.msg_bytes.Control::0       607856                      
-system.ruby.network.routers02.msg_bytes.Request_Control::2       589552                      
-system.ruby.network.routers02.msg_bytes.Response_Data::1      5503248                      
-system.ruby.network.routers02.msg_bytes.Response_Control::1       505392                      
-system.ruby.network.routers02.msg_bytes.Response_Control::2       602456                      
-system.ruby.network.routers02.msg_bytes.Writeback_Data::0       996192                      
-system.ruby.network.routers02.msg_bytes.Writeback_Data::1      3552984                      
-system.ruby.network.routers02.msg_bytes.Writeback_Control::0       202576                      
-system.ruby.l1_cntrl3.L1Dcache.demand_hits            0                       # Number of cache demand hits
-system.ruby.l1_cntrl3.L1Dcache.demand_misses        76366                       # Number of cache demand misses
-system.ruby.l1_cntrl3.L1Dcache.demand_accesses        76366                       # Number of cache demand accesses
+system.ruby.network.routers02.percent_links_utilized     5.401120                      
+system.ruby.network.routers02.msg_count.Control::0        77720                      
+system.ruby.network.routers02.msg_count.Request_Control::2        75340                      
+system.ruby.network.routers02.msg_count.Response_Data::1        78201                      
+system.ruby.network.routers02.msg_count.Response_Control::1        64595                      
+system.ruby.network.routers02.msg_count.Response_Control::2        77107                      
+system.ruby.network.routers02.msg_count.Writeback_Data::0        14370                      
+system.ruby.network.routers02.msg_count.Writeback_Data::1        50215                      
+system.ruby.network.routers02.msg_count.Writeback_Control::0        25440                      
+system.ruby.network.routers02.msg_bytes.Control::0       621760                      
+system.ruby.network.routers02.msg_bytes.Request_Control::2       602720                      
+system.ruby.network.routers02.msg_bytes.Response_Data::1      5630472                      
+system.ruby.network.routers02.msg_bytes.Response_Control::1       516760                      
+system.ruby.network.routers02.msg_bytes.Response_Control::2       616856                      
+system.ruby.network.routers02.msg_bytes.Writeback_Data::0      1034640                      
+system.ruby.network.routers02.msg_bytes.Writeback_Data::1      3615480                      
+system.ruby.network.routers02.msg_bytes.Writeback_Control::0       203520                      
+system.ruby.l1_cntrl3.L1Dcache.demand_hits            2                       # Number of cache demand hits
+system.ruby.l1_cntrl3.L1Dcache.demand_misses        77752                       # Number of cache demand misses
+system.ruby.l1_cntrl3.L1Dcache.demand_accesses        77754                       # Number of cache demand accesses
 system.ruby.l1_cntrl3.L1Icache.demand_hits            0                       # Number of cache demand hits
 system.ruby.l1_cntrl3.L1Icache.demand_misses            0                       # Number of cache demand misses
 system.ruby.l1_cntrl3.L1Icache.demand_accesses            0                       # Number of cache demand accesses
@@ -220,534 +220,534 @@ system.ruby.l1_cntrl3.prefetcher.hits               0                       # nu
 system.ruby.l1_cntrl3.prefetcher.partial_hits            0                       # number of misses observed for a block being prefetched
 system.ruby.l1_cntrl3.prefetcher.pages_crossed            0                       # number of prefetches across pages
 system.ruby.l1_cntrl3.prefetcher.misses_on_prefetched_blocks            0                       # number of misses for blocks that were prefetched, yet missed
-system.ruby.network.routers03.percent_links_utilized     5.433505                      
-system.ruby.network.routers03.msg_count.Control::0        76366                      
-system.ruby.network.routers03.msg_count.Request_Control::2        73906                      
-system.ruby.network.routers03.msg_count.Response_Data::1        76879                      
-system.ruby.network.routers03.msg_count.Response_Control::1        63521                      
-system.ruby.network.routers03.msg_count.Response_Control::2        75747                      
-system.ruby.network.routers03.msg_count.Writeback_Data::0        13928                      
-system.ruby.network.routers03.msg_count.Writeback_Data::1        49494                      
-system.ruby.network.routers03.msg_count.Writeback_Control::0        25551                      
-system.ruby.network.routers03.msg_bytes.Control::0       610928                      
-system.ruby.network.routers03.msg_bytes.Request_Control::2       591248                      
-system.ruby.network.routers03.msg_bytes.Response_Data::1      5535288                      
-system.ruby.network.routers03.msg_bytes.Response_Control::1       508168                      
-system.ruby.network.routers03.msg_bytes.Response_Control::2       605976                      
-system.ruby.network.routers03.msg_bytes.Writeback_Data::0      1002816                      
-system.ruby.network.routers03.msg_bytes.Writeback_Data::1      3563568                      
-system.ruby.network.routers03.msg_bytes.Writeback_Control::0       204408                      
-system.ruby.network.routers04.percent_links_utilized     5.395387                      
-system.ruby.network.routers04.msg_count.Control::0        76033                      
-system.ruby.network.routers04.msg_count.Request_Control::2        73600                      
-system.ruby.network.routers04.msg_count.Response_Data::1        76524                      
-system.ruby.network.routers04.msg_count.Response_Control::1        63335                      
-system.ruby.network.routers04.msg_count.Response_Control::2        75393                      
-system.ruby.network.routers04.msg_count.Writeback_Data::0        13720                      
-system.ruby.network.routers04.msg_count.Writeback_Data::1        48981                      
-system.ruby.network.routers04.msg_count.Writeback_Control::0        25345                      
-system.ruby.network.routers04.msg_bytes.Control::0       608264                      
-system.ruby.network.routers04.msg_bytes.Request_Control::2       588800                      
-system.ruby.network.routers04.msg_bytes.Response_Data::1      5509728                      
-system.ruby.network.routers04.msg_bytes.Response_Control::1       506680                      
-system.ruby.network.routers04.msg_bytes.Response_Control::2       603144                      
-system.ruby.network.routers04.msg_bytes.Writeback_Data::0       987840                      
-system.ruby.network.routers04.msg_bytes.Writeback_Data::1      3526632                      
-system.ruby.network.routers04.msg_bytes.Writeback_Control::0       202760                      
-system.ruby.network.routers05.percent_links_utilized     5.367062                      
-system.ruby.network.routers05.msg_count.Control::0        75626                      
-system.ruby.network.routers05.msg_count.Request_Control::2        73320                      
-system.ruby.network.routers05.msg_count.Response_Data::1        76116                      
-system.ruby.network.routers05.msg_count.Response_Control::1        62950                      
-system.ruby.network.routers05.msg_count.Response_Control::2        74958                      
-system.ruby.network.routers05.msg_count.Writeback_Data::0        13608                      
-system.ruby.network.routers05.msg_count.Writeback_Data::1        48776                      
-system.ruby.network.routers05.msg_count.Writeback_Control::0        25152                      
-system.ruby.network.routers05.msg_bytes.Control::0       605008                      
-system.ruby.network.routers05.msg_bytes.Request_Control::2       586560                      
-system.ruby.network.routers05.msg_bytes.Response_Data::1      5480352                      
-system.ruby.network.routers05.msg_bytes.Response_Control::1       503600                      
-system.ruby.network.routers05.msg_bytes.Response_Control::2       599664                      
-system.ruby.network.routers05.msg_bytes.Writeback_Data::0       979776                      
-system.ruby.network.routers05.msg_bytes.Writeback_Data::1      3511872                      
-system.ruby.network.routers05.msg_bytes.Writeback_Control::0       201216                      
-system.ruby.network.routers06.percent_links_utilized     5.371797                      
-system.ruby.network.routers06.msg_count.Control::0        75751                      
-system.ruby.network.routers06.msg_count.Request_Control::2        73431                      
-system.ruby.network.routers06.msg_count.Response_Data::1        76221                      
-system.ruby.network.routers06.msg_count.Response_Control::1        63027                      
-system.ruby.network.routers06.msg_count.Response_Control::2        75095                      
-system.ruby.network.routers06.msg_count.Writeback_Data::0        13703                      
-system.ruby.network.routers06.msg_count.Writeback_Data::1        48704                      
-system.ruby.network.routers06.msg_count.Writeback_Control::0        24925                      
-system.ruby.network.routers06.msg_bytes.Control::0       606008                      
-system.ruby.network.routers06.msg_bytes.Request_Control::2       587448                      
-system.ruby.network.routers06.msg_bytes.Response_Data::1      5487912                      
-system.ruby.network.routers06.msg_bytes.Response_Control::1       504216                      
-system.ruby.network.routers06.msg_bytes.Response_Control::2       600760                      
-system.ruby.network.routers06.msg_bytes.Writeback_Data::0       986616                      
-system.ruby.network.routers06.msg_bytes.Writeback_Data::1      3506688                      
-system.ruby.network.routers06.msg_bytes.Writeback_Control::0       199400                      
-system.ruby.network.routers07.percent_links_utilized     5.448957                      
-system.ruby.network.routers07.msg_count.Control::0        76551                      
-system.ruby.network.routers07.msg_count.Request_Control::2        74163                      
-system.ruby.network.routers07.msg_count.Response_Data::1        77065                      
-system.ruby.network.routers07.msg_count.Response_Control::1        63812                      
-system.ruby.network.routers07.msg_count.Response_Control::2        75941                      
-system.ruby.network.routers07.msg_count.Writeback_Data::0        13974                      
-system.ruby.network.routers07.msg_count.Writeback_Data::1        49643                      
-system.ruby.network.routers07.msg_count.Writeback_Control::0        25684                      
-system.ruby.network.routers07.msg_bytes.Control::0       612408                      
-system.ruby.network.routers07.msg_bytes.Request_Control::2       593304                      
-system.ruby.network.routers07.msg_bytes.Response_Data::1      5548680                      
-system.ruby.network.routers07.msg_bytes.Response_Control::1       510496                      
-system.ruby.network.routers07.msg_bytes.Response_Control::2       607528                      
-system.ruby.network.routers07.msg_bytes.Writeback_Data::0      1006128                      
-system.ruby.network.routers07.msg_bytes.Writeback_Data::1      3574296                      
-system.ruby.network.routers07.msg_bytes.Writeback_Control::0       205472                      
-system.ruby.l2_cntrl0.L2cache.demand_hits           30                       # Number of cache demand hits
-system.ruby.l2_cntrl0.L2cache.demand_misses       608605                       # Number of cache demand misses
-system.ruby.l2_cntrl0.L2cache.demand_accesses       608635                       # Number of cache demand accesses
-system.ruby.l2_cntrl0.fully_busy_cycles             1                       # cycles for which number of transistions == max transitions
-system.ruby.network.routers08.percent_links_utilized    73.788082                      
-system.ruby.network.routers08.msg_count.Control::0      1211833                      
-system.ruby.network.routers08.msg_count.Request_Control::2       585965                      
-system.ruby.network.routers08.msg_count.Response_Data::1      1420506                      
-system.ruby.network.routers08.msg_count.Response_Control::1      1499731                      
-system.ruby.network.routers08.msg_count.Response_Control::2       603532                      
-system.ruby.network.routers08.msg_count.Writeback_Data::0       110703                      
-system.ruby.network.routers08.msg_count.Writeback_Data::1       393605                      
-system.ruby.network.routers08.msg_count.Writeback_Control::0       202462                      
-system.ruby.network.routers08.msg_bytes.Control::0      9694664                      
-system.ruby.network.routers08.msg_bytes.Request_Control::2      4687720                      
-system.ruby.network.routers08.msg_bytes.Response_Data::1    102276432                      
-system.ruby.network.routers08.msg_bytes.Response_Control::1     11997848                      
-system.ruby.network.routers08.msg_bytes.Response_Control::2      4828256                      
-system.ruby.network.routers08.msg_bytes.Writeback_Data::0      7970616                      
-system.ruby.network.routers08.msg_bytes.Writeback_Data::1     28339560                      
-system.ruby.network.routers08.msg_bytes.Writeback_Control::0      1619696                      
+system.ruby.network.routers03.percent_links_utilized     5.405376                      
+system.ruby.network.routers03.msg_count.Control::0        77752                      
+system.ruby.network.routers03.msg_count.Request_Control::2        75338                      
+system.ruby.network.routers03.msg_count.Response_Data::1        78287                      
+system.ruby.network.routers03.msg_count.Response_Control::1        64277                      
+system.ruby.network.routers03.msg_count.Response_Control::2        77086                      
+system.ruby.network.routers03.msg_count.Writeback_Data::0        14417                      
+system.ruby.network.routers03.msg_count.Writeback_Data::1        50285                      
+system.ruby.network.routers03.msg_count.Writeback_Control::0        25187                      
+system.ruby.network.routers03.msg_bytes.Control::0       622016                      
+system.ruby.network.routers03.msg_bytes.Request_Control::2       602704                      
+system.ruby.network.routers03.msg_bytes.Response_Data::1      5636664                      
+system.ruby.network.routers03.msg_bytes.Response_Control::1       514216                      
+system.ruby.network.routers03.msg_bytes.Response_Control::2       616688                      
+system.ruby.network.routers03.msg_bytes.Writeback_Data::0      1038024                      
+system.ruby.network.routers03.msg_bytes.Writeback_Data::1      3620520                      
+system.ruby.network.routers03.msg_bytes.Writeback_Control::0       201496                      
+system.ruby.network.routers04.percent_links_utilized     5.370206                      
+system.ruby.network.routers04.msg_count.Control::0        77337                      
+system.ruby.network.routers04.msg_count.Request_Control::2        74942                      
+system.ruby.network.routers04.msg_count.Response_Data::1        77832                      
+system.ruby.network.routers04.msg_count.Response_Control::1        64045                      
+system.ruby.network.routers04.msg_count.Response_Control::2        76706                      
+system.ruby.network.routers04.msg_count.Writeback_Data::0        14274                      
+system.ruby.network.routers04.msg_count.Writeback_Data::1        49893                      
+system.ruby.network.routers04.msg_count.Writeback_Control::0        25067                      
+system.ruby.network.routers04.msg_bytes.Control::0       618696                      
+system.ruby.network.routers04.msg_bytes.Request_Control::2       599536                      
+system.ruby.network.routers04.msg_bytes.Response_Data::1      5603904                      
+system.ruby.network.routers04.msg_bytes.Response_Control::1       512360                      
+system.ruby.network.routers04.msg_bytes.Response_Control::2       613648                      
+system.ruby.network.routers04.msg_bytes.Writeback_Data::0      1027728                      
+system.ruby.network.routers04.msg_bytes.Writeback_Data::1      3592296                      
+system.ruby.network.routers04.msg_bytes.Writeback_Control::0       200536                      
+system.ruby.network.routers05.percent_links_utilized     5.437902                      
+system.ruby.network.routers05.msg_count.Control::0        78248                      
+system.ruby.network.routers05.msg_count.Request_Control::2        75756                      
+system.ruby.network.routers05.msg_count.Response_Data::1        78726                      
+system.ruby.network.routers05.msg_count.Response_Control::1        64879                      
+system.ruby.network.routers05.msg_count.Response_Control::2        77614                      
+system.ruby.network.routers05.msg_count.Writeback_Data::0        14469                      
+system.ruby.network.routers05.msg_count.Writeback_Data::1        50596                      
+system.ruby.network.routers05.msg_count.Writeback_Control::0        25597                      
+system.ruby.network.routers05.msg_bytes.Control::0       625984                      
+system.ruby.network.routers05.msg_bytes.Request_Control::2       606048                      
+system.ruby.network.routers05.msg_bytes.Response_Data::1      5668272                      
+system.ruby.network.routers05.msg_bytes.Response_Control::1       519032                      
+system.ruby.network.routers05.msg_bytes.Response_Control::2       620912                      
+system.ruby.network.routers05.msg_bytes.Writeback_Data::0      1041768                      
+system.ruby.network.routers05.msg_bytes.Writeback_Data::1      3642912                      
+system.ruby.network.routers05.msg_bytes.Writeback_Control::0       204776                      
+system.ruby.network.routers06.percent_links_utilized     5.392954                      
+system.ruby.network.routers06.msg_count.Control::0        77661                      
+system.ruby.network.routers06.msg_count.Request_Control::2        75223                      
+system.ruby.network.routers06.msg_count.Response_Data::1        78177                      
+system.ruby.network.routers06.msg_count.Response_Control::1        64312                      
+system.ruby.network.routers06.msg_count.Response_Control::2        77032                      
+system.ruby.network.routers06.msg_count.Writeback_Data::0        14283                      
+system.ruby.network.routers06.msg_count.Writeback_Data::1        50131                      
+system.ruby.network.routers06.msg_count.Writeback_Control::0        25302                      
+system.ruby.network.routers06.msg_bytes.Control::0       621288                      
+system.ruby.network.routers06.msg_bytes.Request_Control::2       601784                      
+system.ruby.network.routers06.msg_bytes.Response_Data::1      5628744                      
+system.ruby.network.routers06.msg_bytes.Response_Control::1       514496                      
+system.ruby.network.routers06.msg_bytes.Response_Control::2       616256                      
+system.ruby.network.routers06.msg_bytes.Writeback_Data::0      1028376                      
+system.ruby.network.routers06.msg_bytes.Writeback_Data::1      3609432                      
+system.ruby.network.routers06.msg_bytes.Writeback_Control::0       202416                      
+system.ruby.network.routers07.percent_links_utilized     5.402086                      
+system.ruby.network.routers07.msg_count.Control::0        77688                      
+system.ruby.network.routers07.msg_count.Request_Control::2        75301                      
+system.ruby.network.routers07.msg_count.Response_Data::1        78207                      
+system.ruby.network.routers07.msg_count.Response_Control::1        64323                      
+system.ruby.network.routers07.msg_count.Response_Control::2        77070                      
+system.ruby.network.routers07.msg_count.Writeback_Data::0        14297                      
+system.ruby.network.routers07.msg_count.Writeback_Data::1        50355                      
+system.ruby.network.routers07.msg_count.Writeback_Control::0        25450                      
+system.ruby.network.routers07.msg_bytes.Control::0       621504                      
+system.ruby.network.routers07.msg_bytes.Request_Control::2       602408                      
+system.ruby.network.routers07.msg_bytes.Response_Data::1      5630904                      
+system.ruby.network.routers07.msg_bytes.Response_Control::1       514584                      
+system.ruby.network.routers07.msg_bytes.Response_Control::2       616560                      
+system.ruby.network.routers07.msg_bytes.Writeback_Data::0      1029384                      
+system.ruby.network.routers07.msg_bytes.Writeback_Data::1      3625560                      
+system.ruby.network.routers07.msg_bytes.Writeback_Control::0       203600                      
+system.ruby.l2_cntrl0.L2cache.demand_hits           27                       # Number of cache demand hits
+system.ruby.l2_cntrl0.L2cache.demand_misses       621533                       # Number of cache demand misses
+system.ruby.l2_cntrl0.L2cache.demand_accesses       621560                       # Number of cache demand accesses
+system.ruby.l2_cntrl0.fully_busy_cycles             2                       # cycles for which number of transistions == max transitions
+system.ruby.network.routers08.percent_links_utilized    73.742176                      
+system.ruby.network.routers08.msg_count.Control::0      1237703                      
+system.ruby.network.routers08.msg_count.Request_Control::2       598605                      
+system.ruby.network.routers08.msg_count.Response_Data::1      1454436                      
+system.ruby.network.routers08.msg_count.Response_Control::1      1526235                      
+system.ruby.network.routers08.msg_count.Response_Control::2       616516                      
+system.ruby.network.routers08.msg_count.Writeback_Data::0       114423                      
+system.ruby.network.routers08.msg_count.Writeback_Data::1       401708                      
+system.ruby.network.routers08.msg_count.Writeback_Control::0       202881                      
+system.ruby.network.routers08.msg_bytes.Control::0      9901624                      
+system.ruby.network.routers08.msg_bytes.Request_Control::2      4788840                      
+system.ruby.network.routers08.msg_bytes.Response_Data::1    104719392                      
+system.ruby.network.routers08.msg_bytes.Response_Control::1     12209880                      
+system.ruby.network.routers08.msg_bytes.Response_Control::2      4932128                      
+system.ruby.network.routers08.msg_bytes.Writeback_Data::0      8238456                      
+system.ruby.network.routers08.msg_bytes.Writeback_Data::1     28922976                      
+system.ruby.network.routers08.msg_bytes.Writeback_Control::0      1623048                      
 system.ruby.memctrl_clk_domain.clock                3                       # Clock period in ticks
-system.ruby.dir_cntrl0.memBuffer.memReq        816132                       # Total number of memory requests
-system.ruby.dir_cntrl0.memBuffer.memRead       603181                       # Number of memory reads
-system.ruby.dir_cntrl0.memBuffer.memWrite       212949                       # Number of memory writes
-system.ruby.dir_cntrl0.memBuffer.memRefresh        50414                       # Number of memory refreshes
-system.ruby.dir_cntrl0.memBuffer.memWaitCycles      5087209                       # Delay stalled at the head of the bank queue
-system.ruby.dir_cntrl0.memBuffer.memInputQ       208626                       # Delay in the input queue
-system.ruby.dir_cntrl0.memBuffer.memBankQ       421577                       # Delay behind the head of the bank queue
-system.ruby.dir_cntrl0.memBuffer.totalStalls      5717412                       # Total number of stall cycles
-system.ruby.dir_cntrl0.memBuffer.stallsPerReq     7.005499                       # Expected number of stall cycles per request
-system.ruby.dir_cntrl0.memBuffer.memBankBusy       996551                       # memory stalls due to busy bank
-system.ruby.dir_cntrl0.memBuffer.memBusBusy      1584957                       # memory stalls due to busy bus
-system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy       931983                       # memory stalls due to read write turnaround
-system.ruby.dir_cntrl0.memBuffer.memDataBusBusy       411910                       # memory stalls due to read read turnaround
-system.ruby.dir_cntrl0.memBuffer.memArbWait       974568                       # memory stalls due to arbitration
-system.ruby.dir_cntrl0.memBuffer.memNotOld       187240                       # memory stalls due to anti starvation
-system.ruby.dir_cntrl0.memBuffer.memBankCount |       25732      3.15%      3.15% |       25542      3.13%      6.28% |       25558      3.13%      9.41% |       25419      3.11%     12.53% |       25578      3.13%     15.66% |       25569      3.13%     18.80% |       25355      3.11%     21.90% |       25427      3.12%     25.02% |       25577      3.13%     28.15% |       25273      3.10%     31.25% |       25829      3.16%     34.41% |       25738      3.15%     37.57% |       25452      3.12%     40.69% |       25562      3.13%     43.82% |       25175      3.08%     46.90% |       25281      3.10%     50.00% |       25608      3.14%     53.14% |       25089      3.07%     56.21% |       25653      3.14%     59.36% |       25208      3.09%     62.44% |       25307      3.10%     65.54% |       25373      3.11%     68.65% |       25373      3.11%     71.76% |       25618      3.14%     74.90% |       25513      3.13%     78.03% |       26009      3.19%     81.21% |       25574      3.13%     84.35% |       25719      3.15%     87.50% |       25435      3.12%     90.62% |       25580      3.13%     93.75% |       25654      3.14%     96.89% |       25352      3.11%    100.00% # Number of accesses per bank
-system.ruby.dir_cntrl0.memBuffer.memBankCount::total       816132                       # Number of accesses per bank
-system.ruby.network.routers09.percent_links_utilized    30.792875                      
-system.ruby.network.routers09.msg_count.Control::0       603181                      
-system.ruby.network.routers09.msg_count.Response_Data::1       816130                      
-system.ruby.network.routers09.msg_count.Response_Control::1       993390                      
-system.ruby.network.routers09.msg_bytes.Control::0      4825448                      
-system.ruby.network.routers09.msg_bytes.Response_Data::1     58761360                      
-system.ruby.network.routers09.msg_bytes.Response_Control::1      7947120                      
-system.ruby.network.routers10.percent_links_utilized    14.793798                      
-system.ruby.network.routers10.msg_count.Control::0      1211833                      
-system.ruby.network.routers10.msg_count.Request_Control::2       589687                      
-system.ruby.network.routers10.msg_count.Response_Data::1      1425926                      
-system.ruby.network.routers10.msg_count.Response_Control::1      1499753                      
-system.ruby.network.routers10.msg_count.Response_Control::2       603532                      
-system.ruby.network.routers10.msg_count.Writeback_Data::0       110703                      
-system.ruby.network.routers10.msg_count.Writeback_Data::1       393605                      
-system.ruby.network.routers10.msg_count.Writeback_Control::0       202462                      
-system.ruby.network.routers10.msg_bytes.Control::0      9694664                      
-system.ruby.network.routers10.msg_bytes.Request_Control::2      4717496                      
-system.ruby.network.routers10.msg_bytes.Response_Data::1    102666672                      
-system.ruby.network.routers10.msg_bytes.Response_Control::1     11998024                      
-system.ruby.network.routers10.msg_bytes.Response_Control::2      4828256                      
-system.ruby.network.routers10.msg_bytes.Writeback_Data::0      7970616                      
-system.ruby.network.routers10.msg_bytes.Writeback_Data::1     28339560                      
-system.ruby.network.routers10.msg_bytes.Writeback_Control::0      1619696                      
-system.ruby.network.msg_count.Control         3635500                      
-system.ruby.network.msg_count.Request_Control      1765339                      
-system.ruby.network.msg_count.Response_Data      4275228                      
-system.ruby.network.msg_count.Response_Control      6309857                      
-system.ruby.network.msg_count.Writeback_Data      1512925                      
-system.ruby.network.msg_count.Writeback_Control       607386                      
-system.ruby.network.msg_byte.Control         29084000                      
-system.ruby.network.msg_byte.Request_Control     14122712                      
-system.ruby.network.msg_byte.Response_Data    307816416                      
-system.ruby.network.msg_byte.Response_Control     50478856                      
-system.ruby.network.msg_byte.Writeback_Data    108930600                      
-system.ruby.network.msg_byte.Writeback_Control      4859088                      
+system.ruby.dir_cntrl0.memBuffer.memReq        837117                       # Total number of memory requests
+system.ruby.dir_cntrl0.memBuffer.memRead       616125                       # Number of memory reads
+system.ruby.dir_cntrl0.memBuffer.memWrite       220987                       # Number of memory writes
+system.ruby.dir_cntrl0.memBuffer.memRefresh        51600                       # Number of memory refreshes
+system.ruby.dir_cntrl0.memBuffer.memWaitCycles      5282130                       # Delay stalled at the head of the bank queue
+system.ruby.dir_cntrl0.memBuffer.memInputQ       213418                       # Delay in the input queue
+system.ruby.dir_cntrl0.memBuffer.memBankQ       448771                       # Delay behind the head of the bank queue
+system.ruby.dir_cntrl0.memBuffer.totalStalls      5944319                       # Total number of stall cycles
+system.ruby.dir_cntrl0.memBuffer.stallsPerReq     7.100942                       # Expected number of stall cycles per request
+system.ruby.dir_cntrl0.memBuffer.memBankBusy      1034385                       # memory stalls due to busy bank
+system.ruby.dir_cntrl0.memBuffer.memBusBusy      1644850                       # memory stalls due to busy bus
+system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy       969543                       # memory stalls due to read write turnaround
+system.ruby.dir_cntrl0.memBuffer.memDataBusBusy       420455                       # memory stalls due to read read turnaround
+system.ruby.dir_cntrl0.memBuffer.memArbWait      1013454                       # memory stalls due to arbitration
+system.ruby.dir_cntrl0.memBuffer.memNotOld       199443                       # memory stalls due to anti starvation
+system.ruby.dir_cntrl0.memBuffer.memBankCount |       26053      3.11%      3.11% |       26238      3.13%      6.25% |       26476      3.16%      9.41% |       26000      3.11%     12.52% |       26163      3.13%     15.64% |       26349      3.15%     18.79% |       26252      3.14%     21.92% |       26118      3.12%     25.04% |       26155      3.12%     28.17% |       25974      3.10%     31.27% |       26485      3.16%     34.44% |       26013      3.11%     37.54% |       26239      3.13%     40.68% |       25904      3.09%     43.77% |       26148      3.12%     46.90% |       26248      3.14%     50.03% |       26068      3.11%     53.14% |       26508      3.17%     56.31% |       25945      3.10%     59.41% |       26211      3.13%     62.54% |       25779      3.08%     65.62% |       25834      3.09%     68.71% |       26282      3.14%     71.85% |       26037      3.11%     74.96% |       26294      3.14%     78.10% |       26232      3.13%     81.23% |       25842      3.09%     84.32% |       26144      3.12%     87.44% |       26060      3.11%     90.55% |       26651      3.18%     93.74% |       26042      3.11%     96.85% |       26373      3.15%    100.00% # Number of accesses per bank
+system.ruby.dir_cntrl0.memBuffer.memBankCount::total       837117                       # Number of accesses per bank
+system.ruby.network.routers09.percent_links_utilized    30.824398                      
+system.ruby.network.routers09.msg_count.Control::0       616128                      
+system.ruby.network.routers09.msg_count.Response_Data::1       837111                      
+system.ruby.network.routers09.msg_count.Response_Control::1      1011244                      
+system.ruby.network.routers09.msg_bytes.Control::0      4929024                      
+system.ruby.network.routers09.msg_bytes.Response_Data::1     60271992                      
+system.ruby.network.routers09.msg_bytes.Response_Control::1      8089952                      
+system.ruby.network.routers10.percent_links_utilized    14.783673                      
+system.ruby.network.routers10.msg_count.Control::0      1237703                      
+system.ruby.network.routers10.msg_count.Request_Control::2       602307                      
+system.ruby.network.routers10.msg_count.Response_Data::1      1459841                      
+system.ruby.network.routers10.msg_count.Response_Control::1      1526251                      
+system.ruby.network.routers10.msg_count.Response_Control::2       616516                      
+system.ruby.network.routers10.msg_count.Writeback_Data::0       114423                      
+system.ruby.network.routers10.msg_count.Writeback_Data::1       401708                      
+system.ruby.network.routers10.msg_count.Writeback_Control::0       202881                      
+system.ruby.network.routers10.msg_bytes.Control::0      9901624                      
+system.ruby.network.routers10.msg_bytes.Request_Control::2      4818456                      
+system.ruby.network.routers10.msg_bytes.Response_Data::1    105108552                      
+system.ruby.network.routers10.msg_bytes.Response_Control::1     12210008                      
+system.ruby.network.routers10.msg_bytes.Response_Control::2      4932128                      
+system.ruby.network.routers10.msg_bytes.Writeback_Data::0      8238456                      
+system.ruby.network.routers10.msg_bytes.Writeback_Data::1     28922976                      
+system.ruby.network.routers10.msg_bytes.Writeback_Control::0      1623048                      
+system.ruby.network.msg_count.Control         3713109                      
+system.ruby.network.msg_count.Request_Control      1803219                      
+system.ruby.network.msg_count.Response_Data      4377004                      
+system.ruby.network.msg_count.Response_Control      6428302                      
+system.ruby.network.msg_count.Writeback_Data      1548393                      
+system.ruby.network.msg_count.Writeback_Control       608643                      
+system.ruby.network.msg_byte.Control         29704872                      
+system.ruby.network.msg_byte.Request_Control     14425752                      
+system.ruby.network.msg_byte.Response_Data    315144288                      
+system.ruby.network.msg_byte.Response_Control     51426416                      
+system.ruby.network.msg_byte.Writeback_Data    111484296                      
+system.ruby.network.msg_byte.Writeback_Control      4869144                      
 system.funcbus.throughput                           0                       # Throughput (bytes/s)
 system.funcbus.data_through_bus                     0                       # Total data (bytes)
-system.cpu0.num_reads                           98705                       # number of read accesses completed
-system.cpu0.num_writes                          53811                       # number of write accesses completed
+system.cpu0.num_reads                           99258                       # number of read accesses completed
+system.cpu0.num_writes                          54534                       # number of write accesses completed
 system.cpu0.num_copies                              0                       # number of copy accesses completed
-system.cpu1.num_reads                           98323                       # number of read accesses completed
-system.cpu1.num_writes                          53379                       # number of write accesses completed
+system.cpu1.num_reads                           98654                       # number of read accesses completed
+system.cpu1.num_writes                          54809                       # number of write accesses completed
 system.cpu1.num_copies                              0                       # number of copy accesses completed
-system.cpu2.num_reads                           98444                       # number of read accesses completed
-system.cpu2.num_writes                          53127                       # number of write accesses completed
+system.cpu2.num_reads                           99249                       # number of read accesses completed
+system.cpu2.num_writes                          54599                       # number of write accesses completed
 system.cpu2.num_copies                              0                       # number of copy accesses completed
-system.cpu3.num_reads                           98629                       # number of read accesses completed
-system.cpu3.num_writes                          53267                       # number of write accesses completed
+system.cpu3.num_reads                           98783                       # number of read accesses completed
+system.cpu3.num_writes                          54952                       # number of write accesses completed
 system.cpu3.num_copies                              0                       # number of copy accesses completed
-system.cpu4.num_reads                           98161                       # number of read accesses completed
-system.cpu4.num_writes                          53090                       # number of write accesses completed
+system.cpu4.num_reads                           98121                       # number of read accesses completed
+system.cpu4.num_writes                          54478                       # number of write accesses completed
 system.cpu4.num_copies                              0                       # number of copy accesses completed
-system.cpu5.num_reads                           98401                       # number of read accesses completed
-system.cpu5.num_writes                          52796                       # number of write accesses completed
+system.cpu5.num_reads                          100000                       # number of read accesses completed
+system.cpu5.num_writes                          55112                       # number of write accesses completed
 system.cpu5.num_copies                              0                       # number of copy accesses completed
-system.cpu6.num_reads                           98263                       # number of read accesses completed
-system.cpu6.num_writes                          53278                       # number of write accesses completed
+system.cpu6.num_reads                           98611                       # number of read accesses completed
+system.cpu6.num_writes                          54867                       # number of write accesses completed
 system.cpu6.num_copies                              0                       # number of copy accesses completed
-system.cpu7.num_reads                          100000                       # number of read accesses completed
-system.cpu7.num_writes                          53646                       # number of write accesses completed
+system.cpu7.num_reads                           99371                       # number of read accesses completed
+system.cpu7.num_writes                          54915                       # number of write accesses completed
 system.cpu7.num_copies                              0                       # number of copy accesses completed
-system.ruby.network.routers00.throttle0.link_utilization     5.504536                      
-system.ruby.network.routers00.throttle0.msg_count.Request_Control::2        73752                      
-system.ruby.network.routers00.throttle0.msg_count.Response_Data::1        76243                      
-system.ruby.network.routers00.throttle0.msg_count.Response_Control::1        39274                      
-system.ruby.network.routers00.throttle0.msg_bytes.Request_Control::2       590016                      
-system.ruby.network.routers00.throttle0.msg_bytes.Response_Data::1      5489496                      
-system.ruby.network.routers00.throttle0.msg_bytes.Response_Control::1       314192                      
-system.ruby.network.routers00.throttle1.link_utilization     5.343032                      
-system.ruby.network.routers00.throttle1.msg_count.Control::0        76245                      
-system.ruby.network.routers00.throttle1.msg_count.Response_Data::1          550                      
-system.ruby.network.routers00.throttle1.msg_count.Response_Control::1        24081                      
-system.ruby.network.routers00.throttle1.msg_count.Response_Control::2        75593                      
-system.ruby.network.routers00.throttle1.msg_count.Writeback_Data::0        14015                      
-system.ruby.network.routers00.throttle1.msg_count.Writeback_Data::1        49278                      
-system.ruby.network.routers00.throttle1.msg_count.Writeback_Control::0        25258                      
-system.ruby.network.routers00.throttle1.msg_bytes.Control::0       609960                      
-system.ruby.network.routers00.throttle1.msg_bytes.Response_Data::1        39600                      
-system.ruby.network.routers00.throttle1.msg_bytes.Response_Control::1       192648                      
-system.ruby.network.routers00.throttle1.msg_bytes.Response_Control::2       604744                      
-system.ruby.network.routers00.throttle1.msg_bytes.Writeback_Data::0      1009080                      
-system.ruby.network.routers00.throttle1.msg_bytes.Writeback_Data::1      3548016                      
-system.ruby.network.routers00.throttle1.msg_bytes.Writeback_Control::0       202064                      
-system.ruby.network.routers01.throttle0.link_utilization     5.494969                      
-system.ruby.network.routers01.throttle0.msg_count.Request_Control::2        73821                      
-system.ruby.network.routers01.throttle0.msg_count.Response_Data::1        76095                      
-system.ruby.network.routers01.throttle0.msg_count.Response_Control::1        39148                      
-system.ruby.network.routers01.throttle0.msg_bytes.Request_Control::2       590568                      
-system.ruby.network.routers01.throttle0.msg_bytes.Response_Data::1      5478840                      
-system.ruby.network.routers01.throttle0.msg_bytes.Response_Control::1       313184                      
-system.ruby.network.routers01.throttle1.link_utilization     5.340911                      
-system.ruby.network.routers01.throttle1.msg_count.Control::0        76099                      
-system.ruby.network.routers01.throttle1.msg_count.Response_Data::1          539                      
-system.ruby.network.routers01.throttle1.msg_count.Response_Control::1        24064                      
-system.ruby.network.routers01.throttle1.msg_count.Response_Control::2        75499                      
-system.ruby.network.routers01.throttle1.msg_count.Writeback_Data::0        13920                      
-system.ruby.network.routers01.throttle1.msg_count.Writeback_Data::1        49382                      
-system.ruby.network.routers01.throttle1.msg_count.Writeback_Control::0        25225                      
-system.ruby.network.routers01.throttle1.msg_bytes.Control::0       608792                      
-system.ruby.network.routers01.throttle1.msg_bytes.Response_Data::1        38808                      
-system.ruby.network.routers01.throttle1.msg_bytes.Response_Control::1       192512                      
-system.ruby.network.routers01.throttle1.msg_bytes.Response_Control::2       603992                      
-system.ruby.network.routers01.throttle1.msg_bytes.Writeback_Data::0      1002240                      
-system.ruby.network.routers01.throttle1.msg_bytes.Writeback_Data::1      3555504                      
-system.ruby.network.routers01.throttle1.msg_bytes.Writeback_Control::0       201800                      
-system.ruby.network.routers02.throttle0.link_utilization     5.486924                      
-system.ruby.network.routers02.throttle0.msg_count.Request_Control::2        73694                      
-system.ruby.network.routers02.throttle0.msg_count.Response_Data::1        75978                      
-system.ruby.network.routers02.throttle0.msg_count.Response_Control::1        39160                      
-system.ruby.network.routers02.throttle0.msg_bytes.Request_Control::2       589552                      
-system.ruby.network.routers02.throttle0.msg_bytes.Response_Data::1      5470416                      
-system.ruby.network.routers02.throttle0.msg_bytes.Response_Control::1       313280                      
-system.ruby.network.routers02.throttle1.link_utilization     5.326585                      
-system.ruby.network.routers02.throttle1.msg_count.Control::0        75982                      
-system.ruby.network.routers02.throttle1.msg_count.Response_Data::1          456                      
-system.ruby.network.routers02.throttle1.msg_count.Response_Control::1        24014                      
-system.ruby.network.routers02.throttle1.msg_count.Response_Control::2        75307                      
-system.ruby.network.routers02.throttle1.msg_count.Writeback_Data::0        13836                      
-system.ruby.network.routers02.throttle1.msg_count.Writeback_Data::1        49347                      
-system.ruby.network.routers02.throttle1.msg_count.Writeback_Control::0        25322                      
-system.ruby.network.routers02.throttle1.msg_bytes.Control::0       607856                      
-system.ruby.network.routers02.throttle1.msg_bytes.Response_Data::1        32832                      
-system.ruby.network.routers02.throttle1.msg_bytes.Response_Control::1       192112                      
-system.ruby.network.routers02.throttle1.msg_bytes.Response_Control::2       602456                      
-system.ruby.network.routers02.throttle1.msg_bytes.Writeback_Data::0       996192                      
-system.ruby.network.routers02.throttle1.msg_bytes.Writeback_Data::1      3552984                      
-system.ruby.network.routers02.throttle1.msg_bytes.Writeback_Control::0       202576                      
-system.ruby.network.routers03.throttle0.link_utilization     5.514392                      
-system.ruby.network.routers03.throttle0.msg_count.Request_Control::2        73906                      
-system.ruby.network.routers03.throttle0.msg_count.Response_Data::1        76362                      
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+system.ruby.network.routers05.throttle1.link_utilization     5.357508                      
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+system.ruby.network.routers06.throttle0.link_utilization     5.475821                      
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+system.ruby.network.routers06.throttle1.msg_bytes.Writeback_Control::0       202416                      
+system.ruby.network.routers07.throttle0.link_utilization     5.479078                      
+system.ruby.network.routers07.throttle0.msg_count.Request_Control::2        75301                      
+system.ruby.network.routers07.throttle0.msg_count.Response_Data::1        77686                      
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+system.ruby.network.routers07.throttle0.msg_bytes.Request_Control::2       602408                      
+system.ruby.network.routers07.throttle0.msg_bytes.Response_Data::1      5593392                      
+system.ruby.network.routers07.throttle0.msg_bytes.Response_Control::1       317984                      
+system.ruby.network.routers07.throttle1.link_utilization     5.325094                      
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+system.ruby.network.routers07.throttle1.msg_count.Response_Data::1          521                      
+system.ruby.network.routers07.throttle1.msg_count.Response_Control::1        24575                      
+system.ruby.network.routers07.throttle1.msg_count.Response_Control::2        77070                      
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+system.ruby.network.routers07.throttle1.msg_bytes.Control::0       621504                      
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+system.ruby.network.routers07.throttle1.msg_bytes.Response_Control::1       196600                      
+system.ruby.network.routers07.throttle1.msg_bytes.Response_Control::2       616560                      
+system.ruby.network.routers07.throttle1.msg_bytes.Writeback_Data::0      1029384                      
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+system.ruby.network.routers07.throttle1.msg_bytes.Writeback_Control::0       203600                      
+system.ruby.network.routers08.throttle0.link_utilization    83.816666                      
+system.ruby.network.routers08.throttle0.msg_count.Control::0       621575                      
+system.ruby.network.routers08.throttle0.msg_count.Response_Data::1       617299                      
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+system.ruby.network.routers08.throttle1.link_utilization    63.667686                      
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+system.ruby.network.routers08.throttle1.msg_bytes.Response_Control::1      5699392                      
+system.ruby.network.routers09.throttle0.link_utilization    20.188695                      
+system.ruby.network.routers09.throttle0.msg_count.Control::0       616128                      
+system.ruby.network.routers09.throttle0.msg_count.Response_Data::1       220989                      
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+system.ruby.network.routers09.throttle0.msg_bytes.Control::0      4929024                      
+system.ruby.network.routers09.throttle0.msg_bytes.Response_Data::1     15911208                      
+system.ruby.network.routers09.throttle0.msg_bytes.Response_Control::1      3161032                      
+system.ruby.network.routers09.throttle1.link_utilization    41.460100                      
+system.ruby.network.routers09.throttle1.msg_count.Response_Data::1       616122                      
+system.ruby.network.routers09.throttle1.msg_count.Response_Control::1       616115                      
+system.ruby.network.routers09.throttle1.msg_bytes.Response_Data::1     44360784                      
+system.ruby.network.routers09.throttle1.msg_bytes.Response_Control::1      4928920                      
+system.ruby.network.routers10.throttle0.link_utilization     5.474139                      
+system.ruby.network.routers10.throttle0.msg_count.Request_Control::2        75225                      
+system.ruby.network.routers10.throttle0.msg_count.Response_Data::1        77614                      
+system.ruby.network.routers10.throttle0.msg_count.Response_Control::1        39738                      
+system.ruby.network.routers10.throttle0.msg_bytes.Request_Control::2       601800                      
+system.ruby.network.routers10.throttle0.msg_bytes.Response_Data::1      5588208                      
+system.ruby.network.routers10.throttle0.msg_bytes.Response_Control::1       317904                      
+system.ruby.network.routers10.throttle1.link_utilization     5.467598                      
+system.ruby.network.routers10.throttle1.msg_count.Request_Control::2        75182                      
+system.ruby.network.routers10.throttle1.msg_count.Response_Data::1        77547                      
+system.ruby.network.routers10.throttle1.msg_count.Response_Control::1        39412                      
+system.ruby.network.routers10.throttle1.msg_bytes.Request_Control::2       601456                      
+system.ruby.network.routers10.throttle1.msg_bytes.Response_Data::1      5583384                      
+system.ruby.network.routers10.throttle1.msg_bytes.Response_Control::1       315296                      
+system.ruby.network.routers10.throttle2.link_utilization     5.481655                      
+system.ruby.network.routers10.throttle2.msg_count.Request_Control::2        75340                      
+system.ruby.network.routers10.throttle2.msg_count.Response_Data::1        77717                      
+system.ruby.network.routers10.throttle2.msg_count.Response_Control::1        39813                      
+system.ruby.network.routers10.throttle2.msg_bytes.Request_Control::2       602720                      
+system.ruby.network.routers10.throttle2.msg_bytes.Response_Data::1      5595624                      
+system.ruby.network.routers10.throttle2.msg_bytes.Response_Control::1       318504                      
+system.ruby.network.routers10.throttle3.link_utilization     5.482126                      
+system.ruby.network.routers10.throttle3.msg_count.Request_Control::2        75338                      
+system.ruby.network.routers10.throttle3.msg_count.Response_Data::1        77748                      
+system.ruby.network.routers10.throttle3.msg_count.Response_Control::1        39606                      
+system.ruby.network.routers10.throttle3.msg_bytes.Request_Control::2       602704                      
+system.ruby.network.routers10.throttle3.msg_bytes.Response_Data::1      5597856                      
+system.ruby.network.routers10.throttle3.msg_bytes.Response_Control::1       316848                      
+system.ruby.network.routers10.throttle4.link_utilization     5.452605                      
+system.ruby.network.routers10.throttle4.msg_count.Request_Control::2        74942                      
+system.ruby.network.routers10.throttle4.msg_count.Response_Data::1        77334                      
+system.ruby.network.routers10.throttle4.msg_count.Response_Control::1        39341                      
+system.ruby.network.routers10.throttle4.msg_bytes.Request_Control::2       599536                      
+system.ruby.network.routers10.throttle4.msg_bytes.Response_Data::1      5568048                      
+system.ruby.network.routers10.throttle4.msg_bytes.Response_Control::1       314728                      
+system.ruby.network.routers10.throttle5.link_utilization     5.518323                      
+system.ruby.network.routers10.throttle5.msg_count.Request_Control::2        75756                      
+system.ruby.network.routers10.throttle5.msg_count.Response_Data::1        78248                      
+system.ruby.network.routers10.throttle5.msg_count.Response_Control::1        40068                      
+system.ruby.network.routers10.throttle5.msg_bytes.Request_Control::2       606048                      
+system.ruby.network.routers10.throttle5.msg_bytes.Response_Data::1      5633856                      
+system.ruby.network.routers10.throttle5.msg_bytes.Response_Control::1       320544                      
+system.ruby.network.routers10.throttle6.link_utilization     5.475821                      
+system.ruby.network.routers10.throttle6.msg_count.Request_Control::2        75223                      
+system.ruby.network.routers10.throttle6.msg_count.Response_Data::1        77659                      
+system.ruby.network.routers10.throttle6.msg_count.Response_Control::1        39585                      
+system.ruby.network.routers10.throttle6.msg_bytes.Request_Control::2       601784                      
+system.ruby.network.routers10.throttle6.msg_bytes.Response_Data::1      5591448                      
+system.ruby.network.routers10.throttle6.msg_bytes.Response_Control::1       316680                      
+system.ruby.network.routers10.throttle7.link_utilization     5.479078                      
+system.ruby.network.routers10.throttle7.msg_count.Request_Control::2        75301                      
+system.ruby.network.routers10.throttle7.msg_count.Response_Data::1        77686                      
+system.ruby.network.routers10.throttle7.msg_count.Response_Control::1        39748                      
+system.ruby.network.routers10.throttle7.msg_bytes.Request_Control::2       602408                      
+system.ruby.network.routers10.throttle7.msg_bytes.Response_Data::1      5593392                      
+system.ruby.network.routers10.throttle7.msg_bytes.Response_Control::1       317984                      
+system.ruby.network.routers10.throttle8.link_utilization    83.816693                      
+system.ruby.network.routers10.throttle8.msg_count.Control::0       621575                      
+system.ruby.network.routers10.throttle8.msg_count.Response_Data::1       617299                      
+system.ruby.network.routers10.throttle8.msg_count.Response_Control::1       813811                      
+system.ruby.network.routers10.throttle8.msg_count.Response_Control::2       616516                      
+system.ruby.network.routers10.throttle8.msg_count.Writeback_Data::0       114423                      
+system.ruby.network.routers10.throttle8.msg_count.Writeback_Data::1       401708                      
+system.ruby.network.routers10.throttle8.msg_count.Writeback_Control::0       202881                      
+system.ruby.network.routers10.throttle8.msg_bytes.Control::0      4972600                      
+system.ruby.network.routers10.throttle8.msg_bytes.Response_Data::1     44445528                      
+system.ruby.network.routers10.throttle8.msg_bytes.Response_Control::1      6510488                      
+system.ruby.network.routers10.throttle8.msg_bytes.Response_Control::2      4932128                      
+system.ruby.network.routers10.throttle8.msg_bytes.Writeback_Data::0      8238456                      
+system.ruby.network.routers10.throttle8.msg_bytes.Writeback_Data::1     28922976                      
+system.ruby.network.routers10.throttle8.msg_bytes.Writeback_Control::0      1623048                      
+system.ruby.network.routers10.throttle9.link_utilization    20.188695                      
+system.ruby.network.routers10.throttle9.msg_count.Control::0       616128                      
+system.ruby.network.routers10.throttle9.msg_count.Response_Data::1       220989                      
+system.ruby.network.routers10.throttle9.msg_count.Response_Control::1       395129                      
+system.ruby.network.routers10.throttle9.msg_bytes.Control::0      4929024                      
+system.ruby.network.routers10.throttle9.msg_bytes.Response_Data::1     15911208                      
+system.ruby.network.routers10.throttle9.msg_bytes.Response_Control::1      3161032                      
 system.ruby.delayVCHist.vnet_0::bucket_size         1024                       # delay histogram for vnet_0
 system.ruby.delayVCHist.vnet_0::max_bucket        10239                       # delay histogram for vnet_0
-system.ruby.delayVCHist.vnet_0::samples       1525319                       # delay histogram for vnet_0
-system.ruby.delayVCHist.vnet_0::mean       436.653207                       # delay histogram for vnet_0
-system.ruby.delayVCHist.vnet_0::stdev      606.114709                       # delay histogram for vnet_0
-system.ruby.delayVCHist.vnet_0           |     1261085     82.68%     82.68% |      228712     14.99%     97.67% |       33514      2.20%     99.87% |        1886      0.12%     99.99% |          92      0.01%    100.00% |          18      0.00%    100.00% |           9      0.00%    100.00% |           3      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for vnet_0
-system.ruby.delayVCHist.vnet_0::total         1525319                       # delay histogram for vnet_0
+system.ruby.delayVCHist.vnet_0::samples       1555371                       # delay histogram for vnet_0
+system.ruby.delayVCHist.vnet_0::mean       430.379487                       # delay histogram for vnet_0
+system.ruby.delayVCHist.vnet_0::stdev      599.375282                       # delay histogram for vnet_0
+system.ruby.delayVCHist.vnet_0           |     1294316     83.22%     83.22% |      226078     14.54%     97.75% |       33026      2.12%     99.87% |        1833      0.12%     99.99% |          87      0.01%    100.00% |          19      0.00%    100.00% |           6      0.00%    100.00% |           5      0.00%    100.00% |           1      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for vnet_0
+system.ruby.delayVCHist.vnet_0::total         1555371                       # delay histogram for vnet_0
 system.ruby.delayVCHist.vnet_1::bucket_size            8                       # delay histogram for vnet_1
 system.ruby.delayVCHist.vnet_1::max_bucket           79                       # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::samples       2716111                       # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::mean         2.646488                       # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::stdev        4.287866                       # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1           |     2267179     83.47%     83.47% |      385375     14.19%     97.66% |       58403      2.15%     99.81% |        4927      0.18%     99.99% |         220      0.01%    100.00% |           7      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::total         2716111                       # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1::samples       2771681                       # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1::mean         2.627178                       # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1::stdev        4.263769                       # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1           |     2317910     83.63%     83.63% |      390114     14.07%     97.70% |       58568      2.11%     99.82% |        4852      0.18%     99.99% |         227      0.01%    100.00% |          10      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1::total         2771681                       # delay histogram for vnet_1
 system.ruby.delayVCHist.vnet_2::bucket_size            1                       # delay histogram for vnet_2
 system.ruby.delayVCHist.vnet_2::max_bucket            9                       # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::samples        589687                       # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::mean         0.009836                       # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::stdev        0.140055                       # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2           |      586790     99.51%     99.51% |           0      0.00%     99.51% |        2894      0.49%    100.00% |           0      0.00%    100.00% |           3      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::total          589687                       # delay histogram for vnet_2
+system.ruby.delayVCHist.vnet_2::samples        602307                       # delay histogram for vnet_2
+system.ruby.delayVCHist.vnet_2::mean         0.009879                       # delay histogram for vnet_2
+system.ruby.delayVCHist.vnet_2::stdev        0.140403                       # delay histogram for vnet_2
+system.ruby.delayVCHist.vnet_2           |      599336     99.51%     99.51% |           0      0.00%     99.51% |        2967      0.49%    100.00% |           0      0.00%    100.00% |           4      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for vnet_2
+system.ruby.delayVCHist.vnet_2::total          602307                       # delay histogram for vnet_2
 system.ruby.LD.latency_hist::bucket_size          512                      
 system.ruby.LD.latency_hist::max_bucket          5119                      
-system.ruby.LD.latency_hist::samples           395022                      
-system.ruby.LD.latency_hist::mean         1526.257907                      
-system.ruby.LD.latency_hist::gmean        1178.948125                      
-system.ruby.LD.latency_hist::stdev         896.605628                      
-system.ruby.LD.latency_hist              |       67167     17.00%     17.00% |       71841     18.19%     35.19% |       64604     16.35%     51.54% |       63098     15.97%     67.52% |       66230     16.77%     84.28% |       48099     12.18%     96.46% |       13081      3.31%     99.77% |         895      0.23%    100.00% |           7      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.LD.latency_hist::total             395022                      
+system.ruby.LD.latency_hist::samples           399945                      
+system.ruby.LD.latency_hist::mean         1530.593369                      
+system.ruby.LD.latency_hist::gmean        1160.417441                      
+system.ruby.LD.latency_hist::stdev         924.127804                      
+system.ruby.LD.latency_hist              |       73625     18.41%     18.41% |       71506     17.88%     36.29% |       59841     14.96%     51.25% |       59858     14.97%     66.22% |       66785     16.70%     82.92% |       52514     13.13%     96.05% |       14850      3.71%     99.76% |         957      0.24%    100.00% |           9      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.latency_hist::total             399945                      
 system.ruby.LD.hit_latency_hist::bucket_size            1                      
 system.ruby.LD.hit_latency_hist::max_bucket            9                      
-system.ruby.LD.hit_latency_hist::samples            6                      
+system.ruby.LD.hit_latency_hist::samples            9                      
 system.ruby.LD.hit_latency_hist::mean               3                      
 system.ruby.LD.hit_latency_hist::gmean       3.000000                      
-system.ruby.LD.hit_latency_hist          |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           6    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.LD.hit_latency_hist::total              6                      
+system.ruby.LD.hit_latency_hist          |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           9    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.hit_latency_hist::total              9                      
 system.ruby.LD.miss_latency_hist::bucket_size          512                      
 system.ruby.LD.miss_latency_hist::max_bucket         5119                      
-system.ruby.LD.miss_latency_hist::samples       395016                      
-system.ruby.LD.miss_latency_hist::mean    1526.281044                      
-system.ruby.LD.miss_latency_hist::gmean   1179.055104                      
-system.ruby.LD.miss_latency_hist::stdev    896.592783                      
-system.ruby.LD.miss_latency_hist         |       67161     17.00%     17.00% |       71841     18.19%     35.19% |       64604     16.35%     51.54% |       63098     15.97%     67.52% |       66230     16.77%     84.28% |       48099     12.18%     96.46% |       13081      3.31%     99.77% |         895      0.23%    100.00% |           7      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.LD.miss_latency_hist::total        395016                      
+system.ruby.LD.miss_latency_hist::samples       399936                      
+system.ruby.LD.miss_latency_hist::mean    1530.627745                      
+system.ruby.LD.miss_latency_hist::gmean   1160.573034                      
+system.ruby.LD.miss_latency_hist::stdev    924.109789                      
+system.ruby.LD.miss_latency_hist         |       73616     18.41%     18.41% |       71506     17.88%     36.29% |       59841     14.96%     51.25% |       59858     14.97%     66.22% |       66785     16.70%     82.91% |       52514     13.13%     96.05% |       14850      3.71%     99.76% |         957      0.24%    100.00% |           9      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.miss_latency_hist::total        399936                      
 system.ruby.ST.latency_hist::bucket_size          512                      
 system.ruby.ST.latency_hist::max_bucket          5119                      
-system.ruby.ST.latency_hist::samples           213616                      
-system.ruby.ST.latency_hist::mean         1527.002743                      
-system.ruby.ST.latency_hist::gmean        1180.113141                      
-system.ruby.ST.latency_hist::stdev         895.963161                      
-system.ruby.ST.latency_hist              |       36156     16.93%     16.93% |       38994     18.25%     35.18% |       34943     16.36%     51.54% |       34153     15.99%     67.53% |       35815     16.77%     84.29% |       26040     12.19%     96.48% |        7013      3.28%     99.76% |         495      0.23%    100.00% |           7      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.ST.latency_hist::total             213616                      
+system.ruby.ST.latency_hist::samples           221620                      
+system.ruby.ST.latency_hist::mean         1528.578535                      
+system.ruby.ST.latency_hist::gmean        1157.593457                      
+system.ruby.ST.latency_hist::stdev         925.343815                      
+system.ruby.ST.latency_hist              |       40981     18.49%     18.49% |       39660     17.90%     36.39% |       33332     15.04%     51.43% |       32999     14.89%     66.32% |       36892     16.65%     82.96% |       28932     13.05%     96.02% |        8258      3.73%     99.74% |         557      0.25%    100.00% |           9      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.latency_hist::total             221620                      
 system.ruby.ST.hit_latency_hist::bucket_size            1                      
 system.ruby.ST.hit_latency_hist::max_bucket            9                      
 system.ruby.ST.hit_latency_hist::samples            3                      
@@ -757,211 +757,211 @@ system.ruby.ST.hit_latency_hist          |           0      0.00%      0.00% |
 system.ruby.ST.hit_latency_hist::total              3                      
 system.ruby.ST.miss_latency_hist::bucket_size          512                      
 system.ruby.ST.miss_latency_hist::max_bucket         5119                      
-system.ruby.ST.miss_latency_hist::samples       213613                      
-system.ruby.ST.miss_latency_hist::mean    1527.024146                      
-system.ruby.ST.miss_latency_hist::gmean   1180.212168                      
-system.ruby.ST.miss_latency_hist::stdev    895.951249                      
-system.ruby.ST.miss_latency_hist         |       36153     16.92%     16.92% |       38994     18.25%     35.18% |       34943     16.36%     51.54% |       34153     15.99%     67.53% |       35815     16.77%     84.29% |       26040     12.19%     96.48% |        7013      3.28%     99.76% |         495      0.23%    100.00% |           7      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.ST.miss_latency_hist::total        213613                      
-system.ruby.L1Cache_Controller.Load      |       49252     12.47%     12.47% |       49194     12.45%     24.92% |       49273     12.47%     37.39% |       49508     12.53%     49.93% |       49535     12.54%     62.46% |       49268     12.47%     74.94% |       49241     12.46%     87.40% |       49772     12.60%    100.00%
-system.ruby.L1Cache_Controller.Load::total       395043                      
-system.ruby.L1Cache_Controller.Store     |       26995     12.64%     12.64% |       26908     12.60%     25.23% |       26710     12.50%     37.73% |       26861     12.57%     50.31% |       26500     12.40%     62.71% |       26362     12.34%     75.05% |       26514     12.41%     87.46% |       26781     12.54%    100.00%
-system.ruby.L1Cache_Controller.Store::total       213631                      
-system.ruby.L1Cache_Controller.Inv       |       73359     12.50%     12.50% |       73446     12.52%     25.02% |       73361     12.50%     37.52% |       73535     12.53%     50.05% |       73248     12.48%     62.53% |       72966     12.43%     74.97% |       73104     12.46%     87.42% |       73798     12.58%    100.00%
-system.ruby.L1Cache_Controller.Inv::total       586817                      
-system.ruby.L1Cache_Controller.L1_Replacement |      531811     12.53%     12.53% |      530092     12.49%     25.02% |      529431     12.47%     37.49% |      530614     12.50%     49.99% |      530965     12.51%     62.50% |      529839     12.48%     74.98% |      528537     12.45%     87.44% |      533293     12.56%    100.00%
-system.ruby.L1Cache_Controller.L1_Replacement::total      4244582                      
-system.ruby.L1Cache_Controller.Fwd_GETX  |         236     13.86%     13.86% |         211     12.39%     26.25% |         210     12.33%     38.58% |         225     13.21%     51.79% |         211     12.39%     64.18% |         216     12.68%     76.86% |         180     10.57%     87.43% |         214     12.57%    100.00%
-system.ruby.L1Cache_Controller.Fwd_GETX::total         1703                      
-system.ruby.L1Cache_Controller.Fwd_GETS  |         157     13.45%     13.45% |         164     14.05%     27.51% |         123     10.54%     38.05% |         146     12.51%     50.56% |         141     12.08%     62.64% |         138     11.83%     74.46% |         147     12.60%     87.06% |         151     12.94%    100.00%
-system.ruby.L1Cache_Controller.Fwd_GETS::total         1167                      
-system.ruby.L1Cache_Controller.Data      |           1      9.09%      9.09% |           2     18.18%     27.27% |           2     18.18%     45.45% |           2     18.18%     63.64% |           2     18.18%     81.82% |           2     18.18%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.L1Cache_Controller.Data::total           11                      
-system.ruby.L1Cache_Controller.Data_Exclusive |       48438     12.46%     12.46% |       48471     12.47%     24.93% |       48461     12.47%     37.39% |       48749     12.54%     49.93% |       48742     12.54%     62.47% |       48430     12.46%     74.93% |       48444     12.46%     87.39% |       49018     12.61%    100.00%
-system.ruby.L1Cache_Controller.Data_Exclusive::total       388753                      
-system.ruby.L1Cache_Controller.DataS_fromL1 |         161     13.80%     13.80% |         121     10.37%     24.16% |         137     11.74%     35.90% |         142     12.17%     48.07% |         154     13.20%     61.27% |         167     14.31%     75.58% |         141     12.08%     87.66% |         144     12.34%    100.00%
-system.ruby.L1Cache_Controller.DataS_fromL1::total         1167                      
-system.ruby.L1Cache_Controller.Data_all_Acks |       27643     12.64%     12.64% |       27501     12.57%     25.21% |       27378     12.52%     37.73% |       27469     12.56%     50.29% |       27133     12.41%     62.70% |       27025     12.36%     75.06% |       27162     12.42%     87.48% |       27387     12.52%    100.00%
-system.ruby.L1Cache_Controller.Data_all_Acks::total       218698                      
-system.ruby.L1Cache_Controller.Ack       |           1      9.09%      9.09% |           2     18.18%     27.27% |           2     18.18%     45.45% |           2     18.18%     63.64% |           2     18.18%     81.82% |           2     18.18%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.L1Cache_Controller.Ack::total           11                      
-system.ruby.L1Cache_Controller.Ack_all   |           1      9.09%      9.09% |           2     18.18%     27.27% |           2     18.18%     45.45% |           2     18.18%     63.64% |           2     18.18%     81.82% |           2     18.18%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.L1Cache_Controller.Ack_all::total           11                      
-system.ruby.L1Cache_Controller.WB_Ack    |       39272     12.54%     12.54% |       39144     12.50%     25.04% |       39156     12.50%     37.54% |       39476     12.61%     50.15% |       39064     12.47%     62.62% |       38757     12.38%     75.00% |       38627     12.33%     87.34% |       39657     12.66%    100.00%
-system.ruby.L1Cache_Controller.WB_Ack::total       313153                      
-system.ruby.L1Cache_Controller.NP.Load   |       49241     12.47%     12.47% |       49181     12.45%     24.92% |       49262     12.47%     37.39% |       49502     12.53%     49.92% |       49529     12.54%     62.46% |       49255     12.47%     74.94% |       49238     12.47%     87.40% |       49760     12.60%    100.00%
-system.ruby.L1Cache_Controller.NP.Load::total       394968                      
-system.ruby.L1Cache_Controller.NP.Store  |       26992     12.64%     12.64% |       26905     12.60%     25.23% |       26705     12.50%     37.74% |       26855     12.57%     50.31% |       26496     12.40%     62.71% |       26357     12.34%     75.05% |       26509     12.41%     87.47% |       26773     12.53%    100.00%
-system.ruby.L1Cache_Controller.NP.Store::total       213592                      
-system.ruby.L1Cache_Controller.NP.Inv    |         208     13.88%     13.88% |         188     12.54%     26.42% |         157     10.47%     36.89% |         198     13.21%     50.10% |         184     12.27%     62.37% |         217     14.48%     76.85% |         178     11.87%     88.73% |         169     11.27%    100.00%
-system.ruby.L1Cache_Controller.NP.Inv::total         1499                      
-system.ruby.L1Cache_Controller.I.Load    |           9     14.52%     14.52% |          10     16.13%     30.65% |          10     16.13%     46.77% |           5      8.06%     54.84% |           6      9.68%     64.52% |          10     16.13%     80.65% |           1      1.61%     82.26% |          11     17.74%    100.00%
-system.ruby.L1Cache_Controller.I.Load::total           62                      
-system.ruby.L1Cache_Controller.I.Store   |           3      9.68%      9.68% |           3      9.68%     19.35% |           5     16.13%     35.48% |           4     12.90%     48.39% |           2      6.45%     54.84% |           4     12.90%     67.74% |           3      9.68%     77.42% |           7     22.58%    100.00%
-system.ruby.L1Cache_Controller.I.Store::total           31                      
-system.ruby.L1Cache_Controller.I.L1_Replacement |       36814     12.51%     12.51% |       36809     12.51%     25.02% |       36687     12.47%     37.48% |       36740     12.48%     49.97% |       36828     12.51%     62.48% |       36690     12.47%     74.95% |       36978     12.57%     87.51% |       36747     12.49%    100.00%
-system.ruby.L1Cache_Controller.I.L1_Replacement::total       294293                      
-system.ruby.L1Cache_Controller.S.Inv     |         689     12.91%     12.91% |         611     11.44%     24.35% |         695     13.02%     37.37% |         637     11.93%     49.30% |         678     12.70%     62.00% |         676     12.66%     74.66% |         689     12.91%     87.56% |         664     12.44%    100.00%
-system.ruby.L1Cache_Controller.S.Inv::total         5339                      
-system.ruby.L1Cache_Controller.S.L1_Replacement |         142     13.28%     13.28% |         128     11.97%     25.26% |         118     11.04%     36.30% |         134     12.54%     48.83% |         128     11.97%     60.80% |         158     14.78%     75.58% |         137     12.82%     88.40% |         124     11.60%    100.00%
-system.ruby.L1Cache_Controller.S.L1_Replacement::total         1069                      
-system.ruby.L1Cache_Controller.E.Load    |           1     50.00%     50.00% |           0      0.00%     50.00% |           0      0.00%     50.00% |           0      0.00%     50.00% |           0      0.00%     50.00% |           0      0.00%     50.00% |           0      0.00%     50.00% |           1     50.00%    100.00%
-system.ruby.L1Cache_Controller.E.Load::total            2                      
-system.ruby.L1Cache_Controller.E.Store   |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           1     33.33%     33.33% |           1     33.33%     66.67% |           1     33.33%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.miss_latency_hist::samples       221617                      
+system.ruby.ST.miss_latency_hist::mean    1528.599187                      
+system.ruby.ST.miss_latency_hist::gmean   1157.686785                      
+system.ruby.ST.miss_latency_hist::stdev    925.333054                      
+system.ruby.ST.miss_latency_hist         |       40978     18.49%     18.49% |       39660     17.90%     36.39% |       33332     15.04%     51.43% |       32999     14.89%     66.32% |       36892     16.65%     82.96% |       28932     13.05%     96.02% |        8258      3.73%     99.74% |         557      0.25%    100.00% |           9      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.miss_latency_hist::total        221617                      
+system.ruby.L1Cache_Controller.Load      |       50236     12.56%     12.56% |       49894     12.47%     25.03% |       50153     12.54%     37.57% |       49767     12.44%     50.02% |       49684     12.42%     62.44% |       50353     12.59%     75.03% |       49936     12.48%     87.51% |       49945     12.49%    100.00%
+system.ruby.L1Cache_Controller.Load::total       399968                      
+system.ruby.L1Cache_Controller.Store     |       27386     12.36%     12.36% |       27661     12.48%     24.84% |       27570     12.44%     37.28% |       27987     12.63%     49.90% |       27654     12.48%     62.38% |       27899     12.59%     74.97% |       27728     12.51%     87.48% |       27746     12.52%    100.00%
+system.ruby.L1Cache_Controller.Store::total       221631                      
+system.ruby.L1Cache_Controller.Inv       |       74856     12.49%     12.49% |       74820     12.48%     24.97% |       74997     12.51%     37.48% |       74956     12.50%     49.99% |       74597     12.44%     62.43% |       75407     12.58%     75.01% |       74858     12.49%     87.50% |       74930     12.50%    100.00%
+system.ruby.L1Cache_Controller.Inv::total       599421                      
+system.ruby.L1Cache_Controller.L1_Replacement |      542695     12.51%     12.51% |      541445     12.48%     24.99% |      542478     12.51%     37.50% |      543601     12.53%     50.03% |      541049     12.47%     62.50% |      543626     12.53%     75.03% |      541855     12.49%     87.52% |      541193     12.48%    100.00%
+system.ruby.L1Cache_Controller.L1_Replacement::total      4337942                      
+system.ruby.L1Cache_Controller.Fwd_GETX  |         217     12.70%     12.70% |         220     12.87%     25.57% |         202     11.82%     37.39% |         225     13.17%     50.56% |         192     11.23%     61.79% |         220     12.87%     74.66% |         212     12.40%     87.07% |         221     12.93%    100.00%
+system.ruby.L1Cache_Controller.Fwd_GETX::total         1709                      
+system.ruby.L1Cache_Controller.Fwd_GETS  |         152     12.91%     12.91% |         142     12.06%     24.98% |         141     11.98%     36.96% |         157     13.34%     50.30% |         153     13.00%     63.30% |         129     10.96%     74.26% |         153     13.00%     87.26% |         150     12.74%    100.00%
+system.ruby.L1Cache_Controller.Fwd_GETS::total         1177                      
+system.ruby.L1Cache_Controller.Data      |           1     12.50%     12.50% |           1     12.50%     25.00% |           2     25.00%     50.00% |           2     25.00%     75.00% |           0      0.00%     75.00% |           1     12.50%     87.50% |           0      0.00%     87.50% |           1     12.50%    100.00%
+system.ruby.L1Cache_Controller.Data::total            8                      
+system.ruby.L1Cache_Controller.Data_Exclusive |       49440     12.56%     12.56% |       49131     12.48%     25.04% |       49410     12.55%     37.59% |       48945     12.43%     50.02% |       48917     12.42%     62.44% |       49564     12.59%     75.03% |       49152     12.48%     87.51% |       49164     12.49%    100.00%
+system.ruby.L1Cache_Controller.Data_Exclusive::total       393723                      
+system.ruby.L1Cache_Controller.DataS_fromL1 |         142     12.06%     12.06% |         147     12.49%     24.55% |         130     11.05%     35.60% |         156     13.25%     48.85% |         135     11.47%     60.32% |         153     13.00%     73.32% |         154     13.08%     86.41% |         160     13.59%    100.00%
+system.ruby.L1Cache_Controller.DataS_fromL1::total         1177                      
+system.ruby.L1Cache_Controller.Data_all_Acks |       28031     12.37%     12.37% |       28268     12.47%     24.84% |       28175     12.43%     37.27% |       28645     12.64%     49.91% |       28282     12.48%     62.39% |       28530     12.59%     74.98% |       28353     12.51%     87.49% |       28361     12.51%    100.00%
+system.ruby.L1Cache_Controller.Data_all_Acks::total       226645                      
+system.ruby.L1Cache_Controller.Ack       |           1     12.50%     12.50% |           1     12.50%     25.00% |           2     25.00%     50.00% |           2     25.00%     75.00% |           0      0.00%     75.00% |           1     12.50%     87.50% |           0      0.00%     87.50% |           1     12.50%    100.00%
+system.ruby.L1Cache_Controller.Ack::total            8                      
+system.ruby.L1Cache_Controller.Ack_all   |           1     12.50%     12.50% |           1     12.50%     25.00% |           2     25.00%     50.00% |           2     25.00%     75.00% |           0      0.00%     75.00% |           1     12.50%     87.50% |           0      0.00%     87.50% |           1     12.50%    100.00%
+system.ruby.L1Cache_Controller.Ack_all::total            8                      
+system.ruby.L1Cache_Controller.WB_Ack    |       39736     12.52%     12.52% |       39410     12.42%     24.94% |       39809     12.55%     37.49% |       39602     12.48%     49.97% |       39341     12.40%     62.37% |       40066     12.63%     75.00% |       39585     12.48%     87.47% |       39746     12.53%    100.00%
+system.ruby.L1Cache_Controller.WB_Ack::total       317295                      
+system.ruby.L1Cache_Controller.NP.Load   |       50223     12.56%     12.56% |       49884     12.47%     25.03% |       50144     12.54%     37.57% |       49760     12.44%     50.02% |       49674     12.42%     62.44% |       50340     12.59%     75.03% |       49925     12.48%     87.51% |       49934     12.49%    100.00%
+system.ruby.L1Cache_Controller.NP.Load::total       399884                      
+system.ruby.L1Cache_Controller.NP.Store  |       27380     12.36%     12.36% |       27654     12.48%     24.84% |       27568     12.44%     37.28% |       27981     12.63%     49.91% |       27651     12.48%     62.38% |       27892     12.59%     74.97% |       27718     12.51%     87.48% |       27743     12.52%    100.00%
+system.ruby.L1Cache_Controller.NP.Store::total       221587                      
+system.ruby.L1Cache_Controller.NP.Inv    |         202     12.95%     12.95% |         197     12.63%     25.58% |         189     12.12%     37.69% |         201     12.88%     50.58% |         175     11.22%     61.79% |         194     12.44%     74.23% |         210     13.46%     87.69% |         192     12.31%    100.00%
+system.ruby.L1Cache_Controller.NP.Inv::total         1560                      
+system.ruby.L1Cache_Controller.I.Load    |          10     15.15%     15.15% |           8     12.12%     27.27% |           7     10.61%     37.88% |           6      9.09%     46.97% |           9     13.64%     60.61% |          10     15.15%     75.76% |           8     12.12%     87.88% |           8     12.12%    100.00%
+system.ruby.L1Cache_Controller.I.Load::total           66                      
+system.ruby.L1Cache_Controller.I.Store   |           5     13.16%     13.16% |           5     13.16%     26.32% |           1      2.63%     28.95% |           5     13.16%     42.11% |           3      7.89%     50.00% |           6     15.79%     65.79% |          10     26.32%     92.11% |           3      7.89%    100.00%
+system.ruby.L1Cache_Controller.I.Store::total           38                      
+system.ruby.L1Cache_Controller.I.L1_Replacement |       37717     12.45%     12.45% |       37982     12.53%     24.98% |       37762     12.46%     37.44% |       38005     12.54%     49.98% |       37865     12.49%     62.48% |       38010     12.54%     75.02% |       37909     12.51%     87.53% |       37797     12.47%    100.00%
+system.ruby.L1Cache_Controller.I.L1_Replacement::total       303047                      
+system.ruby.L1Cache_Controller.S.Inv     |         645     12.46%     12.46% |         625     12.07%     24.53% |         615     11.88%     36.40% |         691     13.34%     49.75% |         653     12.61%     62.36% |         646     12.48%     74.84% |         652     12.59%     87.43% |         651     12.57%    100.00%
+system.ruby.L1Cache_Controller.S.Inv::total         5178                      
+system.ruby.L1Cache_Controller.S.L1_Replacement |         145     13.33%     13.33% |         138     12.68%     26.01% |         136     12.50%     38.51% |         128     11.76%     50.28% |         115     10.57%     60.85% |         152     13.97%     74.82% |         145     13.33%     88.14% |         129     11.86%    100.00%
+system.ruby.L1Cache_Controller.S.L1_Replacement::total         1088                      
+system.ruby.L1Cache_Controller.E.Load    |           0      0.00%      0.00% |           0      0.00%      0.00% |           1     16.67%     16.67% |           1     16.67%     33.33% |           0      0.00%     33.33% |           1     16.67%     50.00% |           2     33.33%     83.33% |           1     16.67%    100.00%
+system.ruby.L1Cache_Controller.E.Load::total            6                      
+system.ruby.L1Cache_Controller.E.Store   |           0      0.00%      0.00% |           1     33.33%     33.33% |           1     33.33%     66.67% |           1     33.33%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.L1Cache_Controller.E.Store::total            3                      
-system.ruby.L1Cache_Controller.E.Inv     |       23113     12.44%     12.44% |       23183     12.48%     24.92% |       23083     12.42%     37.34% |       23138     12.45%     49.80% |       23334     12.56%     62.36% |       23218     12.50%     74.86% |       23460     12.63%     87.48% |       23252     12.52%    100.00%
-system.ruby.L1Cache_Controller.E.Inv::total       185781                      
-system.ruby.L1Cache_Controller.E.L1_Replacement |       25258     12.48%     12.48% |       25225     12.46%     24.93% |       25322     12.51%     37.44% |       25551     12.62%     50.06% |       25345     12.52%     62.58% |       25152     12.42%     75.00% |       24925     12.31%     87.31% |       25684     12.69%    100.00%
-system.ruby.L1Cache_Controller.E.L1_Replacement::total       202462                      
-system.ruby.L1Cache_Controller.E.Fwd_GETX |          57     13.41%     13.41% |          57     13.41%     26.82% |          48     11.29%     38.12% |          52     12.24%     50.35% |          49     11.53%     61.88% |          54     12.71%     74.59% |          46     10.82%     85.41% |          62     14.59%    100.00%
-system.ruby.L1Cache_Controller.E.Fwd_GETX::total          425                      
-system.ruby.L1Cache_Controller.E.Fwd_GETS |          10     12.35%     12.35% |           6      7.41%     19.75% |           8      9.88%     29.63% |           8      9.88%     39.51% |          13     16.05%     55.56% |           5      6.17%     61.73% |          12     14.81%     76.54% |          19     23.46%    100.00%
-system.ruby.L1Cache_Controller.E.Fwd_GETS::total           81                      
-system.ruby.L1Cache_Controller.M.Load    |           0      0.00%      0.00% |           3     75.00%     75.00% |           0      0.00%     75.00% |           0      0.00%     75.00% |           0      0.00%     75.00% |           0      0.00%     75.00% |           1     25.00%    100.00% |           0      0.00%    100.00%
-system.ruby.L1Cache_Controller.M.Load::total            4                      
-system.ruby.L1Cache_Controller.M.Inv     |       12878     12.61%     12.61% |       12884     12.61%     25.22% |       12783     12.51%     37.73% |       12837     12.57%     50.30% |       12701     12.43%     62.73% |       12661     12.39%     75.12% |       12709     12.44%     87.56% |       12708     12.44%    100.00%
-system.ruby.L1Cache_Controller.M.Inv::total       102161                      
-system.ruby.L1Cache_Controller.M.L1_Replacement |       14015     12.66%     12.66% |       13920     12.57%     25.23% |       13836     12.50%     37.73% |       13928     12.58%     50.31% |       13720     12.39%     62.71% |       13608     12.29%     75.00% |       13703     12.38%     87.38% |       13974     12.62%    100.00%
-system.ruby.L1Cache_Controller.M.L1_Replacement::total       110704                      
-system.ruby.L1Cache_Controller.M.Fwd_GETX |          39     13.68%     13.68% |          33     11.58%     25.26% |          41     14.39%     39.65% |          37     12.98%     52.63% |          32     11.23%     63.86% |          36     12.63%     76.49% |          30     10.53%     87.02% |          37     12.98%    100.00%
-system.ruby.L1Cache_Controller.M.Fwd_GETX::total          285                      
-system.ruby.L1Cache_Controller.M.Fwd_GETS |          62     13.33%     13.33% |          70     15.05%     28.39% |          49     10.54%     38.92% |          54     11.61%     50.54% |          45      9.68%     60.22% |          57     12.26%     72.47% |          69     14.84%     87.31% |          59     12.69%    100.00%
-system.ruby.L1Cache_Controller.M.Fwd_GETS::total          465                      
-system.ruby.L1Cache_Controller.IS.Inv    |          52     12.97%     12.97% |          54     13.47%     26.43% |          52     12.97%     39.40% |          48     11.97%     51.37% |          44     10.97%     62.34% |          61     15.21%     77.56% |          48     11.97%     89.53% |          42     10.47%    100.00%
-system.ruby.L1Cache_Controller.IS.Inv::total          401                      
-system.ruby.L1Cache_Controller.IS.L1_Replacement |      294115     12.47%     12.47% |      293860     12.46%     24.92% |      293400     12.44%     37.36% |      295550     12.53%     49.89% |      297332     12.60%     62.49% |      295579     12.53%     75.02% |      293015     12.42%     87.44% |      296279     12.56%    100.00%
-system.ruby.L1Cache_Controller.IS.L1_Replacement::total      2359130                      
-system.ruby.L1Cache_Controller.IS.Data_Exclusive |       48438     12.46%     12.46% |       48471     12.47%     24.93% |       48461     12.47%     37.39% |       48749     12.54%     49.93% |       48742     12.54%     62.47% |       48430     12.46%     74.93% |       48444     12.46%     87.39% |       49018     12.61%    100.00%
-system.ruby.L1Cache_Controller.IS.Data_Exclusive::total       388753                      
-system.ruby.L1Cache_Controller.IS.DataS_fromL1 |         161     13.80%     13.80% |         121     10.37%     24.16% |         137     11.74%     35.90% |         142     12.17%     48.07% |         154     13.20%     61.27% |         167     14.31%     75.58% |         141     12.08%     87.66% |         144     12.34%    100.00%
-system.ruby.L1Cache_Controller.IS.DataS_fromL1::total         1167                      
-system.ruby.L1Cache_Controller.IS.Data_all_Acks |         598     12.74%     12.74% |         542     11.54%     24.28% |         619     13.18%     37.47% |         567     12.08%     49.54% |         594     12.65%     62.19% |         605     12.89%     75.08% |         604     12.86%     87.94% |         566     12.06%    100.00%
-system.ruby.L1Cache_Controller.IS.Data_all_Acks::total         4695                      
-system.ruby.L1Cache_Controller.IM.L1_Replacement |      161466     12.64%     12.64% |      160150     12.54%     25.19% |      160068     12.54%     37.72% |      158711     12.43%     50.15% |      157612     12.34%     62.49% |      158652     12.42%     74.92% |      159779     12.51%     87.43% |      160485     12.57%    100.00%
-system.ruby.L1Cache_Controller.IM.L1_Replacement::total      1276923                      
-system.ruby.L1Cache_Controller.IM.Data   |           1      9.09%      9.09% |           2     18.18%     27.27% |           2     18.18%     45.45% |           2     18.18%     63.64% |           2     18.18%     81.82% |           2     18.18%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.L1Cache_Controller.IM.Data::total           11                      
-system.ruby.L1Cache_Controller.IM.Data_all_Acks |       26993     12.64%     12.64% |       26905     12.60%     25.23% |       26707     12.50%     37.74% |       26854     12.57%     50.31% |       26495     12.40%     62.71% |       26359     12.34%     75.05% |       26510     12.41%     87.46% |       26779     12.54%    100.00%
-system.ruby.L1Cache_Controller.IM.Data_all_Acks::total       213602                      
-system.ruby.L1Cache_Controller.SM.Ack    |           1      9.09%      9.09% |           2     18.18%     27.27% |           2     18.18%     45.45% |           2     18.18%     63.64% |           2     18.18%     81.82% |           2     18.18%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.L1Cache_Controller.SM.Ack::total           11                      
-system.ruby.L1Cache_Controller.SM.Ack_all |           1      9.09%      9.09% |           2     18.18%     27.27% |           2     18.18%     45.45% |           2     18.18%     63.64% |           2     18.18%     81.82% |           2     18.18%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.L1Cache_Controller.SM.Ack_all::total           11                      
-system.ruby.L1Cache_Controller.IS_I.L1_Replacement |           1    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.L1Cache_Controller.IS_I.L1_Replacement::total            1                      
-system.ruby.L1Cache_Controller.IS_I.Data_all_Acks |          52     12.97%     12.97% |          54     13.47%     26.43% |          52     12.97%     39.40% |          48     11.97%     51.37% |          44     10.97%     62.34% |          61     15.21%     77.56% |          48     11.97%     89.53% |          42     10.47%    100.00%
-system.ruby.L1Cache_Controller.IS_I.Data_all_Acks::total          401                      
+system.ruby.L1Cache_Controller.E.Inv     |       23729     12.47%     12.47% |       23871     12.54%     25.01% |       23901     12.56%     37.57% |       23696     12.45%     50.02% |       23788     12.50%     62.52% |       23896     12.56%     75.07% |       23793     12.50%     87.57% |       23649     12.43%    100.00%
+system.ruby.L1Cache_Controller.E.Inv::total       190323                      
+system.ruby.L1Cache_Controller.E.L1_Replacement |       25649     12.64%     12.64% |       25189     12.42%     25.06% |       25440     12.54%     37.60% |       25187     12.41%     50.01% |       25067     12.36%     62.37% |       25597     12.62%     74.98% |       25302     12.47%     87.46% |       25450     12.54%    100.00%
+system.ruby.L1Cache_Controller.E.L1_Replacement::total       202881                      
+system.ruby.L1Cache_Controller.E.Fwd_GETX |          53     11.75%     11.75% |          63     13.97%     25.72% |          61     13.53%     39.25% |          55     12.20%     51.44% |          48     10.64%     62.08% |          64     14.19%     76.27% |          50     11.09%     87.36% |          57     12.64%    100.00%
+system.ruby.L1Cache_Controller.E.Fwd_GETX::total          451                      
+system.ruby.L1Cache_Controller.E.Fwd_GETS |           9     14.06%     14.06% |           7     10.94%     25.00% |           7     10.94%     35.94% |           6      9.38%     45.31% |          14     21.88%     67.19% |           6      9.38%     76.56% |           7     10.94%     87.50% |           8     12.50%    100.00%
+system.ruby.L1Cache_Controller.E.Fwd_GETS::total           64                      
+system.ruby.L1Cache_Controller.M.Load    |           0      0.00%      0.00% |           1     33.33%     33.33% |           1     33.33%     66.67% |           0      0.00%     66.67% |           0      0.00%     66.67% |           0      0.00%     66.67% |           1     33.33%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache_Controller.M.Load::total            3                      
+system.ruby.L1Cache_Controller.M.Inv     |       13206     12.40%     12.40% |       13343     12.53%     24.93% |       13115     12.32%     37.25% |       13481     12.66%     49.91% |       13301     12.49%     62.40% |       13334     12.52%     74.92% |       13349     12.54%     87.45% |       13362     12.55%    100.00%
+system.ruby.L1Cache_Controller.M.Inv::total       106491                      
+system.ruby.L1Cache_Controller.M.L1_Replacement |       14088     12.31%     12.31% |       14225     12.43%     24.74% |       14370     12.56%     37.30% |       14417     12.60%     49.90% |       14274     12.47%     62.38% |       14469     12.65%     75.02% |       14283     12.48%     87.51% |       14297     12.49%    100.00%
+system.ruby.L1Cache_Controller.M.L1_Replacement::total       114423                      
+system.ruby.L1Cache_Controller.M.Fwd_GETX |          35     13.73%     13.73% |          31     12.16%     25.88% |          27     10.59%     36.47% |          33     12.94%     49.41% |          26     10.20%     59.61% |          36     14.12%     73.73% |          35     13.73%     87.45% |          32     12.55%    100.00%
+system.ruby.L1Cache_Controller.M.Fwd_GETX::total          255                      
+system.ruby.L1Cache_Controller.M.Fwd_GETS |          56     12.42%     12.42% |          58     12.86%     25.28% |          56     12.42%     37.69% |          55     12.20%     49.89% |          53     11.75%     61.64% |          59     13.08%     74.72% |          59     13.08%     87.80% |          55     12.20%    100.00%
+system.ruby.L1Cache_Controller.M.Fwd_GETS::total          451                      
+system.ruby.L1Cache_Controller.IS.Inv    |          64     13.85%     13.85% |          62     13.42%     27.27% |          52     11.26%     38.53% |          60     12.99%     51.52% |          62     13.42%     64.94% |          53     11.47%     76.41% |          50     10.82%     87.23% |          59     12.77%    100.00%
+system.ruby.L1Cache_Controller.IS.Inv::total          462                      
+system.ruby.L1Cache_Controller.IS.L1_Replacement |      301738     12.61%     12.61% |      299281     12.51%     25.13% |      299379     12.52%     37.64% |      298179     12.47%     50.11% |      298458     12.48%     62.58% |      299615     12.53%     75.11% |      297962     12.46%     87.56% |      297489     12.44%    100.00%
+system.ruby.L1Cache_Controller.IS.L1_Replacement::total      2392101                      
+system.ruby.L1Cache_Controller.IS.Data_Exclusive |       49440     12.56%     12.56% |       49131     12.48%     25.04% |       49410     12.55%     37.59% |       48945     12.43%     50.02% |       48917     12.42%     62.44% |       49564     12.59%     75.03% |       49152     12.48%     87.51% |       49164     12.49%    100.00%
+system.ruby.L1Cache_Controller.IS.Data_Exclusive::total       393723                      
+system.ruby.L1Cache_Controller.IS.DataS_fromL1 |         142     12.06%     12.06% |         147     12.49%     24.55% |         130     11.05%     35.60% |         156     13.25%     48.85% |         135     11.47%     60.32% |         153     13.00%     73.32% |         154     13.08%     86.41% |         160     13.59%    100.00%
+system.ruby.L1Cache_Controller.IS.DataS_fromL1::total         1177                      
+system.ruby.L1Cache_Controller.IS.Data_all_Acks |         583     12.75%     12.75% |         551     12.05%     24.79% |         558     12.20%     36.99% |         602     13.16%     50.15% |         566     12.37%     62.53% |         580     12.68%     75.21% |         577     12.61%     87.82% |         557     12.18%    100.00%
+system.ruby.L1Cache_Controller.IS.Data_all_Acks::total         4574                      
+system.ruby.L1Cache_Controller.IM.L1_Replacement |      163358     12.33%     12.33% |      164630     12.43%     24.76% |      165391     12.49%     37.25% |      167685     12.66%     49.91% |      165270     12.48%     62.39% |      165783     12.52%     74.91% |      166254     12.55%     87.46% |      166031     12.54%    100.00%
+system.ruby.L1Cache_Controller.IM.L1_Replacement::total      1324402                      
+system.ruby.L1Cache_Controller.IM.Data   |           1     12.50%     12.50% |           1     12.50%     25.00% |           2     25.00%     50.00% |           2     25.00%     75.00% |           0      0.00%     75.00% |           1     12.50%     87.50% |           0      0.00%     87.50% |           1     12.50%    100.00%
+system.ruby.L1Cache_Controller.IM.Data::total            8                      
+system.ruby.L1Cache_Controller.IM.Data_all_Acks |       27384     12.36%     12.36% |       27655     12.48%     24.84% |       27565     12.44%     37.27% |       27983     12.63%     49.90% |       27654     12.48%     62.38% |       27897     12.59%     74.97% |       27726     12.51%     87.48% |       27745     12.52%    100.00%
+system.ruby.L1Cache_Controller.IM.Data_all_Acks::total       221609                      
+system.ruby.L1Cache_Controller.SM.Ack    |           1     12.50%     12.50% |           1     12.50%     25.00% |           2     25.00%     50.00% |           2     25.00%     75.00% |           0      0.00%     75.00% |           1     12.50%     87.50% |           0      0.00%     87.50% |           1     12.50%    100.00%
+system.ruby.L1Cache_Controller.SM.Ack::total            8                      
+system.ruby.L1Cache_Controller.SM.Ack_all |           1     12.50%     12.50% |           1     12.50%     25.00% |           2     25.00%     50.00% |           2     25.00%     75.00% |           0      0.00%     75.00% |           1     12.50%     87.50% |           0      0.00%     87.50% |           1     12.50%    100.00%
+system.ruby.L1Cache_Controller.SM.Ack_all::total            8                      
+system.ruby.L1Cache_Controller.IS_I.Data_all_Acks |          64     13.85%     13.85% |          62     13.42%     27.27% |          52     11.26%     38.53% |          60     12.99%     51.52% |          62     13.42%     64.94% |          53     11.47%     76.41% |          50     10.82%     87.23% |          59     12.77%    100.00%
+system.ruby.L1Cache_Controller.IS_I.Data_all_Acks::total          462                      
 system.ruby.L1Cache_Controller.M_I.Load  |           1    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.L1Cache_Controller.M_I.Load::total            1                      
-system.ruby.L1Cache_Controller.M_I.Inv   |       36400     12.49%     12.49% |       36498     12.52%     25.01% |       36564     12.55%     37.56% |       36657     12.58%     50.14% |       36280     12.45%     62.58% |       36116     12.39%     74.98% |       35995     12.35%     87.33% |       36935     12.67%    100.00%
-system.ruby.L1Cache_Controller.M_I.Inv::total       291445                      
-system.ruby.L1Cache_Controller.M_I.Fwd_GETX |         140     14.10%     14.10% |         121     12.19%     26.28% |         121     12.19%     38.47% |         136     13.70%     52.17% |         130     13.09%     65.26% |         126     12.69%     77.95% |         104     10.47%     88.42% |         115     11.58%    100.00%
-system.ruby.L1Cache_Controller.M_I.Fwd_GETX::total          993                      
-system.ruby.L1Cache_Controller.M_I.Fwd_GETS |          85     13.69%     13.69% |          88     14.17%     27.86% |          66     10.63%     38.49% |          84     13.53%     52.01% |          83     13.37%     65.38% |          76     12.24%     77.62% |          66     10.63%     88.24% |          73     11.76%    100.00%
-system.ruby.L1Cache_Controller.M_I.Fwd_GETS::total          621                      
-system.ruby.L1Cache_Controller.M_I.WB_Ack |        2648     13.17%     13.17% |        2438     12.13%     25.29% |        2407     11.97%     37.27% |        2602     12.94%     50.21% |        2572     12.79%     63.00% |        2442     12.15%     75.14% |        2463     12.25%     87.39% |        2535     12.61%    100.00%
-system.ruby.L1Cache_Controller.M_I.WB_Ack::total        20107                      
-system.ruby.L1Cache_Controller.SINK_WB_ACK.Load |           0      0.00%      0.00% |           0      0.00%      0.00% |           1     16.67%     16.67% |           1     16.67%     33.33% |           0      0.00%     33.33% |           3     50.00%     83.33% |           1     16.67%    100.00% |           0      0.00%    100.00%
-system.ruby.L1Cache_Controller.SINK_WB_ACK.Load::total            6                      
-system.ruby.L1Cache_Controller.SINK_WB_ACK.Store |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           2     40.00%     40.00% |           1     20.00%     60.00% |           0      0.00%     60.00% |           1     20.00%     80.00% |           1     20.00%    100.00%
-system.ruby.L1Cache_Controller.SINK_WB_ACK.Store::total            5                      
-system.ruby.L1Cache_Controller.SINK_WB_ACK.Inv |          19      9.95%      9.95% |          28     14.66%     24.61% |          27     14.14%     38.74% |          20     10.47%     49.21% |          27     14.14%     63.35% |          17      8.90%     72.25% |          25     13.09%     85.34% |          28     14.66%    100.00%
-system.ruby.L1Cache_Controller.SINK_WB_ACK.Inv::total          191                      
-system.ruby.L1Cache_Controller.SINK_WB_ACK.WB_Ack |       36624     12.50%     12.50% |       36706     12.53%     25.02% |       36749     12.54%     37.56% |       36874     12.58%     50.15% |       36492     12.45%     62.60% |       36315     12.39%     74.99% |       36164     12.34%     87.33% |       37122     12.67%    100.00%
-system.ruby.L1Cache_Controller.SINK_WB_ACK.WB_Ack::total       293046                      
-system.ruby.L2Cache_Controller.L1_GETS         396762      0.00%      0.00%
-system.ruby.L2Cache_Controller.L1_GETX         216001      0.00%      0.00%
-system.ruby.L2Cache_Controller.L1_PUTX          21849      0.00%      0.00%
-system.ruby.L2Cache_Controller.L1_PUTX_old       297986      0.00%      0.00%
-system.ruby.L2Cache_Controller.L2_Replacement         8404      0.00%      0.00%
-system.ruby.L2Cache_Controller.L2_Replacement_clean      4560569      0.00%      0.00%
-system.ruby.L2Cache_Controller.Mem_Data        603179      0.00%      0.00%
-system.ruby.L2Cache_Controller.Mem_Ack         603168      0.00%      0.00%
-system.ruby.L2Cache_Controller.WB_Data         205785      0.00%      0.00%
-system.ruby.L2Cache_Controller.WB_Data_clean       188987      0.00%      0.00%
-system.ruby.L2Cache_Controller.Ack               3711      0.00%      0.00%
-system.ruby.L2Cache_Controller.Ack_all         189477      0.00%      0.00%
-system.ruby.L2Cache_Controller.Unblock           1167      0.00%      0.00%
-system.ruby.L2Cache_Controller.Exclusive_Unblock       602364      0.00%      0.00%
-system.ruby.L2Cache_Controller.NP.L1_GETS       391290      0.00%      0.00%
-system.ruby.L2Cache_Controller.NP.L1_GETX       211894      0.00%      0.00%
-system.ruby.L2Cache_Controller.NP.L1_PUTX_old       277792      0.00%      0.00%
-system.ruby.L2Cache_Controller.SS.L1_GETS            4      0.00%      0.00%
-system.ruby.L2Cache_Controller.SS.L1_GETX           11      0.00%      0.00%
-system.ruby.L2Cache_Controller.SS.L1_PUTX          437      0.00%      0.00%
+system.ruby.L1Cache_Controller.M_I.Inv   |       36980     12.53%     12.53% |       36704     12.43%     24.96% |       37100     12.57%     37.53% |       36804     12.47%     49.99% |       36592     12.39%     62.39% |       37262     12.62%     75.01% |       36782     12.46%     87.47% |       36993     12.53%    100.00%
+system.ruby.L1Cache_Controller.M_I.Inv::total       295217                      
+system.ruby.L1Cache_Controller.M_I.Fwd_GETX |         129     12.86%     12.86% |         126     12.56%     25.42% |         114     11.37%     36.79% |         137     13.66%     50.45% |         118     11.76%     62.21% |         120     11.96%     74.18% |         127     12.66%     86.84% |         132     13.16%    100.00%
+system.ruby.L1Cache_Controller.M_I.Fwd_GETX::total         1003                      
+system.ruby.L1Cache_Controller.M_I.Fwd_GETS |          87     13.14%     13.14% |          77     11.63%     24.77% |          78     11.78%     36.56% |          96     14.50%     51.06% |          86     12.99%     64.05% |          64      9.67%     73.72% |          87     13.14%     86.86% |          87     13.14%    100.00%
+system.ruby.L1Cache_Controller.M_I.Fwd_GETS::total          662                      
+system.ruby.L1Cache_Controller.M_I.WB_Ack |        2541     12.44%     12.44% |        2507     12.28%     24.72% |        2518     12.33%     37.05% |        2567     12.57%     49.62% |        2545     12.46%     62.08% |        2620     12.83%     74.91% |        2589     12.68%     87.59% |        2535     12.41%    100.00%
+system.ruby.L1Cache_Controller.M_I.WB_Ack::total        20422                      
+system.ruby.L1Cache_Controller.SINK_WB_ACK.Load |           2     25.00%     25.00% |           1     12.50%     37.50% |           0      0.00%     37.50% |           0      0.00%     37.50% |           1     12.50%     50.00% |           2     25.00%     75.00% |           0      0.00%     75.00% |           2     25.00%    100.00%
+system.ruby.L1Cache_Controller.SINK_WB_ACK.Load::total            8                      
+system.ruby.L1Cache_Controller.SINK_WB_ACK.Store |           1     33.33%     33.33% |           1     33.33%     66.67% |           0      0.00%     66.67% |           0      0.00%     66.67% |           0      0.00%     66.67% |           1     33.33%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache_Controller.SINK_WB_ACK.Store::total            3                      
+system.ruby.L1Cache_Controller.SINK_WB_ACK.Inv |          30     15.79%     15.79% |          18      9.47%     25.26% |          25     13.16%     38.42% |          23     12.11%     50.53% |          26     13.68%     64.21% |          22     11.58%     75.79% |          22     11.58%     87.37% |          24     12.63%    100.00%
+system.ruby.L1Cache_Controller.SINK_WB_ACK.Inv::total          190                      
+system.ruby.L1Cache_Controller.SINK_WB_ACK.WB_Ack |       37195     12.53%     12.53% |       36903     12.43%     24.96% |       37291     12.56%     37.52% |       37035     12.48%     50.00% |       36796     12.39%     62.39% |       37446     12.61%     75.00% |       36996     12.46%     87.47% |       37211     12.53%    100.00%
+system.ruby.L1Cache_Controller.SINK_WB_ACK.WB_Ack::total       296873                      
+system.ruby.L2Cache_Controller.L1_GETS         401738      0.00%      0.00%
+system.ruby.L2Cache_Controller.L1_GETX         224009      0.00%      0.00%
+system.ruby.L2Cache_Controller.L1_PUTX          22269      0.00%      0.00%
+system.ruby.L2Cache_Controller.L1_PUTX_old       301959      0.00%      0.00%
+system.ruby.L2Cache_Controller.L2_Replacement         8861      0.00%      0.00%
+system.ruby.L2Cache_Controller.L2_Replacement_clean      4613091      0.00%      0.00%
+system.ruby.L2Cache_Controller.Mem_Data        616121      0.00%      0.00%
+system.ruby.L2Cache_Controller.Mem_Ack         616114      0.00%      0.00%
+system.ruby.L2Cache_Controller.WB_Data         213442      0.00%      0.00%
+system.ruby.L2Cache_Controller.WB_Data_clean       189443      0.00%      0.00%
+system.ruby.L2Cache_Controller.Ack               3694      0.00%      0.00%
+system.ruby.L2Cache_Controller.Ack_all         194003      0.00%      0.00%
+system.ruby.L2Cache_Controller.Unblock           1177      0.00%      0.00%
+system.ruby.L2Cache_Controller.Exclusive_Unblock       615339      0.00%      0.00%
+system.ruby.L2Cache_Controller.NP.L1_GETS       396229      0.00%      0.00%
+system.ruby.L2Cache_Controller.NP.L1_GETX       219899      0.00%      0.00%
+system.ruby.L2Cache_Controller.NP.L1_PUTX_old       281116      0.00%      0.00%
+system.ruby.L2Cache_Controller.SS.L1_GETS            6      0.00%      0.00%
+system.ruby.L2Cache_Controller.SS.L1_GETX            8      0.00%      0.00%
+system.ruby.L2Cache_Controller.SS.L1_PUTX          480      0.00%      0.00%
 system.ruby.L2Cache_Controller.SS.L1_PUTX_old            3      0.00%      0.00%
-system.ruby.L2Cache_Controller.SS.L2_Replacement         1068      0.00%      0.00%
-system.ruby.L2Cache_Controller.SS.L2_Replacement_clean         2629      0.00%      0.00%
-system.ruby.L2Cache_Controller.M.L1_GETS            7      0.00%      0.00%
-system.ruby.L2Cache_Controller.M.L1_GETX            8      0.00%      0.00%
-system.ruby.L2Cache_Controller.M.L2_Replacement         7166      0.00%      0.00%
-system.ruby.L2Cache_Controller.M.L2_Replacement_clean        12926      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT.L1_GETS         1167      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT.L1_GETX         1703      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT.L1_PUTX        20107      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT.L1_PUTX_old          755      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT.L2_Replacement            6      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT.L2_Replacement_clean       579381      0.00%      0.00%
-system.ruby.L2Cache_Controller.M_I.L1_GETS          220      0.00%      0.00%
-system.ruby.L2Cache_Controller.M_I.L1_GETX          138      0.00%      0.00%
-system.ruby.L2Cache_Controller.M_I.L1_PUTX_old        13507      0.00%      0.00%
-system.ruby.L2Cache_Controller.M_I.Mem_Ack       603168      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT_I.WB_Data            4      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT_I.Ack_all            2      0.00%      0.00%
-system.ruby.L2Cache_Controller.MCT_I.L1_GETS           68      0.00%      0.00%
-system.ruby.L2Cache_Controller.MCT_I.L1_GETX           70      0.00%      0.00%
-system.ruby.L2Cache_Controller.MCT_I.L1_PUTX_old         5372      0.00%      0.00%
-system.ruby.L2Cache_Controller.MCT_I.WB_Data       204712      0.00%      0.00%
-system.ruby.L2Cache_Controller.MCT_I.WB_Data_clean       188889      0.00%      0.00%
-system.ruby.L2Cache_Controller.MCT_I.Ack_all       185778      0.00%      0.00%
-system.ruby.L2Cache_Controller.I_I.Ack           2639      0.00%      0.00%
-system.ruby.L2Cache_Controller.I_I.Ack_all         2629      0.00%      0.00%
-system.ruby.L2Cache_Controller.S_I.Ack           1072      0.00%      0.00%
-system.ruby.L2Cache_Controller.S_I.Ack_all         1068      0.00%      0.00%
-system.ruby.L2Cache_Controller.ISS.L1_GETS         2541      0.00%      0.00%
-system.ruby.L2Cache_Controller.ISS.L1_GETX         1297      0.00%      0.00%
-system.ruby.L2Cache_Controller.ISS.L1_PUTX_old          249      0.00%      0.00%
-system.ruby.L2Cache_Controller.ISS.L2_Replacement_clean      2131813      0.00%      0.00%
-system.ruby.L2Cache_Controller.ISS.Mem_Data       388746      0.00%      0.00%
-system.ruby.L2Cache_Controller.IS.L1_GETS           10      0.00%      0.00%
-system.ruby.L2Cache_Controller.IS.L1_GETX            4      0.00%      0.00%
-system.ruby.L2Cache_Controller.IS.L2_Replacement_clean        13821      0.00%      0.00%
-system.ruby.L2Cache_Controller.IS.Mem_Data         2541      0.00%      0.00%
-system.ruby.L2Cache_Controller.IM.L1_GETS         1307      0.00%      0.00%
-system.ruby.L2Cache_Controller.IM.L1_GETX          792      0.00%      0.00%
-system.ruby.L2Cache_Controller.IM.L1_PUTX_old          303      0.00%      0.00%
-system.ruby.L2Cache_Controller.IM.L2_Replacement_clean      1159948      0.00%      0.00%
-system.ruby.L2Cache_Controller.IM.Mem_Data       211892      0.00%      0.00%
-system.ruby.L2Cache_Controller.SS_MB.L2_Replacement_clean           10      0.00%      0.00%
-system.ruby.L2Cache_Controller.SS_MB.Exclusive_Unblock           11      0.00%      0.00%
+system.ruby.L2Cache_Controller.SS.L2_Replacement         1094      0.00%      0.00%
+system.ruby.L2Cache_Controller.SS.L2_Replacement_clean         2586      0.00%      0.00%
+system.ruby.L2Cache_Controller.M.L1_GETS            9      0.00%      0.00%
+system.ruby.L2Cache_Controller.M.L1_GETX            4      0.00%      0.00%
+system.ruby.L2Cache_Controller.M.L2_Replacement         7542      0.00%      0.00%
+system.ruby.L2Cache_Controller.M.L2_Replacement_clean        12867      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT.L1_GETS         1177      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT.L1_GETX         1709      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT.L1_PUTX        20422      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT.L1_PUTX_old          744      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT.L2_Replacement            9      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT.L2_Replacement_clean       592022      0.00%      0.00%
+system.ruby.L2Cache_Controller.M_I.L1_GETS          235      0.00%      0.00%
+system.ruby.L2Cache_Controller.M_I.L1_GETX          156      0.00%      0.00%
+system.ruby.L2Cache_Controller.M_I.L1_PUTX_old        13986      0.00%      0.00%
+system.ruby.L2Cache_Controller.M_I.Mem_Ack       616114      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT_I.WB_Data            3      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT_I.Ack_all            6      0.00%      0.00%
+system.ruby.L2Cache_Controller.MCT_I.L1_GETS           59      0.00%      0.00%
+system.ruby.L2Cache_Controller.MCT_I.L1_GETX           87      0.00%      0.00%
+system.ruby.L2Cache_Controller.MCT_I.L1_PUTX_old         5561      0.00%      0.00%
+system.ruby.L2Cache_Controller.MCT_I.WB_Data       212344      0.00%      0.00%
+system.ruby.L2Cache_Controller.MCT_I.WB_Data_clean       189361      0.00%      0.00%
+system.ruby.L2Cache_Controller.MCT_I.Ack_all       190317      0.00%      0.00%
+system.ruby.L2Cache_Controller.I_I.Ack           2594      0.00%      0.00%
+system.ruby.L2Cache_Controller.I_I.Ack_all         2586      0.00%      0.00%
+system.ruby.L2Cache_Controller.S_I.Ack           1100      0.00%      0.00%
+system.ruby.L2Cache_Controller.S_I.Ack_all         1094      0.00%      0.00%
+system.ruby.L2Cache_Controller.ISS.L1_GETS         2511      0.00%      0.00%
+system.ruby.L2Cache_Controller.ISS.L1_GETX         1295      0.00%      0.00%
+system.ruby.L2Cache_Controller.ISS.L1_PUTX_old          278      0.00%      0.00%
+system.ruby.L2Cache_Controller.ISS.L2_Replacement_clean      2138971      0.00%      0.00%
+system.ruby.L2Cache_Controller.ISS.Mem_Data       393714      0.00%      0.00%
+system.ruby.L2Cache_Controller.IS.L1_GETS            8      0.00%      0.00%
+system.ruby.L2Cache_Controller.IS.L1_GETX            5      0.00%      0.00%
+system.ruby.L2Cache_Controller.IS.L2_Replacement_clean        13802      0.00%      0.00%
+system.ruby.L2Cache_Controller.IS.Mem_Data         2511      0.00%      0.00%
+system.ruby.L2Cache_Controller.IM.L1_GETS         1354      0.00%      0.00%
+system.ruby.L2Cache_Controller.IM.L1_GETX          755      0.00%      0.00%
+system.ruby.L2Cache_Controller.IM.L1_PUTX_old          265      0.00%      0.00%
+system.ruby.L2Cache_Controller.IM.L2_Replacement_clean      1192970      0.00%      0.00%
+system.ruby.L2Cache_Controller.IM.Mem_Data       219896      0.00%      0.00%
+system.ruby.L2Cache_Controller.SS_MB.L1_PUTX            1      0.00%      0.00%
+system.ruby.L2Cache_Controller.SS_MB.L2_Replacement_clean           11      0.00%      0.00%
+system.ruby.L2Cache_Controller.SS_MB.Exclusive_Unblock            8      0.00%      0.00%
 system.ruby.L2Cache_Controller.MT_MB.L1_GETS          144      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT_MB.L1_GETX           83      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT_MB.L1_PUTX          815      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT_MB.L1_PUTX_old            2      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT_MB.L2_Replacement_clean       657343      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT_MB.Exclusive_Unblock       602353      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT_IIB.L1_GETS            4      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT_IIB.L1_GETX            1      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT_IIB.L1_PUTX          490      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT_MB.L1_GETX           91      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT_MB.L1_PUTX          840      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT_MB.L1_PUTX_old            3      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT_MB.L2_Replacement            6      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT_MB.L2_Replacement_clean       656961      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT_MB.Exclusive_Unblock       615331      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT_IIB.L1_GETS            6      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT_IIB.L1_PUTX          525      0.00%      0.00%
 system.ruby.L2Cache_Controller.MT_IIB.L1_PUTX_old            3      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT_IIB.L2_Replacement_clean         2686      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT_IIB.WB_Data          763      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT_IIB.WB_Data_clean           60      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT_IIB.L2_Replacement_clean         2875      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT_IIB.WB_Data          778      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT_IIB.WB_Data_clean           55      0.00%      0.00%
 system.ruby.L2Cache_Controller.MT_IIB.Unblock          344      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT_IB.L2_Replacement_clean           12      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT_IB.WB_Data          306      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT_IB.WB_Data_clean           38      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT_SB.L2_Replacement          164      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT_SB.Unblock          823      0.00%      0.00%
-system.ruby.Directory_Controller.Fetch         603181      0.00%      0.00%
-system.ruby.Directory_Controller.Data          212951      0.00%      0.00%
-system.ruby.Directory_Controller.Memory_Data       603180      0.00%      0.00%
-system.ruby.Directory_Controller.Memory_Ack       212946      0.00%      0.00%
-system.ruby.Directory_Controller.CleanReplacement       390222      0.00%      0.00%
-system.ruby.Directory_Controller.I.Fetch       603181      0.00%      0.00%
-system.ruby.Directory_Controller.M.Data        212951      0.00%      0.00%
-system.ruby.Directory_Controller.M.CleanReplacement       390222      0.00%      0.00%
-system.ruby.Directory_Controller.IM.Memory_Data       603180      0.00%      0.00%
-system.ruby.Directory_Controller.MI.Memory_Ack       212946      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT_IB.L2_Replacement_clean           26      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT_IB.WB_Data          317      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT_IB.WB_Data_clean           27      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT_SB.L1_PUTX            1      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT_SB.L2_Replacement          210      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT_SB.Unblock          833      0.00%      0.00%
+system.ruby.Directory_Controller.Fetch         616128      0.00%      0.00%
+system.ruby.Directory_Controller.Data          220989      0.00%      0.00%
+system.ruby.Directory_Controller.Memory_Data       616122      0.00%      0.00%
+system.ruby.Directory_Controller.Memory_Ack       220986      0.00%      0.00%
+system.ruby.Directory_Controller.CleanReplacement       395129      0.00%      0.00%
+system.ruby.Directory_Controller.I.Fetch       616128      0.00%      0.00%
+system.ruby.Directory_Controller.M.Data        220989      0.00%      0.00%
+system.ruby.Directory_Controller.M.CleanReplacement       395129      0.00%      0.00%
+system.ruby.Directory_Controller.IM.Memory_Data       616122      0.00%      0.00%
+system.ruby.Directory_Controller.MI.Memory_Ack       220986      0.00%      0.00%
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt
index 9ceb39be3..9c9c7aca3 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt
@@ -1,1171 +1,1155 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.007481                       # Number of seconds simulated
-sim_ticks                                     7481441                       # Number of ticks simulated
-final_tick                                    7481441                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.007646                       # Number of seconds simulated
+sim_ticks                                     7645897                       # Number of ticks simulated
+final_tick                                    7645897                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_tick_rate                                  57492                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 261156                       # Number of bytes of host memory used
-host_seconds                                   130.13                       # Real time elapsed on the host
+host_tick_rate                                  53519                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 294536                       # Number of bytes of host memory used
+host_seconds                                   142.86                       # Real time elapsed on the host
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                             1                       # Clock period in ticks
 system.ruby.clk_domain.clock                        1                       # Clock period in ticks
 system.ruby.outstanding_req_hist::bucket_size            2                      
 system.ruby.outstanding_req_hist::max_bucket           19                      
-system.ruby.outstanding_req_hist::samples       619788                      
-system.ruby.outstanding_req_hist::mean      15.998438                      
-system.ruby.outstanding_req_hist::gmean     15.997160                      
-system.ruby.outstanding_req_hist::stdev      0.126554                      
-system.ruby.outstanding_req_hist         |           8      0.00%      0.00% |          16      0.00%      0.00% |          16      0.00%      0.01% |          16      0.00%      0.01% |          16      0.00%      0.01% |          16      0.00%      0.01% |          16      0.00%      0.02% |          24      0.00%      0.02% |      619660     99.98%    100.00% |           0      0.00%    100.00%
-system.ruby.outstanding_req_hist::total        619788                      
+system.ruby.outstanding_req_hist::samples       632255                      
+system.ruby.outstanding_req_hist::mean      15.998472                      
+system.ruby.outstanding_req_hist::gmean     15.997219                      
+system.ruby.outstanding_req_hist::stdev      0.125288                      
+system.ruby.outstanding_req_hist         |           8      0.00%      0.00% |          16      0.00%      0.00% |          16      0.00%      0.01% |          16      0.00%      0.01% |          16      0.00%      0.01% |          16      0.00%      0.01% |          16      0.00%      0.02% |          22      0.00%      0.02% |      632129     99.98%    100.00% |           0      0.00%    100.00%
+system.ruby.outstanding_req_hist::total        632255                      
 system.ruby.latency_hist::bucket_size            2048                      
 system.ruby.latency_hist::max_bucket            20479                      
-system.ruby.latency_hist::samples              619660                      
-system.ruby.latency_hist::mean            1545.012692                      
-system.ruby.latency_hist::gmean           1029.214657                      
-system.ruby.latency_hist::stdev           1540.360700                      
-system.ruby.latency_hist                 |      466947     75.36%     75.36% |      106679     17.22%     92.57% |       32906      5.31%     97.88% |        9679      1.56%     99.44% |        2729      0.44%     99.88% |         577      0.09%     99.98% |         129      0.02%    100.00% |          11      0.00%    100.00% |           3      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.latency_hist::total                619660                      
+system.ruby.latency_hist::samples              632127                      
+system.ruby.latency_hist::mean            1547.883220                      
+system.ruby.latency_hist::gmean           1029.918853                      
+system.ruby.latency_hist::stdev           1546.131099                      
+system.ruby.latency_hist                 |      476382     75.36%     75.36% |      108333     17.14%     92.50% |       33808      5.35%     97.85% |       10098      1.60%     99.45% |        2721      0.43%     99.88% |         625      0.10%     99.97% |         124      0.02%     99.99% |          33      0.01%    100.00% |           3      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.latency_hist::total                632127                      
 system.ruby.hit_latency_hist::bucket_size            1                      
 system.ruby.hit_latency_hist::max_bucket            9                      
-system.ruby.hit_latency_hist::samples             192                      
+system.ruby.hit_latency_hist::samples             166                      
 system.ruby.hit_latency_hist::mean                  3                      
 system.ruby.hit_latency_hist::gmean          3.000000                      
-system.ruby.hit_latency_hist             |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |         192    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.hit_latency_hist::total               192                      
+system.ruby.hit_latency_hist             |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |         166    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.hit_latency_hist::total               166                      
 system.ruby.miss_latency_hist::bucket_size         2048                      
 system.ruby.miss_latency_hist::max_bucket        20479                      
-system.ruby.miss_latency_hist::samples         619468                      
-system.ruby.miss_latency_hist::mean       1545.490629                      
-system.ruby.miss_latency_hist::gmean      1031.078635                      
-system.ruby.miss_latency_hist::stdev      1540.360114                      
-system.ruby.miss_latency_hist            |      466755     75.35%     75.35% |      106679     17.22%     92.57% |       32906      5.31%     97.88% |        9679      1.56%     99.44% |        2729      0.44%     99.88% |         577      0.09%     99.98% |         129      0.02%    100.00% |          11      0.00%    100.00% |           3      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.miss_latency_hist::total           619468                      
-system.ruby.l1_cntrl4.L1Dcache.demand_hits           21                       # Number of cache demand hits
-system.ruby.l1_cntrl4.L1Dcache.demand_misses        77428                       # Number of cache demand misses
-system.ruby.l1_cntrl4.L1Dcache.demand_accesses        77449                       # Number of cache demand accesses
+system.ruby.miss_latency_hist::samples         631961                      
+system.ruby.miss_latency_hist::mean       1548.289021                      
+system.ruby.miss_latency_hist::gmean      1031.499608                      
+system.ruby.miss_latency_hist::stdev      1546.131374                      
+system.ruby.miss_latency_hist            |      476216     75.36%     75.36% |      108333     17.14%     92.50% |       33808      5.35%     97.85% |       10098      1.60%     99.45% |        2721      0.43%     99.88% |         625      0.10%     99.97% |         124      0.02%     99.99% |          33      0.01%    100.00% |           3      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.miss_latency_hist::total           631961                      
+system.ruby.l1_cntrl4.L1Dcache.demand_hits           27                       # Number of cache demand hits
+system.ruby.l1_cntrl4.L1Dcache.demand_misses        79125                       # Number of cache demand misses
+system.ruby.l1_cntrl4.L1Dcache.demand_accesses        79152                       # Number of cache demand accesses
 system.ruby.l1_cntrl4.L1Icache.demand_hits            0                       # Number of cache demand hits
 system.ruby.l1_cntrl4.L1Icache.demand_misses            0                       # Number of cache demand misses
 system.ruby.l1_cntrl4.L1Icache.demand_accesses            0                       # Number of cache demand accesses
-system.ruby.l1_cntrl5.L1Dcache.demand_hits           25                       # Number of cache demand hits
-system.ruby.l1_cntrl5.L1Dcache.demand_misses        77511                       # Number of cache demand misses
-system.ruby.l1_cntrl5.L1Dcache.demand_accesses        77536                       # Number of cache demand accesses
+system.ruby.l1_cntrl5.L1Dcache.demand_hits           27                       # Number of cache demand hits
+system.ruby.l1_cntrl5.L1Dcache.demand_misses        78996                       # Number of cache demand misses
+system.ruby.l1_cntrl5.L1Dcache.demand_accesses        79023                       # Number of cache demand accesses
 system.ruby.l1_cntrl5.L1Icache.demand_hits            0                       # Number of cache demand hits
 system.ruby.l1_cntrl5.L1Icache.demand_misses            0                       # Number of cache demand misses
 system.ruby.l1_cntrl5.L1Icache.demand_accesses            0                       # Number of cache demand accesses
-system.ruby.l1_cntrl6.L1Dcache.demand_hits           21                       # Number of cache demand hits
-system.ruby.l1_cntrl6.L1Dcache.demand_misses        77666                       # Number of cache demand misses
-system.ruby.l1_cntrl6.L1Dcache.demand_accesses        77687                       # Number of cache demand accesses
+system.ruby.l1_cntrl6.L1Dcache.demand_hits           14                       # Number of cache demand hits
+system.ruby.l1_cntrl6.L1Dcache.demand_misses        79210                       # Number of cache demand misses
+system.ruby.l1_cntrl6.L1Dcache.demand_accesses        79224                       # Number of cache demand accesses
 system.ruby.l1_cntrl6.L1Icache.demand_hits            0                       # Number of cache demand hits
 system.ruby.l1_cntrl6.L1Icache.demand_misses            0                       # Number of cache demand misses
 system.ruby.l1_cntrl6.L1Icache.demand_accesses            0                       # Number of cache demand accesses
-system.ruby.l1_cntrl7.L1Dcache.demand_hits           23                       # Number of cache demand hits
-system.ruby.l1_cntrl7.L1Dcache.demand_misses        77528                       # Number of cache demand misses
-system.ruby.l1_cntrl7.L1Dcache.demand_accesses        77551                       # Number of cache demand accesses
+system.ruby.l1_cntrl7.L1Dcache.demand_hits           17                       # Number of cache demand hits
+system.ruby.l1_cntrl7.L1Dcache.demand_misses        78757                       # Number of cache demand misses
+system.ruby.l1_cntrl7.L1Dcache.demand_accesses        78774                       # Number of cache demand accesses
 system.ruby.l1_cntrl7.L1Icache.demand_hits            0                       # Number of cache demand hits
 system.ruby.l1_cntrl7.L1Icache.demand_misses            0                       # Number of cache demand misses
 system.ruby.l1_cntrl7.L1Icache.demand_accesses            0                       # Number of cache demand accesses
-system.ruby.l1_cntrl0.L1Dcache.demand_hits           27                       # Number of cache demand hits
-system.ruby.l1_cntrl0.L1Dcache.demand_misses        77272                       # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Dcache.demand_accesses        77299                       # Number of cache demand accesses
+system.ruby.l1_cntrl0.L1Dcache.demand_hits           22                       # Number of cache demand hits
+system.ruby.l1_cntrl0.L1Dcache.demand_misses        79077                       # Number of cache demand misses
+system.ruby.l1_cntrl0.L1Dcache.demand_accesses        79099                       # Number of cache demand accesses
 system.ruby.l1_cntrl0.L1Icache.demand_hits            0                       # Number of cache demand hits
 system.ruby.l1_cntrl0.L1Icache.demand_misses            0                       # Number of cache demand misses
 system.ruby.l1_cntrl0.L1Icache.demand_accesses            0                       # Number of cache demand accesses
-system.ruby.l1_cntrl1.L1Dcache.demand_hits           30                       # Number of cache demand hits
-system.ruby.l1_cntrl1.L1Dcache.demand_misses        77679                       # Number of cache demand misses
-system.ruby.l1_cntrl1.L1Dcache.demand_accesses        77709                       # Number of cache demand accesses
+system.ruby.l1_cntrl1.L1Dcache.demand_hits            9                       # Number of cache demand hits
+system.ruby.l1_cntrl1.L1Dcache.demand_misses        78940                       # Number of cache demand misses
+system.ruby.l1_cntrl1.L1Dcache.demand_accesses        78949                       # Number of cache demand accesses
 system.ruby.l1_cntrl1.L1Icache.demand_hits            0                       # Number of cache demand hits
 system.ruby.l1_cntrl1.L1Icache.demand_misses            0                       # Number of cache demand misses
 system.ruby.l1_cntrl1.L1Icache.demand_accesses            0                       # Number of cache demand accesses
-system.ruby.l1_cntrl2.L1Dcache.demand_hits           14                       # Number of cache demand hits
-system.ruby.l1_cntrl2.L1Dcache.demand_misses        77082                       # Number of cache demand misses
-system.ruby.l1_cntrl2.L1Dcache.demand_accesses        77096                       # Number of cache demand accesses
+system.ruby.l1_cntrl2.L1Dcache.demand_hits           26                       # Number of cache demand hits
+system.ruby.l1_cntrl2.L1Dcache.demand_misses        79113                       # Number of cache demand misses
+system.ruby.l1_cntrl2.L1Dcache.demand_accesses        79139                       # Number of cache demand accesses
 system.ruby.l1_cntrl2.L1Icache.demand_hits            0                       # Number of cache demand hits
 system.ruby.l1_cntrl2.L1Icache.demand_misses            0                       # Number of cache demand misses
 system.ruby.l1_cntrl2.L1Icache.demand_accesses            0                       # Number of cache demand accesses
-system.ruby.l1_cntrl3.L1Dcache.demand_hits           31                       # Number of cache demand hits
-system.ruby.l1_cntrl3.L1Dcache.demand_misses        77329                       # Number of cache demand misses
-system.ruby.l1_cntrl3.L1Dcache.demand_accesses        77360                       # Number of cache demand accesses
+system.ruby.l1_cntrl3.L1Dcache.demand_hits           24                       # Number of cache demand hits
+system.ruby.l1_cntrl3.L1Dcache.demand_misses        78765                       # Number of cache demand misses
+system.ruby.l1_cntrl3.L1Dcache.demand_accesses        78789                       # Number of cache demand accesses
 system.ruby.l1_cntrl3.L1Icache.demand_hits            0                       # Number of cache demand hits
 system.ruby.l1_cntrl3.L1Icache.demand_misses            0                       # Number of cache demand misses
 system.ruby.l1_cntrl3.L1Icache.demand_accesses            0                       # Number of cache demand accesses
-system.ruby.l2_cntrl0.L2cache.demand_hits         5922                       # Number of cache demand hits
-system.ruby.l2_cntrl0.L2cache.demand_misses       613572                       # Number of cache demand misses
-system.ruby.l2_cntrl0.L2cache.demand_accesses       619494                       # Number of cache demand accesses
-system.ruby.network.routers00.percent_links_utilized     5.689262                      
-system.ruby.network.routers00.msg_count.Request_Control::0        77272                      
-system.ruby.network.routers00.msg_count.Response_Data::2        75499                      
-system.ruby.network.routers00.msg_count.ResponseL2hit_Data::2          705                      
-system.ruby.network.routers00.msg_count.ResponseLocal_Data::2         2146                      
-system.ruby.network.routers00.msg_count.Response_Control::2          382                      
-system.ruby.network.routers00.msg_count.Writeback_Data::2        76215                      
-system.ruby.network.routers00.msg_count.Writeback_Control::0       154485                      
-system.ruby.network.routers00.msg_count.Forwarded_Control::0         1082                      
-system.ruby.network.routers00.msg_count.Invalidate_Control::0            6                      
-system.ruby.network.routers00.msg_count.Unblock_Control::2        78243                      
-system.ruby.network.routers00.msg_bytes.Request_Control::0       618176                      
-system.ruby.network.routers00.msg_bytes.Response_Data::2      5435928                      
-system.ruby.network.routers00.msg_bytes.ResponseL2hit_Data::2        50760                      
-system.ruby.network.routers00.msg_bytes.ResponseLocal_Data::2       154512                      
-system.ruby.network.routers00.msg_bytes.Response_Control::2         3056                      
-system.ruby.network.routers00.msg_bytes.Writeback_Data::2      5487480                      
-system.ruby.network.routers00.msg_bytes.Writeback_Control::0      1235880                      
-system.ruby.network.routers00.msg_bytes.Forwarded_Control::0         8656                      
-system.ruby.network.routers00.msg_bytes.Invalidate_Control::0           48                      
-system.ruby.network.routers00.msg_bytes.Unblock_Control::2       625944                      
-system.ruby.network.routers01.percent_links_utilized     5.720198                      
-system.ruby.network.routers01.msg_count.Request_Control::0        77679                      
-system.ruby.network.routers01.msg_count.Response_Data::2        75857                      
-system.ruby.network.routers01.msg_count.ResponseL2hit_Data::2          752                      
-system.ruby.network.routers01.msg_count.ResponseLocal_Data::2         2136                      
-system.ruby.network.routers01.msg_count.Response_Control::2          379                      
-system.ruby.network.routers01.msg_count.Writeback_Data::2        76673                      
-system.ruby.network.routers01.msg_count.Writeback_Control::0       155314                      
-system.ruby.network.routers01.msg_count.Forwarded_Control::0         1069                      
-system.ruby.network.routers01.msg_count.Invalidate_Control::0            3                      
-system.ruby.network.routers01.msg_count.Unblock_Control::2        78607                      
-system.ruby.network.routers01.msg_bytes.Request_Control::0       621432                      
-system.ruby.network.routers01.msg_bytes.Response_Data::2      5461704                      
-system.ruby.network.routers01.msg_bytes.ResponseL2hit_Data::2        54144                      
-system.ruby.network.routers01.msg_bytes.ResponseLocal_Data::2       153792                      
-system.ruby.network.routers01.msg_bytes.Response_Control::2         3032                      
-system.ruby.network.routers01.msg_bytes.Writeback_Data::2      5520456                      
-system.ruby.network.routers01.msg_bytes.Writeback_Control::0      1242512                      
-system.ruby.network.routers01.msg_bytes.Forwarded_Control::0         8552                      
-system.ruby.network.routers01.msg_bytes.Invalidate_Control::0           24                      
-system.ruby.network.routers01.msg_bytes.Unblock_Control::2       628856                      
-system.ruby.network.routers02.percent_links_utilized     5.676229                      
-system.ruby.network.routers02.msg_count.Request_Control::0        77082                      
-system.ruby.network.routers02.msg_count.Response_Data::2        75271                      
-system.ruby.network.routers02.msg_count.ResponseL2hit_Data::2          752                      
-system.ruby.network.routers02.msg_count.ResponseLocal_Data::2         2100                      
-system.ruby.network.routers02.msg_count.Response_Control::2          382                      
-system.ruby.network.routers02.msg_count.Writeback_Data::2        76103                      
-system.ruby.network.routers02.msg_count.Writeback_Control::0       154124                      
-system.ruby.network.routers02.msg_count.Forwarded_Control::0         1045                      
-system.ruby.network.routers02.msg_count.Unblock_Control::2        77988                      
-system.ruby.network.routers02.msg_bytes.Request_Control::0       616656                      
-system.ruby.network.routers02.msg_bytes.Response_Data::2      5419512                      
-system.ruby.network.routers02.msg_bytes.ResponseL2hit_Data::2        54144                      
-system.ruby.network.routers02.msg_bytes.ResponseLocal_Data::2       151200                      
-system.ruby.network.routers02.msg_bytes.Response_Control::2         3056                      
-system.ruby.network.routers02.msg_bytes.Writeback_Data::2      5479416                      
-system.ruby.network.routers02.msg_bytes.Writeback_Control::0      1232992                      
-system.ruby.network.routers02.msg_bytes.Forwarded_Control::0         8360                      
-system.ruby.network.routers02.msg_bytes.Unblock_Control::2       623904                      
-system.ruby.network.routers03.percent_links_utilized     5.695076                      
-system.ruby.network.routers03.msg_count.Request_Control::0        77329                      
-system.ruby.network.routers03.msg_count.Response_Data::2        75554                      
-system.ruby.network.routers03.msg_count.ResponseL2hit_Data::2          792                      
-system.ruby.network.routers03.msg_count.ResponseLocal_Data::2         2076                      
-system.ruby.network.routers03.msg_count.Response_Control::2          354                      
-system.ruby.network.routers03.msg_count.Writeback_Data::2        76314                      
-system.ruby.network.routers03.msg_count.Writeback_Control::0       154618                      
-system.ruby.network.routers03.msg_count.Forwarded_Control::0         1099                      
-system.ruby.network.routers03.msg_count.Invalidate_Control::0            3                      
-system.ruby.network.routers03.msg_count.Unblock_Control::2        78268                      
-system.ruby.network.routers03.msg_bytes.Request_Control::0       618632                      
-system.ruby.network.routers03.msg_bytes.Response_Data::2      5439888                      
-system.ruby.network.routers03.msg_bytes.ResponseL2hit_Data::2        57024                      
-system.ruby.network.routers03.msg_bytes.ResponseLocal_Data::2       149472                      
-system.ruby.network.routers03.msg_bytes.Response_Control::2         2832                      
-system.ruby.network.routers03.msg_bytes.Writeback_Data::2      5494608                      
-system.ruby.network.routers03.msg_bytes.Writeback_Control::0      1236944                      
-system.ruby.network.routers03.msg_bytes.Forwarded_Control::0         8792                      
-system.ruby.network.routers03.msg_bytes.Invalidate_Control::0           24                      
-system.ruby.network.routers03.msg_bytes.Unblock_Control::2       626144                      
-system.ruby.network.routers04.percent_links_utilized     5.699310                      
-system.ruby.network.routers04.msg_count.Request_Control::0        77428                      
-system.ruby.network.routers04.msg_count.Response_Data::2        75631                      
-system.ruby.network.routers04.msg_count.ResponseL2hit_Data::2          720                      
-system.ruby.network.routers04.msg_count.ResponseLocal_Data::2         2101                      
-system.ruby.network.routers04.msg_count.Response_Control::2          374                      
-system.ruby.network.routers04.msg_count.Writeback_Data::2        76387                      
-system.ruby.network.routers04.msg_count.Writeback_Control::0       154786                      
-system.ruby.network.routers04.msg_count.Forwarded_Control::0         1028                      
-system.ruby.network.routers04.msg_count.Invalidate_Control::0            2                      
-system.ruby.network.routers04.msg_count.Unblock_Control::2        78393                      
-system.ruby.network.routers04.msg_bytes.Request_Control::0       619424                      
-system.ruby.network.routers04.msg_bytes.Response_Data::2      5445432                      
-system.ruby.network.routers04.msg_bytes.ResponseL2hit_Data::2        51840                      
-system.ruby.network.routers04.msg_bytes.ResponseLocal_Data::2       151272                      
-system.ruby.network.routers04.msg_bytes.Response_Control::2         2992                      
-system.ruby.network.routers04.msg_bytes.Writeback_Data::2      5499864                      
-system.ruby.network.routers04.msg_bytes.Writeback_Control::0      1238288                      
-system.ruby.network.routers04.msg_bytes.Forwarded_Control::0         8224                      
-system.ruby.network.routers04.msg_bytes.Invalidate_Control::0           16                      
-system.ruby.network.routers04.msg_bytes.Unblock_Control::2       627144                      
-system.ruby.network.routers05.percent_links_utilized     5.706217                      
-system.ruby.network.routers05.msg_count.Request_Control::0        77511                      
-system.ruby.network.routers05.msg_count.Response_Data::2        75743                      
-system.ruby.network.routers05.msg_count.ResponseL2hit_Data::2          737                      
-system.ruby.network.routers05.msg_count.ResponseLocal_Data::2         2056                      
-system.ruby.network.routers05.msg_count.Response_Control::2          351                      
-system.ruby.network.routers05.msg_count.Writeback_Data::2        76496                      
-system.ruby.network.routers05.msg_count.Writeback_Control::0       154988                      
-system.ruby.network.routers05.msg_count.Forwarded_Control::0         1028                      
+system.ruby.l2_cntrl0.L2cache.demand_hits         6149                       # Number of cache demand hits
+system.ruby.l2_cntrl0.L2cache.demand_misses       625832                       # Number of cache demand misses
+system.ruby.l2_cntrl0.L2cache.demand_accesses       631981                       # Number of cache demand accesses
+system.ruby.network.routers00.percent_links_utilized     5.698442                      
+system.ruby.network.routers00.msg_count.Request_Control::0        79077                      
+system.ruby.network.routers00.msg_count.Response_Data::2        77245                      
+system.ruby.network.routers00.msg_count.ResponseL2hit_Data::2          780                      
+system.ruby.network.routers00.msg_count.ResponseLocal_Data::2         2140                      
+system.ruby.network.routers00.msg_count.Response_Control::2          385                      
+system.ruby.network.routers00.msg_count.Writeback_Data::2        78067                      
+system.ruby.network.routers00.msg_count.Writeback_Control::0       158122                      
+system.ruby.network.routers00.msg_count.Forwarded_Control::0         1092                      
+system.ruby.network.routers00.msg_count.Invalidate_Control::0            3                      
+system.ruby.network.routers00.msg_count.Unblock_Control::2        80021                      
+system.ruby.network.routers00.msg_bytes.Request_Control::0       632616                      
+system.ruby.network.routers00.msg_bytes.Response_Data::2      5561640                      
+system.ruby.network.routers00.msg_bytes.ResponseL2hit_Data::2        56160                      
+system.ruby.network.routers00.msg_bytes.ResponseLocal_Data::2       154080                      
+system.ruby.network.routers00.msg_bytes.Response_Control::2         3080                      
+system.ruby.network.routers00.msg_bytes.Writeback_Data::2      5620824                      
+system.ruby.network.routers00.msg_bytes.Writeback_Control::0      1264976                      
+system.ruby.network.routers00.msg_bytes.Forwarded_Control::0         8736                      
+system.ruby.network.routers00.msg_bytes.Invalidate_Control::0           24                      
+system.ruby.network.routers00.msg_bytes.Unblock_Control::2       640168                      
+system.ruby.network.routers01.percent_links_utilized     5.685628                      
+system.ruby.network.routers01.msg_count.Request_Control::0        78939                      
+system.ruby.network.routers01.msg_count.Response_Data::2        77083                      
+system.ruby.network.routers01.msg_count.ResponseL2hit_Data::2          799                      
+system.ruby.network.routers01.msg_count.ResponseLocal_Data::2         2117                      
+system.ruby.network.routers01.msg_count.Response_Control::2          369                      
+system.ruby.network.routers01.msg_count.Writeback_Data::2        77862                      
+system.ruby.network.routers01.msg_count.Writeback_Control::0       157816                      
+system.ruby.network.routers01.msg_count.Forwarded_Control::0         1062                      
+system.ruby.network.routers01.msg_count.Invalidate_Control::0            1                      
+system.ruby.network.routers01.msg_count.Unblock_Control::2        79933                      
+system.ruby.network.routers01.msg_bytes.Request_Control::0       631512                      
+system.ruby.network.routers01.msg_bytes.Response_Data::2      5549976                      
+system.ruby.network.routers01.msg_bytes.ResponseL2hit_Data::2        57528                      
+system.ruby.network.routers01.msg_bytes.ResponseLocal_Data::2       152424                      
+system.ruby.network.routers01.msg_bytes.Response_Control::2         2952                      
+system.ruby.network.routers01.msg_bytes.Writeback_Data::2      5606064                      
+system.ruby.network.routers01.msg_bytes.Writeback_Control::0      1262528                      
+system.ruby.network.routers01.msg_bytes.Forwarded_Control::0         8496                      
+system.ruby.network.routers01.msg_bytes.Invalidate_Control::0            8                      
+system.ruby.network.routers01.msg_bytes.Unblock_Control::2       639464                      
+system.ruby.network.routers02.percent_links_utilized     5.700427                      
+system.ruby.network.routers02.msg_count.Request_Control::0        79113                      
+system.ruby.network.routers02.msg_count.Response_Data::2        77289                      
+system.ruby.network.routers02.msg_count.ResponseL2hit_Data::2          789                      
+system.ruby.network.routers02.msg_count.ResponseLocal_Data::2         2124                      
+system.ruby.network.routers02.msg_count.Response_Control::2          368                      
+system.ruby.network.routers02.msg_count.Writeback_Data::2        78085                      
+system.ruby.network.routers02.msg_count.Writeback_Control::0       158176                      
+system.ruby.network.routers02.msg_count.Forwarded_Control::0         1090                      
+system.ruby.network.routers02.msg_count.Invalidate_Control::0            1                      
+system.ruby.network.routers02.msg_count.Unblock_Control::2        80064                      
+system.ruby.network.routers02.msg_bytes.Request_Control::0       632904                      
+system.ruby.network.routers02.msg_bytes.Response_Data::2      5564808                      
+system.ruby.network.routers02.msg_bytes.ResponseL2hit_Data::2        56808                      
+system.ruby.network.routers02.msg_bytes.ResponseLocal_Data::2       152928                      
+system.ruby.network.routers02.msg_bytes.Response_Control::2         2944                      
+system.ruby.network.routers02.msg_bytes.Writeback_Data::2      5622120                      
+system.ruby.network.routers02.msg_bytes.Writeback_Control::0      1265408                      
+system.ruby.network.routers02.msg_bytes.Forwarded_Control::0         8720                      
+system.ruby.network.routers02.msg_bytes.Invalidate_Control::0            8                      
+system.ruby.network.routers02.msg_bytes.Unblock_Control::2       640512                      
+system.ruby.network.routers03.percent_links_utilized     5.674514                      
+system.ruby.network.routers03.msg_count.Request_Control::0        78765                      
+system.ruby.network.routers03.msg_count.Response_Data::2        76945                      
+system.ruby.network.routers03.msg_count.ResponseL2hit_Data::2          741                      
+system.ruby.network.routers03.msg_count.ResponseLocal_Data::2         2155                      
+system.ruby.network.routers03.msg_count.Response_Control::2          398                      
+system.ruby.network.routers03.msg_count.Writeback_Data::2        77719                      
+system.ruby.network.routers03.msg_count.Writeback_Control::0       157450                      
+system.ruby.network.routers03.msg_count.Forwarded_Control::0         1079                      
+system.ruby.network.routers03.msg_count.Invalidate_Control::0            2                      
+system.ruby.network.routers03.msg_count.Unblock_Control::2        79736                      
+system.ruby.network.routers03.msg_bytes.Request_Control::0       630120                      
+system.ruby.network.routers03.msg_bytes.Response_Data::2      5540040                      
+system.ruby.network.routers03.msg_bytes.ResponseL2hit_Data::2        53352                      
+system.ruby.network.routers03.msg_bytes.ResponseLocal_Data::2       155160                      
+system.ruby.network.routers03.msg_bytes.Response_Control::2         3184                      
+system.ruby.network.routers03.msg_bytes.Writeback_Data::2      5595768                      
+system.ruby.network.routers03.msg_bytes.Writeback_Control::0      1259600                      
+system.ruby.network.routers03.msg_bytes.Forwarded_Control::0         8632                      
+system.ruby.network.routers03.msg_bytes.Invalidate_Control::0           16                      
+system.ruby.network.routers03.msg_bytes.Unblock_Control::2       637888                      
+system.ruby.network.routers04.percent_links_utilized     5.699724                      
+system.ruby.network.routers04.msg_count.Request_Control::0        79125                      
+system.ruby.network.routers04.msg_count.Response_Data::2        77230                      
+system.ruby.network.routers04.msg_count.ResponseL2hit_Data::2          793                      
+system.ruby.network.routers04.msg_count.ResponseLocal_Data::2         2159                      
+system.ruby.network.routers04.msg_count.Response_Control::2          414                      
+system.ruby.network.routers04.msg_count.Writeback_Data::2        78072                      
+system.ruby.network.routers04.msg_count.Writeback_Control::0       158198                      
+system.ruby.network.routers04.msg_count.Forwarded_Control::0         1060                      
+system.ruby.network.routers04.msg_count.Invalidate_Control::0            1                      
+system.ruby.network.routers04.msg_count.Unblock_Control::2        80096                      
+system.ruby.network.routers04.msg_bytes.Request_Control::0       633000                      
+system.ruby.network.routers04.msg_bytes.Response_Data::2      5560560                      
+system.ruby.network.routers04.msg_bytes.ResponseL2hit_Data::2        57096                      
+system.ruby.network.routers04.msg_bytes.ResponseLocal_Data::2       155448                      
+system.ruby.network.routers04.msg_bytes.Response_Control::2         3312                      
+system.ruby.network.routers04.msg_bytes.Writeback_Data::2      5621184                      
+system.ruby.network.routers04.msg_bytes.Writeback_Control::0      1265584                      
+system.ruby.network.routers04.msg_bytes.Forwarded_Control::0         8480                      
+system.ruby.network.routers04.msg_bytes.Invalidate_Control::0            8                      
+system.ruby.network.routers04.msg_bytes.Unblock_Control::2       640768                      
+system.ruby.network.routers05.percent_links_utilized     5.689251                      
+system.ruby.network.routers05.msg_count.Request_Control::0        78996                      
+system.ruby.network.routers05.msg_count.Response_Data::2        77132                      
+system.ruby.network.routers05.msg_count.ResponseL2hit_Data::2          770                      
+system.ruby.network.routers05.msg_count.ResponseLocal_Data::2         2086                      
+system.ruby.network.routers05.msg_count.Response_Control::2          391                      
+system.ruby.network.routers05.msg_count.Writeback_Data::2        77981                      
+system.ruby.network.routers05.msg_count.Writeback_Control::0       157934                      
+system.ruby.network.routers05.msg_count.Forwarded_Control::0          994                      
 system.ruby.network.routers05.msg_count.Invalidate_Control::0            1                      
-system.ruby.network.routers05.msg_count.Unblock_Control::2        78462                      
-system.ruby.network.routers05.msg_bytes.Request_Control::0       620088                      
-system.ruby.network.routers05.msg_bytes.Response_Data::2      5453496                      
-system.ruby.network.routers05.msg_bytes.ResponseL2hit_Data::2        53064                      
-system.ruby.network.routers05.msg_bytes.ResponseLocal_Data::2       148032                      
-system.ruby.network.routers05.msg_bytes.Response_Control::2         2808                      
-system.ruby.network.routers05.msg_bytes.Writeback_Data::2      5507712                      
-system.ruby.network.routers05.msg_bytes.Writeback_Control::0      1239904                      
-system.ruby.network.routers05.msg_bytes.Forwarded_Control::0         8224                      
+system.ruby.network.routers05.msg_count.Unblock_Control::2        79943                      
+system.ruby.network.routers05.msg_bytes.Request_Control::0       631968                      
+system.ruby.network.routers05.msg_bytes.Response_Data::2      5553504                      
+system.ruby.network.routers05.msg_bytes.ResponseL2hit_Data::2        55440                      
+system.ruby.network.routers05.msg_bytes.ResponseLocal_Data::2       150192                      
+system.ruby.network.routers05.msg_bytes.Response_Control::2         3128                      
+system.ruby.network.routers05.msg_bytes.Writeback_Data::2      5614632                      
+system.ruby.network.routers05.msg_bytes.Writeback_Control::0      1263472                      
+system.ruby.network.routers05.msg_bytes.Forwarded_Control::0         7952                      
 system.ruby.network.routers05.msg_bytes.Invalidate_Control::0            8                      
-system.ruby.network.routers05.msg_bytes.Unblock_Control::2       627696                      
-system.ruby.network.routers06.percent_links_utilized     5.716967                      
-system.ruby.network.routers06.msg_count.Request_Control::0        77666                      
-system.ruby.network.routers06.msg_count.Response_Data::2        75840                      
-system.ruby.network.routers06.msg_count.ResponseL2hit_Data::2          736                      
-system.ruby.network.routers06.msg_count.ResponseLocal_Data::2         2109                      
-system.ruby.network.routers06.msg_count.Response_Control::2          420                      
-system.ruby.network.routers06.msg_count.Writeback_Data::2        76630                      
-system.ruby.network.routers06.msg_count.Writeback_Control::0       155272                      
-system.ruby.network.routers06.msg_count.Forwarded_Control::0         1022                      
-system.ruby.network.routers06.msg_count.Invalidate_Control::0            3                      
-system.ruby.network.routers06.msg_count.Unblock_Control::2        78631                      
-system.ruby.network.routers06.msg_bytes.Request_Control::0       621328                      
-system.ruby.network.routers06.msg_bytes.Response_Data::2      5460480                      
-system.ruby.network.routers06.msg_bytes.ResponseL2hit_Data::2        52992                      
-system.ruby.network.routers06.msg_bytes.ResponseLocal_Data::2       151848                      
-system.ruby.network.routers06.msg_bytes.Response_Control::2         3360                      
-system.ruby.network.routers06.msg_bytes.Writeback_Data::2      5517360                      
-system.ruby.network.routers06.msg_bytes.Writeback_Control::0      1242176                      
-system.ruby.network.routers06.msg_bytes.Forwarded_Control::0         8176                      
-system.ruby.network.routers06.msg_bytes.Invalidate_Control::0           24                      
-system.ruby.network.routers06.msg_bytes.Unblock_Control::2       629048                      
-system.ruby.network.routers07.percent_links_utilized     5.706304                      
-system.ruby.network.routers07.msg_count.Request_Control::0        77528                      
-system.ruby.network.routers07.msg_count.Response_Data::2        75730                      
-system.ruby.network.routers07.msg_count.ResponseL2hit_Data::2          728                      
-system.ruby.network.routers07.msg_count.ResponseLocal_Data::2         2116                      
-system.ruby.network.routers07.msg_count.Response_Control::2          381                      
-system.ruby.network.routers07.msg_count.Writeback_Data::2        76441                      
-system.ruby.network.routers07.msg_count.Writeback_Control::0       155010                      
-system.ruby.network.routers07.msg_count.Forwarded_Control::0         1048                      
-system.ruby.network.routers07.msg_count.Invalidate_Control::0            1                      
-system.ruby.network.routers07.msg_count.Unblock_Control::2        78552                      
-system.ruby.network.routers07.msg_bytes.Request_Control::0       620224                      
-system.ruby.network.routers07.msg_bytes.Response_Data::2      5452560                      
-system.ruby.network.routers07.msg_bytes.ResponseL2hit_Data::2        52416                      
-system.ruby.network.routers07.msg_bytes.ResponseLocal_Data::2       152352                      
-system.ruby.network.routers07.msg_bytes.Response_Control::2         3048                      
-system.ruby.network.routers07.msg_bytes.Writeback_Data::2      5503752                      
-system.ruby.network.routers07.msg_bytes.Writeback_Control::0      1240080                      
-system.ruby.network.routers07.msg_bytes.Forwarded_Control::0         8384                      
-system.ruby.network.routers07.msg_bytes.Invalidate_Control::0            8                      
-system.ruby.network.routers07.msg_bytes.Unblock_Control::2       628416                      
-system.ruby.network.routers08.percent_links_utilized    79.161635                      
-system.ruby.network.routers08.msg_count.Request_Control::0       619494                      
-system.ruby.network.routers08.msg_count.Request_Control::1       605151                      
-system.ruby.network.routers08.msg_count.Response_Data::2      1210253                      
-system.ruby.network.routers08.msg_count.ResponseL2hit_Data::2         5922                      
-system.ruby.network.routers08.msg_count.Response_Control::2         2985                      
-system.ruby.network.routers08.msg_count.Writeback_Data::2       826501                      
-system.ruby.network.routers08.msg_count.Writeback_Control::0      1238596                      
-system.ruby.network.routers08.msg_count.Writeback_Control::1      1209317                      
-system.ruby.network.routers08.msg_count.Writeback_Control::2       389402                      
-system.ruby.network.routers08.msg_count.Forwarded_Control::0         8421                      
-system.ruby.network.routers08.msg_count.Invalidate_Control::0           19                      
-system.ruby.network.routers08.msg_count.Unblock_Control::2      1232268                      
-system.ruby.network.routers08.msg_bytes.Request_Control::0      4955952                      
-system.ruby.network.routers08.msg_bytes.Request_Control::1      4841208                      
-system.ruby.network.routers08.msg_bytes.Response_Data::2     87138216                      
-system.ruby.network.routers08.msg_bytes.ResponseL2hit_Data::2       426384                      
-system.ruby.network.routers08.msg_bytes.Response_Control::2        23880                      
-system.ruby.network.routers08.msg_bytes.Writeback_Data::2     59508072                      
-system.ruby.network.routers08.msg_bytes.Writeback_Control::0      9908768                      
-system.ruby.network.routers08.msg_bytes.Writeback_Control::1      9674536                      
-system.ruby.network.routers08.msg_bytes.Writeback_Control::2      3115216                      
-system.ruby.network.routers08.msg_bytes.Forwarded_Control::0        67368                      
-system.ruby.network.routers08.msg_bytes.Invalidate_Control::0          152                      
-system.ruby.network.routers08.msg_bytes.Unblock_Control::2      9858144                      
+system.ruby.network.routers05.msg_bytes.Unblock_Control::2       639544                      
+system.ruby.network.routers06.percent_links_utilized     5.706584                      
+system.ruby.network.routers06.msg_count.Request_Control::0        79210                      
+system.ruby.network.routers06.msg_count.Response_Data::2        77396                      
+system.ruby.network.routers06.msg_count.ResponseL2hit_Data::2          741                      
+system.ruby.network.routers06.msg_count.ResponseLocal_Data::2         2181                      
+system.ruby.network.routers06.msg_count.Response_Control::2          373                      
+system.ruby.network.routers06.msg_count.Writeback_Data::2        78123                      
+system.ruby.network.routers06.msg_count.Writeback_Control::0       158387                      
+system.ruby.network.routers06.msg_count.Forwarded_Control::0         1111                      
+system.ruby.network.routers06.msg_count.Invalidate_Control::0            2                      
+system.ruby.network.routers06.msg_count.Unblock_Control::2        80226                      
+system.ruby.network.routers06.msg_bytes.Request_Control::0       633680                      
+system.ruby.network.routers06.msg_bytes.Response_Data::2      5572512                      
+system.ruby.network.routers06.msg_bytes.ResponseL2hit_Data::2        53352                      
+system.ruby.network.routers06.msg_bytes.ResponseLocal_Data::2       157032                      
+system.ruby.network.routers06.msg_bytes.Response_Control::2         2984                      
+system.ruby.network.routers06.msg_bytes.Writeback_Data::2      5624856                      
+system.ruby.network.routers06.msg_bytes.Writeback_Control::0      1267096                      
+system.ruby.network.routers06.msg_bytes.Forwarded_Control::0         8888                      
+system.ruby.network.routers06.msg_bytes.Invalidate_Control::0           16                      
+system.ruby.network.routers06.msg_bytes.Unblock_Control::2       641808                      
+system.ruby.network.routers07.percent_links_utilized     5.672683                      
+system.ruby.network.routers07.msg_count.Request_Control::0        78757                      
+system.ruby.network.routers07.msg_count.Response_Data::2        76940                      
+system.ruby.network.routers07.msg_count.ResponseL2hit_Data::2          736                      
+system.ruby.network.routers07.msg_count.ResponseLocal_Data::2         2142                      
+system.ruby.network.routers07.msg_count.Response_Control::2          362                      
+system.ruby.network.routers07.msg_count.Writeback_Data::2        77687                      
+system.ruby.network.routers07.msg_count.Writeback_Control::0       157436                      
+system.ruby.network.routers07.msg_count.Forwarded_Control::0         1064                      
+system.ruby.network.routers07.msg_count.Unblock_Control::2        79746                      
+system.ruby.network.routers07.msg_bytes.Request_Control::0       630056                      
+system.ruby.network.routers07.msg_bytes.Response_Data::2      5539680                      
+system.ruby.network.routers07.msg_bytes.ResponseL2hit_Data::2        52992                      
+system.ruby.network.routers07.msg_bytes.ResponseLocal_Data::2       154224                      
+system.ruby.network.routers07.msg_bytes.Response_Control::2         2896                      
+system.ruby.network.routers07.msg_bytes.Writeback_Data::2      5593464                      
+system.ruby.network.routers07.msg_bytes.Writeback_Control::0      1259488                      
+system.ruby.network.routers07.msg_bytes.Forwarded_Control::0         8512                      
+system.ruby.network.routers07.msg_bytes.Unblock_Control::2       637968                      
+system.ruby.network.routers08.percent_links_utilized    79.115289                      
+system.ruby.network.routers08.msg_count.Request_Control::0       631981                      
+system.ruby.network.routers08.msg_count.Request_Control::1       617280                      
+system.ruby.network.routers08.msg_count.Response_Data::2      1234524                      
+system.ruby.network.routers08.msg_count.ResponseL2hit_Data::2         6149                      
+system.ruby.network.routers08.msg_count.Response_Control::2         3038                      
+system.ruby.network.routers08.msg_count.Writeback_Data::2       846848                      
+system.ruby.network.routers08.msg_count.Writeback_Control::0      1263518                      
+system.ruby.network.routers08.msg_count.Writeback_Control::1      1233658                      
+system.ruby.network.routers08.msg_count.Writeback_Control::2       393565                      
+system.ruby.network.routers08.msg_count.Forwarded_Control::0         8552                      
+system.ruby.network.routers08.msg_count.Invalidate_Control::0           11                      
+system.ruby.network.routers08.msg_count.Unblock_Control::2      1257012                      
+system.ruby.network.routers08.msg_bytes.Request_Control::0      5055848                      
+system.ruby.network.routers08.msg_bytes.Request_Control::1      4938240                      
+system.ruby.network.routers08.msg_bytes.Response_Data::2     88885728                      
+system.ruby.network.routers08.msg_bytes.ResponseL2hit_Data::2       442728                      
+system.ruby.network.routers08.msg_bytes.Response_Control::2        24304                      
+system.ruby.network.routers08.msg_bytes.Writeback_Data::2     60973056                      
+system.ruby.network.routers08.msg_bytes.Writeback_Control::0     10108144                      
+system.ruby.network.routers08.msg_bytes.Writeback_Control::1      9869264                      
+system.ruby.network.routers08.msg_bytes.Writeback_Control::2      3148520                      
+system.ruby.network.routers08.msg_bytes.Forwarded_Control::0        68416                      
+system.ruby.network.routers08.msg_bytes.Invalidate_Control::0           88                      
+system.ruby.network.routers08.msg_bytes.Unblock_Control::2     10056096                      
 system.ruby.memctrl_clk_domain.clock                3                       # Clock period in ticks
-system.ruby.dir_cntrl0.memBuffer.memReq        820394                       # Total number of memory requests
-system.ruby.dir_cntrl0.memBuffer.memRead       605143                       # Number of memory reads
-system.ruby.dir_cntrl0.memBuffer.memWrite       215243                       # Number of memory writes
-system.ruby.dir_cntrl0.memBuffer.memRefresh        51955                       # Number of memory refreshes
-system.ruby.dir_cntrl0.memBuffer.memWaitCycles     11786270                       # Delay stalled at the head of the bank queue
-system.ruby.dir_cntrl0.memBuffer.memInputQ      6968030                       # Delay in the input queue
-system.ruby.dir_cntrl0.memBuffer.memBankQ      3665383                       # Delay behind the head of the bank queue
-system.ruby.dir_cntrl0.memBuffer.totalStalls     22419683                       # Total number of stall cycles
-system.ruby.dir_cntrl0.memBuffer.stallsPerReq    27.327946                       # Expected number of stall cycles per request
-system.ruby.dir_cntrl0.memBuffer.memBankBusy      2079686                       # memory stalls due to busy bank
-system.ruby.dir_cntrl0.memBuffer.memBusBusy      3902603                       # memory stalls due to busy bus
-system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy       208436                       # memory stalls due to read write turnaround
-system.ruby.dir_cntrl0.memBuffer.memDataBusBusy      1319186                       # memory stalls due to read read turnaround
-system.ruby.dir_cntrl0.memBuffer.memArbWait      2932982                       # memory stalls due to arbitration
-system.ruby.dir_cntrl0.memBuffer.memNotOld      1343377                       # memory stalls due to anti starvation
-system.ruby.dir_cntrl0.memBuffer.memBankCount |       25992      3.17%      3.17% |       25482      3.11%      6.27% |       25735      3.14%      9.41% |       25728      3.14%     12.55% |       25931      3.16%     15.71% |       25829      3.15%     18.86% |       25430      3.10%     21.96% |       25686      3.13%     25.09% |       25772      3.14%     28.23% |       25394      3.10%     31.32% |       25765      3.14%     34.46% |       25528      3.11%     37.58% |       25775      3.14%     40.72% |       25820      3.15%     43.87% |       25548      3.11%     46.98% |       25750      3.14%     50.12% |       25378      3.09%     53.21% |       25625      3.12%     56.33% |       25783      3.14%     59.48% |       25254      3.08%     62.56% |       25786      3.14%     65.70% |       25466      3.10%     68.80% |       25638      3.13%     71.93% |       25430      3.10%     75.03% |       25799      3.14%     78.17% |       25685      3.13%     81.30% |       25362      3.09%     84.39% |       25641      3.13%     87.52% |       25676      3.13%     90.65% |       25658      3.13%     93.78% |       25720      3.14%     96.91% |       25328      3.09%    100.00% # Number of accesses per bank
-system.ruby.dir_cntrl0.memBuffer.memBankCount::total       820394                       # Number of accesses per bank
-system.ruby.network.routers09.percent_links_utilized    34.059110                      
-system.ruby.network.routers09.msg_count.Request_Control::1       605151                      
-system.ruby.network.routers09.msg_count.Response_Data::2       605138                      
-system.ruby.network.routers09.msg_count.Writeback_Data::2       215243                      
-system.ruby.network.routers09.msg_count.Writeback_Control::1      1209343                      
-system.ruby.network.routers09.msg_count.Writeback_Control::2       389402                      
-system.ruby.network.routers09.msg_count.Unblock_Control::2       605124                      
-system.ruby.network.routers09.msg_bytes.Request_Control::1      4841208                      
-system.ruby.network.routers09.msg_bytes.Response_Data::2     43569936                      
-system.ruby.network.routers09.msg_bytes.Writeback_Data::2     15497496                      
-system.ruby.network.routers09.msg_bytes.Writeback_Control::1      9674744                      
-system.ruby.network.routers09.msg_bytes.Writeback_Control::2      3115216                      
-system.ruby.network.routers09.msg_bytes.Unblock_Control::2      4840992                      
-system.ruby.network.routers10.percent_links_utilized    15.882986                      
-system.ruby.network.routers10.msg_count.Request_Control::0       619494                      
-system.ruby.network.routers10.msg_count.Request_Control::1       605151                      
-system.ruby.network.routers10.msg_count.Response_Data::2      1210252                      
-system.ruby.network.routers10.msg_count.ResponseL2hit_Data::2         5922                      
-system.ruby.network.routers10.msg_count.ResponseLocal_Data::2         8420                      
-system.ruby.network.routers10.msg_count.Response_Control::2         3004                      
-system.ruby.network.routers10.msg_count.Writeback_Data::2       826501                      
-system.ruby.network.routers10.msg_count.Writeback_Control::0      1238596                      
-system.ruby.network.routers10.msg_count.Writeback_Control::1      1209317                      
-system.ruby.network.routers10.msg_count.Writeback_Control::2       389402                      
-system.ruby.network.routers10.msg_count.Forwarded_Control::0         8421                      
-system.ruby.network.routers10.msg_count.Invalidate_Control::0           19                      
-system.ruby.network.routers10.msg_count.Unblock_Control::2      1232268                      
-system.ruby.network.routers10.msg_bytes.Request_Control::0      4955952                      
-system.ruby.network.routers10.msg_bytes.Request_Control::1      4841208                      
-system.ruby.network.routers10.msg_bytes.Response_Data::2     87138144                      
-system.ruby.network.routers10.msg_bytes.ResponseL2hit_Data::2       426384                      
-system.ruby.network.routers10.msg_bytes.ResponseLocal_Data::2       606240                      
-system.ruby.network.routers10.msg_bytes.Response_Control::2        24032                      
-system.ruby.network.routers10.msg_bytes.Writeback_Data::2     59508072                      
-system.ruby.network.routers10.msg_bytes.Writeback_Control::0      9908768                      
-system.ruby.network.routers10.msg_bytes.Writeback_Control::1      9674536                      
-system.ruby.network.routers10.msg_bytes.Writeback_Control::2      3115216                      
-system.ruby.network.routers10.msg_bytes.Forwarded_Control::0        67368                      
-system.ruby.network.routers10.msg_bytes.Invalidate_Control::0          152                      
-system.ruby.network.routers10.msg_bytes.Unblock_Control::2      9858144                      
-system.ruby.network.msg_count.Request_Control      3673936                      
-system.ruby.network.msg_count.Response_Data      3630768                      
-system.ruby.network.msg_count.ResponseL2hit_Data        17766                      
-system.ruby.network.msg_count.ResponseLocal_Data        25260                      
-system.ruby.network.msg_count.Response_Control         9012                      
-system.ruby.network.msg_count.Writeback_Data      2479504                      
-system.ruby.network.msg_count.Writeback_Control      8511972                      
-system.ruby.network.msg_count.Forwarded_Control        25263                      
-system.ruby.network.msg_count.Invalidate_Control           57                      
-system.ruby.network.msg_count.Unblock_Control      3696804                      
-system.ruby.network.msg_byte.Request_Control     29391488                      
-system.ruby.network.msg_byte.Response_Data    261415296                      
-system.ruby.network.msg_byte.ResponseL2hit_Data      1279152                      
-system.ruby.network.msg_byte.ResponseLocal_Data      1818720                      
-system.ruby.network.msg_byte.Response_Control        72096                      
-system.ruby.network.msg_byte.Writeback_Data    178524288                      
-system.ruby.network.msg_byte.Writeback_Control     68095776                      
-system.ruby.network.msg_byte.Forwarded_Control       202104                      
-system.ruby.network.msg_byte.Invalidate_Control          456                      
-system.ruby.network.msg_byte.Unblock_Control     29574432                      
+system.ruby.dir_cntrl0.memBuffer.memReq        840532                       # Total number of memory requests
+system.ruby.dir_cntrl0.memBuffer.memRead       617276                       # Number of memory reads
+system.ruby.dir_cntrl0.memBuffer.memWrite       223251                       # Number of memory writes
+system.ruby.dir_cntrl0.memBuffer.memRefresh        53097                       # Number of memory refreshes
+system.ruby.dir_cntrl0.memBuffer.memWaitCycles     12084618                       # Delay stalled at the head of the bank queue
+system.ruby.dir_cntrl0.memBuffer.memInputQ      7109815                       # Delay in the input queue
+system.ruby.dir_cntrl0.memBuffer.memBankQ      3756357                       # Delay behind the head of the bank queue
+system.ruby.dir_cntrl0.memBuffer.totalStalls     22950790                       # Total number of stall cycles
+system.ruby.dir_cntrl0.memBuffer.stallsPerReq    27.305076                       # Expected number of stall cycles per request
+system.ruby.dir_cntrl0.memBuffer.memBankBusy      2125863                       # memory stalls due to busy bank
+system.ruby.dir_cntrl0.memBuffer.memBusBusy      3998707                       # memory stalls due to busy bus
+system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy       215811                       # memory stalls due to read write turnaround
+system.ruby.dir_cntrl0.memBuffer.memDataBusBusy      1338863                       # memory stalls due to read read turnaround
+system.ruby.dir_cntrl0.memBuffer.memArbWait      3014396                       # memory stalls due to arbitration
+system.ruby.dir_cntrl0.memBuffer.memNotOld      1390978                       # memory stalls due to anti starvation
+system.ruby.dir_cntrl0.memBuffer.memBankCount |       26168      3.11%      3.11% |       26574      3.16%      6.27% |       26455      3.15%      9.42% |       26511      3.15%     12.58% |       26226      3.12%     15.70% |       26782      3.19%     18.88% |       26319      3.13%     22.01% |       26430      3.14%     25.16% |       26348      3.13%     28.29% |       26005      3.09%     31.39% |       26264      3.12%     34.51% |       26345      3.13%     37.65% |       26533      3.16%     40.80% |       26231      3.12%     43.92% |       26065      3.10%     47.02% |       26208      3.12%     50.14% |       26194      3.12%     53.26% |       26013      3.09%     56.35% |       26137      3.11%     59.46% |       26424      3.14%     62.61% |       25919      3.08%     65.69% |       26330      3.13%     68.82% |       26181      3.11%     71.94% |       26372      3.14%     75.08% |       26420      3.14%     78.22% |       26347      3.13%     81.35% |       26285      3.13%     84.48% |       25978      3.09%     87.57% |       26022      3.10%     90.67% |       25911      3.08%     93.75% |       26364      3.14%     96.89% |       26171      3.11%    100.00% # Number of accesses per bank
+system.ruby.dir_cntrl0.memBuffer.memBankCount::total       840532                       # Number of accesses per bank
+system.ruby.network.routers09.percent_links_utilized    34.091732                      
+system.ruby.network.routers09.msg_count.Request_Control::1       617280                      
+system.ruby.network.routers09.msg_count.Response_Data::2       617270                      
+system.ruby.network.routers09.msg_count.Writeback_Data::2       223252                      
+system.ruby.network.routers09.msg_count.Writeback_Control::1      1233682                      
+system.ruby.network.routers09.msg_count.Writeback_Control::2       393565                      
+system.ruby.network.routers09.msg_count.Unblock_Control::2       617253                      
+system.ruby.network.routers09.msg_bytes.Request_Control::1      4938240                      
+system.ruby.network.routers09.msg_bytes.Response_Data::2     44443440                      
+system.ruby.network.routers09.msg_bytes.Writeback_Data::2     16074144                      
+system.ruby.network.routers09.msg_bytes.Writeback_Control::1      9869456                      
+system.ruby.network.routers09.msg_bytes.Writeback_Control::2      3148520                      
+system.ruby.network.routers09.msg_bytes.Unblock_Control::2      4938024                      
+system.ruby.network.routers10.percent_links_utilized    15.873398                      
+system.ruby.network.routers10.msg_count.Request_Control::0       631981                      
+system.ruby.network.routers10.msg_count.Request_Control::1       617280                      
+system.ruby.network.routers10.msg_count.Response_Data::2      1234523                      
+system.ruby.network.routers10.msg_count.ResponseL2hit_Data::2         6149                      
+system.ruby.network.routers10.msg_count.ResponseLocal_Data::2         8552                      
+system.ruby.network.routers10.msg_count.Response_Control::2         3049                      
+system.ruby.network.routers10.msg_count.Writeback_Data::2       846848                      
+system.ruby.network.routers10.msg_count.Writeback_Control::0      1263518                      
+system.ruby.network.routers10.msg_count.Writeback_Control::1      1233658                      
+system.ruby.network.routers10.msg_count.Writeback_Control::2       393565                      
+system.ruby.network.routers10.msg_count.Forwarded_Control::0         8552                      
+system.ruby.network.routers10.msg_count.Invalidate_Control::0           11                      
+system.ruby.network.routers10.msg_count.Unblock_Control::2      1257012                      
+system.ruby.network.routers10.msg_bytes.Request_Control::0      5055848                      
+system.ruby.network.routers10.msg_bytes.Request_Control::1      4938240                      
+system.ruby.network.routers10.msg_bytes.Response_Data::2     88885656                      
+system.ruby.network.routers10.msg_bytes.ResponseL2hit_Data::2       442728                      
+system.ruby.network.routers10.msg_bytes.ResponseLocal_Data::2       615744                      
+system.ruby.network.routers10.msg_bytes.Response_Control::2        24392                      
+system.ruby.network.routers10.msg_bytes.Writeback_Data::2     60973056                      
+system.ruby.network.routers10.msg_bytes.Writeback_Control::0     10108144                      
+system.ruby.network.routers10.msg_bytes.Writeback_Control::1      9869264                      
+system.ruby.network.routers10.msg_bytes.Writeback_Control::2      3148520                      
+system.ruby.network.routers10.msg_bytes.Forwarded_Control::0        68416                      
+system.ruby.network.routers10.msg_bytes.Invalidate_Control::0           88                      
+system.ruby.network.routers10.msg_bytes.Unblock_Control::2     10056096                      
+system.ruby.network.msg_count.Request_Control      3747784                      
+system.ruby.network.msg_count.Response_Data      3703577                      
+system.ruby.network.msg_count.ResponseL2hit_Data        18447                      
+system.ruby.network.msg_count.ResponseLocal_Data        25656                      
+system.ruby.network.msg_count.Response_Control         9147                      
+system.ruby.network.msg_count.Writeback_Data      2540544                      
+system.ruby.network.msg_count.Writeback_Control      8672248                      
+system.ruby.network.msg_count.Forwarded_Control        25656                      
+system.ruby.network.msg_count.Invalidate_Control           33                      
+system.ruby.network.msg_count.Unblock_Control      3771042                      
+system.ruby.network.msg_byte.Request_Control     29982272                      
+system.ruby.network.msg_byte.Response_Data    266657544                      
+system.ruby.network.msg_byte.ResponseL2hit_Data      1328184                      
+system.ruby.network.msg_byte.ResponseLocal_Data      1847232                      
+system.ruby.network.msg_byte.Response_Control        73176                      
+system.ruby.network.msg_byte.Writeback_Data    182919168                      
+system.ruby.network.msg_byte.Writeback_Control     69377984                      
+system.ruby.network.msg_byte.Forwarded_Control       205248                      
+system.ruby.network.msg_byte.Invalidate_Control          264                      
+system.ruby.network.msg_byte.Unblock_Control     30168336                      
 system.funcbus.throughput                           0                       # Throughput (bytes/s)
 system.funcbus.data_through_bus                     0                       # Total data (bytes)
 system.cpu_clk_domain.clock                         1                       # Clock period in ticks
-system.cpu0.num_reads                           99553                       # number of read accesses completed
-system.cpu0.num_writes                          54274                       # number of write accesses completed
+system.cpu0.num_reads                           99316                       # number of read accesses completed
+system.cpu0.num_writes                          55500                       # number of write accesses completed
 system.cpu0.num_copies                              0                       # number of copy accesses completed
-system.cpu1.num_reads                           99453                       # number of read accesses completed
-system.cpu1.num_writes                          54478                       # number of write accesses completed
+system.cpu1.num_reads                           99690                       # number of read accesses completed
+system.cpu1.num_writes                          55732                       # number of write accesses completed
 system.cpu1.num_copies                              0                       # number of copy accesses completed
-system.cpu2.num_reads                           98747                       # number of read accesses completed
-system.cpu2.num_writes                          53976                       # number of write accesses completed
+system.cpu2.num_reads                           99856                       # number of read accesses completed
+system.cpu2.num_writes                          55785                       # number of write accesses completed
 system.cpu2.num_copies                              0                       # number of copy accesses completed
-system.cpu3.num_reads                           99232                       # number of read accesses completed
-system.cpu3.num_writes                          54121                       # number of write accesses completed
+system.cpu3.num_reads                           99241                       # number of read accesses completed
+system.cpu3.num_writes                          55367                       # number of write accesses completed
 system.cpu3.num_copies                              0                       # number of copy accesses completed
-system.cpu4.num_reads                           99563                       # number of read accesses completed
-system.cpu4.num_writes                          53960                       # number of write accesses completed
+system.cpu4.num_reads                           99899                       # number of read accesses completed
+system.cpu4.num_writes                          55499                       # number of write accesses completed
 system.cpu4.num_copies                              0                       # number of copy accesses completed
-system.cpu5.num_reads                           99501                       # number of read accesses completed
-system.cpu5.num_writes                          54015                       # number of write accesses completed
+system.cpu5.num_reads                          100000                       # number of read accesses completed
+system.cpu5.num_writes                          55860                       # number of write accesses completed
 system.cpu5.num_copies                              0                       # number of copy accesses completed
-system.cpu6.num_reads                          100000                       # number of read accesses completed
-system.cpu6.num_writes                          54332                       # number of write accesses completed
+system.cpu6.num_reads                           99699                       # number of read accesses completed
+system.cpu6.num_writes                          55767                       # number of write accesses completed
 system.cpu6.num_copies                              0                       # number of copy accesses completed
-system.cpu7.num_reads                           99277                       # number of read accesses completed
-system.cpu7.num_writes                          53851                       # number of write accesses completed
+system.cpu7.num_reads                           99546                       # number of read accesses completed
+system.cpu7.num_writes                          55623                       # number of write accesses completed
 system.cpu7.num_copies                              0                       # number of copy accesses completed
-system.ruby.network.routers00.throttle0.link_utilization     5.173589                      
-system.ruby.network.routers00.throttle0.msg_count.Response_Data::2        75499                      
-system.ruby.network.routers00.throttle0.msg_count.ResponseL2hit_Data::2          705                      
-system.ruby.network.routers00.throttle0.msg_count.ResponseLocal_Data::2         1064                      
-system.ruby.network.routers00.throttle0.msg_count.Response_Control::2          376                      
-system.ruby.network.routers00.throttle0.msg_count.Writeback_Control::0        77242                      
-system.ruby.network.routers00.throttle0.msg_count.Forwarded_Control::0         1082                      
-system.ruby.network.routers00.throttle0.msg_count.Invalidate_Control::0            6                      
-system.ruby.network.routers00.throttle0.msg_bytes.Response_Data::2      5435928                      
-system.ruby.network.routers00.throttle0.msg_bytes.ResponseL2hit_Data::2        50760                      
-system.ruby.network.routers00.throttle0.msg_bytes.ResponseLocal_Data::2        76608                      
-system.ruby.network.routers00.throttle0.msg_bytes.Response_Control::2         3008                      
-system.ruby.network.routers00.throttle0.msg_bytes.Writeback_Control::0       617936                      
-system.ruby.network.routers00.throttle0.msg_bytes.Forwarded_Control::0         8656                      
-system.ruby.network.routers00.throttle0.msg_bytes.Invalidate_Control::0           48                      
-system.ruby.network.routers00.throttle1.link_utilization     6.204934                      
-system.ruby.network.routers00.throttle1.msg_count.Request_Control::0        77272                      
-system.ruby.network.routers00.throttle1.msg_count.ResponseLocal_Data::2         1082                      
-system.ruby.network.routers00.throttle1.msg_count.Response_Control::2            6                      
-system.ruby.network.routers00.throttle1.msg_count.Writeback_Data::2        76215                      
-system.ruby.network.routers00.throttle1.msg_count.Writeback_Control::0        77243                      
-system.ruby.network.routers00.throttle1.msg_count.Unblock_Control::2        78243                      
-system.ruby.network.routers00.throttle1.msg_bytes.Request_Control::0       618176                      
-system.ruby.network.routers00.throttle1.msg_bytes.ResponseLocal_Data::2        77904                      
-system.ruby.network.routers00.throttle1.msg_bytes.Response_Control::2           48                      
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+system.ruby.network.routers10.throttle7.msg_bytes.Response_Control::2         2896                      
+system.ruby.network.routers10.throttle7.msg_bytes.Writeback_Control::0       629744                      
+system.ruby.network.routers10.throttle7.msg_bytes.Forwarded_Control::0         8512                      
+system.ruby.network.routers10.throttle8.link_utilization    89.512362                      
+system.ruby.network.routers10.throttle8.msg_count.Request_Control::0       631981                      
+system.ruby.network.routers10.throttle8.msg_count.Response_Data::2       617263                      
+system.ruby.network.routers10.throttle8.msg_count.Writeback_Data::2       623596                      
+system.ruby.network.routers10.throttle8.msg_count.Writeback_Control::0       631759                      
+system.ruby.network.routers10.throttle8.msg_count.Writeback_Control::1       616817                      
+system.ruby.network.routers10.throttle8.msg_count.Unblock_Control::2       639759                      
+system.ruby.network.routers10.throttle8.msg_bytes.Request_Control::0      5055848                      
+system.ruby.network.routers10.throttle8.msg_bytes.Response_Data::2     44442936                      
+system.ruby.network.routers10.throttle8.msg_bytes.Writeback_Data::2     44898912                      
+system.ruby.network.routers10.throttle8.msg_bytes.Writeback_Control::0      5054072                      
+system.ruby.network.routers10.throttle8.msg_bytes.Writeback_Control::1      4934536                      
+system.ruby.network.routers10.throttle8.msg_bytes.Unblock_Control::2      5118072                      
+system.ruby.network.routers10.throttle9.link_utilization    27.820196                      
+system.ruby.network.routers10.throttle9.msg_count.Request_Control::1       617280                      
+system.ruby.network.routers10.throttle9.msg_count.Writeback_Data::2       223252                      
+system.ruby.network.routers10.throttle9.msg_count.Writeback_Control::1       616841                      
+system.ruby.network.routers10.throttle9.msg_count.Writeback_Control::2       393565                      
+system.ruby.network.routers10.throttle9.msg_count.Unblock_Control::2       617253                      
+system.ruby.network.routers10.throttle9.msg_bytes.Request_Control::1      4938240                      
+system.ruby.network.routers10.throttle9.msg_bytes.Writeback_Data::2     16074144                      
+system.ruby.network.routers10.throttle9.msg_bytes.Writeback_Control::1      4934728                      
+system.ruby.network.routers10.throttle9.msg_bytes.Writeback_Control::2      3148520                      
+system.ruby.network.routers10.throttle9.msg_bytes.Unblock_Control::2      4938024                      
 system.ruby.LD.latency_hist::bucket_size         2048                      
 system.ruby.LD.latency_hist::max_bucket         20479                      
-system.ruby.LD.latency_hist::samples           402593                      
-system.ruby.LD.latency_hist::mean         1545.043245                      
-system.ruby.LD.latency_hist::gmean        1028.893138                      
-system.ruby.LD.latency_hist::stdev        1540.768510                      
-system.ruby.LD.latency_hist              |      303266     75.33%     75.33% |       69452     17.25%     92.58% |       21307      5.29%     97.87% |        6321      1.57%     99.44% |        1780      0.44%     99.88% |         373      0.09%     99.98% |          85      0.02%    100.00% |           6      0.00%    100.00% |           3      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.LD.latency_hist::total             402593                      
+system.ruby.LD.latency_hist::samples           406981                      
+system.ruby.LD.latency_hist::mean         1548.085817                      
+system.ruby.LD.latency_hist::gmean        1028.850116                      
+system.ruby.LD.latency_hist::stdev        1547.317259                      
+system.ruby.LD.latency_hist              |      306593     75.33%     75.33% |       69760     17.14%     92.47% |       21891      5.38%     97.85% |        6472      1.59%     99.44% |        1757      0.43%     99.88% |         406      0.10%     99.97% |          83      0.02%    100.00% |          18      0.00%    100.00% |           1      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.latency_hist::total             406981                      
 system.ruby.LD.hit_latency_hist::bucket_size            1                      
 system.ruby.LD.hit_latency_hist::max_bucket            9                      
-system.ruby.LD.hit_latency_hist::samples          125                      
+system.ruby.LD.hit_latency_hist::samples          113                      
 system.ruby.LD.hit_latency_hist::mean               3                      
 system.ruby.LD.hit_latency_hist::gmean       3.000000                      
-system.ruby.LD.hit_latency_hist          |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |         125    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.LD.hit_latency_hist::total            125                      
+system.ruby.LD.hit_latency_hist          |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |         113    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.hit_latency_hist::total            113                      
 system.ruby.LD.miss_latency_hist::bucket_size         2048                      
 system.ruby.LD.miss_latency_hist::max_bucket        20479                      
-system.ruby.LD.miss_latency_hist::samples       402468                      
-system.ruby.LD.miss_latency_hist::mean    1545.522178                      
-system.ruby.LD.miss_latency_hist::gmean   1030.760288                      
-system.ruby.LD.miss_latency_hist::stdev   1540.768039                      
-system.ruby.LD.miss_latency_hist         |      303141     75.32%     75.32% |       69452     17.26%     92.58% |       21307      5.29%     97.87% |        6321      1.57%     99.44% |        1780      0.44%     99.88% |         373      0.09%     99.98% |          85      0.02%    100.00% |           6      0.00%    100.00% |           3      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.LD.miss_latency_hist::total        402468                      
+system.ruby.LD.miss_latency_hist::samples       406868                      
+system.ruby.LD.miss_latency_hist::mean    1548.514936                      
+system.ruby.LD.miss_latency_hist::gmean   1030.519523                      
+system.ruby.LD.miss_latency_hist::stdev   1547.317818                      
+system.ruby.LD.miss_latency_hist         |      306480     75.33%     75.33% |       69760     17.15%     92.47% |       21891      5.38%     97.85% |        6472      1.59%     99.44% |        1757      0.43%     99.88% |         406      0.10%     99.97% |          83      0.02%    100.00% |          18      0.00%    100.00% |           1      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.miss_latency_hist::total        406868                      
 system.ruby.ST.latency_hist::bucket_size         2048                      
 system.ruby.ST.latency_hist::max_bucket         20479                      
-system.ruby.ST.latency_hist::samples           217067                      
-system.ruby.ST.latency_hist::mean         1544.956027                      
-system.ruby.ST.latency_hist::gmean        1029.811241                      
-system.ruby.ST.latency_hist::stdev        1539.607599                      
-system.ruby.ST.latency_hist              |      163681     75.41%     75.41% |       37227     17.15%     92.56% |       11599      5.34%     97.90% |        3358      1.55%     99.45% |         949      0.44%     99.88% |         204      0.09%     99.98% |          44      0.02%    100.00% |           5      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.ST.latency_hist::total             217067                      
+system.ruby.ST.latency_hist::samples           225146                      
+system.ruby.ST.latency_hist::mean         1547.516998                      
+system.ruby.ST.latency_hist::gmean        1031.853555                      
+system.ruby.ST.latency_hist::stdev        1543.988015                      
+system.ruby.ST.latency_hist              |      169789     75.41%     75.41% |       38573     17.13%     92.55% |       11917      5.29%     97.84% |        3626      1.61%     99.45% |         964      0.43%     99.88% |         219      0.10%     99.97% |          41      0.02%     99.99% |          15      0.01%    100.00% |           2      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.latency_hist::total             225146                      
 system.ruby.ST.hit_latency_hist::bucket_size            1                      
 system.ruby.ST.hit_latency_hist::max_bucket            9                      
-system.ruby.ST.hit_latency_hist::samples           67                      
+system.ruby.ST.hit_latency_hist::samples           53                      
 system.ruby.ST.hit_latency_hist::mean               3                      
 system.ruby.ST.hit_latency_hist::gmean       3.000000                      
-system.ruby.ST.hit_latency_hist          |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |          67    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.ST.hit_latency_hist::total             67                      
+system.ruby.ST.hit_latency_hist          |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |          53    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.hit_latency_hist::total             53                      
 system.ruby.ST.miss_latency_hist::bucket_size         2048                      
 system.ruby.ST.miss_latency_hist::max_bucket        20479                      
-system.ruby.ST.miss_latency_hist::samples       217000                      
-system.ruby.ST.miss_latency_hist::mean    1545.432115                      
-system.ruby.ST.miss_latency_hist::gmean   1031.669331                      
-system.ruby.ST.miss_latency_hist::stdev   1539.606800                      
-system.ruby.ST.miss_latency_hist         |      163614     75.40%     75.40% |       37227     17.16%     92.55% |       11599      5.35%     97.90% |        3358      1.55%     99.45% |         949      0.44%     99.88% |         204      0.09%     99.98% |          44      0.02%    100.00% |           5      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.ST.miss_latency_hist::total        217000                      
-system.ruby.L1Cache_Controller.Load      |       50249     12.48%     12.48% |       50370     12.51%     24.99% |       49923     12.40%     37.38% |       50235     12.47%     49.86% |       50375     12.51%     62.37% |       50577     12.56%     74.93% |       50611     12.57%     87.49% |       50361     12.51%    100.00%
-system.ruby.L1Cache_Controller.Load::total       402701                      
-system.ruby.L1Cache_Controller.Store     |       27052     12.46%     12.46% |       27339     12.59%     25.05% |       27175     12.52%     37.57% |       27153     12.51%     50.08% |       27079     12.47%     62.55% |       26983     12.43%     74.98% |       27113     12.49%     87.47% |       27205     12.53%    100.00%
-system.ruby.L1Cache_Controller.Store::total       217099                      
-system.ruby.L1Cache_Controller.L1_Replacement |     9611009     12.51%     12.51% |     9602265     12.49%     25.00% |     9618315     12.51%     37.51% |     9608777     12.50%     50.02% |     9608029     12.50%     62.52% |     9605100     12.50%     75.02% |     9598595     12.49%     87.50% |     9603783     12.50%    100.00%
-system.ruby.L1Cache_Controller.L1_Replacement::total     76855873                      
-system.ruby.L1Cache_Controller.Own_GETX  |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           1    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.L1Cache_Controller.Own_GETX::total            1                      
-system.ruby.L1Cache_Controller.Fwd_GETX  |         395     12.44%     12.44% |         352     11.09%     23.53% |         364     11.47%     35.00% |         433     13.64%     48.65% |         393     12.38%     61.03% |         374     11.78%     72.81% |         406     12.79%     85.60% |         457     14.40%    100.00%
-system.ruby.L1Cache_Controller.Fwd_GETX::total         3174                      
-system.ruby.L1Cache_Controller.Fwd_GETS  |         764     13.27%     13.27% |         770     13.37%     26.64% |         739     12.83%     39.48% |         739     12.83%     52.31% |         692     12.02%     64.33% |         715     12.42%     76.75% |         690     11.98%     88.73% |         649     11.27%    100.00%
-system.ruby.L1Cache_Controller.Fwd_GETS::total         5758                      
-system.ruby.L1Cache_Controller.Inv       |           6     31.58%     31.58% |           3     15.79%     47.37% |           0      0.00%     47.37% |           3     15.79%     63.16% |           2     10.53%     73.68% |           1      5.26%     78.95% |           3     15.79%     94.74% |           1      5.26%    100.00%
-system.ruby.L1Cache_Controller.Inv::total           19                      
-system.ruby.L1Cache_Controller.Ack       |         376     12.52%     12.52% |         376     12.52%     25.03% |         382     12.72%     37.75% |         351     11.68%     49.43% |         372     12.38%     61.82% |         350     11.65%     73.47% |         417     13.88%     87.35% |         380     12.65%    100.00%
-system.ruby.L1Cache_Controller.Ack::total         3004                      
-system.ruby.L1Cache_Controller.Data      |         720     12.65%     12.65% |         712     12.51%     25.17% |         716     12.58%     37.75% |         661     11.62%     49.37% |         738     12.97%     62.34% |         721     12.67%     75.01% |         703     12.36%     87.36% |         719     12.64%    100.00%
-system.ruby.L1Cache_Controller.Data::total         5690                      
-system.ruby.L1Cache_Controller.Exclusive_Data |       76548     12.47%     12.47% |       76964     12.54%     25.01% |       76362     12.44%     37.45% |       76663     12.49%     49.94% |       76686     12.49%     62.44% |       76787     12.51%     74.95% |       76960     12.54%     87.49% |       76807     12.51%    100.00%
-system.ruby.L1Cache_Controller.Exclusive_Data::total       613777                      
-system.ruby.L1Cache_Controller.Writeback_Ack |         637     12.77%     12.77% |         632     12.67%     25.44% |         612     12.27%     37.70% |         579     11.61%     49.31% |         639     12.81%     62.12% |         632     12.67%     74.78% |         619     12.41%     87.19% |         639     12.81%    100.00%
-system.ruby.L1Cache_Controller.Writeback_Ack::total         4989                      
-system.ruby.L1Cache_Controller.Writeback_Ack_Data |       76553     12.47%     12.47% |       76972     12.54%     25.01% |       76401     12.44%     37.45% |       76678     12.49%     49.94% |       76717     12.50%     62.44% |       76818     12.51%     74.95% |       76980     12.54%     87.49% |       76828     12.51%    100.00%
-system.ruby.L1Cache_Controller.Writeback_Ack_Data::total       613947                      
-system.ruby.L1Cache_Controller.Writeback_Nack |          52     14.36%     14.36% |          53     14.64%     29.01% |          49     13.54%     42.54% |          52     14.36%     56.91% |          37     10.22%     67.13% |          44     12.15%     79.28% |          37     10.22%     89.50% |          38     10.50%    100.00%
-system.ruby.L1Cache_Controller.Writeback_Nack::total          362                      
-system.ruby.L1Cache_Controller.All_acks  |       27041     12.46%     12.46% |       27326     12.59%     25.05% |       27165     12.52%     37.57% |       27136     12.51%     50.08% |       27069     12.47%     62.55% |       26960     12.42%     74.98% |       27107     12.49%     87.47% |       27196     12.53%    100.00%
-system.ruby.L1Cache_Controller.All_acks::total       217000                      
-system.ruby.L1Cache_Controller.Use_Timeout |       76548     12.47%     12.47% |       76964     12.54%     25.01% |       76362     12.44%     37.45% |       76664     12.49%     49.94% |       76686     12.49%     62.44% |       76787     12.51%     74.95% |       76959     12.54%     87.49% |       76807     12.51%    100.00%
-system.ruby.L1Cache_Controller.Use_Timeout::total       613777                      
-system.ruby.L1Cache_Controller.I.Load    |       50230     12.48%     12.48% |       50351     12.51%     24.99% |       49916     12.40%     37.39% |       50192     12.47%     49.86% |       50358     12.51%     62.37% |       50550     12.56%     74.93% |       50559     12.56%     87.49% |       50332     12.51%    100.00%
-system.ruby.L1Cache_Controller.I.Load::total       402488                      
-system.ruby.L1Cache_Controller.I.Store   |       27042     12.46%     12.46% |       27328     12.59%     25.05% |       27166     12.52%     37.57% |       27136     12.50%     50.08% |       27070     12.47%     62.55% |       26961     12.42%     74.98% |       27107     12.49%     87.47% |       27196     12.53%    100.00%
-system.ruby.L1Cache_Controller.I.Store::total       217006                      
-system.ruby.L1Cache_Controller.I.L1_Replacement |          70     13.78%     13.78% |          67     13.19%     26.97% |          65     12.80%     39.76% |          64     12.60%     52.36% |          67     13.19%     65.55% |          57     11.22%     76.77% |          62     12.20%     88.98% |          56     11.02%    100.00%
-system.ruby.L1Cache_Controller.I.L1_Replacement::total          508                      
-system.ruby.L1Cache_Controller.S.Load    |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           1    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.L1Cache_Controller.S.Load::total            1                      
-system.ruby.L1Cache_Controller.S.L1_Replacement |         719     12.65%     12.65% |         712     12.53%     25.18% |         716     12.60%     37.78% |         660     11.61%     49.39% |         736     12.95%     62.34% |         720     12.67%     75.01% |         701     12.34%     87.35% |         719     12.65%    100.00%
-system.ruby.L1Cache_Controller.S.L1_Replacement::total         5683                      
-system.ruby.L1Cache_Controller.S.Inv     |           1     14.29%     14.29% |           0      0.00%     14.29% |           0      0.00%     14.29% |           1     14.29%     28.57% |           2     28.57%     57.14% |           1     14.29%     71.43% |           2     28.57%    100.00% |           0      0.00%    100.00%
-system.ruby.L1Cache_Controller.S.Inv::total            7                      
-system.ruby.L1Cache_Controller.O.Store   |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           1    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.L1Cache_Controller.O.Store::total            1                      
-system.ruby.L1Cache_Controller.O.L1_Replacement |          50     14.75%     14.75% |          43     12.68%     27.43% |          42     12.39%     39.82% |          40     11.80%     51.62% |          37     10.91%     62.54% |          50     14.75%     77.29% |          34     10.03%     87.32% |          43     12.68%    100.00%
-system.ruby.L1Cache_Controller.O.L1_Replacement::total          339                      
-system.ruby.L1Cache_Controller.O.Fwd_GETS |           0      0.00%      0.00% |           2     33.33%     33.33% |           1     16.67%     50.00% |           0      0.00%     50.00% |           1     16.67%     66.67% |           0      0.00%     66.67% |           1     16.67%     83.33% |           1     16.67%    100.00%
-system.ruby.L1Cache_Controller.O.Fwd_GETS::total            6                      
-system.ruby.L1Cache_Controller.M.Load    |           2      8.70%      8.70% |           3     13.04%     21.74% |           2      8.70%     30.43% |           5     21.74%     52.17% |           2      8.70%     60.87% |           5     21.74%     82.61% |           2      8.70%     91.30% |           2      8.70%    100.00%
-system.ruby.L1Cache_Controller.M.Load::total           23                      
-system.ruby.L1Cache_Controller.M.Store   |           3     20.00%     20.00% |           0      0.00%     20.00% |           2     13.33%     33.33% |           2     13.33%     46.67% |           3     20.00%     66.67% |           0      0.00%     66.67% |           0      0.00%     66.67% |           5     33.33%    100.00%
-system.ruby.L1Cache_Controller.M.Store::total           15                      
-system.ruby.L1Cache_Controller.M.L1_Replacement |       49426     12.48%     12.48% |       49555     12.51%     24.98% |       49122     12.40%     37.38% |       49457     12.48%     49.87% |       49545     12.51%     62.37% |       49751     12.56%     74.93% |       49794     12.57%     87.50% |       49535     12.50%    100.00%
-system.ruby.L1Cache_Controller.M.L1_Replacement::total       396185                      
-system.ruby.L1Cache_Controller.M.Fwd_GETX |          24     11.88%     11.88% |          29     14.36%     26.24% |          29     14.36%     40.59% |          27     13.37%     53.96% |          27     13.37%     67.33% |          19      9.41%     76.73% |          22     10.89%     87.62% |          25     12.38%    100.00%
-system.ruby.L1Cache_Controller.M.Fwd_GETX::total          202                      
-system.ruby.L1Cache_Controller.M.Fwd_GETS |          50     14.71%     14.71% |          43     12.65%     27.35% |          42     12.35%     39.71% |          41     12.06%     51.76% |          37     10.88%     62.65% |          50     14.71%     77.35% |          34     10.00%     87.35% |          43     12.65%    100.00%
-system.ruby.L1Cache_Controller.M.Fwd_GETS::total          340                      
-system.ruby.L1Cache_Controller.M_W.Load  |           9     15.79%     15.79% |           8     14.04%     29.82% |           3      5.26%     35.09% |           9     15.79%     50.88% |           7     12.28%     63.16% |           7     12.28%     75.44% |           6     10.53%     85.96% |           8     14.04%    100.00%
-system.ruby.L1Cache_Controller.M_W.Load::total           57                      
-system.ruby.L1Cache_Controller.M_W.Store |           4     12.12%     12.12% |          10     30.30%     42.42% |           2      6.06%     48.48% |           1      3.03%     51.52% |           5     15.15%     66.67% |           7     21.21%     87.88% |           2      6.06%     93.94% |           2      6.06%    100.00%
-system.ruby.L1Cache_Controller.M_W.Store::total           33                      
-system.ruby.L1Cache_Controller.M_W.L1_Replacement |      888542     12.47%     12.47% |      887409     12.46%     24.93% |      886648     12.45%     37.38% |      890208     12.50%     49.88% |      893182     12.54%     62.42% |      893219     12.54%     74.96% |      892511     12.53%     87.49% |      891162     12.51%    100.00%
-system.ruby.L1Cache_Controller.M_W.L1_Replacement::total      7122881                      
-system.ruby.L1Cache_Controller.M_W.Fwd_GETX |          14     12.17%     12.17% |          10      8.70%     20.87% |          15     13.04%     33.91% |          16     13.91%     47.83% |          15     13.04%     60.87% |           9      7.83%     68.70% |          19     16.52%     85.22% |          17     14.78%    100.00%
-system.ruby.L1Cache_Controller.M_W.Fwd_GETX::total          115                      
-system.ruby.L1Cache_Controller.M_W.Fwd_GETS |          35     16.83%     16.83% |          22     10.58%     27.40% |          26     12.50%     39.90% |          25     12.02%     51.92% |          14      6.73%     58.65% |          29     13.94%     72.60% |          32     15.38%     87.98% |          25     12.02%    100.00%
-system.ruby.L1Cache_Controller.M_W.Fwd_GETS::total          208                      
-system.ruby.L1Cache_Controller.M_W.Use_Timeout |       49503     12.48%     12.48% |       49628     12.51%     24.99% |       49195     12.40%     37.39% |       49527     12.48%     49.87% |       49612     12.50%     62.37% |       49820     12.56%     74.93% |       49850     12.56%     87.50% |       49609     12.50%    100.00%
-system.ruby.L1Cache_Controller.M_W.Use_Timeout::total       396744                      
-system.ruby.L1Cache_Controller.MM.Load   |           3     17.65%     17.65% |           3     17.65%     35.29% |           0      0.00%     35.29% |           4     23.53%     58.82% |           3     17.65%     76.47% |           0      0.00%     76.47% |           3     17.65%     94.12% |           1      5.88%    100.00%
-system.ruby.L1Cache_Controller.MM.Load::total           17                      
-system.ruby.L1Cache_Controller.MM.Store  |           0      0.00%      0.00% |           0      0.00%      0.00% |           1     14.29%     14.29% |           3     42.86%     57.14% |           0      0.00%     57.14% |           1     14.29%     71.43% |           1     14.29%     85.71% |           1     14.29%    100.00%
-system.ruby.L1Cache_Controller.MM.Store::total            7                      
-system.ruby.L1Cache_Controller.MM.L1_Replacement |       27003     12.46%     12.46% |       27298     12.59%     25.05% |       27133     12.52%     37.57% |       27103     12.50%     50.08% |       27039     12.47%     62.55% |       26929     12.42%     74.97% |       27071     12.49%     87.46% |       27171     12.54%    100.00%
-system.ruby.L1Cache_Controller.MM.L1_Replacement::total       216747                      
-system.ruby.L1Cache_Controller.MM.Fwd_GETX |           9     10.11%     10.11% |           7      7.87%     17.98% |          14     15.73%     33.71% |          11     12.36%     46.07% |          11     12.36%     58.43% |          13     14.61%     73.03% |          10     11.24%     84.27% |          14     15.73%    100.00%
-system.ruby.L1Cache_Controller.MM.Fwd_GETX::total           89                      
-system.ruby.L1Cache_Controller.MM.Fwd_GETS |          36     17.14%     17.14% |          31     14.76%     31.90% |          22     10.48%     42.38% |          25     11.90%     54.29% |          27     12.86%     67.14% |          24     11.43%     78.57% |          28     13.33%     91.90% |          17      8.10%    100.00%
-system.ruby.L1Cache_Controller.MM.Fwd_GETS::total          210                      
-system.ruby.L1Cache_Controller.MM_W.Load |           4     14.81%     14.81% |           5     18.52%     33.33% |           2      7.41%     40.74% |           5     18.52%     59.26% |           1      3.70%     62.96% |           3     11.11%     74.07% |           4     14.81%     88.89% |           3     11.11%    100.00%
-system.ruby.L1Cache_Controller.MM_W.Load::total           27                      
-system.ruby.L1Cache_Controller.MM_W.Store |           2     16.67%     16.67% |           1      8.33%     25.00% |           2     16.67%     41.67% |           1      8.33%     50.00% |           0      0.00%     50.00% |           2     16.67%     66.67% |           3     25.00%     91.67% |           1      8.33%    100.00%
-system.ruby.L1Cache_Controller.MM_W.Store::total           12                      
-system.ruby.L1Cache_Controller.MM_W.L1_Replacement |      503603     12.54%     12.54% |      505001     12.58%     25.12% |      504191     12.56%     37.68% |      503264     12.54%     50.22% |      498638     12.42%     62.64% |      499252     12.44%     75.08% |      498871     12.43%     87.50% |      501742     12.50%    100.00%
-system.ruby.L1Cache_Controller.MM_W.L1_Replacement::total      4014562                      
-system.ruby.L1Cache_Controller.MM_W.Fwd_GETX |           8     10.67%     10.67% |           6      8.00%     18.67% |           8     10.67%     29.33% |          14     18.67%     48.00% |           9     12.00%     60.00% |          11     14.67%     74.67% |           5      6.67%     81.33% |          14     18.67%    100.00%
-system.ruby.L1Cache_Controller.MM_W.Fwd_GETX::total           75                      
-system.ruby.L1Cache_Controller.MM_W.Fwd_GETS |          20     17.54%     17.54% |          15     13.16%     30.70% |           9      7.89%     38.60% |          19     16.67%     55.26% |          19     16.67%     71.93% |          12     10.53%     82.46% |          18     15.79%     98.25% |           2      1.75%    100.00%
-system.ruby.L1Cache_Controller.MM_W.Fwd_GETS::total          114                      
-system.ruby.L1Cache_Controller.MM_W.Use_Timeout |       27045     12.46%     12.46% |       27336     12.60%     25.06% |       27167     12.52%     37.57% |       27137     12.50%     50.08% |       27074     12.47%     62.55% |       26967     12.43%     74.98% |       27109     12.49%     87.47% |       27198     12.53%    100.00%
-system.ruby.L1Cache_Controller.MM_W.Use_Timeout::total       217033                      
-system.ruby.L1Cache_Controller.IM.L1_Replacement |     2854379     12.51%     12.51% |     2860141     12.54%     25.05% |     2888247     12.66%     37.71% |     2844877     12.47%     50.18% |     2844320     12.47%     62.65% |     2831082     12.41%     75.06% |     2837633     12.44%     87.49% |     2852830     12.51%    100.00%
-system.ruby.L1Cache_Controller.IM.L1_Replacement::total     22813509                      
-system.ruby.L1Cache_Controller.IM.Ack    |         374     12.57%     12.57% |         373     12.54%     25.11% |         380     12.77%     37.88% |         346     11.63%     49.51% |         370     12.44%     61.95% |         346     11.63%     73.58% |         410     13.78%     87.36% |         376     12.64%    100.00%
-system.ruby.L1Cache_Controller.IM.Ack::total         2975                      
-system.ruby.L1Cache_Controller.IM.Exclusive_Data |       27041     12.46%     12.46% |       27326     12.59%     25.05% |       27165     12.52%     37.57% |       27135     12.50%     50.08% |       27069     12.47%     62.55% |       26960     12.42%     74.98% |       27107     12.49%     87.47% |       27196     12.53%    100.00%
-system.ruby.L1Cache_Controller.IM.Exclusive_Data::total       216999                      
-system.ruby.L1Cache_Controller.OM.L1_Replacement |       15977     12.61%     12.61% |       16015     12.64%     25.26% |       16094     12.71%     37.97% |       15787     12.46%     50.43% |       15663     12.37%     62.80% |       15820     12.49%     75.29% |       15975     12.61%     87.90% |       15323     12.10%    100.00%
-system.ruby.L1Cache_Controller.OM.L1_Replacement::total       126654                      
-system.ruby.L1Cache_Controller.OM.Own_GETX |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           1    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.L1Cache_Controller.OM.Own_GETX::total            1                      
-system.ruby.L1Cache_Controller.OM.Ack    |           2      6.90%      6.90% |           3     10.34%     17.24% |           2      6.90%     24.14% |           5     17.24%     41.38% |           2      6.90%     48.28% |           4     13.79%     62.07% |           7     24.14%     86.21% |           4     13.79%    100.00%
-system.ruby.L1Cache_Controller.OM.Ack::total           29                      
-system.ruby.L1Cache_Controller.OM.All_acks |       27041     12.46%     12.46% |       27326     12.59%     25.05% |       27165     12.52%     37.57% |       27136     12.51%     50.08% |       27069     12.47%     62.55% |       26960     12.42%     74.98% |       27107     12.49%     87.47% |       27196     12.53%    100.00%
-system.ruby.L1Cache_Controller.OM.All_acks::total       217000                      
-system.ruby.L1Cache_Controller.IS.L1_Replacement |     5271240     12.50%     12.50% |     5256024     12.47%     24.97% |     5246057     12.44%     37.41% |     5277317     12.52%     49.93% |     5278802     12.52%     62.45% |     5288220     12.54%     75.00% |     5275943     12.51%     87.51% |     5265202     12.49%    100.00%
-system.ruby.L1Cache_Controller.IS.L1_Replacement::total     42158805                      
-system.ruby.L1Cache_Controller.IS.Data   |         720     12.65%     12.65% |         712     12.51%     25.17% |         716     12.58%     37.75% |         661     11.62%     49.37% |         738     12.97%     62.34% |         721     12.67%     75.01% |         703     12.36%     87.36% |         719     12.64%    100.00%
-system.ruby.L1Cache_Controller.IS.Data::total         5690                      
-system.ruby.L1Cache_Controller.IS.Exclusive_Data |       49507     12.48%     12.48% |       49638     12.51%     24.99% |       49197     12.40%     37.39% |       49528     12.48%     49.87% |       49617     12.50%     62.37% |       49827     12.56%     74.93% |       49853     12.56%     87.50% |       49611     12.50%    100.00%
-system.ruby.L1Cache_Controller.IS.Exclusive_Data::total       396778                      
-system.ruby.L1Cache_Controller.SI.Fwd_GETS |           2     25.00%     25.00% |           0      0.00%     25.00% |           3     37.50%     62.50% |           1     12.50%     75.00% |           1     12.50%     87.50% |           0      0.00%     87.50% |           1     12.50%    100.00% |           0      0.00%    100.00%
-system.ruby.L1Cache_Controller.SI.Fwd_GETS::total            8                      
-system.ruby.L1Cache_Controller.SI.Inv    |           5     41.67%     41.67% |           3     25.00%     66.67% |           0      0.00%     66.67% |           2     16.67%     83.33% |           0      0.00%     83.33% |           0      0.00%     83.33% |           1      8.33%     91.67% |           1      8.33%    100.00%
-system.ruby.L1Cache_Controller.SI.Inv::total           12                      
-system.ruby.L1Cache_Controller.SI.Writeback_Ack |         637     12.77%     12.77% |         632     12.67%     25.44% |         612     12.27%     37.70% |         579     11.61%     49.31% |         639     12.81%     62.12% |         632     12.67%     74.78% |         619     12.41%     87.19% |         639     12.81%    100.00%
-system.ruby.L1Cache_Controller.SI.Writeback_Ack::total         4989                      
-system.ruby.L1Cache_Controller.SI.Writeback_Ack_Data |          77     11.29%     11.29% |          77     11.29%     22.58% |         104     15.25%     37.83% |          79     11.58%     49.41% |          97     14.22%     63.64% |          88     12.90%     76.54% |          81     11.88%     88.42% |          79     11.58%    100.00%
-system.ruby.L1Cache_Controller.SI.Writeback_Ack_Data::total          682                      
-system.ruby.L1Cache_Controller.OI.Fwd_GETX |           3     25.00%     25.00% |           1      8.33%     33.33% |           1      8.33%     41.67% |           0      0.00%     41.67% |           2     16.67%     58.33% |           1      8.33%     66.67% |           3     25.00%     91.67% |           1      8.33%    100.00%
-system.ruby.L1Cache_Controller.OI.Fwd_GETX::total           12                      
-system.ruby.L1Cache_Controller.OI.Fwd_GETS |           1      5.00%      5.00% |           5     25.00%     30.00% |           2     10.00%     40.00% |           0      0.00%     40.00% |           4     20.00%     60.00% |           2     10.00%     70.00% |           5     25.00%     95.00% |           1      5.00%    100.00%
-system.ruby.L1Cache_Controller.OI.Fwd_GETS::total           20                      
-system.ruby.L1Cache_Controller.OI.Writeback_Ack_Data |         667     12.88%     12.88% |         694     13.40%     26.28% |         675     13.03%     39.31% |         668     12.90%     52.21% |         624     12.05%     64.26% |         647     12.49%     76.75% |         602     11.62%     88.38% |         602     11.62%    100.00%
-system.ruby.L1Cache_Controller.OI.Writeback_Ack_Data::total         5179                      
-system.ruby.L1Cache_Controller.OI.Writeback_Nack |          45     13.04%     13.04% |          49     14.20%     27.25% |          49     14.20%     41.45% |          49     14.20%     55.65% |          36     10.43%     66.09% |          44     12.75%     78.84% |          36     10.43%     89.28% |          37     10.72%    100.00%
-system.ruby.L1Cache_Controller.OI.Writeback_Nack::total          345                      
-system.ruby.L1Cache_Controller.MI.Load   |           1      1.14%      1.14% |           0      0.00%      1.14% |           0      0.00%      1.14% |          19     21.59%     22.73% |           4      4.55%     27.27% |          12     13.64%     40.91% |          37     42.05%     82.95% |          15     17.05%    100.00%
-system.ruby.L1Cache_Controller.MI.Load::total           88                      
-system.ruby.L1Cache_Controller.MI.Store  |           1      4.00%      4.00% |           0      0.00%      4.00% |           2      8.00%     12.00% |           9     36.00%     48.00% |           1      4.00%     52.00% |          12     48.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.L1Cache_Controller.MI.Store::total           25                      
-system.ruby.L1Cache_Controller.MI.Fwd_GETX |         337     12.57%     12.57% |         299     11.15%     23.72% |         297     11.08%     34.80% |         365     13.61%     48.41% |         329     12.27%     60.69% |         321     11.97%     72.66% |         347     12.94%     85.60% |         386     14.40%    100.00%
-system.ruby.L1Cache_Controller.MI.Fwd_GETX::total         2681                      
-system.ruby.L1Cache_Controller.MI.Fwd_GETS |         620     12.78%     12.78% |         652     13.44%     26.22% |         634     13.07%     39.28% |         628     12.94%     52.23% |         589     12.14%     64.37% |         598     12.32%     76.69% |         571     11.77%     88.46% |         560     11.54%    100.00%
-system.ruby.L1Cache_Controller.MI.Fwd_GETS::total         4852                      
-system.ruby.L1Cache_Controller.MI.Writeback_Ack_Data |       75471     12.47%     12.47% |       75902     12.54%     25.00% |       75324     12.44%     37.45% |       75567     12.48%     49.93% |       75666     12.50%     62.43% |       75761     12.51%     74.94% |       75947     12.54%     87.49% |       75760     12.51%    100.00%
-system.ruby.L1Cache_Controller.MI.Writeback_Ack_Data::total       605398                      
-system.ruby.L1Cache_Controller.II.Writeback_Ack_Data |         338     12.57%     12.57% |         299     11.12%     23.70% |         298     11.09%     34.78% |         364     13.54%     48.33% |         330     12.28%     60.60% |         322     11.98%     72.58% |         350     13.02%     85.60% |         387     14.40%    100.00%
-system.ruby.L1Cache_Controller.II.Writeback_Ack_Data::total         2688                      
-system.ruby.L1Cache_Controller.II.Writeback_Nack |           7     41.18%     41.18% |           4     23.53%     64.71% |           0      0.00%     64.71% |           3     17.65%     82.35% |           1      5.88%     88.24% |           0      0.00%     88.24% |           1      5.88%     94.12% |           1      5.88%    100.00%
-system.ruby.L1Cache_Controller.II.Writeback_Nack::total           17                      
-system.ruby.L2Cache_Controller.L1_GETS         504389      0.00%      0.00%
-system.ruby.L2Cache_Controller.L1_GETX         272648      0.00%      0.00%
-system.ruby.L2Cache_Controller.L1_PUTO           1593      0.00%      0.00%
-system.ruby.L2Cache_Controller.L1_PUTX         699797      0.00%      0.00%
-system.ruby.L2Cache_Controller.L1_PUTS_only        21673      0.00%      0.00%
-system.ruby.L2Cache_Controller.L1_PUTS            495      0.00%      0.00%
-system.ruby.L2Cache_Controller.All_Acks        211934      0.00%      0.00%
-system.ruby.L2Cache_Controller.Data            212372      0.00%      0.00%
-system.ruby.L2Cache_Controller.Data_Exclusive       392755      0.00%      0.00%
-system.ruby.L2Cache_Controller.L1_WBCLEANDATA       393957      0.00%      0.00%
-system.ruby.L2Cache_Controller.L1_WBDIRTYDATA       217301      0.00%      0.00%
-system.ruby.L2Cache_Controller.Writeback_Ack       604645      0.00%      0.00%
-system.ruby.L2Cache_Controller.Unblock          13367      0.00%      0.00%
-system.ruby.L2Cache_Controller.Exclusive_Unblock       613777      0.00%      0.00%
-system.ruby.L2Cache_Controller.L2_Replacement       690149      0.00%      0.00%
-system.ruby.L2Cache_Controller.NP.L1_GETS       393211      0.00%      0.00%
-system.ruby.L2Cache_Controller.NP.L1_GETX       211938      0.00%      0.00%
-system.ruby.L2Cache_Controller.ILS.L1_GETS            8      0.00%      0.00%
-system.ruby.L2Cache_Controller.ILS.L1_GETX            1      0.00%      0.00%
-system.ruby.L2Cache_Controller.ILS.L1_PUTS_only          666      0.00%      0.00%
-system.ruby.L2Cache_Controller.ILS.L1_PUTS           16      0.00%      0.00%
-system.ruby.L2Cache_Controller.ILX.L1_GETS         5402      0.00%      0.00%
-system.ruby.L2Cache_Controller.ILX.L1_GETX         2972      0.00%      0.00%
-system.ruby.L2Cache_Controller.ILX.L1_PUTO            2      0.00%      0.00%
-system.ruby.L2Cache_Controller.ILX.L1_PUTX       608084      0.00%      0.00%
-system.ruby.L2Cache_Controller.ILX.L1_PUTS           12      0.00%      0.00%
+system.ruby.ST.miss_latency_hist::samples       225093                      
+system.ruby.ST.miss_latency_hist::mean    1547.880667                      
+system.ruby.ST.miss_latency_hist::gmean   1033.273530                      
+system.ruby.ST.miss_latency_hist::stdev   1543.987848                      
+system.ruby.ST.miss_latency_hist         |      169736     75.41%     75.41% |       38573     17.14%     92.54% |       11917      5.29%     97.84% |        3626      1.61%     99.45% |         964      0.43%     99.88% |         219      0.10%     99.97% |          41      0.02%     99.99% |          15      0.01%    100.00% |           2      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.miss_latency_hist::total        225093                      
+system.ruby.L1Cache_Controller.Load      |       50872     12.50%     12.50% |       50771     12.47%     24.97% |       50915     12.51%     37.48% |       50811     12.48%     49.96% |       51089     12.55%     62.51% |       50942     12.51%     75.02% |       50938     12.51%     87.53% |       50752     12.47%    100.00%
+system.ruby.L1Cache_Controller.Load::total       407090                      
+system.ruby.L1Cache_Controller.Store     |       28229     12.54%     12.54% |       28181     12.52%     25.05% |       28245     12.54%     37.60% |       27993     12.43%     50.03% |       28086     12.47%     62.50% |       28102     12.48%     74.98% |       28291     12.56%     87.54% |       28047     12.46%    100.00%
+system.ruby.L1Cache_Controller.Store::total       225174                      
+system.ruby.L1Cache_Controller.L1_Replacement |     9814873     12.50%     12.50% |     9819645     12.50%     25.00% |     9815706     12.50%     37.50% |     9824325     12.51%     50.01% |     9814920     12.50%     62.50% |     9818100     12.50%     75.00% |     9808821     12.49%     87.49% |     9823009     12.51%    100.00%
+system.ruby.L1Cache_Controller.L1_Replacement::total     78539399                      
+system.ruby.L1Cache_Controller.Fwd_GETX  |         372     11.56%     11.56% |         430     13.37%     24.93% |         403     12.53%     37.46% |         422     13.12%     50.58% |         400     12.43%     63.01% |         387     12.03%     75.04% |         436     13.55%     88.59% |         367     11.41%    100.00%
+system.ruby.L1Cache_Controller.Fwd_GETX::total         3217                      
+system.ruby.L1Cache_Controller.Fwd_GETS  |         784     13.34%     13.34% |         703     11.96%     25.30% |         761     12.95%     38.24% |         724     12.32%     50.56% |         723     12.30%     62.86% |         690     11.74%     74.60% |         733     12.47%     87.07% |         760     12.93%    100.00%
+system.ruby.L1Cache_Controller.Fwd_GETS::total         5878                      
+system.ruby.L1Cache_Controller.Inv       |           3     27.27%     27.27% |           1      9.09%     36.36% |           1      9.09%     45.45% |           2     18.18%     63.64% |           1      9.09%     72.73% |           1      9.09%     81.82% |           2     18.18%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache_Controller.Inv::total           11                      
+system.ruby.L1Cache_Controller.Ack       |         382     12.53%     12.53% |         368     12.07%     24.60% |         367     12.04%     36.63% |         396     12.99%     49.62% |         413     13.55%     63.17% |         390     12.79%     75.96% |         371     12.17%     88.13% |         362     11.87%    100.00%
+system.ruby.L1Cache_Controller.Ack::total         3049                      
+system.ruby.L1Cache_Controller.Data      |         694     12.16%     12.16% |         704     12.34%     24.50% |         697     12.21%     36.71% |         700     12.27%     48.97% |         718     12.58%     61.56% |         729     12.77%     74.33% |         707     12.39%     86.72% |         758     13.28%    100.00%
+system.ruby.L1Cache_Controller.Data::total         5707                      
+system.ruby.L1Cache_Controller.Exclusive_Data |       78379     12.52%     12.52% |       78233     12.49%     25.01% |       78415     12.52%     37.53% |       78062     12.46%     49.99% |       78404     12.52%     62.51% |       78265     12.50%     75.01% |       78500     12.53%     87.55% |       77996     12.45%    100.00%
+system.ruby.L1Cache_Controller.Exclusive_Data::total       626254                      
+system.ruby.L1Cache_Controller.Writeback_Ack |         625     12.30%     12.30% |         638     12.55%     24.85% |         619     12.18%     37.03% |         619     12.18%     49.20% |         632     12.43%     61.64% |         635     12.49%     74.13% |         642     12.63%     86.76% |         673     13.24%    100.00%
+system.ruby.L1Cache_Controller.Writeback_Ack::total         5083                      
+system.ruby.L1Cache_Controller.Writeback_Ack_Data |       78390     12.52%     12.52% |       78220     12.49%     25.00% |       78418     12.52%     37.53% |       78074     12.47%     49.99% |       78414     12.52%     62.51% |       78296     12.50%     75.01% |       78500     12.53%     87.55% |       78006     12.45%    100.00%
+system.ruby.L1Cache_Controller.Writeback_Ack_Data::total       626318                      
+system.ruby.L1Cache_Controller.Writeback_Nack |          46     12.85%     12.85% |          50     13.97%     26.82% |          51     14.25%     41.06% |          32      8.94%     50.00% |          53     14.80%     64.80% |          36     10.06%     74.86% |          51     14.25%     89.11% |          39     10.89%    100.00%
+system.ruby.L1Cache_Controller.Writeback_Nack::total          358                      
+system.ruby.L1Cache_Controller.All_acks  |       28217     12.54%     12.54% |       28176     12.52%     25.05% |       28229     12.54%     37.59% |       27981     12.43%     50.03% |       28079     12.47%     62.50% |       28094     12.48%     74.98% |       28283     12.57%     87.55% |       28034     12.45%    100.00%
+system.ruby.L1Cache_Controller.All_acks::total       225093                      
+system.ruby.L1Cache_Controller.Use_Timeout |       78379     12.52%     12.52% |       78232     12.49%     25.01% |       78413     12.52%     37.53% |       78061     12.46%     49.99% |       78404     12.52%     62.51% |       78263     12.50%     75.01% |       78499     12.53%     87.55% |       77996     12.45%    100.00%
+system.ruby.L1Cache_Controller.Use_Timeout::total       626247                      
+system.ruby.L1Cache_Controller.I.Load    |       50857     12.50%     12.50% |       50764     12.48%     24.98% |       50884     12.51%     37.48% |       50783     12.48%     49.96% |       51044     12.55%     62.51% |       50901     12.51%     75.02% |       50925     12.52%     87.53% |       50722     12.47%    100.00%
+system.ruby.L1Cache_Controller.I.Load::total       406880                      
+system.ruby.L1Cache_Controller.I.Store   |       28220     12.54%     12.54% |       28176     12.52%     25.05% |       28229     12.54%     37.59% |       27982     12.43%     50.02% |       28081     12.47%     62.50% |       28095     12.48%     74.98% |       28285     12.57%     87.55% |       28035     12.45%    100.00%
+system.ruby.L1Cache_Controller.I.Store::total       225103                      
+system.ruby.L1Cache_Controller.I.L1_Replacement |          56     10.51%     10.51% |          76     14.26%     24.77% |          71     13.32%     38.09% |          65     12.20%     50.28% |          72     13.51%     63.79% |          59     11.07%     74.86% |          61     11.44%     86.30% |          73     13.70%    100.00%
+system.ruby.L1Cache_Controller.I.L1_Replacement::total          533                      
+system.ruby.L1Cache_Controller.S.L1_Replacement |         693     12.15%     12.15% |         703     12.32%     24.47% |         696     12.20%     36.68% |         700     12.27%     48.95% |         718     12.59%     61.54% |         729     12.78%     74.32% |         707     12.39%     86.71% |         758     13.29%    100.00%
+system.ruby.L1Cache_Controller.S.L1_Replacement::total         5704                      
+system.ruby.L1Cache_Controller.S.Inv     |           1     33.33%     33.33% |           1     33.33%     66.67% |           1     33.33%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache_Controller.S.Inv::total            3                      
+system.ruby.L1Cache_Controller.O.L1_Replacement |          54     14.21%     14.21% |          48     12.63%     26.84% |          36      9.47%     36.32% |          47     12.37%     48.68% |          53     13.95%     62.63% |          49     12.89%     75.53% |          55     14.47%     90.00% |          38     10.00%    100.00%
+system.ruby.L1Cache_Controller.O.L1_Replacement::total          380                      
+system.ruby.L1Cache_Controller.O.Fwd_GETX |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           1    100.00%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache_Controller.O.Fwd_GETX::total            1                      
+system.ruby.L1Cache_Controller.M.Load    |           3     21.43%     21.43% |           1      7.14%     28.57% |           2     14.29%     42.86% |           3     21.43%     64.29% |           0      0.00%     64.29% |           1      7.14%     71.43% |           1      7.14%     78.57% |           3     21.43%    100.00%
+system.ruby.L1Cache_Controller.M.Load::total           14                      
+system.ruby.L1Cache_Controller.M.Store   |           0      0.00%      0.00% |           0      0.00%      0.00% |           2     22.22%     22.22% |           3     33.33%     55.56% |           0      0.00%     55.56% |           2     22.22%     77.78% |           0      0.00%     77.78% |           2     22.22%    100.00%
+system.ruby.L1Cache_Controller.M.Store::total            9                      
+system.ruby.L1Cache_Controller.M.L1_Replacement |       50081     12.50%     12.50% |       49976     12.48%     24.98% |       50119     12.51%     37.49% |       50002     12.48%     49.98% |       50246     12.54%     62.52% |       50092     12.51%     75.03% |       50133     12.52%     87.54% |       49901     12.46%    100.00%
+system.ruby.L1Cache_Controller.M.L1_Replacement::total       400550                      
+system.ruby.L1Cache_Controller.M.Fwd_GETX |          21     10.94%     10.94% |          31     16.15%     27.08% |          25     13.02%     40.10% |          25     13.02%     53.13% |          21     10.94%     64.06% |          25     13.02%     77.08% |          25     13.02%     90.10% |          19      9.90%    100.00%
+system.ruby.L1Cache_Controller.M.Fwd_GETX::total          192                      
+system.ruby.L1Cache_Controller.M.Fwd_GETS |          54     14.17%     14.17% |          48     12.60%     26.77% |          36      9.45%     36.22% |          47     12.34%     48.56% |          53     13.91%     62.47% |          49     12.86%     75.33% |          56     14.70%     90.03% |          38      9.97%    100.00%
+system.ruby.L1Cache_Controller.M.Fwd_GETS::total          381                      
+system.ruby.L1Cache_Controller.M_W.Load  |           8     14.81%     14.81% |           3      5.56%     20.37% |           9     16.67%     37.04% |           5      9.26%     46.30% |          10     18.52%     64.81% |          11     20.37%     85.19% |           3      5.56%     90.74% |           5      9.26%    100.00%
+system.ruby.L1Cache_Controller.M_W.Load::total           54                      
+system.ruby.L1Cache_Controller.M_W.Store |           6     26.09%     26.09% |           2      8.70%     34.78% |           2      8.70%     43.48% |           4     17.39%     60.87% |           4     17.39%     78.26% |           1      4.35%     82.61% |           3     13.04%     95.65% |           1      4.35%    100.00%
+system.ruby.L1Cache_Controller.M_W.Store::total           23                      
+system.ruby.L1Cache_Controller.M_W.L1_Replacement |      902830     12.52%     12.52% |      899421     12.48%     25.00% |      898295     12.46%     37.46% |      905887     12.57%     50.02% |      901263     12.50%     62.53% |      899087     12.47%     75.00% |      900514     12.49%     87.49% |      901987     12.51%    100.00%
+system.ruby.L1Cache_Controller.M_W.L1_Replacement::total      7209284                      
+system.ruby.L1Cache_Controller.M_W.Fwd_GETX |          14     11.76%     11.76% |          15     12.61%     24.37% |          15     12.61%     36.97% |          14     11.76%     48.74% |          14     11.76%     60.50% |          27     22.69%     83.19% |          14     11.76%     94.96% |           6      5.04%    100.00%
+system.ruby.L1Cache_Controller.M_W.Fwd_GETX::total          119                      
+system.ruby.L1Cache_Controller.M_W.Fwd_GETS |          32     13.45%     13.45% |          36     15.13%     28.57% |          23      9.66%     38.24% |          24     10.08%     48.32% |          36     15.13%     63.45% |          37     15.55%     78.99% |          24     10.08%     89.08% |          26     10.92%    100.00%
+system.ruby.L1Cache_Controller.M_W.Fwd_GETS::total          238                      
+system.ruby.L1Cache_Controller.M_W.Use_Timeout |       50156     12.50%     12.50% |       50055     12.48%     24.98% |       50183     12.51%     37.49% |       50077     12.48%     49.98% |       50321     12.54%     62.52% |       50168     12.51%     75.03% |       50214     12.52%     87.55% |       49961     12.45%    100.00%
+system.ruby.L1Cache_Controller.M_W.Use_Timeout::total       401135                      
+system.ruby.L1Cache_Controller.MM.Load   |           1      6.67%      6.67% |           1      6.67%     13.33% |           3     20.00%     33.33% |           2     13.33%     46.67% |           3     20.00%     66.67% |           3     20.00%     86.67% |           1      6.67%     93.33% |           1      6.67%    100.00%
+system.ruby.L1Cache_Controller.MM.Load::total           15                      
+system.ruby.L1Cache_Controller.MM.Store  |           1     25.00%     25.00% |           0      0.00%     25.00% |           0      0.00%     25.00% |           0      0.00%     25.00% |           0      0.00%     25.00% |           1     25.00%     50.00% |           1     25.00%     75.00% |           1     25.00%    100.00%
+system.ruby.L1Cache_Controller.MM.Store::total            4                      
+system.ruby.L1Cache_Controller.MM.L1_Replacement |       28189     12.54%     12.54% |       28133     12.52%     25.06% |       28187     12.54%     37.60% |       27946     12.43%     50.03% |       28032     12.47%     62.50% |       28063     12.48%     74.98% |       28250     12.57%     87.55% |       27983     12.45%    100.00%
+system.ruby.L1Cache_Controller.MM.L1_Replacement::total       224783                      
+system.ruby.L1Cache_Controller.MM.Fwd_GETX |          10      8.55%      8.55% |          14     11.97%     20.51% |          17     14.53%     35.04% |          18     15.38%     50.43% |          15     12.82%     63.25% |          13     11.11%     74.36% |          13     11.11%     85.47% |          17     14.53%    100.00%
+system.ruby.L1Cache_Controller.MM.Fwd_GETX::total          117                      
+system.ruby.L1Cache_Controller.MM.Fwd_GETS |          24     10.86%     10.86% |          30     13.57%     24.43% |          28     12.67%     37.10% |          23     10.41%     47.51% |          36     16.29%     63.80% |          21      9.50%     73.30% |          22      9.95%     83.26% |          37     16.74%    100.00%
+system.ruby.L1Cache_Controller.MM.Fwd_GETS::total          221                      
+system.ruby.L1Cache_Controller.MM_W.Load |           1      3.33%      3.33% |           0      0.00%      3.33% |           6     20.00%     23.33% |           3     10.00%     33.33% |           9     30.00%     63.33% |           6     20.00%     83.33% |           4     13.33%     96.67% |           1      3.33%    100.00%
+system.ruby.L1Cache_Controller.MM_W.Load::total           30                      
+system.ruby.L1Cache_Controller.MM_W.Store |           2     11.76%     11.76% |           2     11.76%     23.53% |           2     11.76%     35.29% |           4     23.53%     58.82% |           1      5.88%     64.71% |           2     11.76%     76.47% |           1      5.88%     82.35% |           3     17.65%    100.00%
+system.ruby.L1Cache_Controller.MM_W.Store::total           17                      
+system.ruby.L1Cache_Controller.MM_W.L1_Replacement |      518661     12.49%     12.49% |      521491     12.56%     25.06% |      520698     12.54%     37.60% |      514785     12.40%     50.00% |      518151     12.48%     62.48% |      520112     12.53%     75.01% |      520576     12.54%     87.55% |      516624     12.45%    100.00%
+system.ruby.L1Cache_Controller.MM_W.L1_Replacement::total      4151098                      
+system.ruby.L1Cache_Controller.MM_W.Fwd_GETX |           4      6.67%      6.67% |          11     18.33%     25.00% |          12     20.00%     45.00% |          10     16.67%     61.67% |           6     10.00%     71.67% |           6     10.00%     81.67% |           6     10.00%     91.67% |           5      8.33%    100.00%
+system.ruby.L1Cache_Controller.MM_W.Fwd_GETX::total           60                      
+system.ruby.L1Cache_Controller.MM_W.Fwd_GETS |          14     11.11%     11.11% |           9      7.14%     18.25% |          24     19.05%     37.30% |          19     15.08%     52.38% |           7      5.56%     57.94% |          13     10.32%     68.25% |          14     11.11%     79.37% |          26     20.63%    100.00%
+system.ruby.L1Cache_Controller.MM_W.Fwd_GETS::total          126                      
+system.ruby.L1Cache_Controller.MM_W.Use_Timeout |       28223     12.54%     12.54% |       28177     12.52%     25.05% |       28230     12.54%     37.59% |       27984     12.43%     50.03% |       28083     12.48%     62.50% |       28095     12.48%     74.98% |       28285     12.56%     87.55% |       28035     12.45%    100.00%
+system.ruby.L1Cache_Controller.MM_W.Use_Timeout::total       225112                      
+system.ruby.L1Cache_Controller.IM.L1_Replacement |     2966552     12.54%     12.54% |     2968528     12.55%     25.10% |     2951843     12.48%     37.58% |     2970169     12.56%     50.14% |     2931613     12.40%     62.54% |     2956351     12.50%     75.04% |     2958165     12.51%     87.55% |     2944845     12.45%    100.00%
+system.ruby.L1Cache_Controller.IM.L1_Replacement::total     23648066                      
+system.ruby.L1Cache_Controller.IM.Ack    |         380     12.62%     12.62% |         361     11.99%     24.61% |         364     12.09%     36.70% |         391     12.99%     49.68% |         409     13.58%     63.27% |         381     12.65%     75.92% |         365     12.12%     88.04% |         360     11.96%    100.00%
+system.ruby.L1Cache_Controller.IM.Ack::total         3011                      
+system.ruby.L1Cache_Controller.IM.Exclusive_Data |       28217     12.54%     12.54% |       28176     12.52%     25.05% |       28229     12.54%     37.59% |       27981     12.43%     50.03% |       28079     12.47%     62.50% |       28094     12.48%     74.98% |       28283     12.57%     87.55% |       28034     12.45%    100.00%
+system.ruby.L1Cache_Controller.IM.Exclusive_Data::total       225093                      
+system.ruby.L1Cache_Controller.OM.L1_Replacement |       16577     12.58%     12.58% |       16710     12.68%     25.26% |       16598     12.59%     37.85% |       16673     12.65%     50.50% |       16150     12.25%     62.75% |       16566     12.57%     75.32% |       16599     12.59%     87.92% |       15925     12.08%    100.00%
+system.ruby.L1Cache_Controller.OM.L1_Replacement::total       131798                      
+system.ruby.L1Cache_Controller.OM.Ack    |           2      5.26%      5.26% |           7     18.42%     23.68% |           3      7.89%     31.58% |           5     13.16%     44.74% |           4     10.53%     55.26% |           9     23.68%     78.95% |           6     15.79%     94.74% |           2      5.26%    100.00%
+system.ruby.L1Cache_Controller.OM.Ack::total           38                      
+system.ruby.L1Cache_Controller.OM.All_acks |       28217     12.54%     12.54% |       28176     12.52%     25.05% |       28229     12.54%     37.59% |       27981     12.43%     50.03% |       28079     12.47%     62.50% |       28094     12.48%     74.98% |       28283     12.57%     87.55% |       28034     12.45%    100.00%
+system.ruby.L1Cache_Controller.OM.All_acks::total       225093                      
+system.ruby.L1Cache_Controller.IS.L1_Replacement |     5331180     12.47%     12.47% |     5334559     12.47%     24.94% |     5349163     12.51%     37.45% |     5338051     12.48%     49.93% |     5368622     12.55%     62.48% |     5346992     12.50%     74.98% |     5333761     12.47%     87.46% |     5364875     12.54%    100.00%
+system.ruby.L1Cache_Controller.IS.L1_Replacement::total     42767203                      
+system.ruby.L1Cache_Controller.IS.Data   |         694     12.16%     12.16% |         704     12.34%     24.50% |         697     12.21%     36.71% |         700     12.27%     48.97% |         718     12.58%     61.56% |         729     12.77%     74.33% |         707     12.39%     86.72% |         758     13.28%    100.00%
+system.ruby.L1Cache_Controller.IS.Data::total         5707                      
+system.ruby.L1Cache_Controller.IS.Exclusive_Data |       50162     12.50%     12.50% |       50057     12.48%     24.98% |       50186     12.51%     37.49% |       50081     12.48%     49.98% |       50325     12.54%     62.52% |       50171     12.51%     75.03% |       50217     12.52%     87.55% |       49962     12.45%    100.00%
+system.ruby.L1Cache_Controller.IS.Exclusive_Data::total       401161                      
+system.ruby.L1Cache_Controller.SI.Load   |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           1    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache_Controller.SI.Load::total            1                      
+system.ruby.L1Cache_Controller.SI.Inv    |           2     25.00%     25.00% |           0      0.00%     25.00% |           0      0.00%     25.00% |           2     25.00%     50.00% |           1     12.50%     62.50% |           1     12.50%     75.00% |           2     25.00%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache_Controller.SI.Inv::total            8                      
+system.ruby.L1Cache_Controller.SI.Writeback_Ack |         625     12.30%     12.30% |         638     12.55%     24.85% |         619     12.18%     37.03% |         619     12.18%     49.20% |         632     12.43%     61.64% |         635     12.49%     74.13% |         642     12.63%     86.76% |         673     13.24%    100.00%
+system.ruby.L1Cache_Controller.SI.Writeback_Ack::total         5083                      
+system.ruby.L1Cache_Controller.SI.Writeback_Ack_Data |          66     10.77%     10.77% |          65     10.60%     21.37% |          77     12.56%     33.93% |          79     12.89%     46.82% |          85     13.87%     60.69% |          93     15.17%     75.86% |          63     10.28%     86.13% |          85     13.87%    100.00%
+system.ruby.L1Cache_Controller.SI.Writeback_Ack_Data::total          613                      
+system.ruby.L1Cache_Controller.OI.Fwd_GETX |           0      0.00%      0.00% |           0      0.00%      0.00% |           3     50.00%     50.00% |           0      0.00%     50.00% |           1     16.67%     66.67% |           0      0.00%     66.67% |           0      0.00%     66.67% |           2     33.33%    100.00%
+system.ruby.L1Cache_Controller.OI.Fwd_GETX::total            6                      
+system.ruby.L1Cache_Controller.OI.Fwd_GETS |           3     10.71%     10.71% |           2      7.14%     17.86% |           3     10.71%     28.57% |           5     17.86%     46.43% |           6     21.43%     67.86% |           3     10.71%     78.57% |           2      7.14%     85.71% |           4     14.29%    100.00%
+system.ruby.L1Cache_Controller.OI.Fwd_GETS::total           28                      
+system.ruby.L1Cache_Controller.OI.Writeback_Ack_Data |         711     13.52%     13.52% |         626     11.91%     25.43% |         680     12.93%     38.36% |         653     12.42%     50.78% |         637     12.11%     62.89% |         616     11.72%     74.61% |         670     12.74%     87.35% |         665     12.65%    100.00%
+system.ruby.L1Cache_Controller.OI.Writeback_Ack_Data::total         5258                      
+system.ruby.L1Cache_Controller.OI.Writeback_Nack |          44     12.79%     12.79% |          49     14.24%     27.03% |          50     14.53%     41.57% |          30      8.72%     50.29% |          50     14.53%     64.83% |          34      9.88%     74.71% |          49     14.24%     88.95% |          38     11.05%    100.00%
+system.ruby.L1Cache_Controller.OI.Writeback_Nack::total          344                      
+system.ruby.L1Cache_Controller.MI.Load   |           2      2.08%      2.08% |           2      2.08%      4.17% |          11     11.46%     15.62% |          15     15.62%     31.25% |          23     23.96%     55.21% |          19     19.79%     75.00% |           4      4.17%     79.17% |          20     20.83%    100.00%
+system.ruby.L1Cache_Controller.MI.Load::total           96                      
+system.ruby.L1Cache_Controller.MI.Store  |           0      0.00%      0.00% |           1      5.56%      5.56% |          10     55.56%     61.11% |           0      0.00%     61.11% |           0      0.00%     61.11% |           1      5.56%     66.67% |           1      5.56%     72.22% |           5     27.78%    100.00%
+system.ruby.L1Cache_Controller.MI.Store::total           18                      
+system.ruby.L1Cache_Controller.MI.Fwd_GETX |         323     11.87%     11.87% |         359     13.19%     25.06% |         331     12.16%     37.22% |         355     13.04%     50.26% |         343     12.60%     62.86% |         316     11.61%     74.47% |         377     13.85%     88.32% |         318     11.68%    100.00%
+system.ruby.L1Cache_Controller.MI.Fwd_GETX::total         2722                      
+system.ruby.L1Cache_Controller.MI.Fwd_GETS |         657     13.45%     13.45% |         578     11.83%     25.29% |         647     13.25%     38.53% |         606     12.41%     50.94% |         585     11.98%     62.92% |         567     11.61%     74.53% |         615     12.59%     87.12% |         629     12.88%    100.00%
+system.ruby.L1Cache_Controller.MI.Fwd_GETS::total         4884                      
+system.ruby.L1Cache_Controller.MI.Writeback_Ack_Data |       77290     12.51%     12.51% |       77171     12.49%     25.00% |       77328     12.52%     37.52% |       76987     12.46%     49.99% |       77350     12.52%     62.51% |       77272     12.51%     75.02% |       77390     12.53%     87.55% |       76937     12.45%    100.00%
+system.ruby.L1Cache_Controller.MI.Writeback_Ack_Data::total       617725                      
+system.ruby.L1Cache_Controller.II.Writeback_Ack_Data |         323     11.87%     11.87% |         358     13.15%     25.02% |         333     12.23%     37.25% |         355     13.04%     50.29% |         342     12.56%     62.86% |         315     11.57%     74.43% |         377     13.85%     88.28% |         319     11.72%    100.00%
+system.ruby.L1Cache_Controller.II.Writeback_Ack_Data::total         2722                      
+system.ruby.L1Cache_Controller.II.Writeback_Nack |           2     14.29%     14.29% |           1      7.14%     21.43% |           1      7.14%     28.57% |           2     14.29%     42.86% |           3     21.43%     64.29% |           2     14.29%     78.57% |           2     14.29%     92.86% |           1      7.14%    100.00%
+system.ruby.L1Cache_Controller.II.Writeback_Nack::total           14                      
+system.ruby.L2Cache_Controller.L1_GETS         510526      0.00%      0.00%
+system.ruby.L2Cache_Controller.L1_GETX         279973      0.00%      0.00%
+system.ruby.L2Cache_Controller.L1_PUTO           1729      0.00%      0.00%
+system.ruby.L2Cache_Controller.L1_PUTX         714197      0.00%      0.00%
+system.ruby.L2Cache_Controller.L1_PUTS_only        22269      0.00%      0.00%
+system.ruby.L2Cache_Controller.L1_PUTS            380      0.00%      0.00%
+system.ruby.L2Cache_Controller.All_Acks        219823      0.00%      0.00%
+system.ruby.L2Cache_Controller.Data            220223      0.00%      0.00%
+system.ruby.L2Cache_Controller.Data_Exclusive       397040      0.00%      0.00%
+system.ruby.L2Cache_Controller.L1_WBCLEANDATA       398133      0.00%      0.00%
+system.ruby.L2Cache_Controller.L1_WBDIRTYDATA       225463      0.00%      0.00%
+system.ruby.L2Cache_Controller.Writeback_Ack       616817      0.00%      0.00%
+system.ruby.L2Cache_Controller.Unblock          13512      0.00%      0.00%
+system.ruby.L2Cache_Controller.Exclusive_Unblock       626247      0.00%      0.00%
+system.ruby.L2Cache_Controller.L2_Replacement       705892      0.00%      0.00%
+system.ruby.L2Cache_Controller.NP.L1_GETS       397447      0.00%      0.00%
+system.ruby.L2Cache_Controller.NP.L1_GETX       219833      0.00%      0.00%
+system.ruby.L2Cache_Controller.ILS.L1_PUTS_only          612      0.00%      0.00%
+system.ruby.L2Cache_Controller.ILS.L1_PUTS            1      0.00%      0.00%
+system.ruby.L2Cache_Controller.ILX.L1_GETS         5486      0.00%      0.00%
+system.ruby.L2Cache_Controller.ILX.L1_GETX         3031      0.00%      0.00%
+system.ruby.L2Cache_Controller.ILX.L1_PUTO            1      0.00%      0.00%
+system.ruby.L2Cache_Controller.ILX.L1_PUTX       620443      0.00%      0.00%
+system.ruby.L2Cache_Controller.ILX.L1_PUTS            8      0.00%      0.00%
 system.ruby.L2Cache_Controller.ILOX.L1_GETS            4      0.00%      0.00%
-system.ruby.L2Cache_Controller.ILOX.L1_GETX            2      0.00%      0.00%
-system.ruby.L2Cache_Controller.ILOX.L1_PUTO          498      0.00%      0.00%
+system.ruby.L2Cache_Controller.ILOX.L1_GETX            3      0.00%      0.00%
+system.ruby.L2Cache_Controller.ILOX.L1_PUTO          511      0.00%      0.00%
 system.ruby.L2Cache_Controller.ILOX.L1_PUTX          345      0.00%      0.00%
-system.ruby.L2Cache_Controller.ILOSX.L1_GETS           22      0.00%      0.00%
-system.ruby.L2Cache_Controller.ILOSX.L1_GETX           11      0.00%      0.00%
-system.ruby.L2Cache_Controller.ILOSX.L1_PUTO          184      0.00%      0.00%
-system.ruby.L2Cache_Controller.ILOSX.L1_PUTX         4499      0.00%      0.00%
-system.ruby.L2Cache_Controller.ILOSX.L1_PUTS_only          504      0.00%      0.00%
-system.ruby.L2Cache_Controller.ILOSX.L1_PUTS           11      0.00%      0.00%
-system.ruby.L2Cache_Controller.S.L1_GETS            6      0.00%      0.00%
-system.ruby.L2Cache_Controller.S.L1_GETX            1      0.00%      0.00%
-system.ruby.L2Cache_Controller.S.L2_Replacement          675      0.00%      0.00%
-system.ruby.L2Cache_Controller.OLSX.L1_GETS           20      0.00%      0.00%
+system.ruby.L2Cache_Controller.ILOSX.L1_GETS           24      0.00%      0.00%
+system.ruby.L2Cache_Controller.ILOSX.L1_GETX            4      0.00%      0.00%
+system.ruby.L2Cache_Controller.ILOSX.L1_PUTO          212      0.00%      0.00%
+system.ruby.L2Cache_Controller.ILOSX.L1_PUTX         4539      0.00%      0.00%
+system.ruby.L2Cache_Controller.ILOSX.L1_PUTS_only          518      0.00%      0.00%
+system.ruby.L2Cache_Controller.ILOSX.L1_PUTS            6      0.00%      0.00%
+system.ruby.L2Cache_Controller.S.L1_GETS            2      0.00%      0.00%
+system.ruby.L2Cache_Controller.S.L2_Replacement          611      0.00%      0.00%
+system.ruby.L2Cache_Controller.OLSX.L1_GETS           13      0.00%      0.00%
 system.ruby.L2Cache_Controller.OLSX.L1_GETX            7      0.00%      0.00%
-system.ruby.L2Cache_Controller.OLSX.L1_PUTS_only         4435      0.00%      0.00%
-system.ruby.L2Cache_Controller.OLSX.L1_PUTS           23      0.00%      0.00%
-system.ruby.L2Cache_Controller.OLSX.L2_Replacement          239      0.00%      0.00%
-system.ruby.L2Cache_Controller.SLS.L1_PUTS_only           16      0.00%      0.00%
-system.ruby.L2Cache_Controller.SLS.L2_Replacement            6      0.00%      0.00%
-system.ruby.L2Cache_Controller.M.L1_GETS         3814      0.00%      0.00%
-system.ruby.L2Cache_Controller.M.L1_GETX         2075      0.00%      0.00%
+system.ruby.L2Cache_Controller.OLSX.L1_PUTX            1      0.00%      0.00%
+system.ruby.L2Cache_Controller.OLSX.L1_PUTS_only         4528      0.00%      0.00%
+system.ruby.L2Cache_Controller.OLSX.L1_PUTS           30      0.00%      0.00%
+system.ruby.L2Cache_Controller.OLSX.L2_Replacement          212      0.00%      0.00%
+system.ruby.L2Cache_Controller.SLS.L1_PUTS_only            1      0.00%      0.00%
+system.ruby.L2Cache_Controller.SLS.L2_Replacement            2      0.00%      0.00%
+system.ruby.L2Cache_Controller.M.L1_GETS         3902      0.00%      0.00%
+system.ruby.L2Cache_Controller.M.L1_GETX         2225      0.00%      0.00%
 system.ruby.L2Cache_Controller.M.L1_PUTX            3      0.00%      0.00%
-system.ruby.L2Cache_Controller.M.L2_Replacement       604433      0.00%      0.00%
-system.ruby.L2Cache_Controller.ILOXW.L1_GETS           53      0.00%      0.00%
-system.ruby.L2Cache_Controller.ILOXW.L1_GETX           42      0.00%      0.00%
-system.ruby.L2Cache_Controller.ILOXW.L1_PUTO          826      0.00%      0.00%
-system.ruby.L2Cache_Controller.ILOXW.L1_PUTX         4960      0.00%      0.00%
-system.ruby.L2Cache_Controller.ILOXW.L1_WBCLEANDATA          389      0.00%      0.00%
-system.ruby.L2Cache_Controller.ILOXW.L1_WBDIRTYDATA          109      0.00%      0.00%
-system.ruby.L2Cache_Controller.ILOXW.Unblock          504      0.00%      0.00%
-system.ruby.L2Cache_Controller.ILOSXW.L1_GETS          138      0.00%      0.00%
-system.ruby.L2Cache_Controller.ILOSXW.L1_GETX           87      0.00%      0.00%
-system.ruby.L2Cache_Controller.ILOSXW.L1_PUTO            8      0.00%      0.00%
-system.ruby.L2Cache_Controller.ILOSXW.L1_PUTX           63      0.00%      0.00%
-system.ruby.L2Cache_Controller.ILOSXW.L1_PUTS_only        14625      0.00%      0.00%
-system.ruby.L2Cache_Controller.ILOSXW.L1_PUTS           56      0.00%      0.00%
-system.ruby.L2Cache_Controller.ILOSXW.L1_WBCLEANDATA         3112      0.00%      0.00%
-system.ruby.L2Cache_Controller.ILOSXW.L1_WBDIRTYDATA         1569      0.00%      0.00%
-system.ruby.L2Cache_Controller.ILOSXW.Unblock           13      0.00%      0.00%
-system.ruby.L2Cache_Controller.ILSW.L1_PUTS           78      0.00%      0.00%
-system.ruby.L2Cache_Controller.ILSW.L1_WBCLEANDATA           16      0.00%      0.00%
-system.ruby.L2Cache_Controller.IW.L1_GETS           53      0.00%      0.00%
-system.ruby.L2Cache_Controller.IW.L1_GETX           14      0.00%      0.00%
-system.ruby.L2Cache_Controller.IW.L1_WBCLEANDATA          666      0.00%      0.00%
-system.ruby.L2Cache_Controller.SW.Unblock           16      0.00%      0.00%
-system.ruby.L2Cache_Controller.SW.L2_Replacement          297      0.00%      0.00%
-system.ruby.L2Cache_Controller.OXW.L1_GETS          163      0.00%      0.00%
-system.ruby.L2Cache_Controller.OXW.L1_GETX           69      0.00%      0.00%
-system.ruby.L2Cache_Controller.OXW.Unblock         4435      0.00%      0.00%
-system.ruby.L2Cache_Controller.OXW.L2_Replacement        33711      0.00%      0.00%
-system.ruby.L2Cache_Controller.OLSXW.L1_PUTS          119      0.00%      0.00%
-system.ruby.L2Cache_Controller.OLSXW.Unblock           23      0.00%      0.00%
-system.ruby.L2Cache_Controller.OLSXW.L2_Replacement          225      0.00%      0.00%
-system.ruby.L2Cache_Controller.ILXW.L1_GETS        23787      0.00%      0.00%
-system.ruby.L2Cache_Controller.ILXW.L1_GETX        12537      0.00%      0.00%
-system.ruby.L2Cache_Controller.ILXW.L1_PUTX         5410      0.00%      0.00%
-system.ruby.L2Cache_Controller.ILXW.L1_PUTS           21      0.00%      0.00%
-system.ruby.L2Cache_Controller.ILXW.L1_WBCLEANDATA       389774      0.00%      0.00%
-system.ruby.L2Cache_Controller.ILXW.L1_WBDIRTYDATA       215623      0.00%      0.00%
-system.ruby.L2Cache_Controller.ILXW.Unblock         2686      0.00%      0.00%
-system.ruby.L2Cache_Controller.IFLS.L1_PUTS_only           50      0.00%      0.00%
-system.ruby.L2Cache_Controller.IFLS.Unblock            8      0.00%      0.00%
-system.ruby.L2Cache_Controller.IFLOX.L1_PUTX           15      0.00%      0.00%
-system.ruby.L2Cache_Controller.IFLOX.L1_PUTS_only           35      0.00%      0.00%
+system.ruby.L2Cache_Controller.M.L2_Replacement       616629      0.00%      0.00%
+system.ruby.L2Cache_Controller.ILOXW.L1_GETS           86      0.00%      0.00%
+system.ruby.L2Cache_Controller.ILOXW.L1_GETX           44      0.00%      0.00%
+system.ruby.L2Cache_Controller.ILOXW.L1_PUTO          929      0.00%      0.00%
+system.ruby.L2Cache_Controller.ILOXW.L1_PUTX         5022      0.00%      0.00%
+system.ruby.L2Cache_Controller.ILOXW.L1_WBCLEANDATA          377      0.00%      0.00%
+system.ruby.L2Cache_Controller.ILOXW.L1_WBDIRTYDATA          134      0.00%      0.00%
+system.ruby.L2Cache_Controller.ILOXW.Unblock          518      0.00%      0.00%
+system.ruby.L2Cache_Controller.ILOSXW.L1_GETS           84      0.00%      0.00%
+system.ruby.L2Cache_Controller.ILOSXW.L1_GETX           73      0.00%      0.00%
+system.ruby.L2Cache_Controller.ILOSXW.L1_PUTX           83      0.00%      0.00%
+system.ruby.L2Cache_Controller.ILOSXW.L1_PUTS_only        15289      0.00%      0.00%
+system.ruby.L2Cache_Controller.ILOSXW.L1_PUTS           91      0.00%      0.00%
+system.ruby.L2Cache_Controller.ILOSXW.L1_WBCLEANDATA         3142      0.00%      0.00%
+system.ruby.L2Cache_Controller.ILOSXW.L1_WBDIRTYDATA         1605      0.00%      0.00%
+system.ruby.L2Cache_Controller.ILOSXW.Unblock           10      0.00%      0.00%
+system.ruby.L2Cache_Controller.ILSW.L1_PUTS            9      0.00%      0.00%
+system.ruby.L2Cache_Controller.ILSW.L1_WBCLEANDATA            1      0.00%      0.00%
+system.ruby.L2Cache_Controller.IW.L1_GETS           11      0.00%      0.00%
+system.ruby.L2Cache_Controller.IW.L1_WBCLEANDATA          612      0.00%      0.00%
+system.ruby.L2Cache_Controller.SW.Unblock            1      0.00%      0.00%
+system.ruby.L2Cache_Controller.SW.L2_Replacement           25      0.00%      0.00%
+system.ruby.L2Cache_Controller.OXW.L1_GETS          121      0.00%      0.00%
+system.ruby.L2Cache_Controller.OXW.L1_GETX           86      0.00%      0.00%
+system.ruby.L2Cache_Controller.OXW.Unblock         4528      0.00%      0.00%
+system.ruby.L2Cache_Controller.OXW.L2_Replacement        34549      0.00%      0.00%
+system.ruby.L2Cache_Controller.OLSXW.L1_PUTS          165      0.00%      0.00%
+system.ruby.L2Cache_Controller.OLSXW.Unblock           30      0.00%      0.00%
+system.ruby.L2Cache_Controller.OLSXW.L2_Replacement          246      0.00%      0.00%
+system.ruby.L2Cache_Controller.ILXW.L1_GETS        24257      0.00%      0.00%
+system.ruby.L2Cache_Controller.ILXW.L1_GETX        13813      0.00%      0.00%
+system.ruby.L2Cache_Controller.ILXW.L1_PUTX         5282      0.00%      0.00%
+system.ruby.L2Cache_Controller.ILXW.L1_PUTS           17      0.00%      0.00%
+system.ruby.L2Cache_Controller.ILXW.L1_WBCLEANDATA       394001      0.00%      0.00%
+system.ruby.L2Cache_Controller.ILXW.L1_WBDIRTYDATA       223724      0.00%      0.00%
+system.ruby.L2Cache_Controller.ILXW.Unblock         2718      0.00%      0.00%
+system.ruby.L2Cache_Controller.IFLOX.L1_PUTO            5      0.00%      0.00%
+system.ruby.L2Cache_Controller.IFLOX.L1_PUTX            7      0.00%      0.00%
+system.ruby.L2Cache_Controller.IFLOX.L1_PUTS_only           45      0.00%      0.00%
 system.ruby.L2Cache_Controller.IFLOX.Unblock            4      0.00%      0.00%
 system.ruby.L2Cache_Controller.IFLOX.Exclusive_Unblock            7      0.00%      0.00%
-system.ruby.L2Cache_Controller.IFLOXX.L1_GETS          550      0.00%      0.00%
-system.ruby.L2Cache_Controller.IFLOXX.L1_GETX          221      0.00%      0.00%
-system.ruby.L2Cache_Controller.IFLOXX.L1_PUTO           75      0.00%      0.00%
-system.ruby.L2Cache_Controller.IFLOXX.L1_PUTX        75456      0.00%      0.00%
-system.ruby.L2Cache_Controller.IFLOXX.L1_PUTS           40      0.00%      0.00%
-system.ruby.L2Cache_Controller.IFLOXX.Unblock         5192      0.00%      0.00%
-system.ruby.L2Cache_Controller.IFLOXX.Exclusive_Unblock         3184      0.00%      0.00%
-system.ruby.L2Cache_Controller.IFLOSX.L1_PUTX          175      0.00%      0.00%
-system.ruby.L2Cache_Controller.IFLOSX.L1_PUTS_only          115      0.00%      0.00%
-system.ruby.L2Cache_Controller.IFLOSX.Unblock           22      0.00%      0.00%
-system.ruby.L2Cache_Controller.IFLXO.L1_PUTX          134      0.00%      0.00%
-system.ruby.L2Cache_Controller.IFLXO.L1_PUTS_only           81      0.00%      0.00%
-system.ruby.L2Cache_Controller.IFLXO.Exclusive_Unblock           11      0.00%      0.00%
-system.ruby.L2Cache_Controller.IGS.L1_GETS        49660      0.00%      0.00%
-system.ruby.L2Cache_Controller.IGS.L1_GETX        26581      0.00%      0.00%
-system.ruby.L2Cache_Controller.IGS.L1_PUTX          426      0.00%      0.00%
-system.ruby.L2Cache_Controller.IGS.L1_PUTS           11      0.00%      0.00%
-system.ruby.L2Cache_Controller.IGS.Data           438      0.00%      0.00%
-system.ruby.L2Cache_Controller.IGS.Data_Exclusive       392755      0.00%      0.00%
-system.ruby.L2Cache_Controller.IGS.Unblock          438      0.00%      0.00%
-system.ruby.L2Cache_Controller.IGS.Exclusive_Unblock       392753      0.00%      0.00%
-system.ruby.L2Cache_Controller.IGM.L1_GETS        19915      0.00%      0.00%
-system.ruby.L2Cache_Controller.IGM.L1_GETX        11908      0.00%      0.00%
-system.ruby.L2Cache_Controller.IGM.Data        211933      0.00%      0.00%
-system.ruby.L2Cache_Controller.IGMLS.L1_PUTS_only           23      0.00%      0.00%
-system.ruby.L2Cache_Controller.IGMLS.Data            1      0.00%      0.00%
-system.ruby.L2Cache_Controller.IGMO.L1_GETS         4990      0.00%      0.00%
-system.ruby.L2Cache_Controller.IGMO.L1_GETX         3032      0.00%      0.00%
-system.ruby.L2Cache_Controller.IGMO.L1_PUTX          215      0.00%      0.00%
-system.ruby.L2Cache_Controller.IGMO.L1_PUTS_only            5      0.00%      0.00%
-system.ruby.L2Cache_Controller.IGMO.All_Acks       211934      0.00%      0.00%
-system.ruby.L2Cache_Controller.IGMO.Exclusive_Unblock       211933      0.00%      0.00%
-system.ruby.L2Cache_Controller.MM.L1_GETS           41      0.00%      0.00%
-system.ruby.L2Cache_Controller.MM.L1_GETX           46      0.00%      0.00%
-system.ruby.L2Cache_Controller.MM.L1_PUTX            5      0.00%      0.00%
-system.ruby.L2Cache_Controller.MM.Exclusive_Unblock         2075      0.00%      0.00%
-system.ruby.L2Cache_Controller.SS.Unblock            6      0.00%      0.00%
-system.ruby.L2Cache_Controller.SS.L2_Replacement          127      0.00%      0.00%
-system.ruby.L2Cache_Controller.OO.L1_GETS          101      0.00%      0.00%
-system.ruby.L2Cache_Controller.OO.L1_GETX           49      0.00%      0.00%
-system.ruby.L2Cache_Controller.OO.L1_PUTX            7      0.00%      0.00%
-system.ruby.L2Cache_Controller.OO.Exclusive_Unblock         3814      0.00%      0.00%
-system.ruby.L2Cache_Controller.OO.L2_Replacement        50262      0.00%      0.00%
-system.ruby.L2Cache_Controller.OLSXS.L1_PUTS_only          107      0.00%      0.00%
-system.ruby.L2Cache_Controller.OLSXS.Unblock           20      0.00%      0.00%
-system.ruby.L2Cache_Controller.OLSXS.L2_Replacement          174      0.00%      0.00%
-system.ruby.L2Cache_Controller.MI.L1_GETS         2451      0.00%      0.00%
-system.ruby.L2Cache_Controller.MI.L1_GETX         1055      0.00%      0.00%
-system.ruby.L2Cache_Controller.MI.Writeback_Ack       604406      0.00%      0.00%
-system.ruby.L2Cache_Controller.OLSI.L1_PUTS_only         1011      0.00%      0.00%
-system.ruby.L2Cache_Controller.OLSI.L1_PUTS          108      0.00%      0.00%
-system.ruby.L2Cache_Controller.OLSI.Writeback_Ack          239      0.00%      0.00%
-system.ruby.Directory_Controller.GETX          211949      0.00%      0.00%
-system.ruby.Directory_Controller.GETS          393220      0.00%      0.00%
-system.ruby.Directory_Controller.PUTX          604433      0.00%      0.00%
-system.ruby.Directory_Controller.PUTO_SHARERS          239      0.00%      0.00%
-system.ruby.Directory_Controller.Last_Unblock          438      0.00%      0.00%
-system.ruby.Directory_Controller.Exclusive_Unblock       604686      0.00%      0.00%
-system.ruby.Directory_Controller.Clean_Writeback       389402      0.00%      0.00%
-system.ruby.Directory_Controller.Dirty_Writeback       215243      0.00%      0.00%
-system.ruby.Directory_Controller.Memory_Data       605138      0.00%      0.00%
-system.ruby.Directory_Controller.Memory_Ack       215243      0.00%      0.00%
-system.ruby.Directory_Controller.I.GETX        211704      0.00%      0.00%
-system.ruby.Directory_Controller.I.GETS        392773      0.00%      0.00%
-system.ruby.Directory_Controller.I.Memory_Ack       213458      0.00%      0.00%
-system.ruby.Directory_Controller.S.GETX           236      0.00%      0.00%
-system.ruby.Directory_Controller.S.GETS           438      0.00%      0.00%
-system.ruby.Directory_Controller.S.Memory_Ack           82      0.00%      0.00%
-system.ruby.Directory_Controller.M.PUTX        604433      0.00%      0.00%
-system.ruby.Directory_Controller.M.PUTO_SHARERS          239      0.00%      0.00%
-system.ruby.Directory_Controller.IS.Exclusive_Unblock       392753      0.00%      0.00%
-system.ruby.Directory_Controller.IS.Memory_Data       392763      0.00%      0.00%
-system.ruby.Directory_Controller.IS.Memory_Ack         1125      0.00%      0.00%
-system.ruby.Directory_Controller.SS.Last_Unblock          438      0.00%      0.00%
-system.ruby.Directory_Controller.SS.Memory_Data          438      0.00%      0.00%
-system.ruby.Directory_Controller.MM.Exclusive_Unblock       211933      0.00%      0.00%
-system.ruby.Directory_Controller.MM.Memory_Data       211937      0.00%      0.00%
-system.ruby.Directory_Controller.MM.Memory_Ack          578      0.00%      0.00%
-system.ruby.Directory_Controller.MI.GETX            9      0.00%      0.00%
-system.ruby.Directory_Controller.MI.GETS            9      0.00%      0.00%
-system.ruby.Directory_Controller.MI.Clean_Writeback       389245      0.00%      0.00%
-system.ruby.Directory_Controller.MI.Dirty_Writeback       215161      0.00%      0.00%
-system.ruby.Directory_Controller.MIS.Clean_Writeback          157      0.00%      0.00%
-system.ruby.Directory_Controller.MIS.Dirty_Writeback           82      0.00%      0.00%
+system.ruby.L2Cache_Controller.IFLOXX.L1_GETS          513      0.00%      0.00%
+system.ruby.L2Cache_Controller.IFLOXX.L1_GETX          128      0.00%      0.00%
+system.ruby.L2Cache_Controller.IFLOXX.L1_PUTO           71      0.00%      0.00%
+system.ruby.L2Cache_Controller.IFLOXX.L1_PUTX        77511      0.00%      0.00%
+system.ruby.L2Cache_Controller.IFLOXX.L1_PUTS           34      0.00%      0.00%
+system.ruby.L2Cache_Controller.IFLOXX.Unblock         5265      0.00%      0.00%
+system.ruby.L2Cache_Controller.IFLOXX.Exclusive_Unblock         3255      0.00%      0.00%
+system.ruby.L2Cache_Controller.IFLOSX.L1_PUTX          264      0.00%      0.00%
+system.ruby.L2Cache_Controller.IFLOSX.L1_PUTS_only          138      0.00%      0.00%
+system.ruby.L2Cache_Controller.IFLOSX.Unblock           24      0.00%      0.00%
+system.ruby.L2Cache_Controller.IFLXO.L1_PUTX           50      0.00%      0.00%
+system.ruby.L2Cache_Controller.IFLXO.L1_PUTS_only           29      0.00%      0.00%
+system.ruby.L2Cache_Controller.IFLXO.Exclusive_Unblock            4      0.00%      0.00%
+system.ruby.L2Cache_Controller.IGS.L1_GETS        48444      0.00%      0.00%
+system.ruby.L2Cache_Controller.IGS.L1_GETX        25465      0.00%      0.00%
+system.ruby.L2Cache_Controller.IGS.L1_PUTX          427      0.00%      0.00%
+system.ruby.L2Cache_Controller.IGS.L1_PUTS            4      0.00%      0.00%
+system.ruby.L2Cache_Controller.IGS.Data           399      0.00%      0.00%
+system.ruby.L2Cache_Controller.IGS.Data_Exclusive       397040      0.00%      0.00%
+system.ruby.L2Cache_Controller.IGS.Unblock          399      0.00%      0.00%
+system.ruby.L2Cache_Controller.IGS.Exclusive_Unblock       397035      0.00%      0.00%
+system.ruby.L2Cache_Controller.IGM.L1_GETS        21845      0.00%      0.00%
+system.ruby.L2Cache_Controller.IGM.L1_GETX        11064      0.00%      0.00%
+system.ruby.L2Cache_Controller.IGM.Data        219824      0.00%      0.00%
+system.ruby.L2Cache_Controller.IGMO.L1_GETS         5622      0.00%      0.00%
+system.ruby.L2Cache_Controller.IGMO.L1_GETX         2829      0.00%      0.00%
+system.ruby.L2Cache_Controller.IGMO.L1_PUTX          209      0.00%      0.00%
+system.ruby.L2Cache_Controller.IGMO.All_Acks       219823      0.00%      0.00%
+system.ruby.L2Cache_Controller.IGMO.Exclusive_Unblock       219819      0.00%      0.00%
+system.ruby.L2Cache_Controller.MM.L1_GETS           61      0.00%      0.00%
+system.ruby.L2Cache_Controller.MM.L1_GETX           48      0.00%      0.00%
+system.ruby.L2Cache_Controller.MM.L1_PUTX            3      0.00%      0.00%
+system.ruby.L2Cache_Controller.MM.Exclusive_Unblock         2225      0.00%      0.00%
+system.ruby.L2Cache_Controller.SS.Unblock            2      0.00%      0.00%
+system.ruby.L2Cache_Controller.SS.L2_Replacement           21      0.00%      0.00%
+system.ruby.L2Cache_Controller.OO.L1_GETS          100      0.00%      0.00%
+system.ruby.L2Cache_Controller.OO.L1_GETX           62      0.00%      0.00%
+system.ruby.L2Cache_Controller.OO.L1_PUTX            8      0.00%      0.00%
+system.ruby.L2Cache_Controller.OO.Exclusive_Unblock         3902      0.00%      0.00%
+system.ruby.L2Cache_Controller.OO.L2_Replacement        53526      0.00%      0.00%
+system.ruby.L2Cache_Controller.OLSXS.L1_PUTS_only           50      0.00%      0.00%
+system.ruby.L2Cache_Controller.OLSXS.Unblock           13      0.00%      0.00%
+system.ruby.L2Cache_Controller.OLSXS.L2_Replacement           71      0.00%      0.00%
+system.ruby.L2Cache_Controller.MI.L1_GETS         2504      0.00%      0.00%
+system.ruby.L2Cache_Controller.MI.L1_GETX         1258      0.00%      0.00%
+system.ruby.L2Cache_Controller.MI.Writeback_Ack       616605      0.00%      0.00%
+system.ruby.L2Cache_Controller.OLSI.L1_PUTS_only         1059      0.00%      0.00%
+system.ruby.L2Cache_Controller.OLSI.L1_PUTS           15      0.00%      0.00%
+system.ruby.L2Cache_Controller.OLSI.Writeback_Ack          212      0.00%      0.00%
+system.ruby.Directory_Controller.GETX          219834      0.00%      0.00%
+system.ruby.Directory_Controller.GETS          397454      0.00%      0.00%
+system.ruby.Directory_Controller.PUTX          616629      0.00%      0.00%
+system.ruby.Directory_Controller.PUTO_SHARERS          212      0.00%      0.00%
+system.ruby.Directory_Controller.Last_Unblock          399      0.00%      0.00%
+system.ruby.Directory_Controller.Exclusive_Unblock       616854      0.00%      0.00%
+system.ruby.Directory_Controller.Clean_Writeback       393565      0.00%      0.00%
+system.ruby.Directory_Controller.Dirty_Writeback       223252      0.00%      0.00%
+system.ruby.Directory_Controller.Memory_Data       617270      0.00%      0.00%
+system.ruby.Directory_Controller.Memory_Ack       223251      0.00%      0.00%
+system.ruby.Directory_Controller.I.GETX        219624      0.00%      0.00%
+system.ruby.Directory_Controller.I.GETS        397048      0.00%      0.00%
+system.ruby.Directory_Controller.I.Memory_Ack       221545      0.00%      0.00%
+system.ruby.Directory_Controller.S.GETX           209      0.00%      0.00%
+system.ruby.Directory_Controller.S.GETS           399      0.00%      0.00%
+system.ruby.Directory_Controller.S.Memory_Ack           75      0.00%      0.00%
+system.ruby.Directory_Controller.M.PUTX        616629      0.00%      0.00%
+system.ruby.Directory_Controller.M.PUTO_SHARERS          212      0.00%      0.00%
+system.ruby.Directory_Controller.IS.Exclusive_Unblock       397035      0.00%      0.00%
+system.ruby.Directory_Controller.IS.Memory_Data       397043      0.00%      0.00%
+system.ruby.Directory_Controller.IS.Memory_Ack         1058      0.00%      0.00%
+system.ruby.Directory_Controller.SS.Last_Unblock          399      0.00%      0.00%
+system.ruby.Directory_Controller.SS.Memory_Data          399      0.00%      0.00%
+system.ruby.Directory_Controller.MM.Exclusive_Unblock       219819      0.00%      0.00%
+system.ruby.Directory_Controller.MM.Memory_Data       219828      0.00%      0.00%
+system.ruby.Directory_Controller.MM.Memory_Ack          573      0.00%      0.00%
+system.ruby.Directory_Controller.MI.GETX            1      0.00%      0.00%
+system.ruby.Directory_Controller.MI.GETS            7      0.00%      0.00%
+system.ruby.Directory_Controller.MI.Clean_Writeback       393428      0.00%      0.00%
+system.ruby.Directory_Controller.MI.Dirty_Writeback       223177      0.00%      0.00%
+system.ruby.Directory_Controller.MIS.Clean_Writeback          137      0.00%      0.00%
+system.ruby.Directory_Controller.MIS.Dirty_Writeback           75      0.00%      0.00%
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt
index 7d7ea198b..607213fd3 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt
@@ -1,1351 +1,1360 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.006151                       # Number of seconds simulated
-sim_ticks                                     6151475                       # Number of ticks simulated
-final_tick                                    6151475                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.006285                       # Number of seconds simulated
+sim_ticks                                     6284915                       # Number of ticks simulated
+final_tick                                    6284915                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_tick_rate                                  74061                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 259044                       # Number of bytes of host memory used
-host_seconds                                    83.06                       # Real time elapsed on the host
+host_tick_rate                                  64396                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 293488                       # Number of bytes of host memory used
+host_seconds                                    97.60                       # Real time elapsed on the host
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                             1                       # Clock period in ticks
 system.ruby.clk_domain.clock                        1                       # Clock period in ticks
 system.ruby.outstanding_req_hist::bucket_size            2                      
 system.ruby.outstanding_req_hist::max_bucket           19                      
-system.ruby.outstanding_req_hist::samples       617095                      
-system.ruby.outstanding_req_hist::mean      15.998444                      
-system.ruby.outstanding_req_hist::gmean     15.997161                      
-system.ruby.outstanding_req_hist::stdev      0.126779                      
-system.ruby.outstanding_req_hist         |           8      0.00%      0.00% |          16      0.00%      0.00% |          16      0.00%      0.01% |          16      0.00%      0.01% |          16      0.00%      0.01% |          16      0.00%      0.01% |          16      0.00%      0.02% |          16      0.00%      0.02% |      616975     99.98%    100.00% |           0      0.00%    100.00%
-system.ruby.outstanding_req_hist::total        617095                      
-system.ruby.latency_hist::bucket_size            1024                      
-system.ruby.latency_hist::max_bucket            10239                      
-system.ruby.latency_hist::samples              616967                      
-system.ruby.latency_hist::mean            1276.004801                      
-system.ruby.latency_hist::gmean            906.102654                      
-system.ruby.latency_hist::stdev            879.924073                      
-system.ruby.latency_hist                 |      283362     45.93%     45.93% |      188407     30.54%     76.47% |      133926     21.71%     98.17% |       11074      1.79%     99.97% |         197      0.03%    100.00% |           1      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.latency_hist::total                616967                      
+system.ruby.outstanding_req_hist::samples       628367                      
+system.ruby.outstanding_req_hist::mean      15.998471                      
+system.ruby.outstanding_req_hist::gmean     15.997210                      
+system.ruby.outstanding_req_hist::stdev      0.125643                      
+system.ruby.outstanding_req_hist         |           8      0.00%      0.00% |          16      0.00%      0.00% |          16      0.00%      0.01% |          16      0.00%      0.01% |          16      0.00%      0.01% |          16      0.00%      0.01% |          16      0.00%      0.02% |          17      0.00%      0.02% |      628246     99.98%    100.00% |           0      0.00%    100.00%
+system.ruby.outstanding_req_hist::total        628367                      
+system.ruby.latency_hist::bucket_size             512                      
+system.ruby.latency_hist::max_bucket             5119                      
+system.ruby.latency_hist::samples              628239                      
+system.ruby.latency_hist::mean            1280.340022                      
+system.ruby.latency_hist::gmean            910.453414                      
+system.ruby.latency_hist::stdev            881.906997                      
+system.ruby.latency_hist                 |      178239     28.37%     28.37% |      109504     17.43%     45.80% |       92912     14.79%     60.59% |       97614     15.54%     76.13% |       93350     14.86%     90.99% |       44633      7.10%     98.09% |       10565      1.68%     99.77% |        1287      0.20%     99.98% |         121      0.02%    100.00% |          14      0.00%    100.00%
+system.ruby.latency_hist::total                628239                      
 system.ruby.hit_latency_hist::bucket_size          512                      
 system.ruby.hit_latency_hist::max_bucket         5119                      
-system.ruby.hit_latency_hist::samples            3585                      
-system.ruby.hit_latency_hist::mean        1200.185216                      
-system.ruby.hit_latency_hist::gmean        616.910494                      
-system.ruby.hit_latency_hist::stdev        912.592872                      
-system.ruby.hit_latency_hist             |        1173     32.72%     32.72% |         570     15.90%     48.62% |         519     14.48%     63.10% |         546     15.23%     78.33% |         453     12.64%     90.96% |         259      7.22%     98.19% |          56      1.56%     99.75% |           8      0.22%     99.97% |           1      0.03%    100.00% |           0      0.00%    100.00%
-system.ruby.hit_latency_hist::total              3585                      
-system.ruby.miss_latency_hist::bucket_size         1024                      
-system.ruby.miss_latency_hist::max_bucket        10239                      
-system.ruby.miss_latency_hist::samples         613382                      
-system.ruby.miss_latency_hist::mean       1276.447939                      
-system.ruby.miss_latency_hist::gmean       908.140819                      
-system.ruby.miss_latency_hist::stdev       879.711134                      
-system.ruby.miss_latency_hist            |      281619     45.91%     45.91% |      187342     30.54%     76.45% |      133214     21.72%     98.17% |       11010      1.79%     99.97% |         196      0.03%    100.00% |           1      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.miss_latency_hist::total           613382                      
-system.ruby.L1Cache.incomplete_times             2563                      
-system.ruby.Directory.incomplete_times         610812                      
-system.ruby.l1_cntrl4.L1Dcache.demand_hits           20                       # Number of cache demand hits
-system.ruby.l1_cntrl4.L1Dcache.demand_misses        76947                       # Number of cache demand misses
-system.ruby.l1_cntrl4.L1Dcache.demand_accesses        76967                       # Number of cache demand accesses
+system.ruby.hit_latency_hist::samples            3487                      
+system.ruby.hit_latency_hist::mean        1186.728993                      
+system.ruby.hit_latency_hist::gmean        569.952123                      
+system.ruby.hit_latency_hist::stdev        923.761130                      
+system.ruby.hit_latency_hist             |        1143     32.78%     32.78% |         594     17.03%     49.81% |         495     14.20%     64.01% |         467     13.39%     77.40% |         486     13.94%     91.34% |         230      6.60%     97.94% |          60      1.72%     99.66% |          11      0.32%     99.97% |           1      0.03%    100.00% |           0      0.00%    100.00%
+system.ruby.hit_latency_hist::total              3487                      
+system.ruby.miss_latency_hist::bucket_size          512                      
+system.ruby.miss_latency_hist::max_bucket         5119                      
+system.ruby.miss_latency_hist::samples         624752                      
+system.ruby.miss_latency_hist::mean       1280.862504                      
+system.ruby.miss_latency_hist::gmean       912.836708                      
+system.ruby.miss_latency_hist::stdev       881.640698                      
+system.ruby.miss_latency_hist            |      177096     28.35%     28.35% |      108910     17.43%     45.78% |       92417     14.79%     60.57% |       97147     15.55%     76.12% |       92864     14.86%     90.99% |       44403      7.11%     98.09% |       10505      1.68%     99.77% |        1276      0.20%     99.98% |         120      0.02%    100.00% |          14      0.00%    100.00%
+system.ruby.miss_latency_hist::total           624752                      
+system.ruby.L1Cache.incomplete_times             2524                      
+system.ruby.Directory.incomplete_times         622224                      
+system.ruby.l1_cntrl4.L1Dcache.demand_hits           34                       # Number of cache demand hits
+system.ruby.l1_cntrl4.L1Dcache.demand_misses        78735                       # Number of cache demand misses
+system.ruby.l1_cntrl4.L1Dcache.demand_accesses        78769                       # Number of cache demand accesses
 system.ruby.l1_cntrl4.L1Icache.demand_hits            0                       # Number of cache demand hits
 system.ruby.l1_cntrl4.L1Icache.demand_misses            0                       # Number of cache demand misses
 system.ruby.l1_cntrl4.L1Icache.demand_accesses            0                       # Number of cache demand accesses
-system.ruby.l1_cntrl5.L1Dcache.demand_hits           25                       # Number of cache demand hits
-system.ruby.l1_cntrl5.L1Dcache.demand_misses        77241                       # Number of cache demand misses
-system.ruby.l1_cntrl5.L1Dcache.demand_accesses        77266                       # Number of cache demand accesses
+system.ruby.l1_cntrl5.L1Dcache.demand_hits           26                       # Number of cache demand hits
+system.ruby.l1_cntrl5.L1Dcache.demand_misses        78593                       # Number of cache demand misses
+system.ruby.l1_cntrl5.L1Dcache.demand_accesses        78619                       # Number of cache demand accesses
 system.ruby.l1_cntrl5.L1Icache.demand_hits            0                       # Number of cache demand hits
 system.ruby.l1_cntrl5.L1Icache.demand_misses            0                       # Number of cache demand misses
 system.ruby.l1_cntrl5.L1Icache.demand_accesses            0                       # Number of cache demand accesses
-system.ruby.l1_cntrl6.L1Dcache.demand_hits           19                       # Number of cache demand hits
-system.ruby.l1_cntrl6.L1Dcache.demand_misses        77320                       # Number of cache demand misses
-system.ruby.l1_cntrl6.L1Dcache.demand_accesses        77339                       # Number of cache demand accesses
+system.ruby.l1_cntrl6.L1Dcache.demand_hits           25                       # Number of cache demand hits
+system.ruby.l1_cntrl6.L1Dcache.demand_misses        78361                       # Number of cache demand misses
+system.ruby.l1_cntrl6.L1Dcache.demand_accesses        78386                       # Number of cache demand accesses
 system.ruby.l1_cntrl6.L1Icache.demand_hits            0                       # Number of cache demand hits
 system.ruby.l1_cntrl6.L1Icache.demand_misses            0                       # Number of cache demand misses
 system.ruby.l1_cntrl6.L1Icache.demand_accesses            0                       # Number of cache demand accesses
-system.ruby.l1_cntrl7.L1Dcache.demand_hits           21                       # Number of cache demand hits
-system.ruby.l1_cntrl7.L1Dcache.demand_misses        76925                       # Number of cache demand misses
-system.ruby.l1_cntrl7.L1Dcache.demand_accesses        76946                       # Number of cache demand accesses
+system.ruby.l1_cntrl7.L1Dcache.demand_hits           26                       # Number of cache demand hits
+system.ruby.l1_cntrl7.L1Dcache.demand_misses        78366                       # Number of cache demand misses
+system.ruby.l1_cntrl7.L1Dcache.demand_accesses        78392                       # Number of cache demand accesses
 system.ruby.l1_cntrl7.L1Icache.demand_hits            0                       # Number of cache demand hits
 system.ruby.l1_cntrl7.L1Icache.demand_misses            0                       # Number of cache demand misses
 system.ruby.l1_cntrl7.L1Icache.demand_accesses            0                       # Number of cache demand accesses
 system.ruby.l1_cntrl0.L1Dcache.demand_hits           24                       # Number of cache demand hits
-system.ruby.l1_cntrl0.L1Dcache.demand_misses        77267                       # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Dcache.demand_accesses        77291                       # Number of cache demand accesses
+system.ruby.l1_cntrl0.L1Dcache.demand_misses        78372                       # Number of cache demand misses
+system.ruby.l1_cntrl0.L1Dcache.demand_accesses        78396                       # Number of cache demand accesses
 system.ruby.l1_cntrl0.L1Icache.demand_hits            0                       # Number of cache demand hits
 system.ruby.l1_cntrl0.L1Icache.demand_misses            0                       # Number of cache demand misses
 system.ruby.l1_cntrl0.L1Icache.demand_accesses            0                       # Number of cache demand accesses
-system.ruby.l1_cntrl1.L1Dcache.demand_hits           17                       # Number of cache demand hits
-system.ruby.l1_cntrl1.L1Dcache.demand_misses        77262                       # Number of cache demand misses
-system.ruby.l1_cntrl1.L1Dcache.demand_accesses        77279                       # Number of cache demand accesses
+system.ruby.l1_cntrl1.L1Dcache.demand_hits           27                       # Number of cache demand hits
+system.ruby.l1_cntrl1.L1Dcache.demand_misses        78895                       # Number of cache demand misses
+system.ruby.l1_cntrl1.L1Dcache.demand_accesses        78922                       # Number of cache demand accesses
 system.ruby.l1_cntrl1.L1Icache.demand_hits            0                       # Number of cache demand hits
 system.ruby.l1_cntrl1.L1Icache.demand_misses            0                       # Number of cache demand misses
 system.ruby.l1_cntrl1.L1Icache.demand_accesses            0                       # Number of cache demand accesses
-system.ruby.l1_cntrl2.L1Dcache.demand_hits           17                       # Number of cache demand hits
-system.ruby.l1_cntrl2.L1Dcache.demand_misses        77078                       # Number of cache demand misses
-system.ruby.l1_cntrl2.L1Dcache.demand_accesses        77095                       # Number of cache demand accesses
+system.ruby.l1_cntrl2.L1Dcache.demand_hits           23                       # Number of cache demand hits
+system.ruby.l1_cntrl2.L1Dcache.demand_misses        78341                       # Number of cache demand misses
+system.ruby.l1_cntrl2.L1Dcache.demand_accesses        78364                       # Number of cache demand accesses
 system.ruby.l1_cntrl2.L1Icache.demand_hits            0                       # Number of cache demand hits
 system.ruby.l1_cntrl2.L1Icache.demand_misses            0                       # Number of cache demand misses
 system.ruby.l1_cntrl2.L1Icache.demand_accesses            0                       # Number of cache demand accesses
 system.ruby.l1_cntrl3.L1Dcache.demand_hits           22                       # Number of cache demand hits
-system.ruby.l1_cntrl3.L1Dcache.demand_misses        76783                       # Number of cache demand misses
-system.ruby.l1_cntrl3.L1Dcache.demand_accesses        76805                       # Number of cache demand accesses
+system.ruby.l1_cntrl3.L1Dcache.demand_misses        78389                       # Number of cache demand misses
+system.ruby.l1_cntrl3.L1Dcache.demand_accesses        78411                       # Number of cache demand accesses
 system.ruby.l1_cntrl3.L1Icache.demand_hits            0                       # Number of cache demand hits
 system.ruby.l1_cntrl3.L1Icache.demand_misses            0                       # Number of cache demand misses
 system.ruby.l1_cntrl3.L1Icache.demand_accesses            0                       # Number of cache demand accesses
-system.ruby.l2_cntrl0.L2cache.demand_hits         1681                       # Number of cache demand hits
-system.ruby.l2_cntrl0.L2cache.demand_misses       615142                       # Number of cache demand misses
-system.ruby.l2_cntrl0.L2cache.demand_accesses       616823                       # Number of cache demand accesses
-system.ruby.network.routers00.percent_links_utilized     9.956291                      
-system.ruby.network.routers00.msg_count.Request_Control::1        77267                      
-system.ruby.network.routers00.msg_count.Response_Data::4        76923                      
-system.ruby.network.routers00.msg_count.ResponseL2hit_Data::4          231                      
-system.ruby.network.routers00.msg_count.ResponseLocal_Data::4          399                      
-system.ruby.network.routers00.msg_count.Response_Control::4          188                      
-system.ruby.network.routers00.msg_count.Writeback_Data::4        85053                      
-system.ruby.network.routers00.msg_count.Broadcast_Control::1       616823                      
-system.ruby.network.routers00.msg_count.Persistent_Control::3       292106                      
-system.ruby.network.routers00.msg_bytes.Request_Control::1       618136                      
-system.ruby.network.routers00.msg_bytes.Response_Data::4      5538456                      
-system.ruby.network.routers00.msg_bytes.ResponseL2hit_Data::4        16632                      
-system.ruby.network.routers00.msg_bytes.ResponseLocal_Data::4        28728                      
-system.ruby.network.routers00.msg_bytes.Response_Control::4         1504                      
-system.ruby.network.routers00.msg_bytes.Writeback_Data::4      6123816                      
-system.ruby.network.routers00.msg_bytes.Broadcast_Control::1      4934584                      
-system.ruby.network.routers00.msg_bytes.Persistent_Control::3      2336848                      
-system.ruby.network.routers01.percent_links_utilized     9.941095                      
-system.ruby.network.routers01.msg_count.Request_Control::1        77262                      
-system.ruby.network.routers01.msg_count.Response_Data::4        76930                      
-system.ruby.network.routers01.msg_count.ResponseL2hit_Data::4          196                      
-system.ruby.network.routers01.msg_count.ResponseLocal_Data::4          372                      
-system.ruby.network.routers01.msg_count.Response_Control::4          173                      
-system.ruby.network.routers01.msg_count.Writeback_Data::4        84683                      
-system.ruby.network.routers01.msg_count.Broadcast_Control::1       616823                      
-system.ruby.network.routers01.msg_count.Persistent_Control::3       292209                      
-system.ruby.network.routers01.msg_bytes.Request_Control::1       618096                      
-system.ruby.network.routers01.msg_bytes.Response_Data::4      5538960                      
-system.ruby.network.routers01.msg_bytes.ResponseL2hit_Data::4        14112                      
-system.ruby.network.routers01.msg_bytes.ResponseLocal_Data::4        26784                      
-system.ruby.network.routers01.msg_bytes.Response_Control::4         1384                      
-system.ruby.network.routers01.msg_bytes.Writeback_Data::4      6097176                      
-system.ruby.network.routers01.msg_bytes.Broadcast_Control::1      4934584                      
-system.ruby.network.routers01.msg_bytes.Persistent_Control::3      2337672                      
-system.ruby.network.routers02.percent_links_utilized     9.933215                      
-system.ruby.network.routers02.msg_count.Request_Control::1        77078                      
-system.ruby.network.routers02.msg_count.Response_Data::4        76729                      
-system.ruby.network.routers02.msg_count.ResponseL2hit_Data::4          197                      
-system.ruby.network.routers02.msg_count.ResponseLocal_Data::4          401                      
-system.ruby.network.routers02.msg_count.Response_Control::4          179                      
-system.ruby.network.routers02.msg_count.Writeback_Data::4        84627                      
-system.ruby.network.routers02.msg_count.Broadcast_Control::1       616823                      
-system.ruby.network.routers02.msg_count.Persistent_Control::3       292491                      
-system.ruby.network.routers02.msg_bytes.Request_Control::1       616624                      
-system.ruby.network.routers02.msg_bytes.Response_Data::4      5524488                      
-system.ruby.network.routers02.msg_bytes.ResponseL2hit_Data::4        14184                      
-system.ruby.network.routers02.msg_bytes.ResponseLocal_Data::4        28872                      
-system.ruby.network.routers02.msg_bytes.Response_Control::4         1432                      
-system.ruby.network.routers02.msg_bytes.Writeback_Data::4      6093144                      
-system.ruby.network.routers02.msg_bytes.Broadcast_Control::1      4934584                      
-system.ruby.network.routers02.msg_bytes.Persistent_Control::3      2339928                      
-system.ruby.network.routers03.percent_links_utilized     9.903320                      
-system.ruby.network.routers03.msg_count.Request_Control::1        76783                      
-system.ruby.network.routers03.msg_count.Response_Data::4        76429                      
-system.ruby.network.routers03.msg_count.ResponseL2hit_Data::4          214                      
-system.ruby.network.routers03.msg_count.ResponseLocal_Data::4          379                      
-system.ruby.network.routers03.msg_count.Response_Control::4          182                      
-system.ruby.network.routers03.msg_count.Writeback_Data::4        84224                      
-system.ruby.network.routers03.msg_count.Broadcast_Control::1       616823                      
-system.ruby.network.routers03.msg_count.Persistent_Control::3       291799                      
-system.ruby.network.routers03.msg_bytes.Request_Control::1       614264                      
-system.ruby.network.routers03.msg_bytes.Response_Data::4      5502888                      
-system.ruby.network.routers03.msg_bytes.ResponseL2hit_Data::4        15408                      
-system.ruby.network.routers03.msg_bytes.ResponseLocal_Data::4        27288                      
-system.ruby.network.routers03.msg_bytes.Response_Control::4         1456                      
-system.ruby.network.routers03.msg_bytes.Writeback_Data::4      6064128                      
-system.ruby.network.routers03.msg_bytes.Broadcast_Control::1      4934584                      
-system.ruby.network.routers03.msg_bytes.Persistent_Control::3      2334392                      
-system.ruby.network.routers04.percent_links_utilized     9.916236                      
-system.ruby.network.routers04.msg_count.Request_Control::1        76947                      
-system.ruby.network.routers04.msg_count.Response_Data::4        76520                      
-system.ruby.network.routers04.msg_count.ResponseL2hit_Data::4          224                      
-system.ruby.network.routers04.msg_count.ResponseLocal_Data::4          401                      
-system.ruby.network.routers04.msg_count.Response_Control::4          179                      
-system.ruby.network.routers04.msg_count.Writeback_Data::4        84404                      
-system.ruby.network.routers04.msg_count.Broadcast_Control::1       616823                      
-system.ruby.network.routers04.msg_count.Persistent_Control::3       292089                      
-system.ruby.network.routers04.msg_bytes.Request_Control::1       615576                      
-system.ruby.network.routers04.msg_bytes.Response_Data::4      5509440                      
-system.ruby.network.routers04.msg_bytes.ResponseL2hit_Data::4        16128                      
-system.ruby.network.routers04.msg_bytes.ResponseLocal_Data::4        28872                      
-system.ruby.network.routers04.msg_bytes.Response_Control::4         1432                      
-system.ruby.network.routers04.msg_bytes.Writeback_Data::4      6077088                      
-system.ruby.network.routers04.msg_bytes.Broadcast_Control::1      4934584                      
-system.ruby.network.routers04.msg_bytes.Persistent_Control::3      2336712                      
-system.ruby.network.routers05.percent_links_utilized     9.943201                      
-system.ruby.network.routers05.msg_count.Request_Control::1        77241                      
-system.ruby.network.routers05.msg_count.Response_Data::4        76822                      
-system.ruby.network.routers05.msg_count.ResponseL2hit_Data::4          228                      
-system.ruby.network.routers05.msg_count.ResponseLocal_Data::4          398                      
-system.ruby.network.routers05.msg_count.Response_Control::4          168                      
-system.ruby.network.routers05.msg_count.Writeback_Data::4        84787                      
-system.ruby.network.routers05.msg_count.Broadcast_Control::1       616823                      
-system.ruby.network.routers05.msg_count.Persistent_Control::3       292267                      
-system.ruby.network.routers05.msg_bytes.Request_Control::1       617928                      
-system.ruby.network.routers05.msg_bytes.Response_Data::4      5531184                      
-system.ruby.network.routers05.msg_bytes.ResponseL2hit_Data::4        16416                      
-system.ruby.network.routers05.msg_bytes.ResponseLocal_Data::4        28656                      
-system.ruby.network.routers05.msg_bytes.Response_Control::4         1344                      
-system.ruby.network.routers05.msg_bytes.Writeback_Data::4      6104664                      
-system.ruby.network.routers05.msg_bytes.Broadcast_Control::1      4934584                      
-system.ruby.network.routers05.msg_bytes.Persistent_Control::3      2338136                      
-system.ruby.network.routers06.percent_links_utilized     9.948553                      
-system.ruby.network.routers06.msg_count.Request_Control::1        77320                      
-system.ruby.network.routers06.msg_count.Response_Data::4        76935                      
-system.ruby.network.routers06.msg_count.ResponseL2hit_Data::4          187                      
-system.ruby.network.routers06.msg_count.ResponseLocal_Data::4          362                      
-system.ruby.network.routers06.msg_count.Response_Control::4          166                      
-system.ruby.network.routers06.msg_count.Writeback_Data::4        84904                      
-system.ruby.network.routers06.msg_count.Broadcast_Control::1       616823                      
-system.ruby.network.routers06.msg_count.Persistent_Control::3       292130                      
-system.ruby.network.routers06.msg_bytes.Request_Control::1       618560                      
-system.ruby.network.routers06.msg_bytes.Response_Data::4      5539320                      
-system.ruby.network.routers06.msg_bytes.ResponseL2hit_Data::4        13464                      
-system.ruby.network.routers06.msg_bytes.ResponseLocal_Data::4        26064                      
-system.ruby.network.routers06.msg_bytes.Response_Control::4         1328                      
-system.ruby.network.routers06.msg_bytes.Writeback_Data::4      6113088                      
-system.ruby.network.routers06.msg_bytes.Broadcast_Control::1      4934584                      
-system.ruby.network.routers06.msg_bytes.Persistent_Control::3      2337040                      
-system.ruby.network.routers07.percent_links_utilized     9.919076                      
-system.ruby.network.routers07.msg_count.Request_Control::1        76925                      
-system.ruby.network.routers07.msg_count.Response_Data::4        76452                      
-system.ruby.network.routers07.msg_count.ResponseL2hit_Data::4          214                      
-system.ruby.network.routers07.msg_count.ResponseLocal_Data::4          420                      
-system.ruby.network.routers07.msg_count.Response_Control::4          195                      
-system.ruby.network.routers07.msg_count.Writeback_Data::4        84536                      
-system.ruby.network.routers07.msg_count.Broadcast_Control::1       616823                      
-system.ruby.network.routers07.msg_count.Persistent_Control::3       292137                      
-system.ruby.network.routers07.msg_bytes.Request_Control::1       615400                      
-system.ruby.network.routers07.msg_bytes.Response_Data::4      5504544                      
-system.ruby.network.routers07.msg_bytes.ResponseL2hit_Data::4        15408                      
-system.ruby.network.routers07.msg_bytes.ResponseLocal_Data::4        30240                      
-system.ruby.network.routers07.msg_bytes.Response_Control::4         1560                      
-system.ruby.network.routers07.msg_bytes.Writeback_Data::4      6086592                      
-system.ruby.network.routers07.msg_bytes.Broadcast_Control::1      4934584                      
-system.ruby.network.routers07.msg_bytes.Persistent_Control::3      2337096                      
-system.ruby.network.routers08.percent_links_utilized    38.819523                      
-system.ruby.network.routers08.msg_count.Request_Control::1       616823                      
-system.ruby.network.routers08.msg_count.Request_Control::2       615142                      
-system.ruby.network.routers08.msg_count.Response_Data::4         1316                      
-system.ruby.network.routers08.msg_count.ResponseL2hit_Data::4         1684                      
-system.ruby.network.routers08.msg_count.Response_Control::4         1398                      
-system.ruby.network.routers08.msg_count.Writeback_Data::4       850473                      
-system.ruby.network.routers08.msg_count.Writeback_Control::4       377581                      
-system.ruby.network.routers08.msg_count.Persistent_Control::3       259692                      
-system.ruby.network.routers08.msg_bytes.Request_Control::1      4934584                      
-system.ruby.network.routers08.msg_bytes.Request_Control::2      4921136                      
-system.ruby.network.routers08.msg_bytes.Response_Data::4        94752                      
-system.ruby.network.routers08.msg_bytes.ResponseL2hit_Data::4       121248                      
-system.ruby.network.routers08.msg_bytes.Response_Control::4        11184                      
-system.ruby.network.routers08.msg_bytes.Writeback_Data::4     61234056                      
-system.ruby.network.routers08.msg_bytes.Writeback_Control::4      3020648                      
-system.ruby.network.routers08.msg_bytes.Persistent_Control::3      2077536                      
+system.ruby.l2_cntrl0.L2cache.demand_hits         1540                       # Number of cache demand hits
+system.ruby.l2_cntrl0.L2cache.demand_misses       626511                       # Number of cache demand misses
+system.ruby.l2_cntrl0.L2cache.demand_accesses       628051                       # Number of cache demand accesses
+system.ruby.network.routers00.percent_links_utilized     9.881597                      
+system.ruby.network.routers00.msg_count.Request_Control::1        78371                      
+system.ruby.network.routers00.msg_count.Response_Data::4        78092                      
+system.ruby.network.routers00.msg_count.ResponseL2hit_Data::4          187                      
+system.ruby.network.routers00.msg_count.ResponseLocal_Data::4          360                      
+system.ruby.network.routers00.msg_count.Response_Control::4          159                      
+system.ruby.network.routers00.msg_count.Writeback_Data::4        85878                      
+system.ruby.network.routers00.msg_count.Broadcast_Control::1       628051                      
+system.ruby.network.routers00.msg_count.Persistent_Control::3       296969                      
+system.ruby.network.routers00.msg_bytes.Request_Control::1       626968                      
+system.ruby.network.routers00.msg_bytes.Response_Data::4      5622624                      
+system.ruby.network.routers00.msg_bytes.ResponseL2hit_Data::4        13464                      
+system.ruby.network.routers00.msg_bytes.ResponseLocal_Data::4        25920                      
+system.ruby.network.routers00.msg_bytes.Response_Control::4         1272                      
+system.ruby.network.routers00.msg_bytes.Writeback_Data::4      6183216                      
+system.ruby.network.routers00.msg_bytes.Broadcast_Control::1      5024408                      
+system.ruby.network.routers00.msg_bytes.Persistent_Control::3      2375752                      
+system.ruby.network.routers01.percent_links_utilized     9.921833                      
+system.ruby.network.routers01.msg_count.Request_Control::1        78895                      
+system.ruby.network.routers01.msg_count.Response_Data::4        78610                      
+system.ruby.network.routers01.msg_count.ResponseL2hit_Data::4          189                      
+system.ruby.network.routers01.msg_count.ResponseLocal_Data::4          337                      
+system.ruby.network.routers01.msg_count.Response_Control::4          156                      
+system.ruby.network.routers01.msg_count.Writeback_Data::4        86402                      
+system.ruby.network.routers01.msg_count.Writeback_Control::4            2                      
+system.ruby.network.routers01.msg_count.Broadcast_Control::1       628051                      
+system.ruby.network.routers01.msg_count.Persistent_Control::3       297369                      
+system.ruby.network.routers01.msg_bytes.Request_Control::1       631160                      
+system.ruby.network.routers01.msg_bytes.Response_Data::4      5659920                      
+system.ruby.network.routers01.msg_bytes.ResponseL2hit_Data::4        13608                      
+system.ruby.network.routers01.msg_bytes.ResponseLocal_Data::4        24264                      
+system.ruby.network.routers01.msg_bytes.Response_Control::4         1248                      
+system.ruby.network.routers01.msg_bytes.Writeback_Data::4      6220944                      
+system.ruby.network.routers01.msg_bytes.Writeback_Control::4           16                      
+system.ruby.network.routers01.msg_bytes.Broadcast_Control::1      5024408                      
+system.ruby.network.routers01.msg_bytes.Persistent_Control::3      2378952                      
+system.ruby.network.routers02.percent_links_utilized     9.878833                      
+system.ruby.network.routers02.msg_count.Request_Control::1        78341                      
+system.ruby.network.routers02.msg_count.Response_Data::4        77980                      
+system.ruby.network.routers02.msg_count.ResponseL2hit_Data::4          204                      
+system.ruby.network.routers02.msg_count.ResponseLocal_Data::4          408                      
+system.ruby.network.routers02.msg_count.Response_Control::4          170                      
+system.ruby.network.routers02.msg_count.Writeback_Data::4        85810                      
+system.ruby.network.routers02.msg_count.Broadcast_Control::1       628051                      
+system.ruby.network.routers02.msg_count.Persistent_Control::3       297325                      
+system.ruby.network.routers02.msg_bytes.Request_Control::1       626728                      
+system.ruby.network.routers02.msg_bytes.Response_Data::4      5614560                      
+system.ruby.network.routers02.msg_bytes.ResponseL2hit_Data::4        14688                      
+system.ruby.network.routers02.msg_bytes.ResponseLocal_Data::4        29376                      
+system.ruby.network.routers02.msg_bytes.Response_Control::4         1360                      
+system.ruby.network.routers02.msg_bytes.Writeback_Data::4      6178320                      
+system.ruby.network.routers02.msg_bytes.Broadcast_Control::1      5024408                      
+system.ruby.network.routers02.msg_bytes.Persistent_Control::3      2378600                      
+system.ruby.network.routers03.percent_links_utilized     9.881140                      
+system.ruby.network.routers03.msg_count.Request_Control::1        78389                      
+system.ruby.network.routers03.msg_count.Response_Data::4        78013                      
+system.ruby.network.routers03.msg_count.ResponseL2hit_Data::4          216                      
+system.ruby.network.routers03.msg_count.ResponseLocal_Data::4          388                      
+system.ruby.network.routers03.msg_count.Response_Control::4          177                      
+system.ruby.network.routers03.msg_count.Writeback_Data::4        85850                      
+system.ruby.network.routers03.msg_count.Writeback_Control::4            1                      
+system.ruby.network.routers03.msg_count.Broadcast_Control::1       628051                      
+system.ruby.network.routers03.msg_count.Persistent_Control::3       297264                      
+system.ruby.network.routers03.msg_bytes.Request_Control::1       627112                      
+system.ruby.network.routers03.msg_bytes.Response_Data::4      5616936                      
+system.ruby.network.routers03.msg_bytes.ResponseL2hit_Data::4        15552                      
+system.ruby.network.routers03.msg_bytes.ResponseLocal_Data::4        27936                      
+system.ruby.network.routers03.msg_bytes.Response_Control::4         1416                      
+system.ruby.network.routers03.msg_bytes.Writeback_Data::4      6181200                      
+system.ruby.network.routers03.msg_bytes.Writeback_Control::4            8                      
+system.ruby.network.routers03.msg_bytes.Broadcast_Control::1      5024408                      
+system.ruby.network.routers03.msg_bytes.Persistent_Control::3      2378112                      
+system.ruby.network.routers04.percent_links_utilized     9.912946                      
+system.ruby.network.routers04.msg_count.Request_Control::1        78735                      
+system.ruby.network.routers04.msg_count.Response_Data::4        78378                      
+system.ruby.network.routers04.msg_count.ResponseL2hit_Data::4          176                      
+system.ruby.network.routers04.msg_count.ResponseLocal_Data::4          410                      
+system.ruby.network.routers04.msg_count.Response_Control::4          192                      
+system.ruby.network.routers04.msg_count.Writeback_Data::4        86320                      
+system.ruby.network.routers04.msg_count.Writeback_Control::4            2                      
+system.ruby.network.routers04.msg_count.Broadcast_Control::1       628051                      
+system.ruby.network.routers04.msg_count.Persistent_Control::3       297545                      
+system.ruby.network.routers04.msg_bytes.Request_Control::1       629880                      
+system.ruby.network.routers04.msg_bytes.Response_Data::4      5643216                      
+system.ruby.network.routers04.msg_bytes.ResponseL2hit_Data::4        12672                      
+system.ruby.network.routers04.msg_bytes.ResponseLocal_Data::4        29520                      
+system.ruby.network.routers04.msg_bytes.Response_Control::4         1536                      
+system.ruby.network.routers04.msg_bytes.Writeback_Data::4      6215040                      
+system.ruby.network.routers04.msg_bytes.Writeback_Control::4           16                      
+system.ruby.network.routers04.msg_bytes.Broadcast_Control::1      5024408                      
+system.ruby.network.routers04.msg_bytes.Persistent_Control::3      2380360                      
+system.ruby.network.routers05.percent_links_utilized     9.904116                      
+system.ruby.network.routers05.msg_count.Request_Control::1        78593                      
+system.ruby.network.routers05.msg_count.Response_Data::4        78170                      
+system.ruby.network.routers05.msg_count.ResponseL2hit_Data::4          203                      
+system.ruby.network.routers05.msg_count.ResponseLocal_Data::4          374                      
+system.ruby.network.routers05.msg_count.Response_Control::4          171                      
+system.ruby.network.routers05.msg_count.Writeback_Data::4        86349                      
+system.ruby.network.routers05.msg_count.Broadcast_Control::1       628051                      
+system.ruby.network.routers05.msg_count.Persistent_Control::3       297182                      
+system.ruby.network.routers05.msg_bytes.Request_Control::1       628744                      
+system.ruby.network.routers05.msg_bytes.Response_Data::4      5628240                      
+system.ruby.network.routers05.msg_bytes.ResponseL2hit_Data::4        14616                      
+system.ruby.network.routers05.msg_bytes.ResponseLocal_Data::4        26928                      
+system.ruby.network.routers05.msg_bytes.Response_Control::4         1368                      
+system.ruby.network.routers05.msg_bytes.Writeback_Data::4      6217128                      
+system.ruby.network.routers05.msg_bytes.Broadcast_Control::1      5024408                      
+system.ruby.network.routers05.msg_bytes.Persistent_Control::3      2377456                      
+system.ruby.network.routers06.percent_links_utilized     9.877453                      
+system.ruby.network.routers06.msg_count.Request_Control::1        78361                      
+system.ruby.network.routers06.msg_count.Response_Data::4        77958                      
+system.ruby.network.routers06.msg_count.ResponseL2hit_Data::4          176                      
+system.ruby.network.routers06.msg_count.ResponseLocal_Data::4          389                      
+system.ruby.network.routers06.msg_count.Response_Control::4          176                      
+system.ruby.network.routers06.msg_count.Writeback_Data::4        85870                      
+system.ruby.network.routers06.msg_count.Broadcast_Control::1       628051                      
+system.ruby.network.routers06.msg_count.Persistent_Control::3       297033                      
+system.ruby.network.routers06.msg_bytes.Request_Control::1       626888                      
+system.ruby.network.routers06.msg_bytes.Response_Data::4      5612976                      
+system.ruby.network.routers06.msg_bytes.ResponseL2hit_Data::4        12672                      
+system.ruby.network.routers06.msg_bytes.ResponseLocal_Data::4        28008                      
+system.ruby.network.routers06.msg_bytes.Response_Control::4         1408                      
+system.ruby.network.routers06.msg_bytes.Writeback_Data::4      6182640                      
+system.ruby.network.routers06.msg_bytes.Broadcast_Control::1      5024408                      
+system.ruby.network.routers06.msg_bytes.Persistent_Control::3      2376264                      
+system.ruby.network.routers07.percent_links_utilized     9.879175                      
+system.ruby.network.routers07.msg_count.Request_Control::1        78366                      
+system.ruby.network.routers07.msg_count.Response_Data::4        77966                      
+system.ruby.network.routers07.msg_count.ResponseL2hit_Data::4          194                      
+system.ruby.network.routers07.msg_count.ResponseLocal_Data::4          394                      
+system.ruby.network.routers07.msg_count.Response_Control::4          200                      
+system.ruby.network.routers07.msg_count.Writeback_Data::4        85877                      
+system.ruby.network.routers07.msg_count.Broadcast_Control::1       628051                      
+system.ruby.network.routers07.msg_count.Persistent_Control::3       297095                      
+system.ruby.network.routers07.msg_bytes.Request_Control::1       626928                      
+system.ruby.network.routers07.msg_bytes.Response_Data::4      5613552                      
+system.ruby.network.routers07.msg_bytes.ResponseL2hit_Data::4        13968                      
+system.ruby.network.routers07.msg_bytes.ResponseLocal_Data::4        28368                      
+system.ruby.network.routers07.msg_bytes.Response_Control::4         1600                      
+system.ruby.network.routers07.msg_bytes.Writeback_Data::4      6183144                      
+system.ruby.network.routers07.msg_bytes.Broadcast_Control::1      5024408                      
+system.ruby.network.routers07.msg_bytes.Persistent_Control::3      2376760                      
+system.ruby.network.routers08.percent_links_utilized    38.794550                      
+system.ruby.network.routers08.msg_count.Request_Control::1       628051                      
+system.ruby.network.routers08.msg_count.Request_Control::2       626511                      
+system.ruby.network.routers08.msg_count.Response_Data::4         1307                      
+system.ruby.network.routers08.msg_count.ResponseL2hit_Data::4         1542                      
+system.ruby.network.routers08.msg_count.Response_Control::4         1381                      
+system.ruby.network.routers08.msg_count.Writeback_Data::4       869556                      
+system.ruby.network.routers08.msg_count.Writeback_Control::4       381032                      
+system.ruby.network.routers08.msg_count.Persistent_Control::3       264198                      
+system.ruby.network.routers08.msg_bytes.Request_Control::1      5024408                      
+system.ruby.network.routers08.msg_bytes.Request_Control::2      5012088                      
+system.ruby.network.routers08.msg_bytes.Response_Data::4        94104                      
+system.ruby.network.routers08.msg_bytes.ResponseL2hit_Data::4       111024                      
+system.ruby.network.routers08.msg_bytes.Response_Control::4        11048                      
+system.ruby.network.routers08.msg_bytes.Writeback_Data::4     62608032                      
+system.ruby.network.routers08.msg_bytes.Writeback_Control::4      3048256                      
+system.ruby.network.routers08.msg_bytes.Persistent_Control::3      2113584                      
 system.ruby.memctrl_clk_domain.clock                3                       # Clock period in ticks
-system.ruby.dir_cntrl0.memBuffer.memReq        844944                       # Total number of memory requests
-system.ruby.dir_cntrl0.memBuffer.memRead       610587                       # Number of memory reads
-system.ruby.dir_cntrl0.memBuffer.memWrite       234338                       # Number of memory writes
-system.ruby.dir_cntrl0.memBuffer.memRefresh        42719                       # Number of memory refreshes
-system.ruby.dir_cntrl0.memBuffer.memWaitCycles     26579508                       # Delay stalled at the head of the bank queue
-system.ruby.dir_cntrl0.memBuffer.memInputQ       577720                       # Delay in the input queue
-system.ruby.dir_cntrl0.memBuffer.memBankQ     15763537                       # Delay behind the head of the bank queue
-system.ruby.dir_cntrl0.memBuffer.totalStalls     42920765                       # Total number of stall cycles
-system.ruby.dir_cntrl0.memBuffer.stallsPerReq    50.797171                       # Expected number of stall cycles per request
-system.ruby.dir_cntrl0.memBuffer.memBankBusy      4097613                       # memory stalls due to busy bank
-system.ruby.dir_cntrl0.memBuffer.memBusBusy      7372232                       # memory stalls due to busy bus
-system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy      2122830                       # memory stalls due to read write turnaround
-system.ruby.dir_cntrl0.memBuffer.memDataBusBusy      1320142                       # memory stalls due to read read turnaround
-system.ruby.dir_cntrl0.memBuffer.memArbWait      5356376                       # memory stalls due to arbitration
-system.ruby.dir_cntrl0.memBuffer.memNotOld      6310315                       # memory stalls due to anti starvation
-system.ruby.dir_cntrl0.memBuffer.memBankCount |       26606      3.15%      3.15% |       25663      3.04%      6.19% |       25635      3.03%      9.22% |       25980      3.07%     12.29% |       25947      3.07%     15.37% |       25870      3.06%     18.43% |       25993      3.08%     21.50% |       25627      3.03%     24.54% |       26268      3.11%     27.65% |       26143      3.09%     30.74% |       25936      3.07%     33.81% |       26178      3.10%     36.91% |       26391      3.12%     40.03% |       26459      3.13%     43.16% |       26079      3.09%     46.25% |       26348      3.12%     49.37% |       26234      3.10%     52.47% |       26478      3.13%     55.61% |       26175      3.10%     58.70% |       26431      3.13%     61.83% |       26351      3.12%     64.95% |       26505      3.14%     68.09% |       26354      3.12%     71.21% |       26626      3.15%     74.36% |       26636      3.15%     77.51% |       26614      3.15%     80.66% |       27037      3.20%     83.86% |       26934      3.19%     87.05% |       26972      3.19%     90.24% |       27613      3.27%     93.51% |       27729      3.28%     96.79% |       27132      3.21%    100.00% # Number of accesses per bank
-system.ruby.dir_cntrl0.memBuffer.memBankCount::total       844944                       # Number of accesses per bank
-system.ruby.network.routers09.percent_links_utilized    36.009872                      
-system.ruby.network.routers09.msg_count.Request_Control::2       615142                      
-system.ruby.network.routers09.msg_count.Response_Data::4       610757                      
-system.ruby.network.routers09.msg_count.ResponseL2hit_Data::4            7                      
+system.ruby.dir_cntrl0.memBuffer.memReq        864242                       # Total number of memory requests
+system.ruby.dir_cntrl0.memBuffer.memRead       622033                       # Number of memory reads
+system.ruby.dir_cntrl0.memBuffer.memWrite       242193                       # Number of memory writes
+system.ruby.dir_cntrl0.memBuffer.memRefresh        43645                       # Number of memory refreshes
+system.ruby.dir_cntrl0.memBuffer.memWaitCycles     27461495                       # Delay stalled at the head of the bank queue
+system.ruby.dir_cntrl0.memBuffer.memInputQ       578673                       # Delay in the input queue
+system.ruby.dir_cntrl0.memBuffer.memBankQ     16277009                       # Delay behind the head of the bank queue
+system.ruby.dir_cntrl0.memBuffer.totalStalls     44317177                       # Total number of stall cycles
+system.ruby.dir_cntrl0.memBuffer.stallsPerReq    51.278666                       # Expected number of stall cycles per request
+system.ruby.dir_cntrl0.memBuffer.memBankBusy      4218454                       # memory stalls due to busy bank
+system.ruby.dir_cntrl0.memBuffer.memBusBusy      7606216                       # memory stalls due to busy bus
+system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy      2196938                       # memory stalls due to read write turnaround
+system.ruby.dir_cntrl0.memBuffer.memDataBusBusy      1343216                       # memory stalls due to read read turnaround
+system.ruby.dir_cntrl0.memBuffer.memArbWait      5525484                       # memory stalls due to arbitration
+system.ruby.dir_cntrl0.memBuffer.memNotOld      6571187                       # memory stalls due to anti starvation
+system.ruby.dir_cntrl0.memBuffer.memBankCount |       26896      3.11%      3.11% |       26818      3.10%      6.22% |       26669      3.09%      9.30% |       26464      3.06%     12.36% |       26562      3.07%     15.44% |       26747      3.09%     18.53% |       26938      3.12%     21.65% |       26620      3.08%     24.73% |       26486      3.06%     27.79% |       26669      3.09%     30.88% |       26845      3.11%     33.99% |       26587      3.08%     37.06% |       26997      3.12%     40.19% |       27036      3.13%     43.31% |       27094      3.14%     46.45% |       27338      3.16%     49.61% |       26976      3.12%     52.73% |       26825      3.10%     55.84% |       26849      3.11%     58.94% |       27229      3.15%     62.09% |       26807      3.10%     65.20% |       26957      3.12%     68.32% |       26908      3.11%     71.43% |       26873      3.11%     74.54% |       27042      3.13%     77.67% |       27208      3.15%     80.82% |       26897      3.11%     83.93% |       27258      3.15%     87.08% |       27597      3.19%     90.27% |       27873      3.23%     93.50% |       27778      3.21%     96.71% |       28399      3.29%    100.00% # Number of accesses per bank
+system.ruby.dir_cntrl0.memBuffer.memBankCount::total       864242                       # Number of accesses per bank
+system.ruby.network.routers09.percent_links_utilized    36.011036                      
+system.ruby.network.routers09.msg_count.Request_Control::2       626510                      
+system.ruby.network.routers09.msg_count.Response_Data::4       622169                      
+system.ruby.network.routers09.msg_count.ResponseL2hit_Data::4            3                      
 system.ruby.network.routers09.msg_count.Response_Control::4            4                      
-system.ruby.network.routers09.msg_count.Writeback_Data::4       234585                      
-system.ruby.network.routers09.msg_count.Writeback_Control::4       377581                      
-system.ruby.network.routers09.msg_count.Persistent_Control::3       259692                      
-system.ruby.network.routers09.msg_bytes.Request_Control::2      4921136                      
-system.ruby.network.routers09.msg_bytes.Response_Data::4     43974504                      
-system.ruby.network.routers09.msg_bytes.ResponseL2hit_Data::4          504                      
+system.ruby.network.routers09.msg_count.Writeback_Data::4       242418                      
+system.ruby.network.routers09.msg_count.Writeback_Control::4       381037                      
+system.ruby.network.routers09.msg_count.Persistent_Control::3       264198                      
+system.ruby.network.routers09.msg_bytes.Request_Control::2      5012080                      
+system.ruby.network.routers09.msg_bytes.Response_Data::4     44796168                      
+system.ruby.network.routers09.msg_bytes.ResponseL2hit_Data::4          216                      
 system.ruby.network.routers09.msg_bytes.Response_Control::4           32                      
-system.ruby.network.routers09.msg_bytes.Writeback_Data::4     16890120                      
-system.ruby.network.routers09.msg_bytes.Writeback_Control::4      3020648                      
-system.ruby.network.routers09.msg_bytes.Persistent_Control::3      2077536                      
-system.ruby.network.routers10.percent_links_utilized    17.671908                      
-system.ruby.network.routers10.msg_count.Request_Control::1       616823                      
-system.ruby.network.routers10.msg_count.Request_Control::2       615142                      
-system.ruby.network.routers10.msg_count.Response_Data::4       612906                      
-system.ruby.network.routers10.msg_count.ResponseL2hit_Data::4         1691                      
-system.ruby.network.routers10.msg_count.ResponseLocal_Data::4         1566                      
-system.ruby.network.routers10.msg_count.Response_Control::4         1416                      
-system.ruby.network.routers10.msg_count.Writeback_Data::4       881138                      
-system.ruby.network.routers10.msg_count.Writeback_Control::4       377581                      
-system.ruby.network.routers10.msg_count.Broadcast_Control::1      4317761                      
-system.ruby.network.routers10.msg_count.Persistent_Control::3      2337228                      
-system.ruby.network.routers10.msg_bytes.Request_Control::1      4934584                      
-system.ruby.network.routers10.msg_bytes.Request_Control::2      4921136                      
-system.ruby.network.routers10.msg_bytes.Response_Data::4     44129232                      
-system.ruby.network.routers10.msg_bytes.ResponseL2hit_Data::4       121752                      
-system.ruby.network.routers10.msg_bytes.ResponseLocal_Data::4       112752                      
-system.ruby.network.routers10.msg_bytes.Response_Control::4        11328                      
-system.ruby.network.routers10.msg_bytes.Writeback_Data::4     63441936                      
-system.ruby.network.routers10.msg_bytes.Writeback_Control::4      3020648                      
-system.ruby.network.routers10.msg_bytes.Broadcast_Control::1     34542088                      
-system.ruby.network.routers10.msg_bytes.Persistent_Control::3     18697824                      
-system.ruby.network.msg_count.Request_Control      3695895                      
-system.ruby.network.msg_count.Response_Data      1838719                      
-system.ruby.network.msg_count.ResponseL2hit_Data         5073                      
-system.ruby.network.msg_count.ResponseLocal_Data         4698                      
-system.ruby.network.msg_count.Response_Control         4248                      
-system.ruby.network.msg_count.Writeback_Data      2643414                      
-system.ruby.network.msg_count.Writeback_Control      1132743                      
-system.ruby.network.msg_count.Broadcast_Control      9252345                      
-system.ruby.network.msg_count.Persistent_Control      5193840                      
-system.ruby.network.msg_byte.Request_Control     29567160                      
-system.ruby.network.msg_byte.Response_Data    132387768                      
-system.ruby.network.msg_byte.ResponseL2hit_Data       365256                      
-system.ruby.network.msg_byte.ResponseLocal_Data       338256                      
-system.ruby.network.msg_byte.Response_Control        33984                      
-system.ruby.network.msg_byte.Writeback_Data    190325808                      
-system.ruby.network.msg_byte.Writeback_Control      9061944                      
-system.ruby.network.msg_byte.Broadcast_Control     74018760                      
-system.ruby.network.msg_byte.Persistent_Control     41550720                      
+system.ruby.network.routers09.msg_bytes.Writeback_Data::4     17454096                      
+system.ruby.network.routers09.msg_bytes.Writeback_Control::4      3048296                      
+system.ruby.network.routers09.msg_bytes.Persistent_Control::3      2113584                      
+system.ruby.network.routers10.percent_links_utilized    17.628861                      
+system.ruby.network.routers10.msg_count.Request_Control::1       628051                      
+system.ruby.network.routers10.msg_count.Request_Control::2       626510                      
+system.ruby.network.routers10.msg_count.Response_Data::4       624321                      
+system.ruby.network.routers10.msg_count.ResponseL2hit_Data::4         1545                      
+system.ruby.network.routers10.msg_count.ResponseLocal_Data::4         1530                      
+system.ruby.network.routers10.msg_count.Response_Control::4         1393                      
+system.ruby.network.routers10.msg_count.Writeback_Data::4       900165                      
+system.ruby.network.routers10.msg_count.Writeback_Control::4       381037                      
+system.ruby.network.routers10.msg_count.Broadcast_Control::1      4396357                      
+system.ruby.network.routers10.msg_count.Persistent_Control::3      2377782                      
+system.ruby.network.routers10.msg_bytes.Request_Control::1      5024408                      
+system.ruby.network.routers10.msg_bytes.Request_Control::2      5012080                      
+system.ruby.network.routers10.msg_bytes.Response_Data::4     44951112                      
+system.ruby.network.routers10.msg_bytes.ResponseL2hit_Data::4       111240                      
+system.ruby.network.routers10.msg_bytes.ResponseLocal_Data::4       110160                      
+system.ruby.network.routers10.msg_bytes.Response_Control::4        11144                      
+system.ruby.network.routers10.msg_bytes.Writeback_Data::4     64811880                      
+system.ruby.network.routers10.msg_bytes.Writeback_Control::4      3048296                      
+system.ruby.network.routers10.msg_bytes.Broadcast_Control::1     35170856                      
+system.ruby.network.routers10.msg_bytes.Persistent_Control::3     19022256                      
+system.ruby.network.msg_count.Request_Control      3763684                      
+system.ruby.network.msg_count.Response_Data      1872964                      
+system.ruby.network.msg_count.ResponseL2hit_Data         4635                      
+system.ruby.network.msg_count.ResponseLocal_Data         4590                      
+system.ruby.network.msg_count.Response_Control         4179                      
+system.ruby.network.msg_count.Writeback_Data      2700495                      
+system.ruby.network.msg_count.Writeback_Control      1143111                      
+system.ruby.network.msg_count.Broadcast_Control      9420765                      
+system.ruby.network.msg_count.Persistent_Control      5283960                      
+system.ruby.network.msg_byte.Request_Control     30109472                      
+system.ruby.network.msg_byte.Response_Data    134853408                      
+system.ruby.network.msg_byte.ResponseL2hit_Data       333720                      
+system.ruby.network.msg_byte.ResponseLocal_Data       330480                      
+system.ruby.network.msg_byte.Response_Control        33432                      
+system.ruby.network.msg_byte.Writeback_Data    194435640                      
+system.ruby.network.msg_byte.Writeback_Control      9144888                      
+system.ruby.network.msg_byte.Broadcast_Control     75366120                      
+system.ruby.network.msg_byte.Persistent_Control     42271680                      
 system.funcbus.throughput                           0                       # Throughput (bytes/s)
 system.funcbus.data_through_bus                     0                       # Total data (bytes)
 system.cpu_clk_domain.clock                         1                       # Clock period in ticks
 system.cpu0.num_reads                          100000                       # number of read accesses completed
-system.cpu0.num_writes                          54250                       # number of write accesses completed
+system.cpu0.num_writes                          55570                       # number of write accesses completed
 system.cpu0.num_copies                              0                       # number of copy accesses completed
-system.cpu1.num_reads                           99858                       # number of read accesses completed
-system.cpu1.num_writes                          54337                       # number of write accesses completed
+system.cpu1.num_reads                           99982                       # number of read accesses completed
+system.cpu1.num_writes                          55877                       # number of write accesses completed
 system.cpu1.num_copies                              0                       # number of copy accesses completed
-system.cpu2.num_reads                           99660                       # number of read accesses completed
-system.cpu2.num_writes                          53758                       # number of write accesses completed
+system.cpu2.num_reads                           99439                       # number of read accesses completed
+system.cpu2.num_writes                          55577                       # number of write accesses completed
 system.cpu2.num_copies                              0                       # number of copy accesses completed
-system.cpu3.num_reads                           99997                       # number of read accesses completed
-system.cpu3.num_writes                          53569                       # number of write accesses completed
+system.cpu3.num_reads                           99038                       # number of read accesses completed
+system.cpu3.num_writes                          55261                       # number of write accesses completed
 system.cpu3.num_copies                              0                       # number of copy accesses completed
-system.cpu4.num_reads                           99232                       # number of read accesses completed
-system.cpu4.num_writes                          53727                       # number of write accesses completed
+system.cpu4.num_reads                           99740                       # number of read accesses completed
+system.cpu4.num_writes                          55487                       # number of write accesses completed
 system.cpu4.num_copies                              0                       # number of copy accesses completed
-system.cpu5.num_reads                           99852                       # number of read accesses completed
-system.cpu5.num_writes                          54401                       # number of write accesses completed
+system.cpu5.num_reads                           99865                       # number of read accesses completed
+system.cpu5.num_writes                          55475                       # number of write accesses completed
 system.cpu5.num_copies                              0                       # number of copy accesses completed
-system.cpu6.num_reads                           99007                       # number of read accesses completed
-system.cpu6.num_writes                          53961                       # number of write accesses completed
+system.cpu6.num_reads                           99179                       # number of read accesses completed
+system.cpu6.num_writes                          55288                       # number of write accesses completed
 system.cpu6.num_copies                              0                       # number of copy accesses completed
-system.cpu7.num_reads                           99727                       # number of read accesses completed
-system.cpu7.num_writes                          53437                       # number of write accesses completed
+system.cpu7.num_reads                           99432                       # number of read accesses completed
+system.cpu7.num_writes                          55258                       # number of write accesses completed
 system.cpu7.num_copies                              0                       # number of copy accesses completed
-system.ruby.network.routers00.throttle0.link_utilization    12.440008                      
-system.ruby.network.routers00.throttle0.msg_count.Response_Data::4        76833                      
-system.ruby.network.routers00.throttle0.msg_count.ResponseL2hit_Data::4          229                      
-system.ruby.network.routers00.throttle0.msg_count.ResponseLocal_Data::4          190                      
-system.ruby.network.routers00.throttle0.msg_count.Response_Control::4            2                      
-system.ruby.network.routers00.throttle0.msg_count.Writeback_Data::4         3997                      
-system.ruby.network.routers00.throttle0.msg_count.Broadcast_Control::1       539556                      
-system.ruby.network.routers00.throttle0.msg_count.Persistent_Control::3       259692                      
-system.ruby.network.routers00.throttle0.msg_bytes.Response_Data::4      5531976                      
-system.ruby.network.routers00.throttle0.msg_bytes.ResponseL2hit_Data::4        16488                      
-system.ruby.network.routers00.throttle0.msg_bytes.ResponseLocal_Data::4        13680                      
-system.ruby.network.routers00.throttle0.msg_bytes.Response_Control::4           16                      
-system.ruby.network.routers00.throttle0.msg_bytes.Writeback_Data::4       287784                      
-system.ruby.network.routers00.throttle0.msg_bytes.Broadcast_Control::1      4316448                      
-system.ruby.network.routers00.throttle0.msg_bytes.Persistent_Control::3      2077536                      
-system.ruby.network.routers00.throttle1.link_utilization     7.472574                      
-system.ruby.network.routers00.throttle1.msg_count.Request_Control::1        77267                      
-system.ruby.network.routers00.throttle1.msg_count.Response_Data::4           90                      
-system.ruby.network.routers00.throttle1.msg_count.ResponseL2hit_Data::4            2                      
-system.ruby.network.routers00.throttle1.msg_count.ResponseLocal_Data::4          209                      
-system.ruby.network.routers00.throttle1.msg_count.Response_Control::4          186                      
-system.ruby.network.routers00.throttle1.msg_count.Writeback_Data::4        81056                      
-system.ruby.network.routers00.throttle1.msg_count.Broadcast_Control::1        77267                      
-system.ruby.network.routers00.throttle1.msg_count.Persistent_Control::3        32414                      
-system.ruby.network.routers00.throttle1.msg_bytes.Request_Control::1       618136                      
-system.ruby.network.routers00.throttle1.msg_bytes.Response_Data::4         6480                      
-system.ruby.network.routers00.throttle1.msg_bytes.ResponseL2hit_Data::4          144                      
-system.ruby.network.routers00.throttle1.msg_bytes.ResponseLocal_Data::4        15048                      
-system.ruby.network.routers00.throttle1.msg_bytes.Response_Control::4         1488                      
-system.ruby.network.routers00.throttle1.msg_bytes.Writeback_Data::4      5836032                      
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 system.ruby.LD.latency_hist::max_bucket          5119                      
-system.ruby.LD.latency_hist::samples           401150                      
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-system.ruby.LD.latency_hist::stdev         880.306835                      
-system.ruby.LD.latency_hist              |      114447     28.53%     28.53% |       69647     17.36%     45.89% |       58610     14.61%     60.50% |       63948     15.94%     76.44% |       59270     14.78%     91.22% |       27867      6.95%     98.17% |        6198      1.55%     99.71% |        1034      0.26%     99.97% |         109      0.03%    100.00% |          20      0.00%    100.00%
-system.ruby.LD.latency_hist::total             401150                      
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+system.ruby.LD.latency_hist              |      114672     28.34%     28.34% |       70346     17.39%     45.73% |       59895     14.80%     60.53% |       62905     15.55%     76.08% |       60348     14.92%     91.00% |       28706      7.10%     98.09% |        6783      1.68%     99.77% |         841      0.21%     99.98% |          80      0.02%    100.00% |          11      0.00%    100.00%
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 system.ruby.LD.hit_latency_hist::bucket_size          512                      
 system.ruby.LD.hit_latency_hist::max_bucket         5119                      
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-system.ruby.LD.hit_latency_hist::gmean     607.027231                      
-system.ruby.LD.hit_latency_hist::stdev     920.547274                      
-system.ruby.LD.hit_latency_hist          |         761     32.73%     32.73% |         367     15.78%     48.52% |         331     14.24%     62.75% |         343     14.75%     77.51% |         308     13.25%     90.75% |         177      7.61%     98.37% |          31      1.33%     99.70% |           6      0.26%     99.96% |           1      0.04%    100.00% |           0      0.00%    100.00%
-system.ruby.LD.hit_latency_hist::total           2325                      
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+system.ruby.LD.hit_latency_hist          |         747     33.08%     33.08% |         381     16.87%     49.96% |         319     14.13%     64.08% |         286     12.67%     76.75% |         325     14.39%     91.14% |         151      6.69%     97.83% |          42      1.86%     99.69% |           6      0.27%     99.96% |           1      0.04%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.hit_latency_hist::total           2258                      
 system.ruby.LD.miss_latency_hist::bucket_size          512                      
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-system.ruby.LD.miss_latency_hist::gmean    908.133083                      
-system.ruby.LD.miss_latency_hist::stdev    880.051843                      
-system.ruby.LD.miss_latency_hist         |      113686     28.51%     28.51% |       69280     17.37%     45.88% |       58279     14.61%     60.49% |       63605     15.95%     76.44% |       58962     14.78%     91.22% |       27690      6.94%     98.16% |        6167      1.55%     99.71% |        1028      0.26%     99.97% |         108      0.03%     99.99% |          20      0.01%    100.00%
-system.ruby.LD.miss_latency_hist::total        398825                      
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-system.ruby.ST.latency_hist::stdev         879.213376                      
-system.ruby.ST.latency_hist              |       99268     46.00%     46.00% |       65849     30.51%     76.51% |       46789     21.68%     98.19% |        3842      1.78%     99.97% |          68      0.03%    100.00% |           1      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.ST.latency_hist::total             215817                      
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-system.ruby.ST.hit_latency_hist::stdev     897.966582                      
-system.ruby.ST.hit_latency_hist          |         412     32.70%     32.70% |         203     16.11%     48.81% |         188     14.92%     63.73% |         203     16.11%     79.84% |         145     11.51%     91.35% |          82      6.51%     97.86% |          25      1.98%     99.84% |           2      0.16%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.ST.hit_latency_hist::total           1260                      
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-system.ruby.ST.miss_latency_hist         |       98653     45.98%     45.98% |       65458     30.51%     76.49% |       46562     21.70%     98.19% |        3815      1.78%     99.97% |          68      0.03%    100.00% |           1      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
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 system.ruby.L1Cache.hit_mach_latency_hist::bucket_size            1                      
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 system.ruby.L1Cache.hit_mach_latency_hist::gmean     2.000000                      
-system.ruby.L1Cache.hit_mach_latency_hist |           0      0.00%      0.00% |           0      0.00%      0.00% |         165    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
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+system.ruby.L1Cache.hit_mach_latency_hist |           0      0.00%      0.00% |           0      0.00%      0.00% |         207    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
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-system.ruby.L1Cache.miss_mach_latency_hist |         782     30.51%     30.51% |         487     19.00%     49.51% |         387     15.10%     64.61% |         376     14.67%     79.28% |         340     13.27%     92.55% |         158      6.16%     98.71% |          29      1.13%     99.84% |           3      0.12%     99.96% |           1      0.04%    100.00% |           0      0.00%    100.00%
-system.ruby.L1Cache.miss_mach_latency_hist::total         2563                      
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+system.ruby.L1Cache.miss_mach_latency_hist |         755     29.91%     29.91% |         443     17.55%     47.46% |         398     15.77%     63.23% |         388     15.37%     78.61% |         337     13.35%     91.96% |         163      6.46%     98.42% |          35      1.39%     99.80% |           5      0.20%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
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-system.ruby.L2Cache.hit_mach_latency_hist::stdev   894.645782                      
-system.ruby.L2Cache.hit_mach_latency_hist |        1008     29.47%     29.47% |         570     16.67%     46.14% |         519     15.18%     61.32% |         546     15.96%     77.28% |         453     13.25%     90.53% |         259      7.57%     98.10% |          56      1.64%     99.74% |           8      0.23%     99.97% |           1      0.03%    100.00% |           0      0.00%    100.00%
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-system.ruby.Directory.miss_mach_latency_hist::stdev   879.729106                      
-system.ruby.Directory.miss_mach_latency_hist |      280350     45.90%     45.90% |      186579     30.55%     76.44% |      132716     21.73%     98.17% |       10978      1.80%     99.97% |         195      0.03%    100.00% |           1      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.Directory.miss_mach_latency_hist::total       610819                      
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+system.ruby.L2Cache.hit_mach_latency_hist::stdev   901.668484                      
+system.ruby.L2Cache.hit_mach_latency_hist |         936     28.54%     28.54% |         594     18.11%     46.65% |         495     15.09%     61.74% |         467     14.24%     75.98% |         486     14.82%     90.79% |         230      7.01%     97.80% |          60      1.83%     99.63% |          11      0.34%     99.97% |           1      0.03%    100.00% |           0      0.00%    100.00%
+system.ruby.L2Cache.hit_mach_latency_hist::total         3280                      
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+system.ruby.Directory.miss_mach_latency_hist |      176341     28.34%     28.34% |      108467     17.43%     45.77% |       92019     14.79%     60.56% |       96759     15.55%     76.11% |       92527     14.87%     90.98% |       44240      7.11%     98.09% |       10470      1.68%     99.77% |        1271      0.20%     99.98% |         120      0.02%    100.00% |          14      0.00%    100.00%
+system.ruby.Directory.miss_mach_latency_hist::total       622228                      
 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size            1                      
 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::max_bucket            9                      
-system.ruby.Directory.miss_latency_hist.issue_to_initial_request::samples            7                      
-system.ruby.Directory.miss_latency_hist.issue_to_initial_request |           7    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.Directory.miss_latency_hist.issue_to_initial_request::total            7                      
+system.ruby.Directory.miss_latency_hist.issue_to_initial_request::samples            4                      
+system.ruby.Directory.miss_latency_hist.issue_to_initial_request |           4    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.Directory.miss_latency_hist.issue_to_initial_request::total            4                      
 system.ruby.Directory.miss_latency_hist.initial_to_forward::bucket_size            1                      
 system.ruby.Directory.miss_latency_hist.initial_to_forward::max_bucket            9                      
-system.ruby.Directory.miss_latency_hist.initial_to_forward::samples            7                      
-system.ruby.Directory.miss_latency_hist.initial_to_forward |           7    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.Directory.miss_latency_hist.initial_to_forward::total            7                      
+system.ruby.Directory.miss_latency_hist.initial_to_forward::samples            4                      
+system.ruby.Directory.miss_latency_hist.initial_to_forward |           4    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.Directory.miss_latency_hist.initial_to_forward::total            4                      
 system.ruby.Directory.miss_latency_hist.forward_to_first_response::bucket_size            1                      
 system.ruby.Directory.miss_latency_hist.forward_to_first_response::max_bucket            9                      
-system.ruby.Directory.miss_latency_hist.forward_to_first_response::samples            7                      
-system.ruby.Directory.miss_latency_hist.forward_to_first_response |           7    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.Directory.miss_latency_hist.forward_to_first_response::total            7                      
-system.ruby.Directory.miss_latency_hist.first_response_to_completion::bucket_size           32                      
-system.ruby.Directory.miss_latency_hist.first_response_to_completion::max_bucket          319                      
-system.ruby.Directory.miss_latency_hist.first_response_to_completion::samples            7                      
-system.ruby.Directory.miss_latency_hist.first_response_to_completion::mean   122.714286                      
-system.ruby.Directory.miss_latency_hist.first_response_to_completion::gmean   113.915443                      
-system.ruby.Directory.miss_latency_hist.first_response_to_completion::stdev    50.582323                      
-system.ruby.Directory.miss_latency_hist.first_response_to_completion |           0      0.00%      0.00% |           0      0.00%      0.00% |           4     57.14%     57.14% |           0      0.00%     57.14% |           0      0.00%     57.14% |           3     42.86%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.Directory.miss_latency_hist.first_response_to_completion::total            7                      
+system.ruby.Directory.miss_latency_hist.forward_to_first_response::samples            4                      
+system.ruby.Directory.miss_latency_hist.forward_to_first_response |           4    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.Directory.miss_latency_hist.forward_to_first_response::total            4                      
+system.ruby.Directory.miss_latency_hist.first_response_to_completion::bucket_size           16                      
+system.ruby.Directory.miss_latency_hist.first_response_to_completion::max_bucket          159                      
+system.ruby.Directory.miss_latency_hist.first_response_to_completion::samples            4                      
+system.ruby.Directory.miss_latency_hist.first_response_to_completion::mean    84.250000                      
+system.ruby.Directory.miss_latency_hist.first_response_to_completion::gmean    83.040125                      
+system.ruby.Directory.miss_latency_hist.first_response_to_completion::stdev    17.211914                      
+system.ruby.Directory.miss_latency_hist.first_response_to_completion |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           2     50.00%     50.00% |           1     25.00%     75.00% |           1     25.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.Directory.miss_latency_hist.first_response_to_completion::total            4                      
 system.ruby.LD.L1Cache.hit_type_mach_latency_hist::bucket_size            1                      
 system.ruby.LD.L1Cache.hit_type_mach_latency_hist::max_bucket            9                      
-system.ruby.LD.L1Cache.hit_type_mach_latency_hist::samples          112                      
+system.ruby.LD.L1Cache.hit_type_mach_latency_hist::samples          139                      
 system.ruby.LD.L1Cache.hit_type_mach_latency_hist::mean            2                      
 system.ruby.LD.L1Cache.hit_type_mach_latency_hist::gmean            2                      
-system.ruby.LD.L1Cache.hit_type_mach_latency_hist |           0      0.00%      0.00% |           0      0.00%      0.00% |         112    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.LD.L1Cache.hit_type_mach_latency_hist::total          112                      
+system.ruby.LD.L1Cache.hit_type_mach_latency_hist |           0      0.00%      0.00% |           0      0.00%      0.00% |         139    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.L1Cache.hit_type_mach_latency_hist::total          139                      
 system.ruby.LD.L1Cache.miss_type_mach_latency_hist::bucket_size          512                      
 system.ruby.LD.L1Cache.miss_type_mach_latency_hist::max_bucket         5119                      
-system.ruby.LD.L1Cache.miss_type_mach_latency_hist::samples         1608                      
-system.ruby.LD.L1Cache.miss_type_mach_latency_hist::mean  1188.308458                      
-system.ruby.LD.L1Cache.miss_type_mach_latency_hist::gmean   741.622065                      
-system.ruby.LD.L1Cache.miss_type_mach_latency_hist::stdev   867.195204                      
-system.ruby.LD.L1Cache.miss_type_mach_latency_hist |         500     31.09%     31.09% |         292     18.16%     49.25% |         245     15.24%     64.49% |         245     15.24%     79.73% |         206     12.81%     92.54% |          98      6.09%     98.63% |          20      1.24%     99.88% |           2      0.12%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.LD.L1Cache.miss_type_mach_latency_hist::total         1608                      
+system.ruby.LD.L1Cache.miss_type_mach_latency_hist::samples         1645                      
+system.ruby.LD.L1Cache.miss_type_mach_latency_hist::mean  1213.688754                      
+system.ruby.LD.L1Cache.miss_type_mach_latency_hist::gmean   768.636375                      
+system.ruby.LD.L1Cache.miss_type_mach_latency_hist::stdev   877.770074                      
+system.ruby.LD.L1Cache.miss_type_mach_latency_hist |         498     30.27%     30.27% |         276     16.78%     47.05% |         273     16.60%     63.65% |         252     15.32%     78.97% |         220     13.37%     92.34% |          99      6.02%     98.36% |          23      1.40%     99.76% |           4      0.24%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.L1Cache.miss_type_mach_latency_hist::total         1645                      
 system.ruby.LD.L2Cache.hit_type_mach_latency_hist::bucket_size          512                      
 system.ruby.LD.L2Cache.hit_type_mach_latency_hist::max_bucket         5119                      
-system.ruby.LD.L2Cache.hit_type_mach_latency_hist::samples         2213                      
-system.ruby.LD.L2Cache.hit_type_mach_latency_hist::mean  1267.732038                      
-system.ruby.LD.L2Cache.hit_type_mach_latency_hist::gmean   810.646085                      
-system.ruby.LD.L2Cache.hit_type_mach_latency_hist::stdev   901.722652                      
-system.ruby.LD.L2Cache.hit_type_mach_latency_hist |         649     29.33%     29.33% |         367     16.58%     45.91% |         331     14.96%     60.87% |         343     15.50%     76.37% |         308     13.92%     90.28% |         177      8.00%     98.28% |          31      1.40%     99.68% |           6      0.27%     99.95% |           1      0.05%    100.00% |           0      0.00%    100.00%
-system.ruby.LD.L2Cache.hit_type_mach_latency_hist::total         2213                      
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+system.ruby.LD.L2Cache.hit_type_mach_latency_hist::gmean   817.259797                      
+system.ruby.LD.L2Cache.hit_type_mach_latency_hist::stdev   906.345230                      
+system.ruby.LD.L2Cache.hit_type_mach_latency_hist |         608     28.69%     28.69% |         381     17.98%     46.67% |         319     15.05%     61.73% |         286     13.50%     75.22% |         325     15.34%     90.56% |         151      7.13%     97.69% |          42      1.98%     99.67% |           6      0.28%     99.95% |           1      0.05%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.L2Cache.hit_type_mach_latency_hist::total         2119                      
 system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size          512                      
 system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket         5119                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist::samples       397217                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist::mean  1277.296166                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean   908.878022                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev   880.086444                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist |      113186     28.49%     28.49% |       68988     17.37%     45.86% |       58034     14.61%     60.47% |       63360     15.95%     76.42% |       58756     14.79%     91.22% |       27592      6.95%     98.16% |        6147      1.55%     99.71% |        1026      0.26%     99.97% |         108      0.03%     99.99% |          20      0.01%    100.00%
-system.ruby.LD.Directory.miss_type_mach_latency_hist::total       397217                      
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+system.ruby.LD.Directory.miss_type_mach_latency_hist::mean  1282.297551                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean   914.805796                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev   881.552049                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist |      113427     28.31%     28.31% |       69689     17.39%     45.70% |       59303     14.80%     60.50% |       62367     15.57%     76.07% |       59803     14.93%     90.99% |       28456      7.10%     98.09% |        6718      1.68%     99.77% |         831      0.21%     99.98% |          79      0.02%    100.00% |          11      0.00%    100.00%
+system.ruby.LD.Directory.miss_type_mach_latency_hist::total       400684                      
 system.ruby.ST.L1Cache.hit_type_mach_latency_hist::bucket_size            1                      
 system.ruby.ST.L1Cache.hit_type_mach_latency_hist::max_bucket            9                      
-system.ruby.ST.L1Cache.hit_type_mach_latency_hist::samples           53                      
+system.ruby.ST.L1Cache.hit_type_mach_latency_hist::samples           68                      
 system.ruby.ST.L1Cache.hit_type_mach_latency_hist::mean            2                      
-system.ruby.ST.L1Cache.hit_type_mach_latency_hist::gmean            2                      
-system.ruby.ST.L1Cache.hit_type_mach_latency_hist |           0      0.00%      0.00% |           0      0.00%      0.00% |          53    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.ST.L1Cache.hit_type_mach_latency_hist::total           53                      
+system.ruby.ST.L1Cache.hit_type_mach_latency_hist::gmean     2.000000                      
+system.ruby.ST.L1Cache.hit_type_mach_latency_hist |           0      0.00%      0.00% |           0      0.00%      0.00% |          68    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.L1Cache.hit_type_mach_latency_hist::total           68                      
 system.ruby.ST.L1Cache.miss_type_mach_latency_hist::bucket_size          512                      
 system.ruby.ST.L1Cache.miss_type_mach_latency_hist::max_bucket         5119                      
-system.ruby.ST.L1Cache.miss_type_mach_latency_hist::samples          955                      
-system.ruby.ST.L1Cache.miss_type_mach_latency_hist::mean  1192.065969                      
-system.ruby.ST.L1Cache.miss_type_mach_latency_hist::gmean   742.089221                      
-system.ruby.ST.L1Cache.miss_type_mach_latency_hist::stdev   878.516392                      
-system.ruby.ST.L1Cache.miss_type_mach_latency_hist |         282     29.53%     29.53% |         195     20.42%     49.95% |         142     14.87%     64.82% |         131     13.72%     78.53% |         134     14.03%     92.57% |          60      6.28%     98.85% |           9      0.94%     99.79% |           1      0.10%     99.90% |           1      0.10%    100.00% |           0      0.00%    100.00%
-system.ruby.ST.L1Cache.miss_type_mach_latency_hist::total          955                      
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+system.ruby.ST.L1Cache.miss_type_mach_latency_hist::stdev   883.472744                      
+system.ruby.ST.L1Cache.miss_type_mach_latency_hist |         257     29.24%     29.24% |         167     19.00%     48.24% |         125     14.22%     62.46% |         136     15.47%     77.93% |         117     13.31%     91.24% |          64      7.28%     98.52% |          12      1.37%     99.89% |           1      0.11%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.L1Cache.miss_type_mach_latency_hist::total          879                      
 system.ruby.ST.L2Cache.hit_type_mach_latency_hist::bucket_size          512                      
 system.ruby.ST.L2Cache.hit_type_mach_latency_hist::max_bucket         5119                      
-system.ruby.ST.L2Cache.hit_type_mach_latency_hist::samples         1207                      
-system.ruby.ST.L2Cache.hit_type_mach_latency_hist::mean  1240.135046                      
-system.ruby.ST.L2Cache.hit_type_mach_latency_hist::gmean   818.530124                      
-system.ruby.ST.L2Cache.hit_type_mach_latency_hist::stdev   881.614674                      
-system.ruby.ST.L2Cache.hit_type_mach_latency_hist |         359     29.74%     29.74% |         203     16.82%     46.56% |         188     15.58%     62.14% |         203     16.82%     78.96% |         145     12.01%     90.97% |          82      6.79%     97.76% |          25      2.07%     99.83% |           2      0.17%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.ST.L2Cache.hit_type_mach_latency_hist::total         1207                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size         1024                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket        10239                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist::samples       213602                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist::mean  1275.911349                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean   908.975529                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev   879.065559                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist |       98176     45.96%     45.96% |       65185     30.52%     76.48% |       46368     21.71%     98.19% |        3805      1.78%     99.97% |          67      0.03%    100.00% |           1      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.ST.Directory.miss_type_mach_latency_hist::total       213602                      
-system.ruby.L1Cache_Controller.Load      |       50331     12.55%     12.55% |       49967     12.46%     25.00% |       50254     12.53%     37.53% |       50183     12.51%     50.04% |       50017     12.47%     62.51% |       50259     12.53%     75.03% |       50136     12.50%     87.53% |       50016     12.47%    100.00%
-system.ruby.L1Cache_Controller.Load::total       401163                      
-system.ruby.L1Cache_Controller.Store     |       26960     12.49%     12.49% |       27312     12.65%     25.15% |       26841     12.44%     37.58% |       26622     12.33%     49.92% |       26950     12.49%     62.40% |       27007     12.51%     74.92% |       27203     12.60%     87.52% |       26930     12.48%    100.00%
-system.ruby.L1Cache_Controller.Store::total       215825                      
-system.ruby.L1Cache_Controller.L1_Replacement |     1368057     12.53%     12.53% |     1367643     12.53%     25.06% |     1363908     12.49%     37.56% |     1358410     12.44%     50.00% |     1362554     12.48%     62.48% |     1365525     12.51%     74.99% |     1369124     12.54%     87.53% |     1360777     12.47%    100.00%
-system.ruby.L1Cache_Controller.L1_Replacement::total     10915998                      
-system.ruby.L1Cache_Controller.Data_Shared |         236     13.02%     13.02% |         219     12.09%     25.11% |         237     13.08%     38.19% |         210     11.59%     49.78% |         242     13.36%     63.13% |         233     12.86%     75.99% |         202     11.15%     87.14% |         233     12.86%    100.00%
-system.ruby.L1Cache_Controller.Data_Shared::total         1812                      
-system.ruby.L1Cache_Controller.Data_Owner |          73     15.24%     15.24% |          74     15.45%     30.69% |          52     10.86%     41.54% |          50     10.44%     51.98% |          71     14.82%     66.81% |          66     13.78%     80.58% |          41      8.56%     89.14% |          52     10.86%    100.00%
-system.ruby.L1Cache_Controller.Data_Owner::total          479                      
-system.ruby.L1Cache_Controller.Data_All_Tokens |       80940     12.55%     12.55% |       80743     12.52%     25.06% |       80630     12.50%     37.56% |       80297     12.45%     50.01% |       80401     12.46%     62.47% |       80744     12.52%     74.99% |       80888     12.54%     87.53% |       80464     12.47%    100.00%
-system.ruby.L1Cache_Controller.Data_All_Tokens::total       645107                      
-system.ruby.L1Cache_Controller.Ack       |           1      7.14%      7.14% |           0      0.00%      7.14% |           3     21.43%     28.57% |           0      0.00%     28.57% |           3     21.43%     50.00% |           2     14.29%     64.29% |           4     28.57%     92.86% |           1      7.14%    100.00%
-system.ruby.L1Cache_Controller.Ack::total           14                      
-system.ruby.L1Cache_Controller.Ack_All_Tokens |           1     20.00%     20.00% |           1     20.00%     40.00% |           0      0.00%     40.00% |           1     20.00%     60.00% |           1     20.00%     80.00% |           0      0.00%     80.00% |           0      0.00%     80.00% |           1     20.00%    100.00%
-system.ruby.L1Cache_Controller.Ack_All_Tokens::total            5                      
-system.ruby.L1Cache_Controller.Transient_Local_GETX |      188823     12.50%     12.50% |      188465     12.48%     24.98% |      188937     12.51%     37.49% |      189155     12.52%     50.01% |      188828     12.50%     62.51% |      188776     12.50%     75.01% |      188573     12.48%     87.50% |      188847     12.50%    100.00%
-system.ruby.L1Cache_Controller.Transient_Local_GETX::total      1510404                      
-system.ruby.L1Cache_Controller.Transient_Local_GETS |      350731     12.49%     12.49% |      351096     12.51%     25.00% |      350807     12.50%     37.50% |      350881     12.50%     49.99% |      351048     12.50%     62.50% |      350805     12.50%     74.99% |      350930     12.50%     87.50% |      351050     12.50%    100.00%
-system.ruby.L1Cache_Controller.Transient_Local_GETS::total      2807348                      
-system.ruby.L1Cache_Controller.Transient_Local_GETS_Last_Token |           2     22.22%     22.22% |           0      0.00%     22.22% |           1     11.11%     33.33% |           4     44.44%     77.78% |           0      0.00%     77.78% |           1     11.11%     88.89% |           0      0.00%     88.89% |           1     11.11%    100.00%
-system.ruby.L1Cache_Controller.Transient_Local_GETS_Last_Token::total            9                      
-system.ruby.L1Cache_Controller.Persistent_GETX |       40243     12.48%     12.48% |       40235     12.48%     24.97% |       40237     12.48%     37.45% |       40452     12.55%     50.00% |       40236     12.48%     62.48% |       40319     12.51%     74.99% |       40323     12.51%     87.50% |       40294     12.50%    100.00%
-system.ruby.L1Cache_Controller.Persistent_GETX::total       322339                      
-system.ruby.L1Cache_Controller.Persistent_GETS |       74022     12.51%     12.51% |       73973     12.50%     25.00% |       73853     12.48%     37.48% |       73992     12.50%     49.98% |       74071     12.51%     62.50% |       73914     12.49%     74.99% |       74014     12.51%     87.49% |       74024     12.51%    100.00%
-system.ruby.L1Cache_Controller.Persistent_GETS::total       591863                      
-system.ruby.L1Cache_Controller.Persistent_GETS_Last_Token |           0      0.00%      0.00% |           0      0.00%      0.00% |           1     33.33%     33.33% |           1     33.33%     66.67% |           1     33.33%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.L1Cache_Controller.Persistent_GETS_Last_Token::total            3                      
-system.ruby.L1Cache_Controller.Own_Lock_or_Unlock |      145427     12.50%     12.50% |      145484     12.51%     25.01% |      145601     12.52%     37.52% |      145247     12.49%     50.01% |      145384     12.50%     62.51% |      145459     12.50%     75.01% |      145355     12.49%     87.50% |      145374     12.50%    100.00%
-system.ruby.L1Cache_Controller.Own_Lock_or_Unlock::total      1163331                      
-system.ruby.L1Cache_Controller.Request_Timeout |       60159     12.52%     12.52% |       59656     12.41%     24.93% |       60277     12.54%     37.47% |       60879     12.67%     50.14% |       60010     12.49%     62.63% |       60642     12.62%     75.24% |       60033     12.49%     87.74% |       58941     12.26%    100.00%
-system.ruby.L1Cache_Controller.Request_Timeout::total       480597                      
-system.ruby.L1Cache_Controller.Use_TimeoutStarverX |           5      5.62%      5.62% |           4      4.49%     10.11% |          12     13.48%     23.60% |          11     12.36%     35.96% |          13     14.61%     50.56% |          10     11.24%     61.80% |          18     20.22%     82.02% |          16     17.98%    100.00%
-system.ruby.L1Cache_Controller.Use_TimeoutStarverX::total           89                      
-system.ruby.L1Cache_Controller.Use_TimeoutStarverS |           6      4.35%      4.35% |          15     10.87%     15.22% |          16     11.59%     26.81% |          13      9.42%     36.23% |          14     10.14%     46.38% |          25     18.12%     64.49% |          24     17.39%     81.88% |          25     18.12%    100.00%
-system.ruby.L1Cache_Controller.Use_TimeoutStarverS::total          138                      
-system.ruby.L1Cache_Controller.Use_TimeoutNoStarvers |       76982     12.53%     12.53% |       76971     12.53%     25.05% |       76777     12.49%     37.55% |       76512     12.45%     50.00% |       76634     12.47%     62.47% |       76926     12.52%     74.99% |       77048     12.54%     87.53% |       76616     12.47%    100.00%
-system.ruby.L1Cache_Controller.Use_TimeoutNoStarvers::total       614466                      
-system.ruby.L1Cache_Controller.NP.Load   |       50234     12.54%     12.54% |       49878     12.46%     25.00% |       50162     12.53%     37.53% |       50102     12.51%     50.04% |       49920     12.47%     62.51% |       50179     12.53%     75.04% |       50054     12.50%     87.54% |       49912     12.46%    100.00%
-system.ruby.L1Cache_Controller.NP.Load::total       400441                      
-system.ruby.L1Cache_Controller.NP.Store  |       26908     12.49%     12.49% |       27274     12.66%     25.15% |       26779     12.43%     37.57% |       26582     12.34%     49.91% |       26907     12.49%     62.40% |       26962     12.51%     74.91% |       27158     12.60%     87.52% |       26896     12.48%    100.00%
-system.ruby.L1Cache_Controller.NP.Store::total       215466                      
-system.ruby.L1Cache_Controller.NP.Data_Shared |          15     25.42%     25.42% |           7     11.86%     37.29% |           5      8.47%     45.76% |           4      6.78%     52.54% |          11     18.64%     71.19% |           6     10.17%     81.36% |           6     10.17%     91.53% |           5      8.47%    100.00%
-system.ruby.L1Cache_Controller.NP.Data_Shared::total           59                      
-system.ruby.L1Cache_Controller.NP.Data_Owner |          21     18.26%     18.26% |          15     13.04%     31.30% |          12     10.43%     41.74% |          10      8.70%     50.43% |          18     15.65%     66.09% |          16     13.91%     80.00% |          11      9.57%     89.57% |          12     10.43%    100.00%
-system.ruby.L1Cache_Controller.NP.Data_Owner::total          115                      
-system.ruby.L1Cache_Controller.NP.Data_All_Tokens |        3905     12.91%     12.91% |        3708     12.26%     25.17% |        3801     12.57%     37.73% |        3744     12.38%     50.11% |        3722     12.30%     62.42% |        3775     12.48%     74.90% |        3791     12.53%     87.43% |        3803     12.57%    100.00%
-system.ruby.L1Cache_Controller.NP.Data_All_Tokens::total        30249                      
-system.ruby.L1Cache_Controller.NP.Ack    |           0      0.00%      0.00% |           0      0.00%      0.00% |           1     50.00%     50.00% |           0      0.00%     50.00% |           0      0.00%     50.00% |           0      0.00%     50.00% |           1     50.00%    100.00% |           0      0.00%    100.00%
-system.ruby.L1Cache_Controller.NP.Ack::total            2                      
-system.ruby.L1Cache_Controller.NP.Transient_Local_GETX |      188213     12.50%     12.50% |      187862     12.48%     24.98% |      188356     12.51%     37.49% |      188542     12.52%     50.01% |      188229     12.50%     62.52% |      188157     12.50%     75.01% |      187989     12.49%     87.50% |      188206     12.50%    100.00%
-system.ruby.L1Cache_Controller.NP.Transient_Local_GETX::total      1505554                      
-system.ruby.L1Cache_Controller.NP.Transient_Local_GETS |      349628     12.49%     12.49% |      349983     12.51%     25.00% |      349669     12.50%     37.50% |      349728     12.50%     49.99% |      349922     12.50%     62.50% |      349655     12.50%     74.99% |      349776     12.50%     87.49% |      349964     12.51%    100.00%
-system.ruby.L1Cache_Controller.NP.Transient_Local_GETS::total      2798325                      
-system.ruby.L1Cache_Controller.NP.Own_Lock_or_Unlock |      126885     12.50%     12.50% |      126871     12.50%     25.00% |      126751     12.49%     37.48% |      126905     12.50%     49.99% |      126881     12.50%     62.49% |      126869     12.50%     74.98% |      126992     12.51%     87.49% |      126955     12.51%    100.00%
-system.ruby.L1Cache_Controller.NP.Own_Lock_or_Unlock::total      1015109                      
-system.ruby.L1Cache_Controller.I.Load    |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           1    100.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.L2Cache.hit_type_mach_latency_hist::samples         1161                      
+system.ruby.ST.L2Cache.hit_type_mach_latency_hist::mean  1254.556417                      
+system.ruby.ST.L2Cache.hit_type_mach_latency_hist::gmean   808.800824                      
+system.ruby.ST.L2Cache.hit_type_mach_latency_hist::stdev   893.416755                      
+system.ruby.ST.L2Cache.hit_type_mach_latency_hist |         328     28.25%     28.25% |         213     18.35%     46.60% |         176     15.16%     61.76% |         181     15.59%     77.35% |         161     13.87%     91.21% |          79      6.80%     98.02% |          18      1.55%     99.57% |           5      0.43%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.L2Cache.hit_type_mach_latency_hist::total         1161                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size          512                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket         5119                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist::samples       221544                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist::mean  1279.003724                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean   911.136653                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev   881.797207                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist |       62914     28.40%     28.40% |       38778     17.50%     45.90% |       32716     14.77%     60.67% |       34392     15.52%     76.19% |       32724     14.77%     90.96% |       15784      7.12%     98.09% |        3752      1.69%     99.78% |         440      0.20%     99.98% |          41      0.02%    100.00% |           3      0.00%    100.00%
+system.ruby.ST.Directory.miss_type_mach_latency_hist::total       221544                      
+system.ruby.L1Cache_Controller.Load      |       50657     12.52%     12.52% |       50729     12.54%     25.06% |       50452     12.47%     37.53% |       50277     12.43%     49.95% |       50756     12.54%     62.50% |       50740     12.54%     75.04% |       50491     12.48%     87.52% |       50498     12.48%    100.00%
+system.ruby.L1Cache_Controller.Load::total       404600                      
+system.ruby.L1Cache_Controller.Store     |       27739     12.40%     12.40% |       28193     12.61%     25.01% |       27912     12.48%     37.49% |       28134     12.58%     50.07% |       28013     12.52%     62.59% |       27879     12.46%     75.06% |       27895     12.47%     87.53% |       27894     12.47%    100.00%
+system.ruby.L1Cache_Controller.Store::total       223659                      
+system.ruby.L1Cache_Controller.L1_Replacement |     1387935     12.49%     12.49% |     1393411     12.54%     25.03% |     1386651     12.48%     37.51% |     1386696     12.48%     49.99% |     1393529     12.54%     62.54% |     1389740     12.51%     75.04% |     1385760     12.47%     87.52% |     1387026     12.48%    100.00%
+system.ruby.L1Cache_Controller.L1_Replacement::total     11110748                      
+system.ruby.L1Cache_Controller.Data_Shared |         207     12.27%     12.27% |         196     11.62%     23.89% |         225     13.34%     37.23% |         230     13.63%     50.86% |         203     12.03%     62.89% |         226     13.40%     76.29% |         199     11.80%     88.09% |         201     11.91%    100.00%
+system.ruby.L1Cache_Controller.Data_Shared::total         1687                      
+system.ruby.L1Cache_Controller.Data_Owner |          58     12.24%     12.24% |          57     12.03%     24.26% |          63     13.29%     37.55% |          59     12.45%     50.00% |          55     11.60%     61.60% |          73     15.40%     77.00% |          70     14.77%     91.77% |          39      8.23%    100.00%
+system.ruby.L1Cache_Controller.Data_Owner::total          474                      
+system.ruby.L1Cache_Controller.Data_All_Tokens |       81933     12.48%     12.48% |       82456     12.56%     25.04% |       81847     12.47%     37.51% |       81887     12.47%     49.99% |       82319     12.54%     62.53% |       82200     12.52%     75.05% |       81861     12.47%     87.52% |       81912     12.48%    100.00%
+system.ruby.L1Cache_Controller.Data_All_Tokens::total       656415                      
+system.ruby.L1Cache_Controller.Ack       |           1      9.09%      9.09% |           2     18.18%     27.27% |           3     27.27%     54.55% |           0      0.00%     54.55% |           3     27.27%     81.82% |           0      0.00%     81.82% |           1      9.09%     90.91% |           1      9.09%    100.00%
+system.ruby.L1Cache_Controller.Ack::total           11                      
+system.ruby.L1Cache_Controller.Ack_All_Tokens |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           2     66.67%     66.67% |           0      0.00%     66.67% |           0      0.00%     66.67% |           0      0.00%     66.67% |           1     33.33%    100.00%
+system.ruby.L1Cache_Controller.Ack_All_Tokens::total            3                      
+system.ruby.L1Cache_Controller.Transient_Local_GETX |      195856     12.51%     12.51% |      195405     12.48%     25.00% |      195686     12.50%     37.50% |      195464     12.49%     49.99% |      195589     12.50%     62.49% |      195721     12.51%     74.99% |      195705     12.50%     87.50% |      195711     12.50%    100.00%
+system.ruby.L1Cache_Controller.Transient_Local_GETX::total      1565137                      
+system.ruby.L1Cache_Controller.Transient_Local_GETS |      353824     12.50%     12.50% |      353751     12.49%     24.99% |      354024     12.50%     37.50% |      354198     12.51%     50.01% |      353727     12.49%     62.50% |      353736     12.49%     74.99% |      353985     12.50%     87.50% |      353973     12.50%    100.00%
+system.ruby.L1Cache_Controller.Transient_Local_GETS::total      2831218                      
+system.ruby.L1Cache_Controller.Transient_Local_GETS_Last_Token |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           1     50.00%     50.00% |           0      0.00%     50.00% |           1     50.00%    100.00%
+system.ruby.L1Cache_Controller.Transient_Local_GETS_Last_Token::total            2                      
+system.ruby.L1Cache_Controller.Persistent_GETX |       41310     12.50%     12.50% |       41193     12.47%     24.97% |       41275     12.49%     37.46% |       41218     12.47%     49.93% |       41337     12.51%     62.44% |       41353     12.51%     74.95% |       41394     12.53%     87.48% |       41368     12.52%    100.00%
+system.ruby.L1Cache_Controller.Persistent_GETX::total       330448                      
+system.ruby.L1Cache_Controller.Persistent_GETS |       75041     12.51%     12.51% |       74960     12.50%     25.02% |       74914     12.49%     37.51% |       75011     12.51%     50.02% |       74765     12.47%     62.49% |       74943     12.50%     74.99% |       74980     12.50%     87.49% |       74997     12.51%    100.00%
+system.ruby.L1Cache_Controller.Persistent_GETS::total       599611                      
+system.ruby.L1Cache_Controller.Persistent_GETS_Last_Token |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           1    100.00%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache_Controller.Persistent_GETS_Last_Token::total            1                      
+system.ruby.L1Cache_Controller.Own_Lock_or_Unlock |      147847     12.49%     12.49% |      148045     12.51%     25.00% |      148009     12.51%     37.51% |      147969     12.50%     50.01% |      148096     12.51%     62.52% |      147902     12.50%     75.02% |      147823     12.49%     87.51% |      147833     12.49%    100.00%
+system.ruby.L1Cache_Controller.Own_Lock_or_Unlock::total      1183524                      
+system.ruby.L1Cache_Controller.Request_Timeout |       60198     12.41%     12.41% |       61718     12.72%     25.13% |       61562     12.69%     37.81% |       60908     12.55%     50.36% |       60726     12.51%     62.88% |       60057     12.38%     75.26% |       59803     12.32%     87.58% |       60259     12.42%    100.00%
+system.ruby.L1Cache_Controller.Request_Timeout::total       485231                      
+system.ruby.L1Cache_Controller.Use_TimeoutStarverX |           5      5.38%      5.38% |           4      4.30%      9.68% |           3      3.23%     12.90% |          14     15.05%     27.96% |          17     18.28%     46.24% |          11     11.83%     58.06% |          19     20.43%     78.49% |          20     21.51%    100.00%
+system.ruby.L1Cache_Controller.Use_TimeoutStarverX::total           93                      
+system.ruby.L1Cache_Controller.Use_TimeoutStarverS |           5      3.27%      3.27% |           6      3.92%      7.19% |          12      7.84%     15.03% |          17     11.11%     26.14% |          23     15.03%     41.18% |          24     15.69%     56.86% |          34     22.22%     79.08% |          32     20.92%    100.00%
+system.ruby.L1Cache_Controller.Use_TimeoutStarverS::total          153                      
+system.ruby.L1Cache_Controller.Use_TimeoutNoStarvers |       78118     12.48%     12.48% |       78650     12.57%     25.05% |       78056     12.47%     37.52% |       78094     12.48%     50.00% |       78456     12.54%     62.54% |       78284     12.51%     75.05% |       78056     12.47%     87.52% |       78078     12.48%    100.00%
+system.ruby.L1Cache_Controller.Use_TimeoutNoStarvers::total       625792                      
+system.ruby.L1Cache_Controller.NP.Load   |       50564     12.52%     12.52% |       50644     12.54%     25.06% |       50367     12.47%     37.53% |       50194     12.43%     49.96% |       50652     12.54%     62.50% |       50646     12.54%     75.04% |       50410     12.48%     87.52% |       50414     12.48%    100.00%
+system.ruby.L1Cache_Controller.NP.Load::total       403891                      
+system.ruby.L1Cache_Controller.NP.Store  |       27691     12.40%     12.40% |       28155     12.61%     25.01% |       27877     12.48%     37.50% |       28080     12.58%     50.07% |       27961     12.52%     62.59% |       27826     12.46%     75.06% |       27849     12.47%     87.53% |       27846     12.47%    100.00%
+system.ruby.L1Cache_Controller.NP.Store::total       223285                      
+system.ruby.L1Cache_Controller.NP.Data_Shared |           8     14.55%     14.55% |           8     14.55%     29.09% |           9     16.36%     45.45% |          10     18.18%     63.64% |           8     14.55%     78.18% |           8     14.55%     92.73% |           3      5.45%     98.18% |           1      1.82%    100.00%
+system.ruby.L1Cache_Controller.NP.Data_Shared::total           55                      
+system.ruby.L1Cache_Controller.NP.Data_Owner |          15     13.39%     13.39% |          13     11.61%     25.00% |          11      9.82%     34.82% |          17     15.18%     50.00% |          14     12.50%     62.50% |          19     16.96%     79.46% |          17     15.18%     94.64% |           6      5.36%    100.00%
+system.ruby.L1Cache_Controller.NP.Data_Owner::total          112                      
+system.ruby.L1Cache_Controller.NP.Data_All_Tokens |        3770     12.48%     12.48% |        3762     12.45%     24.92% |        3754     12.42%     37.35% |        3737     12.37%     49.71% |        3801     12.58%     62.29% |        3871     12.81%     75.10% |        3746     12.40%     87.50% |        3778     12.50%    100.00%
+system.ruby.L1Cache_Controller.NP.Data_All_Tokens::total        30219                      
+system.ruby.L1Cache_Controller.NP.Ack    |           0      0.00%      0.00% |           2     40.00%     40.00% |           1     20.00%     60.00% |           0      0.00%     60.00% |           1     20.00%     80.00% |           0      0.00%     80.00% |           1     20.00%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache_Controller.NP.Ack::total            5                      
+system.ruby.L1Cache_Controller.NP.Transient_Local_GETX |      195270     12.52%     12.52% |      194792     12.48%     25.00% |      195065     12.50%     37.50% |      194859     12.49%     49.99% |      194966     12.50%     62.49% |      195149     12.51%     74.99% |      195088     12.50%     87.50% |      195074     12.50%    100.00%
+system.ruby.L1Cache_Controller.NP.Transient_Local_GETX::total      1560263                      
+system.ruby.L1Cache_Controller.NP.Transient_Local_GETS |      352736     12.50%     12.50% |      352665     12.50%     24.99% |      352880     12.50%     37.50% |      353067     12.51%     50.01% |      352630     12.49%     62.50% |      352652     12.50%     75.00% |      352848     12.50%     87.50% |      352851     12.50%    100.00%
+system.ruby.L1Cache_Controller.NP.Transient_Local_GETS::total      2822329                      
+system.ruby.L1Cache_Controller.NP.Own_Lock_or_Unlock |      129129     12.50%     12.50% |      129222     12.51%     25.01% |      129019     12.49%     37.50% |      129118     12.50%     50.00% |      129094     12.50%     62.50% |      129148     12.50%     75.00% |      129162     12.50%     87.51% |      129056     12.49%    100.00%
+system.ruby.L1Cache_Controller.NP.Own_Lock_or_Unlock::total      1032948                      
+system.ruby.L1Cache_Controller.I.Load    |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           1    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.L1Cache_Controller.I.Load::total            1                      
-system.ruby.L1Cache_Controller.I.L1_Replacement |         183     13.13%     13.13% |         170     12.20%     25.32% |         174     12.48%     37.80% |         180     12.91%     50.72% |         173     12.41%     63.13% |         164     11.76%     74.89% |         159     11.41%     86.30% |         191     13.70%    100.00%
-system.ruby.L1Cache_Controller.I.L1_Replacement::total         1394                      
-system.ruby.L1Cache_Controller.I.Transient_Local_GETX |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           1    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.L1Cache_Controller.I.Transient_Local_GETX::total            1                      
-system.ruby.L1Cache_Controller.I.Transient_Local_GETS |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           2     66.67%     66.67% |           0      0.00%     66.67% |           1     33.33%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.L1Cache_Controller.I.Transient_Local_GETS::total            3                      
-system.ruby.L1Cache_Controller.I.Persistent_GETX |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           1    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache_Controller.I.L1_Replacement |         158     11.47%     11.47% |         153     11.10%     22.57% |         166     12.05%     34.62% |         174     12.63%     47.24% |         189     13.72%     60.96% |         170     12.34%     73.29% |         173     12.55%     85.85% |         195     14.15%    100.00%
+system.ruby.L1Cache_Controller.I.L1_Replacement::total         1378                      
+system.ruby.L1Cache_Controller.I.Transient_Local_GETX |           1     25.00%     25.00% |           1     25.00%     50.00% |           0      0.00%     50.00% |           0      0.00%     50.00% |           1     25.00%     75.00% |           1     25.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache_Controller.I.Transient_Local_GETX::total            4                      
+system.ruby.L1Cache_Controller.I.Transient_Local_GETS |           0      0.00%      0.00% |           0      0.00%      0.00% |           1    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache_Controller.I.Transient_Local_GETS::total            1                      
+system.ruby.L1Cache_Controller.I.Persistent_GETX |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           1    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.L1Cache_Controller.I.Persistent_GETX::total            1                      
-system.ruby.L1Cache_Controller.I.Persistent_GETS |           1     33.33%     33.33% |           1     33.33%     66.67% |           0      0.00%     66.67% |           1     33.33%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.L1Cache_Controller.I.Persistent_GETS::total            3                      
-system.ruby.L1Cache_Controller.I.Own_Lock_or_Unlock |           0      0.00%      0.00% |           1     50.00%     50.00% |           0      0.00%     50.00% |           0      0.00%     50.00% |           1     50.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.L1Cache_Controller.I.Own_Lock_or_Unlock::total            2                      
-system.ruby.L1Cache_Controller.S.Load    |           0      0.00%      0.00% |           0      0.00%      0.00% |           1    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.L1Cache_Controller.S.Load::total            1                      
-system.ruby.L1Cache_Controller.S.L1_Replacement |         249     11.95%     11.95% |         252     12.09%     24.04% |         274     13.15%     37.19% |         244     11.71%     48.90% |         272     13.05%     61.95% |         281     13.48%     75.43% |         241     11.56%     87.00% |         271     13.00%    100.00%
-system.ruby.L1Cache_Controller.S.L1_Replacement::total         2084                      
-system.ruby.L1Cache_Controller.S.Data_Shared |           1     20.00%     20.00% |           0      0.00%     20.00% |           2     40.00%     60.00% |           0      0.00%     60.00% |           1     20.00%     80.00% |           0      0.00%     80.00% |           0      0.00%     80.00% |           1     20.00%    100.00%
+system.ruby.L1Cache_Controller.I.Persistent_GETS |           1    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache_Controller.I.Persistent_GETS::total            1                      
+system.ruby.L1Cache_Controller.I.Own_Lock_or_Unlock |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           1     20.00%     20.00% |           0      0.00%     20.00% |           2     40.00%     60.00% |           1     20.00%     80.00% |           1     20.00%    100.00%
+system.ruby.L1Cache_Controller.I.Own_Lock_or_Unlock::total            5                      
+system.ruby.L1Cache_Controller.S.Load    |           0      0.00%      0.00% |           1     50.00%     50.00% |           1     50.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache_Controller.S.Load::total            2                      
+system.ruby.L1Cache_Controller.S.L1_Replacement |         239     12.11%     12.11% |         233     11.80%     23.91% |         265     13.42%     37.34% |         258     13.07%     50.41% |         244     12.36%     62.77% |         250     12.66%     75.43% |         244     12.36%     87.79% |         241     12.21%    100.00%
+system.ruby.L1Cache_Controller.S.L1_Replacement::total         1974                      
+system.ruby.L1Cache_Controller.S.Data_Shared |           2     40.00%     40.00% |           0      0.00%     40.00% |           0      0.00%     40.00% |           0      0.00%     40.00% |           0      0.00%     40.00% |           2     40.00%     80.00% |           1     20.00%    100.00% |           0      0.00%    100.00%
 system.ruby.L1Cache_Controller.S.Data_Shared::total            5                      
-system.ruby.L1Cache_Controller.S.Data_All_Tokens |           0      0.00%      0.00% |           1    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache_Controller.S.Data_All_Tokens |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           1    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.L1Cache_Controller.S.Data_All_Tokens::total            1                      
-system.ruby.L1Cache_Controller.S.Transient_Local_GETX |           1     12.50%     12.50% |           2     25.00%     37.50% |           1     12.50%     50.00% |           1     12.50%     62.50% |           2     25.00%     87.50% |           0      0.00%     87.50% |           0      0.00%     87.50% |           1     12.50%    100.00%
-system.ruby.L1Cache_Controller.S.Transient_Local_GETX::total            8                      
-system.ruby.L1Cache_Controller.S.Transient_Local_GETS |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           1    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache_Controller.S.Transient_Local_GETX |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           1     25.00%     25.00% |           0      0.00%     25.00% |           1     25.00%     50.00% |           2     50.00%    100.00%
+system.ruby.L1Cache_Controller.S.Transient_Local_GETX::total            4                      
+system.ruby.L1Cache_Controller.S.Transient_Local_GETS |           0      0.00%      0.00% |           0      0.00%      0.00% |           1    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.L1Cache_Controller.S.Transient_Local_GETS::total            1                      
-system.ruby.L1Cache_Controller.S.Transient_Local_GETS_Last_Token |           2     22.22%     22.22% |           0      0.00%     22.22% |           1     11.11%     33.33% |           4     44.44%     77.78% |           0      0.00%     77.78% |           1     11.11%     88.89% |           0      0.00%     88.89% |           1     11.11%    100.00%
-system.ruby.L1Cache_Controller.S.Transient_Local_GETS_Last_Token::total            9                      
-system.ruby.L1Cache_Controller.S.Persistent_GETX |           1    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.L1Cache_Controller.S.Persistent_GETX::total            1                      
-system.ruby.L1Cache_Controller.S.Persistent_GETS |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           1     50.00%     50.00% |           1     50.00%    100.00% |           0      0.00%    100.00%
-system.ruby.L1Cache_Controller.S.Persistent_GETS::total            2                      
-system.ruby.L1Cache_Controller.S.Persistent_GETS_Last_Token |           0      0.00%      0.00% |           0      0.00%      0.00% |           1     33.33%     33.33% |           1     33.33%     66.67% |           1     33.33%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.L1Cache_Controller.S.Persistent_GETS_Last_Token::total            3                      
-system.ruby.L1Cache_Controller.O.L1_Replacement |         133     13.05%     13.05% |         127     12.46%     25.52% |         116     11.38%     36.90% |         134     13.15%     50.05% |         132     12.95%     63.00% |         145     14.23%     77.23% |         111     10.89%     88.13% |         121     11.87%    100.00%
-system.ruby.L1Cache_Controller.O.L1_Replacement::total         1019                      
-system.ruby.L1Cache_Controller.O.Data_All_Tokens |           1     50.00%     50.00% |           0      0.00%     50.00% |           0      0.00%     50.00% |           0      0.00%     50.00% |           0      0.00%     50.00% |           0      0.00%     50.00% |           0      0.00%     50.00% |           1     50.00%    100.00%
+system.ruby.L1Cache_Controller.S.Transient_Local_GETS_Last_Token |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           1     50.00%     50.00% |           0      0.00%     50.00% |           1     50.00%    100.00%
+system.ruby.L1Cache_Controller.S.Transient_Local_GETS_Last_Token::total            2                      
+system.ruby.L1Cache_Controller.S.Persistent_GETS_Last_Token |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           1    100.00%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache_Controller.S.Persistent_GETS_Last_Token::total            1                      
+system.ruby.L1Cache_Controller.O.Load    |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           1    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache_Controller.O.Load::total            1                      
+system.ruby.L1Cache_Controller.O.L1_Replacement |         124     12.44%     12.44% |         120     12.04%     24.47% |         135     13.54%     38.01% |         119     11.94%     49.95% |         122     12.24%     62.19% |         121     12.14%     74.32% |         138     13.84%     88.16% |         118     11.84%    100.00%
+system.ruby.L1Cache_Controller.O.L1_Replacement::total          997                      
+system.ruby.L1Cache_Controller.O.Data_All_Tokens |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           1     50.00%     50.00% |           0      0.00%     50.00% |           1     50.00%    100.00% |           0      0.00%    100.00%
 system.ruby.L1Cache_Controller.O.Data_All_Tokens::total            2                      
-system.ruby.L1Cache_Controller.O.Ack_All_Tokens |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           1    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.L1Cache_Controller.O.Ack_All_Tokens::total            1                      
-system.ruby.L1Cache_Controller.O.Transient_Local_GETX |           0      0.00%      0.00% |           1     50.00%     50.00% |           0      0.00%     50.00% |           0      0.00%     50.00% |           0      0.00%     50.00% |           1     50.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.L1Cache_Controller.O.Transient_Local_GETX::total            2                      
-system.ruby.L1Cache_Controller.O.Persistent_GETS |           0      0.00%      0.00% |           1     50.00%     50.00% |           0      0.00%     50.00% |           1     50.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.L1Cache_Controller.O.Persistent_GETS::total            2                      
-system.ruby.L1Cache_Controller.O.Own_Lock_or_Unlock |          12     12.24%     12.24% |          15     15.31%     27.55% |          17     17.35%     44.90% |          13     13.27%     58.16% |          12     12.24%     70.41% |          13     13.27%     83.67% |          10     10.20%     93.88% |           6      6.12%    100.00%
-system.ruby.L1Cache_Controller.O.Own_Lock_or_Unlock::total           98                      
-system.ruby.L1Cache_Controller.M.Load    |           5     12.20%     12.20% |           2      4.88%     17.07% |           3      7.32%     24.39% |           5     12.20%     36.59% |           5     12.20%     48.78% |           3      7.32%     56.10% |           8     19.51%     75.61% |          10     24.39%    100.00%
-system.ruby.L1Cache_Controller.M.Load::total           41                      
-system.ruby.L1Cache_Controller.M.Store   |           3     14.29%     14.29% |           2      9.52%     23.81% |           5     23.81%     47.62% |           4     19.05%     66.67% |           3     14.29%     80.95% |           4     19.05%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.L1Cache_Controller.M.Store::total           21                      
-system.ruby.L1Cache_Controller.M.L1_Replacement |       49847     12.55%     12.55% |       49500     12.46%     25.00% |       49774     12.53%     37.53% |       49713     12.51%     50.04% |       49519     12.46%     62.51% |       49733     12.52%     75.03% |       49702     12.51%     87.53% |       49527     12.47%    100.00%
-system.ruby.L1Cache_Controller.M.L1_Replacement::total       397315                      
-system.ruby.L1Cache_Controller.M.Transient_Local_GETX |          50     13.62%     13.62% |          36      9.81%     23.43% |          52     14.17%     37.60% |          40     10.90%     48.50% |          46     12.53%     61.04% |          55     14.99%     76.02% |          33      8.99%     85.01% |          55     14.99%    100.00%
-system.ruby.L1Cache_Controller.M.Transient_Local_GETX::total          367                      
-system.ruby.L1Cache_Controller.M.Transient_Local_GETS |          83     12.44%     12.44% |          71     10.64%     23.09% |          76     11.39%     34.48% |          96     14.39%     48.88% |          80     11.99%     60.87% |          96     14.39%     75.26% |          81     12.14%     87.41% |          84     12.59%    100.00%
-system.ruby.L1Cache_Controller.M.Transient_Local_GETS::total          667                      
-system.ruby.L1Cache_Controller.M.Persistent_GETX |          25     16.78%     16.78% |          26     17.45%     34.23% |          14      9.40%     43.62% |          21     14.09%     57.72% |          21     14.09%     71.81% |          13      8.72%     80.54% |          18     12.08%     92.62% |          11      7.38%    100.00%
-system.ruby.L1Cache_Controller.M.Persistent_GETX::total          149                      
-system.ruby.L1Cache_Controller.M.Persistent_GETS |          27     10.63%     10.63% |          31     12.20%     22.83% |          33     12.99%     35.83% |          32     12.60%     48.43% |          36     14.17%     62.60% |          38     14.96%     77.56% |          28     11.02%     88.58% |          29     11.42%    100.00%
-system.ruby.L1Cache_Controller.M.Persistent_GETS::total          254                      
-system.ruby.L1Cache_Controller.M.Own_Lock_or_Unlock |        1187     12.24%     12.24% |        1229     12.68%     24.92% |        1293     13.34%     38.25% |        1200     12.38%     50.63% |        1221     12.59%     63.22% |        1249     12.88%     76.10% |        1131     11.66%     87.77% |        1186     12.23%    100.00%
-system.ruby.L1Cache_Controller.M.Own_Lock_or_Unlock::total         9696                      
-system.ruby.L1Cache_Controller.MM.Load   |           1      4.17%      4.17% |           5     20.83%     25.00% |           2      8.33%     33.33% |           7     29.17%     62.50% |           3     12.50%     75.00% |           2      8.33%     83.33% |           3     12.50%     95.83% |           1      4.17%    100.00%
-system.ruby.L1Cache_Controller.MM.Load::total           24                      
-system.ruby.L1Cache_Controller.MM.Store  |           5     33.33%     33.33% |           1      6.67%     40.00% |           1      6.67%     46.67% |           1      6.67%     53.33% |           0      0.00%     53.33% |           3     20.00%     73.33% |           1      6.67%     80.00% |           3     20.00%    100.00%
-system.ruby.L1Cache_Controller.MM.Store::total           15                      
-system.ruby.L1Cache_Controller.MM.L1_Replacement |       26851     12.49%     12.49% |       27209     12.66%     25.15% |       26736     12.44%     37.58% |       26508     12.33%     49.91% |       26847     12.49%     62.40% |       26914     12.52%     74.92% |       27102     12.61%     87.53% |       26811     12.47%    100.00%
-system.ruby.L1Cache_Controller.MM.L1_Replacement::total       214978                      
-system.ruby.L1Cache_Controller.MM.Transient_Local_GETX |          31     14.76%     14.76% |          33     15.71%     30.48% |          27     12.86%     43.33% |          28     13.33%     56.67% |          17      8.10%     64.76% |          21     10.00%     74.76% |          25     11.90%     86.67% |          28     13.33%    100.00%
-system.ruby.L1Cache_Controller.MM.Transient_Local_GETX::total          210                      
-system.ruby.L1Cache_Controller.MM.Transient_Local_GETS |          45     14.11%     14.11% |          36     11.29%     25.39% |          37     11.60%     36.99% |          41     12.85%     49.84% |          49     15.36%     65.20% |          33     10.34%     75.55% |          36     11.29%     86.83% |          42     13.17%    100.00%
-system.ruby.L1Cache_Controller.MM.Transient_Local_GETS::total          319                      
-system.ruby.L1Cache_Controller.MM.Persistent_GETX |          11     13.10%     13.10% |          11     13.10%     26.19% |          10     11.90%     38.10% |          17     20.24%     58.33% |          10     11.90%     70.24% |          10     11.90%     82.14% |           8      9.52%     91.67% |           7      8.33%    100.00%
-system.ruby.L1Cache_Controller.MM.Persistent_GETX::total           84                      
-system.ruby.L1Cache_Controller.MM.Persistent_GETS |          12     10.17%     10.17% |          17     14.41%     24.58% |          17     14.41%     38.98% |          14     11.86%     50.85% |           9      7.63%     58.47% |          12     10.17%     68.64% |          15     12.71%     81.36% |          22     18.64%    100.00%
-system.ruby.L1Cache_Controller.MM.Persistent_GETS::total          118                      
-system.ruby.L1Cache_Controller.MM.Own_Lock_or_Unlock |         712     13.37%     13.37% |         667     12.52%     25.89% |         685     12.86%     38.75% |         670     12.58%     51.32% |         668     12.54%     63.86% |         648     12.16%     76.03% |         636     11.94%     87.97% |         641     12.03%    100.00%
-system.ruby.L1Cache_Controller.MM.Own_Lock_or_Unlock::total         5327                      
-system.ruby.L1Cache_Controller.M_W.Load  |           2      7.14%      7.14% |           4     14.29%     21.43% |           5     17.86%     39.29% |           3     10.71%     50.00% |           3     10.71%     60.71% |           4     14.29%     75.00% |           3     10.71%     85.71% |           4     14.29%    100.00%
-system.ruby.L1Cache_Controller.M_W.Load::total           28                      
-system.ruby.L1Cache_Controller.M_W.Store |           1     11.11%     11.11% |           2     22.22%     33.33% |           0      0.00%     33.33% |           0      0.00%     33.33% |           1     11.11%     44.44% |           2     22.22%     66.67% |           2     22.22%     88.89% |           1     11.11%    100.00%
-system.ruby.L1Cache_Controller.M_W.Store::total            9                      
-system.ruby.L1Cache_Controller.M_W.L1_Replacement |      291266     12.59%     12.59% |      289622     12.52%     25.11% |      289644     12.52%     37.63% |      290259     12.55%     50.18% |      288045     12.45%     62.63% |      288216     12.46%     75.09% |      288197     12.46%     87.55% |      287895     12.45%    100.00%
-system.ruby.L1Cache_Controller.M_W.L1_Replacement::total      2313144                      
-system.ruby.L1Cache_Controller.M_W.Transient_Local_GETX |          42     14.38%     14.38% |          27      9.25%     23.63% |          30     10.27%     33.90% |          37     12.67%     46.58% |          39     13.36%     59.93% |          45     15.41%     75.34% |          33     11.30%     86.64% |          39     13.36%    100.00%
-system.ruby.L1Cache_Controller.M_W.Transient_Local_GETX::total          292                      
-system.ruby.L1Cache_Controller.M_W.Transient_Local_GETS |          66     11.60%     11.60% |          79     13.88%     25.48% |          75     13.18%     38.66% |          88     15.47%     54.13% |          63     11.07%     65.20% |          60     10.54%     75.75% |          78     13.71%     89.46% |          60     10.54%    100.00%
-system.ruby.L1Cache_Controller.M_W.Transient_Local_GETS::total          569                      
-system.ruby.L1Cache_Controller.M_W.Persistent_GETX |           3      7.14%      7.14% |           4      9.52%     16.67% |           4      9.52%     26.19% |           5     11.90%     38.10% |           4      9.52%     47.62% |           6     14.29%     61.90% |           8     19.05%     80.95% |           8     19.05%    100.00%
-system.ruby.L1Cache_Controller.M_W.Persistent_GETX::total           42                      
-system.ruby.L1Cache_Controller.M_W.Persistent_GETS |           5      5.88%      5.88% |          11     12.94%     18.82% |          11     12.94%     31.76% |           4      4.71%     36.47% |           7      8.24%     44.71% |          15     17.65%     62.35% |          15     17.65%     80.00% |          17     20.00%    100.00%
-system.ruby.L1Cache_Controller.M_W.Persistent_GETS::total           85                      
-system.ruby.L1Cache_Controller.M_W.Own_Lock_or_Unlock |         469     12.17%     12.17% |         479     12.43%     24.60% |         514     13.34%     37.94% |         489     12.69%     50.64% |         496     12.87%     63.51% |         466     12.09%     75.60% |         481     12.48%     88.09% |         459     11.91%    100.00%
-system.ruby.L1Cache_Controller.M_W.Own_Lock_or_Unlock::total         3853                      
-system.ruby.L1Cache_Controller.M_W.Use_TimeoutStarverX |           4      7.69%      7.69% |           4      7.69%     15.38% |           5      9.62%     25.00% |           6     11.54%     36.54% |           5      9.62%     46.15% |           7     13.46%     59.62% |          11     21.15%     80.77% |          10     19.23%    100.00%
-system.ruby.L1Cache_Controller.M_W.Use_TimeoutStarverX::total           52                      
-system.ruby.L1Cache_Controller.M_W.Use_TimeoutStarverS |           5      5.38%      5.38% |          11     11.83%     17.20% |          12     12.90%     30.11% |           6      6.45%     36.56% |           8      8.60%     45.16% |          17     18.28%     63.44% |          17     18.28%     81.72% |          17     18.28%    100.00%
-system.ruby.L1Cache_Controller.M_W.Use_TimeoutStarverS::total           93                      
-system.ruby.L1Cache_Controller.M_W.Use_TimeoutNoStarvers |       50035     12.55%     12.55% |       49666     12.45%     25.00% |       49954     12.53%     37.53% |       49907     12.52%     50.04% |       49705     12.46%     62.51% |       49940     12.52%     75.03% |       49862     12.50%     87.54% |       49706     12.46%    100.00%
-system.ruby.L1Cache_Controller.M_W.Use_TimeoutNoStarvers::total       398775                      
-system.ruby.L1Cache_Controller.MM_W.Load |           5     27.78%     27.78% |           1      5.56%     33.33% |           0      0.00%     33.33% |           2     11.11%     44.44% |           3     16.67%     61.11% |           5     27.78%     88.89% |           1      5.56%     94.44% |           1      5.56%    100.00%
-system.ruby.L1Cache_Controller.MM_W.Load::total           18                      
-system.ruby.L1Cache_Controller.MM_W.Store |           2     25.00%     25.00% |           0      0.00%     25.00% |           0      0.00%     25.00% |           0      0.00%     25.00% |           2     25.00%     50.00% |           2     25.00%     75.00% |           1     12.50%     87.50% |           1     12.50%    100.00%
-system.ruby.L1Cache_Controller.MM_W.Store::total            8                      
-system.ruby.L1Cache_Controller.MM_W.L1_Replacement |      155942     12.48%     12.48% |      158074     12.65%     25.12% |      153918     12.31%     37.44% |      152634     12.21%     49.65% |      158304     12.67%     62.32% |      157087     12.57%     74.89% |      158031     12.64%     87.53% |      155857     12.47%    100.00%
-system.ruby.L1Cache_Controller.MM_W.L1_Replacement::total      1249847                      
-system.ruby.L1Cache_Controller.MM_W.Transient_Local_GETX |          23     13.07%     13.07% |          18     10.23%     23.30% |          18     10.23%     33.52% |          26     14.77%     48.30% |          23     13.07%     61.36% |          21     11.93%     73.30% |          20     11.36%     84.66% |          27     15.34%    100.00%
+system.ruby.L1Cache_Controller.O.Ack     |           0      0.00%      0.00% |           0      0.00%      0.00% |           1    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache_Controller.O.Ack::total            1                      
+system.ruby.L1Cache_Controller.O.Transient_Local_GETX |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           1    100.00%    100.00%
+system.ruby.L1Cache_Controller.O.Transient_Local_GETX::total            1                      
+system.ruby.L1Cache_Controller.O.Transient_Local_GETS |           0      0.00%      0.00% |           0      0.00%      0.00% |           1     50.00%     50.00% |           1     50.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache_Controller.O.Transient_Local_GETS::total            2                      
+system.ruby.L1Cache_Controller.O.Persistent_GETX |           1    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache_Controller.O.Persistent_GETX::total            1                      
+system.ruby.L1Cache_Controller.O.Persistent_GETS |           1     25.00%     25.00% |           1     25.00%     50.00% |           0      0.00%     50.00% |           0      0.00%     50.00% |           2     50.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache_Controller.O.Persistent_GETS::total            4                      
+system.ruby.L1Cache_Controller.O.Own_Lock_or_Unlock |          15     17.44%     17.44% |          11     12.79%     30.23% |          13     15.12%     45.35% |           9     10.47%     55.81% |          10     11.63%     67.44% |           9     10.47%     77.91% |          12     13.95%     91.86% |           7      8.14%    100.00%
+system.ruby.L1Cache_Controller.O.Own_Lock_or_Unlock::total           86                      
+system.ruby.L1Cache_Controller.M.Load    |           6     12.00%     12.00% |           9     18.00%     30.00% |           5     10.00%     40.00% |           4      8.00%     48.00% |           8     16.00%     64.00% |           8     16.00%     80.00% |           4      8.00%     88.00% |           6     12.00%    100.00%
+system.ruby.L1Cache_Controller.M.Load::total           50                      
+system.ruby.L1Cache_Controller.M.Store   |           2      8.00%      8.00% |           4     16.00%     24.00% |           2      8.00%     32.00% |           3     12.00%     44.00% |           5     20.00%     64.00% |           4     16.00%     80.00% |           3     12.00%     92.00% |           2      8.00%    100.00%
+system.ruby.L1Cache_Controller.M.Store::total           25                      
+system.ruby.L1Cache_Controller.M.L1_Replacement |       50210     12.52%     12.52% |       50284     12.54%     25.07% |       49968     12.46%     37.53% |       49814     12.43%     49.96% |       50283     12.54%     62.50% |       50284     12.54%     75.04% |       50007     12.47%     87.52% |       50037     12.48%    100.00%
+system.ruby.L1Cache_Controller.M.L1_Replacement::total       400887                      
+system.ruby.L1Cache_Controller.M.Transient_Local_GETX |          39     11.82%     11.82% |          40     12.12%     23.94% |          47     14.24%     38.18% |          39     11.82%     50.00% |          45     13.64%     63.64% |          36     10.91%     74.55% |          38     11.52%     86.06% |          46     13.94%    100.00%
+system.ruby.L1Cache_Controller.M.Transient_Local_GETX::total          330                      
+system.ruby.L1Cache_Controller.M.Transient_Local_GETS |          83     12.85%     12.85% |          77     11.92%     24.77% |          83     12.85%     37.62% |          79     12.23%     49.85% |          84     13.00%     62.85% |          67     10.37%     73.22% |          86     13.31%     86.53% |          87     13.47%    100.00%
+system.ruby.L1Cache_Controller.M.Transient_Local_GETS::total          646                      
+system.ruby.L1Cache_Controller.M.Persistent_GETX |          15     11.03%     11.03% |          18     13.24%     24.26% |          14     10.29%     34.56% |          16     11.76%     46.32% |          19     13.97%     60.29% |          16     11.76%     72.06% |          22     16.18%     88.24% |          16     11.76%    100.00%
+system.ruby.L1Cache_Controller.M.Persistent_GETX::total          136                      
+system.ruby.L1Cache_Controller.M.Persistent_GETS |          38     15.08%     15.08% |          40     15.87%     30.95% |          41     16.27%     47.22% |          32     12.70%     59.92% |          32     12.70%     72.62% |          20      7.94%     80.56% |          26     10.32%     90.87% |          23      9.13%    100.00%
+system.ruby.L1Cache_Controller.M.Persistent_GETS::total          252                      
+system.ruby.L1Cache_Controller.M.Own_Lock_or_Unlock |        1217     12.47%     12.47% |        1156     11.84%     24.31% |        1266     12.97%     37.28% |        1220     12.50%     49.77% |        1200     12.29%     62.07% |        1226     12.56%     74.63% |        1208     12.37%     87.00% |        1269     13.00%    100.00%
+system.ruby.L1Cache_Controller.M.Own_Lock_or_Unlock::total         9762                      
+system.ruby.L1Cache_Controller.MM.Load   |           5     19.23%     19.23% |           2      7.69%     26.92% |           2      7.69%     34.62% |           1      3.85%     38.46% |          10     38.46%     76.92% |           1      3.85%     80.77% |           2      7.69%     88.46% |           3     11.54%    100.00%
+system.ruby.L1Cache_Controller.MM.Load::total           26                      
+system.ruby.L1Cache_Controller.MM.Store  |           0      0.00%      0.00% |           0      0.00%      0.00% |           3     21.43%     21.43% |           3     21.43%     42.86% |           1      7.14%     50.00% |           2     14.29%     64.29% |           2     14.29%     78.57% |           3     21.43%    100.00%
+system.ruby.L1Cache_Controller.MM.Store::total           14                      
+system.ruby.L1Cache_Controller.MM.L1_Replacement |       27637     12.41%     12.41% |       28101     12.61%     25.02% |       27803     12.48%     37.50% |       28019     12.58%     50.08% |       27893     12.52%     62.60% |       27764     12.46%     75.06% |       27795     12.48%     87.53% |       27771     12.47%    100.00%
+system.ruby.L1Cache_Controller.MM.L1_Replacement::total       222783                      
+system.ruby.L1Cache_Controller.MM.Transient_Local_GETX |          21     11.41%     11.41% |          15      8.15%     19.57% |          28     15.22%     34.78% |          22     11.96%     46.74% |          31     16.85%     63.59% |          26     14.13%     77.72% |          23     12.50%     90.22% |          18      9.78%    100.00%
+system.ruby.L1Cache_Controller.MM.Transient_Local_GETX::total          184                      
+system.ruby.L1Cache_Controller.MM.Transient_Local_GETS |          48     13.11%     13.11% |          42     11.48%     24.59% |          44     12.02%     36.61% |          47     12.84%     49.45% |          43     11.75%     61.20% |          48     13.11%     74.32% |          41     11.20%     85.52% |          53     14.48%    100.00%
+system.ruby.L1Cache_Controller.MM.Transient_Local_GETS::total          366                      
+system.ruby.L1Cache_Controller.MM.Persistent_GETX |          10     13.89%     13.89% |          10     13.89%     27.78% |           9     12.50%     40.28% |           8     11.11%     51.39% |          10     13.89%     65.28% |           7      9.72%     75.00% |           6      8.33%     83.33% |          12     16.67%    100.00%
+system.ruby.L1Cache_Controller.MM.Persistent_GETX::total           72                      
+system.ruby.L1Cache_Controller.MM.Persistent_GETS |          17     12.59%     12.59% |          22     16.30%     28.89% |          17     12.59%     41.48% |          19     14.07%     55.56% |          16     11.85%     67.41% |          16     11.85%     79.26% |          13      9.63%     88.89% |          15     11.11%    100.00%
+system.ruby.L1Cache_Controller.MM.Persistent_GETS::total          135                      
+system.ruby.L1Cache_Controller.MM.Own_Lock_or_Unlock |         653     12.24%     12.24% |         657     12.31%     24.55% |         734     13.75%     38.30% |         664     12.44%     50.74% |         685     12.83%     63.58% |         640     11.99%     75.57% |         621     11.64%     87.20% |         683     12.80%    100.00%
+system.ruby.L1Cache_Controller.MM.Own_Lock_or_Unlock::total         5337                      
+system.ruby.L1Cache_Controller.M_W.Load  |           6     17.14%     17.14% |           4     11.43%     28.57% |           4     11.43%     40.00% |           6     17.14%     57.14% |           3      8.57%     65.71% |           6     17.14%     82.86% |           4     11.43%     94.29% |           2      5.71%    100.00%
+system.ruby.L1Cache_Controller.M_W.Load::total           35                      
+system.ruby.L1Cache_Controller.M_W.Store |           1      5.26%      5.26% |           2     10.53%     15.79% |           2     10.53%     26.32% |           1      5.26%     31.58% |           3     15.79%     47.37% |           2     10.53%     57.89% |           2     10.53%     68.42% |           6     31.58%    100.00%
+system.ruby.L1Cache_Controller.M_W.Store::total           19                      
+system.ruby.L1Cache_Controller.M_W.L1_Replacement |      292424     12.54%     12.54% |      289923     12.43%     24.97% |      291806     12.51%     37.49% |      287812     12.34%     49.83% |      293129     12.57%     62.40% |      292944     12.56%     74.96% |      290472     12.46%     87.41% |      293489     12.59%    100.00%
+system.ruby.L1Cache_Controller.M_W.L1_Replacement::total      2331999                      
+system.ruby.L1Cache_Controller.M_W.Transient_Local_GETX |          53     17.04%     17.04% |          43     13.83%     30.87% |          36     11.58%     42.44% |          43     13.83%     56.27% |          38     12.22%     68.49% |          29      9.32%     77.81% |          25      8.04%     85.85% |          44     14.15%    100.00%
+system.ruby.L1Cache_Controller.M_W.Transient_Local_GETX::total          311                      
+system.ruby.L1Cache_Controller.M_W.Transient_Local_GETS |          63     12.07%     12.07% |          49      9.39%     21.46% |          78     14.94%     36.40% |          71     13.60%     50.00% |          59     11.30%     61.30% |          70     13.41%     74.71% |          71     13.60%     88.31% |          61     11.69%    100.00%
+system.ruby.L1Cache_Controller.M_W.Transient_Local_GETS::total          522                      
+system.ruby.L1Cache_Controller.M_W.Persistent_GETX |           3      5.36%      5.36% |           3      5.36%     10.71% |           1      1.79%     12.50% |           8     14.29%     26.79% |           7     12.50%     39.29% |           4      7.14%     46.43% |          16     28.57%     75.00% |          14     25.00%    100.00%
+system.ruby.L1Cache_Controller.M_W.Persistent_GETX::total           56                      
+system.ruby.L1Cache_Controller.M_W.Persistent_GETS |           3      3.45%      3.45% |           5      5.75%      9.20% |           6      6.90%     16.09% |           7      8.05%     24.14% |          14     16.09%     40.23% |          13     14.94%     55.17% |          21     24.14%     79.31% |          18     20.69%    100.00%
+system.ruby.L1Cache_Controller.M_W.Persistent_GETS::total           87                      
+system.ruby.L1Cache_Controller.M_W.Own_Lock_or_Unlock |         494     12.81%     12.81% |         485     12.58%     25.39% |         490     12.71%     38.10% |         468     12.14%     50.23% |         495     12.84%     63.07% |         487     12.63%     75.70% |         488     12.66%     88.36% |         449     11.64%    100.00%
+system.ruby.L1Cache_Controller.M_W.Own_Lock_or_Unlock::total         3856                      
+system.ruby.L1Cache_Controller.M_W.Use_TimeoutStarverX |           3      4.92%      4.92% |           3      4.92%      9.84% |           1      1.64%     11.48% |           9     14.75%     26.23% |           8     13.11%     39.34% |           6      9.84%     49.18% |          17     27.87%     77.05% |          14     22.95%    100.00%
+system.ruby.L1Cache_Controller.M_W.Use_TimeoutStarverX::total           61                      
+system.ruby.L1Cache_Controller.M_W.Use_TimeoutStarverS |           3      3.00%      3.00% |           5      5.00%      8.00% |           8      8.00%     16.00% |           8      8.00%     24.00% |          16     16.00%     40.00% |          15     15.00%     55.00% |          24     24.00%     79.00% |          21     21.00%    100.00%
+system.ruby.L1Cache_Controller.M_W.Use_TimeoutStarverS::total          100                      
+system.ruby.L1Cache_Controller.M_W.Use_TimeoutNoStarvers |       50387     12.53%     12.53% |       50464     12.54%     25.07% |       50156     12.47%     37.54% |       49982     12.42%     49.96% |       50468     12.55%     62.51% |       50427     12.54%     75.04% |       50181     12.47%     87.52% |       50211     12.48%    100.00%
+system.ruby.L1Cache_Controller.M_W.Use_TimeoutNoStarvers::total       402276                      
+system.ruby.L1Cache_Controller.MM_W.Load |           3     12.00%     12.00% |           4     16.00%     28.00% |           4     16.00%     44.00% |           4     16.00%     60.00% |           1      4.00%     64.00% |           2      8.00%     72.00% |           6     24.00%     96.00% |           1      4.00%    100.00%
+system.ruby.L1Cache_Controller.MM_W.Load::total           25                      
+system.ruby.L1Cache_Controller.MM_W.Store |           1     10.00%     10.00% |           1     10.00%     20.00% |           0      0.00%     20.00% |           0      0.00%     20.00% |           2     20.00%     40.00% |           1     10.00%     50.00% |           2     20.00%     70.00% |           3     30.00%    100.00%
+system.ruby.L1Cache_Controller.MM_W.Store::total           10                      
+system.ruby.L1Cache_Controller.MM_W.L1_Replacement |      161716     12.53%     12.53% |      161272     12.49%     25.02% |      160842     12.46%     37.48% |      163936     12.70%     50.18% |      160722     12.45%     62.63% |      161511     12.51%     75.15% |      160578     12.44%     87.59% |      160236     12.41%    100.00%
+system.ruby.L1Cache_Controller.MM_W.L1_Replacement::total      1290813                      
+system.ruby.L1Cache_Controller.MM_W.Transient_Local_GETX |          24     13.64%     13.64% |          26     14.77%     28.41% |          25     14.20%     42.61% |          16      9.09%     51.70% |          22     12.50%     64.20% |          17      9.66%     73.86% |          13      7.39%     81.25% |          33     18.75%    100.00%
 system.ruby.L1Cache_Controller.MM_W.Transient_Local_GETX::total          176                      
-system.ruby.L1Cache_Controller.MM_W.Transient_Local_GETS |          30      9.71%      9.71% |          45     14.56%     24.27% |          31     10.03%     34.30% |          43     13.92%     48.22% |          33     10.68%     58.90% |          40     12.94%     71.84% |          44     14.24%     86.08% |          43     13.92%    100.00%
-system.ruby.L1Cache_Controller.MM_W.Transient_Local_GETS::total          309                      
-system.ruby.L1Cache_Controller.MM_W.Persistent_GETX |           1      3.03%      3.03% |           0      0.00%      3.03% |           6     18.18%     21.21% |           4     12.12%     33.33% |           7     21.21%     54.55% |           2      6.06%     60.61% |           7     21.21%     81.82% |           6     18.18%    100.00%
-system.ruby.L1Cache_Controller.MM_W.Persistent_GETX::total           33                      
-system.ruby.L1Cache_Controller.MM_W.Persistent_GETS |           1      2.38%      2.38% |           3      7.14%      9.52% |           3      7.14%     16.67% |           7     16.67%     33.33% |           6     14.29%     47.62% |           7     16.67%     64.29% |           7     16.67%     80.95% |           8     19.05%    100.00%
-system.ruby.L1Cache_Controller.MM_W.Persistent_GETS::total           42                      
-system.ruby.L1Cache_Controller.MM_W.Own_Lock_or_Unlock |         292     13.90%     13.90% |         270     12.85%     26.75% |         253     12.04%     38.79% |         231     10.99%     49.79% |         270     12.85%     62.64% |         272     12.95%     75.58% |         278     13.23%     88.81% |         235     11.19%    100.00%
-system.ruby.L1Cache_Controller.MM_W.Own_Lock_or_Unlock::total         2101                      
-system.ruby.L1Cache_Controller.MM_W.Use_TimeoutStarverX |           1      2.70%      2.70% |           0      0.00%      2.70% |           7     18.92%     21.62% |           5     13.51%     35.14% |           8     21.62%     56.76% |           3      8.11%     64.86% |           7     18.92%     83.78% |           6     16.22%    100.00%
-system.ruby.L1Cache_Controller.MM_W.Use_TimeoutStarverX::total           37                      
-system.ruby.L1Cache_Controller.MM_W.Use_TimeoutStarverS |           1      2.22%      2.22% |           4      8.89%     11.11% |           4      8.89%     20.00% |           7     15.56%     35.56% |           6     13.33%     48.89% |           8     17.78%     66.67% |           7     15.56%     82.22% |           8     17.78%    100.00%
-system.ruby.L1Cache_Controller.MM_W.Use_TimeoutStarverS::total           45                      
-system.ruby.L1Cache_Controller.MM_W.Use_TimeoutNoStarvers |       26947     12.49%     12.49% |       27305     12.66%     25.15% |       26823     12.44%     37.59% |       26605     12.33%     49.92% |       26929     12.48%     62.41% |       26986     12.51%     74.92% |       27186     12.60%     87.52% |       26910     12.48%    100.00%
-system.ruby.L1Cache_Controller.MM_W.Use_TimeoutNoStarvers::total       215691                      
-system.ruby.L1Cache_Controller.IM.L1_Replacement |      293340     12.49%     12.49% |      295809     12.59%     25.08% |      291989     12.43%     37.52% |      287885     12.26%     49.77% |      295320     12.57%     62.35% |      295503     12.58%     74.93% |      296204     12.61%     87.54% |      292704     12.46%    100.00%
-system.ruby.L1Cache_Controller.IM.L1_Replacement::total      2348754                      
-system.ruby.L1Cache_Controller.IM.Data_Owner |           1     20.00%     20.00% |           1     20.00%     40.00% |           0      0.00%     40.00% |           1     20.00%     60.00% |           0      0.00%     60.00% |           0      0.00%     60.00% |           0      0.00%     60.00% |           2     40.00%    100.00%
-system.ruby.L1Cache_Controller.IM.Data_Owner::total            5                      
-system.ruby.L1Cache_Controller.IM.Data_All_Tokens |       26946     12.49%     12.49% |       27305     12.66%     25.15% |       26829     12.44%     37.58% |       26615     12.34%     49.92% |       26941     12.49%     62.40% |       26992     12.51%     74.92% |       27198     12.61%     87.52% |       26921     12.48%    100.00%
-system.ruby.L1Cache_Controller.IM.Data_All_Tokens::total       215747                      
-system.ruby.L1Cache_Controller.IM.Ack    |           1     10.00%     10.00% |           0      0.00%     10.00% |           1     10.00%     20.00% |           0      0.00%     20.00% |           2     20.00%     40.00% |           2     20.00%     60.00% |           3     30.00%     90.00% |           1     10.00%    100.00%
-system.ruby.L1Cache_Controller.IM.Ack::total           10                      
-system.ruby.L1Cache_Controller.IM.Transient_Local_GETX |          90     12.45%     12.45% |          84     11.62%     24.07% |          90     12.45%     36.51% |          94     13.00%     49.52% |          93     12.86%     62.38% |          87     12.03%     74.41% |          89     12.31%     86.72% |          96     13.28%    100.00%
-system.ruby.L1Cache_Controller.IM.Transient_Local_GETX::total          723                      
-system.ruby.L1Cache_Controller.IM.Transient_Local_GETS |         147     11.89%     11.89% |         144     11.65%     23.54% |         177     14.32%     37.86% |         153     12.38%     50.24% |         146     11.81%     62.06% |         154     12.46%     74.51% |         150     12.14%     86.65% |         165     13.35%    100.00%
-system.ruby.L1Cache_Controller.IM.Transient_Local_GETS::total         1236                      
-system.ruby.L1Cache_Controller.IM.Persistent_GETX |          29     14.15%     14.15% |          27     13.17%     27.32% |          22     10.73%     38.05% |          27     13.17%     51.22% |          26     12.68%     63.90% |          33     16.10%     80.00% |          22     10.73%     90.73% |          19      9.27%    100.00%
-system.ruby.L1Cache_Controller.IM.Persistent_GETX::total          205                      
-system.ruby.L1Cache_Controller.IM.Persistent_GETS |          36      9.28%      9.28% |          39     10.05%     19.33% |          50     12.89%     32.22% |          42     10.82%     43.04% |          48     12.37%     55.41% |          53     13.66%     69.07% |          57     14.69%     83.76% |          63     16.24%    100.00%
-system.ruby.L1Cache_Controller.IM.Persistent_GETS::total          388                      
-system.ruby.L1Cache_Controller.IM.Own_Lock_or_Unlock |        5483     12.57%     12.57% |        5506     12.62%     25.19% |        5529     12.68%     37.87% |        5327     12.21%     50.08% |        5492     12.59%     62.67% |        5408     12.40%     75.07% |        5402     12.38%     87.46% |        5471     12.54%    100.00%
-system.ruby.L1Cache_Controller.IM.Own_Lock_or_Unlock::total        43618                      
-system.ruby.L1Cache_Controller.IM.Request_Timeout |       20923     12.52%     12.52% |       21057     12.60%     25.13% |       21290     12.74%     37.87% |       20719     12.40%     50.27% |       21245     12.72%     62.99% |       21018     12.58%     75.57% |       20732     12.41%     87.98% |       20087     12.02%    100.00%
-system.ruby.L1Cache_Controller.IM.Request_Timeout::total       167071                      
-system.ruby.L1Cache_Controller.OM.L1_Replacement |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           1    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.L1Cache_Controller.OM.L1_Replacement::total            1                      
-system.ruby.L1Cache_Controller.OM.Data_All_Tokens |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           1    100.00%    100.00%
-system.ruby.L1Cache_Controller.OM.Data_All_Tokens::total            1                      
-system.ruby.L1Cache_Controller.OM.Ack_All_Tokens |           1     25.00%     25.00% |           1     25.00%     50.00% |           0      0.00%     50.00% |           1     25.00%     75.00% |           0      0.00%     75.00% |           0      0.00%     75.00% |           0      0.00%     75.00% |           1     25.00%    100.00%
-system.ruby.L1Cache_Controller.OM.Ack_All_Tokens::total            4                      
-system.ruby.L1Cache_Controller.OM.Own_Lock_or_Unlock |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           1    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.L1Cache_Controller.OM.Own_Lock_or_Unlock::total            1                      
-system.ruby.L1Cache_Controller.OM.Request_Timeout |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           1    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.L1Cache_Controller.OM.Request_Timeout::total            1                      
-system.ruby.L1Cache_Controller.IS.L1_Replacement |      548020     12.55%     12.55% |      544678     12.47%     25.02% |      548767     12.57%     37.58% |      548504     12.56%     50.14% |      541488     12.40%     62.54% |      544959     12.48%     75.02% |      546694     12.52%     87.54% |      544234     12.46%    100.00%
-system.ruby.L1Cache_Controller.IS.L1_Replacement::total      4367344                      
-system.ruby.L1Cache_Controller.IS.Data_Shared |         219     12.55%     12.55% |         212     12.15%     24.70% |         230     13.18%     37.88% |         206     11.81%     49.68% |         230     13.18%     62.87% |         226     12.95%     75.82% |         196     11.23%     87.05% |         226     12.95%    100.00%
-system.ruby.L1Cache_Controller.IS.Data_Shared::total         1745                      
-system.ruby.L1Cache_Controller.IS.Data_Owner |          51     14.21%     14.21% |          58     16.16%     30.36% |          40     11.14%     41.50% |          39     10.86%     52.37% |          53     14.76%     67.13% |          50     13.93%     81.06% |          30      8.36%     89.42% |          38     10.58%    100.00%
+system.ruby.L1Cache_Controller.MM_W.Transient_Local_GETS |          30     10.53%     10.53% |          33     11.58%     22.11% |          43     15.09%     37.19% |          30     10.53%     47.72% |          32     11.23%     58.95% |          41     14.39%     73.33% |          38     13.33%     86.67% |          38     13.33%    100.00%
+system.ruby.L1Cache_Controller.MM_W.Transient_Local_GETS::total          285                      
+system.ruby.L1Cache_Controller.MM_W.Persistent_GETX |           2      6.67%      6.67% |           1      3.33%     10.00% |           1      3.33%     13.33% |           4     13.33%     26.67% |           9     30.00%     56.67% |           5     16.67%     73.33% |           2      6.67%     80.00% |           6     20.00%    100.00%
+system.ruby.L1Cache_Controller.MM_W.Persistent_GETX::total           30                      
+system.ruby.L1Cache_Controller.MM_W.Persistent_GETS |           2      4.17%      4.17% |           1      2.08%      6.25% |           4      8.33%     14.58% |           9     18.75%     33.33% |           6     12.50%     45.83% |           9     18.75%     64.58% |           8     16.67%     81.25% |           9     18.75%    100.00%
+system.ruby.L1Cache_Controller.MM_W.Persistent_GETS::total           48                      
+system.ruby.L1Cache_Controller.MM_W.Own_Lock_or_Unlock |         275     12.91%     12.91% |         284     13.33%     26.24% |         284     13.33%     39.58% |         295     13.85%     53.43% |         247     11.60%     65.02% |         261     12.25%     77.28% |         232     10.89%     88.17% |         252     11.83%    100.00%
+system.ruby.L1Cache_Controller.MM_W.Own_Lock_or_Unlock::total         2130                      
+system.ruby.L1Cache_Controller.MM_W.Use_TimeoutStarverX |           2      6.25%      6.25% |           1      3.12%      9.38% |           2      6.25%     15.62% |           5     15.62%     31.25% |           9     28.12%     59.38% |           5     15.62%     75.00% |           2      6.25%     81.25% |           6     18.75%    100.00%
+system.ruby.L1Cache_Controller.MM_W.Use_TimeoutStarverX::total           32                      
+system.ruby.L1Cache_Controller.MM_W.Use_TimeoutStarverS |           2      3.77%      3.77% |           1      1.89%      5.66% |           4      7.55%     13.21% |           9     16.98%     30.19% |           7     13.21%     43.40% |           9     16.98%     60.38% |          10     18.87%     79.25% |          11     20.75%    100.00%
+system.ruby.L1Cache_Controller.MM_W.Use_TimeoutStarverS::total           53                      
+system.ruby.L1Cache_Controller.MM_W.Use_TimeoutNoStarvers |       27731     12.41%     12.41% |       28186     12.61%     25.02% |       27900     12.48%     37.50% |       28112     12.58%     50.08% |       27988     12.52%     62.60% |       27857     12.46%     75.06% |       27875     12.47%     87.53% |       27867     12.47%    100.00%
+system.ruby.L1Cache_Controller.MM_W.Use_TimeoutNoStarvers::total       223516                      
+system.ruby.L1Cache_Controller.IM.L1_Replacement |      300828     12.38%     12.38% |      309296     12.73%     25.11% |      302781     12.46%     37.57% |      307942     12.67%     50.24% |      302491     12.45%     62.69% |      302723     12.46%     75.15% |      301437     12.41%     87.55% |      302449     12.45%    100.00%
+system.ruby.L1Cache_Controller.IM.L1_Replacement::total      2429947                      
+system.ruby.L1Cache_Controller.IM.Data_Owner |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           2     66.67%     66.67% |           0      0.00%     66.67% |           0      0.00%     66.67% |           0      0.00%     66.67% |           1     33.33%    100.00%
+system.ruby.L1Cache_Controller.IM.Data_Owner::total            3                      
+system.ruby.L1Cache_Controller.IM.Data_All_Tokens |       27732     12.40%     12.40% |       28185     12.61%     25.01% |       27903     12.48%     37.49% |       28123     12.58%     50.07% |       28000     12.52%     62.59% |       27869     12.47%     75.06% |       27883     12.47%     87.53% |       27875     12.47%    100.00%
+system.ruby.L1Cache_Controller.IM.Data_All_Tokens::total       223570                      
+system.ruby.L1Cache_Controller.IM.Ack    |           1     20.00%     20.00% |           0      0.00%     20.00% |           1     20.00%     40.00% |           0      0.00%     40.00% |           2     40.00%     80.00% |           0      0.00%     80.00% |           0      0.00%     80.00% |           1     20.00%    100.00%
+system.ruby.L1Cache_Controller.IM.Ack::total            5                      
+system.ruby.L1Cache_Controller.IM.Transient_Local_GETX |          72     10.26%     10.26% |          91     12.96%     23.22% |          90     12.82%     36.04% |          89     12.68%     48.72% |          97     13.82%     62.54% |          87     12.39%     74.93% |          93     13.25%     88.18% |          83     11.82%    100.00%
+system.ruby.L1Cache_Controller.IM.Transient_Local_GETX::total          702                      
+system.ruby.L1Cache_Controller.IM.Transient_Local_GETS |         151     11.48%     11.48% |         171     13.00%     24.49% |         164     12.47%     36.96% |         175     13.31%     50.27% |         155     11.79%     62.05% |         156     11.86%     73.92% |         166     12.62%     86.54% |         177     13.46%    100.00%
+system.ruby.L1Cache_Controller.IM.Transient_Local_GETS::total         1315                      
+system.ruby.L1Cache_Controller.IM.Persistent_GETX |          27     10.47%     10.47% |          29     11.24%     21.71% |          37     14.34%     36.05% |          28     10.85%     46.90% |          40     15.50%     62.40% |          29     11.24%     73.64% |          34     13.18%     86.82% |          34     13.18%    100.00%
+system.ruby.L1Cache_Controller.IM.Persistent_GETX::total          258                      
+system.ruby.L1Cache_Controller.IM.Persistent_GETS |          49     11.75%     11.75% |          35      8.39%     20.14% |          45     10.79%     30.94% |          52     12.47%     43.41% |          51     12.23%     55.64% |          70     16.79%     72.42% |          58     13.91%     86.33% |          57     13.67%    100.00%
+system.ruby.L1Cache_Controller.IM.Persistent_GETS::total          417                      
+system.ruby.L1Cache_Controller.IM.Own_Lock_or_Unlock |        5586     12.50%     12.50% |        5689     12.73%     25.22% |        5604     12.54%     37.76% |        5653     12.65%     50.40% |        5575     12.47%     62.87% |        5536     12.38%     75.26% |        5523     12.35%     87.61% |        5538     12.39%    100.00%
+system.ruby.L1Cache_Controller.IM.Own_Lock_or_Unlock::total        44704                      
+system.ruby.L1Cache_Controller.IM.Request_Timeout |       20724     12.08%     12.08% |       21868     12.75%     24.83% |       21815     12.72%     37.55% |       21448     12.50%     50.05% |       21768     12.69%     62.74% |       21311     12.42%     75.16% |       21334     12.44%     87.60% |       21268     12.40%    100.00%
+system.ruby.L1Cache_Controller.IM.Request_Timeout::total       171536                      
+system.ruby.L1Cache_Controller.OM.Ack_All_Tokens |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           2     66.67%     66.67% |           0      0.00%     66.67% |           0      0.00%     66.67% |           0      0.00%     66.67% |           1     33.33%    100.00%
+system.ruby.L1Cache_Controller.OM.Ack_All_Tokens::total            3                      
+system.ruby.L1Cache_Controller.IS.L1_Replacement |      552820     12.53%     12.53% |      551947     12.51%     25.05% |      550867     12.49%     37.54% |      546383     12.39%     49.92% |      555966     12.60%     62.53% |      551042     12.49%     75.02% |      551994     12.51%     87.54% |      549743     12.46%    100.00%
+system.ruby.L1Cache_Controller.IS.L1_Replacement::total      4410762                      
+system.ruby.L1Cache_Controller.IS.Data_Shared |         197     12.14%     12.14% |         187     11.52%     23.66% |         216     13.31%     36.97% |         219     13.49%     50.46% |         195     12.01%     62.48% |         215     13.25%     75.72% |         195     12.01%     87.74% |         199     12.26%    100.00%
+system.ruby.L1Cache_Controller.IS.Data_Shared::total         1623                      
+system.ruby.L1Cache_Controller.IS.Data_Owner |          43     11.98%     11.98% |          44     12.26%     24.23% |          52     14.48%     38.72% |          40     11.14%     49.86% |          41     11.42%     61.28% |          54     15.04%     76.32% |          53     14.76%     91.09% |          32      8.91%    100.00%
 system.ruby.L1Cache_Controller.IS.Data_Owner::total          359                      
-system.ruby.L1Cache_Controller.IS.Data_All_Tokens |       50045     12.55%     12.55% |       49683     12.45%     25.00% |       49970     12.53%     37.53% |       49916     12.51%     50.04% |       49717     12.46%     62.50% |       49963     12.52%     75.03% |       49887     12.51%     87.53% |       49732     12.47%    100.00%
-system.ruby.L1Cache_Controller.IS.Data_All_Tokens::total       398913                      
-system.ruby.L1Cache_Controller.IS.Ack    |           0      0.00%      0.00% |           0      0.00%      0.00% |           1     50.00%     50.00% |           0      0.00%     50.00% |           1     50.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.L1Cache_Controller.IS.Ack::total            2                      
-system.ruby.L1Cache_Controller.IS.Transient_Local_GETX |         152     12.13%     12.13% |         168     13.41%     25.54% |         140     11.17%     36.71% |         160     12.77%     49.48% |         153     12.21%     61.69% |         161     12.85%     74.54% |         153     12.21%     86.75% |         166     13.25%    100.00%
-system.ruby.L1Cache_Controller.IS.Transient_Local_GETX::total         1253                      
-system.ruby.L1Cache_Controller.IS.Transient_Local_GETS |         287     12.04%     12.04% |         298     12.50%     24.54% |         300     12.58%     37.12% |         291     12.21%     49.33% |         322     13.51%     62.84% |         311     13.05%     75.88% |         302     12.67%     88.55% |         273     11.45%    100.00%
-system.ruby.L1Cache_Controller.IS.Transient_Local_GETS::total         2384                      
-system.ruby.L1Cache_Controller.IS.Persistent_GETX |          36      9.07%      9.07% |          37      9.32%     18.39% |          47     11.84%     30.23% |          56     14.11%     44.33% |          49     12.34%     56.68% |          57     14.36%     71.03% |          59     14.86%     85.89% |          56     14.11%    100.00%
-system.ruby.L1Cache_Controller.IS.Persistent_GETX::total          397                      
-system.ruby.L1Cache_Controller.IS.Persistent_GETS |          86     10.87%     10.87% |         112     14.16%     25.03% |          92     11.63%     36.66% |          95     12.01%     48.67% |         105     13.27%     61.95% |         100     12.64%     74.59% |         104     13.15%     87.74% |          97     12.26%    100.00%
-system.ruby.L1Cache_Controller.IS.Persistent_GETS::total          791                      
-system.ruby.L1Cache_Controller.IS.Own_Lock_or_Unlock |        9989     12.48%     12.48% |       10016     12.52%     25.00% |       10115     12.64%     37.64% |        9985     12.48%     50.12% |        9893     12.36%     62.49% |       10088     12.61%     75.09% |        9969     12.46%     87.55% |        9961     12.45%    100.00%
-system.ruby.L1Cache_Controller.IS.Own_Lock_or_Unlock::total        80016                      
-system.ruby.L1Cache_Controller.IS.Request_Timeout |       38867     12.52%     12.52% |       38204     12.31%     24.83% |       38667     12.46%     37.29% |       39766     12.81%     50.11% |       38271     12.33%     62.44% |       39197     12.63%     75.07% |       38932     12.54%     87.61% |       38452     12.39%    100.00%
-system.ruby.L1Cache_Controller.IS.Request_Timeout::total       310356                      
-system.ruby.L1Cache_Controller.I_L.Load  |          84     13.79%     13.79% |          77     12.64%     26.44% |          81     13.30%     39.74% |          64     10.51%     50.25% |          83     13.63%     63.88% |          66     10.84%     74.71% |          66     10.84%     85.55% |          88     14.45%    100.00%
-system.ruby.L1Cache_Controller.I_L.Load::total          609                      
-system.ruby.L1Cache_Controller.I_L.Store |          41     13.40%     13.40% |          33     10.78%     24.18% |          56     18.30%     42.48% |          35     11.44%     53.92% |          37     12.09%     66.01% |          34     11.11%     77.12% |          41     13.40%     90.52% |          29      9.48%    100.00%
+system.ruby.L1Cache_Controller.IS.Data_All_Tokens |       50394     12.52%     12.52% |       50475     12.54%     25.06% |       50165     12.47%     37.53% |       50000     12.42%     49.95% |       50492     12.55%     62.50% |       50447     12.54%     75.04% |       50219     12.48%     87.51% |       50250     12.49%    100.00%
+system.ruby.L1Cache_Controller.IS.Data_All_Tokens::total       402442                      
+system.ruby.L1Cache_Controller.IS.Transient_Local_GETX |         157     11.91%     11.91% |         160     12.14%     24.05% |         142     10.77%     34.83% |         172     13.05%     47.88% |         154     11.68%     59.56% |         148     11.23%     70.79% |         192     14.57%     85.36% |         193     14.64%    100.00%
+system.ruby.L1Cache_Controller.IS.Transient_Local_GETX::total         1318                      
+system.ruby.L1Cache_Controller.IS.Transient_Local_GETS |         293     12.49%     12.49% |         280     11.94%     24.42% |         287     12.23%     36.66% |         306     13.04%     49.70% |         299     12.75%     62.45% |         285     12.15%     74.60% |         314     13.38%     87.98% |         282     12.02%    100.00%
+system.ruby.L1Cache_Controller.IS.Transient_Local_GETS::total         2346                      
+system.ruby.L1Cache_Controller.IS.Persistent_GETX |          46     10.60%     10.60% |          54     12.44%     23.04% |          61     14.06%     37.10% |          49     11.29%     48.39% |          46     10.60%     58.99% |          58     13.36%     72.35% |          62     14.29%     86.64% |          58     13.36%    100.00%
+system.ruby.L1Cache_Controller.IS.Persistent_GETX::total          434                      
+system.ruby.L1Cache_Controller.IS.Persistent_GETS |          83     11.11%     11.11% |          92     12.32%     23.43% |          98     13.12%     36.55% |          87     11.65%     48.19% |          94     12.58%     60.78% |          86     11.51%     72.29% |         115     15.39%     87.68% |          92     12.32%    100.00%
+system.ruby.L1Cache_Controller.IS.Persistent_GETS::total          747                      
+system.ruby.L1Cache_Controller.IS.Own_Lock_or_Unlock |       10066     12.40%     12.40% |       10135     12.49%     24.89% |       10168     12.53%     37.42% |       10107     12.46%     49.88% |       10323     12.72%     62.60% |       10139     12.49%     75.10% |       10091     12.44%     87.53% |       10118     12.47%    100.00%
+system.ruby.L1Cache_Controller.IS.Own_Lock_or_Unlock::total        81147                      
+system.ruby.L1Cache_Controller.IS.Request_Timeout |       39132     12.61%     12.61% |       39345     12.68%     25.28% |       39222     12.64%     37.92% |       39039     12.58%     50.50% |       38571     12.43%     62.92% |       38411     12.37%     75.30% |       38124     12.28%     87.58% |       38551     12.42%    100.00%
+system.ruby.L1Cache_Controller.IS.Request_Timeout::total       310395                      
+system.ruby.L1Cache_Controller.I_L.Load  |          73     12.83%     12.83% |          65     11.42%     24.25% |          69     12.13%     36.38% |          67     11.78%     48.15% |          81     14.24%     62.39% |          77     13.53%     75.92% |          65     11.42%     87.35% |          72     12.65%    100.00%
+system.ruby.L1Cache_Controller.I_L.Load::total          569                      
+system.ruby.L1Cache_Controller.I_L.Store |          44     14.38%     14.38% |          31     10.13%     24.51% |          28      9.15%     33.66% |          47     15.36%     49.02% |          41     13.40%     62.42% |          44     14.38%     76.80% |          37     12.09%     88.89% |          34     11.11%    100.00%
 system.ruby.L1Cache_Controller.I_L.Store::total          306                      
-system.ruby.L1Cache_Controller.I_L.L1_Replacement |         206     10.60%     10.60% |         148      7.61%     18.21% |         234     12.04%     30.25% |         329     16.92%     47.17% |         249     12.81%     59.98% |         203     10.44%     70.42% |         258     13.27%     83.69% |         317     16.31%    100.00%
-system.ruby.L1Cache_Controller.I_L.L1_Replacement::total         1944                      
-system.ruby.L1Cache_Controller.I_L.Data_All_Tokens |          41     25.00%     25.00% |          45     27.44%     52.44% |          23     14.02%     66.46% |          18     10.98%     77.44% |          18     10.98%     88.41% |           8      4.88%     93.29% |           7      4.27%     97.56% |           4      2.44%    100.00%
-system.ruby.L1Cache_Controller.I_L.Data_All_Tokens::total          164                      
-system.ruby.L1Cache_Controller.I_L.Transient_Local_GETX |         221     12.20%     12.20% |         233     12.87%     25.07% |         222     12.26%     37.33% |         225     12.42%     49.75% |         225     12.42%     62.18% |         228     12.59%     74.77% |         230     12.70%     87.47% |         227     12.53%    100.00%
-system.ruby.L1Cache_Controller.I_L.Transient_Local_GETX::total         1811                      
-system.ruby.L1Cache_Controller.I_L.Transient_Local_GETS |         445     12.62%     12.62% |         439     12.45%     25.07% |         441     12.51%     37.58% |         435     12.34%     49.91% |         432     12.25%     62.17% |         455     12.90%     75.07% |         463     13.13%     88.20% |         416     11.80%    100.00%
-system.ruby.L1Cache_Controller.I_L.Transient_Local_GETS::total         3526                      
-system.ruby.L1Cache_Controller.I_L.Persistent_GETX |       40137     12.49%     12.49% |       40125     12.49%     24.98% |       40121     12.49%     37.47% |       40304     12.54%     50.01% |       40099     12.48%     62.49% |       40175     12.50%     75.00% |       40167     12.50%     87.50% |       40156     12.50%    100.00%
-system.ruby.L1Cache_Controller.I_L.Persistent_GETX::total       321284                      
-system.ruby.L1Cache_Controller.I_L.Persistent_GETS |       73854     12.52%     12.52% |       73741     12.50%     25.02% |       73628     12.48%     37.50% |       73761     12.50%     50.01% |       73818     12.51%     62.52% |       73632     12.48%     75.01% |       73718     12.50%     87.50% |       73704     12.50%    100.00%
-system.ruby.L1Cache_Controller.I_L.Persistent_GETS::total       589856                      
-system.ruby.L1Cache_Controller.I_L.Own_Lock_or_Unlock |          57     11.56%     11.56% |          63     12.78%     24.34% |          57     11.56%     35.90% |          71     14.40%     50.30% |          60     12.17%     62.47% |          54     10.95%     73.43% |          66     13.39%     86.82% |          65     13.18%    100.00%
-system.ruby.L1Cache_Controller.I_L.Own_Lock_or_Unlock::total          493                      
-system.ruby.L1Cache_Controller.S_L.L1_Replacement |          42     10.42%     10.42% |          35      8.68%     19.11% |          64     15.88%     34.99% |          55     13.65%     48.64% |          24      5.96%     54.59% |          80     19.85%     74.44% |          47     11.66%     86.10% |          56     13.90%    100.00%
-system.ruby.L1Cache_Controller.S_L.L1_Replacement::total          403                      
-system.ruby.L1Cache_Controller.S_L.Transient_Local_GETX |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           1    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.L1Cache_Controller.S_L.Transient_Local_GETX::total            1                      
-system.ruby.L1Cache_Controller.S_L.Persistent_GETS |           0      0.00%      0.00% |           4      6.35%      6.35% |           7     11.11%     17.46% |           6      9.52%     26.98% |           5      7.94%     34.92% |          17     26.98%     61.90% |          10     15.87%     77.78% |          14     22.22%    100.00%
-system.ruby.L1Cache_Controller.S_L.Persistent_GETS::total           63                      
-system.ruby.L1Cache_Controller.S_L.Own_Lock_or_Unlock |          32      9.04%      9.04% |          43     12.15%     21.19% |          46     12.99%     34.18% |          40     11.30%     45.48% |          45     12.71%     58.19% |          56     15.82%     74.01% |          46     12.99%     87.01% |          46     12.99%    100.00%
-system.ruby.L1Cache_Controller.S_L.Own_Lock_or_Unlock::total          354                      
-system.ruby.L1Cache_Controller.IM_L.L1_Replacement |         616     10.64%     10.64% |         650     11.23%     21.87% |         788     13.61%     35.49% |         576      9.95%     45.44% |         691     11.94%     57.38% |         852     14.72%     72.10% |         843     14.56%     86.66% |         772     13.34%    100.00%
-system.ruby.L1Cache_Controller.IM_L.L1_Replacement::total         5788                      
-system.ruby.L1Cache_Controller.IM_L.Data_All_Tokens |           1      8.33%      8.33% |           1      8.33%     16.67% |           5     41.67%     58.33% |           1      8.33%     66.67% |           1      8.33%     75.00% |           3     25.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.L1Cache_Controller.IM_L.Data_All_Tokens::total           12                      
-system.ruby.L1Cache_Controller.IM_L.Transient_Local_GETX |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           1     33.33%     33.33% |           0      0.00%     33.33% |           1     33.33%     66.67% |           1     33.33%    100.00%
+system.ruby.L1Cache_Controller.I_L.L1_Replacement |         129      6.65%      6.65% |         284     14.64%     21.29% |         163      8.40%     29.69% |         208     10.72%     40.41% |         294     15.15%     55.57% |         224     11.55%     67.11% |         336     17.32%     84.43% |         302     15.57%    100.00%
+system.ruby.L1Cache_Controller.I_L.L1_Replacement::total         1940                      
+system.ruby.L1Cache_Controller.I_L.Data_All_Tokens |          34     22.67%     22.67% |          33     22.00%     44.67% |          22     14.67%     59.33% |          23     15.33%     74.67% |          20     13.33%     88.00% |           9      6.00%     94.00% |           5      3.33%     97.33% |           4      2.67%    100.00%
+system.ruby.L1Cache_Controller.I_L.Data_All_Tokens::total          150                      
+system.ruby.L1Cache_Controller.I_L.Transient_Local_GETX |         218     11.86%     11.86% |         235     12.79%     24.65% |         253     13.76%     38.41% |         223     12.13%     50.54% |         234     12.73%     63.28% |         227     12.35%     75.63% |         231     12.57%     88.19% |         217     11.81%    100.00%
+system.ruby.L1Cache_Controller.I_L.Transient_Local_GETX::total         1838                      
+system.ruby.L1Cache_Controller.I_L.Transient_Local_GETS |         417     12.29%     12.29% |         432     12.74%     25.03% |         441     13.00%     38.03% |         421     12.41%     50.44% |         424     12.50%     62.94% |         414     12.21%     75.15% |         419     12.35%     87.50% |         424     12.50%    100.00%
+system.ruby.L1Cache_Controller.I_L.Transient_Local_GETS::total         3392                      
+system.ruby.L1Cache_Controller.I_L.Persistent_GETX |       41206     12.51%     12.51% |       41068     12.47%     24.99% |       41138     12.49%     37.48% |       41087     12.48%     49.96% |       41184     12.51%     62.46% |       41199     12.51%     74.98% |       41210     12.52%     87.49% |       41190     12.51%    100.00%
+system.ruby.L1Cache_Controller.I_L.Persistent_GETX::total       329282                      
+system.ruby.L1Cache_Controller.I_L.Persistent_GETS |       74847     12.52%     12.52% |       74756     12.51%     25.03% |       74686     12.50%     37.53% |       74789     12.51%     50.04% |       74514     12.47%     62.51% |       74673     12.49%     75.01% |       74669     12.49%     87.50% |       74707     12.50%    100.00%
+system.ruby.L1Cache_Controller.I_L.Persistent_GETS::total       597641                      
+system.ruby.L1Cache_Controller.I_L.Own_Lock_or_Unlock |          51     10.28%     10.28% |          56     11.29%     21.57% |          47      9.48%     31.05% |          68     13.71%     44.76% |          69     13.91%     58.67% |          60     12.10%     70.77% |          70     14.11%     84.88% |          75     15.12%    100.00%
+system.ruby.L1Cache_Controller.I_L.Own_Lock_or_Unlock::total          496                      
+system.ruby.L1Cache_Controller.S_L.L1_Replacement |           5      1.51%      1.51% |          83     25.00%     26.51% |          34     10.24%     36.75% |          12      3.61%     40.36% |          56     16.87%     57.23% |          41     12.35%     69.58% |          41     12.35%     81.93% |          60     18.07%    100.00%
+system.ruby.L1Cache_Controller.S_L.L1_Replacement::total          332                      
+system.ruby.L1Cache_Controller.S_L.Persistent_GETS |           0      0.00%      0.00% |           3      4.84%      4.84% |           2      3.23%      8.06% |           0      0.00%      8.06% |           9     14.52%     22.58% |          11     17.74%     40.32% |          18     29.03%     69.35% |          19     30.65%    100.00%
+system.ruby.L1Cache_Controller.S_L.Persistent_GETS::total           62                      
+system.ruby.L1Cache_Controller.S_L.Own_Lock_or_Unlock |          42     11.76%     11.76% |          46     12.89%     24.65% |          49     13.73%     38.38% |          40     11.20%     49.58% |          50     14.01%     63.59% |          35      9.80%     73.39% |          51     14.29%     87.68% |          44     12.32%    100.00%
+system.ruby.L1Cache_Controller.S_L.Own_Lock_or_Unlock::total          357                      
+system.ruby.L1Cache_Controller.IM_L.L1_Replacement |         710     11.66%     11.66% |         553      9.08%     20.74% |         675     11.08%     31.82% |         757     12.43%     44.25% |         762     12.51%     56.76% |         889     14.60%     71.35% |         956     15.70%     87.05% |         789     12.95%    100.00%
+system.ruby.L1Cache_Controller.IM_L.L1_Replacement::total         6091                      
+system.ruby.L1Cache_Controller.IM_L.Data_All_Tokens |           2     18.18%     18.18% |           1      9.09%     27.27% |           1      9.09%     36.36% |           1      9.09%     45.45% |           2     18.18%     63.64% |           0      0.00%     63.64% |           2     18.18%     81.82% |           2     18.18%    100.00%
+system.ruby.L1Cache_Controller.IM_L.Data_All_Tokens::total           11                      
+system.ruby.L1Cache_Controller.IM_L.Transient_Local_GETX |           1     33.33%     33.33% |           1     33.33%     66.67% |           0      0.00%     66.67% |           1     33.33%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.L1Cache_Controller.IM_L.Transient_Local_GETX::total            3                      
-system.ruby.L1Cache_Controller.IM_L.Transient_Local_GETS |           0      0.00%      0.00% |           1     20.00%     20.00% |           1     20.00%     40.00% |           2     40.00%     80.00% |           0      0.00%     80.00% |           0      0.00%     80.00% |           0      0.00%     80.00% |           1     20.00%    100.00%
-system.ruby.L1Cache_Controller.IM_L.Transient_Local_GETS::total            5                      
-system.ruby.L1Cache_Controller.IM_L.Persistent_GETX |           0      0.00%      0.00% |           3      6.67%      6.67% |           2      4.44%     11.11% |           4      8.89%     20.00% |          10     22.22%     42.22% |          10     22.22%     64.44% |          10     22.22%     86.67% |           6     13.33%    100.00%
-system.ruby.L1Cache_Controller.IM_L.Persistent_GETX::total           45                      
-system.ruby.L1Cache_Controller.IM_L.Persistent_GETS |           0      0.00%      0.00% |           2      2.00%      2.00% |           7      7.00%      9.00% |          11     11.00%     20.00% |          13     13.00%     33.00% |          15     15.00%     48.00% |          23     23.00%     71.00% |          29     29.00%    100.00%
-system.ruby.L1Cache_Controller.IM_L.Persistent_GETS::total          100                      
-system.ruby.L1Cache_Controller.IM_L.Own_Lock_or_Unlock |         105     11.84%     11.84% |          98     11.05%     22.89% |         123     13.87%     36.75% |         103     11.61%     48.37% |         110     12.40%     60.77% |         117     13.19%     73.96% |         120     13.53%     87.49% |         111     12.51%    100.00%
-system.ruby.L1Cache_Controller.IM_L.Own_Lock_or_Unlock::total          887                      
-system.ruby.L1Cache_Controller.IM_L.Request_Timeout |          92      8.01%      8.01% |         153     13.33%     21.34% |         130     11.32%     32.67% |         128     11.15%     43.82% |         153     13.33%     57.14% |         194     16.90%     74.04% |         147     12.80%     86.85% |         151     13.15%    100.00%
-system.ruby.L1Cache_Controller.IM_L.Request_Timeout::total         1148                      
-system.ruby.L1Cache_Controller.IS_L.L1_Replacement |        1362     11.37%     11.37% |        1369     11.42%     22.79% |        1430     11.93%     34.72% |        1388     11.58%     46.31% |        1490     12.43%     58.74% |        1388     11.58%     70.32% |        1535     12.81%     83.13% |        2021     16.87%    100.00%
-system.ruby.L1Cache_Controller.IS_L.L1_Replacement::total        11983                      
-system.ruby.L1Cache_Controller.IS_L.Data_Shared |           1     33.33%     33.33% |           0      0.00%     33.33% |           0      0.00%     33.33% |           0      0.00%     33.33% |           0      0.00%     33.33% |           1     33.33%     66.67% |           0      0.00%     66.67% |           1     33.33%    100.00%
-system.ruby.L1Cache_Controller.IS_L.Data_Shared::total            3                      
-system.ruby.L1Cache_Controller.IS_L.Data_All_Tokens |           1      5.56%      5.56% |           0      0.00%      5.56% |           2     11.11%     16.67% |           3     16.67%     33.33% |           2     11.11%     44.44% |           3     16.67%     61.11% |           5     27.78%     88.89% |           2     11.11%    100.00%
-system.ruby.L1Cache_Controller.IS_L.Data_All_Tokens::total           18                      
-system.ruby.L1Cache_Controller.IS_L.Transient_Local_GETX |           0      0.00%      0.00% |           1     33.33%     33.33% |           1     33.33%     66.67% |           0      0.00%     66.67% |           0      0.00%     66.67% |           0      0.00%     66.67% |           0      0.00%     66.67% |           1     33.33%    100.00%
+system.ruby.L1Cache_Controller.IM_L.Transient_Local_GETS |           2     33.33%     33.33% |           1     16.67%     50.00% |           0      0.00%     50.00% |           0      0.00%     50.00% |           0      0.00%     50.00% |           2     33.33%     83.33% |           1     16.67%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache_Controller.IM_L.Transient_Local_GETS::total            6                      
+system.ruby.L1Cache_Controller.IM_L.Persistent_GETX |           0      0.00%      0.00% |           3      4.55%      4.55% |           2      3.03%      7.58% |           7     10.61%     18.18% |          11     16.67%     34.85% |          14     21.21%     56.06% |          16     24.24%     80.30% |          13     19.70%    100.00%
+system.ruby.L1Cache_Controller.IM_L.Persistent_GETX::total           66                      
+system.ruby.L1Cache_Controller.IM_L.Persistent_GETS |           0      0.00%      0.00% |           0      0.00%      0.00% |           4      4.88%      4.88% |           9     10.98%     15.85% |          14     17.07%     32.93% |          23     28.05%     60.98% |          11     13.41%     74.39% |          21     25.61%    100.00%
+system.ruby.L1Cache_Controller.IM_L.Persistent_GETS::total           82                      
+system.ruby.L1Cache_Controller.IM_L.Own_Lock_or_Unlock |         118     12.16%     12.16% |          94      9.69%     21.86% |         109     11.24%     33.09% |         126     12.99%     46.08% |         130     13.40%     59.48% |         143     14.74%     74.23% |         127     13.09%     87.32% |         123     12.68%    100.00%
+system.ruby.L1Cache_Controller.IM_L.Own_Lock_or_Unlock::total          970                      
+system.ruby.L1Cache_Controller.IM_L.Request_Timeout |         114      9.64%      9.64% |         186     15.72%     25.36% |         156     13.19%     38.55% |         163     13.78%     52.32% |         190     16.06%     68.39% |         134     11.33%     79.71% |          73      6.17%     85.88% |         167     14.12%    100.00%
+system.ruby.L1Cache_Controller.IM_L.Request_Timeout::total         1183                      
+system.ruby.L1Cache_Controller.IS_L.L1_Replacement |         935      8.62%      8.62% |        1162     10.71%     19.34% |        1146     10.57%     29.90% |        1262     11.64%     41.54% |        1378     12.71%     54.25% |        1777     16.39%     70.63% |        1589     14.65%     85.28% |        1596     14.72%    100.00%
+system.ruby.L1Cache_Controller.IS_L.L1_Replacement::total        10845                      
+system.ruby.L1Cache_Controller.IS_L.Data_Shared |           0      0.00%      0.00% |           1     25.00%     25.00% |           0      0.00%     25.00% |           1     25.00%     50.00% |           0      0.00%     50.00% |           1     25.00%     75.00% |           0      0.00%     75.00% |           1     25.00%    100.00%
+system.ruby.L1Cache_Controller.IS_L.Data_Shared::total            4                      
+system.ruby.L1Cache_Controller.IS_L.Data_All_Tokens |           1      5.00%      5.00% |           0      0.00%      5.00% |           2     10.00%     15.00% |           2     10.00%     25.00% |           3     15.00%     40.00% |           4     20.00%     60.00% |           5     25.00%     85.00% |           3     15.00%    100.00%
+system.ruby.L1Cache_Controller.IS_L.Data_All_Tokens::total           20                      
+system.ruby.L1Cache_Controller.IS_L.Transient_Local_GETX |           0      0.00%      0.00% |           1     33.33%     33.33% |           0      0.00%     33.33% |           0      0.00%     33.33% |           0      0.00%     33.33% |           1     33.33%     66.67% |           1     33.33%    100.00% |           0      0.00%    100.00%
 system.ruby.L1Cache_Controller.IS_L.Transient_Local_GETX::total            3                      
-system.ruby.L1Cache_Controller.IS_L.Transient_Local_GETS |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           2     50.00%     50.00% |           0      0.00%     50.00% |           0      0.00%     50.00% |           0      0.00%     50.00% |           2     50.00%    100.00%
-system.ruby.L1Cache_Controller.IS_L.Transient_Local_GETS::total            4                      
-system.ruby.L1Cache_Controller.IS_L.Persistent_GETX |           0      0.00%      0.00% |           2      2.04%      2.04% |          11     11.22%     13.27% |          14     14.29%     27.55% |           9      9.18%     36.73% |          13     13.27%     50.00% |          24     24.49%     74.49% |          25     25.51%    100.00%
-system.ruby.L1Cache_Controller.IS_L.Persistent_GETX::total           98                      
-system.ruby.L1Cache_Controller.IS_L.Persistent_GETS |           0      0.00%      0.00% |          11      6.92%      6.92% |           5      3.14%     10.06% |          18     11.32%     21.38% |          24     15.09%     36.48% |          24     15.09%     51.57% |          36     22.64%     74.21% |          41     25.79%    100.00%
-system.ruby.L1Cache_Controller.IS_L.Persistent_GETS::total          159                      
-system.ruby.L1Cache_Controller.IS_L.Own_Lock_or_Unlock |         204     11.49%     11.49% |         226     12.73%     24.21% |         218     12.27%     36.49% |         212     11.94%     48.42% |         235     13.23%     61.66% |         219     12.33%     73.99% |         224     12.61%     86.60% |         238     13.40%    100.00%
-system.ruby.L1Cache_Controller.IS_L.Own_Lock_or_Unlock::total         1776                      
-system.ruby.L1Cache_Controller.IS_L.Request_Timeout |         277     13.71%     13.71% |         242     11.97%     25.68% |         190      9.40%     35.08% |         265     13.11%     48.19% |         341     16.87%     65.07% |         233     11.53%     76.60% |         222     10.98%     87.58% |         251     12.42%    100.00%
-system.ruby.L1Cache_Controller.IS_L.Request_Timeout::total         2021                      
-system.ruby.L2Cache_Controller.L1_GETS         401048      0.00%      0.00%
+system.ruby.L1Cache_Controller.IS_L.Transient_Local_GETS |           1     14.29%     14.29% |           1     14.29%     28.57% |           1     14.29%     42.86% |           1     14.29%     57.14% |           1     14.29%     71.43% |           1     14.29%     85.71% |           1     14.29%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache_Controller.IS_L.Transient_Local_GETS::total            7                      
+system.ruby.L1Cache_Controller.IS_L.Persistent_GETX |           0      0.00%      0.00% |           7      6.25%      6.25% |          12     10.71%     16.96% |          10      8.93%     25.89% |          11      9.82%     35.71% |          21     18.75%     54.46% |          26     23.21%     77.68% |          25     22.32%    100.00%
+system.ruby.L1Cache_Controller.IS_L.Persistent_GETX::total          112                      
+system.ruby.L1Cache_Controller.IS_L.Persistent_GETS |           0      0.00%      0.00% |           5      3.70%      3.70% |          11      8.15%     11.85% |           7      5.19%     17.04% |          13      9.63%     26.67% |          22     16.30%     42.96% |          41     30.37%     73.33% |          36     26.67%    100.00%
+system.ruby.L1Cache_Controller.IS_L.Persistent_GETS::total          135                      
+system.ruby.L1Cache_Controller.IS_L.Own_Lock_or_Unlock |         201     11.65%     11.65% |         210     12.17%     23.81% |         226     13.09%     36.91% |         200     11.59%     48.49% |         218     12.63%     61.12% |         216     12.51%     73.64% |         237     13.73%     87.37% |         218     12.63%    100.00%
+system.ruby.L1Cache_Controller.IS_L.Own_Lock_or_Unlock::total         1726                      
+system.ruby.L1Cache_Controller.IS_L.Request_Timeout |         228     10.77%     10.77% |         319     15.07%     25.84% |         369     17.43%     43.27% |         258     12.19%     55.46% |         197      9.31%     64.76% |         201      9.49%     74.26% |         272     12.85%     87.10% |         273     12.90%    100.00%
+system.ruby.L1Cache_Controller.IS_L.Request_Timeout::total         2117                      
+system.ruby.L2Cache_Controller.L1_GETS         404457      0.00%      0.00%
 system.ruby.L2Cache_Controller.L1_GETS_Last_Token            3      0.00%      0.00%
-system.ruby.L2Cache_Controller.L1_GETX         215772      0.00%      0.00%
-system.ruby.L2Cache_Controller.L1_INV            1395      0.00%      0.00%
-system.ruby.L2Cache_Controller.L2_Replacement       583206      0.00%      0.00%
-system.ruby.L2Cache_Controller.Writeback_Shared_Data         1451      0.00%      0.00%
-system.ruby.L2Cache_Controller.Writeback_All_Tokens       613102      0.00%      0.00%
-system.ruby.L2Cache_Controller.Writeback_Owned          843      0.00%      0.00%
-system.ruby.L2Cache_Controller.Persistent_GETX        46049      0.00%      0.00%
-system.ruby.L2Cache_Controller.Persistent_GETS        84554      0.00%      0.00%
-system.ruby.L2Cache_Controller.Own_Lock_or_Unlock       129089      0.00%      0.00%
-system.ruby.L2Cache_Controller.NP.L1_GETS       399363      0.00%      0.00%
-system.ruby.L2Cache_Controller.NP.L1_GETX       214874      0.00%      0.00%
-system.ruby.L2Cache_Controller.NP.L1_INV          909      0.00%      0.00%
-system.ruby.L2Cache_Controller.NP.Writeback_Shared_Data         1386      0.00%      0.00%
-system.ruby.L2Cache_Controller.NP.Writeback_All_Tokens       581094      0.00%      0.00%
-system.ruby.L2Cache_Controller.NP.Writeback_Owned          734      0.00%      0.00%
-system.ruby.L2Cache_Controller.NP.Own_Lock_or_Unlock       128754      0.00%      0.00%
-system.ruby.L2Cache_Controller.I.L1_GETS            2      0.00%      0.00%
-system.ruby.L2Cache_Controller.I.L1_INV             2      0.00%      0.00%
-system.ruby.L2Cache_Controller.I.L2_Replacement          559      0.00%      0.00%
-system.ruby.L2Cache_Controller.I.Writeback_All_Tokens          366      0.00%      0.00%
-system.ruby.L2Cache_Controller.I.Writeback_Owned            2      0.00%      0.00%
+system.ruby.L2Cache_Controller.L1_GETX         223591      0.00%      0.00%
+system.ruby.L2Cache_Controller.L1_INV            1379      0.00%      0.00%
+system.ruby.L2Cache_Controller.L2_Replacement       594493      0.00%      0.00%
+system.ruby.L2Cache_Controller.Writeback_Shared_Data         1349      0.00%      0.00%
+system.ruby.L2Cache_Controller.Writeback_All_Tokens       624482      0.00%      0.00%
+system.ruby.L2Cache_Controller.Writeback_Owned          809      0.00%      0.00%
+system.ruby.L2Cache_Controller.Persistent_GETX        47208      0.00%      0.00%
+system.ruby.L2Cache_Controller.Persistent_GETS        85660      0.00%      0.00%
+system.ruby.L2Cache_Controller.Own_Lock_or_Unlock       131330      0.00%      0.00%
+system.ruby.L2Cache_Controller.NP.L1_GETS       402910      0.00%      0.00%
+system.ruby.L2Cache_Controller.NP.L1_GETX       222716      0.00%      0.00%
+system.ruby.L2Cache_Controller.NP.L1_INV          890      0.00%      0.00%
+system.ruby.L2Cache_Controller.NP.Writeback_Shared_Data         1290      0.00%      0.00%
+system.ruby.L2Cache_Controller.NP.Writeback_All_Tokens       592515      0.00%      0.00%
+system.ruby.L2Cache_Controller.NP.Writeback_Owned          696      0.00%      0.00%
+system.ruby.L2Cache_Controller.NP.Own_Lock_or_Unlock       130991      0.00%      0.00%
+system.ruby.L2Cache_Controller.I.L1_INV             1      0.00%      0.00%
+system.ruby.L2Cache_Controller.I.L2_Replacement          531      0.00%      0.00%
+system.ruby.L2Cache_Controller.I.Writeback_All_Tokens          360      0.00%      0.00%
+system.ruby.L2Cache_Controller.I.Writeback_Owned            3      0.00%      0.00%
+system.ruby.L2Cache_Controller.I.Persistent_GETX            1      0.00%      0.00%
+system.ruby.L2Cache_Controller.I.Persistent_GETS            1      0.00%      0.00%
 system.ruby.L2Cache_Controller.S.L1_GETS_Last_Token            3      0.00%      0.00%
 system.ruby.L2Cache_Controller.S.L1_GETX            1      0.00%      0.00%
-system.ruby.L2Cache_Controller.S.L2_Replacement         1209      0.00%      0.00%
-system.ruby.L2Cache_Controller.S.Writeback_Shared_Data            5      0.00%      0.00%
-system.ruby.L2Cache_Controller.S.Writeback_All_Tokens          176      0.00%      0.00%
-system.ruby.L2Cache_Controller.S.Persistent_GETX            2      0.00%      0.00%
-system.ruby.L2Cache_Controller.O.L1_GETS           13      0.00%      0.00%
-system.ruby.L2Cache_Controller.O.L1_GETX            3      0.00%      0.00%
-system.ruby.L2Cache_Controller.O.L2_Replacement         1168      0.00%      0.00%
-system.ruby.L2Cache_Controller.O.Writeback_Shared_Data            7      0.00%      0.00%
-system.ruby.L2Cache_Controller.O.Writeback_All_Tokens          633      0.00%      0.00%
-system.ruby.L2Cache_Controller.O.Persistent_GETX            1      0.00%      0.00%
-system.ruby.L2Cache_Controller.O.Persistent_GETS            6      0.00%      0.00%
-system.ruby.L2Cache_Controller.M.L1_GETS         1075      0.00%      0.00%
-system.ruby.L2Cache_Controller.M.L1_GETX          590      0.00%      0.00%
-system.ruby.L2Cache_Controller.M.L2_Replacement       579287      0.00%      0.00%
-system.ruby.L2Cache_Controller.M.Persistent_GETX          460      0.00%      0.00%
-system.ruby.L2Cache_Controller.M.Persistent_GETS          849      0.00%      0.00%
-system.ruby.L2Cache_Controller.I_L.L1_GETS          595      0.00%      0.00%
-system.ruby.L2Cache_Controller.I_L.L1_GETX          304      0.00%      0.00%
-system.ruby.L2Cache_Controller.I_L.L1_INV          484      0.00%      0.00%
-system.ruby.L2Cache_Controller.I_L.L2_Replacement          982      0.00%      0.00%
-system.ruby.L2Cache_Controller.I_L.Writeback_Shared_Data           53      0.00%      0.00%
-system.ruby.L2Cache_Controller.I_L.Writeback_All_Tokens        30833      0.00%      0.00%
-system.ruby.L2Cache_Controller.I_L.Writeback_Owned          107      0.00%      0.00%
-system.ruby.L2Cache_Controller.I_L.Persistent_GETX        45586      0.00%      0.00%
-system.ruby.L2Cache_Controller.I_L.Persistent_GETS        83699      0.00%      0.00%
-system.ruby.L2Cache_Controller.I_L.Own_Lock_or_Unlock          330      0.00%      0.00%
-system.ruby.L2Cache_Controller.S_L.L2_Replacement            1      0.00%      0.00%
-system.ruby.L2Cache_Controller.S_L.Own_Lock_or_Unlock            5      0.00%      0.00%
-system.ruby.Directory_Controller.GETX          255487      0.00%      0.00%
-system.ruby.Directory_Controller.GETS          476933      0.00%      0.00%
-system.ruby.Directory_Controller.Lockdown       130603      0.00%      0.00%
-system.ruby.Directory_Controller.Unlockdown       129089      0.00%      0.00%
-system.ruby.Directory_Controller.Data_Owner          344      0.00%      0.00%
-system.ruby.Directory_Controller.Data_All_Tokens       235610      0.00%      0.00%
-system.ruby.Directory_Controller.Ack_Owner          694      0.00%      0.00%
-system.ruby.Directory_Controller.Ack_Owner_All_Tokens       375677      0.00%      0.00%
-system.ruby.Directory_Controller.Tokens           456      0.00%      0.00%
-system.ruby.Directory_Controller.Ack_All_Tokens         3709      0.00%      0.00%
-system.ruby.Directory_Controller.Memory_Data       610582      0.00%      0.00%
-system.ruby.Directory_Controller.Memory_Ack       234338      0.00%      0.00%
-system.ruby.Directory_Controller.O.GETX        212118      0.00%      0.00%
-system.ruby.Directory_Controller.O.GETS        394360      0.00%      0.00%
-system.ruby.Directory_Controller.O.Lockdown         2461      0.00%      0.00%
-system.ruby.Directory_Controller.O.Data_All_Tokens           49      0.00%      0.00%
-system.ruby.Directory_Controller.O.Tokens            4      0.00%      0.00%
-system.ruby.Directory_Controller.O.Ack_All_Tokens          967      0.00%      0.00%
-system.ruby.Directory_Controller.NO.GETX         2212      0.00%      0.00%
-system.ruby.Directory_Controller.NO.GETS         3891      0.00%      0.00%
-system.ruby.Directory_Controller.NO.Lockdown        20370      0.00%      0.00%
-system.ruby.Directory_Controller.NO.Data_Owner          344      0.00%      0.00%
-system.ruby.Directory_Controller.NO.Data_All_Tokens       233998      0.00%      0.00%
-system.ruby.Directory_Controller.NO.Ack_Owner          694      0.00%      0.00%
-system.ruby.Directory_Controller.NO.Ack_Owner_All_Tokens       375526      0.00%      0.00%
-system.ruby.Directory_Controller.NO.Tokens          248      0.00%      0.00%
-system.ruby.Directory_Controller.L.GETX           852      0.00%      0.00%
-system.ruby.Directory_Controller.L.GETS          1708      0.00%      0.00%
-system.ruby.Directory_Controller.L.Lockdown         1080      0.00%      0.00%
-system.ruby.Directory_Controller.L.Unlockdown       129089      0.00%      0.00%
-system.ruby.Directory_Controller.L.Data_All_Tokens          106      0.00%      0.00%
-system.ruby.Directory_Controller.L.Ack_Owner_All_Tokens          151      0.00%      0.00%
+system.ruby.L2Cache_Controller.S.L2_Replacement         1099      0.00%      0.00%
+system.ruby.L2Cache_Controller.S.Writeback_Shared_Data            3      0.00%      0.00%
+system.ruby.L2Cache_Controller.S.Writeback_All_Tokens          188      0.00%      0.00%
+system.ruby.L2Cache_Controller.S.Writeback_Owned            2      0.00%      0.00%
+system.ruby.L2Cache_Controller.S.Persistent_GETS            1      0.00%      0.00%
+system.ruby.L2Cache_Controller.O.L1_GETS            4      0.00%      0.00%
+system.ruby.L2Cache_Controller.O.L1_GETX            2      0.00%      0.00%
+system.ruby.L2Cache_Controller.O.L2_Replacement         1049      0.00%      0.00%
+system.ruby.L2Cache_Controller.O.Writeback_Shared_Data            1      0.00%      0.00%
+system.ruby.L2Cache_Controller.O.Writeback_All_Tokens          625      0.00%      0.00%
+system.ruby.L2Cache_Controller.O.Persistent_GETS            3      0.00%      0.00%
+system.ruby.L2Cache_Controller.M.L1_GETS          978      0.00%      0.00%
+system.ruby.L2Cache_Controller.M.L1_GETX          555      0.00%      0.00%
+system.ruby.L2Cache_Controller.M.L2_Replacement       590843      0.00%      0.00%
+system.ruby.L2Cache_Controller.M.Persistent_GETX          445      0.00%      0.00%
+system.ruby.L2Cache_Controller.M.Persistent_GETS          859      0.00%      0.00%
+system.ruby.L2Cache_Controller.I_L.L1_GETS          565      0.00%      0.00%
+system.ruby.L2Cache_Controller.I_L.L1_GETX          317      0.00%      0.00%
+system.ruby.L2Cache_Controller.I_L.L1_INV          487      0.00%      0.00%
+system.ruby.L2Cache_Controller.I_L.L2_Replacement          971      0.00%      0.00%
+system.ruby.L2Cache_Controller.I_L.Writeback_Shared_Data           55      0.00%      0.00%
+system.ruby.L2Cache_Controller.I_L.Writeback_All_Tokens        30794      0.00%      0.00%
+system.ruby.L2Cache_Controller.I_L.Writeback_Owned          108      0.00%      0.00%
+system.ruby.L2Cache_Controller.I_L.Persistent_GETX        46762      0.00%      0.00%
+system.ruby.L2Cache_Controller.I_L.Persistent_GETS        84796      0.00%      0.00%
+system.ruby.L2Cache_Controller.I_L.Own_Lock_or_Unlock          335      0.00%      0.00%
+system.ruby.L2Cache_Controller.S_L.L1_INV            1      0.00%      0.00%
+system.ruby.L2Cache_Controller.S_L.Own_Lock_or_Unlock            4      0.00%      0.00%
+system.ruby.Directory_Controller.GETX          263101      0.00%      0.00%
+system.ruby.Directory_Controller.GETS          477895      0.00%      0.00%
+system.ruby.Directory_Controller.Lockdown       132868      0.00%      0.00%
+system.ruby.Directory_Controller.Unlockdown       131330      0.00%      0.00%
+system.ruby.Directory_Controller.Data_Owner          346      0.00%      0.00%
+system.ruby.Directory_Controller.Data_All_Tokens       243507      0.00%      0.00%
+system.ruby.Directory_Controller.Ack_Owner          579      0.00%      0.00%
+system.ruby.Directory_Controller.Ack_Owner_All_Tokens       379354      0.00%      0.00%
+system.ruby.Directory_Controller.Tokens           299      0.00%      0.00%
+system.ruby.Directory_Controller.Ack_All_Tokens         3429      0.00%      0.00%
+system.ruby.Directory_Controller.Memory_Data       622028      0.00%      0.00%
+system.ruby.Directory_Controller.Memory_Ack       242193      0.00%      0.00%
+system.ruby.Directory_Controller.O.GETX        219976      0.00%      0.00%
+system.ruby.Directory_Controller.O.GETS        397919      0.00%      0.00%
+system.ruby.Directory_Controller.O.Lockdown         2510      0.00%      0.00%
+system.ruby.Directory_Controller.O.Data_All_Tokens           52      0.00%      0.00%
+system.ruby.Directory_Controller.O.Tokens            2      0.00%      0.00%
+system.ruby.Directory_Controller.O.Ack_All_Tokens          864      0.00%      0.00%
+system.ruby.Directory_Controller.NO.GETX         2155      0.00%      0.00%
+system.ruby.Directory_Controller.NO.GETS         3924      0.00%      0.00%
+system.ruby.Directory_Controller.NO.Lockdown        20743      0.00%      0.00%
+system.ruby.Directory_Controller.NO.Data_Owner          346      0.00%      0.00%
+system.ruby.Directory_Controller.NO.Data_All_Tokens       241851      0.00%      0.00%
+system.ruby.Directory_Controller.NO.Ack_Owner          579      0.00%      0.00%
+system.ruby.Directory_Controller.NO.Ack_Owner_All_Tokens       379230      0.00%      0.00%
+system.ruby.Directory_Controller.NO.Tokens          238      0.00%      0.00%
+system.ruby.Directory_Controller.L.GETX           905      0.00%      0.00%
+system.ruby.Directory_Controller.L.GETS          1631      0.00%      0.00%
+system.ruby.Directory_Controller.L.Lockdown         1114      0.00%      0.00%
+system.ruby.Directory_Controller.L.Unlockdown       131330      0.00%      0.00%
+system.ruby.Directory_Controller.L.Data_All_Tokens           93      0.00%      0.00%
+system.ruby.Directory_Controller.L.Ack_Owner_All_Tokens          124      0.00%      0.00%
 system.ruby.Directory_Controller.L.Tokens            3      0.00%      0.00%
-system.ruby.Directory_Controller.O_W.GETX        13301      0.00%      0.00%
-system.ruby.Directory_Controller.O_W.GETS        26689      0.00%      0.00%
-system.ruby.Directory_Controller.O_W.Lockdown         1663      0.00%      0.00%
-system.ruby.Directory_Controller.O_W.Data_All_Tokens         1388      0.00%      0.00%
-system.ruby.Directory_Controller.O_W.Tokens          201      0.00%      0.00%
-system.ruby.Directory_Controller.O_W.Ack_All_Tokens         2722      0.00%      0.00%
-system.ruby.Directory_Controller.O_W.Memory_Ack       232675      0.00%      0.00%
-system.ruby.Directory_Controller.L_O_W.GETX         6131      0.00%      0.00%
-system.ruby.Directory_Controller.L_O_W.GETS        13880      0.00%      0.00%
-system.ruby.Directory_Controller.L_O_W.Lockdown           30      0.00%      0.00%
-system.ruby.Directory_Controller.L_O_W.Data_All_Tokens           69      0.00%      0.00%
-system.ruby.Directory_Controller.L_O_W.Memory_Data         4123      0.00%      0.00%
-system.ruby.Directory_Controller.L_O_W.Memory_Ack         1663      0.00%      0.00%
-system.ruby.Directory_Controller.L_NO_W.GETX         5886      0.00%      0.00%
-system.ruby.Directory_Controller.L_NO_W.GETS        10623      0.00%      0.00%
-system.ruby.Directory_Controller.L_NO_W.Lockdown          398      0.00%      0.00%
-system.ruby.Directory_Controller.L_NO_W.Memory_Data       104596      0.00%      0.00%
-system.ruby.Directory_Controller.NO_W.GETX        14987      0.00%      0.00%
-system.ruby.Directory_Controller.NO_W.GETS        25782      0.00%      0.00%
-system.ruby.Directory_Controller.NO_W.Lockdown       104601      0.00%      0.00%
-system.ruby.Directory_Controller.NO_W.Ack_All_Tokens           20      0.00%      0.00%
-system.ruby.Directory_Controller.NO_W.Memory_Data       501863      0.00%      0.00%
+system.ruby.Directory_Controller.O_W.GETX        13508      0.00%      0.00%
+system.ruby.Directory_Controller.O_W.GETS        25780      0.00%      0.00%
+system.ruby.Directory_Controller.O_W.Lockdown         1640      0.00%      0.00%
+system.ruby.Directory_Controller.O_W.Data_All_Tokens         1511      0.00%      0.00%
+system.ruby.Directory_Controller.O_W.Tokens           54      0.00%      0.00%
+system.ruby.Directory_Controller.O_W.Ack_All_Tokens         2445      0.00%      0.00%
+system.ruby.Directory_Controller.O_W.Memory_Ack       240553      0.00%      0.00%
+system.ruby.Directory_Controller.L_O_W.GETX         5952      0.00%      0.00%
+system.ruby.Directory_Controller.L_O_W.GETS        11594      0.00%      0.00%
+system.ruby.Directory_Controller.L_O_W.Lockdown           34      0.00%      0.00%
+system.ruby.Directory_Controller.L_O_W.Ack_All_Tokens           45      0.00%      0.00%
+system.ruby.Directory_Controller.L_O_W.Memory_Data         4150      0.00%      0.00%
+system.ruby.Directory_Controller.L_O_W.Memory_Ack         1640      0.00%      0.00%
+system.ruby.Directory_Controller.L_NO_W.GETX         5644      0.00%      0.00%
+system.ruby.Directory_Controller.L_NO_W.GETS         9783      0.00%      0.00%
+system.ruby.Directory_Controller.L_NO_W.Lockdown          384      0.00%      0.00%
+system.ruby.Directory_Controller.L_NO_W.Ack_All_Tokens           33      0.00%      0.00%
+system.ruby.Directory_Controller.L_NO_W.Memory_Data       106440      0.00%      0.00%
+system.ruby.Directory_Controller.NO_W.GETX        14961      0.00%      0.00%
+system.ruby.Directory_Controller.NO_W.GETS        27264      0.00%      0.00%
+system.ruby.Directory_Controller.NO_W.Lockdown       106443      0.00%      0.00%
+system.ruby.Directory_Controller.NO_W.Tokens            2      0.00%      0.00%
+system.ruby.Directory_Controller.NO_W.Ack_All_Tokens           42      0.00%      0.00%
+system.ruby.Directory_Controller.NO_W.Memory_Data       511438      0.00%      0.00%
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt
index c7c9aeb58..2a34715b3 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt
@@ -1,1242 +1,1247 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.005796                       # Number of seconds simulated
-sim_ticks                                     5795833                       # Number of ticks simulated
-final_tick                                    5795833                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.005921                       # Number of seconds simulated
+sim_ticks                                     5920895                       # Number of ticks simulated
+final_tick                                    5920895                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_tick_rate                                  66984                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 260008                       # Number of bytes of host memory used
-host_seconds                                    86.53                       # Real time elapsed on the host
+host_tick_rate                                  58624                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 293400                       # Number of bytes of host memory used
+host_seconds                                   101.00                       # Real time elapsed on the host
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                             1                       # Clock period in ticks
 system.ruby.clk_domain.clock                        1                       # Clock period in ticks
 system.ruby.outstanding_req_hist::bucket_size            2                      
 system.ruby.outstanding_req_hist::max_bucket           19                      
-system.ruby.outstanding_req_hist::samples       618244                      
-system.ruby.outstanding_req_hist::mean      15.998447                      
-system.ruby.outstanding_req_hist::gmean     15.997166                      
-system.ruby.outstanding_req_hist::stdev      0.126661                      
-system.ruby.outstanding_req_hist         |           8      0.00%      0.00% |          16      0.00%      0.00% |          16      0.00%      0.01% |          16      0.00%      0.01% |          16      0.00%      0.01% |          16      0.00%      0.01% |          16      0.00%      0.02% |          16      0.00%      0.02% |      618124     99.98%    100.00% |           0      0.00%    100.00%
-system.ruby.outstanding_req_hist::total        618244                      
+system.ruby.outstanding_req_hist::samples       629183                      
+system.ruby.outstanding_req_hist::mean      15.998474                      
+system.ruby.outstanding_req_hist::gmean     15.997215                      
+system.ruby.outstanding_req_hist::stdev      0.125555                      
+system.ruby.outstanding_req_hist         |           8      0.00%      0.00% |          16      0.00%      0.00% |          16      0.00%      0.01% |          16      0.00%      0.01% |          16      0.00%      0.01% |          16      0.00%      0.01% |          16      0.00%      0.02% |          16      0.00%      0.02% |      629063     99.98%    100.00% |           0      0.00%    100.00%
+system.ruby.outstanding_req_hist::total        629183                      
 system.ruby.latency_hist::bucket_size            1024                      
 system.ruby.latency_hist::max_bucket            10239                      
-system.ruby.latency_hist::samples              618116                      
-system.ruby.latency_hist::mean            1200.021813                      
-system.ruby.latency_hist::gmean            820.629025                      
-system.ruby.latency_hist::stdev            895.776411                      
-system.ruby.latency_hist                 |      317693     51.40%     51.40% |      164349     26.59%     77.99% |      123580     19.99%     97.98% |       12269      1.98%     99.96% |         224      0.04%    100.00% |           1      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.latency_hist::total                618116                      
+system.ruby.latency_hist::samples              629055                      
+system.ruby.latency_hist::mean            1204.590594                      
+system.ruby.latency_hist::gmean            823.731643                      
+system.ruby.latency_hist::stdev            899.026148                      
+system.ruby.latency_hist                 |      322549     51.28%     51.28% |      166734     26.51%     77.78% |      126612     20.13%     97.91% |       12813      2.04%     99.94% |         340      0.05%    100.00% |           7      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.latency_hist::total                629055                      
 system.ruby.hit_latency_hist::bucket_size          256                      
 system.ruby.hit_latency_hist::max_bucket         2559                      
-system.ruby.hit_latency_hist::samples             737                      
-system.ruby.hit_latency_hist::mean         133.263229                      
-system.ruby.hit_latency_hist::gmean         41.298079                      
-system.ruby.hit_latency_hist::stdev        176.676430                      
-system.ruby.hit_latency_hist             |         600     81.41%     81.41% |         109     14.79%     96.20% |          20      2.71%     98.91% |           6      0.81%     99.73% |           1      0.14%     99.86% |           0      0.00%     99.86% |           0      0.00%     99.86% |           1      0.14%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.hit_latency_hist::total               737                      
+system.ruby.hit_latency_hist::samples             752                      
+system.ruby.hit_latency_hist::mean         140.220745                      
+system.ruby.hit_latency_hist::gmean         42.859600                      
+system.ruby.hit_latency_hist::stdev        185.954397                      
+system.ruby.hit_latency_hist             |         612     81.38%     81.38% |         110     14.63%     96.01% |          20      2.66%     98.67% |           7      0.93%     99.60% |           1      0.13%     99.73% |           1      0.13%     99.87% |           1      0.13%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.hit_latency_hist::total               752                      
 system.ruby.miss_latency_hist::bucket_size         1024                      
 system.ruby.miss_latency_hist::max_bucket        10239                      
-system.ruby.miss_latency_hist::samples         617379                      
-system.ruby.miss_latency_hist::mean       1201.295263                      
-system.ruby.miss_latency_hist::gmean       823.562623                      
-system.ruby.miss_latency_hist::stdev       895.531111                      
-system.ruby.miss_latency_hist            |      316958     51.34%     51.34% |      164347     26.62%     77.96% |      123580     20.02%     97.98% |       12269      1.99%     99.96% |         224      0.04%    100.00% |           1      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.miss_latency_hist::total           617379                      
-system.ruby.L1Cache.incomplete_times              439                      
-system.ruby.l1_cntrl4.L1Dcache.demand_hits           14                       # Number of cache demand hits
-system.ruby.l1_cntrl4.L1Dcache.demand_misses        77212                       # Number of cache demand misses
-system.ruby.l1_cntrl4.L1Dcache.demand_accesses        77226                       # Number of cache demand accesses
+system.ruby.miss_latency_hist::samples         628303                      
+system.ruby.miss_latency_hist::mean       1205.864511                      
+system.ruby.miss_latency_hist::gmean       826.651052                      
+system.ruby.miss_latency_hist::stdev       898.786133                      
+system.ruby.miss_latency_hist            |      321800     51.22%     51.22% |      166731     26.54%     77.75% |      126612     20.15%     97.91% |       12813      2.04%     99.94% |         340      0.05%    100.00% |           7      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.miss_latency_hist::total           628303                      
+system.ruby.L1Cache.incomplete_times              423                      
+system.ruby.l1_cntrl4.L1Dcache.demand_hits           19                       # Number of cache demand hits
+system.ruby.l1_cntrl4.L1Dcache.demand_misses        78646                       # Number of cache demand misses
+system.ruby.l1_cntrl4.L1Dcache.demand_accesses        78665                       # Number of cache demand accesses
 system.ruby.l1_cntrl4.L1Icache.demand_hits            0                       # Number of cache demand hits
 system.ruby.l1_cntrl4.L1Icache.demand_misses            0                       # Number of cache demand misses
 system.ruby.l1_cntrl4.L1Icache.demand_accesses            0                       # Number of cache demand accesses
-system.ruby.l1_cntrl4.L2cache.demand_hits           66                       # Number of cache demand hits
-system.ruby.l1_cntrl4.L2cache.demand_misses        77146                       # Number of cache demand misses
-system.ruby.l1_cntrl4.L2cache.demand_accesses        77212                       # Number of cache demand accesses
-system.ruby.l1_cntrl5.L1Dcache.demand_hits           28                       # Number of cache demand hits
-system.ruby.l1_cntrl5.L1Dcache.demand_misses        77076                       # Number of cache demand misses
-system.ruby.l1_cntrl5.L1Dcache.demand_accesses        77104                       # Number of cache demand accesses
+system.ruby.l1_cntrl4.L2cache.demand_hits           77                       # Number of cache demand hits
+system.ruby.l1_cntrl4.L2cache.demand_misses        78569                       # Number of cache demand misses
+system.ruby.l1_cntrl4.L2cache.demand_accesses        78646                       # Number of cache demand accesses
+system.ruby.l1_cntrl5.L1Dcache.demand_hits           19                       # Number of cache demand hits
+system.ruby.l1_cntrl5.L1Dcache.demand_misses        78666                       # Number of cache demand misses
+system.ruby.l1_cntrl5.L1Dcache.demand_accesses        78685                       # Number of cache demand accesses
 system.ruby.l1_cntrl5.L1Icache.demand_hits            0                       # Number of cache demand hits
 system.ruby.l1_cntrl5.L1Icache.demand_misses            0                       # Number of cache demand misses
 system.ruby.l1_cntrl5.L1Icache.demand_accesses            0                       # Number of cache demand accesses
-system.ruby.l1_cntrl5.L2cache.demand_hits           84                       # Number of cache demand hits
-system.ruby.l1_cntrl5.L2cache.demand_misses        76992                       # Number of cache demand misses
-system.ruby.l1_cntrl5.L2cache.demand_accesses        77076                       # Number of cache demand accesses
-system.ruby.l1_cntrl6.L1Dcache.demand_hits           12                       # Number of cache demand hits
-system.ruby.l1_cntrl6.L1Dcache.demand_misses        77608                       # Number of cache demand misses
-system.ruby.l1_cntrl6.L1Dcache.demand_accesses        77620                       # Number of cache demand accesses
+system.ruby.l1_cntrl5.L2cache.demand_hits           76                       # Number of cache demand hits
+system.ruby.l1_cntrl5.L2cache.demand_misses        78590                       # Number of cache demand misses
+system.ruby.l1_cntrl5.L2cache.demand_accesses        78666                       # Number of cache demand accesses
+system.ruby.l1_cntrl6.L1Dcache.demand_hits           16                       # Number of cache demand hits
+system.ruby.l1_cntrl6.L1Dcache.demand_misses        78670                       # Number of cache demand misses
+system.ruby.l1_cntrl6.L1Dcache.demand_accesses        78686                       # Number of cache demand accesses
 system.ruby.l1_cntrl6.L1Icache.demand_hits            0                       # Number of cache demand hits
 system.ruby.l1_cntrl6.L1Icache.demand_misses            0                       # Number of cache demand misses
 system.ruby.l1_cntrl6.L1Icache.demand_accesses            0                       # Number of cache demand accesses
-system.ruby.l1_cntrl6.L2cache.demand_hits           66                       # Number of cache demand hits
-system.ruby.l1_cntrl6.L2cache.demand_misses        77542                       # Number of cache demand misses
-system.ruby.l1_cntrl6.L2cache.demand_accesses        77608                       # Number of cache demand accesses
-system.ruby.l1_cntrl7.L1Dcache.demand_hits           14                       # Number of cache demand hits
-system.ruby.l1_cntrl7.L1Dcache.demand_misses        76959                       # Number of cache demand misses
-system.ruby.l1_cntrl7.L1Dcache.demand_accesses        76973                       # Number of cache demand accesses
+system.ruby.l1_cntrl6.L2cache.demand_hits           70                       # Number of cache demand hits
+system.ruby.l1_cntrl6.L2cache.demand_misses        78600                       # Number of cache demand misses
+system.ruby.l1_cntrl6.L2cache.demand_accesses        78670                       # Number of cache demand accesses
+system.ruby.l1_cntrl7.L1Dcache.demand_hits           24                       # Number of cache demand hits
+system.ruby.l1_cntrl7.L1Dcache.demand_misses        78321                       # Number of cache demand misses
+system.ruby.l1_cntrl7.L1Dcache.demand_accesses        78345                       # Number of cache demand accesses
 system.ruby.l1_cntrl7.L1Icache.demand_hits            0                       # Number of cache demand hits
 system.ruby.l1_cntrl7.L1Icache.demand_misses            0                       # Number of cache demand misses
 system.ruby.l1_cntrl7.L1Icache.demand_accesses            0                       # Number of cache demand accesses
-system.ruby.l1_cntrl7.L2cache.demand_hits           67                       # Number of cache demand hits
-system.ruby.l1_cntrl7.L2cache.demand_misses        76892                       # Number of cache demand misses
-system.ruby.l1_cntrl7.L2cache.demand_accesses        76959                       # Number of cache demand accesses
+system.ruby.l1_cntrl7.L2cache.demand_hits           78                       # Number of cache demand hits
+system.ruby.l1_cntrl7.L2cache.demand_misses        78243                       # Number of cache demand misses
+system.ruby.l1_cntrl7.L2cache.demand_accesses        78321                       # Number of cache demand accesses
 system.ruby.l1_cntrl0.L1Dcache.demand_hits           17                       # Number of cache demand hits
-system.ruby.l1_cntrl0.L1Dcache.demand_misses        76963                       # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Dcache.demand_accesses        76980                       # Number of cache demand accesses
+system.ruby.l1_cntrl0.L1Dcache.demand_misses        78395                       # Number of cache demand misses
+system.ruby.l1_cntrl0.L1Dcache.demand_accesses        78412                       # Number of cache demand accesses
 system.ruby.l1_cntrl0.L1Icache.demand_hits            0                       # Number of cache demand hits
 system.ruby.l1_cntrl0.L1Icache.demand_misses            0                       # Number of cache demand misses
 system.ruby.l1_cntrl0.L1Icache.demand_accesses            0                       # Number of cache demand accesses
-system.ruby.l1_cntrl0.L2cache.demand_hits           72                       # Number of cache demand hits
-system.ruby.l1_cntrl0.L2cache.demand_misses        76891                       # Number of cache demand misses
-system.ruby.l1_cntrl0.L2cache.demand_accesses        76963                       # Number of cache demand accesses
-system.ruby.l1_cntrl1.L1Dcache.demand_hits           22                       # Number of cache demand hits
-system.ruby.l1_cntrl1.L1Dcache.demand_misses        77461                       # Number of cache demand misses
-system.ruby.l1_cntrl1.L1Dcache.demand_accesses        77483                       # Number of cache demand accesses
+system.ruby.l1_cntrl0.L2cache.demand_hits           80                       # Number of cache demand hits
+system.ruby.l1_cntrl0.L2cache.demand_misses        78315                       # Number of cache demand misses
+system.ruby.l1_cntrl0.L2cache.demand_accesses        78395                       # Number of cache demand accesses
+system.ruby.l1_cntrl1.L1Dcache.demand_hits           15                       # Number of cache demand hits
+system.ruby.l1_cntrl1.L1Dcache.demand_misses        78908                       # Number of cache demand misses
+system.ruby.l1_cntrl1.L1Dcache.demand_accesses        78923                       # Number of cache demand accesses
 system.ruby.l1_cntrl1.L1Icache.demand_hits            0                       # Number of cache demand hits
 system.ruby.l1_cntrl1.L1Icache.demand_misses            0                       # Number of cache demand misses
 system.ruby.l1_cntrl1.L1Icache.demand_accesses            0                       # Number of cache demand accesses
-system.ruby.l1_cntrl1.L2cache.demand_hits           69                       # Number of cache demand hits
-system.ruby.l1_cntrl1.L2cache.demand_misses        77392                       # Number of cache demand misses
-system.ruby.l1_cntrl1.L2cache.demand_accesses        77461                       # Number of cache demand accesses
-system.ruby.l1_cntrl2.L1Dcache.demand_hits           12                       # Number of cache demand hits
-system.ruby.l1_cntrl2.L1Dcache.demand_misses        77314                       # Number of cache demand misses
-system.ruby.l1_cntrl2.L1Dcache.demand_accesses        77326                       # Number of cache demand accesses
+system.ruby.l1_cntrl1.L2cache.demand_hits           80                       # Number of cache demand hits
+system.ruby.l1_cntrl1.L2cache.demand_misses        78828                       # Number of cache demand misses
+system.ruby.l1_cntrl1.L2cache.demand_accesses        78908                       # Number of cache demand accesses
+system.ruby.l1_cntrl2.L1Dcache.demand_hits           15                       # Number of cache demand hits
+system.ruby.l1_cntrl2.L1Dcache.demand_misses        78622                       # Number of cache demand misses
+system.ruby.l1_cntrl2.L1Dcache.demand_accesses        78637                       # Number of cache demand accesses
 system.ruby.l1_cntrl2.L1Icache.demand_hits            0                       # Number of cache demand hits
 system.ruby.l1_cntrl2.L1Icache.demand_misses            0                       # Number of cache demand misses
 system.ruby.l1_cntrl2.L1Icache.demand_accesses            0                       # Number of cache demand accesses
-system.ruby.l1_cntrl2.L2cache.demand_hits           98                       # Number of cache demand hits
-system.ruby.l1_cntrl2.L2cache.demand_misses        77216                       # Number of cache demand misses
-system.ruby.l1_cntrl2.L2cache.demand_accesses        77314                       # Number of cache demand accesses
-system.ruby.l1_cntrl3.L1Dcache.demand_hits           19                       # Number of cache demand hits
-system.ruby.l1_cntrl3.L1Dcache.demand_misses        77408                       # Number of cache demand misses
-system.ruby.l1_cntrl3.L1Dcache.demand_accesses        77427                       # Number of cache demand accesses
+system.ruby.l1_cntrl2.L2cache.demand_hits           77                       # Number of cache demand hits
+system.ruby.l1_cntrl2.L2cache.demand_misses        78545                       # Number of cache demand misses
+system.ruby.l1_cntrl2.L2cache.demand_accesses        78622                       # Number of cache demand accesses
+system.ruby.l1_cntrl3.L1Dcache.demand_hits           17                       # Number of cache demand hits
+system.ruby.l1_cntrl3.L1Dcache.demand_misses        78711                       # Number of cache demand misses
+system.ruby.l1_cntrl3.L1Dcache.demand_accesses        78728                       # Number of cache demand accesses
 system.ruby.l1_cntrl3.L1Icache.demand_hits            0                       # Number of cache demand hits
 system.ruby.l1_cntrl3.L1Icache.demand_misses            0                       # Number of cache demand misses
 system.ruby.l1_cntrl3.L1Icache.demand_accesses            0                       # Number of cache demand accesses
-system.ruby.l1_cntrl3.L2cache.demand_hits           77                       # Number of cache demand hits
-system.ruby.l1_cntrl3.L2cache.demand_misses        77331                       # Number of cache demand misses
-system.ruby.l1_cntrl3.L2cache.demand_accesses        77408                       # Number of cache demand accesses
-system.ruby.network.routers0.percent_links_utilized    12.556021                      
-system.ruby.network.routers0.msg_count.Request_Control::2        76891                      
-system.ruby.network.routers0.msg_count.Request_Control::3           67                      
-system.ruby.network.routers0.msg_count.Response_Data::4        79331                      
-system.ruby.network.routers0.msg_count.Response_Control::4      1073182                      
-system.ruby.network.routers0.msg_count.Writeback_Data::5        26490                      
-system.ruby.network.routers0.msg_count.Writeback_Control::2        72619                      
-system.ruby.network.routers0.msg_count.Writeback_Control::3        72619                      
-system.ruby.network.routers0.msg_count.Writeback_Control::5        46104                      
-system.ruby.network.routers0.msg_count.Broadcast_Control::3       540121                      
-system.ruby.network.routers0.msg_count.Unblock_Control::5        76912                      
-system.ruby.network.routers0.msg_bytes.Request_Control::2       615128                      
-system.ruby.network.routers0.msg_bytes.Request_Control::3          536                      
-system.ruby.network.routers0.msg_bytes.Response_Data::4      5711832                      
-system.ruby.network.routers0.msg_bytes.Response_Control::4      8585456                      
-system.ruby.network.routers0.msg_bytes.Writeback_Data::5      1907280                      
-system.ruby.network.routers0.msg_bytes.Writeback_Control::2       580952                      
-system.ruby.network.routers0.msg_bytes.Writeback_Control::3       580952                      
-system.ruby.network.routers0.msg_bytes.Writeback_Control::5       368832                      
-system.ruby.network.routers0.msg_bytes.Broadcast_Control::3      4320968                      
-system.ruby.network.routers0.msg_bytes.Unblock_Control::5       615296                      
-system.ruby.network.routers1.percent_links_utilized    12.611060                      
-system.ruby.network.routers1.msg_count.Request_Control::2        77392                      
-system.ruby.network.routers1.msg_count.Request_Control::3           47                      
-system.ruby.network.routers1.msg_count.Response_Data::4        79893                      
-system.ruby.network.routers1.msg_count.Response_Control::4      1076151                      
-system.ruby.network.routers1.msg_count.Writeback_Data::5        26871                      
-system.ruby.network.routers1.msg_count.Writeback_Control::2        73022                      
-system.ruby.network.routers1.msg_count.Writeback_Control::3        73022                      
-system.ruby.network.routers1.msg_count.Writeback_Control::5        46119                      
-system.ruby.network.routers1.msg_count.Broadcast_Control::3       539613                      
-system.ruby.network.routers1.msg_count.Unblock_Control::5        77422                      
-system.ruby.network.routers1.msg_bytes.Request_Control::2       619136                      
-system.ruby.network.routers1.msg_bytes.Request_Control::3          376                      
-system.ruby.network.routers1.msg_bytes.Response_Data::4      5752296                      
-system.ruby.network.routers1.msg_bytes.Response_Control::4      8609208                      
-system.ruby.network.routers1.msg_bytes.Writeback_Data::5      1934712                      
-system.ruby.network.routers1.msg_bytes.Writeback_Control::2       584176                      
-system.ruby.network.routers1.msg_bytes.Writeback_Control::3       584176                      
-system.ruby.network.routers1.msg_bytes.Writeback_Control::5       368952                      
-system.ruby.network.routers1.msg_bytes.Broadcast_Control::3      4316904                      
-system.ruby.network.routers1.msg_bytes.Unblock_Control::5       619376                      
-system.ruby.network.routers2.percent_links_utilized    12.591042                      
-system.ruby.network.routers2.msg_count.Request_Control::2        77216                      
-system.ruby.network.routers2.msg_count.Request_Control::3           56                      
-system.ruby.network.routers2.msg_count.Response_Data::4        79706                      
-system.ruby.network.routers2.msg_count.Response_Control::4      1075089                      
-system.ruby.network.routers2.msg_count.Writeback_Data::5        26730                      
-system.ruby.network.routers2.msg_count.Writeback_Control::2        72821                      
-system.ruby.network.routers2.msg_count.Writeback_Control::3        72821                      
-system.ruby.network.routers2.msg_count.Writeback_Control::5        46059                      
-system.ruby.network.routers2.msg_count.Broadcast_Control::3       539797                      
-system.ruby.network.routers2.msg_count.Unblock_Control::5        77245                      
-system.ruby.network.routers2.msg_bytes.Request_Control::2       617728                      
-system.ruby.network.routers2.msg_bytes.Request_Control::3          448                      
-system.ruby.network.routers2.msg_bytes.Response_Data::4      5738832                      
-system.ruby.network.routers2.msg_bytes.Response_Control::4      8600712                      
-system.ruby.network.routers2.msg_bytes.Writeback_Data::5      1924560                      
-system.ruby.network.routers2.msg_bytes.Writeback_Control::2       582568                      
-system.ruby.network.routers2.msg_bytes.Writeback_Control::3       582568                      
-system.ruby.network.routers2.msg_bytes.Writeback_Control::5       368472                      
-system.ruby.network.routers2.msg_bytes.Broadcast_Control::3      4318376                      
-system.ruby.network.routers2.msg_bytes.Unblock_Control::5       617960                      
-system.ruby.network.routers3.percent_links_utilized    12.606475                      
-system.ruby.network.routers3.msg_count.Request_Control::2        77331                      
-system.ruby.network.routers3.msg_count.Request_Control::3           60                      
-system.ruby.network.routers3.msg_count.Response_Data::4        79797                      
-system.ruby.network.routers3.msg_count.Response_Control::4      1075802                      
-system.ruby.network.routers3.msg_count.Writeback_Data::5        26915                      
-system.ruby.network.routers3.msg_count.Writeback_Control::2        72965                      
-system.ruby.network.routers3.msg_count.Writeback_Control::3        72965                      
-system.ruby.network.routers3.msg_count.Writeback_Control::5        46025                      
-system.ruby.network.routers3.msg_count.Broadcast_Control::3       539692                      
-system.ruby.network.routers3.msg_count.Unblock_Control::5        77353                      
-system.ruby.network.routers3.msg_bytes.Request_Control::2       618648                      
-system.ruby.network.routers3.msg_bytes.Request_Control::3          480                      
-system.ruby.network.routers3.msg_bytes.Response_Data::4      5745384                      
-system.ruby.network.routers3.msg_bytes.Response_Control::4      8606416                      
-system.ruby.network.routers3.msg_bytes.Writeback_Data::5      1937880                      
-system.ruby.network.routers3.msg_bytes.Writeback_Control::2       583720                      
-system.ruby.network.routers3.msg_bytes.Writeback_Control::3       583720                      
-system.ruby.network.routers3.msg_bytes.Writeback_Control::5       368200                      
-system.ruby.network.routers3.msg_bytes.Broadcast_Control::3      4317536                      
-system.ruby.network.routers3.msg_bytes.Unblock_Control::5       618824                      
-system.ruby.network.routers4.percent_links_utilized    12.582311                      
-system.ruby.network.routers4.msg_count.Request_Control::2        77146                      
-system.ruby.network.routers4.msg_count.Request_Control::3           48                      
-system.ruby.network.routers4.msg_count.Response_Data::4        79619                      
-system.ruby.network.routers4.msg_count.Response_Control::4      1074623                      
-system.ruby.network.routers4.msg_count.Writeback_Data::5        26652                      
-system.ruby.network.routers4.msg_count.Writeback_Control::2        72792                      
-system.ruby.network.routers4.msg_count.Writeback_Control::3        72792                      
-system.ruby.network.routers4.msg_count.Writeback_Control::5        46109                      
-system.ruby.network.routers4.msg_count.Broadcast_Control::3       539876                      
-system.ruby.network.routers4.msg_count.Unblock_Control::5        77174                      
-system.ruby.network.routers4.msg_bytes.Request_Control::2       617168                      
-system.ruby.network.routers4.msg_bytes.Request_Control::3          384                      
-system.ruby.network.routers4.msg_bytes.Response_Data::4      5732568                      
-system.ruby.network.routers4.msg_bytes.Response_Control::4      8596984                      
-system.ruby.network.routers4.msg_bytes.Writeback_Data::5      1918944                      
-system.ruby.network.routers4.msg_bytes.Writeback_Control::2       582336                      
-system.ruby.network.routers4.msg_bytes.Writeback_Control::3       582336                      
-system.ruby.network.routers4.msg_bytes.Writeback_Control::5       368872                      
-system.ruby.network.routers4.msg_bytes.Broadcast_Control::3      4319008                      
-system.ruby.network.routers4.msg_bytes.Unblock_Control::5       617392                      
-system.ruby.network.routers5.percent_links_utilized    12.572088                      
-system.ruby.network.routers5.msg_count.Request_Control::2        76992                      
-system.ruby.network.routers5.msg_count.Request_Control::3           51                      
-system.ruby.network.routers5.msg_count.Response_Data::4        79504                      
-system.ruby.network.routers5.msg_count.Response_Control::4      1073637                      
-system.ruby.network.routers5.msg_count.Writeback_Data::5        26712                      
-system.ruby.network.routers5.msg_count.Writeback_Control::2        72564                      
-system.ruby.network.routers5.msg_count.Writeback_Control::3        72564                      
-system.ruby.network.routers5.msg_count.Writeback_Control::5        45823                      
-system.ruby.network.routers5.msg_count.Broadcast_Control::3       540035                      
-system.ruby.network.routers5.msg_count.Unblock_Control::5        77019                      
-system.ruby.network.routers5.msg_bytes.Request_Control::2       615936                      
-system.ruby.network.routers5.msg_bytes.Request_Control::3          408                      
-system.ruby.network.routers5.msg_bytes.Response_Data::4      5724288                      
-system.ruby.network.routers5.msg_bytes.Response_Control::4      8589096                      
-system.ruby.network.routers5.msg_bytes.Writeback_Data::5      1923264                      
-system.ruby.network.routers5.msg_bytes.Writeback_Control::2       580512                      
-system.ruby.network.routers5.msg_bytes.Writeback_Control::3       580512                      
-system.ruby.network.routers5.msg_bytes.Writeback_Control::5       366584                      
-system.ruby.network.routers5.msg_bytes.Broadcast_Control::3      4320280                      
-system.ruby.network.routers5.msg_bytes.Unblock_Control::5       616152                      
-system.ruby.network.routers6.percent_links_utilized    12.626714                      
-system.ruby.network.routers6.msg_count.Request_Control::2        77542                      
-system.ruby.network.routers6.msg_count.Request_Control::3           52                      
-system.ruby.network.routers6.msg_count.Response_Data::4        80017                      
-system.ruby.network.routers6.msg_count.Response_Control::4      1077041                      
-system.ruby.network.routers6.msg_count.Writeback_Data::5        26999                      
-system.ruby.network.routers6.msg_count.Writeback_Control::2        73171                      
-system.ruby.network.routers6.msg_count.Writeback_Control::3        73169                      
-system.ruby.network.routers6.msg_count.Writeback_Control::5        46140                      
-system.ruby.network.routers6.msg_count.Broadcast_Control::3       539467                      
-system.ruby.network.routers6.msg_count.Unblock_Control::5        77567                      
-system.ruby.network.routers6.msg_bytes.Request_Control::2       620336                      
-system.ruby.network.routers6.msg_bytes.Request_Control::3          416                      
-system.ruby.network.routers6.msg_bytes.Response_Data::4      5761224                      
-system.ruby.network.routers6.msg_bytes.Response_Control::4      8616328                      
-system.ruby.network.routers6.msg_bytes.Writeback_Data::5      1943928                      
-system.ruby.network.routers6.msg_bytes.Writeback_Control::2       585368                      
-system.ruby.network.routers6.msg_bytes.Writeback_Control::3       585352                      
-system.ruby.network.routers6.msg_bytes.Writeback_Control::5       369120                      
-system.ruby.network.routers6.msg_bytes.Broadcast_Control::3      4315736                      
-system.ruby.network.routers6.msg_bytes.Unblock_Control::5       620536                      
-system.ruby.network.routers7.percent_links_utilized    12.559398                      
-system.ruby.network.routers7.msg_count.Request_Control::2        76892                      
-system.ruby.network.routers7.msg_count.Request_Control::3           58                      
-system.ruby.network.routers7.msg_count.Response_Data::4        79385                      
-system.ruby.network.routers7.msg_count.Response_Control::4      1073007                      
-system.ruby.network.routers7.msg_count.Writeback_Data::5        26654                      
-system.ruby.network.routers7.msg_count.Writeback_Control::2        72340                      
-system.ruby.network.routers7.msg_count.Writeback_Control::3        72340                      
-system.ruby.network.routers7.msg_count.Writeback_Control::5        45668                      
-system.ruby.network.routers7.msg_count.Broadcast_Control::3       540126                      
-system.ruby.network.routers7.msg_count.Unblock_Control::5        76905                      
-system.ruby.network.routers7.msg_bytes.Request_Control::2       615136                      
-system.ruby.network.routers7.msg_bytes.Request_Control::3          464                      
-system.ruby.network.routers7.msg_bytes.Response_Data::4      5715720                      
-system.ruby.network.routers7.msg_bytes.Response_Control::4      8584056                      
-system.ruby.network.routers7.msg_bytes.Writeback_Data::5      1919088                      
-system.ruby.network.routers7.msg_bytes.Writeback_Control::2       578720                      
-system.ruby.network.routers7.msg_bytes.Writeback_Control::3       578720                      
-system.ruby.network.routers7.msg_bytes.Writeback_Control::5       365344                      
-system.ruby.network.routers7.msg_bytes.Broadcast_Control::3      4321008                      
-system.ruby.network.routers7.msg_bytes.Unblock_Control::5       615240                      
+system.ruby.l1_cntrl3.L2cache.demand_hits           72                       # Number of cache demand hits
+system.ruby.l1_cntrl3.L2cache.demand_misses        78639                       # Number of cache demand misses
+system.ruby.l1_cntrl3.L2cache.demand_accesses        78711                       # Number of cache demand accesses
+system.ruby.network.routers0.percent_links_utilized    12.539882                      
+system.ruby.network.routers0.msg_count.Request_Control::2        78315                      
+system.ruby.network.routers0.msg_count.Request_Control::3           59                      
+system.ruby.network.routers0.msg_count.Response_Data::4        80905                      
+system.ruby.network.routers0.msg_count.Response_Control::4      1092447                      
+system.ruby.network.routers0.msg_count.Writeback_Data::5        27634                      
+system.ruby.network.routers0.msg_count.Writeback_Control::2        73965                      
+system.ruby.network.routers0.msg_count.Writeback_Control::3        73965                      
+system.ruby.network.routers0.msg_count.Writeback_Control::5        46315                      
+system.ruby.network.routers0.msg_count.Broadcast_Control::3       549648                      
+system.ruby.network.routers0.msg_count.Unblock_Control::5        78328                      
+system.ruby.network.routers0.msg_bytes.Request_Control::2       626520                      
+system.ruby.network.routers0.msg_bytes.Request_Control::3          472                      
+system.ruby.network.routers0.msg_bytes.Response_Data::4      5825160                      
+system.ruby.network.routers0.msg_bytes.Response_Control::4      8739576                      
+system.ruby.network.routers0.msg_bytes.Writeback_Data::5      1989648                      
+system.ruby.network.routers0.msg_bytes.Writeback_Control::2       591720                      
+system.ruby.network.routers0.msg_bytes.Writeback_Control::3       591720                      
+system.ruby.network.routers0.msg_bytes.Writeback_Control::5       370520                      
+system.ruby.network.routers0.msg_bytes.Broadcast_Control::3      4397184                      
+system.ruby.network.routers0.msg_bytes.Unblock_Control::5       626624                      
+system.ruby.network.routers1.percent_links_utilized    12.590850                      
+system.ruby.network.routers1.msg_count.Request_Control::2        78828                      
+system.ruby.network.routers1.msg_count.Request_Control::3           53                      
+system.ruby.network.routers1.msg_count.Response_Data::4        81413                      
+system.ruby.network.routers1.msg_count.Response_Control::4      1095506                      
+system.ruby.network.routers1.msg_count.Writeback_Data::5        27983                      
+system.ruby.network.routers1.msg_count.Writeback_Control::2        74350                      
+system.ruby.network.routers1.msg_count.Writeback_Control::3        74350                      
+system.ruby.network.routers1.msg_count.Writeback_Control::5        46341                      
+system.ruby.network.routers1.msg_count.Broadcast_Control::3       549124                      
+system.ruby.network.routers1.msg_count.Unblock_Control::5        78851                      
+system.ruby.network.routers1.msg_bytes.Request_Control::2       630624                      
+system.ruby.network.routers1.msg_bytes.Request_Control::3          424                      
+system.ruby.network.routers1.msg_bytes.Response_Data::4      5861736                      
+system.ruby.network.routers1.msg_bytes.Response_Control::4      8764048                      
+system.ruby.network.routers1.msg_bytes.Writeback_Data::5      2014776                      
+system.ruby.network.routers1.msg_bytes.Writeback_Control::2       594800                      
+system.ruby.network.routers1.msg_bytes.Writeback_Control::3       594800                      
+system.ruby.network.routers1.msg_bytes.Writeback_Control::5       370728                      
+system.ruby.network.routers1.msg_bytes.Broadcast_Control::3      4392992                      
+system.ruby.network.routers1.msg_bytes.Unblock_Control::5       630808                      
+system.ruby.network.routers2.percent_links_utilized    12.557548                      
+system.ruby.network.routers2.msg_count.Request_Control::2        78545                      
+system.ruby.network.routers2.msg_count.Request_Control::3           51                      
+system.ruby.network.routers2.msg_count.Response_Data::4        81046                      
+system.ruby.network.routers2.msg_count.Response_Control::4      1093927                      
+system.ruby.network.routers2.msg_count.Writeback_Data::5        27726                      
+system.ruby.network.routers2.msg_count.Writeback_Control::2        74128                      
+system.ruby.network.routers2.msg_count.Writeback_Control::3        74128                      
+system.ruby.network.routers2.msg_count.Writeback_Control::5        46381                      
+system.ruby.network.routers2.msg_count.Broadcast_Control::3       549406                      
+system.ruby.network.routers2.msg_count.Unblock_Control::5        78563                      
+system.ruby.network.routers2.msg_bytes.Request_Control::2       628360                      
+system.ruby.network.routers2.msg_bytes.Request_Control::3          408                      
+system.ruby.network.routers2.msg_bytes.Response_Data::4      5835312                      
+system.ruby.network.routers2.msg_bytes.Response_Control::4      8751416                      
+system.ruby.network.routers2.msg_bytes.Writeback_Data::5      1996272                      
+system.ruby.network.routers2.msg_bytes.Writeback_Control::2       593024                      
+system.ruby.network.routers2.msg_bytes.Writeback_Control::3       593024                      
+system.ruby.network.routers2.msg_bytes.Writeback_Control::5       371048                      
+system.ruby.network.routers2.msg_bytes.Broadcast_Control::3      4395248                      
+system.ruby.network.routers2.msg_bytes.Unblock_Control::5       628504                      
+system.ruby.network.routers3.percent_links_utilized    12.569726                      
+system.ruby.network.routers3.msg_count.Request_Control::2        78639                      
+system.ruby.network.routers3.msg_count.Request_Control::3           54                      
+system.ruby.network.routers3.msg_count.Response_Data::4        81256                      
+system.ruby.network.routers3.msg_count.Response_Control::4      1094314                      
+system.ruby.network.routers3.msg_count.Writeback_Data::5        27761                      
+system.ruby.network.routers3.msg_count.Writeback_Control::2        74201                      
+system.ruby.network.routers3.msg_count.Writeback_Control::3        74201                      
+system.ruby.network.routers3.msg_count.Writeback_Control::5        46424                      
+system.ruby.network.routers3.msg_count.Broadcast_Control::3       549323                      
+system.ruby.network.routers3.msg_count.Unblock_Control::5        78652                      
+system.ruby.network.routers3.msg_bytes.Request_Control::2       629112                      
+system.ruby.network.routers3.msg_bytes.Request_Control::3          432                      
+system.ruby.network.routers3.msg_bytes.Response_Data::4      5850432                      
+system.ruby.network.routers3.msg_bytes.Response_Control::4      8754512                      
+system.ruby.network.routers3.msg_bytes.Writeback_Data::5      1998792                      
+system.ruby.network.routers3.msg_bytes.Writeback_Control::2       593608                      
+system.ruby.network.routers3.msg_bytes.Writeback_Control::3       593608                      
+system.ruby.network.routers3.msg_bytes.Writeback_Control::5       371392                      
+system.ruby.network.routers3.msg_bytes.Broadcast_Control::3      4394584                      
+system.ruby.network.routers3.msg_bytes.Unblock_Control::5       629216                      
+system.ruby.network.routers4.percent_links_utilized    12.558849                      
+system.ruby.network.routers4.msg_count.Request_Control::2        78569                      
+system.ruby.network.routers4.msg_count.Request_Control::3           57                      
+system.ruby.network.routers4.msg_count.Response_Data::4        81144                      
+system.ruby.network.routers4.msg_count.Response_Control::4      1093886                      
+system.ruby.network.routers4.msg_count.Writeback_Data::5        27693                      
+system.ruby.network.routers4.msg_count.Writeback_Control::2        74027                      
+system.ruby.network.routers4.msg_count.Writeback_Control::3        74027                      
+system.ruby.network.routers4.msg_count.Writeback_Control::5        46298                      
+system.ruby.network.routers4.msg_count.Broadcast_Control::3       549387                      
+system.ruby.network.routers4.msg_count.Unblock_Control::5        78601                      
+system.ruby.network.routers4.msg_bytes.Request_Control::2       628552                      
+system.ruby.network.routers4.msg_bytes.Request_Control::3          456                      
+system.ruby.network.routers4.msg_bytes.Response_Data::4      5842368                      
+system.ruby.network.routers4.msg_bytes.Response_Control::4      8751088                      
+system.ruby.network.routers4.msg_bytes.Writeback_Data::5      1993896                      
+system.ruby.network.routers4.msg_bytes.Writeback_Control::2       592216                      
+system.ruby.network.routers4.msg_bytes.Writeback_Control::3       592216                      
+system.ruby.network.routers4.msg_bytes.Writeback_Control::5       370384                      
+system.ruby.network.routers4.msg_bytes.Broadcast_Control::3      4395096                      
+system.ruby.network.routers4.msg_bytes.Unblock_Control::5       628808                      
+system.ruby.network.routers5.percent_links_utilized    12.551928                      
+system.ruby.network.routers5.msg_count.Request_Control::2        78590                      
+system.ruby.network.routers5.msg_count.Request_Control::3           45                      
+system.ruby.network.routers5.msg_count.Response_Data::4        81153                      
+system.ruby.network.routers5.msg_count.Response_Control::4      1094141                      
+system.ruby.network.routers5.msg_count.Writeback_Data::5        27387                      
+system.ruby.network.routers5.msg_count.Writeback_Control::2        74179                      
+system.ruby.network.routers5.msg_count.Writeback_Control::3        74179                      
+system.ruby.network.routers5.msg_count.Writeback_Control::5        46760                      
+system.ruby.network.routers5.msg_count.Broadcast_Control::3       549374                      
+system.ruby.network.routers5.msg_count.Unblock_Control::5        78618                      
+system.ruby.network.routers5.msg_bytes.Request_Control::2       628720                      
+system.ruby.network.routers5.msg_bytes.Request_Control::3          360                      
+system.ruby.network.routers5.msg_bytes.Response_Data::4      5843016                      
+system.ruby.network.routers5.msg_bytes.Response_Control::4      8753128                      
+system.ruby.network.routers5.msg_bytes.Writeback_Data::5      1971864                      
+system.ruby.network.routers5.msg_bytes.Writeback_Control::2       593432                      
+system.ruby.network.routers5.msg_bytes.Writeback_Control::3       593432                      
+system.ruby.network.routers5.msg_bytes.Writeback_Control::5       374080                      
+system.ruby.network.routers5.msg_bytes.Broadcast_Control::3      4394992                      
+system.ruby.network.routers5.msg_bytes.Unblock_Control::5       628944                      
+system.ruby.network.routers6.percent_links_utilized    12.555969                      
+system.ruby.network.routers6.msg_count.Request_Control::2        78600                      
+system.ruby.network.routers6.msg_count.Request_Control::3           62                      
+system.ruby.network.routers6.msg_count.Response_Data::4        81186                      
+system.ruby.network.routers6.msg_count.Response_Control::4      1094124                      
+system.ruby.network.routers6.msg_count.Writeback_Data::5        27482                      
+system.ruby.network.routers6.msg_count.Writeback_Control::2        74144                      
+system.ruby.network.routers6.msg_count.Writeback_Control::3        74144                      
+system.ruby.network.routers6.msg_count.Writeback_Control::5        46633                      
+system.ruby.network.routers6.msg_count.Broadcast_Control::3       549359                      
+system.ruby.network.routers6.msg_count.Unblock_Control::5        78625                      
+system.ruby.network.routers6.msg_bytes.Request_Control::2       628800                      
+system.ruby.network.routers6.msg_bytes.Request_Control::3          496                      
+system.ruby.network.routers6.msg_bytes.Response_Data::4      5845392                      
+system.ruby.network.routers6.msg_bytes.Response_Control::4      8752992                      
+system.ruby.network.routers6.msg_bytes.Writeback_Data::5      1978704                      
+system.ruby.network.routers6.msg_bytes.Writeback_Control::2       593152                      
+system.ruby.network.routers6.msg_bytes.Writeback_Control::3       593152                      
+system.ruby.network.routers6.msg_bytes.Writeback_Control::5       373064                      
+system.ruby.network.routers6.msg_bytes.Broadcast_Control::3      4394872                      
+system.ruby.network.routers6.msg_bytes.Unblock_Control::5       629000                      
+system.ruby.network.routers7.percent_links_utilized    12.542424                      
+system.ruby.network.routers7.msg_count.Request_Control::2        78243                      
+system.ruby.network.routers7.msg_count.Request_Control::3           42                      
+system.ruby.network.routers7.msg_count.Response_Data::4        80772                      
+system.ruby.network.routers7.msg_count.Response_Control::4      1092029                      
+system.ruby.network.routers7.msg_count.Writeback_Data::5        27935                      
+system.ruby.network.routers7.msg_count.Writeback_Control::2        73931                      
+system.ruby.network.routers7.msg_count.Writeback_Control::3        73931                      
+system.ruby.network.routers7.msg_count.Writeback_Control::5        45971                      
+system.ruby.network.routers7.msg_count.Broadcast_Control::3       549721                      
+system.ruby.network.routers7.msg_count.Unblock_Control::5        78264                      
+system.ruby.network.routers7.msg_bytes.Request_Control::2       625944                      
+system.ruby.network.routers7.msg_bytes.Request_Control::3          336                      
+system.ruby.network.routers7.msg_bytes.Response_Data::4      5815584                      
+system.ruby.network.routers7.msg_bytes.Response_Control::4      8736232                      
+system.ruby.network.routers7.msg_bytes.Writeback_Data::5      2011320                      
+system.ruby.network.routers7.msg_bytes.Writeback_Control::2       591448                      
+system.ruby.network.routers7.msg_bytes.Writeback_Control::3       591448                      
+system.ruby.network.routers7.msg_bytes.Writeback_Control::5       367768                      
+system.ruby.network.routers7.msg_bytes.Broadcast_Control::3      4397768                      
+system.ruby.network.routers7.msg_bytes.Unblock_Control::5       626112                      
 system.ruby.memctrl_clk_domain.clock                3                       # Clock period in ticks
-system.ruby.dir_cntrl0.memBuffer.memReq        811546                       # Total number of memory requests
-system.ruby.dir_cntrl0.memBuffer.memRead       597507                       # Number of memory reads
-system.ruby.dir_cntrl0.memBuffer.memWrite       214013                       # Number of memory writes
-system.ruby.dir_cntrl0.memBuffer.memRefresh        40249                       # Number of memory refreshes
-system.ruby.dir_cntrl0.memBuffer.memWaitCycles     29190456                       # Delay stalled at the head of the bank queue
-system.ruby.dir_cntrl0.memBuffer.memInputQ       408038                       # Delay in the input queue
-system.ruby.dir_cntrl0.memBuffer.memBankQ     19549348                       # Delay behind the head of the bank queue
-system.ruby.dir_cntrl0.memBuffer.totalStalls     49147842                       # Total number of stall cycles
-system.ruby.dir_cntrl0.memBuffer.stallsPerReq    60.560759                       # Expected number of stall cycles per request
-system.ruby.dir_cntrl0.memBuffer.memBankBusy      4395939                       # memory stalls due to busy bank
-system.ruby.dir_cntrl0.memBuffer.memBusBusy      8156080                       # memory stalls due to busy bus
-system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy      2068734                       # memory stalls due to read write turnaround
-system.ruby.dir_cntrl0.memBuffer.memDataBusBusy      1377698                       # memory stalls due to read read turnaround
-system.ruby.dir_cntrl0.memBuffer.memArbWait      6011646                       # memory stalls due to arbitration
-system.ruby.dir_cntrl0.memBuffer.memNotOld      7180359                       # memory stalls due to anti starvation
-system.ruby.dir_cntrl0.memBuffer.memBankCount |       25525      3.15%      3.15% |       25047      3.09%      6.23% |       25485      3.14%      9.37% |       25568      3.15%     12.52% |       25590      3.15%     15.68% |       25517      3.14%     18.82% |       25716      3.17%     21.99% |       25410      3.13%     25.12% |       25335      3.12%     28.24% |       25484      3.14%     31.38% |       25540      3.15%     34.53% |       25414      3.13%     37.66% |       25457      3.14%     40.80% |       25303      3.12%     43.92% |       25416      3.13%     47.05% |       25361      3.13%     50.17% |       25622      3.16%     53.33% |       25433      3.13%     56.46% |       25171      3.10%     59.56% |       25194      3.10%     62.67% |       25397      3.13%     65.80% |       25498      3.14%     68.94% |       25175      3.10%     72.04% |       25106      3.09%     75.14% |       25081      3.09%     78.23% |       25088      3.09%     81.32% |       24820      3.06%     84.38% |       25599      3.15%     87.53% |       25387      3.13%     90.66% |       25331      3.12%     93.78% |       25290      3.12%     96.90% |       25186      3.10%    100.00% # Number of accesses per bank
-system.ruby.dir_cntrl0.memBuffer.memBankCount::total       811546                       # Number of accesses per bank
+system.ruby.dir_cntrl0.memBuffer.memReq        829348                       # Total number of memory requests
+system.ruby.dir_cntrl0.memBuffer.memRead       607726                       # Number of memory reads
+system.ruby.dir_cntrl0.memBuffer.memWrite       221589                       # Number of memory writes
+system.ruby.dir_cntrl0.memBuffer.memRefresh        41118                       # Number of memory refreshes
+system.ruby.dir_cntrl0.memBuffer.memWaitCycles     29891924                       # Delay stalled at the head of the bank queue
+system.ruby.dir_cntrl0.memBuffer.memInputQ       415495                       # Delay in the input queue
+system.ruby.dir_cntrl0.memBuffer.memBankQ     20161616                       # Delay behind the head of the bank queue
+system.ruby.dir_cntrl0.memBuffer.totalStalls     50469035                       # Total number of stall cycles
+system.ruby.dir_cntrl0.memBuffer.stallsPerReq    60.853870                       # Expected number of stall cycles per request
+system.ruby.dir_cntrl0.memBuffer.memBankBusy      4511761                       # memory stalls due to busy bank
+system.ruby.dir_cntrl0.memBuffer.memBusBusy      8350172                       # memory stalls due to busy bus
+system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy      2127555                       # memory stalls due to read write turnaround
+system.ruby.dir_cntrl0.memBuffer.memDataBusBusy      1394322                       # memory stalls due to read read turnaround
+system.ruby.dir_cntrl0.memBuffer.memArbWait      6158676                       # memory stalls due to arbitration
+system.ruby.dir_cntrl0.memBuffer.memNotOld      7349438                       # memory stalls due to anti starvation
+system.ruby.dir_cntrl0.memBuffer.memBankCount |       26193      3.16%      3.16% |       26128      3.15%      6.31% |       26105      3.15%      9.46% |       25961      3.13%     12.59% |       26151      3.15%     15.74% |       26370      3.18%     18.92% |       25970      3.13%     22.05% |       26083      3.15%     25.20% |       25945      3.13%     28.32% |       25763      3.11%     31.43% |       26082      3.14%     34.58% |       26004      3.14%     37.71% |       26080      3.14%     40.86% |       26077      3.14%     44.00% |       25922      3.13%     47.13% |       25819      3.11%     50.24% |       25968      3.13%     53.37% |       25870      3.12%     56.49% |       25867      3.12%     59.61% |       25796      3.11%     62.72% |       25881      3.12%     65.84% |       25705      3.10%     68.94% |       25499      3.07%     72.01% |       25623      3.09%     75.10% |       26078      3.14%     78.25% |       25821      3.11%     81.36% |       25430      3.07%     84.43% |       25795      3.11%     87.54% |       25934      3.13%     90.66% |       25506      3.08%     93.74% |       25828      3.11%     96.85% |       26094      3.15%    100.00% # Number of accesses per bank
+system.ruby.dir_cntrl0.memBuffer.memBankCount::total       829348                       # Number of accesses per bank
 system.ruby.dir_cntrl0.probeFilter.demand_hits            0                       # Number of cache demand hits
 system.ruby.dir_cntrl0.probeFilter.demand_misses            0                       # Number of cache demand misses
 system.ruby.dir_cntrl0.probeFilter.demand_accesses            0                       # Number of cache demand accesses
-system.ruby.network.routers8.percent_links_utilized    46.105327                      
-system.ruby.network.routers8.msg_count.Request_Control::2       617400                      
-system.ruby.network.routers8.msg_count.Request_Control::3          439                      
-system.ruby.network.routers8.msg_count.Response_Data::4       597502                      
-system.ruby.network.routers8.msg_count.Writeback_Data::5       214023                      
-system.ruby.network.routers8.msg_count.Writeback_Control::2       582292                      
-system.ruby.network.routers8.msg_count.Writeback_Control::3       582292                      
-system.ruby.network.routers8.msg_count.Writeback_Control::5       368046                      
-system.ruby.network.routers8.msg_count.Broadcast_Control::3       616961                      
-system.ruby.network.routers8.msg_count.Unblock_Control::5       617596                      
-system.ruby.network.routers8.msg_bytes.Request_Control::2      4939200                      
-system.ruby.network.routers8.msg_bytes.Request_Control::3         3512                      
-system.ruby.network.routers8.msg_bytes.Response_Data::4     43020144                      
-system.ruby.network.routers8.msg_bytes.Writeback_Data::5     15409656                      
-system.ruby.network.routers8.msg_bytes.Writeback_Control::2      4658336                      
-system.ruby.network.routers8.msg_bytes.Writeback_Control::3      4658336                      
-system.ruby.network.routers8.msg_bytes.Writeback_Control::5      2944368                      
-system.ruby.network.routers8.msg_bytes.Broadcast_Control::3      4935688                      
-system.ruby.network.routers8.msg_bytes.Unblock_Control::5      4940768                      
-system.ruby.network.routers9.percent_links_utilized    18.086419                      
-system.ruby.network.routers9.msg_count.Request_Control::2       617401                      
-system.ruby.network.routers9.msg_count.Request_Control::3          439                      
-system.ruby.network.routers9.msg_count.Response_Data::4       617377                      
-system.ruby.network.routers9.msg_count.Response_Control::4      4299263                      
-system.ruby.network.routers9.msg_count.Writeback_Data::5       214023                      
-system.ruby.network.routers9.msg_count.Writeback_Control::2       582292                      
-system.ruby.network.routers9.msg_count.Writeback_Control::3       582292                      
-system.ruby.network.routers9.msg_count.Writeback_Control::5       368047                      
-system.ruby.network.routers9.msg_count.Broadcast_Control::3      4318727                      
-system.ruby.network.routers9.msg_count.Unblock_Control::5       617596                      
-system.ruby.network.routers9.msg_bytes.Request_Control::2      4939208                      
-system.ruby.network.routers9.msg_bytes.Request_Control::3         3512                      
-system.ruby.network.routers9.msg_bytes.Response_Data::4     44451144                      
-system.ruby.network.routers9.msg_bytes.Response_Control::4     34394104                      
-system.ruby.network.routers9.msg_bytes.Writeback_Data::5     15409656                      
-system.ruby.network.routers9.msg_bytes.Writeback_Control::2      4658336                      
-system.ruby.network.routers9.msg_bytes.Writeback_Control::3      4658336                      
-system.ruby.network.routers9.msg_bytes.Writeback_Control::5      2944376                      
-system.ruby.network.routers9.msg_bytes.Broadcast_Control::3     34549816                      
-system.ruby.network.routers9.msg_bytes.Unblock_Control::5      4940768                      
-system.ruby.network.msg_count.Request_Control      1853520                      
-system.ruby.network.msg_count.Response_Data      1852131                      
-system.ruby.network.msg_count.Response_Control     12897795                      
-system.ruby.network.msg_count.Writeback_Data       642069                      
-system.ruby.network.msg_count.Writeback_Control      4597894                      
-system.ruby.network.msg_count.Broadcast_Control      9254415                      
-system.ruby.network.msg_count.Unblock_Control      1852789                      
-system.ruby.network.msg_byte.Request_Control     14828160                      
-system.ruby.network.msg_byte.Response_Data    133353432                      
-system.ruby.network.msg_byte.Response_Control    103182360                      
-system.ruby.network.msg_byte.Writeback_Data     46228968                      
-system.ruby.network.msg_byte.Writeback_Control     36783152                      
-system.ruby.network.msg_byte.Broadcast_Control     74035320                      
-system.ruby.network.msg_byte.Unblock_Control     14822312                      
+system.ruby.network.routers8.percent_links_utilized    46.048912                      
+system.ruby.network.routers8.msg_count.Request_Control::2       628329                      
+system.ruby.network.routers8.msg_count.Request_Control::3          423                      
+system.ruby.network.routers8.msg_count.Response_Data::4       607721                      
+system.ruby.network.routers8.msg_count.Writeback_Data::5       221601                      
+system.ruby.network.routers8.msg_count.Writeback_Control::2       592925                      
+system.ruby.network.routers8.msg_count.Writeback_Control::3       592925                      
+system.ruby.network.routers8.msg_count.Writeback_Control::5       371123                      
+system.ruby.network.routers8.msg_count.Broadcast_Control::3       627906                      
+system.ruby.network.routers8.msg_count.Unblock_Control::5       628502                      
+system.ruby.network.routers8.msg_bytes.Request_Control::2      5026632                      
+system.ruby.network.routers8.msg_bytes.Request_Control::3         3384                      
+system.ruby.network.routers8.msg_bytes.Response_Data::4     43755912                      
+system.ruby.network.routers8.msg_bytes.Writeback_Data::5     15955272                      
+system.ruby.network.routers8.msg_bytes.Writeback_Control::2      4743400                      
+system.ruby.network.routers8.msg_bytes.Writeback_Control::3      4743400                      
+system.ruby.network.routers8.msg_bytes.Writeback_Control::5      2968984                      
+system.ruby.network.routers8.msg_bytes.Broadcast_Control::3      5023248                      
+system.ruby.network.routers8.msg_bytes.Unblock_Control::5      5028016                      
+system.ruby.network.routers9.percent_links_utilized    18.047053                      
+system.ruby.network.routers9.msg_count.Request_Control::2       628329                      
+system.ruby.network.routers9.msg_count.Request_Control::3          423                      
+system.ruby.network.routers9.msg_count.Response_Data::4       628298                      
+system.ruby.network.routers9.msg_count.Response_Control::4      4375187                      
+system.ruby.network.routers9.msg_count.Writeback_Data::5       221601                      
+system.ruby.network.routers9.msg_count.Writeback_Control::2       592925                      
+system.ruby.network.routers9.msg_count.Writeback_Control::3       592925                      
+system.ruby.network.routers9.msg_count.Writeback_Control::5       371123                      
+system.ruby.network.routers9.msg_count.Broadcast_Control::3      4395342                      
+system.ruby.network.routers9.msg_count.Unblock_Control::5       628502                      
+system.ruby.network.routers9.msg_bytes.Request_Control::2      5026632                      
+system.ruby.network.routers9.msg_bytes.Request_Control::3         3384                      
+system.ruby.network.routers9.msg_bytes.Response_Data::4     45237456                      
+system.ruby.network.routers9.msg_bytes.Response_Control::4     35001496                      
+system.ruby.network.routers9.msg_bytes.Writeback_Data::5     15955272                      
+system.ruby.network.routers9.msg_bytes.Writeback_Control::2      4743400                      
+system.ruby.network.routers9.msg_bytes.Writeback_Control::3      4743400                      
+system.ruby.network.routers9.msg_bytes.Writeback_Control::5      2968984                      
+system.ruby.network.routers9.msg_bytes.Broadcast_Control::3     35162736                      
+system.ruby.network.routers9.msg_bytes.Unblock_Control::5      5028016                      
+system.ruby.network.msg_count.Request_Control      1886256                      
+system.ruby.network.msg_count.Response_Data      1884894                      
+system.ruby.network.msg_count.Response_Control     13125561                      
+system.ruby.network.msg_count.Writeback_Data       664803                      
+system.ruby.network.msg_count.Writeback_Control      4670919                      
+system.ruby.network.msg_count.Broadcast_Control      9418590                      
+system.ruby.network.msg_count.Unblock_Control      1885506                      
+system.ruby.network.msg_byte.Request_Control     15090048                      
+system.ruby.network.msg_byte.Response_Data    135712368                      
+system.ruby.network.msg_byte.Response_Control    105004488                      
+system.ruby.network.msg_byte.Writeback_Data     47865816                      
+system.ruby.network.msg_byte.Writeback_Control     37367352                      
+system.ruby.network.msg_byte.Broadcast_Control     75348720                      
+system.ruby.network.msg_byte.Unblock_Control     15084048                      
 system.funcbus.throughput                           0                       # Throughput (bytes/s)
 system.funcbus.data_through_bus                     0                       # Total data (bytes)
 system.cpu_clk_domain.clock                         1                       # Clock period in ticks
-system.cpu0.num_reads                           99395                       # number of read accesses completed
-system.cpu0.num_writes                          53721                       # number of write accesses completed
+system.cpu0.num_reads                           99506                       # number of read accesses completed
+system.cpu0.num_writes                          55459                       # number of write accesses completed
 system.cpu0.num_copies                              0                       # number of copy accesses completed
-system.cpu1.num_reads                           99652                       # number of read accesses completed
-system.cpu1.num_writes                          54399                       # number of write accesses completed
+system.cpu1.num_reads                          100000                       # number of read accesses completed
+system.cpu1.num_writes                          56034                       # number of write accesses completed
 system.cpu1.num_copies                              0                       # number of copy accesses completed
-system.cpu2.num_reads                          100000                       # number of read accesses completed
-system.cpu2.num_writes                          54294                       # number of write accesses completed
+system.cpu2.num_reads                           99774                       # number of read accesses completed
+system.cpu2.num_writes                          55650                       # number of write accesses completed
 system.cpu2.num_copies                              0                       # number of copy accesses completed
-system.cpu3.num_reads                           99790                       # number of read accesses completed
-system.cpu3.num_writes                          54193                       # number of write accesses completed
+system.cpu3.num_reads                           99487                       # number of read accesses completed
+system.cpu3.num_writes                          55471                       # number of write accesses completed
 system.cpu3.num_copies                              0                       # number of copy accesses completed
-system.cpu4.num_reads                           99482                       # number of read accesses completed
-system.cpu4.num_writes                          53726                       # number of write accesses completed
+system.cpu4.num_reads                           99515                       # number of read accesses completed
+system.cpu4.num_writes                          55612                       # number of write accesses completed
 system.cpu4.num_copies                              0                       # number of copy accesses completed
-system.cpu5.num_reads                           99470                       # number of read accesses completed
-system.cpu5.num_writes                          54029                       # number of write accesses completed
+system.cpu5.num_reads                           99579                       # number of read accesses completed
+system.cpu5.num_writes                          55211                       # number of write accesses completed
 system.cpu5.num_copies                              0                       # number of copy accesses completed
-system.cpu6.num_reads                           99753                       # number of read accesses completed
-system.cpu6.num_writes                          54335                       # number of write accesses completed
+system.cpu6.num_reads                           99679                       # number of read accesses completed
+system.cpu6.num_writes                          55618                       # number of write accesses completed
 system.cpu6.num_copies                              0                       # number of copy accesses completed
-system.cpu7.num_reads                           99102                       # number of read accesses completed
-system.cpu7.num_writes                          53848                       # number of write accesses completed
+system.cpu7.num_reads                           98792                       # number of read accesses completed
+system.cpu7.num_writes                          55627                       # number of write accesses completed
 system.cpu7.num_copies                              0                       # number of copy accesses completed
-system.ruby.network.routers0.throttle0.link_utilization    15.875388                      
-system.ruby.network.routers0.throttle0.msg_count.Request_Control::3           67                      
-system.ruby.network.routers0.throttle0.msg_count.Response_Data::4        76886                      
-system.ruby.network.routers0.throttle0.msg_count.Response_Control::4       535441                      
-system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3        72619                      
-system.ruby.network.routers0.throttle0.msg_count.Broadcast_Control::3       540121                      
-system.ruby.network.routers0.throttle0.msg_bytes.Request_Control::3          536                      
-system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4      5535792                      
-system.ruby.network.routers0.throttle0.msg_bytes.Response_Control::4      4283528                      
-system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3       580952                      
-system.ruby.network.routers0.throttle0.msg_bytes.Broadcast_Control::3      4320968                      
-system.ruby.network.routers0.throttle1.link_utilization     9.236653                      
-system.ruby.network.routers0.throttle1.msg_count.Request_Control::2        76891                      
-system.ruby.network.routers0.throttle1.msg_count.Response_Data::4         2445                      
-system.ruby.network.routers0.throttle1.msg_count.Response_Control::4       537741                      
-system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::5        26490                      
-system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::2        72619                      
-system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::5        46104                      
-system.ruby.network.routers0.throttle1.msg_count.Unblock_Control::5        76912                      
-system.ruby.network.routers0.throttle1.msg_bytes.Request_Control::2       615128                      
-system.ruby.network.routers0.throttle1.msg_bytes.Response_Data::4       176040                      
-system.ruby.network.routers0.throttle1.msg_bytes.Response_Control::4      4301928                      
-system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::5      1907280                      
-system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::2       580952                      
-system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::5       368832                      
-system.ruby.network.routers0.throttle1.msg_bytes.Unblock_Control::5       615296                      
-system.ruby.network.routers1.throttle0.link_utilization    15.944041                      
-system.ruby.network.routers1.throttle0.msg_count.Request_Control::3           47                      
-system.ruby.network.routers1.throttle0.msg_count.Response_Data::4        77389                      
-system.ruby.network.routers1.throttle0.msg_count.Response_Control::4       538997                      
-system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::3        73022                      
-system.ruby.network.routers1.throttle0.msg_count.Broadcast_Control::3       539613                      
-system.ruby.network.routers1.throttle0.msg_bytes.Request_Control::3          376                      
-system.ruby.network.routers1.throttle0.msg_bytes.Response_Data::4      5572008                      
-system.ruby.network.routers1.throttle0.msg_bytes.Response_Control::4      4311976                      
-system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::3       584176                      
-system.ruby.network.routers1.throttle0.msg_bytes.Broadcast_Control::3      4316904                      
-system.ruby.network.routers1.throttle1.link_utilization     9.278080                      
-system.ruby.network.routers1.throttle1.msg_count.Request_Control::2        77392                      
-system.ruby.network.routers1.throttle1.msg_count.Response_Data::4         2504                      
-system.ruby.network.routers1.throttle1.msg_count.Response_Control::4       537154                      
-system.ruby.network.routers1.throttle1.msg_count.Writeback_Data::5        26871                      
-system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::2        73022                      
-system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::5        46119                      
-system.ruby.network.routers1.throttle1.msg_count.Unblock_Control::5        77422                      
-system.ruby.network.routers1.throttle1.msg_bytes.Request_Control::2       619136                      
-system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4       180288                      
-system.ruby.network.routers1.throttle1.msg_bytes.Response_Control::4      4297232                      
-system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::5      1934712                      
-system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::2       584176                      
-system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::5       368952                      
-system.ruby.network.routers1.throttle1.msg_bytes.Unblock_Control::5       619376                      
-system.ruby.network.routers2.throttle0.link_utilization    15.919411                      
-system.ruby.network.routers2.throttle0.msg_count.Request_Control::3           56                      
-system.ruby.network.routers2.throttle0.msg_count.Response_Data::4        77214                      
-system.ruby.network.routers2.throttle0.msg_count.Response_Control::4       537730                      
-system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3        72821                      
-system.ruby.network.routers2.throttle0.msg_count.Broadcast_Control::3       539797                      
-system.ruby.network.routers2.throttle0.msg_bytes.Request_Control::3          448                      
-system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4      5559408                      
-system.ruby.network.routers2.throttle0.msg_bytes.Response_Control::4      4301840                      
-system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3       582568                      
-system.ruby.network.routers2.throttle0.msg_bytes.Broadcast_Control::3      4318376                      
-system.ruby.network.routers2.throttle1.link_utilization     9.262672                      
-system.ruby.network.routers2.throttle1.msg_count.Request_Control::2        77216                      
-system.ruby.network.routers2.throttle1.msg_count.Response_Data::4         2492                      
-system.ruby.network.routers2.throttle1.msg_count.Response_Control::4       537359                      
-system.ruby.network.routers2.throttle1.msg_count.Writeback_Data::5        26730                      
-system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::2        72821                      
-system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::5        46059                      
-system.ruby.network.routers2.throttle1.msg_count.Unblock_Control::5        77245                      
-system.ruby.network.routers2.throttle1.msg_bytes.Request_Control::2       617728                      
-system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::4       179424                      
-system.ruby.network.routers2.throttle1.msg_bytes.Response_Control::4      4298872                      
-system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Data::5      1924560                      
-system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::2       582568                      
-system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::5       368472                      
-system.ruby.network.routers2.throttle1.msg_bytes.Unblock_Control::5       617960                      
-system.ruby.network.routers3.throttle0.link_utilization    15.935501                      
-system.ruby.network.routers3.throttle0.msg_count.Request_Control::3           60                      
-system.ruby.network.routers3.throttle0.msg_count.Response_Data::4        77328                      
-system.ruby.network.routers3.throttle0.msg_count.Response_Control::4       538521                      
-system.ruby.network.routers3.throttle0.msg_count.Writeback_Control::3        72965                      
-system.ruby.network.routers3.throttle0.msg_count.Broadcast_Control::3       539692                      
-system.ruby.network.routers3.throttle0.msg_bytes.Request_Control::3          480                      
-system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::4      5567616                      
-system.ruby.network.routers3.throttle0.msg_bytes.Response_Control::4      4308168                      
-system.ruby.network.routers3.throttle0.msg_bytes.Writeback_Control::3       583720                      
-system.ruby.network.routers3.throttle0.msg_bytes.Broadcast_Control::3      4317536                      
-system.ruby.network.routers3.throttle1.link_utilization     9.277450                      
-system.ruby.network.routers3.throttle1.msg_count.Request_Control::2        77331                      
-system.ruby.network.routers3.throttle1.msg_count.Response_Data::4         2469                      
-system.ruby.network.routers3.throttle1.msg_count.Response_Control::4       537281                      
-system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::5        26915                      
-system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::2        72965                      
-system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::5        46025                      
-system.ruby.network.routers3.throttle1.msg_count.Unblock_Control::5        77353                      
-system.ruby.network.routers3.throttle1.msg_bytes.Request_Control::2       618648                      
-system.ruby.network.routers3.throttle1.msg_bytes.Response_Data::4       177768                      
-system.ruby.network.routers3.throttle1.msg_bytes.Response_Control::4      4298248                      
-system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::5      1937880                      
-system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::2       583720                      
-system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::5       368200                      
-system.ruby.network.routers3.throttle1.msg_bytes.Unblock_Control::5       618824                      
-system.ruby.network.routers4.throttle0.link_utilization    15.909534                      
-system.ruby.network.routers4.throttle0.msg_count.Request_Control::3           48                      
-system.ruby.network.routers4.throttle0.msg_count.Response_Data::4        77143                      
-system.ruby.network.routers4.throttle0.msg_count.Response_Control::4       537177                      
-system.ruby.network.routers4.throttle0.msg_count.Writeback_Control::3        72792                      
-system.ruby.network.routers4.throttle0.msg_count.Broadcast_Control::3       539876                      
-system.ruby.network.routers4.throttle0.msg_bytes.Request_Control::3          384                      
-system.ruby.network.routers4.throttle0.msg_bytes.Response_Data::4      5554296                      
-system.ruby.network.routers4.throttle0.msg_bytes.Response_Control::4      4297416                      
-system.ruby.network.routers4.throttle0.msg_bytes.Writeback_Control::3       582336                      
-system.ruby.network.routers4.throttle0.msg_bytes.Broadcast_Control::3      4319008                      
-system.ruby.network.routers4.throttle1.link_utilization     9.255089                      
-system.ruby.network.routers4.throttle1.msg_count.Request_Control::2        77146                      
-system.ruby.network.routers4.throttle1.msg_count.Response_Data::4         2476                      
-system.ruby.network.routers4.throttle1.msg_count.Response_Control::4       537446                      
-system.ruby.network.routers4.throttle1.msg_count.Writeback_Data::5        26652                      
-system.ruby.network.routers4.throttle1.msg_count.Writeback_Control::2        72792                      
-system.ruby.network.routers4.throttle1.msg_count.Writeback_Control::5        46109                      
-system.ruby.network.routers4.throttle1.msg_count.Unblock_Control::5        77174                      
-system.ruby.network.routers4.throttle1.msg_bytes.Request_Control::2       617168                      
-system.ruby.network.routers4.throttle1.msg_bytes.Response_Data::4       178272                      
-system.ruby.network.routers4.throttle1.msg_bytes.Response_Control::4      4299568                      
-system.ruby.network.routers4.throttle1.msg_bytes.Writeback_Data::5      1918944                      
-system.ruby.network.routers4.throttle1.msg_bytes.Writeback_Control::2       582336                      
-system.ruby.network.routers4.throttle1.msg_bytes.Writeback_Control::5       368872                      
-system.ruby.network.routers4.throttle1.msg_bytes.Unblock_Control::5       617392                      
-system.ruby.network.routers5.throttle0.link_utilization    15.887509                      
-system.ruby.network.routers5.throttle0.msg_count.Request_Control::3           51                      
-system.ruby.network.routers5.throttle0.msg_count.Response_Data::4        76990                      
-system.ruby.network.routers5.throttle0.msg_count.Response_Control::4       536067                      
-system.ruby.network.routers5.throttle0.msg_count.Writeback_Control::3        72564                      
-system.ruby.network.routers5.throttle0.msg_count.Broadcast_Control::3       540035                      
-system.ruby.network.routers5.throttle0.msg_bytes.Request_Control::3          408                      
-system.ruby.network.routers5.throttle0.msg_bytes.Response_Data::4      5543280                      
-system.ruby.network.routers5.throttle0.msg_bytes.Response_Control::4      4288536                      
-system.ruby.network.routers5.throttle0.msg_bytes.Writeback_Control::3       580512                      
-system.ruby.network.routers5.throttle0.msg_bytes.Broadcast_Control::3      4320280                      
-system.ruby.network.routers5.throttle1.link_utilization     9.256668                      
-system.ruby.network.routers5.throttle1.msg_count.Request_Control::2        76992                      
-system.ruby.network.routers5.throttle1.msg_count.Response_Data::4         2514                      
-system.ruby.network.routers5.throttle1.msg_count.Response_Control::4       537570                      
-system.ruby.network.routers5.throttle1.msg_count.Writeback_Data::5        26712                      
-system.ruby.network.routers5.throttle1.msg_count.Writeback_Control::2        72564                      
-system.ruby.network.routers5.throttle1.msg_count.Writeback_Control::5        45823                      
-system.ruby.network.routers5.throttle1.msg_count.Unblock_Control::5        77019                      
-system.ruby.network.routers5.throttle1.msg_bytes.Request_Control::2       615936                      
-system.ruby.network.routers5.throttle1.msg_bytes.Response_Data::4       181008                      
-system.ruby.network.routers5.throttle1.msg_bytes.Response_Control::4      4300560                      
-system.ruby.network.routers5.throttle1.msg_bytes.Writeback_Data::5      1923264                      
-system.ruby.network.routers5.throttle1.msg_bytes.Writeback_Control::2       580512                      
-system.ruby.network.routers5.throttle1.msg_bytes.Writeback_Control::5       366584                      
-system.ruby.network.routers5.throttle1.msg_bytes.Unblock_Control::5       616152                      
-system.ruby.network.routers6.throttle0.link_utilization    15.964409                      
-system.ruby.network.routers6.throttle0.msg_count.Request_Control::3           52                      
-system.ruby.network.routers6.throttle0.msg_count.Response_Data::4        77539                      
-system.ruby.network.routers6.throttle0.msg_count.Response_Control::4       540002                      
-system.ruby.network.routers6.throttle0.msg_count.Writeback_Control::3        73169                      
-system.ruby.network.routers6.throttle0.msg_count.Broadcast_Control::3       539467                      
-system.ruby.network.routers6.throttle0.msg_bytes.Request_Control::3          416                      
-system.ruby.network.routers6.throttle0.msg_bytes.Response_Data::4      5582808                      
-system.ruby.network.routers6.throttle0.msg_bytes.Response_Control::4      4320016                      
-system.ruby.network.routers6.throttle0.msg_bytes.Writeback_Control::3       585352                      
-system.ruby.network.routers6.throttle0.msg_bytes.Broadcast_Control::3      4315736                      
-system.ruby.network.routers6.throttle1.link_utilization     9.289019                      
-system.ruby.network.routers6.throttle1.msg_count.Request_Control::2        77542                      
-system.ruby.network.routers6.throttle1.msg_count.Response_Data::4         2478                      
-system.ruby.network.routers6.throttle1.msg_count.Response_Control::4       537039                      
-system.ruby.network.routers6.throttle1.msg_count.Writeback_Data::5        26999                      
-system.ruby.network.routers6.throttle1.msg_count.Writeback_Control::2        73171                      
-system.ruby.network.routers6.throttle1.msg_count.Writeback_Control::5        46140                      
-system.ruby.network.routers6.throttle1.msg_count.Unblock_Control::5        77567                      
-system.ruby.network.routers6.throttle1.msg_bytes.Request_Control::2       620336                      
-system.ruby.network.routers6.throttle1.msg_bytes.Response_Data::4       178416                      
-system.ruby.network.routers6.throttle1.msg_bytes.Response_Control::4      4296312                      
-system.ruby.network.routers6.throttle1.msg_bytes.Writeback_Data::5      1943928                      
-system.ruby.network.routers6.throttle1.msg_bytes.Writeback_Control::2       585368                      
-system.ruby.network.routers6.throttle1.msg_bytes.Writeback_Control::5       369120                      
-system.ruby.network.routers6.throttle1.msg_bytes.Unblock_Control::5       620536                      
-system.ruby.network.routers7.throttle0.link_utilization    15.872058                      
-system.ruby.network.routers7.throttle0.msg_count.Request_Control::3           58                      
-system.ruby.network.routers7.throttle0.msg_count.Response_Data::4        76888                      
-system.ruby.network.routers7.throttle0.msg_count.Response_Control::4       535320                      
-system.ruby.network.routers7.throttle0.msg_count.Writeback_Control::3        72340                      
-system.ruby.network.routers7.throttle0.msg_count.Broadcast_Control::3       540126                      
-system.ruby.network.routers7.throttle0.msg_bytes.Request_Control::3          464                      
-system.ruby.network.routers7.throttle0.msg_bytes.Response_Data::4      5535936                      
-system.ruby.network.routers7.throttle0.msg_bytes.Response_Control::4      4282560                      
-system.ruby.network.routers7.throttle0.msg_bytes.Writeback_Control::3       578720                      
-system.ruby.network.routers7.throttle0.msg_bytes.Broadcast_Control::3      4321008                      
-system.ruby.network.routers7.throttle1.link_utilization     9.246738                      
-system.ruby.network.routers7.throttle1.msg_count.Request_Control::2        76892                      
-system.ruby.network.routers7.throttle1.msg_count.Response_Data::4         2497                      
-system.ruby.network.routers7.throttle1.msg_count.Response_Control::4       537687                      
-system.ruby.network.routers7.throttle1.msg_count.Writeback_Data::5        26654                      
-system.ruby.network.routers7.throttle1.msg_count.Writeback_Control::2        72340                      
-system.ruby.network.routers7.throttle1.msg_count.Writeback_Control::5        45668                      
-system.ruby.network.routers7.throttle1.msg_count.Unblock_Control::5        76905                      
-system.ruby.network.routers7.throttle1.msg_bytes.Request_Control::2       615136                      
-system.ruby.network.routers7.throttle1.msg_bytes.Response_Data::4       179784                      
-system.ruby.network.routers7.throttle1.msg_bytes.Response_Control::4      4301496                      
-system.ruby.network.routers7.throttle1.msg_bytes.Writeback_Data::5      1919088                      
-system.ruby.network.routers7.throttle1.msg_bytes.Writeback_Control::2       578720                      
-system.ruby.network.routers7.throttle1.msg_bytes.Writeback_Control::5       365344                      
-system.ruby.network.routers7.throttle1.msg_bytes.Unblock_Control::5       615240                      
-system.ruby.network.routers8.throttle0.link_utilization    35.469802                      
-system.ruby.network.routers8.throttle0.msg_count.Request_Control::2       617400                      
-system.ruby.network.routers8.throttle0.msg_count.Writeback_Data::5       214023                      
-system.ruby.network.routers8.throttle0.msg_count.Writeback_Control::2       582292                      
-system.ruby.network.routers8.throttle0.msg_count.Writeback_Control::5       368046                      
-system.ruby.network.routers8.throttle0.msg_count.Unblock_Control::5       617596                      
-system.ruby.network.routers8.throttle0.msg_bytes.Request_Control::2      4939200                      
-system.ruby.network.routers8.throttle0.msg_bytes.Writeback_Data::5     15409656                      
-system.ruby.network.routers8.throttle0.msg_bytes.Writeback_Control::2      4658336                      
-system.ruby.network.routers8.throttle0.msg_bytes.Writeback_Control::5      2944368                      
-system.ruby.network.routers8.throttle0.msg_bytes.Unblock_Control::5      4940768                      
-system.ruby.network.routers8.throttle1.link_utilization    56.740852                      
-system.ruby.network.routers8.throttle1.msg_count.Request_Control::3          439                      
-system.ruby.network.routers8.throttle1.msg_count.Response_Data::4       597502                      
-system.ruby.network.routers8.throttle1.msg_count.Writeback_Control::3       582292                      
-system.ruby.network.routers8.throttle1.msg_count.Broadcast_Control::3       616961                      
-system.ruby.network.routers8.throttle1.msg_bytes.Request_Control::3         3512                      
-system.ruby.network.routers8.throttle1.msg_bytes.Response_Data::4     43020144                      
-system.ruby.network.routers8.throttle1.msg_bytes.Writeback_Control::3      4658336                      
-system.ruby.network.routers8.throttle1.msg_bytes.Broadcast_Control::3      4935688                      
-system.ruby.network.routers9.throttle0.link_utilization    15.875423                      
-system.ruby.network.routers9.throttle0.msg_count.Request_Control::3           67                      
-system.ruby.network.routers9.throttle0.msg_count.Response_Data::4        76886                      
-system.ruby.network.routers9.throttle0.msg_count.Response_Control::4       535445                      
-system.ruby.network.routers9.throttle0.msg_count.Writeback_Control::3        72619                      
-system.ruby.network.routers9.throttle0.msg_count.Broadcast_Control::3       540121                      
-system.ruby.network.routers9.throttle0.msg_bytes.Request_Control::3          536                      
-system.ruby.network.routers9.throttle0.msg_bytes.Response_Data::4      5535792                      
-system.ruby.network.routers9.throttle0.msg_bytes.Response_Control::4      4283560                      
-system.ruby.network.routers9.throttle0.msg_bytes.Writeback_Control::3       580952                      
-system.ruby.network.routers9.throttle0.msg_bytes.Broadcast_Control::3      4320968                      
-system.ruby.network.routers9.throttle1.link_utilization    15.944041                      
-system.ruby.network.routers9.throttle1.msg_count.Request_Control::3           47                      
-system.ruby.network.routers9.throttle1.msg_count.Response_Data::4        77389                      
-system.ruby.network.routers9.throttle1.msg_count.Response_Control::4       538997                      
-system.ruby.network.routers9.throttle1.msg_count.Writeback_Control::3        73022                      
-system.ruby.network.routers9.throttle1.msg_count.Broadcast_Control::3       539613                      
-system.ruby.network.routers9.throttle1.msg_bytes.Request_Control::3          376                      
-system.ruby.network.routers9.throttle1.msg_bytes.Response_Data::4      5572008                      
-system.ruby.network.routers9.throttle1.msg_bytes.Response_Control::4      4311976                      
-system.ruby.network.routers9.throttle1.msg_bytes.Writeback_Control::3       584176                      
-system.ruby.network.routers9.throttle1.msg_bytes.Broadcast_Control::3      4316904                      
-system.ruby.network.routers9.throttle2.link_utilization    15.919446                      
-system.ruby.network.routers9.throttle2.msg_count.Request_Control::3           56                      
-system.ruby.network.routers9.throttle2.msg_count.Response_Data::4        77214                      
-system.ruby.network.routers9.throttle2.msg_count.Response_Control::4       537730                      
-system.ruby.network.routers9.throttle2.msg_count.Writeback_Control::3        72821                      
-system.ruby.network.routers9.throttle2.msg_count.Broadcast_Control::3       539797                      
-system.ruby.network.routers9.throttle2.msg_bytes.Request_Control::3          448                      
-system.ruby.network.routers9.throttle2.msg_bytes.Response_Data::4      5559408                      
-system.ruby.network.routers9.throttle2.msg_bytes.Response_Control::4      4301840                      
-system.ruby.network.routers9.throttle2.msg_bytes.Writeback_Control::3       582568                      
-system.ruby.network.routers9.throttle2.msg_bytes.Broadcast_Control::3      4318376                      
-system.ruby.network.routers9.throttle3.link_utilization    15.935501                      
-system.ruby.network.routers9.throttle3.msg_count.Request_Control::3           60                      
-system.ruby.network.routers9.throttle3.msg_count.Response_Data::4        77328                      
-system.ruby.network.routers9.throttle3.msg_count.Response_Control::4       538521                      
-system.ruby.network.routers9.throttle3.msg_count.Writeback_Control::3        72965                      
-system.ruby.network.routers9.throttle3.msg_count.Broadcast_Control::3       539692                      
-system.ruby.network.routers9.throttle3.msg_bytes.Request_Control::3          480                      
-system.ruby.network.routers9.throttle3.msg_bytes.Response_Data::4      5567616                      
-system.ruby.network.routers9.throttle3.msg_bytes.Response_Control::4      4308168                      
-system.ruby.network.routers9.throttle3.msg_bytes.Writeback_Control::3       583720                      
-system.ruby.network.routers9.throttle3.msg_bytes.Broadcast_Control::3      4317536                      
-system.ruby.network.routers9.throttle4.link_utilization    15.909568                      
-system.ruby.network.routers9.throttle4.msg_count.Request_Control::3           48                      
-system.ruby.network.routers9.throttle4.msg_count.Response_Data::4        77143                      
-system.ruby.network.routers9.throttle4.msg_count.Response_Control::4       537181                      
-system.ruby.network.routers9.throttle4.msg_count.Writeback_Control::3        72792                      
-system.ruby.network.routers9.throttle4.msg_count.Broadcast_Control::3       539876                      
-system.ruby.network.routers9.throttle4.msg_bytes.Request_Control::3          384                      
-system.ruby.network.routers9.throttle4.msg_bytes.Response_Data::4      5554296                      
-system.ruby.network.routers9.throttle4.msg_bytes.Response_Control::4      4297448                      
-system.ruby.network.routers9.throttle4.msg_bytes.Writeback_Control::3       582336                      
-system.ruby.network.routers9.throttle4.msg_bytes.Broadcast_Control::3      4319008                      
-system.ruby.network.routers9.throttle5.link_utilization    15.887509                      
-system.ruby.network.routers9.throttle5.msg_count.Request_Control::3           51                      
-system.ruby.network.routers9.throttle5.msg_count.Response_Data::4        76990                      
-system.ruby.network.routers9.throttle5.msg_count.Response_Control::4       536067                      
-system.ruby.network.routers9.throttle5.msg_count.Writeback_Control::3        72564                      
-system.ruby.network.routers9.throttle5.msg_count.Broadcast_Control::3       540035                      
-system.ruby.network.routers9.throttle5.msg_bytes.Request_Control::3          408                      
-system.ruby.network.routers9.throttle5.msg_bytes.Response_Data::4      5543280                      
-system.ruby.network.routers9.throttle5.msg_bytes.Response_Control::4      4288536                      
-system.ruby.network.routers9.throttle5.msg_bytes.Writeback_Control::3       580512                      
-system.ruby.network.routers9.throttle5.msg_bytes.Broadcast_Control::3      4320280                      
-system.ruby.network.routers9.throttle6.link_utilization    15.964409                      
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 system.ruby.LD.latency_hist::bucket_size         1024                      
 system.ruby.LD.latency_hist::max_bucket         10239                      
-system.ruby.LD.latency_hist::samples           401404                      
-system.ruby.LD.latency_hist::mean         1200.205225                      
-system.ruby.LD.latency_hist::gmean         820.467518                      
-system.ruby.LD.latency_hist::stdev         896.107731                      
-system.ruby.LD.latency_hist              |      206231     51.38%     51.38% |      106792     26.60%     77.98% |       80227     19.99%     97.97% |        8012      2.00%     99.96% |         141      0.04%    100.00% |           1      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.LD.latency_hist::total             401404                      
-system.ruby.LD.hit_latency_hist::bucket_size          256                      
-system.ruby.LD.hit_latency_hist::max_bucket         2559                      
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-system.ruby.LD.hit_latency_hist::mean      129.788306                      
-system.ruby.LD.hit_latency_hist::gmean      40.678454                      
-system.ruby.LD.hit_latency_hist::stdev     179.340502                      
-system.ruby.LD.hit_latency_hist          |         409     82.46%     82.46% |          72     14.52%     96.98% |           8      1.61%     98.59% |           5      1.01%     99.60% |           1      0.20%     99.80% |           0      0.00%     99.80% |           0      0.00%     99.80% |           1      0.20%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.LD.hit_latency_hist::total            496                      
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+system.ruby.LD.latency_hist::stdev         899.503786                      
+system.ruby.LD.latency_hist              |      207765     51.36%     51.36% |      106851     26.41%     77.77% |       81488     20.14%     97.91% |        8228      2.03%     99.95% |         210      0.05%    100.00% |           6      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
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+system.ruby.LD.hit_latency_hist::stdev     171.671956                      
+system.ruby.LD.hit_latency_hist          |         282     57.55%     57.55% |         119     24.29%     81.84% |          50     10.20%     92.04% |          20      4.08%     96.12% |           8      1.63%     97.76% |           6      1.22%     98.98% |           1      0.20%     99.18% |           3      0.61%     99.80% |           1      0.20%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.hit_latency_hist::total            490                      
 system.ruby.LD.miss_latency_hist::bucket_size         1024                      
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-system.ruby.LD.miss_latency_hist::gmean    823.522657                      
-system.ruby.LD.miss_latency_hist::stdev    895.847928                      
-system.ruby.LD.miss_latency_hist         |      205737     51.32%     51.32% |      106790     26.64%     77.95% |       80227     20.01%     97.97% |        8012      2.00%     99.96% |         141      0.04%    100.00% |           1      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.LD.miss_latency_hist::total        400908                      
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-system.ruby.ST.latency_hist::stdev         895.164370                      
-system.ruby.ST.latency_hist              |       72217     33.32%     33.32% |       39245     18.11%     51.43% |       26157     12.07%     63.50% |       31400     14.49%     77.99% |       29405     13.57%     91.56% |       13948      6.44%     98.00% |        3617      1.67%     99.67% |         640      0.30%     99.96% |          77      0.04%    100.00% |           6      0.00%    100.00%
-system.ruby.ST.latency_hist::total             216712                      
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-system.ruby.ST.hit_latency_hist::gmean      42.603184                      
-system.ruby.ST.hit_latency_hist::stdev     171.207823                      
-system.ruby.ST.hit_latency_hist          |         141     58.51%     58.51% |          50     20.75%     79.25% |          31     12.86%     92.12% |           6      2.49%     94.61% |           6      2.49%     97.10% |           6      2.49%     99.59% |           1      0.41%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.ST.hit_latency_hist::total            241                      
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-system.ruby.ST.miss_latency_hist::stdev    894.945970                      
-system.ruby.ST.miss_latency_hist         |       71989     33.26%     33.26% |       39232     18.12%     51.38% |       26157     12.08%     63.46% |       31400     14.51%     77.97% |       29405     13.58%     91.55% |       13948      6.44%     98.00% |        3617      1.67%     99.67% |         640      0.30%     99.96% |          77      0.04%    100.00% |           6      0.00%    100.00%
-system.ruby.ST.miss_latency_hist::total        216471                      
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+system.ruby.ST.hit_latency_hist          |         211     80.53%     80.53% |          40     15.27%     95.80% |           6      2.29%     98.09% |           3      1.15%     99.24% |           0      0.00%     99.24% |           1      0.38%     99.62% |           1      0.38%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
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+system.ruby.ST.miss_latency_hist         |      114524     51.07%     51.07% |       59881     26.70%     77.77% |       45124     20.12%     97.90% |        4585      2.04%     99.94% |         130      0.06%    100.00% |           1      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
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 system.ruby.L1Cache.hit_mach_latency_hist::bucket_size            1                      
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-system.ruby.L1Cache.hit_mach_latency_hist::samples          138                      
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-system.ruby.L1Cache.hit_mach_latency_hist::gmean     2.000000                      
-system.ruby.L1Cache.hit_mach_latency_hist |           0      0.00%      0.00% |           0      0.00%      0.00% |         138    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.L1Cache.hit_mach_latency_hist::total          138                      
+system.ruby.L1Cache.hit_mach_latency_hist::gmean            2                      
+system.ruby.L1Cache.hit_mach_latency_hist |           0      0.00%      0.00% |           0      0.00%      0.00% |         142    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
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 system.ruby.L1Cache.miss_mach_latency_hist::max_bucket         5119                      
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-system.ruby.L1Cache.miss_mach_latency_hist::stdev   891.446161                      
-system.ruby.L1Cache.miss_mach_latency_hist |        8066     40.58%     40.58% |        2780     13.99%     54.57% |        2446     12.31%     66.87% |        2998     15.08%     81.95% |        2398     12.06%     94.02% |         956      4.81%     98.83% |         195      0.98%     99.81% |          36      0.18%     99.99% |           2      0.01%    100.00% |           0      0.00%    100.00%
-system.ruby.L1Cache.miss_mach_latency_hist::total        19877                      
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+system.ruby.L1Cache.miss_mach_latency_hist::stdev   895.586319                      
+system.ruby.L1Cache.miss_mach_latency_hist |        8287     40.26%     40.26% |        2815     13.68%     53.94% |        2557     12.42%     66.36% |        3192     15.51%     81.87% |        2465     11.98%     93.85% |         962      4.67%     98.52% |         261      1.27%     99.79% |          37      0.18%     99.97% |           5      0.02%    100.00% |           1      0.00%    100.00%
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 system.ruby.L1Cache.miss_latency_hist.issue_to_initial_request::max_bucket         5119                      
-system.ruby.L1Cache.miss_latency_hist.issue_to_initial_request::samples        19438                      
-system.ruby.L1Cache.miss_latency_hist.issue_to_initial_request::mean   985.051343                      
-system.ruby.L1Cache.miss_latency_hist.issue_to_initial_request::gmean   380.663652                      
-system.ruby.L1Cache.miss_latency_hist.issue_to_initial_request::stdev   886.076563                      
-system.ruby.L1Cache.miss_latency_hist.issue_to_initial_request |        8575     44.11%     44.11% |        2388     12.29%     56.40% |        2456     12.64%     69.03% |        2961     15.23%     84.27% |        2158     11.10%     95.37% |         735      3.78%     99.15% |         140      0.72%     99.87% |          24      0.12%     99.99% |           1      0.01%    100.00% |           0      0.00%    100.00%
-system.ruby.L1Cache.miss_latency_hist.issue_to_initial_request::total        19438                      
+system.ruby.L1Cache.miss_latency_hist.issue_to_initial_request::samples        20159                      
+system.ruby.L1Cache.miss_latency_hist.issue_to_initial_request::mean   995.735453                      
+system.ruby.L1Cache.miss_latency_hist.issue_to_initial_request::gmean   387.436377                      
+system.ruby.L1Cache.miss_latency_hist.issue_to_initial_request::stdev   890.441418                      
+system.ruby.L1Cache.miss_latency_hist.issue_to_initial_request |        8785     43.58%     43.58% |        2515     12.48%     56.05% |        2495     12.38%     68.43% |        3188     15.81%     84.25% |        2171     10.77%     95.01% |         809      4.01%     99.03% |         167      0.83%     99.86% |          27      0.13%     99.99% |           1      0.00%    100.00% |           1      0.00%    100.00%
+system.ruby.L1Cache.miss_latency_hist.issue_to_initial_request::total        20159                      
 system.ruby.L1Cache.miss_latency_hist.initial_to_forward::bucket_size          128                      
 system.ruby.L1Cache.miss_latency_hist.initial_to_forward::max_bucket         1279                      
-system.ruby.L1Cache.miss_latency_hist.initial_to_forward::samples        19438                      
-system.ruby.L1Cache.miss_latency_hist.initial_to_forward::mean    56.696677                      
-system.ruby.L1Cache.miss_latency_hist.initial_to_forward::gmean    19.964374                      
-system.ruby.L1Cache.miss_latency_hist.initial_to_forward::stdev    97.360116                      
-system.ruby.L1Cache.miss_latency_hist.initial_to_forward |       16154     83.11%     83.11% |        2126     10.94%     94.04% |         813      4.18%     98.23% |         254      1.31%     99.53% |          69      0.35%     99.89% |          19      0.10%     99.98% |           2      0.01%     99.99% |           1      0.01%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.L1Cache.miss_latency_hist.initial_to_forward::total        19438                      
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+system.ruby.L1Cache.miss_latency_hist.initial_to_forward::stdev    98.374308                      
+system.ruby.L1Cache.miss_latency_hist.initial_to_forward |       16939     84.03%     84.03% |        2034     10.09%     94.12% |         801      3.97%     98.09% |         289      1.43%     99.52% |          69      0.34%     99.87% |          13      0.06%     99.93% |           9      0.04%     99.98% |           3      0.01%     99.99% |           1      0.00%    100.00% |           1      0.00%    100.00%
+system.ruby.L1Cache.miss_latency_hist.initial_to_forward::total        20159                      
 system.ruby.L1Cache.miss_latency_hist.forward_to_first_response::bucket_size            8                      
 system.ruby.L1Cache.miss_latency_hist.forward_to_first_response::max_bucket           79                      
-system.ruby.L1Cache.miss_latency_hist.forward_to_first_response::samples        19438                      
-system.ruby.L1Cache.miss_latency_hist.forward_to_first_response::mean    25.929108                      
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-system.ruby.L1Cache.miss_latency_hist.forward_to_first_response::stdev     2.214187                      
-system.ruby.L1Cache.miss_latency_hist.forward_to_first_response |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |       19044     97.97%     97.97% |         390      2.01%     99.98% |           4      0.02%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.L1Cache.miss_latency_hist.forward_to_first_response::total        19438                      
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+system.ruby.L1Cache.miss_latency_hist.forward_to_first_response::stdev     2.232570                      
+system.ruby.L1Cache.miss_latency_hist.forward_to_first_response |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |       19700     97.72%     97.72% |         454      2.25%     99.98% |           5      0.02%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache.miss_latency_hist.forward_to_first_response::total        20159                      
 system.ruby.L1Cache.miss_latency_hist.first_response_to_completion::bucket_size            2                      
 system.ruby.L1Cache.miss_latency_hist.first_response_to_completion::max_bucket           19                      
-system.ruby.L1Cache.miss_latency_hist.first_response_to_completion::samples        19438                      
-system.ruby.L1Cache.miss_latency_hist.first_response_to_completion::mean     1.883990                      
-system.ruby.L1Cache.miss_latency_hist.first_response_to_completion::stdev     1.916605                      
-system.ruby.L1Cache.miss_latency_hist.first_response_to_completion |        9557     49.17%     49.17% |        7546     38.82%     87.99% |        1175      6.04%     94.03% |         733      3.77%     97.80% |         258      1.33%     99.13% |         122      0.63%     99.76% |          25      0.13%     99.89% |          17      0.09%     99.97% |           5      0.03%    100.00% |           0      0.00%    100.00%
-system.ruby.L1Cache.miss_latency_hist.first_response_to_completion::total        19438                      
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+system.ruby.L1Cache.miss_latency_hist.first_response_to_completion |        9775     48.49%     48.49% |        7935     39.36%     87.85% |        1298      6.44%     94.29% |         729      3.62%     97.91% |         268      1.33%     99.24% |         107      0.53%     99.77% |          30      0.15%     99.92% |          14      0.07%     99.99% |           3      0.01%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache.miss_latency_hist.first_response_to_completion::total        20159                      
 system.ruby.L2Cache.hit_mach_latency_hist::bucket_size          256                      
 system.ruby.L2Cache.hit_mach_latency_hist::max_bucket         2559                      
-system.ruby.L2Cache.hit_mach_latency_hist::samples          599                      
-system.ruby.L2Cache.hit_mach_latency_hist::mean   163.504174                      
-system.ruby.L2Cache.hit_mach_latency_hist::gmean    82.958655                      
-system.ruby.L2Cache.hit_mach_latency_hist::stdev   183.100288                      
-system.ruby.L2Cache.hit_mach_latency_hist |         462     77.13%     77.13% |         109     18.20%     95.33% |          20      3.34%     98.66% |           6      1.00%     99.67% |           1      0.17%     99.83% |           0      0.00%     99.83% |           0      0.00%     99.83% |           1      0.17%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.L2Cache.hit_mach_latency_hist::total          599                      
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+system.ruby.L2Cache.hit_mach_latency_hist::stdev   192.743659                      
+system.ruby.L2Cache.hit_mach_latency_hist |         470     77.05%     77.05% |         110     18.03%     95.08% |          20      3.28%     98.36% |           7      1.15%     99.51% |           1      0.16%     99.67% |           1      0.16%     99.84% |           1      0.16%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.L2Cache.hit_mach_latency_hist::total          610                      
 system.ruby.Directory.miss_mach_latency_hist::bucket_size         1024                      
 system.ruby.Directory.miss_mach_latency_hist::max_bucket        10239                      
-system.ruby.Directory.miss_mach_latency_hist::samples       597502                      
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-system.ruby.Directory.miss_mach_latency_hist::gmean   831.864990                      
-system.ruby.Directory.miss_mach_latency_hist::stdev   895.329653                      
-system.ruby.Directory.miss_mach_latency_hist |      306112     51.23%     51.23% |      158903     26.59%     77.83% |      120226     20.12%     97.95% |       12038      2.01%     99.96% |         222      0.04%    100.00% |           1      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.Directory.miss_mach_latency_hist::total       597502                      
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-system.ruby.Directory.miss_latency_hist.issue_to_initial_request::mean   986.665291                      
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-system.ruby.Directory.miss_latency_hist.issue_to_initial_request::stdev   885.752609                      
-system.ruby.Directory.miss_latency_hist.issue_to_initial_request |      262430     43.92%     43.92% |       74515     12.47%     56.39% |       75171     12.58%     68.97% |       92711     15.52%     84.49% |       64576     10.81%     95.30% |       22828      3.82%     99.12% |        4553      0.76%     99.88% |         651      0.11%     99.99% |          67      0.01%    100.00% |           0      0.00%    100.00%
-system.ruby.Directory.miss_latency_hist.issue_to_initial_request::total       597502                      
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+system.ruby.Directory.miss_mach_latency_hist::stdev   898.577352                      
+system.ruby.Directory.miss_mach_latency_hist |      310698     51.13%     51.13% |      160982     26.49%     77.61% |      123185     20.27%     97.88% |       12515      2.06%     99.94% |         334      0.05%    100.00% |           7      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.Directory.miss_mach_latency_hist::total       607721                      
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+system.ruby.Directory.miss_latency_hist.issue_to_initial_request::stdev   888.781055                      
+system.ruby.Directory.miss_latency_hist.issue_to_initial_request |      342354     56.33%     56.33% |      169786     27.94%     84.27% |       89798     14.78%     99.05% |        5668      0.93%     99.98% |         112      0.02%    100.00% |           3      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
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 system.ruby.Directory.miss_latency_hist.initial_to_forward::bucket_size          128                      
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-system.ruby.Directory.miss_latency_hist.initial_to_forward::stdev    16.805315                      
-system.ruby.Directory.miss_latency_hist.initial_to_forward |      595424     99.65%     99.65% |        1243      0.21%     99.86% |         564      0.09%     99.95% |         180      0.03%     99.98% |          66      0.01%    100.00% |          18      0.00%    100.00% |           6      0.00%    100.00% |           1      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.Directory.miss_latency_hist.initial_to_forward::total       597502                      
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+system.ruby.Directory.miss_latency_hist.initial_to_forward |      605646     99.66%     99.66% |        1201      0.20%     99.86% |         563      0.09%     99.95% |         192      0.03%     99.98% |          81      0.01%     99.99% |          28      0.00%    100.00% |           7      0.00%    100.00% |           2      0.00%    100.00% |           1      0.00%    100.00% |           0      0.00%    100.00%
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 system.ruby.Directory.miss_latency_hist.forward_to_first_response::bucket_size            8                      
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-system.ruby.Directory.miss_latency_hist.forward_to_first_response::stdev     2.225599                      
-system.ruby.Directory.miss_latency_hist.forward_to_first_response |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |      583382     97.64%     97.64% |       14030      2.35%     99.98% |          90      0.02%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.Directory.miss_latency_hist.forward_to_first_response::total       597502                      
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+system.ruby.Directory.miss_latency_hist.forward_to_first_response |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |      593224     97.61%     97.61% |       14398      2.37%     99.98% |          99      0.02%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
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-system.ruby.Directory.miss_latency_hist.first_response_to_completion::stdev   133.940990                      
-system.ruby.Directory.miss_latency_hist.first_response_to_completion |      252378     42.24%     42.24% |      203805     34.11%     76.35% |       91328     15.28%     91.63% |       33805      5.66%     97.29% |       11457      1.92%     99.21% |        3490      0.58%     99.79% |         948      0.16%     99.95% |         231      0.04%     99.99% |          51      0.01%    100.00% |           9      0.00%    100.00%
-system.ruby.Directory.miss_latency_hist.first_response_to_completion::total       597502                      
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+system.ruby.Directory.miss_latency_hist.first_response_to_completion |      255219     42.00%     42.00% |      207246     34.10%     76.10% |       93561     15.40%     91.49% |       35437      5.83%     97.32% |       11568      1.90%     99.23% |        3450      0.57%     99.80% |         937      0.15%     99.95% |         242      0.04%     99.99% |          55      0.01%    100.00% |           6      0.00%    100.00%
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-system.ruby.LD.L1Cache.hit_type_mach_latency_hist::samples           88                      
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 system.ruby.LD.L1Cache.hit_type_mach_latency_hist::gmean            2                      
-system.ruby.LD.L1Cache.hit_type_mach_latency_hist |           0      0.00%      0.00% |           0      0.00%      0.00% |          88    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.LD.L1Cache.hit_type_mach_latency_hist::total           88                      
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-system.ruby.LD.L1Cache.miss_type_mach_latency_hist |        5286     40.86%     40.86% |        1815     14.03%     54.89% |        1582     12.23%     67.12% |        1934     14.95%     82.07% |        1539     11.90%     93.97% |         627      4.85%     98.82% |         128      0.99%     99.81% |          24      0.19%     99.99% |           1      0.01%    100.00% |           0      0.00%    100.00%
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-system.ruby.LD.L2Cache.hit_type_mach_latency_hist::stdev   186.614207                      
-system.ruby.LD.L2Cache.hit_type_mach_latency_hist |         321     78.68%     78.68% |          72     17.65%     96.32% |           8      1.96%     98.28% |           5      1.23%     99.51% |           1      0.25%     99.75% |           0      0.00%     99.75% |           0      0.00%     99.75% |           1      0.25%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.LD.L2Cache.hit_type_mach_latency_hist::total          408                      
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+system.ruby.LD.L1Cache.miss_type_mach_latency_hist::gmean   616.224244                      
+system.ruby.LD.L1Cache.miss_type_mach_latency_hist::stdev   894.841487                      
+system.ruby.LD.L1Cache.miss_type_mach_latency_hist |        5304     40.24%     40.24% |        1827     13.86%     54.10% |        1624     12.32%     66.42% |        2023     15.35%     81.77% |        1594     12.09%     93.86% |         613      4.65%     98.51% |         170      1.29%     99.80% |          23      0.17%     99.98% |           2      0.02%     99.99% |           1      0.01%    100.00%
+system.ruby.LD.L1Cache.miss_type_mach_latency_hist::total        13181                      
+system.ruby.LD.L2Cache.hit_type_mach_latency_hist::bucket_size          128                      
+system.ruby.LD.L2Cache.hit_type_mach_latency_hist::max_bucket         1279                      
+system.ruby.LD.L2Cache.hit_type_mach_latency_hist::samples          401                      
+system.ruby.LD.L2Cache.hit_type_mach_latency_hist::mean   169.992519                      
+system.ruby.LD.L2Cache.hit_type_mach_latency_hist::gmean    88.681357                      
+system.ruby.LD.L2Cache.hit_type_mach_latency_hist::stdev   175.755106                      
+system.ruby.LD.L2Cache.hit_type_mach_latency_hist |         193     48.13%     48.13% |         119     29.68%     77.81% |          50     12.47%     90.27% |          20      4.99%     95.26% |           8      2.00%     97.26% |           6      1.50%     98.75% |           1      0.25%     99.00% |           3      0.75%     99.75% |           1      0.25%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.L2Cache.hit_type_mach_latency_hist::total          401                      
 system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size         1024                      
 system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket        10239                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist::samples       387972                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist::mean  1206.137840                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean   832.105820                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev   895.608577                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist |      198636     51.20%     51.20% |      103274     26.62%     77.82% |       78061     20.12%     97.94% |        7860      2.03%     99.96% |         140      0.04%    100.00% |           1      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.LD.Directory.miss_type_mach_latency_hist::total       387972                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist::samples       390877                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist::mean  1209.415893                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean   833.719014                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev   899.100909                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist |      200145     51.20%     51.20% |      103203     26.40%     77.61% |       79281     20.28%     97.89% |        8035      2.06%     99.95% |         207      0.05%    100.00% |           6      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.Directory.miss_type_mach_latency_hist::total       390877                      
 system.ruby.ST.L1Cache.hit_type_mach_latency_hist::bucket_size            1                      
 system.ruby.ST.L1Cache.hit_type_mach_latency_hist::max_bucket            9                      
-system.ruby.ST.L1Cache.hit_type_mach_latency_hist::samples           50                      
+system.ruby.ST.L1Cache.hit_type_mach_latency_hist::samples           53                      
 system.ruby.ST.L1Cache.hit_type_mach_latency_hist::mean            2                      
 system.ruby.ST.L1Cache.hit_type_mach_latency_hist::gmean            2                      
-system.ruby.ST.L1Cache.hit_type_mach_latency_hist |           0      0.00%      0.00% |           0      0.00%      0.00% |          50    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.ST.L1Cache.hit_type_mach_latency_hist::total           50                      
+system.ruby.ST.L1Cache.hit_type_mach_latency_hist |           0      0.00%      0.00% |           0      0.00%      0.00% |          53    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.L1Cache.hit_type_mach_latency_hist::total           53                      
 system.ruby.ST.L1Cache.miss_type_mach_latency_hist::bucket_size          512                      
 system.ruby.ST.L1Cache.miss_type_mach_latency_hist::max_bucket         5119                      
-system.ruby.ST.L1Cache.miss_type_mach_latency_hist::samples         6941                      
-system.ruby.ST.L1Cache.miss_type_mach_latency_hist::mean  1078.536522                      
-system.ruby.ST.L1Cache.miss_type_mach_latency_hist::gmean   620.066573                      
-system.ruby.ST.L1Cache.miss_type_mach_latency_hist::stdev   890.327819                      
-system.ruby.ST.L1Cache.miss_type_mach_latency_hist |        2780     40.05%     40.05% |         965     13.90%     53.95% |         864     12.45%     66.40% |        1064     15.33%     81.73% |         859     12.38%     94.11% |         329      4.74%     98.85% |          67      0.97%     99.81% |          12      0.17%     99.99% |           1      0.01%    100.00% |           0      0.00%    100.00%
-system.ruby.ST.L1Cache.miss_type_mach_latency_hist::total         6941                      
-system.ruby.ST.L2Cache.hit_type_mach_latency_hist::bucket_size          128                      
-system.ruby.ST.L2Cache.hit_type_mach_latency_hist::max_bucket         1279                      
-system.ruby.ST.L2Cache.hit_type_mach_latency_hist::samples          191                      
-system.ruby.ST.L2Cache.hit_type_mach_latency_hist::mean   176.649215                      
-system.ruby.ST.L2Cache.hit_type_mach_latency_hist::gmean    94.884201                      
-system.ruby.ST.L2Cache.hit_type_mach_latency_hist::stdev   175.112077                      
-system.ruby.ST.L2Cache.hit_type_mach_latency_hist |          91     47.64%     47.64% |          50     26.18%     73.82% |          31     16.23%     90.05% |           6      3.14%     93.19% |           6      3.14%     96.34% |           6      3.14%     99.48% |           1      0.52%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.ST.L2Cache.hit_type_mach_latency_hist::total          191                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size          512                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket         5119                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist::samples       209530                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist::mean  1204.913583                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean   831.419247                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev   894.814552                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist |       69209     33.03%     33.03% |       38267     18.26%     51.29% |       25293     12.07%     63.37% |       30336     14.48%     77.84% |       28546     13.62%     91.47% |       13619      6.50%     97.97% |        3550      1.69%     99.66% |         628      0.30%     99.96% |          76      0.04%    100.00% |           6      0.00%    100.00%
-system.ruby.ST.Directory.miss_type_mach_latency_hist::total       209530                      
-system.ruby.L1Cache_Controller.Load      |       50266     12.51%     12.51% |       50315     12.53%     25.04% |       50271     12.52%     37.56% |       50212     12.50%     50.06% |       50263     12.51%     62.57% |       50069     12.47%     75.04% |       50306     12.52%     87.56% |       49970     12.44%    100.00%
-system.ruby.L1Cache_Controller.Load::total       401672                      
-system.ruby.L1Cache_Controller.Store     |       26762     12.34%     12.34% |       27215     12.55%     24.89% |       27106     12.50%     37.39% |       27272     12.58%     49.96% |       27014     12.46%     62.42% |       27080     12.49%     74.91% |       27361     12.62%     87.52% |       27054     12.48%    100.00%
-system.ruby.L1Cache_Controller.Store::total       216864                      
-system.ruby.L1Cache_Controller.L2_Replacement |       76877     12.45%     12.45% |       77378     12.53%     24.99% |       77204     12.51%     37.50% |       77319     12.53%     50.02% |       77135     12.50%     62.52% |       76978     12.47%     74.99% |       77528     12.56%     87.55% |       76877     12.45%    100.00%
-system.ruby.L1Cache_Controller.L2_Replacement::total       617296                      
-system.ruby.L1Cache_Controller.L1_to_L2  |      839684     12.46%     12.46% |      843217     12.52%     24.98% |      843158     12.52%     37.50% |      840771     12.48%     49.98% |      842565     12.51%     62.49% |      841910     12.50%     74.98% |      845488     12.55%     87.54% |      839694     12.46%    100.00%
-system.ruby.L1Cache_Controller.L1_to_L2::total      6736487                      
-system.ruby.L1Cache_Controller.Trigger_L2_to_L1D |          75     12.08%     12.08% |          72     11.59%     23.67% |          99     15.94%     39.61% |          79     12.72%     52.33% |          66     10.63%     62.96% |          89     14.33%     77.29% |          69     11.11%     88.41% |          72     11.59%    100.00%
-system.ruby.L1Cache_Controller.Trigger_L2_to_L1D::total          621                      
-system.ruby.L1Cache_Controller.Complete_L2_to_L1 |          75     12.08%     12.08% |          72     11.59%     23.67% |          99     15.94%     39.61% |          79     12.72%     52.33% |          66     10.63%     62.96% |          89     14.33%     77.29% |          69     11.11%     88.41% |          72     11.59%    100.00%
-system.ruby.L1Cache_Controller.Complete_L2_to_L1::total          621                      
-system.ruby.L1Cache_Controller.Other_GETX |      189761     12.52%     12.52% |      189309     12.49%     25.02% |      189417     12.50%     37.52% |      189262     12.49%     50.01% |      189522     12.51%     62.51% |      189457     12.50%     75.01% |      189156     12.48%     87.50% |      189455     12.50%    100.00%
-system.ruby.L1Cache_Controller.Other_GETX::total      1515339                      
-system.ruby.L1Cache_Controller.Other_GETS |      350360     12.50%     12.50% |      350304     12.50%     24.99% |      350380     12.50%     37.49% |      350430     12.50%     49.99% |      350354     12.50%     62.49% |      350578     12.51%     75.00% |      350311     12.50%     87.49% |      350671     12.51%    100.00%
-system.ruby.L1Cache_Controller.Other_GETS::total      2803388                      
-system.ruby.L1Cache_Controller.Merged_GETS |          67     15.26%     15.26% |          47     10.71%     25.97% |          56     12.76%     38.72% |          60     13.67%     52.39% |          48     10.93%     63.33% |          51     11.62%     74.94% |          52     11.85%     86.79% |          58     13.21%    100.00%
-system.ruby.L1Cache_Controller.Merged_GETS::total          439                      
-system.ruby.L1Cache_Controller.Ack       |      535380     12.45%     12.45% |      538939     12.54%     24.99% |      537669     12.51%     37.50% |      538458     12.53%     50.02% |      537124     12.49%     62.52% |      535993     12.47%     74.99% |      539952     12.56%     87.55% |      535252     12.45%    100.00%
-system.ruby.L1Cache_Controller.Ack::total      4298767                      
-system.ruby.L1Cache_Controller.Shared_Ack |          61     12.55%     12.55% |          58     11.93%     24.49% |          61     12.55%     37.04% |          63     12.96%     50.00% |          51     10.49%     60.49% |          74     15.23%     75.72% |          50     10.29%     86.01% |          68     13.99%    100.00%
-system.ruby.L1Cache_Controller.Shared_Ack::total          486                      
-system.ruby.L1Cache_Controller.Data      |        2873     11.99%     11.99% |        3045     12.71%     24.69% |        2960     12.35%     37.04% |        3027     12.63%     49.67% |        2998     12.51%     62.18% |        3000     12.52%     74.70% |        2981     12.44%     87.14% |        3082     12.86%    100.00%
-system.ruby.L1Cache_Controller.Data::total        23966                      
-system.ruby.L1Cache_Controller.Shared_Data |        1060     12.39%     12.39% |        1048     12.25%     24.63% |        1056     12.34%     36.98% |        1053     12.31%     49.28% |        1045     12.21%     61.49% |        1094     12.78%     74.28% |        1078     12.60%     86.88% |        1123     13.12%    100.00%
-system.ruby.L1Cache_Controller.Shared_Data::total         8557                      
-system.ruby.L1Cache_Controller.Exclusive_Data |       72953     12.47%     12.47% |       73296     12.53%     25.01% |       73198     12.52%     37.52% |       73248     12.52%     50.05% |       73100     12.50%     62.54% |       72896     12.46%     75.01% |       73480     12.56%     87.57% |       72683     12.43%    100.00%
-system.ruby.L1Cache_Controller.Exclusive_Data::total       584854                      
-system.ruby.L1Cache_Controller.Writeback_Ack |       72619     12.47%     12.47% |       73022     12.54%     25.01% |       72821     12.51%     37.52% |       72965     12.53%     50.05% |       72792     12.50%     62.55% |       72564     12.46%     75.01% |       73169     12.57%     87.58% |       72340     12.42%    100.00%
-system.ruby.L1Cache_Controller.Writeback_Ack::total       582292                      
-system.ruby.L1Cache_Controller.All_acks  |        1114     12.42%     12.42% |        1096     12.21%     24.63% |        1109     12.36%     36.99% |        1107     12.34%     49.33% |        1091     12.16%     61.48% |        1156     12.88%     74.37% |        1120     12.48%     86.85% |        1180     13.15%    100.00%
-system.ruby.L1Cache_Controller.All_acks::total         8973                      
-system.ruby.L1Cache_Controller.All_acks_no_sharers |       75773     12.45%     12.45% |       76294     12.54%     24.99% |       76104     12.51%     37.50% |       76221     12.53%     50.03% |       76052     12.50%     62.53% |       75834     12.46%     75.00% |       76419     12.56%     87.56% |       75708     12.44%    100.00%
-system.ruby.L1Cache_Controller.All_acks_no_sharers::total       608405                      
-system.ruby.L1Cache_Controller.I.Load    |       50174     12.51%     12.51% |       50224     12.53%     25.04% |       50155     12.51%     37.55% |       50116     12.50%     50.05% |       50191     12.52%     62.57% |       49971     12.46%     75.04% |       50219     12.53%     87.56% |       49868     12.44%    100.00%
-system.ruby.L1Cache_Controller.I.Load::total       400918                      
-system.ruby.L1Cache_Controller.I.Store   |       26713     12.34%     12.34% |       27165     12.55%     24.89% |       27060     12.50%     37.39% |       27213     12.57%     49.96% |       26955     12.45%     62.42% |       27016     12.48%     74.90% |       27320     12.62%     87.52% |       27019     12.48%    100.00%
-system.ruby.L1Cache_Controller.I.Store::total       216461                      
-system.ruby.L1Cache_Controller.I.L2_Replacement |        1339     11.82%     11.82% |        1403     12.39%     24.21% |        1446     12.76%     36.97% |        1410     12.45%     49.42% |        1437     12.69%     62.10% |        1441     12.72%     74.82% |        1373     12.12%     86.94% |        1479     13.06%    100.00%
-system.ruby.L1Cache_Controller.I.L2_Replacement::total        11328                      
-system.ruby.L1Cache_Controller.I.L1_to_L2 |         263     12.00%     12.00% |         295     13.46%     25.47% |         253     11.55%     37.02% |         281     12.83%     49.84% |         292     13.33%     63.17% |         256     11.68%     74.85% |         261     11.91%     86.76% |         290     13.24%    100.00%
-system.ruby.L1Cache_Controller.I.L1_to_L2::total         2191                      
-system.ruby.L1Cache_Controller.I.Trigger_L2_to_L1D |           3     20.00%     20.00% |           0      0.00%     20.00% |           1      6.67%     26.67% |           2     13.33%     40.00% |           0      0.00%     40.00% |           4     26.67%     66.67% |           2     13.33%     80.00% |           3     20.00%    100.00%
+system.ruby.ST.L1Cache.miss_type_mach_latency_hist::samples         7401                      
+system.ruby.ST.L1Cache.miss_type_mach_latency_hist::mean  1078.644237                      
+system.ruby.ST.L1Cache.miss_type_mach_latency_hist::gmean   612.289487                      
+system.ruby.ST.L1Cache.miss_type_mach_latency_hist::stdev   896.971610                      
+system.ruby.ST.L1Cache.miss_type_mach_latency_hist |        2983     40.31%     40.31% |         988     13.35%     53.65% |         933     12.61%     66.26% |        1169     15.80%     82.06% |         871     11.77%     93.83% |         349      4.72%     98.54% |          91      1.23%     99.77% |          14      0.19%     99.96% |           3      0.04%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.L1Cache.miss_type_mach_latency_hist::total         7401                      
+system.ruby.ST.L2Cache.hit_type_mach_latency_hist::bucket_size          256                      
+system.ruby.ST.L2Cache.hit_type_mach_latency_hist::max_bucket         2559                      
+system.ruby.ST.L2Cache.hit_type_mach_latency_hist::samples          209                      
+system.ruby.ST.L2Cache.hit_type_mach_latency_hist::mean   177.009569                      
+system.ruby.ST.L2Cache.hit_type_mach_latency_hist::gmean    85.210589                      
+system.ruby.ST.L2Cache.hit_type_mach_latency_hist::stdev   222.115203                      
+system.ruby.ST.L2Cache.hit_type_mach_latency_hist |         158     75.60%     75.60% |          40     19.14%     94.74% |           6      2.87%     97.61% |           3      1.44%     99.04% |           0      0.00%     99.04% |           1      0.48%     99.52% |           1      0.48%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.L2Cache.hit_type_mach_latency_hist::total          209                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size         1024                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket        10239                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist::samples       216844                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist::mean  1211.584083                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean   837.263042                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev   897.633219                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist |      110553     50.98%     50.98% |       57779     26.65%     77.63% |       43904     20.25%     97.87% |        4480      2.07%     99.94% |         127      0.06%    100.00% |           1      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.Directory.miss_type_mach_latency_hist::total       216844                      
+system.ruby.L1Cache_Controller.Load      |       50433     12.46%     12.46% |       50616     12.50%     24.96% |       50620     12.50%     37.46% |       50648     12.51%     49.97% |       50636     12.51%     62.48% |       50962     12.59%     75.07% |       50842     12.56%     87.63% |       50083     12.37%    100.00%
+system.ruby.L1Cache_Controller.Load::total       404840                      
+system.ruby.L1Cache_Controller.Store     |       28039     12.48%     12.48% |       28372     12.63%     25.11% |       28070     12.49%     37.60% |       28136     12.52%     50.13% |       28079     12.50%     62.62% |       27776     12.36%     74.99% |       27886     12.41%     87.40% |       28307     12.60%    100.00%
+system.ruby.L1Cache_Controller.Store::total       224665                      
+system.ruby.L1Cache_Controller.L2_Replacement |       78300     12.46%     12.46% |       78816     12.55%     25.01% |       78529     12.50%     37.51% |       78625     12.52%     50.03% |       78556     12.50%     62.53% |       78576     12.51%     75.04% |       78587     12.51%     87.55% |       78231     12.45%    100.00%
+system.ruby.L1Cache_Controller.L2_Replacement::total       628220                      
+system.ruby.L1Cache_Controller.L1_to_L2  |      858524     12.53%     12.53% |      857879     12.52%     25.05% |      856223     12.49%     37.54% |      857953     12.52%     50.06% |      859985     12.55%     62.61% |      855111     12.48%     75.09% |      853105     12.45%     87.53% |      854232     12.47%    100.00%
+system.ruby.L1Cache_Controller.L1_to_L2::total      6853012                      
+system.ruby.L1Cache_Controller.Trigger_L2_to_L1D |          85     13.34%     13.34% |          83     13.03%     26.37% |          81     12.72%     39.09% |          75     11.77%     50.86% |          80     12.56%     63.42% |          80     12.56%     75.98% |          73     11.46%     87.44% |          80     12.56%    100.00%
+system.ruby.L1Cache_Controller.Trigger_L2_to_L1D::total          637                      
+system.ruby.L1Cache_Controller.Complete_L2_to_L1 |          85     13.34%     13.34% |          83     13.03%     26.37% |          81     12.72%     39.09% |          75     11.77%     50.86% |          80     12.56%     63.42% |          80     12.56%     75.98% |          73     11.46%     87.44% |          80     12.56%    100.00%
+system.ruby.L1Cache_Controller.Complete_L2_to_L1::total          637                      
+system.ruby.L1Cache_Controller.Other_GETX |      196274     12.50%     12.50% |      195945     12.48%     24.99% |      196230     12.50%     37.49% |      196167     12.50%     49.98% |      196227     12.50%     62.48% |      196523     12.52%     75.00% |      196414     12.51%     87.51% |      196005     12.49%    100.00%
+system.ruby.L1Cache_Controller.Other_GETX::total      1569785                      
+system.ruby.L1Cache_Controller.Other_GETS |      353374     12.51%     12.51% |      353179     12.50%     25.01% |      353176     12.50%     37.51% |      353156     12.50%     50.00% |      353160     12.50%     62.50% |      352851     12.49%     74.99% |      352945     12.49%     87.48% |      353716     12.52%    100.00%
+system.ruby.L1Cache_Controller.Other_GETS::total      2825557                      
+system.ruby.L1Cache_Controller.Merged_GETS |          59     13.95%     13.95% |          53     12.53%     26.48% |          51     12.06%     38.53% |          54     12.77%     51.30% |          57     13.48%     64.78% |          45     10.64%     75.41% |          62     14.66%     90.07% |          42      9.93%    100.00%
+system.ruby.L1Cache_Controller.Merged_GETS::total          423                      
+system.ruby.L1Cache_Controller.Ack       |      545290     12.46%     12.46% |      548865     12.55%     25.01% |      546914     12.50%     37.51% |      547510     12.52%     50.03% |      546983     12.50%     62.53% |      547231     12.51%     75.04% |      547243     12.51%     87.55% |      544739     12.45%    100.00%
+system.ruby.L1Cache_Controller.Ack::total      4374775                      
+system.ruby.L1Cache_Controller.Shared_Ack |          46     11.17%     11.17% |          52     12.62%     23.79% |          60     14.56%     38.35% |          48     11.65%     50.00% |          38      9.22%     59.22% |          59     14.32%     73.54% |          49     11.89%     85.44% |          60     14.56%    100.00%
+system.ruby.L1Cache_Controller.Shared_Ack::total          412                      
+system.ruby.L1Cache_Controller.Data      |        2902     12.29%     12.29% |        2956     12.52%     24.81% |        2952     12.50%     37.31% |        2956     12.52%     49.83% |        3021     12.80%     62.63% |        2932     12.42%     75.05% |        2963     12.55%     87.60% |        2928     12.40%    100.00%
+system.ruby.L1Cache_Controller.Data::total        23610                      
+system.ruby.L1Cache_Controller.Shared_Data |        1044     12.06%     12.06% |        1090     12.59%     24.65% |        1109     12.81%     37.47% |        1077     12.44%     49.91% |        1114     12.87%     62.78% |        1071     12.37%     75.15% |        1132     13.08%     88.23% |        1019     11.77%    100.00%
+system.ruby.L1Cache_Controller.Shared_Data::total         8656                      
+system.ruby.L1Cache_Controller.Exclusive_Data |       74363     12.48%     12.48% |       74779     12.55%     25.02% |       74481     12.50%     37.52% |       74602     12.52%     50.04% |       74430     12.49%     62.52% |       74583     12.51%     75.04% |       74502     12.50%     87.54% |       74292     12.46%    100.00%
+system.ruby.L1Cache_Controller.Exclusive_Data::total       596032                      
+system.ruby.L1Cache_Controller.Writeback_Ack |       73965     12.47%     12.47% |       74350     12.54%     25.01% |       74128     12.50%     37.52% |       74201     12.51%     50.03% |       74027     12.49%     62.52% |       74179     12.51%     75.03% |       74144     12.50%     87.53% |       73931     12.47%    100.00%
+system.ruby.L1Cache_Controller.Writeback_Ack::total       592925                      
+system.ruby.L1Cache_Controller.All_acks  |        1085     12.05%     12.05% |        1134     12.59%     24.64% |        1163     12.91%     37.55% |        1122     12.46%     50.01% |        1145     12.71%     62.72% |        1121     12.45%     75.16% |        1174     13.03%     88.20% |        1063     11.80%    100.00%
+system.ruby.L1Cache_Controller.All_acks::total         9007                      
+system.ruby.L1Cache_Controller.All_acks_no_sharers |       77227     12.47%     12.47% |       77692     12.55%     25.02% |       77379     12.49%     37.51% |       77514     12.52%     50.03% |       77420     12.50%     62.53% |       77465     12.51%     75.04% |       77423     12.50%     87.54% |       77176     12.46%    100.00%
+system.ruby.L1Cache_Controller.All_acks_no_sharers::total       619296                      
+system.ruby.L1Cache_Controller.I.Load    |       50333     12.46%     12.46% |       50517     12.50%     24.96% |       50518     12.50%     37.46% |       50550     12.51%     49.97% |       50540     12.51%     62.48% |       50855     12.59%     75.07% |       50759     12.56%     87.63% |       49992     12.37%    100.00%
+system.ruby.L1Cache_Controller.I.Load::total       404064                      
+system.ruby.L1Cache_Controller.I.Store   |       27977     12.48%     12.48% |       28308     12.62%     25.10% |       28022     12.50%     37.60% |       28085     12.52%     50.12% |       28026     12.50%     62.62% |       27731     12.37%     74.99% |       27838     12.41%     87.40% |       28249     12.60%    100.00%
+system.ruby.L1Cache_Controller.I.Store::total       224236                      
+system.ruby.L1Cache_Controller.I.L2_Replacement |        1529     12.80%     12.80% |        1508     12.62%     25.42% |        1449     12.13%     37.55% |        1525     12.77%     50.32% |        1515     12.68%     63.00% |        1499     12.55%     75.55% |        1468     12.29%     87.84% |        1453     12.16%    100.00%
+system.ruby.L1Cache_Controller.I.L2_Replacement::total        11946                      
+system.ruby.L1Cache_Controller.I.L1_to_L2 |         278     12.20%     12.20% |         287     12.59%     24.79% |         266     11.67%     36.46% |         294     12.90%     49.36% |         308     13.51%     62.88% |         269     11.80%     74.68% |         277     12.15%     86.84% |         300     13.16%    100.00%
+system.ruby.L1Cache_Controller.I.L1_to_L2::total         2279                      
+system.ruby.L1Cache_Controller.I.Trigger_L2_to_L1D |           2     13.33%     13.33% |           1      6.67%     20.00% |           3     20.00%     40.00% |           2     13.33%     53.33% |           2     13.33%     66.67% |           3     20.00%     86.67% |           0      0.00%     86.67% |           2     13.33%    100.00%
 system.ruby.L1Cache_Controller.I.Trigger_L2_to_L1D::total           15                      
-system.ruby.L1Cache_Controller.I.Other_GETX |      188850     12.52%     12.52% |      188385     12.49%     25.02% |      188473     12.50%     37.52% |      188307     12.49%     50.00% |      188572     12.51%     62.51% |      188504     12.50%     75.01% |      188287     12.49%     87.50% |      188527     12.50%    100.00%
-system.ruby.L1Cache_Controller.I.Other_GETX::total      1507905                      
-system.ruby.L1Cache_Controller.I.Other_GETS |      348728     12.50%     12.50% |      348598     12.49%     24.99% |      348711     12.50%     37.49% |      348779     12.50%     49.99% |      348712     12.50%     62.49% |      348887     12.50%     75.00% |      348575     12.49%     87.49% |      348998     12.51%    100.00%
-system.ruby.L1Cache_Controller.I.Other_GETS::total      2789988                      
-system.ruby.L1Cache_Controller.S.Load    |           1     16.67%     16.67% |           1     16.67%     33.33% |           2     33.33%     66.67% |           0      0.00%     66.67% |           0      0.00%     66.67% |           0      0.00%     66.67% |           1     16.67%     83.33% |           1     16.67%    100.00%
-system.ruby.L1Cache_Controller.S.Load::total            6                      
-system.ruby.L1Cache_Controller.S.L2_Replacement |        2919     12.33%     12.33% |        2953     12.47%     24.80% |        2937     12.41%     37.21% |        2944     12.44%     49.65% |        2906     12.28%     61.92% |        2973     12.56%     74.48% |        2984     12.60%     87.08% |        3058     12.92%    100.00%
-system.ruby.L1Cache_Controller.S.L2_Replacement::total        23674                      
-system.ruby.L1Cache_Controller.S.L1_to_L2 |        2947     12.34%     12.34% |        2984     12.49%     24.83% |        2973     12.45%     37.27% |        2971     12.44%     49.71% |        2929     12.26%     61.97% |        2993     12.53%     74.50% |        3006     12.58%     87.08% |        3086     12.92%    100.00%
-system.ruby.L1Cache_Controller.S.L1_to_L2::total        23889                      
-system.ruby.L1Cache_Controller.S.Trigger_L2_to_L1D |           2      8.70%      8.70% |           5     21.74%     30.43% |           4     17.39%     47.83% |           1      4.35%     52.17% |           0      0.00%     52.17% |           2      8.70%     60.87% |           3     13.04%     73.91% |           6     26.09%    100.00%
-system.ruby.L1Cache_Controller.S.Trigger_L2_to_L1D::total           23                      
-system.ruby.L1Cache_Controller.S.Other_GETX |          29     11.74%     11.74% |          31     12.55%     24.29% |          38     15.38%     39.68% |          33     13.36%     53.04% |          32     12.96%     65.99% |          28     11.34%     77.33% |          25     10.12%     87.45% |          31     12.55%    100.00%
-system.ruby.L1Cache_Controller.S.Other_GETX::total          247                      
-system.ruby.L1Cache_Controller.S.Other_GETS |          57     11.73%     11.73% |          56     11.52%     23.25% |          59     12.14%     35.39% |          72     14.81%     50.21% |          52     10.70%     60.91% |          62     12.76%     73.66% |          79     16.26%     89.92% |          49     10.08%    100.00%
-system.ruby.L1Cache_Controller.S.Other_GETS::total          486                      
-system.ruby.L1Cache_Controller.O.Store   |           1    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.L1Cache_Controller.O.Store::total            1                      
-system.ruby.L1Cache_Controller.O.L2_Replacement |        1037     12.92%     12.92% |        1033     12.87%     25.79% |         990     12.33%     38.12% |         999     12.45%     50.57% |         972     12.11%     62.68% |        1001     12.47%     75.15% |        1015     12.64%     87.79% |         980     12.21%    100.00%
-system.ruby.L1Cache_Controller.O.L2_Replacement::total         8027                      
-system.ruby.L1Cache_Controller.O.L1_to_L2 |         204     12.62%     12.62% |         188     11.63%     24.26% |         202     12.50%     36.76% |         199     12.31%     49.07% |         190     11.76%     60.83% |         218     13.49%     74.32% |         217     13.43%     87.75% |         198     12.25%    100.00%
-system.ruby.L1Cache_Controller.O.L1_to_L2::total         1616                      
-system.ruby.L1Cache_Controller.O.Trigger_L2_to_L1D |           0      0.00%      0.00% |           2     33.33%     33.33% |           0      0.00%     33.33% |           1     16.67%     50.00% |           0      0.00%     50.00% |           1     16.67%     66.67% |           0      0.00%     66.67% |           2     33.33%    100.00%
-system.ruby.L1Cache_Controller.O.Trigger_L2_to_L1D::total            6                      
-system.ruby.L1Cache_Controller.O.Other_GETX |           7     12.50%     12.50% |           8     14.29%     26.79% |           8     14.29%     41.07% |           5      8.93%     50.00% |           3      5.36%     55.36% |          11     19.64%     75.00% |           9     16.07%     91.07% |           5      8.93%    100.00%
-system.ruby.L1Cache_Controller.O.Other_GETX::total           56                      
-system.ruby.L1Cache_Controller.O.Other_GETS |           9      9.89%      9.89% |          14     15.38%     25.27% |          12     13.19%     38.46% |          12     13.19%     51.65% |          13     14.29%     65.93% |           9      9.89%     75.82% |           9      9.89%     85.71% |          13     14.29%    100.00%
-system.ruby.L1Cache_Controller.O.Other_GETS::total           91                      
-system.ruby.L1Cache_Controller.O.Merged_GETS |           4     19.05%     19.05% |           3     14.29%     33.33% |           2      9.52%     42.86% |           6     28.57%     71.43% |           3     14.29%     85.71% |           1      4.76%     90.48% |           1      4.76%     95.24% |           1      4.76%    100.00%
-system.ruby.L1Cache_Controller.O.Merged_GETS::total           21                      
-system.ruby.L1Cache_Controller.M.Load    |           7     16.67%     16.67% |           3      7.14%     23.81% |           5     11.90%     35.71% |           6     14.29%     50.00% |           2      4.76%     54.76% |          11     26.19%     80.95% |           6     14.29%     95.24% |           2      4.76%    100.00%
-system.ruby.L1Cache_Controller.M.Load::total           42                      
-system.ruby.L1Cache_Controller.M.Store   |           5     16.13%     16.13% |           5     16.13%     32.26% |           2      6.45%     38.71% |           5     16.13%     54.84% |           2      6.45%     61.29% |           9     29.03%     90.32% |           1      3.23%     93.55% |           2      6.45%    100.00%
-system.ruby.L1Cache_Controller.M.Store::total           31                      
-system.ruby.L1Cache_Controller.M.L2_Replacement |       45647     12.52%     12.52% |       45669     12.52%     25.04% |       45641     12.52%     37.56% |       45593     12.50%     50.06% |       45746     12.55%     62.61% |       45407     12.45%     75.06% |       45688     12.53%     87.59% |       45251     12.41%    100.00%
-system.ruby.L1Cache_Controller.M.L2_Replacement::total       364642                      
-system.ruby.L1Cache_Controller.M.L1_to_L2 |       46941     12.52%     12.52% |       46960     12.53%     25.05% |       46927     12.52%     37.57% |       46865     12.50%     50.08% |       46980     12.53%     62.61% |       46700     12.46%     75.07% |       46933     12.52%     87.59% |       46507     12.41%    100.00%
-system.ruby.L1Cache_Controller.M.L1_to_L2::total       374813                      
-system.ruby.L1Cache_Controller.M.Trigger_L2_to_L1D |          49     13.14%     13.14% |          40     10.72%     23.86% |          60     16.09%     39.95% |          51     13.67%     53.62% |          41     10.99%     64.61% |          55     14.75%     79.36% |          37      9.92%     89.28% |          40     10.72%    100.00%
-system.ruby.L1Cache_Controller.M.Trigger_L2_to_L1D::total          373                      
-system.ruby.L1Cache_Controller.M.Other_GETX |         529     12.54%     12.54% |         518     12.28%     24.82% |         538     12.75%     37.57% |         533     12.63%     50.20% |         520     12.33%     62.53% |         540     12.80%     75.33% |         502     11.90%     87.22% |         539     12.78%    100.00%
-system.ruby.L1Cache_Controller.M.Other_GETX::total         4219                      
-system.ruby.L1Cache_Controller.M.Other_GETS |         983     12.81%     12.81% |         999     13.02%     25.84% |         944     12.31%     38.14% |         950     12.38%     50.53% |         931     12.14%     62.66% |         962     12.54%     75.21% |         974     12.70%     87.90% |         928     12.10%    100.00%
-system.ruby.L1Cache_Controller.M.Other_GETS::total         7671                      
-system.ruby.L1Cache_Controller.M.Merged_GETS |          39     15.29%     15.29% |          27     10.59%     25.88% |          33     12.94%     38.82% |          31     12.16%     50.98% |          27     10.59%     61.57% |          27     10.59%     72.16% |          29     11.37%     83.53% |          42     16.47%    100.00%
-system.ruby.L1Cache_Controller.M.Merged_GETS::total          255                      
-system.ruby.L1Cache_Controller.MM.Load   |           4     10.00%     10.00% |           8     20.00%     30.00% |           2      5.00%     35.00% |           6     15.00%     50.00% |           6     15.00%     65.00% |           4     10.00%     75.00% |           3      7.50%     82.50% |           7     17.50%    100.00%
-system.ruby.L1Cache_Controller.MM.Load::total           40                      
-system.ruby.L1Cache_Controller.MM.Store  |           0      0.00%      0.00% |           5     26.32%     26.32% |           1      5.26%     31.58% |           2     10.53%     42.11% |           4     21.05%     63.16% |           4     21.05%     84.21% |           1      5.26%     89.47% |           2     10.53%    100.00%
+system.ruby.L1Cache_Controller.I.Other_GETX |      195293     12.50%     12.50% |      194946     12.48%     24.98% |      195299     12.50%     37.49% |      195174     12.50%     49.98% |      195217     12.50%     62.48% |      195495     12.52%     75.00% |      195467     12.51%     87.51% |      195040     12.49%    100.00%
+system.ruby.L1Cache_Controller.I.Other_GETX::total      1561931                      
+system.ruby.L1Cache_Controller.I.Other_GETS |      351649     12.51%     12.51% |      351467     12.50%     25.00% |      351522     12.50%     37.51% |      351428     12.50%     50.00% |      351472     12.50%     62.50% |      351196     12.49%     74.99% |      351192     12.49%     87.48% |      352050     12.52%    100.00%
+system.ruby.L1Cache_Controller.I.Other_GETS::total      2811976                      
+system.ruby.L1Cache_Controller.S.Load    |           1     20.00%     20.00% |           0      0.00%     20.00% |           0      0.00%     20.00% |           0      0.00%     20.00% |           3     60.00%     80.00% |           1     20.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache_Controller.S.Load::total            5                      
+system.ruby.L1Cache_Controller.S.Store   |           0      0.00%      0.00% |           0      0.00%      0.00% |           1     50.00%     50.00% |           1     50.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache_Controller.S.Store::total            2                      
+system.ruby.L1Cache_Controller.S.L2_Replacement |        2806     12.02%     12.02% |        2958     12.67%     24.69% |        2952     12.64%     37.33% |        2899     12.42%     49.75% |        3014     12.91%     62.65% |        2898     12.41%     75.07% |        2975     12.74%     87.81% |        2847     12.19%    100.00%
+system.ruby.L1Cache_Controller.S.L2_Replacement::total        23349                      
+system.ruby.L1Cache_Controller.S.L1_to_L2 |        2835     12.03%     12.03% |        2983     12.66%     24.69% |        2980     12.65%     37.34% |        2927     12.42%     49.76% |        3041     12.91%     62.66% |        2923     12.40%     75.07% |        2999     12.73%     87.79% |        2876     12.21%    100.00%
+system.ruby.L1Cache_Controller.S.L1_to_L2::total        23564                      
+system.ruby.L1Cache_Controller.S.Trigger_L2_to_L1D |           0      0.00%      0.00% |           3     14.29%     14.29% |           4     19.05%     33.33% |           3     14.29%     47.62% |           3     14.29%     61.90% |           3     14.29%     76.19% |           3     14.29%     90.48% |           2      9.52%    100.00%
+system.ruby.L1Cache_Controller.S.Trigger_L2_to_L1D::total           21                      
+system.ruby.L1Cache_Controller.S.Other_GETX |          33     13.64%     13.64% |          30     12.40%     26.03% |          29     11.98%     38.02% |          31     12.81%     50.83% |          35     14.46%     65.29% |          27     11.16%     76.45% |          26     10.74%     87.19% |          31     12.81%    100.00%
+system.ruby.L1Cache_Controller.S.Other_GETX::total          242                      
+system.ruby.L1Cache_Controller.S.Other_GETS |          57     13.83%     13.83% |          65     15.78%     29.61% |          41      9.95%     39.56% |          38      9.22%     48.79% |          58     14.08%     62.86% |          52     12.62%     75.49% |          53     12.86%     88.35% |          48     11.65%    100.00%
+system.ruby.L1Cache_Controller.S.Other_GETS::total          412                      
+system.ruby.L1Cache_Controller.O.Load    |           0      0.00%      0.00% |           0      0.00%      0.00% |           1    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache_Controller.O.Load::total            1                      
+system.ruby.L1Cache_Controller.O.L2_Replacement |        1012     12.53%     12.53% |        1001     12.40%     24.93% |         990     12.26%     37.19% |        1022     12.66%     49.85% |         997     12.35%     62.20% |         995     12.32%     74.52% |        1049     12.99%     87.52% |        1008     12.48%    100.00%
+system.ruby.L1Cache_Controller.O.L2_Replacement::total         8074                      
+system.ruby.L1Cache_Controller.O.L1_to_L2 |         169     10.51%     10.51% |         186     11.57%     22.08% |         201     12.50%     34.58% |         205     12.75%     47.33% |         202     12.56%     59.89% |         213     13.25%     73.13% |         222     13.81%     86.94% |         210     13.06%    100.00%
+system.ruby.L1Cache_Controller.O.L1_to_L2::total         1608                      
+system.ruby.L1Cache_Controller.O.Trigger_L2_to_L1D |           3     42.86%     42.86% |           2     28.57%     71.43% |           0      0.00%     71.43% |           1     14.29%     85.71% |           0      0.00%     85.71% |           1     14.29%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache_Controller.O.Trigger_L2_to_L1D::total            7                      
+system.ruby.L1Cache_Controller.O.Other_GETX |          10     16.67%     16.67% |           9     15.00%     31.67% |           8     13.33%     45.00% |           8     13.33%     58.33% |           6     10.00%     68.33% |           5      8.33%     76.67% |           7     11.67%     88.33% |           7     11.67%    100.00%
+system.ruby.L1Cache_Controller.O.Other_GETX::total           60                      
+system.ruby.L1Cache_Controller.O.Other_GETS |          11     13.10%     13.10% |          13     15.48%     28.57% |          15     17.86%     46.43% |          12     14.29%     60.71% |           7      8.33%     69.05% |           8      9.52%     78.57% |           8      9.52%     88.10% |          10     11.90%    100.00%
+system.ruby.L1Cache_Controller.O.Other_GETS::total           84                      
+system.ruby.L1Cache_Controller.O.Merged_GETS |           1      4.55%      4.55% |           3     13.64%     18.18% |           2      9.09%     27.27% |           4     18.18%     45.45% |           5     22.73%     68.18% |           3     13.64%     81.82% |           2      9.09%     90.91% |           2      9.09%    100.00%
+system.ruby.L1Cache_Controller.O.Merged_GETS::total           22                      
+system.ruby.L1Cache_Controller.M.Load    |           2      3.57%      3.57% |           8     14.29%     17.86% |           4      7.14%     25.00% |           6     10.71%     35.71% |          10     17.86%     53.57% |           8     14.29%     67.86% |           7     12.50%     80.36% |          11     19.64%    100.00%
+system.ruby.L1Cache_Controller.M.Load::total           56                      
+system.ruby.L1Cache_Controller.M.Store   |           3      8.82%      8.82% |           3      8.82%     17.65% |           6     17.65%     35.29% |           5     14.71%     50.00% |           1      2.94%     52.94% |           3      8.82%     61.76% |           5     14.71%     76.47% |           8     23.53%    100.00%
+system.ruby.L1Cache_Controller.M.Store::total           34                      
+system.ruby.L1Cache_Controller.M.L2_Replacement |       45887     12.48%     12.48% |       45937     12.49%     24.97% |       46011     12.51%     37.47% |       46008     12.51%     49.98% |       45925     12.49%     62.47% |       46336     12.60%     75.07% |       46151     12.55%     87.61% |       45554     12.39%    100.00%
+system.ruby.L1Cache_Controller.M.L2_Replacement::total       367809                      
+system.ruby.L1Cache_Controller.M.L1_to_L2 |       47252     12.49%     12.49% |       47281     12.50%     24.99% |       47263     12.49%     37.48% |       47324     12.51%     49.99% |       47202     12.48%     62.47% |       47652     12.60%     75.07% |       47474     12.55%     87.62% |       46832     12.38%    100.00%
+system.ruby.L1Cache_Controller.M.L1_to_L2::total       378280                      
+system.ruby.L1Cache_Controller.M.Trigger_L2_to_L1D |          52     13.27%     13.27% |          52     13.27%     26.53% |          42     10.71%     37.24% |          45     11.48%     48.72% |          46     11.73%     60.46% |          50     12.76%     73.21% |          49     12.50%     85.71% |          56     14.29%    100.00%
+system.ruby.L1Cache_Controller.M.Trigger_L2_to_L1D::total          392                      
+system.ruby.L1Cache_Controller.M.Other_GETX |         573     12.90%     12.90% |         565     12.72%     25.61% |         521     11.73%     37.34% |         575     12.94%     50.28% |         559     12.58%     62.86% |         587     13.21%     76.07% |         542     12.20%     88.27% |         521     11.73%    100.00%
+system.ruby.L1Cache_Controller.M.Other_GETX::total         4443                      
+system.ruby.L1Cache_Controller.M.Other_GETS |         968     12.50%     12.50% |         962     12.42%     24.92% |         950     12.26%     37.18% |         983     12.69%     49.87% |         952     12.29%     62.16% |         958     12.37%     74.53% |         998     12.88%     87.41% |         975     12.59%    100.00%
+system.ruby.L1Cache_Controller.M.Other_GETS::total         7746                      
+system.ruby.L1Cache_Controller.M.Merged_GETS |          34     13.65%     13.65% |          36     14.46%     28.11% |          26     10.44%     38.55% |          27     10.84%     49.40% |          30     12.05%     61.45% |          31     12.45%     73.90% |          37     14.86%     88.76% |          28     11.24%    100.00%
+system.ruby.L1Cache_Controller.M.Merged_GETS::total          249                      
+system.ruby.L1Cache_Controller.MM.Load   |           9     33.33%     33.33% |           2      7.41%     40.74% |           3     11.11%     51.85% |           5     18.52%     70.37% |           2      7.41%     77.78% |           1      3.70%     81.48% |           1      3.70%     85.19% |           4     14.81%    100.00%
+system.ruby.L1Cache_Controller.MM.Load::total           27                      
+system.ruby.L1Cache_Controller.MM.Store  |           2     10.53%     10.53% |           2     10.53%     21.05% |           1      5.26%     26.32% |           1      5.26%     31.58% |           3     15.79%     47.37% |           6     31.58%     78.95% |           3     15.79%     94.74% |           1      5.26%    100.00%
 system.ruby.L1Cache_Controller.MM.Store::total           19                      
-system.ruby.L1Cache_Controller.MM.L2_Replacement |       25935     12.37%     12.37% |       26320     12.56%     24.93% |       26190     12.49%     37.42% |       26373     12.58%     50.00% |       26074     12.44%     62.44% |       26156     12.48%     74.92% |       26468     12.63%     87.54% |       26109     12.46%    100.00%
-system.ruby.L1Cache_Controller.MM.L2_Replacement::total       209625                      
-system.ruby.L1Cache_Controller.MM.L1_to_L2 |       26603     12.35%     12.35% |       27029     12.54%     24.89% |       26955     12.51%     37.40% |       27088     12.57%     49.98% |       26817     12.45%     62.42% |       26905     12.49%     74.91% |       27186     12.62%     87.53% |       26874     12.47%    100.00%
-system.ruby.L1Cache_Controller.MM.L1_to_L2::total       215457                      
-system.ruby.L1Cache_Controller.MM.Trigger_L2_to_L1D |          21     10.29%     10.29% |          25     12.25%     22.55% |          34     16.67%     39.22% |          24     11.76%     50.98% |          25     12.25%     63.24% |          27     13.24%     76.47% |          27     13.24%     89.71% |          21     10.29%    100.00%
-system.ruby.L1Cache_Controller.MM.Trigger_L2_to_L1D::total          204                      
-system.ruby.L1Cache_Controller.MM.Other_GETX |         296     12.11%     12.11% |         298     12.19%     24.30% |         301     12.32%     36.62% |         320     13.09%     49.71% |         334     13.67%     63.38% |         308     12.60%     75.98% |         279     11.42%     87.40% |         308     12.60%    100.00%
-system.ruby.L1Cache_Controller.MM.Other_GETX::total         2444                      
-system.ruby.L1Cache_Controller.MM.Other_GETS |         481     10.98%     10.98% |         549     12.54%     23.52% |         562     12.83%     36.36% |         521     11.90%     48.25% |         548     12.51%     60.77% |         558     12.74%     73.51% |         561     12.81%     86.32% |         599     13.68%    100.00%
-system.ruby.L1Cache_Controller.MM.Other_GETS::total         4379                      
-system.ruby.L1Cache_Controller.MM.Merged_GETS |          23     14.37%     14.37% |          16     10.00%     24.38% |          21     13.12%     37.50% |          23     14.37%     51.88% |          18     11.25%     63.13% |          23     14.37%     77.50% |          21     13.12%     90.63% |          15      9.38%    100.00%
-system.ruby.L1Cache_Controller.MM.Merged_GETS::total          160                      
-system.ruby.L1Cache_Controller.IR.Load   |           1     16.67%     16.67% |           0      0.00%     16.67% |           1     16.67%     33.33% |           0      0.00%     33.33% |           0      0.00%     33.33% |           1     16.67%     50.00% |           1     16.67%     66.67% |           2     33.33%    100.00%
-system.ruby.L1Cache_Controller.IR.Load::total            6                      
-system.ruby.L1Cache_Controller.IR.Store  |           2     22.22%     22.22% |           0      0.00%     22.22% |           0      0.00%     22.22% |           2     22.22%     44.44% |           0      0.00%     44.44% |           3     33.33%     77.78% |           1     11.11%     88.89% |           1     11.11%    100.00%
-system.ruby.L1Cache_Controller.IR.Store::total            9                      
-system.ruby.L1Cache_Controller.IR.L1_to_L2 |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |          11     84.62%     84.62% |           0      0.00%     84.62% |           2     15.38%    100.00%
-system.ruby.L1Cache_Controller.IR.L1_to_L2::total           13                      
-system.ruby.L1Cache_Controller.SR.Load   |           2     11.76%     11.76% |           3     17.65%     29.41% |           4     23.53%     52.94% |           1      5.88%     58.82% |           0      0.00%     58.82% |           1      5.88%     64.71% |           2     11.76%     76.47% |           4     23.53%    100.00%
-system.ruby.L1Cache_Controller.SR.Load::total           17                      
-system.ruby.L1Cache_Controller.SR.Store  |           0      0.00%      0.00% |           2     33.33%     33.33% |           0      0.00%     33.33% |           0      0.00%     33.33% |           0      0.00%     33.33% |           1     16.67%     50.00% |           1     16.67%     66.67% |           2     33.33%    100.00%
-system.ruby.L1Cache_Controller.SR.Store::total            6                      
-system.ruby.L1Cache_Controller.SR.L1_to_L2 |           0      0.00%      0.00% |           3     18.75%     18.75% |           0      0.00%     18.75% |           0      0.00%     18.75% |           0      0.00%     18.75% |           0      0.00%     18.75% |           0      0.00%     18.75% |          13     81.25%    100.00%
-system.ruby.L1Cache_Controller.SR.L1_to_L2::total           16                      
-system.ruby.L1Cache_Controller.OR.Load   |           0      0.00%      0.00% |           1     20.00%     20.00% |           0      0.00%     20.00% |           1     20.00%     40.00% |           0      0.00%     40.00% |           1     20.00%     60.00% |           0      0.00%     60.00% |           2     40.00%    100.00%
-system.ruby.L1Cache_Controller.OR.Load::total            5                      
-system.ruby.L1Cache_Controller.OR.Store  |           0      0.00%      0.00% |           1    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.L1Cache_Controller.OR.Store::total            1                      
-system.ruby.L1Cache_Controller.MR.Load   |          32     12.85%     12.85% |          27     10.84%     23.69% |          42     16.87%     40.56% |          33     13.25%     53.82% |          20      8.03%     61.85% |          37     14.86%     76.71% |          27     10.84%     87.55% |          31     12.45%    100.00%
-system.ruby.L1Cache_Controller.MR.Load::total          249                      
-system.ruby.L1Cache_Controller.MR.Store  |          17     13.71%     13.71% |          13     10.48%     24.19% |          18     14.52%     38.71% |          18     14.52%     53.23% |          21     16.94%     70.16% |          18     14.52%     84.68% |          10      8.06%     92.74% |           9      7.26%    100.00%
-system.ruby.L1Cache_Controller.MR.Store::total          124                      
-system.ruby.L1Cache_Controller.MR.L1_to_L2 |          91     14.35%     14.35% |          56      8.83%     23.19% |         102     16.09%     39.27% |          86     13.56%     52.84% |          95     14.98%     67.82% |          89     14.04%     81.86% |          59      9.31%     91.17% |          56      8.83%    100.00%
-system.ruby.L1Cache_Controller.MR.L1_to_L2::total          634                      
-system.ruby.L1Cache_Controller.MMR.Load  |          14     10.22%     10.22% |          17     12.41%     22.63% |          26     18.98%     41.61% |          16     11.68%     53.28% |          16     11.68%     64.96% |          16     11.68%     76.64% |          18     13.14%     89.78% |          14     10.22%    100.00%
-system.ruby.L1Cache_Controller.MMR.Load::total          137                      
-system.ruby.L1Cache_Controller.MMR.Store |           7     10.45%     10.45% |           8     11.94%     22.39% |           8     11.94%     34.33% |           8     11.94%     46.27% |           9     13.43%     59.70% |          11     16.42%     76.12% |           9     13.43%     89.55% |           7     10.45%    100.00%
-system.ruby.L1Cache_Controller.MMR.Store::total           67                      
-system.ruby.L1Cache_Controller.MMR.L1_to_L2 |          59     15.28%     15.28% |          75     19.43%     34.72% |          46     11.92%     46.63% |          41     10.62%     57.25% |          49     12.69%     69.95% |          33      8.55%     78.50% |          49     12.69%     91.19% |          34      8.81%    100.00%
-system.ruby.L1Cache_Controller.MMR.L1_to_L2::total          386                      
-system.ruby.L1Cache_Controller.IM.L1_to_L2 |      264282     12.35%     12.35% |      266577     12.46%     24.81% |      267890     12.52%     37.33% |      269848     12.61%     49.94% |      268056     12.53%     62.46% |      268579     12.55%     75.02% |      269306     12.59%     87.60% |      265306     12.40%    100.00%
-system.ruby.L1Cache_Controller.IM.L1_to_L2::total      2139844                      
-system.ruby.L1Cache_Controller.IM.Other_GETX |           7      7.69%      7.69% |          12     13.19%     20.88% |          10     10.99%     31.87% |          15     16.48%     48.35% |           9      9.89%     58.24% |          15     16.48%     74.73% |          10     10.99%     85.71% |          13     14.29%    100.00%
-system.ruby.L1Cache_Controller.IM.Other_GETX::total           91                      
-system.ruby.L1Cache_Controller.IM.Other_GETS |          21     14.00%     14.00% |          19     12.67%     26.67% |          20     13.33%     40.00% |          24     16.00%     56.00% |          14      9.33%     65.33% |          14      9.33%     74.67% |          22     14.67%     89.33% |          16     10.67%    100.00%
-system.ruby.L1Cache_Controller.IM.Other_GETS::total          150                      
-system.ruby.L1Cache_Controller.IM.Ack    |      183448     12.33%     12.33% |      186647     12.55%     24.88% |      185973     12.50%     37.38% |      187270     12.59%     49.97% |      185299     12.46%     62.42% |      185768     12.49%     74.91% |      187652     12.61%     87.52% |      185613     12.48%    100.00%
-system.ruby.L1Cache_Controller.IM.Ack::total      1487670                      
-system.ruby.L1Cache_Controller.IM.Data   |         985     11.47%     11.47% |        1103     12.85%     24.32% |        1041     12.12%     36.44% |        1101     12.82%     49.27% |        1105     12.87%     62.14% |        1091     12.71%     74.84% |        1048     12.21%     87.05% |        1112     12.95%    100.00%
-system.ruby.L1Cache_Controller.IM.Data::total         8586                      
-system.ruby.L1Cache_Controller.IM.Exclusive_Data |       25729     12.38%     12.38% |       26061     12.54%     24.91% |       26018     12.52%     37.43% |       26114     12.56%     49.99% |       25848     12.43%     62.43% |       25928     12.47%     74.90% |       26272     12.64%     87.54% |       25907     12.46%    100.00%
-system.ruby.L1Cache_Controller.IM.Exclusive_Data::total       207877                      
-system.ruby.L1Cache_Controller.SM.L1_to_L2 |           0      0.00%      0.00% |          11     57.89%     57.89% |           0      0.00%     57.89% |           0      0.00%     57.89% |           0      0.00%     57.89% |           1      5.26%     63.16% |           7     36.84%    100.00% |           0      0.00%    100.00%
-system.ruby.L1Cache_Controller.SM.L1_to_L2::total           19                      
-system.ruby.L1Cache_Controller.SM.Ack    |           0      0.00%      0.00% |          14     33.33%     33.33% |           0      0.00%     33.33% |           0      0.00%     33.33% |           0      0.00%     33.33% |           7     16.67%     50.00% |           7     16.67%     66.67% |          14     33.33%    100.00%
-system.ruby.L1Cache_Controller.SM.Ack::total           42                      
-system.ruby.L1Cache_Controller.SM.Data   |           0      0.00%      0.00% |           2     33.33%     33.33% |           0      0.00%     33.33% |           0      0.00%     33.33% |           0      0.00%     33.33% |           1     16.67%     50.00% |           1     16.67%     66.67% |           2     33.33%    100.00%
-system.ruby.L1Cache_Controller.SM.Data::total            6                      
-system.ruby.L1Cache_Controller.OM.Ack    |           7     50.00%     50.00% |           7     50.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.L1Cache_Controller.OM.Ack::total           14                      
-system.ruby.L1Cache_Controller.OM.All_acks_no_sharers |           1     50.00%     50.00% |           1     50.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.L1Cache_Controller.OM.All_acks_no_sharers::total            2                      
-system.ruby.L1Cache_Controller.ISM.L1_to_L2 |           2     11.11%     11.11% |           0      0.00%     11.11% |           0      0.00%     11.11% |           0      0.00%     11.11% |           1      5.56%     16.67% |           0      0.00%     16.67% |          14     77.78%     94.44% |           1      5.56%    100.00%
-system.ruby.L1Cache_Controller.ISM.L1_to_L2::total           18                      
-system.ruby.L1Cache_Controller.ISM.Ack   |         104     12.84%     12.84% |          73      9.01%     21.85% |         108     13.33%     35.19% |         117     14.44%     49.63% |         100     12.35%     61.98% |         106     13.09%     75.06% |         115     14.20%     89.26% |          87     10.74%    100.00%
-system.ruby.L1Cache_Controller.ISM.Ack::total          810                      
-system.ruby.L1Cache_Controller.ISM.All_acks_no_sharers |         985     11.46%     11.46% |        1105     12.86%     24.32% |        1041     12.12%     36.44% |        1101     12.81%     49.26% |        1105     12.86%     62.12% |        1092     12.71%     74.83% |        1049     12.21%     87.03% |        1114     12.97%    100.00%
-system.ruby.L1Cache_Controller.ISM.All_acks_no_sharers::total         8592                      
-system.ruby.L1Cache_Controller.M_W.L1_to_L2 |         539     13.66%     13.66% |         550     13.94%     27.60% |         404     10.24%     37.84% |         533     13.51%     51.34% |         478     12.11%     63.46% |         492     12.47%     75.92% |         525     13.30%     89.23% |         425     10.77%    100.00%
-system.ruby.L1Cache_Controller.M_W.L1_to_L2::total         3946                      
-system.ruby.L1Cache_Controller.M_W.Ack   |        1618     12.50%     12.50% |        1714     13.24%     25.73% |        1578     12.19%     37.92% |        1607     12.41%     50.33% |        1665     12.86%     63.19% |        1631     12.60%     75.78% |        1583     12.22%     88.01% |        1553     11.99%    100.00%
-system.ruby.L1Cache_Controller.M_W.Ack::total        12949                      
-system.ruby.L1Cache_Controller.M_W.All_acks_no_sharers |       47224     12.53%     12.53% |       47235     12.53%     25.06% |       47179     12.52%     37.57% |       47134     12.50%     50.08% |       47252     12.53%     62.61% |       46968     12.46%     75.07% |       47208     12.52%     87.59% |       46776     12.41%    100.00%
-system.ruby.L1Cache_Controller.M_W.All_acks_no_sharers::total       376976                      
-system.ruby.L1Cache_Controller.MM_W.L1_to_L2 |        1079     15.32%     15.32% |         875     12.43%     27.75% |         817     11.60%     39.36% |         808     11.48%     50.83% |         798     11.33%     62.16% |         840     11.93%     74.09% |         931     13.22%     87.32% |         893     12.68%    100.00%
-system.ruby.L1Cache_Controller.MM_W.L1_to_L2::total         7041                      
-system.ruby.L1Cache_Controller.MM_W.Ack  |        2578     12.99%     12.99% |        2557     12.89%     25.88% |        2465     12.42%     38.30% |        2275     11.47%     49.77% |        2427     12.23%     62.00% |        2427     12.23%     74.23% |        2583     13.02%     87.24% |        2531     12.76%    100.00%
-system.ruby.L1Cache_Controller.MM_W.Ack::total        19843                      
-system.ruby.L1Cache_Controller.MM_W.All_acks_no_sharers |       25729     12.38%     12.38% |       26061     12.54%     24.91% |       26018     12.52%     37.43% |       26114     12.56%     49.99% |       25848     12.43%     62.43% |       25928     12.47%     74.90% |       26272     12.64%     87.54% |       25907     12.46%    100.00%
-system.ruby.L1Cache_Controller.MM_W.All_acks_no_sharers::total       207877                      
-system.ruby.L1Cache_Controller.IS.L1_to_L2 |      495283     12.52%     12.52% |      496463     12.55%     25.07% |      495139     12.51%     37.58% |      490703     12.40%     49.98% |      494908     12.51%     62.49% |      493655     12.48%     74.97% |      495921     12.53%     87.50% |      494562     12.50%    100.00%
-system.ruby.L1Cache_Controller.IS.L1_to_L2::total      3956634                      
-system.ruby.L1Cache_Controller.IS.Other_GETX |          18     11.46%     11.46% |          25     15.92%     27.39% |          17     10.83%     38.22% |          24     15.29%     53.50% |          21     13.38%     66.88% |          22     14.01%     80.89% |          15      9.55%     90.45% |          15      9.55%    100.00%
-system.ruby.L1Cache_Controller.IS.Other_GETX::total          157                      
-system.ruby.L1Cache_Controller.IS.Other_GETS |          33     12.36%     12.36% |          30     11.24%     23.60% |          33     12.36%     35.96% |          29     10.86%     46.82% |          36     13.48%     60.30% |          40     14.98%     75.28% |          28     10.49%     85.77% |          38     14.23%    100.00%
-system.ruby.L1Cache_Controller.IS.Other_GETS::total          267                      
-system.ruby.L1Cache_Controller.IS.Ack    |      344673     12.52%     12.52% |      344866     12.53%     25.05% |      344538     12.51%     37.56% |      344199     12.50%     50.06% |      344619     12.52%     62.58% |      343059     12.46%     75.04% |      344891     12.53%     87.57% |      342300     12.43%    100.00%
-system.ruby.L1Cache_Controller.IS.Ack::total      2753145                      
-system.ruby.L1Cache_Controller.IS.Shared_Ack |          57     12.61%     12.61% |          54     11.95%     24.56% |          57     12.61%     37.17% |          59     13.05%     50.22% |          48     10.62%     60.84% |          68     15.04%     75.88% |          45      9.96%     85.84% |          64     14.16%    100.00%
-system.ruby.L1Cache_Controller.IS.Shared_Ack::total          452                      
-system.ruby.L1Cache_Controller.IS.Data   |        1888     12.28%     12.28% |        1940     12.62%     24.90% |        1919     12.48%     37.38% |        1926     12.53%     49.91% |        1893     12.31%     62.22% |        1908     12.41%     74.63% |        1932     12.57%     87.20% |        1968     12.80%    100.00%
-system.ruby.L1Cache_Controller.IS.Data::total        15374                      
-system.ruby.L1Cache_Controller.IS.Shared_Data |        1060     12.39%     12.39% |        1048     12.25%     24.63% |        1056     12.34%     36.98% |        1053     12.31%     49.28% |        1045     12.21%     61.49% |        1094     12.78%     74.28% |        1078     12.60%     86.88% |        1123     13.12%    100.00%
-system.ruby.L1Cache_Controller.IS.Shared_Data::total         8557                      
-system.ruby.L1Cache_Controller.IS.Exclusive_Data |       47224     12.53%     12.53% |       47235     12.53%     25.06% |       47180     12.52%     37.57% |       47134     12.50%     50.08% |       47252     12.53%     62.61% |       46968     12.46%     75.07% |       47208     12.52%     87.59% |       46776     12.41%    100.00%
-system.ruby.L1Cache_Controller.IS.Exclusive_Data::total       376977                      
-system.ruby.L1Cache_Controller.SS.L1_to_L2 |        1116     14.02%     14.02% |         874     10.98%     25.01% |        1194     15.00%     40.01% |        1064     13.37%     53.38% |         767      9.64%     63.02% |         881     11.07%     74.09% |         901     11.32%     85.41% |        1161     14.59%    100.00%
-system.ruby.L1Cache_Controller.SS.L1_to_L2::total         7958                      
-system.ruby.L1Cache_Controller.SS.Ack    |        2952     12.15%     12.15% |        3061     12.60%     24.75% |        3007     12.38%     37.13% |        2990     12.31%     49.44% |        3014     12.41%     61.84% |        2995     12.33%     74.17% |        3121     12.85%     87.02% |        3154     12.98%    100.00%
-system.ruby.L1Cache_Controller.SS.Ack::total        24294                      
-system.ruby.L1Cache_Controller.SS.Shared_Ack |           4     11.76%     11.76% |           4     11.76%     23.53% |           4     11.76%     35.29% |           4     11.76%     47.06% |           3      8.82%     55.88% |           6     17.65%     73.53% |           5     14.71%     88.24% |           4     11.76%    100.00%
-system.ruby.L1Cache_Controller.SS.Shared_Ack::total           34                      
-system.ruby.L1Cache_Controller.SS.All_acks |        1114     12.42%     12.42% |        1096     12.21%     24.63% |        1109     12.36%     36.99% |        1107     12.34%     49.33% |        1091     12.16%     61.48% |        1156     12.88%     74.37% |        1120     12.48%     86.85% |        1180     13.15%    100.00%
-system.ruby.L1Cache_Controller.SS.All_acks::total         8973                      
-system.ruby.L1Cache_Controller.SS.All_acks_no_sharers |        1834     12.26%     12.26% |        1892     12.65%     24.91% |        1866     12.47%     37.38% |        1872     12.52%     49.90% |        1847     12.35%     62.25% |        1846     12.34%     74.59% |        1890     12.64%     87.22% |        1911     12.78%    100.00%
-system.ruby.L1Cache_Controller.SS.All_acks_no_sharers::total        14958                      
-system.ruby.L1Cache_Controller.OI.Load   |           0      0.00%      0.00% |           1     33.33%     33.33% |           2     66.67%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache_Controller.MM.L2_Replacement |       27066     12.47%     12.47% |       27412     12.63%     25.10% |       27127     12.50%     37.60% |       27171     12.52%     50.12% |       27105     12.49%     62.61% |       26848     12.37%     74.98% |       26944     12.41%     87.39% |       27369     12.61%    100.00%
+system.ruby.L1Cache_Controller.MM.L2_Replacement::total       217042                      
+system.ruby.L1Cache_Controller.MM.L1_to_L2 |       27857     12.48%     12.48% |       28167     12.62%     25.10% |       27907     12.50%     37.61% |       27956     12.53%     50.13% |       27889     12.50%     62.63% |       27605     12.37%     75.00% |       27694     12.41%     87.41% |       28099     12.59%    100.00%
+system.ruby.L1Cache_Controller.MM.L1_to_L2::total       223174                      
+system.ruby.L1Cache_Controller.MM.Trigger_L2_to_L1D |          28     13.86%     13.86% |          25     12.38%     26.24% |          32     15.84%     42.08% |          24     11.88%     53.96% |          29     14.36%     68.32% |          23     11.39%     79.70% |          21     10.40%     90.10% |          20      9.90%    100.00%
+system.ruby.L1Cache_Controller.MM.Trigger_L2_to_L1D::total          202                      
+system.ruby.L1Cache_Controller.MM.Other_GETX |         323     12.00%     12.00% |         349     12.96%     24.96% |         322     11.96%     36.92% |         331     12.30%     49.22% |         348     12.93%     62.15% |         351     13.04%     75.19% |         310     11.52%     86.70% |         358     13.30%    100.00%
+system.ruby.L1Cache_Controller.MM.Other_GETX::total         2692                      
+system.ruby.L1Cache_Controller.MM.Other_GETS |         592     13.08%     13.08% |         556     12.29%     25.37% |         572     12.64%     38.01% |         582     12.86%     50.87% |         569     12.57%     63.45% |         533     11.78%     75.23% |         583     12.88%     88.11% |         538     11.89%    100.00%
+system.ruby.L1Cache_Controller.MM.Other_GETS::total         4525                      
+system.ruby.L1Cache_Controller.MM.Merged_GETS |          23     15.86%     15.86% |          13      8.97%     24.83% |          22     15.17%     40.00% |          22     15.17%     55.17% |          21     14.48%     69.66% |          11      7.59%     77.24% |          21     14.48%     91.72% |          12      8.28%    100.00%
+system.ruby.L1Cache_Controller.MM.Merged_GETS::total          145                      
+system.ruby.L1Cache_Controller.IR.Load   |           1     10.00%     10.00% |           1     10.00%     20.00% |           2     20.00%     40.00% |           1     10.00%     50.00% |           1     10.00%     60.00% |           3     30.00%     90.00% |           0      0.00%     90.00% |           1     10.00%    100.00%
+system.ruby.L1Cache_Controller.IR.Load::total           10                      
+system.ruby.L1Cache_Controller.IR.Store  |           1     20.00%     20.00% |           0      0.00%     20.00% |           1     20.00%     40.00% |           1     20.00%     60.00% |           1     20.00%     80.00% |           0      0.00%     80.00% |           0      0.00%     80.00% |           1     20.00%    100.00%
+system.ruby.L1Cache_Controller.IR.Store::total            5                      
+system.ruby.L1Cache_Controller.IR.L1_to_L2 |           0      0.00%      0.00% |           0      0.00%      0.00% |           2     50.00%     50.00% |           2     50.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache_Controller.IR.L1_to_L2::total            4                      
+system.ruby.L1Cache_Controller.SR.Load   |           0      0.00%      0.00% |           2     14.29%     14.29% |           3     21.43%     35.71% |           3     21.43%     57.14% |           2     14.29%     71.43% |           2     14.29%     85.71% |           0      0.00%     85.71% |           2     14.29%    100.00%
+system.ruby.L1Cache_Controller.SR.Load::total           14                      
+system.ruby.L1Cache_Controller.SR.Store  |           0      0.00%      0.00% |           1     14.29%     14.29% |           1     14.29%     28.57% |           0      0.00%     28.57% |           1     14.29%     42.86% |           1     14.29%     57.14% |           3     42.86%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache_Controller.SR.Store::total            7                      
+system.ruby.L1Cache_Controller.SR.L1_to_L2 |           0      0.00%      0.00% |          15     22.39%     22.39% |           0      0.00%     22.39% |          19     28.36%     50.75% |           1      1.49%     52.24% |           9     13.43%     65.67% |          11     16.42%     82.09% |          12     17.91%    100.00%
+system.ruby.L1Cache_Controller.SR.L1_to_L2::total           67                      
+system.ruby.L1Cache_Controller.OR.Load   |           0      0.00%      0.00% |           1     50.00%     50.00% |           0      0.00%     50.00% |           0      0.00%     50.00% |           0      0.00%     50.00% |           1     50.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache_Controller.OR.Load::total            2                      
+system.ruby.L1Cache_Controller.OR.Store  |           3     60.00%     60.00% |           1     20.00%     80.00% |           0      0.00%     80.00% |           1     20.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache_Controller.OR.Store::total            5                      
+system.ruby.L1Cache_Controller.OR.L1_to_L2 |           0      0.00%      0.00% |           3    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache_Controller.OR.L1_to_L2::total            3                      
+system.ruby.L1Cache_Controller.MR.Load   |          31     12.16%     12.16% |          32     12.55%     24.71% |          28     10.98%     35.69% |          30     11.76%     47.45% |          29     11.37%     58.82% |          39     15.29%     74.12% |          31     12.16%     86.27% |          35     13.73%    100.00%
+system.ruby.L1Cache_Controller.MR.Load::total          255                      
+system.ruby.L1Cache_Controller.MR.Store  |          21     15.33%     15.33% |          20     14.60%     29.93% |          14     10.22%     40.15% |          15     10.95%     51.09% |          17     12.41%     63.50% |          11      8.03%     71.53% |          18     13.14%     84.67% |          21     15.33%    100.00%
+system.ruby.L1Cache_Controller.MR.Store::total          137                      
+system.ruby.L1Cache_Controller.MR.L1_to_L2 |          85     11.52%     11.52% |         114     15.45%     26.96% |          93     12.60%     39.57% |         116     15.72%     55.28% |          75     10.16%     65.45% |         106     14.36%     79.81% |          89     12.06%     91.87% |          60      8.13%    100.00%
+system.ruby.L1Cache_Controller.MR.L1_to_L2::total          738                      
+system.ruby.L1Cache_Controller.MMR.Load  |          17     13.08%     13.08% |          15     11.54%     24.62% |          22     16.92%     41.54% |          14     10.77%     52.31% |          19     14.62%     66.92% |          16     12.31%     79.23% |          15     11.54%     90.77% |          12      9.23%    100.00%
+system.ruby.L1Cache_Controller.MMR.Load::total          130                      
+system.ruby.L1Cache_Controller.MMR.Store |          11     15.28%     15.28% |          10     13.89%     29.17% |          10     13.89%     43.06% |          10     13.89%     56.94% |          10     13.89%     70.83% |           7      9.72%     80.56% |           6      8.33%     88.89% |           8     11.11%    100.00%
+system.ruby.L1Cache_Controller.MMR.Store::total           72                      
+system.ruby.L1Cache_Controller.MMR.L1_to_L2 |          92     24.40%     24.40% |          40     10.61%     35.01% |          50     13.26%     48.28% |          50     13.26%     61.54% |          56     14.85%     76.39% |          38     10.08%     86.47% |          37      9.81%     96.29% |          14      3.71%    100.00%
+system.ruby.L1Cache_Controller.MMR.L1_to_L2::total          377                      
+system.ruby.L1Cache_Controller.IM.L1_to_L2 |      279047     12.60%     12.60% |      277330     12.52%     25.12% |      275250     12.43%     37.55% |      279472     12.62%     50.17% |      278951     12.60%     62.76% |      271687     12.27%     75.03% |      273637     12.36%     87.39% |      279316     12.61%    100.00%
+system.ruby.L1Cache_Controller.IM.L1_to_L2::total      2214690                      
+system.ruby.L1Cache_Controller.IM.Other_GETX |          10     12.99%     12.99% |           7      9.09%     22.08% |          10     12.99%     35.06% |           8     10.39%     45.45% |           8     10.39%     55.84% |          12     15.58%     71.43% |          13     16.88%     88.31% |           9     11.69%    100.00%
+system.ruby.L1Cache_Controller.IM.Other_GETX::total           77                      
+system.ruby.L1Cache_Controller.IM.Other_GETS |          14      9.93%      9.93% |          18     12.77%     22.70% |           9      6.38%     29.08% |          18     12.77%     41.84% |          24     17.02%     58.87% |          24     17.02%     75.89% |          23     16.31%     92.20% |          11      7.80%    100.00%
+system.ruby.L1Cache_Controller.IM.Other_GETS::total          141                      
+system.ruby.L1Cache_Controller.IM.Ack    |      192325     12.48%     12.48% |      194543     12.63%     25.11% |      192710     12.51%     37.62% |      193005     12.53%     50.15% |      192362     12.49%     62.64% |      190662     12.38%     75.01% |      191105     12.41%     87.42% |      193794     12.58%    100.00%
+system.ruby.L1Cache_Controller.IM.Ack::total      1540506                      
+system.ruby.L1Cache_Controller.IM.Data   |        1107     12.79%     12.79% |        1055     12.19%     24.98% |        1076     12.43%     37.41% |        1101     12.72%     50.13% |        1084     12.52%     62.65% |        1076     12.43%     75.08% |        1088     12.57%     87.65% |        1069     12.35%    100.00%
+system.ruby.L1Cache_Controller.IM.Data::total         8656                      
+system.ruby.L1Cache_Controller.IM.Exclusive_Data |       26870     12.46%     12.46% |       27253     12.64%     25.11% |       26946     12.50%     37.61% |       26984     12.52%     50.12% |       26942     12.50%     62.62% |       26653     12.36%     74.98% |       26748     12.41%     87.39% |       27179     12.61%    100.00%
+system.ruby.L1Cache_Controller.IM.Exclusive_Data::total       215575                      
+system.ruby.L1Cache_Controller.SM.L1_to_L2 |           0      0.00%      0.00% |           3      5.17%      5.17% |           3      5.17%     10.34% |          11     18.97%     29.31% |           4      6.90%     36.21% |          11     18.97%     55.17% |          26     44.83%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache_Controller.SM.L1_to_L2::total           58                      
+system.ruby.L1Cache_Controller.SM.Ack    |           0      0.00%      0.00% |           7     13.46%     13.46% |          14     26.92%     40.38% |           2      3.85%     44.23% |           7     13.46%     57.69% |           7     13.46%     71.15% |          15     28.85%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache_Controller.SM.Ack::total           52                      
+system.ruby.L1Cache_Controller.SM.Data   |           0      0.00%      0.00% |           1     11.11%     11.11% |           2     22.22%     33.33% |           1     11.11%     44.44% |           1     11.11%     55.56% |           1     11.11%     66.67% |           3     33.33%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache_Controller.SM.Data::total            9                      
+system.ruby.L1Cache_Controller.OM.L1_to_L2 |           1      9.09%      9.09% |          10     90.91%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache_Controller.OM.L1_to_L2::total           11                      
+system.ruby.L1Cache_Controller.OM.Ack    |          21     60.00%     60.00% |           7     20.00%     80.00% |           0      0.00%     80.00% |           7     20.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache_Controller.OM.Ack::total           35                      
+system.ruby.L1Cache_Controller.OM.All_acks_no_sharers |           3     60.00%     60.00% |           1     20.00%     80.00% |           0      0.00%     80.00% |           1     20.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache_Controller.OM.All_acks_no_sharers::total            5                      
+system.ruby.L1Cache_Controller.ISM.L1_to_L2 |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           6    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache_Controller.ISM.L1_to_L2::total            6                      
+system.ruby.L1Cache_Controller.ISM.Ack   |         103     13.09%     13.09% |          72      9.15%     22.24% |          81     10.29%     32.53% |         141     17.92%     50.44% |         104     13.21%     63.66% |          66      8.39%     72.05% |         123     15.63%     87.67% |          97     12.33%    100.00%
+system.ruby.L1Cache_Controller.ISM.Ack::total          787                      
+system.ruby.L1Cache_Controller.ISM.All_acks_no_sharers |        1107     12.78%     12.78% |        1056     12.19%     24.96% |        1078     12.44%     37.40% |        1102     12.72%     50.12% |        1085     12.52%     62.64% |        1077     12.43%     75.07% |        1091     12.59%     87.66% |        1069     12.34%    100.00%
+system.ruby.L1Cache_Controller.ISM.All_acks_no_sharers::total         8665                      
+system.ruby.L1Cache_Controller.M_W.L1_to_L2 |         539     12.99%     12.99% |         495     11.93%     24.92% |         492     11.86%     36.77% |         419     10.10%     46.87% |         531     12.80%     59.66% |         564     13.59%     73.25% |         491     11.83%     85.08% |         619     14.92%    100.00%
+system.ruby.L1Cache_Controller.M_W.L1_to_L2::total         4150                      
+system.ruby.L1Cache_Controller.M_W.Ack   |        1679     12.46%     12.46% |        1730     12.83%     25.29% |        1809     13.42%     38.71% |        1706     12.66%     51.36% |        1691     12.54%     63.91% |        1597     11.85%     75.76% |        1608     11.93%     87.69% |        1660     12.31%    100.00%
+system.ruby.L1Cache_Controller.M_W.Ack::total        13480                      
+system.ruby.L1Cache_Controller.M_W.All_acks_no_sharers |       47493     12.48%     12.48% |       47526     12.49%     24.97% |       47535     12.49%     37.47% |       47618     12.52%     49.99% |       47488     12.48%     62.47% |       47930     12.60%     75.06% |       47754     12.55%     87.62% |       47113     12.38%    100.00%
+system.ruby.L1Cache_Controller.M_W.All_acks_no_sharers::total       380457                      
+system.ruby.L1Cache_Controller.MM_W.L1_to_L2 |         771     11.84%     11.84% |         740     11.36%     23.20% |         854     13.11%     36.31% |         604      9.27%     45.59% |         903     13.86%     59.45% |         860     13.20%     72.65% |         844     12.96%     85.61% |         937     14.39%    100.00%
+system.ruby.L1Cache_Controller.MM_W.L1_to_L2::total         6513                      
+system.ruby.L1Cache_Controller.MM_W.Ack  |        2493     11.87%     11.87% |        2604     12.40%     24.26% |        2495     11.88%     36.14% |        2540     12.09%     48.23% |        2763     13.15%     61.38% |        2507     11.93%     73.31% |        2716     12.93%     86.24% |        2890     13.76%    100.00%
+system.ruby.L1Cache_Controller.MM_W.Ack::total        21008                      
+system.ruby.L1Cache_Controller.MM_W.All_acks_no_sharers |       26870     12.46%     12.46% |       27253     12.64%     25.11% |       26946     12.50%     37.61% |       26984     12.52%     50.12% |       26942     12.50%     62.62% |       26653     12.36%     74.98% |       26748     12.41%     87.39% |       27179     12.61%    100.00%
+system.ruby.L1Cache_Controller.MM_W.All_acks_no_sharers::total       215575                      
+system.ruby.L1Cache_Controller.IS.L1_to_L2 |      498330     12.50%     12.50% |      498790     12.51%     25.01% |      499590     12.53%     37.54% |      497231     12.47%     50.01% |      499578     12.53%     62.54% |      501862     12.59%     75.12% |      498020     12.49%     87.61% |      493961     12.39%    100.00%
+system.ruby.L1Cache_Controller.IS.L1_to_L2::total      3987362                      
+system.ruby.L1Cache_Controller.IS.Other_GETX |          16     11.51%     11.51% |          13      9.35%     20.86% |          20     14.39%     35.25% |          24     17.27%     52.52% |          18     12.95%     65.47% |          14     10.07%     75.54% |          20     14.39%     89.93% |          14     10.07%    100.00%
+system.ruby.L1Cache_Controller.IS.Other_GETX::total          139                      
+system.ruby.L1Cache_Controller.IS.Other_GETS |          39     14.44%     14.44% |          43     15.93%     30.37% |          23      8.52%     38.89% |          35     12.96%     51.85% |          33     12.22%     64.07% |          32     11.85%     75.93% |          38     14.07%     90.00% |          27     10.00%    100.00%
+system.ruby.L1Cache_Controller.IS.Other_GETS::total          270                      
+system.ruby.L1Cache_Controller.IS.Ack    |      345718     12.46%     12.46% |      346858     12.50%     24.96% |      346646     12.49%     37.46% |      347061     12.51%     49.97% |      346855     12.50%     62.47% |      349503     12.60%     75.06% |      348504     12.56%     87.63% |      343326     12.37%    100.00%
+system.ruby.L1Cache_Controller.IS.Ack::total      2774471                      
+system.ruby.L1Cache_Controller.IS.Shared_Ack |          44     11.43%     11.43% |          49     12.73%     24.16% |          57     14.81%     38.96% |          46     11.95%     50.91% |          36      9.35%     60.26% |          53     13.77%     74.03% |          48     12.47%     86.49% |          52     13.51%    100.00%
+system.ruby.L1Cache_Controller.IS.Shared_Ack::total          385                      
+system.ruby.L1Cache_Controller.IS.Data   |        1795     12.01%     12.01% |        1900     12.71%     24.72% |        1874     12.54%     37.26% |        1854     12.41%     49.67% |        1936     12.95%     62.62% |        1855     12.41%     75.04% |        1872     12.53%     87.56% |        1859     12.44%    100.00%
+system.ruby.L1Cache_Controller.IS.Data::total        14945                      
+system.ruby.L1Cache_Controller.IS.Shared_Data |        1044     12.06%     12.06% |        1090     12.59%     24.65% |        1109     12.81%     37.47% |        1077     12.44%     49.91% |        1114     12.87%     62.78% |        1071     12.37%     75.15% |        1132     13.08%     88.23% |        1019     11.77%    100.00%
+system.ruby.L1Cache_Controller.IS.Shared_Data::total         8656                      
+system.ruby.L1Cache_Controller.IS.Exclusive_Data |       47493     12.48%     12.48% |       47526     12.49%     24.97% |       47535     12.49%     37.47% |       47618     12.52%     49.99% |       47488     12.48%     62.47% |       47930     12.60%     75.06% |       47754     12.55%     87.62% |       47113     12.38%    100.00%
+system.ruby.L1Cache_Controller.IS.Exclusive_Data::total       380457                      
+system.ruby.L1Cache_Controller.SS.L1_to_L2 |         904     11.52%     11.52% |        1091     13.90%     25.42% |        1010     12.87%     38.29% |        1049     13.37%     51.66% |        1008     12.84%     64.50% |        1028     13.10%     77.60% |         970     12.36%     89.96% |         788     10.04%    100.00%
+system.ruby.L1Cache_Controller.SS.L1_to_L2::total         7848                      
+system.ruby.L1Cache_Controller.SS.Ack    |        2951     12.08%     12.08% |        3044     12.46%     24.53% |        3159     12.93%     37.46% |        3048     12.47%     49.93% |        3201     13.10%     63.03% |        2889     11.82%     74.86% |        3172     12.98%     87.84% |        2972     12.16%    100.00%
+system.ruby.L1Cache_Controller.SS.Ack::total        24436                      
+system.ruby.L1Cache_Controller.SS.Shared_Ack |           2      7.41%      7.41% |           3     11.11%     18.52% |           3     11.11%     29.63% |           2      7.41%     37.04% |           2      7.41%     44.44% |           6     22.22%     66.67% |           1      3.70%     70.37% |           8     29.63%    100.00%
+system.ruby.L1Cache_Controller.SS.Shared_Ack::total           27                      
+system.ruby.L1Cache_Controller.SS.All_acks |        1085     12.05%     12.05% |        1134     12.59%     24.64% |        1163     12.91%     37.55% |        1122     12.46%     50.01% |        1145     12.71%     62.72% |        1121     12.45%     75.16% |        1174     13.03%     88.20% |        1063     11.80%    100.00%
+system.ruby.L1Cache_Controller.SS.All_acks::total         9007                      
+system.ruby.L1Cache_Controller.SS.All_acks_no_sharers |        1754     12.02%     12.02% |        1856     12.72%     24.74% |        1820     12.47%     37.21% |        1809     12.40%     49.60% |        1905     13.05%     62.66% |        1805     12.37%     75.02% |        1830     12.54%     87.56% |        1815     12.44%    100.00%
+system.ruby.L1Cache_Controller.SS.All_acks_no_sharers::total        14594                      
+system.ruby.L1Cache_Controller.OI.Load   |           1     33.33%     33.33% |           0      0.00%     33.33% |           1     33.33%     66.67% |           0      0.00%     66.67% |           0      0.00%     66.67% |           1     33.33%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.L1Cache_Controller.OI.Load::total            3                      
-system.ruby.L1Cache_Controller.OI.Other_GETX |           0      0.00%      0.00% |           0      0.00%      0.00% |           2    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.L1Cache_Controller.OI.Other_GETX::total            2                      
-system.ruby.L1Cache_Controller.OI.Other_GETS |           1     33.33%     33.33% |           0      0.00%     33.33% |           0      0.00%     33.33% |           1     33.33%     66.67% |           0      0.00%     66.67% |           0      0.00%     66.67% |           0      0.00%     66.67% |           1     33.33%    100.00%
+system.ruby.L1Cache_Controller.OI.Other_GETX |           1     20.00%     20.00% |           0      0.00%     20.00% |           0      0.00%     20.00% |           1     20.00%     40.00% |           0      0.00%     40.00% |           0      0.00%     40.00% |           1     20.00%     60.00% |           2     40.00%    100.00%
+system.ruby.L1Cache_Controller.OI.Other_GETX::total            5                      
+system.ruby.L1Cache_Controller.OI.Other_GETS |           1     33.33%     33.33% |           0      0.00%     33.33% |           0      0.00%     33.33% |           0      0.00%     33.33% |           1     33.33%     66.67% |           0      0.00%     66.67% |           1     33.33%    100.00% |           0      0.00%    100.00%
 system.ruby.L1Cache_Controller.OI.Other_GETS::total            3                      
-system.ruby.L1Cache_Controller.OI.Merged_GETS |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           1    100.00%    100.00% |           0      0.00%    100.00%
-system.ruby.L1Cache_Controller.OI.Merged_GETS::total            1                      
-system.ruby.L1Cache_Controller.OI.Writeback_Ack |        1085     12.95%     12.95% |        1073     12.81%     25.75% |        1027     12.26%     38.01% |        1041     12.42%     50.44% |        1020     12.17%     62.61% |        1047     12.50%     75.10% |        1077     12.85%     87.96% |        1009     12.04%    100.00%
-system.ruby.L1Cache_Controller.OI.Writeback_Ack::total         8379                      
-system.ruby.L1Cache_Controller.MI.Load   |          10     11.63%     11.63% |          11     12.79%     24.42% |          14     16.28%     40.70% |          12     13.95%     54.65% |          12     13.95%     68.60% |           8      9.30%     77.91% |           7      8.14%     86.05% |          12     13.95%    100.00%
-system.ruby.L1Cache_Controller.MI.Load::total           86                      
-system.ruby.L1Cache_Controller.MI.Store  |           7     12.07%     12.07% |           4      6.90%     18.97% |           4      6.90%     25.86% |          12     20.69%     46.55% |           9     15.52%     62.07% |           7     12.07%     74.14% |           8     13.79%     87.93% |           7     12.07%    100.00%
-system.ruby.L1Cache_Controller.MI.Store::total           58                      
-system.ruby.L1Cache_Controller.MI.Other_GETX |          25     11.47%     11.47% |          32     14.68%     26.15% |          30     13.76%     39.91% |          25     11.47%     51.38% |          31     14.22%     65.60% |          29     13.30%     78.90% |          29     13.30%     92.20% |          17      7.80%    100.00%
-system.ruby.L1Cache_Controller.MI.Other_GETX::total          218                      
-system.ruby.L1Cache_Controller.MI.Other_GETS |          47     13.31%     13.31% |          39     11.05%     24.36% |          39     11.05%     35.41% |          42     11.90%     47.31% |          48     13.60%     60.91% |          46     13.03%     73.94% |          63     17.85%     91.78% |          29      8.22%    100.00%
-system.ruby.L1Cache_Controller.MI.Other_GETS::total          353                      
-system.ruby.L1Cache_Controller.MI.Merged_GETS |           1     50.00%     50.00% |           1     50.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.L1Cache_Controller.MI.Merged_GETS::total            2                      
-system.ruby.L1Cache_Controller.MI.Writeback_Ack |       71509     12.46%     12.46% |       71917     12.54%     25.00% |       71762     12.51%     37.51% |       71899     12.53%     50.04% |       71741     12.51%     62.55% |       71488     12.46%     75.01% |       72063     12.56%     87.57% |       71314     12.43%    100.00%
-system.ruby.L1Cache_Controller.MI.Writeback_Ack::total       573693                      
-system.ruby.L1Cache_Controller.II.Writeback_Ack |          25     11.36%     11.36% |          32     14.55%     25.91% |          32     14.55%     40.45% |          25     11.36%     51.82% |          31     14.09%     65.91% |          29     13.18%     79.09% |          29     13.18%     92.27% |          17      7.73%    100.00%
-system.ruby.L1Cache_Controller.II.Writeback_Ack::total          220                      
-system.ruby.L1Cache_Controller.IT.Load   |           0      0.00%      0.00% |           0      0.00%      0.00% |           1     33.33%     33.33% |           0      0.00%     33.33% |           0      0.00%     33.33% |           0      0.00%     33.33% |           0      0.00%     33.33% |           2     66.67%    100.00%
+system.ruby.L1Cache_Controller.OI.Merged_GETS |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           1     50.00%     50.00% |           1     50.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache_Controller.OI.Merged_GETS::total            2                      
+system.ruby.L1Cache_Controller.OI.Writeback_Ack |        1055     12.45%     12.45% |        1057     12.47%     24.92% |        1035     12.21%     37.14% |        1081     12.76%     49.89% |        1041     12.28%     62.18% |        1043     12.31%     74.49% |        1099     12.97%     87.46% |        1063     12.54%    100.00%
+system.ruby.L1Cache_Controller.OI.Writeback_Ack::total         8474                      
+system.ruby.L1Cache_Controller.MI.Load   |          14     16.09%     16.09% |          13     14.94%     31.03% |           8      9.20%     40.23% |          11     12.64%     52.87% |          12     13.79%     66.67% |           8      9.20%     75.86% |           9     10.34%     86.21% |          12     13.79%    100.00%
+system.ruby.L1Cache_Controller.MI.Load::total           87                      
+system.ruby.L1Cache_Controller.MI.Store  |           5     10.20%     10.20% |           8     16.33%     26.53% |           5     10.20%     36.73% |           4      8.16%     44.90% |           7     14.29%     59.18% |          10     20.41%     79.59% |           4      8.16%     87.76% |           6     12.24%    100.00%
+system.ruby.L1Cache_Controller.MI.Store::total           49                      
+system.ruby.L1Cache_Controller.MI.Other_GETX |          15      7.65%      7.65% |          26     13.27%     20.92% |          21     10.71%     31.63% |          15      7.65%     39.29% |          36     18.37%     57.65% |          32     16.33%     73.98% |          28     14.29%     88.27% |          23     11.73%    100.00%
+system.ruby.L1Cache_Controller.MI.Other_GETX::total          196                      
+system.ruby.L1Cache_Controller.MI.Other_GETS |          43     10.75%     10.75% |          55     13.75%     24.50% |          44     11.00%     35.50% |          60     15.00%     50.50% |          44     11.00%     61.50% |          48     12.00%     73.50% |          49     12.25%     85.75% |          57     14.25%    100.00%
+system.ruby.L1Cache_Controller.MI.Other_GETS::total          400                      
+system.ruby.L1Cache_Controller.MI.Merged_GETS |           1     20.00%     20.00% |           1     20.00%     40.00% |           1     20.00%     60.00% |           0      0.00%     60.00% |           0      0.00%     60.00% |           0      0.00%     60.00% |           2     40.00%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache_Controller.MI.Merged_GETS::total            5                      
+system.ruby.L1Cache_Controller.MI.Writeback_Ack |       72894     12.48%     12.48% |       73267     12.54%     25.02% |       73072     12.51%     37.52% |       73104     12.51%     50.04% |       72950     12.49%     62.52% |       73104     12.51%     75.03% |       73016     12.50%     87.53% |       72843     12.47%    100.00%
+system.ruby.L1Cache_Controller.MI.Writeback_Ack::total       584250                      
+system.ruby.L1Cache_Controller.II.Writeback_Ack |          16      7.96%      7.96% |          26     12.94%     20.90% |          21     10.45%     31.34% |          16      7.96%     39.30% |          36     17.91%     57.21% |          32     15.92%     73.13% |          29     14.43%     87.56% |          25     12.44%    100.00%
+system.ruby.L1Cache_Controller.II.Writeback_Ack::total          201                      
+system.ruby.L1Cache_Controller.IT.Load   |           0      0.00%      0.00% |           0      0.00%      0.00% |           2     66.67%     66.67% |           1     33.33%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.L1Cache_Controller.IT.Load::total            3                      
-system.ruby.L1Cache_Controller.IT.Store  |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           1     50.00%     50.00% |           0      0.00%     50.00% |           1     50.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.L1Cache_Controller.IT.Store::total            2                      
-system.ruby.L1Cache_Controller.IT.L1_to_L2 |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           1      4.17%      4.17% |           0      0.00%      4.17% |          11     45.83%     50.00% |           9     37.50%     87.50% |           3     12.50%    100.00%
-system.ruby.L1Cache_Controller.IT.L1_to_L2::total           24                      
-system.ruby.L1Cache_Controller.IT.Complete_L2_to_L1 |           3     20.00%     20.00% |           0      0.00%     20.00% |           1      6.67%     26.67% |           2     13.33%     40.00% |           0      0.00%     40.00% |           4     26.67%     66.67% |           2     13.33%     80.00% |           3     20.00%    100.00%
+system.ruby.L1Cache_Controller.IT.L1_to_L2 |           0      0.00%      0.00% |           0      0.00%      0.00% |           2     15.38%     15.38% |           2     15.38%     30.77% |           9     69.23%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache_Controller.IT.L1_to_L2::total           13                      
+system.ruby.L1Cache_Controller.IT.Complete_L2_to_L1 |           2     13.33%     13.33% |           1      6.67%     20.00% |           3     20.00%     40.00% |           2     13.33%     53.33% |           2     13.33%     66.67% |           3     20.00%     86.67% |           0      0.00%     86.67% |           2     13.33%    100.00%
 system.ruby.L1Cache_Controller.IT.Complete_L2_to_L1::total           15                      
-system.ruby.L1Cache_Controller.ST.Load   |           0      0.00%      0.00% |           1     20.00%     20.00% |           0      0.00%     20.00% |           0      0.00%     20.00% |           0      0.00%     20.00% |           1     20.00%     40.00% |           0      0.00%     40.00% |           3     60.00%    100.00%
-system.ruby.L1Cache_Controller.ST.Load::total            5                      
-system.ruby.L1Cache_Controller.ST.Store  |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           1    100.00%    100.00%
-system.ruby.L1Cache_Controller.ST.Store::total            1                      
-system.ruby.L1Cache_Controller.ST.L1_to_L2 |          10     12.99%     12.99% |          21     27.27%     40.26% |           7      9.09%     49.35% |           9     11.69%     61.04% |           0      0.00%     61.04% |           0      0.00%     61.04% |           5      6.49%     67.53% |          25     32.47%    100.00%
-system.ruby.L1Cache_Controller.ST.L1_to_L2::total           77                      
-system.ruby.L1Cache_Controller.ST.Complete_L2_to_L1 |           2      8.70%      8.70% |           5     21.74%     30.43% |           4     17.39%     47.83% |           1      4.35%     52.17% |           0      0.00%     52.17% |           2      8.70%     60.87% |           3     13.04%     73.91% |           6     26.09%    100.00%
-system.ruby.L1Cache_Controller.ST.Complete_L2_to_L1::total           23                      
-system.ruby.L1Cache_Controller.OT.Load   |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           2    100.00%    100.00%
-system.ruby.L1Cache_Controller.OT.Load::total            2                      
-system.ruby.L1Cache_Controller.OT.L1_to_L2 |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           6    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.L1Cache_Controller.OT.L1_to_L2::total            6                      
-system.ruby.L1Cache_Controller.OT.Complete_L2_to_L1 |           0      0.00%      0.00% |           2     33.33%     33.33% |           0      0.00%     33.33% |           1     16.67%     50.00% |           0      0.00%     50.00% |           1     16.67%     66.67% |           0      0.00%     66.67% |           2     33.33%    100.00%
-system.ruby.L1Cache_Controller.OT.Complete_L2_to_L1::total            6                      
-system.ruby.L1Cache_Controller.MT.Load   |          13     13.68%     13.68% |           7      7.37%     21.05% |          10     10.53%     31.58% |          13     13.68%     45.26% |          10     10.53%     55.79% |          14     14.74%     70.53% |          13     13.68%     84.21% |          15     15.79%    100.00%
-system.ruby.L1Cache_Controller.MT.Load::total           95                      
-system.ruby.L1Cache_Controller.MT.Store  |           6     10.71%     10.71% |           9     16.07%     26.79% |           9     16.07%     42.86% |           9     16.07%     58.93% |           9     16.07%     75.00% |           7     12.50%     87.50% |           5      8.93%     96.43% |           2      3.57%    100.00%
-system.ruby.L1Cache_Controller.MT.Store::total           56                      
-system.ruby.L1Cache_Controller.MT.L1_to_L2 |         179     15.61%     15.61% |         117     10.20%     25.81% |         164     14.30%     40.10% |         171     14.91%     55.01% |         115     10.03%     65.04% |         155     13.51%     78.55% |          80      6.97%     85.53% |         166     14.47%    100.00%
-system.ruby.L1Cache_Controller.MT.L1_to_L2::total         1147                      
-system.ruby.L1Cache_Controller.MT.Complete_L2_to_L1 |          49     13.14%     13.14% |          40     10.72%     23.86% |          60     16.09%     39.95% |          51     13.67%     53.62% |          41     10.99%     64.61% |          55     14.75%     79.36% |          37      9.92%     89.28% |          40     10.72%    100.00%
-system.ruby.L1Cache_Controller.MT.Complete_L2_to_L1::total          373                      
-system.ruby.L1Cache_Controller.MMT.Load  |           8     13.79%     13.79% |          11     18.97%     32.76% |           7     12.07%     44.83% |           8     13.79%     58.62% |           6     10.34%     68.97% |           4      6.90%     75.86% |           9     15.52%     91.38% |           5      8.62%    100.00%
+system.ruby.L1Cache_Controller.ST.Load   |           0      0.00%      0.00% |           2     22.22%     22.22% |           1     11.11%     33.33% |           3     33.33%     66.67% |           0      0.00%     66.67% |           1     11.11%     77.78% |           0      0.00%     77.78% |           2     22.22%    100.00%
+system.ruby.L1Cache_Controller.ST.Load::total            9                      
+system.ruby.L1Cache_Controller.ST.Store  |           0      0.00%      0.00% |           1     25.00%     25.00% |           0      0.00%     25.00% |           0      0.00%     25.00% |           1     25.00%     50.00% |           0      0.00%     50.00% |           2     50.00%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache_Controller.ST.Store::total            4                      
+system.ruby.L1Cache_Controller.ST.L1_to_L2 |           0      0.00%      0.00% |          15     17.24%     17.24% |           1      1.15%     18.39% |          19     21.84%     40.23% |           7      8.05%     48.28% |          14     16.09%     64.37% |          19     21.84%     86.21% |          12     13.79%    100.00%
+system.ruby.L1Cache_Controller.ST.L1_to_L2::total           87                      
+system.ruby.L1Cache_Controller.ST.Complete_L2_to_L1 |           0      0.00%      0.00% |           3     14.29%     14.29% |           4     19.05%     33.33% |           3     14.29%     47.62% |           3     14.29%     61.90% |           3     14.29%     76.19% |           3     14.29%     90.48% |           2      9.52%    100.00%
+system.ruby.L1Cache_Controller.ST.Complete_L2_to_L1::total           21                      
+system.ruby.L1Cache_Controller.OT.Load   |           0      0.00%      0.00% |           1    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache_Controller.OT.Load::total            1                      
+system.ruby.L1Cache_Controller.OT.Store  |           2     66.67%     66.67% |           0      0.00%     66.67% |           0      0.00%     66.67% |           1     33.33%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache_Controller.OT.Store::total            3                      
+system.ruby.L1Cache_Controller.OT.L1_to_L2 |           0      0.00%      0.00% |          12    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache_Controller.OT.L1_to_L2::total           12                      
+system.ruby.L1Cache_Controller.OT.Complete_L2_to_L1 |           3     42.86%     42.86% |           2     28.57%     71.43% |           0      0.00%     71.43% |           1     14.29%     85.71% |           0      0.00%     85.71% |           1     14.29%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache_Controller.OT.Complete_L2_to_L1::total            7                      
+system.ruby.L1Cache_Controller.MT.Load   |          15     13.04%     13.04% |          15     13.04%     26.09% |          15     13.04%     39.13% |          18     15.65%     54.78% |          10      8.70%     63.48% |          19     16.52%     80.00% |          14     12.17%     92.17% |           9      7.83%    100.00%
+system.ruby.L1Cache_Controller.MT.Load::total          115                      
+system.ruby.L1Cache_Controller.MT.Store  |           9     15.00%     15.00% |          12     20.00%     35.00% |           6     10.00%     45.00% |           5      8.33%     53.33% |           9     15.00%     68.33% |           4      6.67%     75.00% |           5      8.33%     83.33% |          10     16.67%    100.00%
+system.ruby.L1Cache_Controller.MT.Store::total           60                      
+system.ruby.L1Cache_Controller.MT.L1_to_L2 |         188     13.56%     13.56% |         221     15.95%     29.51% |         164     11.83%     41.34% |         173     12.48%     53.82% |         142     10.25%     64.07% |         170     12.27%     76.33% |         188     13.56%     89.90% |         140     10.10%    100.00%
+system.ruby.L1Cache_Controller.MT.L1_to_L2::total         1386                      
+system.ruby.L1Cache_Controller.MT.Complete_L2_to_L1 |          52     13.27%     13.27% |          52     13.27%     26.53% |          42     10.71%     37.24% |          45     11.48%     48.72% |          46     11.73%     60.46% |          50     12.76%     73.21% |          49     12.50%     85.71% |          56     14.29%    100.00%
+system.ruby.L1Cache_Controller.MT.Complete_L2_to_L1::total          392                      
+system.ruby.L1Cache_Controller.MMT.Load  |           9     15.52%     15.52% |           7     12.07%     27.59% |          12     20.69%     48.28% |           6     10.34%     58.62% |           8     13.79%     72.41% |           7     12.07%     84.48% |           6     10.34%     94.83% |           3      5.17%    100.00%
 system.ruby.L1Cache_Controller.MMT.Load::total           58                      
-system.ruby.L1Cache_Controller.MMT.Store |           4     14.29%     14.29% |           3     10.71%     25.00% |           4     14.29%     39.29% |           2      7.14%     46.43% |           5     17.86%     64.29% |           3     10.71%     75.00% |           5     17.86%     92.86% |           2      7.14%    100.00%
-system.ruby.L1Cache_Controller.MMT.Store::total           28                      
-system.ruby.L1Cache_Controller.MMT.L1_to_L2 |          86     11.35%     11.35% |         139     18.34%     29.68% |          85     11.21%     40.90% |          97     12.80%     53.69% |          90     11.87%     65.57% |          91     12.01%     77.57% |          78     10.29%     87.86% |          92     12.14%    100.00%
-system.ruby.L1Cache_Controller.MMT.L1_to_L2::total          758                      
-system.ruby.L1Cache_Controller.MMT.Complete_L2_to_L1 |          21     10.29%     10.29% |          25     12.25%     22.55% |          34     16.67%     39.22% |          24     11.76%     50.98% |          25     12.25%     63.24% |          27     13.24%     76.47% |          27     13.24%     89.71% |          21     10.29%    100.00%
-system.ruby.L1Cache_Controller.MMT.Complete_L2_to_L1::total          204                      
-system.ruby.Directory_Controller.GETX          220023      0.00%      0.00%
-system.ruby.Directory_Controller.GETS          406995      0.00%      0.00%
-system.ruby.Directory_Controller.PUT           585083      0.00%      0.00%
-system.ruby.Directory_Controller.Unblock          220      0.00%      0.00%
-system.ruby.Directory_Controller.UnblockS        23931      0.00%      0.00%
-system.ruby.Directory_Controller.UnblockM       593445      0.00%      0.00%
-system.ruby.Directory_Controller.Writeback_Clean         8030      0.00%      0.00%
-system.ruby.Directory_Controller.Writeback_Dirty          349      0.00%      0.00%
-system.ruby.Directory_Controller.Writeback_Exclusive_Clean       360015      0.00%      0.00%
-system.ruby.Directory_Controller.Writeback_Exclusive_Dirty       213674      0.00%      0.00%
-system.ruby.Directory_Controller.Memory_Data       597503      0.00%      0.00%
-system.ruby.Directory_Controller.Memory_Ack       214013      0.00%      0.00%
-system.ruby.Directory_Controller.All_Unblocks          439      0.00%      0.00%
-system.ruby.Directory_Controller.NX.GETX           61      0.00%      0.00%
-system.ruby.Directory_Controller.NX.GETS           97      0.00%      0.00%
-system.ruby.Directory_Controller.NX.PUT          8595      0.00%      0.00%
-system.ruby.Directory_Controller.NO.GETX         6880      0.00%      0.00%
-system.ruby.Directory_Controller.NO.GETS        12400      0.00%      0.00%
-system.ruby.Directory_Controller.NO.PUT        573697      0.00%      0.00%
-system.ruby.Directory_Controller.O.GETX          8316      0.00%      0.00%
-system.ruby.Directory_Controller.O.GETS         15375      0.00%      0.00%
-system.ruby.Directory_Controller.E.GETX        201220      0.00%      0.00%
-system.ruby.Directory_Controller.E.GETS        372612      0.00%      0.00%
-system.ruby.Directory_Controller.NO_B.GETX          205      0.00%      0.00%
-system.ruby.Directory_Controller.NO_B.GETS          439      0.00%      0.00%
-system.ruby.Directory_Controller.NO_B.PUT         2778      0.00%      0.00%
-system.ruby.Directory_Controller.NO_B.UnblockS         8092      0.00%      0.00%
-system.ruby.Directory_Controller.NO_B.UnblockM       592827      0.00%      0.00%
-system.ruby.Directory_Controller.NO_B_X.UnblockS            4      0.00%      0.00%
-system.ruby.Directory_Controller.NO_B_X.UnblockM          201      0.00%      0.00%
-system.ruby.Directory_Controller.NO_B_S.PUT            2      0.00%      0.00%
-system.ruby.Directory_Controller.NO_B_S.UnblockS           22      0.00%      0.00%
-system.ruby.Directory_Controller.NO_B_S.UnblockM          417      0.00%      0.00%
-system.ruby.Directory_Controller.NO_B_S_W.GETX            1      0.00%      0.00%
-system.ruby.Directory_Controller.NO_B_S_W.GETS            1      0.00%      0.00%
-system.ruby.Directory_Controller.NO_B_S_W.PUT            7      0.00%      0.00%
-system.ruby.Directory_Controller.NO_B_S_W.UnblockS          439      0.00%      0.00%
-system.ruby.Directory_Controller.NO_B_S_W.All_Unblocks          439      0.00%      0.00%
-system.ruby.Directory_Controller.O_B.GETX            9      0.00%      0.00%
-system.ruby.Directory_Controller.O_B.GETS            6      0.00%      0.00%
-system.ruby.Directory_Controller.O_B.UnblockS        15374      0.00%      0.00%
-system.ruby.Directory_Controller.NO_B_W.GETX         1957      0.00%      0.00%
-system.ruby.Directory_Controller.NO_B_W.GETS         3492      0.00%      0.00%
-system.ruby.Directory_Controller.NO_B_W.Memory_Data       582129      0.00%      0.00%
-system.ruby.Directory_Controller.O_B_W.GETX           38      0.00%      0.00%
-system.ruby.Directory_Controller.O_B_W.GETS          103      0.00%      0.00%
-system.ruby.Directory_Controller.O_B_W.Memory_Data        15374      0.00%      0.00%
-system.ruby.Directory_Controller.WB.GETX          295      0.00%      0.00%
-system.ruby.Directory_Controller.WB.GETS          514      0.00%      0.00%
-system.ruby.Directory_Controller.WB.PUT             4      0.00%      0.00%
-system.ruby.Directory_Controller.WB.Unblock          220      0.00%      0.00%
-system.ruby.Directory_Controller.WB.Writeback_Clean         8030      0.00%      0.00%
-system.ruby.Directory_Controller.WB.Writeback_Dirty          349      0.00%      0.00%
-system.ruby.Directory_Controller.WB.Writeback_Exclusive_Clean       360015      0.00%      0.00%
-system.ruby.Directory_Controller.WB.Writeback_Exclusive_Dirty       213674      0.00%      0.00%
-system.ruby.Directory_Controller.WB_O_W.GETS            3      0.00%      0.00%
-system.ruby.Directory_Controller.WB_O_W.Memory_Ack          348      0.00%      0.00%
-system.ruby.Directory_Controller.WB_E_W.GETX         1041      0.00%      0.00%
-system.ruby.Directory_Controller.WB_E_W.GETS         1953      0.00%      0.00%
-system.ruby.Directory_Controller.WB_E_W.Memory_Ack       213665      0.00%      0.00%
+system.ruby.L1Cache_Controller.MMT.Store |           5     15.62%     15.62% |           6     18.75%     34.38% |           3      9.38%     43.75% |           7     21.88%     65.62% |           3      9.38%     75.00% |           3      9.38%     84.38% |           2      6.25%     90.62% |           3      9.38%    100.00%
+system.ruby.L1Cache_Controller.MMT.Store::total           32                      
+system.ruby.L1Cache_Controller.MMT.L1_to_L2 |         176     22.51%     22.51% |          96     12.28%     34.78% |          95     12.15%     46.93% |          80     10.23%     57.16% |          78      9.97%     67.14% |          94     12.02%     79.16% |         107     13.68%     92.84% |          56      7.16%    100.00%
+system.ruby.L1Cache_Controller.MMT.L1_to_L2::total          782                      
+system.ruby.L1Cache_Controller.MMT.Complete_L2_to_L1 |          28     13.86%     13.86% |          25     12.38%     26.24% |          32     15.84%     42.08% |          24     11.88%     53.96% |          29     14.36%     68.32% |          23     11.39%     79.70% |          21     10.40%     90.10% |          20      9.90%    100.00%
+system.ruby.L1Cache_Controller.MMT.Complete_L2_to_L1::total          202                      
+system.ruby.Directory_Controller.GETX          227829      0.00%      0.00%
+system.ruby.Directory_Controller.GETS          410069      0.00%      0.00%
+system.ruby.Directory_Controller.PUT           595805      0.00%      0.00%
+system.ruby.Directory_Controller.Unblock          201      0.00%      0.00%
+system.ruby.Directory_Controller.UnblockS        23601      0.00%      0.00%
+system.ruby.Directory_Controller.UnblockM       604700      0.00%      0.00%
+system.ruby.Directory_Controller.Writeback_Clean         8091      0.00%      0.00%
+system.ruby.Directory_Controller.Writeback_Dirty          383      0.00%      0.00%
+system.ruby.Directory_Controller.Writeback_Exclusive_Clean       363032      0.00%      0.00%
+system.ruby.Directory_Controller.Writeback_Exclusive_Dirty       221218      0.00%      0.00%
+system.ruby.Directory_Controller.Memory_Data       607721      0.00%      0.00%
+system.ruby.Directory_Controller.Memory_Ack       221589      0.00%      0.00%
+system.ruby.Directory_Controller.All_Unblocks          423      0.00%      0.00%
+system.ruby.Directory_Controller.NX.GETX           74      0.00%      0.00%
+system.ruby.Directory_Controller.NX.GETS           87      0.00%      0.00%
+system.ruby.Directory_Controller.NX.PUT          8671      0.00%      0.00%
+system.ruby.Directory_Controller.NO.GETX         7327      0.00%      0.00%
+system.ruby.Directory_Controller.NO.GETS        12671      0.00%      0.00%
+system.ruby.Directory_Controller.NO.PUT        584254      0.00%      0.00%
+system.ruby.Directory_Controller.O.GETX          8405      0.00%      0.00%
+system.ruby.Directory_Controller.O.GETS         14947      0.00%      0.00%
+system.ruby.Directory_Controller.E.GETX        208449      0.00%      0.00%
+system.ruby.Directory_Controller.E.GETS        375946      0.00%      0.00%
+system.ruby.Directory_Controller.NO_B.GETX          243      0.00%      0.00%
+system.ruby.Directory_Controller.NO_B.GETS          423      0.00%      0.00%
+system.ruby.Directory_Controller.NO_B.PUT         2868      0.00%      0.00%
+system.ruby.Directory_Controller.NO_B.UnblockS         8198      0.00%      0.00%
+system.ruby.Directory_Controller.NO_B.UnblockM       604069      0.00%      0.00%
+system.ruby.Directory_Controller.NO_B_X.PUT            1      0.00%      0.00%
+system.ruby.Directory_Controller.NO_B_X.UnblockS           11      0.00%      0.00%
+system.ruby.Directory_Controller.NO_B_X.UnblockM          232      0.00%      0.00%
+system.ruby.Directory_Controller.NO_B_S.UnblockS           24      0.00%      0.00%
+system.ruby.Directory_Controller.NO_B_S.UnblockM          399      0.00%      0.00%
+system.ruby.Directory_Controller.NO_B_S_W.PUT           10      0.00%      0.00%
+system.ruby.Directory_Controller.NO_B_S_W.UnblockS          423      0.00%      0.00%
+system.ruby.Directory_Controller.NO_B_S_W.All_Unblocks          423      0.00%      0.00%
+system.ruby.Directory_Controller.O_B.GETX            5      0.00%      0.00%
+system.ruby.Directory_Controller.O_B.GETS            5      0.00%      0.00%
+system.ruby.Directory_Controller.O_B.UnblockS        14945      0.00%      0.00%
+system.ruby.Directory_Controller.NO_B_W.GETX         1903      0.00%      0.00%
+system.ruby.Directory_Controller.NO_B_W.GETS         3455      0.00%      0.00%
+system.ruby.Directory_Controller.NO_B_W.Memory_Data       592776      0.00%      0.00%
+system.ruby.Directory_Controller.O_B_W.GETX           48      0.00%      0.00%
+system.ruby.Directory_Controller.O_B_W.GETS           72      0.00%      0.00%
+system.ruby.Directory_Controller.O_B_W.Memory_Data        14945      0.00%      0.00%
+system.ruby.Directory_Controller.WB.GETX          290      0.00%      0.00%
+system.ruby.Directory_Controller.WB.GETS          530      0.00%      0.00%
+system.ruby.Directory_Controller.WB.PUT             1      0.00%      0.00%
+system.ruby.Directory_Controller.WB.Unblock          201      0.00%      0.00%
+system.ruby.Directory_Controller.WB.Writeback_Clean         8091      0.00%      0.00%
+system.ruby.Directory_Controller.WB.Writeback_Dirty          383      0.00%      0.00%
+system.ruby.Directory_Controller.WB.Writeback_Exclusive_Clean       363032      0.00%      0.00%
+system.ruby.Directory_Controller.WB.Writeback_Exclusive_Dirty       221218      0.00%      0.00%
+system.ruby.Directory_Controller.WB_O_W.GETX            3      0.00%      0.00%
+system.ruby.Directory_Controller.WB_O_W.GETS            2      0.00%      0.00%
+system.ruby.Directory_Controller.WB_O_W.Memory_Ack          383      0.00%      0.00%
+system.ruby.Directory_Controller.WB_E_W.GETX         1082      0.00%      0.00%
+system.ruby.Directory_Controller.WB_E_W.GETS         1931      0.00%      0.00%
+system.ruby.Directory_Controller.WB_E_W.Memory_Ack       221206      0.00%      0.00%
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt
index ef37353bc..f296585bd 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt
@@ -1,529 +1,529 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.008665                       # Number of seconds simulated
-sim_ticks                                     8664886                       # Number of ticks simulated
-final_tick                                    8664886                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.008851                       # Number of seconds simulated
+sim_ticks                                     8851106                       # Number of ticks simulated
+final_tick                                    8851106                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_tick_rate                                 160889                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 306216                       # Number of bytes of host memory used
-host_seconds                                    53.86                       # Real time elapsed on the host
+host_tick_rate                                 251677                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 263028                       # Number of bytes of host memory used
+host_seconds                                    35.17                       # Real time elapsed on the host
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                             1                       # Clock period in ticks
 system.ruby.clk_domain.clock                        1                       # Clock period in ticks
 system.ruby.delayHist::bucket_size                  4                       # delay histogram for all message
 system.ruby.delayHist::max_bucket                  39                       # delay histogram for all message
-system.ruby.delayHist::samples                1237687                       # delay histogram for all message
-system.ruby.delayHist::mean                  0.014190                       # delay histogram for all message
-system.ruby.delayHist::stdev                 0.298328                       # delay histogram for all message
-system.ruby.delayHist                    |     1235151     99.80%     99.80% |        1617      0.13%     99.93% |         897      0.07%    100.00% |           6      0.00%    100.00% |          12      0.00%    100.00% |           3      0.00%    100.00% |           1      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for all message
-system.ruby.delayHist::total                  1237687                       # delay histogram for all message
+system.ruby.delayHist::samples                1264357                       # delay histogram for all message
+system.ruby.delayHist::mean                  0.014702                       # delay histogram for all message
+system.ruby.delayHist::stdev                 0.302971                       # delay histogram for all message
+system.ruby.delayHist                    |     1261652     99.79%     99.79% |        1743      0.14%     99.92% |         940      0.07%    100.00% |           5      0.00%    100.00% |          13      0.00%    100.00% |           2      0.00%    100.00% |           2      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for all message
+system.ruby.delayHist::total                  1264357                       # delay histogram for all message
 system.ruby.outstanding_req_hist::bucket_size            2                      
 system.ruby.outstanding_req_hist::max_bucket           19                      
-system.ruby.outstanding_req_hist::samples       617680                      
-system.ruby.outstanding_req_hist::mean      15.998443                      
-system.ruby.outstanding_req_hist::gmean     15.997160                      
-system.ruby.outstanding_req_hist::stdev      0.126732                      
-system.ruby.outstanding_req_hist         |           8      0.00%      0.00% |          16      0.00%      0.00% |          16      0.00%      0.01% |          16      0.00%      0.01% |          16      0.00%      0.01% |          16      0.00%      0.01% |          16      0.00%      0.02% |          18      0.00%      0.02% |      617558     99.98%    100.00% |           0      0.00%    100.00%
-system.ruby.outstanding_req_hist::total        617680                      
+system.ruby.outstanding_req_hist::samples       630979                      
+system.ruby.outstanding_req_hist::mean      15.998479                      
+system.ruby.outstanding_req_hist::gmean     15.997223                      
+system.ruby.outstanding_req_hist::stdev      0.125377                      
+system.ruby.outstanding_req_hist         |           8      0.00%      0.00% |          16      0.00%      0.00% |          16      0.00%      0.01% |          16      0.00%      0.01% |          16      0.00%      0.01% |          16      0.00%      0.01% |          16      0.00%      0.02% |          16      0.00%      0.02% |      630859     99.98%    100.00% |           0      0.00%    100.00%
+system.ruby.outstanding_req_hist::total        630979                      
 system.ruby.latency_hist::bucket_size             512                      
 system.ruby.latency_hist::max_bucket             5119                      
-system.ruby.latency_hist::samples              617552                      
-system.ruby.latency_hist::mean            1795.769022                      
-system.ruby.latency_hist::gmean           1749.288930                      
-system.ruby.latency_hist::stdev            410.975839                      
-system.ruby.latency_hist                 |          49      0.01%      0.01% |        8521      1.38%      1.39% |      161856     26.21%     27.60% |      292941     47.44%     75.03% |      127050     20.57%     95.61% |       24164      3.91%     99.52% |        2669      0.43%     99.95% |         258      0.04%     99.99% |          42      0.01%    100.00% |           2      0.00%    100.00%
-system.ruby.latency_hist::total                617552                      
+system.ruby.latency_hist::samples              630851                      
+system.ruby.latency_hist::mean            1795.719672                      
+system.ruby.latency_hist::gmean           1748.933148                      
+system.ruby.latency_hist::stdev            412.147444                      
+system.ruby.latency_hist                 |          49      0.01%      0.01% |        8914      1.41%      1.42% |      165687     26.26%     27.68% |      297783     47.20%     74.89% |      130737     20.72%     95.61% |       24608      3.90%     99.51% |        2780      0.44%     99.95% |         265      0.04%    100.00% |          24      0.00%    100.00% |           4      0.00%    100.00%
+system.ruby.latency_hist::total                630851                      
 system.ruby.miss_latency_hist::bucket_size          512                      
 system.ruby.miss_latency_hist::max_bucket         5119                      
-system.ruby.miss_latency_hist::samples         617552                      
-system.ruby.miss_latency_hist::mean       1795.769022                      
-system.ruby.miss_latency_hist::gmean      1749.288930                      
-system.ruby.miss_latency_hist::stdev       410.975839                      
-system.ruby.miss_latency_hist            |          49      0.01%      0.01% |        8521      1.38%      1.39% |      161856     26.21%     27.60% |      292941     47.44%     75.03% |      127050     20.57%     95.61% |       24164      3.91%     99.52% |        2669      0.43%     99.95% |         258      0.04%     99.99% |          42      0.01%    100.00% |           2      0.00%    100.00%
-system.ruby.miss_latency_hist::total           617552                      
-system.ruby.L1Cache.incomplete_times             8208                      
-system.ruby.Directory.incomplete_times         609337                      
+system.ruby.miss_latency_hist::samples         630851                      
+system.ruby.miss_latency_hist::mean       1795.719672                      
+system.ruby.miss_latency_hist::gmean      1748.933148                      
+system.ruby.miss_latency_hist::stdev       412.147444                      
+system.ruby.miss_latency_hist            |          49      0.01%      0.01% |        8914      1.41%      1.42% |      165687     26.26%     27.68% |      297783     47.20%     74.89% |      130737     20.72%     95.61% |       24608      3.90%     99.51% |        2780      0.44%     99.95% |         265      0.04%    100.00% |          24      0.00%    100.00% |           4      0.00%    100.00%
+system.ruby.miss_latency_hist::total           630851                      
+system.ruby.L1Cache.incomplete_times             8485                      
+system.ruby.Directory.incomplete_times         622362                      
 system.ruby.l1_cntrl4.cacheMemory.demand_hits            0                       # Number of cache demand hits
-system.ruby.l1_cntrl4.cacheMemory.demand_misses        77331                       # Number of cache demand misses
-system.ruby.l1_cntrl4.cacheMemory.demand_accesses        77331                       # Number of cache demand accesses
+system.ruby.l1_cntrl4.cacheMemory.demand_misses        78801                       # Number of cache demand misses
+system.ruby.l1_cntrl4.cacheMemory.demand_accesses        78801                       # Number of cache demand accesses
 system.ruby.l1_cntrl5.cacheMemory.demand_hits            0                       # Number of cache demand hits
-system.ruby.l1_cntrl5.cacheMemory.demand_misses        77389                       # Number of cache demand misses
-system.ruby.l1_cntrl5.cacheMemory.demand_accesses        77389                       # Number of cache demand accesses
+system.ruby.l1_cntrl5.cacheMemory.demand_misses        78712                       # Number of cache demand misses
+system.ruby.l1_cntrl5.cacheMemory.demand_accesses        78712                       # Number of cache demand accesses
 system.ruby.l1_cntrl6.cacheMemory.demand_hits            0                       # Number of cache demand hits
-system.ruby.l1_cntrl6.cacheMemory.demand_misses        77354                       # Number of cache demand misses
-system.ruby.l1_cntrl6.cacheMemory.demand_accesses        77354                       # Number of cache demand accesses
+system.ruby.l1_cntrl6.cacheMemory.demand_misses        78682                       # Number of cache demand misses
+system.ruby.l1_cntrl6.cacheMemory.demand_accesses        78682                       # Number of cache demand accesses
 system.ruby.l1_cntrl7.cacheMemory.demand_hits            0                       # Number of cache demand hits
-system.ruby.l1_cntrl7.cacheMemory.demand_misses        77281                       # Number of cache demand misses
-system.ruby.l1_cntrl7.cacheMemory.demand_accesses        77281                       # Number of cache demand accesses
+system.ruby.l1_cntrl7.cacheMemory.demand_misses        79132                       # Number of cache demand misses
+system.ruby.l1_cntrl7.cacheMemory.demand_accesses        79132                       # Number of cache demand accesses
 system.ruby.l1_cntrl0.cacheMemory.demand_hits            0                       # Number of cache demand hits
-system.ruby.l1_cntrl0.cacheMemory.demand_misses        77377                       # Number of cache demand misses
-system.ruby.l1_cntrl0.cacheMemory.demand_accesses        77377                       # Number of cache demand accesses
+system.ruby.l1_cntrl0.cacheMemory.demand_misses        78906                       # Number of cache demand misses
+system.ruby.l1_cntrl0.cacheMemory.demand_accesses        78906                       # Number of cache demand accesses
 system.ruby.l1_cntrl1.cacheMemory.demand_hits            0                       # Number of cache demand hits
-system.ruby.l1_cntrl1.cacheMemory.demand_misses        77193                       # Number of cache demand misses
-system.ruby.l1_cntrl1.cacheMemory.demand_accesses        77193                       # Number of cache demand accesses
+system.ruby.l1_cntrl1.cacheMemory.demand_misses        78862                       # Number of cache demand misses
+system.ruby.l1_cntrl1.cacheMemory.demand_accesses        78862                       # Number of cache demand accesses
 system.ruby.l1_cntrl2.cacheMemory.demand_hits            0                       # Number of cache demand hits
-system.ruby.l1_cntrl2.cacheMemory.demand_misses        76824                       # Number of cache demand misses
-system.ruby.l1_cntrl2.cacheMemory.demand_accesses        76824                       # Number of cache demand accesses
+system.ruby.l1_cntrl2.cacheMemory.demand_misses        78717                       # Number of cache demand misses
+system.ruby.l1_cntrl2.cacheMemory.demand_accesses        78717                       # Number of cache demand accesses
 system.ruby.l1_cntrl3.cacheMemory.demand_hits            0                       # Number of cache demand hits
-system.ruby.l1_cntrl3.cacheMemory.demand_misses        76825                       # Number of cache demand misses
-system.ruby.l1_cntrl3.cacheMemory.demand_accesses        76825                       # Number of cache demand accesses
-system.ruby.network.routers0.percent_links_utilized     4.474669                      
-system.ruby.network.routers0.msg_count.Control::2        77377                      
-system.ruby.network.routers0.msg_count.Data::2        76667                      
-system.ruby.network.routers0.msg_count.Response_Data::4        78423                      
-system.ruby.network.routers0.msg_count.Writeback_Control::3        77713                      
-system.ruby.network.routers0.msg_bytes.Control::2       619016                      
-system.ruby.network.routers0.msg_bytes.Data::2      5520024                      
-system.ruby.network.routers0.msg_bytes.Response_Data::4      5646456                      
-system.ruby.network.routers0.msg_bytes.Writeback_Control::3       621704                      
-system.ruby.network.routers1.percent_links_utilized     4.463498                      
-system.ruby.network.routers1.msg_count.Control::2        77193                      
-system.ruby.network.routers1.msg_count.Data::2        76469                      
-system.ruby.network.routers1.msg_count.Response_Data::4        78234                      
-system.ruby.network.routers1.msg_count.Writeback_Control::3        77508                      
-system.ruby.network.routers1.msg_bytes.Control::2       617544                      
-system.ruby.network.routers1.msg_bytes.Data::2      5505768                      
-system.ruby.network.routers1.msg_bytes.Response_Data::4      5632848                      
-system.ruby.network.routers1.msg_bytes.Writeback_Control::3       620064                      
-system.ruby.network.routers2.percent_links_utilized     4.442205                      
-system.ruby.network.routers2.msg_count.Control::2        76824                      
-system.ruby.network.routers2.msg_count.Data::2        76104                      
-system.ruby.network.routers2.msg_count.Response_Data::4        77861                      
-system.ruby.network.routers2.msg_count.Writeback_Control::3        77139                      
-system.ruby.network.routers2.msg_bytes.Control::2       614592                      
-system.ruby.network.routers2.msg_bytes.Data::2      5479488                      
-system.ruby.network.routers2.msg_bytes.Response_Data::4      5605992                      
-system.ruby.network.routers2.msg_bytes.Writeback_Control::3       617112                      
-system.ruby.network.routers3.percent_links_utilized     4.442687                      
-system.ruby.network.routers3.msg_count.Control::2        76823                      
-system.ruby.network.routers3.msg_count.Data::2        76096                      
-system.ruby.network.routers3.msg_count.Response_Data::4        77886                      
-system.ruby.network.routers3.msg_count.Writeback_Control::3        77157                      
-system.ruby.network.routers3.msg_bytes.Control::2       614584                      
-system.ruby.network.routers3.msg_bytes.Data::2      5478912                      
-system.ruby.network.routers3.msg_bytes.Response_Data::4      5607792                      
-system.ruby.network.routers3.msg_bytes.Writeback_Control::3       617256                      
-system.ruby.network.routers4.percent_links_utilized     4.471582                      
-system.ruby.network.routers4.msg_count.Control::2        77331                      
-system.ruby.network.routers4.msg_count.Data::2        76659                      
-system.ruby.network.routers4.msg_count.Response_Data::4        78324                      
-system.ruby.network.routers4.msg_count.Writeback_Control::3        77652                      
-system.ruby.network.routers4.msg_bytes.Control::2       618648                      
-system.ruby.network.routers4.msg_bytes.Data::2      5519448                      
-system.ruby.network.routers4.msg_bytes.Response_Data::4      5639328                      
-system.ruby.network.routers4.msg_bytes.Writeback_Control::3       621216                      
-system.ruby.network.routers5.percent_links_utilized     4.475356                      
-system.ruby.network.routers5.msg_count.Control::2        77389                      
-system.ruby.network.routers5.msg_count.Data::2        76728                      
-system.ruby.network.routers5.msg_count.Response_Data::4        78386                      
-system.ruby.network.routers5.msg_count.Writeback_Control::3        77723                      
-system.ruby.network.routers5.msg_bytes.Control::2       619112                      
-system.ruby.network.routers5.msg_bytes.Data::2      5524416                      
-system.ruby.network.routers5.msg_bytes.Response_Data::4      5643792                      
-system.ruby.network.routers5.msg_bytes.Writeback_Control::3       621784                      
-system.ruby.network.routers6.percent_links_utilized     4.472419                      
-system.ruby.network.routers6.msg_count.Control::2        77354                      
-system.ruby.network.routers6.msg_count.Data::2        76662                      
-system.ruby.network.routers6.msg_count.Response_Data::4        78350                      
-system.ruby.network.routers6.msg_count.Writeback_Control::3        77658                      
-system.ruby.network.routers6.msg_bytes.Control::2       618832                      
-system.ruby.network.routers6.msg_bytes.Data::2      5519664                      
-system.ruby.network.routers6.msg_bytes.Response_Data::4      5641200                      
-system.ruby.network.routers6.msg_bytes.Writeback_Control::3       621264                      
-system.ruby.network.routers7.percent_links_utilized     4.468123                      
-system.ruby.network.routers7.msg_count.Control::2        77277                      
-system.ruby.network.routers7.msg_count.Data::2        76568                      
-system.ruby.network.routers7.msg_count.Response_Data::4        78296                      
-system.ruby.network.routers7.msg_count.Writeback_Control::3        77585                      
-system.ruby.network.routers7.msg_bytes.Control::2       618216                      
-system.ruby.network.routers7.msg_bytes.Data::2      5512896                      
-system.ruby.network.routers7.msg_bytes.Response_Data::4      5637312                      
-system.ruby.network.routers7.msg_bytes.Writeback_Control::3       620680                      
+system.ruby.l1_cntrl3.cacheMemory.demand_misses        79057                       # Number of cache demand misses
+system.ruby.l1_cntrl3.cacheMemory.demand_accesses        79057                       # Number of cache demand accesses
+system.ruby.network.routers0.percent_links_utilized     4.466411                      
+system.ruby.network.routers0.msg_count.Control::2        78906                      
+system.ruby.network.routers0.msg_count.Data::2        78209                      
+system.ruby.network.routers0.msg_count.Response_Data::4        79922                      
+system.ruby.network.routers0.msg_count.Writeback_Control::3        79222                      
+system.ruby.network.routers0.msg_bytes.Control::2       631248                      
+system.ruby.network.routers0.msg_bytes.Data::2      5631048                      
+system.ruby.network.routers0.msg_bytes.Response_Data::4      5754384                      
+system.ruby.network.routers0.msg_bytes.Writeback_Control::3       633776                      
+system.ruby.network.routers1.percent_links_utilized     4.464072                      
+system.ruby.network.routers1.msg_count.Control::2        78862                      
+system.ruby.network.routers1.msg_count.Data::2        78116                      
+system.ruby.network.routers1.msg_count.Response_Data::4        79932                      
+system.ruby.network.routers1.msg_count.Writeback_Control::3        79185                      
+system.ruby.network.routers1.msg_bytes.Control::2       630896                      
+system.ruby.network.routers1.msg_bytes.Data::2      5624352                      
+system.ruby.network.routers1.msg_bytes.Response_Data::4      5755104                      
+system.ruby.network.routers1.msg_bytes.Writeback_Control::3       633480                      
+system.ruby.network.routers2.percent_links_utilized     4.456923                      
+system.ruby.network.routers2.msg_count.Control::2        78717                      
+system.ruby.network.routers2.msg_count.Data::2        78011                      
+system.ruby.network.routers2.msg_count.Response_Data::4        79784                      
+system.ruby.network.routers2.msg_count.Writeback_Control::3        79076                      
+system.ruby.network.routers2.msg_bytes.Control::2       629736                      
+system.ruby.network.routers2.msg_bytes.Data::2      5616792                      
+system.ruby.network.routers2.msg_bytes.Response_Data::4      5744448                      
+system.ruby.network.routers2.msg_bytes.Writeback_Control::3       632608                      
+system.ruby.network.routers3.percent_links_utilized     4.475147                      
+system.ruby.network.routers3.msg_count.Control::2        79057                      
+system.ruby.network.routers3.msg_count.Data::2        78335                      
+system.ruby.network.routers3.msg_count.Response_Data::4        80105                      
+system.ruby.network.routers3.msg_count.Writeback_Control::3        79383                      
+system.ruby.network.routers3.msg_bytes.Control::2       632456                      
+system.ruby.network.routers3.msg_bytes.Data::2      5640120                      
+system.ruby.network.routers3.msg_bytes.Response_Data::4      5767560                      
+system.ruby.network.routers3.msg_bytes.Writeback_Control::3       635064                      
+system.ruby.network.routers4.percent_links_utilized     4.460937                      
+system.ruby.network.routers4.msg_count.Control::2        78801                      
+system.ruby.network.routers4.msg_count.Data::2        78061                      
+system.ruby.network.routers4.msg_count.Response_Data::4        79876                      
+system.ruby.network.routers4.msg_count.Writeback_Control::3        79135                      
+system.ruby.network.routers4.msg_bytes.Control::2       630408                      
+system.ruby.network.routers4.msg_bytes.Data::2      5620392                      
+system.ruby.network.routers4.msg_bytes.Response_Data::4      5751072                      
+system.ruby.network.routers4.msg_bytes.Writeback_Control::3       633080                      
+system.ruby.network.routers5.percent_links_utilized     4.455593                      
+system.ruby.network.routers5.msg_count.Control::2        78712                      
+system.ruby.network.routers5.msg_count.Data::2        77972                      
+system.ruby.network.routers5.msg_count.Response_Data::4        79776                      
+system.ruby.network.routers5.msg_count.Writeback_Control::3        79033                      
+system.ruby.network.routers5.msg_bytes.Control::2       629696                      
+system.ruby.network.routers5.msg_bytes.Data::2      5613984                      
+system.ruby.network.routers5.msg_bytes.Response_Data::4      5743872                      
+system.ruby.network.routers5.msg_bytes.Writeback_Control::3       632264                      
+system.ruby.network.routers6.percent_links_utilized     4.454384                      
+system.ruby.network.routers6.msg_count.Control::2        78682                      
+system.ruby.network.routers6.msg_count.Data::2        77916                      
+system.ruby.network.routers6.msg_count.Response_Data::4        79789                      
+system.ruby.network.routers6.msg_count.Writeback_Control::3        79022                      
+system.ruby.network.routers6.msg_bytes.Control::2       629456                      
+system.ruby.network.routers6.msg_bytes.Data::2      5609952                      
+system.ruby.network.routers6.msg_bytes.Response_Data::4      5744808                      
+system.ruby.network.routers6.msg_bytes.Writeback_Control::3       632176                      
+system.ruby.network.routers7.percent_links_utilized     4.479124                      
+system.ruby.network.routers7.msg_count.Control::2        79132                      
+system.ruby.network.routers7.msg_count.Data::2        78429                      
+system.ruby.network.routers7.msg_count.Response_Data::4        80152                      
+system.ruby.network.routers7.msg_count.Writeback_Control::3        79450                      
+system.ruby.network.routers7.msg_bytes.Control::2       633056                      
+system.ruby.network.routers7.msg_bytes.Data::2      5646888                      
+system.ruby.network.routers7.msg_bytes.Response_Data::4      5770944                      
+system.ruby.network.routers7.msg_bytes.Writeback_Control::3       635600                      
 system.ruby.memctrl_clk_domain.clock                3                       # Clock period in ticks
-system.ruby.dir_cntrl0.memBuffer.memReq       1218678                       # Total number of memory requests
-system.ruby.dir_cntrl0.memBuffer.memRead       609346                       # Number of memory reads
-system.ruby.dir_cntrl0.memBuffer.memWrite       609308                       # Number of memory writes
-system.ruby.dir_cntrl0.memBuffer.memRefresh        60173                       # Number of memory refreshes
-system.ruby.dir_cntrl0.memBuffer.memWaitCycles     45858057                       # Delay stalled at the head of the bank queue
-system.ruby.dir_cntrl0.memBuffer.memInputQ      1522193                       # Delay in the input queue
-system.ruby.dir_cntrl0.memBuffer.memBankQ     40100008                       # Delay behind the head of the bank queue
-system.ruby.dir_cntrl0.memBuffer.totalStalls     87480258                       # Total number of stall cycles
-system.ruby.dir_cntrl0.memBuffer.stallsPerReq    71.782914                       # Expected number of stall cycles per request
-system.ruby.dir_cntrl0.memBuffer.memBankBusy      7076344                       # memory stalls due to busy bank
-system.ruby.dir_cntrl0.memBuffer.memBusBusy     12585722                       # memory stalls due to busy bus
-system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy      4642017                       # memory stalls due to read write turnaround
-system.ruby.dir_cntrl0.memBuffer.memDataBusBusy      1076094                       # memory stalls due to read read turnaround
-system.ruby.dir_cntrl0.memBuffer.memArbWait      9195209                       # memory stalls due to arbitration
-system.ruby.dir_cntrl0.memBuffer.memNotOld     11282671                       # memory stalls due to anti starvation
-system.ruby.dir_cntrl0.memBuffer.memBankCount |       38404      3.15%      3.15% |       37646      3.09%      6.24% |       38381      3.15%      9.39% |       38273      3.14%     12.53% |       38109      3.13%     15.66% |       38021      3.12%     18.78% |       38580      3.17%     21.94% |       38357      3.15%     25.09% |       38057      3.12%     28.21% |       38004      3.12%     31.33% |       38123      3.13%     34.46% |       37658      3.09%     37.55% |       37751      3.10%     40.65% |       38546      3.16%     43.81% |       37560      3.08%     46.89% |       38514      3.16%     50.05% |       38232      3.14%     53.19% |       38045      3.12%     56.31% |       38749      3.18%     59.49% |       38589      3.17%     62.66% |       38066      3.12%     65.78% |       37687      3.09%     68.87% |       38032      3.12%     71.99% |       38060      3.12%     75.12% |       37804      3.10%     78.22% |       38206      3.14%     81.35% |       37726      3.10%     84.45% |       38148      3.13%     87.58% |       37682      3.09%     90.67% |       38049      3.12%     93.79% |       37701      3.09%     96.89% |       37918      3.11%    100.00% # Number of accesses per bank
-system.ruby.dir_cntrl0.memBuffer.memBankCount::total      1218678                       # Number of accesses per bank
-system.ruby.network.routers8.percent_links_utilized    35.284146                      
-system.ruby.network.routers8.msg_count.Control::2       617562                      
-system.ruby.network.routers8.msg_count.Data::2       611948                      
-system.ruby.network.routers8.msg_count.Response_Data::4       609345                      
-system.ruby.network.routers8.msg_count.Writeback_Control::3       620135                      
-system.ruby.network.routers8.msg_bytes.Control::2      4940496                      
-system.ruby.network.routers8.msg_bytes.Data::2     44060256                      
-system.ruby.network.routers8.msg_bytes.Response_Data::4     43872840                      
-system.ruby.network.routers8.msg_bytes.Writeback_Control::3      4961080                      
-system.ruby.network.routers9.percent_links_utilized     7.888285                      
-system.ruby.network.routers9.msg_count.Control::2       617562                      
-system.ruby.network.routers9.msg_count.Data::2       611948                      
-system.ruby.network.routers9.msg_count.Response_Data::4       617553                      
-system.ruby.network.routers9.msg_count.Writeback_Control::3       620135                      
-system.ruby.network.routers9.msg_bytes.Control::2      4940496                      
-system.ruby.network.routers9.msg_bytes.Data::2     44060256                      
-system.ruby.network.routers9.msg_bytes.Response_Data::4     44463816                      
-system.ruby.network.routers9.msg_bytes.Writeback_Control::3      4961080                      
-system.ruby.network.msg_count.Control         1852692                      
-system.ruby.network.msg_count.Data            1835849                      
-system.ruby.network.msg_count.Response_Data      1852658                      
-system.ruby.network.msg_count.Writeback_Control      1860405                      
-system.ruby.network.msg_byte.Control         14821536                      
-system.ruby.network.msg_byte.Data           132181128                      
-system.ruby.network.msg_byte.Response_Data    133391376                      
-system.ruby.network.msg_byte.Writeback_Control     14883240                      
+system.ruby.dir_cntrl0.memBuffer.memReq       1244736                       # Total number of memory requests
+system.ruby.dir_cntrl0.memBuffer.memRead       622369                       # Number of memory reads
+system.ruby.dir_cntrl0.memBuffer.memWrite       622327                       # Number of memory writes
+system.ruby.dir_cntrl0.memBuffer.memRefresh        61466                       # Number of memory refreshes
+system.ruby.dir_cntrl0.memBuffer.memWaitCycles     46843919                       # Delay stalled at the head of the bank queue
+system.ruby.dir_cntrl0.memBuffer.memInputQ      1544719                       # Delay in the input queue
+system.ruby.dir_cntrl0.memBuffer.memBankQ     40914855                       # Delay behind the head of the bank queue
+system.ruby.dir_cntrl0.memBuffer.totalStalls     89303493                       # Total number of stall cycles
+system.ruby.dir_cntrl0.memBuffer.stallsPerReq    71.744927                       # Expected number of stall cycles per request
+system.ruby.dir_cntrl0.memBuffer.memBankBusy      7226521                       # memory stalls due to busy bank
+system.ruby.dir_cntrl0.memBuffer.memBusBusy     12850865                       # memory stalls due to busy bus
+system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy      4733152                       # memory stalls due to read write turnaround
+system.ruby.dir_cntrl0.memBuffer.memDataBusBusy      1096174                       # memory stalls due to read read turnaround
+system.ruby.dir_cntrl0.memBuffer.memArbWait      9395532                       # memory stalls due to arbitration
+system.ruby.dir_cntrl0.memBuffer.memNotOld     11541675                       # memory stalls due to anti starvation
+system.ruby.dir_cntrl0.memBuffer.memBankCount |       39236      3.15%      3.15% |       39187      3.15%      6.30% |       38854      3.12%      9.42% |       39063      3.14%     12.56% |       38454      3.09%     15.65% |       39210      3.15%     18.80% |       39083      3.14%     21.94% |       39085      3.14%     25.08% |       38983      3.13%     28.21% |       39280      3.16%     31.37% |       39090      3.14%     34.51% |       38371      3.08%     37.59% |       38752      3.11%     40.70% |       38808      3.12%     43.82% |       39073      3.14%     46.96% |       38752      3.11%     50.07% |       38633      3.10%     53.18% |       39174      3.15%     56.32% |       38907      3.13%     59.45% |       39057      3.14%     62.59% |       38471      3.09%     65.68% |       38694      3.11%     68.79% |       38561      3.10%     71.88% |       38553      3.10%     74.98% |       38571      3.10%     78.08% |       38875      3.12%     81.20% |       39085      3.14%     84.34% |       39006      3.13%     87.48% |       39194      3.15%     90.63% |       38693      3.11%     93.74% |       38713      3.11%     96.85% |       39268      3.15%    100.00% # Number of accesses per bank
+system.ruby.dir_cntrl0.memBuffer.memBankCount::total      1244736                       # Number of accesses per bank
+system.ruby.network.routers8.percent_links_utilized    35.281218                      
+system.ruby.network.routers8.msg_count.Control::2       630869                      
+system.ruby.network.routers8.msg_count.Data::2       625049                      
+system.ruby.network.routers8.msg_count.Response_Data::4       622367                      
+system.ruby.network.routers8.msg_count.Writeback_Control::3       633506                      
+system.ruby.network.routers8.msg_bytes.Control::2      5046952                      
+system.ruby.network.routers8.msg_bytes.Data::2     45003528                      
+system.ruby.network.routers8.msg_bytes.Response_Data::4     44810424                      
+system.ruby.network.routers8.msg_bytes.Writeback_Control::3      5068048                      
+system.ruby.network.routers9.percent_links_utilized     7.888201                      
+system.ruby.network.routers9.msg_count.Control::2       630869                      
+system.ruby.network.routers9.msg_count.Data::2       625049                      
+system.ruby.network.routers9.msg_count.Response_Data::4       630851                      
+system.ruby.network.routers9.msg_count.Writeback_Control::3       633506                      
+system.ruby.network.routers9.msg_bytes.Control::2      5046952                      
+system.ruby.network.routers9.msg_bytes.Data::2     45003528                      
+system.ruby.network.routers9.msg_bytes.Response_Data::4     45421272                      
+system.ruby.network.routers9.msg_bytes.Writeback_Control::3      5068048                      
+system.ruby.network.msg_count.Control         1892607                      
+system.ruby.network.msg_count.Data            1875147                      
+system.ruby.network.msg_count.Response_Data      1892554                      
+system.ruby.network.msg_count.Writeback_Control      1900518                      
+system.ruby.network.msg_byte.Control         15140856                      
+system.ruby.network.msg_byte.Data           135010584                      
+system.ruby.network.msg_byte.Response_Data    136263888                      
+system.ruby.network.msg_byte.Writeback_Control     15204144                      
 system.funcbus.throughput                           0                       # Throughput (bytes/s)
 system.funcbus.data_through_bus                     0                       # Total data (bytes)
 system.cpu_clk_domain.clock                         1                       # Clock period in ticks
-system.cpu0.num_reads                           99885                       # number of read accesses completed
-system.cpu0.num_writes                          54375                       # number of write accesses completed
+system.cpu0.num_reads                           99672                       # number of read accesses completed
+system.cpu0.num_writes                          55456                       # number of write accesses completed
 system.cpu0.num_copies                              0                       # number of copy accesses completed
-system.cpu1.num_reads                           99537                       # number of read accesses completed
-system.cpu1.num_writes                          53839                       # number of write accesses completed
+system.cpu1.num_reads                           99787                       # number of read accesses completed
+system.cpu1.num_writes                          55562                       # number of write accesses completed
 system.cpu1.num_copies                              0                       # number of copy accesses completed
-system.cpu2.num_reads                           99297                       # number of read accesses completed
-system.cpu2.num_writes                          53929                       # number of write accesses completed
+system.cpu2.num_reads                           99865                       # number of read accesses completed
+system.cpu2.num_writes                          55847                       # number of write accesses completed
 system.cpu2.num_copies                              0                       # number of copy accesses completed
-system.cpu3.num_reads                           99124                       # number of read accesses completed
-system.cpu3.num_writes                          54072                       # number of write accesses completed
+system.cpu3.num_reads                           99798                       # number of read accesses completed
+system.cpu3.num_writes                          55621                       # number of write accesses completed
 system.cpu3.num_copies                              0                       # number of copy accesses completed
-system.cpu4.num_reads                           99259                       # number of read accesses completed
-system.cpu4.num_writes                          54427                       # number of write accesses completed
+system.cpu4.num_reads                           99867                       # number of read accesses completed
+system.cpu4.num_writes                          55560                       # number of write accesses completed
 system.cpu4.num_copies                              0                       # number of copy accesses completed
-system.cpu5.num_reads                           99389                       # number of read accesses completed
-system.cpu5.num_writes                          54074                       # number of write accesses completed
+system.cpu5.num_reads                           99021                       # number of read accesses completed
+system.cpu5.num_writes                          55459                       # number of write accesses completed
 system.cpu5.num_copies                              0                       # number of copy accesses completed
-system.cpu6.num_reads                           99658                       # number of read accesses completed
-system.cpu6.num_writes                          54033                       # number of write accesses completed
+system.cpu6.num_reads                           99570                       # number of read accesses completed
+system.cpu6.num_writes                          55395                       # number of write accesses completed
 system.cpu6.num_copies                              0                       # number of copy accesses completed
 system.cpu7.num_reads                          100000                       # number of read accesses completed
-system.cpu7.num_writes                          53796                       # number of write accesses completed
+system.cpu7.num_writes                          56251                       # number of write accesses completed
 system.cpu7.num_copies                              0                       # number of copy accesses completed
-system.ruby.network.routers0.throttle0.link_utilization     4.466810                      
-system.ruby.network.routers0.throttle0.msg_count.Response_Data::4        77375                      
-system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3        77713                      
-system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4      5571000                      
-system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3       621704                      
-system.ruby.network.routers0.throttle1.link_utilization     4.482529                      
-system.ruby.network.routers0.throttle1.msg_count.Control::2        77377                      
-system.ruby.network.routers0.throttle1.msg_count.Data::2        76667                      
-system.ruby.network.routers0.throttle1.msg_count.Response_Data::4         1048                      
-system.ruby.network.routers0.throttle1.msg_bytes.Control::2       619016                      
-system.ruby.network.routers0.throttle1.msg_bytes.Data::2      5520024                      
-system.ruby.network.routers0.throttle1.msg_bytes.Response_Data::4        75456                      
-system.ruby.network.routers1.throttle0.link_utilization     4.456123                      
-system.ruby.network.routers1.throttle0.msg_count.Response_Data::4        77192                      
-system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::3        77508                      
-system.ruby.network.routers1.throttle0.msg_bytes.Response_Data::4      5557824                      
-system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::3       620064                      
-system.ruby.network.routers1.throttle1.link_utilization     4.470872                      
-system.ruby.network.routers1.throttle1.msg_count.Control::2        77193                      
-system.ruby.network.routers1.throttle1.msg_count.Data::2        76469                      
-system.ruby.network.routers1.throttle1.msg_count.Response_Data::4         1042                      
-system.ruby.network.routers1.throttle1.msg_bytes.Control::2       617544                      
-system.ruby.network.routers1.throttle1.msg_bytes.Data::2      5505768                      
-system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4        75024                      
-system.ruby.network.routers2.throttle0.link_utilization     4.434727                      
-system.ruby.network.routers2.throttle0.msg_count.Response_Data::4        76821                      
-system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3        77139                      
-system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4      5531112                      
-system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3       617112                      
-system.ruby.network.routers2.throttle1.link_utilization     4.449683                      
-system.ruby.network.routers2.throttle1.msg_count.Control::2        76824                      
-system.ruby.network.routers2.throttle1.msg_count.Data::2        76104                      
-system.ruby.network.routers2.throttle1.msg_count.Response_Data::4         1040                      
-system.ruby.network.routers2.throttle1.msg_bytes.Control::2       614592                      
-system.ruby.network.routers2.throttle1.msg_bytes.Data::2      5479488                      
-system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::4        74880                      
-system.ruby.network.routers3.throttle0.link_utilization     4.434830                      
-system.ruby.network.routers3.throttle0.msg_count.Response_Data::4        76821                      
-system.ruby.network.routers3.throttle0.msg_count.Writeback_Control::3        77157                      
-system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::4      5531112                      
-system.ruby.network.routers3.throttle0.msg_bytes.Writeback_Control::3       617256                      
-system.ruby.network.routers3.throttle1.link_utilization     4.450543                      
-system.ruby.network.routers3.throttle1.msg_count.Control::2        76823                      
-system.ruby.network.routers3.throttle1.msg_count.Data::2        76096                      
-system.ruby.network.routers3.throttle1.msg_count.Response_Data::4         1065                      
-system.ruby.network.routers3.throttle1.msg_bytes.Control::2       614584                      
-system.ruby.network.routers3.throttle1.msg_bytes.Data::2      5478912                      
-system.ruby.network.routers3.throttle1.msg_bytes.Response_Data::4        76680                      
-system.ruby.network.routers4.throttle0.link_utilization     4.464069                      
-system.ruby.network.routers4.throttle0.msg_count.Response_Data::4        77329                      
-system.ruby.network.routers4.throttle0.msg_count.Writeback_Control::3        77652                      
-system.ruby.network.routers4.throttle0.msg_bytes.Response_Data::4      5567688                      
-system.ruby.network.routers4.throttle0.msg_bytes.Writeback_Control::3       621216                      
-system.ruby.network.routers4.throttle1.link_utilization     4.479095                      
-system.ruby.network.routers4.throttle1.msg_count.Control::2        77331                      
-system.ruby.network.routers4.throttle1.msg_count.Data::2        76659                      
-system.ruby.network.routers4.throttle1.msg_count.Response_Data::4          995                      
-system.ruby.network.routers4.throttle1.msg_bytes.Control::2       618648                      
-system.ruby.network.routers4.throttle1.msg_bytes.Data::2      5519448                      
-system.ruby.network.routers4.throttle1.msg_bytes.Response_Data::4        71640                      
-system.ruby.network.routers5.throttle0.link_utilization     4.467387                      
-system.ruby.network.routers5.throttle0.msg_count.Response_Data::4        77385                      
-system.ruby.network.routers5.throttle0.msg_count.Writeback_Control::3        77723                      
-system.ruby.network.routers5.throttle0.msg_bytes.Response_Data::4      5571720                      
-system.ruby.network.routers5.throttle0.msg_bytes.Writeback_Control::3       621784                      
-system.ruby.network.routers5.throttle1.link_utilization     4.483325                      
-system.ruby.network.routers5.throttle1.msg_count.Control::2        77389                      
-system.ruby.network.routers5.throttle1.msg_count.Data::2        76728                      
-system.ruby.network.routers5.throttle1.msg_count.Response_Data::4         1001                      
-system.ruby.network.routers5.throttle1.msg_bytes.Control::2       619112                      
-system.ruby.network.routers5.throttle1.msg_bytes.Data::2      5524416                      
-system.ruby.network.routers5.throttle1.msg_bytes.Response_Data::4        72072                      
-system.ruby.network.routers6.throttle0.link_utilization     4.465298                      
-system.ruby.network.routers6.throttle0.msg_count.Response_Data::4        77352                      
-system.ruby.network.routers6.throttle0.msg_count.Writeback_Control::3        77658                      
-system.ruby.network.routers6.throttle0.msg_bytes.Response_Data::4      5569344                      
-system.ruby.network.routers6.throttle0.msg_bytes.Writeback_Control::3       621264                      
-system.ruby.network.routers6.throttle1.link_utilization     4.479540                      
-system.ruby.network.routers6.throttle1.msg_count.Control::2        77354                      
-system.ruby.network.routers6.throttle1.msg_count.Data::2        76662                      
-system.ruby.network.routers6.throttle1.msg_count.Response_Data::4          998                      
-system.ruby.network.routers6.throttle1.msg_bytes.Control::2       618832                      
-system.ruby.network.routers6.throttle1.msg_bytes.Data::2      5519664                      
-system.ruby.network.routers6.throttle1.msg_bytes.Response_Data::4        71856                      
-system.ruby.network.routers7.throttle0.link_utilization     4.460982                      
-system.ruby.network.routers7.throttle0.msg_count.Response_Data::4        77277                      
-system.ruby.network.routers7.throttle0.msg_count.Writeback_Control::3        77585                      
-system.ruby.network.routers7.throttle0.msg_bytes.Response_Data::4      5563944                      
-system.ruby.network.routers7.throttle0.msg_bytes.Writeback_Control::3       620680                      
-system.ruby.network.routers7.throttle1.link_utilization     4.475264                      
-system.ruby.network.routers7.throttle1.msg_count.Control::2        77277                      
-system.ruby.network.routers7.throttle1.msg_count.Data::2        76568                      
-system.ruby.network.routers7.throttle1.msg_count.Response_Data::4         1019                      
-system.ruby.network.routers7.throttle1.msg_bytes.Control::2       618216                      
-system.ruby.network.routers7.throttle1.msg_bytes.Data::2      5512896                      
-system.ruby.network.routers7.throttle1.msg_bytes.Response_Data::4        73368                      
-system.ruby.network.routers8.throttle0.link_utilization    35.344302                      
-system.ruby.network.routers8.throttle0.msg_count.Control::2       617562                      
-system.ruby.network.routers8.throttle0.msg_count.Data::2       611948                      
-system.ruby.network.routers8.throttle0.msg_bytes.Control::2      4940496                      
-system.ruby.network.routers8.throttle0.msg_bytes.Data::2     44060256                      
-system.ruby.network.routers8.throttle1.link_utilization    35.223989                      
-system.ruby.network.routers8.throttle1.msg_count.Response_Data::4       609345                      
-system.ruby.network.routers8.throttle1.msg_count.Writeback_Control::3       620135                      
-system.ruby.network.routers8.throttle1.msg_bytes.Response_Data::4     43872840                      
-system.ruby.network.routers8.throttle1.msg_bytes.Writeback_Control::3      4961080                      
-system.ruby.network.routers9.throttle0.link_utilization     4.466810                      
-system.ruby.network.routers9.throttle0.msg_count.Response_Data::4        77375                      
-system.ruby.network.routers9.throttle0.msg_count.Writeback_Control::3        77713                      
-system.ruby.network.routers9.throttle0.msg_bytes.Response_Data::4      5571000                      
-system.ruby.network.routers9.throttle0.msg_bytes.Writeback_Control::3       621704                      
-system.ruby.network.routers9.throttle1.link_utilization     4.456123                      
-system.ruby.network.routers9.throttle1.msg_count.Response_Data::4        77192                      
-system.ruby.network.routers9.throttle1.msg_count.Writeback_Control::3        77508                      
-system.ruby.network.routers9.throttle1.msg_bytes.Response_Data::4      5557824                      
-system.ruby.network.routers9.throttle1.msg_bytes.Writeback_Control::3       620064                      
-system.ruby.network.routers9.throttle2.link_utilization     4.434727                      
-system.ruby.network.routers9.throttle2.msg_count.Response_Data::4        76821                      
-system.ruby.network.routers9.throttle2.msg_count.Writeback_Control::3        77139                      
-system.ruby.network.routers9.throttle2.msg_bytes.Response_Data::4      5531112                      
-system.ruby.network.routers9.throttle2.msg_bytes.Writeback_Control::3       617112                      
-system.ruby.network.routers9.throttle3.link_utilization     4.434830                      
-system.ruby.network.routers9.throttle3.msg_count.Response_Data::4        76821                      
-system.ruby.network.routers9.throttle3.msg_count.Writeback_Control::3        77157                      
-system.ruby.network.routers9.throttle3.msg_bytes.Response_Data::4      5531112                      
-system.ruby.network.routers9.throttle3.msg_bytes.Writeback_Control::3       617256                      
-system.ruby.network.routers9.throttle4.link_utilization     4.464081                      
-system.ruby.network.routers9.throttle4.msg_count.Response_Data::4        77330                      
-system.ruby.network.routers9.throttle4.msg_count.Writeback_Control::3        77652                      
-system.ruby.network.routers9.throttle4.msg_bytes.Response_Data::4      5567760                      
-system.ruby.network.routers9.throttle4.msg_bytes.Writeback_Control::3       621216                      
-system.ruby.network.routers9.throttle5.link_utilization     4.467387                      
-system.ruby.network.routers9.throttle5.msg_count.Response_Data::4        77385                      
-system.ruby.network.routers9.throttle5.msg_count.Writeback_Control::3        77723                      
-system.ruby.network.routers9.throttle5.msg_bytes.Response_Data::4      5571720                      
-system.ruby.network.routers9.throttle5.msg_bytes.Writeback_Control::3       621784                      
-system.ruby.network.routers9.throttle6.link_utilization     4.465298                      
-system.ruby.network.routers9.throttle6.msg_count.Response_Data::4        77352                      
-system.ruby.network.routers9.throttle6.msg_count.Writeback_Control::3        77658                      
-system.ruby.network.routers9.throttle6.msg_bytes.Response_Data::4      5569344                      
-system.ruby.network.routers9.throttle6.msg_bytes.Writeback_Control::3       621264                      
-system.ruby.network.routers9.throttle7.link_utilization     4.460982                      
-system.ruby.network.routers9.throttle7.msg_count.Response_Data::4        77277                      
-system.ruby.network.routers9.throttle7.msg_count.Writeback_Control::3        77585                      
-system.ruby.network.routers9.throttle7.msg_bytes.Response_Data::4      5563944                      
-system.ruby.network.routers9.throttle7.msg_bytes.Writeback_Control::3       620680                      
-system.ruby.network.routers9.throttle8.link_utilization    35.344325                      
-system.ruby.network.routers9.throttle8.msg_count.Control::2       617562                      
-system.ruby.network.routers9.throttle8.msg_count.Data::2       611948                      
-system.ruby.network.routers9.throttle8.msg_bytes.Control::2      4940496                      
-system.ruby.network.routers9.throttle8.msg_bytes.Data::2     44060256                      
+system.ruby.network.routers0.throttle0.link_utilization     4.459092                      
+system.ruby.network.routers0.throttle0.msg_count.Response_Data::4        78904                      
+system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3        79222                      
+system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4      5681088                      
+system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3       633776                      
+system.ruby.network.routers0.throttle1.link_utilization     4.473729                      
+system.ruby.network.routers0.throttle1.msg_count.Control::2        78906                      
+system.ruby.network.routers0.throttle1.msg_count.Data::2        78209                      
+system.ruby.network.routers0.throttle1.msg_count.Response_Data::4         1018                      
+system.ruby.network.routers0.throttle1.msg_bytes.Control::2       631248                      
+system.ruby.network.routers0.throttle1.msg_bytes.Data::2      5631048                      
+system.ruby.network.routers0.throttle1.msg_bytes.Response_Data::4        73296                      
+system.ruby.network.routers1.throttle0.link_utilization     4.456697                      
+system.ruby.network.routers1.throttle0.msg_count.Response_Data::4        78861                      
+system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::3        79185                      
+system.ruby.network.routers1.throttle0.msg_bytes.Response_Data::4      5677992                      
+system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::3       633480                      
+system.ruby.network.routers1.throttle1.link_utilization     4.471447                      
+system.ruby.network.routers1.throttle1.msg_count.Control::2        78862                      
+system.ruby.network.routers1.throttle1.msg_count.Data::2        78116                      
+system.ruby.network.routers1.throttle1.msg_count.Response_Data::4         1071                      
+system.ruby.network.routers1.throttle1.msg_bytes.Control::2       630896                      
+system.ruby.network.routers1.throttle1.msg_bytes.Data::2      5624352                      
+system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4        77112                      
+system.ruby.network.routers2.throttle0.link_utilization     4.448659                      
+system.ruby.network.routers2.throttle0.msg_count.Response_Data::4        78715                      
+system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3        79076                      
+system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4      5667480                      
+system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3       632608                      
+system.ruby.network.routers2.throttle1.link_utilization     4.465188                      
+system.ruby.network.routers2.throttle1.msg_count.Control::2        78717                      
+system.ruby.network.routers2.throttle1.msg_count.Data::2        78011                      
+system.ruby.network.routers2.throttle1.msg_count.Response_Data::4         1069                      
+system.ruby.network.routers2.throttle1.msg_bytes.Control::2       629736                      
+system.ruby.network.routers2.throttle1.msg_bytes.Data::2      5616792                      
+system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::4        76968                      
+system.ruby.network.routers3.throttle0.link_utilization     4.467628                      
+system.ruby.network.routers3.throttle0.msg_count.Response_Data::4        79054                      
+system.ruby.network.routers3.throttle0.msg_count.Writeback_Control::3        79383                      
+system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::4      5691888                      
+system.ruby.network.routers3.throttle0.msg_bytes.Writeback_Control::3       635064                      
+system.ruby.network.routers3.throttle1.link_utilization     4.482666                      
+system.ruby.network.routers3.throttle1.msg_count.Control::2        79057                      
+system.ruby.network.routers3.throttle1.msg_count.Data::2        78335                      
+system.ruby.network.routers3.throttle1.msg_count.Response_Data::4         1051                      
+system.ruby.network.routers3.throttle1.msg_bytes.Control::2       632456                      
+system.ruby.network.routers3.throttle1.msg_bytes.Data::2      5640120                      
+system.ruby.network.routers3.throttle1.msg_bytes.Response_Data::4        75672                      
+system.ruby.network.routers4.throttle0.link_utilization     4.453263                      
+system.ruby.network.routers4.throttle0.msg_count.Response_Data::4        78799                      
+system.ruby.network.routers4.throttle0.msg_count.Writeback_Control::3        79135                      
+system.ruby.network.routers4.throttle0.msg_bytes.Response_Data::4      5673528                      
+system.ruby.network.routers4.throttle0.msg_bytes.Writeback_Control::3       633080                      
+system.ruby.network.routers4.throttle1.link_utilization     4.468611                      
+system.ruby.network.routers4.throttle1.msg_count.Control::2        78801                      
+system.ruby.network.routers4.throttle1.msg_count.Data::2        78061                      
+system.ruby.network.routers4.throttle1.msg_count.Response_Data::4         1077                      
+system.ruby.network.routers4.throttle1.msg_bytes.Control::2       630408                      
+system.ruby.network.routers4.throttle1.msg_bytes.Data::2      5620392                      
+system.ruby.network.routers4.throttle1.msg_bytes.Response_Data::4        77544                      
+system.ruby.network.routers5.throttle0.link_utilization     4.448111                      
+system.ruby.network.routers5.throttle0.msg_count.Response_Data::4        78709                      
+system.ruby.network.routers5.throttle0.msg_count.Writeback_Control::3        79033                      
+system.ruby.network.routers5.throttle0.msg_bytes.Response_Data::4      5667048                      
+system.ruby.network.routers5.throttle0.msg_bytes.Writeback_Control::3       632264                      
+system.ruby.network.routers5.throttle1.link_utilization     4.463075                      
+system.ruby.network.routers5.throttle1.msg_count.Control::2        78712                      
+system.ruby.network.routers5.throttle1.msg_count.Data::2        77972                      
+system.ruby.network.routers5.throttle1.msg_count.Response_Data::4         1067                      
+system.ruby.network.routers5.throttle1.msg_bytes.Control::2       629696                      
+system.ruby.network.routers5.throttle1.msg_bytes.Data::2      5613984                      
+system.ruby.network.routers5.throttle1.msg_bytes.Response_Data::4        76824                      
+system.ruby.network.routers6.throttle0.link_utilization     4.446523                      
+system.ruby.network.routers6.throttle0.msg_count.Response_Data::4        78679                      
+system.ruby.network.routers6.throttle0.msg_count.Writeback_Control::3        79022                      
+system.ruby.network.routers6.throttle0.msg_bytes.Response_Data::4      5664888                      
+system.ruby.network.routers6.throttle0.msg_bytes.Writeback_Control::3       632176                      
+system.ruby.network.routers6.throttle1.link_utilization     4.462245                      
+system.ruby.network.routers6.throttle1.msg_count.Control::2        78682                      
+system.ruby.network.routers6.throttle1.msg_count.Data::2        77916                      
+system.ruby.network.routers6.throttle1.msg_count.Response_Data::4         1110                      
+system.ruby.network.routers6.throttle1.msg_bytes.Control::2       629456                      
+system.ruby.network.routers6.throttle1.msg_bytes.Data::2      5609952                      
+system.ruby.network.routers6.throttle1.msg_bytes.Response_Data::4        79920                      
+system.ruby.network.routers7.throttle0.link_utilization     4.471854                      
+system.ruby.network.routers7.throttle0.msg_count.Response_Data::4        79130                      
+system.ruby.network.routers7.throttle0.msg_count.Writeback_Control::3        79450                      
+system.ruby.network.routers7.throttle0.msg_bytes.Response_Data::4      5697360                      
+system.ruby.network.routers7.throttle0.msg_bytes.Writeback_Control::3       635600                      
+system.ruby.network.routers7.throttle1.link_utilization     4.486394                      
+system.ruby.network.routers7.throttle1.msg_count.Control::2        79132                      
+system.ruby.network.routers7.throttle1.msg_count.Data::2        78429                      
+system.ruby.network.routers7.throttle1.msg_count.Response_Data::4         1022                      
+system.ruby.network.routers7.throttle1.msg_bytes.Control::2       633056                      
+system.ruby.network.routers7.throttle1.msg_bytes.Data::2      5646888                      
+system.ruby.network.routers7.throttle1.msg_bytes.Response_Data::4        73584                      
+system.ruby.network.routers8.throttle0.link_utilization    35.341967                      
+system.ruby.network.routers8.throttle0.msg_count.Control::2       630869                      
+system.ruby.network.routers8.throttle0.msg_count.Data::2       625049                      
+system.ruby.network.routers8.throttle0.msg_bytes.Control::2      5046952                      
+system.ruby.network.routers8.throttle0.msg_bytes.Data::2     45003528                      
+system.ruby.network.routers8.throttle1.link_utilization    35.220468                      
+system.ruby.network.routers8.throttle1.msg_count.Response_Data::4       622367                      
+system.ruby.network.routers8.throttle1.msg_count.Writeback_Control::3       633506                      
+system.ruby.network.routers8.throttle1.msg_bytes.Response_Data::4     44810424                      
+system.ruby.network.routers8.throttle1.msg_bytes.Writeback_Control::3      5068048                      
+system.ruby.network.routers9.throttle0.link_utilization     4.459092                      
+system.ruby.network.routers9.throttle0.msg_count.Response_Data::4        78904                      
+system.ruby.network.routers9.throttle0.msg_count.Writeback_Control::3        79222                      
+system.ruby.network.routers9.throttle0.msg_bytes.Response_Data::4      5681088                      
+system.ruby.network.routers9.throttle0.msg_bytes.Writeback_Control::3       633776                      
+system.ruby.network.routers9.throttle1.link_utilization     4.456697                      
+system.ruby.network.routers9.throttle1.msg_count.Response_Data::4        78861                      
+system.ruby.network.routers9.throttle1.msg_count.Writeback_Control::3        79185                      
+system.ruby.network.routers9.throttle1.msg_bytes.Response_Data::4      5677992                      
+system.ruby.network.routers9.throttle1.msg_bytes.Writeback_Control::3       633480                      
+system.ruby.network.routers9.throttle2.link_utilization     4.448659                      
+system.ruby.network.routers9.throttle2.msg_count.Response_Data::4        78715                      
+system.ruby.network.routers9.throttle2.msg_count.Writeback_Control::3        79076                      
+system.ruby.network.routers9.throttle2.msg_bytes.Response_Data::4      5667480                      
+system.ruby.network.routers9.throttle2.msg_bytes.Writeback_Control::3       632608                      
+system.ruby.network.routers9.throttle3.link_utilization     4.467628                      
+system.ruby.network.routers9.throttle3.msg_count.Response_Data::4        79054                      
+system.ruby.network.routers9.throttle3.msg_count.Writeback_Control::3        79383                      
+system.ruby.network.routers9.throttle3.msg_bytes.Response_Data::4      5691888                      
+system.ruby.network.routers9.throttle3.msg_bytes.Writeback_Control::3       635064                      
+system.ruby.network.routers9.throttle4.link_utilization     4.453263                      
+system.ruby.network.routers9.throttle4.msg_count.Response_Data::4        78799                      
+system.ruby.network.routers9.throttle4.msg_count.Writeback_Control::3        79135                      
+system.ruby.network.routers9.throttle4.msg_bytes.Response_Data::4      5673528                      
+system.ruby.network.routers9.throttle4.msg_bytes.Writeback_Control::3       633080                      
+system.ruby.network.routers9.throttle5.link_utilization     4.448111                      
+system.ruby.network.routers9.throttle5.msg_count.Response_Data::4        78709                      
+system.ruby.network.routers9.throttle5.msg_count.Writeback_Control::3        79033                      
+system.ruby.network.routers9.throttle5.msg_bytes.Response_Data::4      5667048                      
+system.ruby.network.routers9.throttle5.msg_bytes.Writeback_Control::3       632264                      
+system.ruby.network.routers9.throttle6.link_utilization     4.446523                      
+system.ruby.network.routers9.throttle6.msg_count.Response_Data::4        78679                      
+system.ruby.network.routers9.throttle6.msg_count.Writeback_Control::3        79022                      
+system.ruby.network.routers9.throttle6.msg_bytes.Response_Data::4      5664888                      
+system.ruby.network.routers9.throttle6.msg_bytes.Writeback_Control::3       632176                      
+system.ruby.network.routers9.throttle7.link_utilization     4.471871                      
+system.ruby.network.routers9.throttle7.msg_count.Response_Data::4        79130                      
+system.ruby.network.routers9.throttle7.msg_count.Writeback_Control::3        79450                      
+system.ruby.network.routers9.throttle7.msg_bytes.Response_Data::4      5697360                      
+system.ruby.network.routers9.throttle7.msg_bytes.Writeback_Control::3       635600                      
+system.ruby.network.routers9.throttle8.link_utilization    35.341967                      
+system.ruby.network.routers9.throttle8.msg_count.Control::2       630869                      
+system.ruby.network.routers9.throttle8.msg_count.Data::2       625049                      
+system.ruby.network.routers9.throttle8.msg_bytes.Control::2      5046952                      
+system.ruby.network.routers9.throttle8.msg_bytes.Data::2     45003528                      
 system.ruby.delayVCHist.vnet_1::bucket_size            1                       # delay histogram for vnet_1
 system.ruby.delayVCHist.vnet_1::max_bucket            9                       # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::samples        617552                       # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::mean         0.002021                       # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::stdev        0.103548                       # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1           |      617290     99.96%     99.96% |           0      0.00%     99.96% |          38      0.01%     99.96% |           0      0.00%     99.96% |         102      0.02%     99.98% |           0      0.00%     99.98% |         106      0.02%    100.00% |           0      0.00%    100.00% |          16      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::total          617552                       # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1::samples        630851                       # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1::mean         0.002302                       # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1::stdev        0.111910                       # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1           |      630553     99.95%     99.95% |           0      0.00%     99.95% |          42      0.01%     99.96% |           0      0.00%     99.96% |         109      0.02%     99.98% |           0      0.00%     99.98% |         122      0.02%    100.00% |           0      0.00%    100.00% |          25      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1::total          630851                       # delay histogram for vnet_1
 system.ruby.delayVCHist.vnet_2::bucket_size            4                       # delay histogram for vnet_2
 system.ruby.delayVCHist.vnet_2::max_bucket           39                       # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::samples        620135                       # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::mean         0.026309                       # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::stdev        0.408237                       # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2           |      617823     99.63%     99.63% |        1409      0.23%     99.85% |         881      0.14%    100.00% |           6      0.00%    100.00% |          12      0.00%    100.00% |           3      0.00%    100.00% |           1      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::total          620135                       # delay histogram for vnet_2
+system.ruby.delayVCHist.vnet_2::samples        633506                       # delay histogram for vnet_2
+system.ruby.delayVCHist.vnet_2::mean         0.027049                       # delay histogram for vnet_2
+system.ruby.delayVCHist.vnet_2::stdev        0.412821                       # delay histogram for vnet_2
+system.ruby.delayVCHist.vnet_2           |      631057     99.61%     99.61% |        1512      0.24%     99.85% |         915      0.14%    100.00% |           5      0.00%    100.00% |          13      0.00%    100.00% |           2      0.00%    100.00% |           2      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for vnet_2
+system.ruby.delayVCHist.vnet_2::total          633506                       # delay histogram for vnet_2
 system.ruby.LD.latency_hist::bucket_size          512                      
 system.ruby.LD.latency_hist::max_bucket          5119                      
-system.ruby.LD.latency_hist::samples           401489                      
-system.ruby.LD.latency_hist::mean         1796.245110                      
-system.ruby.LD.latency_hist::gmean        1749.779554                      
-system.ruby.LD.latency_hist::stdev         410.866792                      
-system.ruby.LD.latency_hist              |          31      0.01%      0.01% |        5545      1.38%      1.39% |      105136     26.19%     27.58% |      190357     47.41%     74.99% |       82770     20.62%     95.60% |       15751      3.92%     99.53% |        1714      0.43%     99.95% |         157      0.04%     99.99% |          27      0.01%    100.00% |           1      0.00%    100.00%
-system.ruby.LD.latency_hist::total             401489                      
+system.ruby.LD.latency_hist::samples           405837                      
+system.ruby.LD.latency_hist::mean         1795.827911                      
+system.ruby.LD.latency_hist::gmean        1749.100087                      
+system.ruby.LD.latency_hist::stdev         411.882283                      
+system.ruby.LD.latency_hist              |          28      0.01%      0.01% |        5711      1.41%      1.41% |      106493     26.24%     27.65% |      191622     47.22%     74.87% |       84296     20.77%     95.64% |       15709      3.87%     99.51% |        1790      0.44%     99.95% |         171      0.04%    100.00% |          14      0.00%    100.00% |           3      0.00%    100.00%
+system.ruby.LD.latency_hist::total             405837                      
 system.ruby.LD.miss_latency_hist::bucket_size          512                      
 system.ruby.LD.miss_latency_hist::max_bucket         5119                      
-system.ruby.LD.miss_latency_hist::samples       401489                      
-system.ruby.LD.miss_latency_hist::mean    1796.245110                      
-system.ruby.LD.miss_latency_hist::gmean   1749.779554                      
-system.ruby.LD.miss_latency_hist::stdev    410.866792                      
-system.ruby.LD.miss_latency_hist         |          31      0.01%      0.01% |        5545      1.38%      1.39% |      105136     26.19%     27.58% |      190357     47.41%     74.99% |       82770     20.62%     95.60% |       15751      3.92%     99.53% |        1714      0.43%     99.95% |         157      0.04%     99.99% |          27      0.01%    100.00% |           1      0.00%    100.00%
-system.ruby.LD.miss_latency_hist::total        401489                      
+system.ruby.LD.miss_latency_hist::samples       405837                      
+system.ruby.LD.miss_latency_hist::mean    1795.827911                      
+system.ruby.LD.miss_latency_hist::gmean   1749.100087                      
+system.ruby.LD.miss_latency_hist::stdev    411.882283                      
+system.ruby.LD.miss_latency_hist         |          28      0.01%      0.01% |        5711      1.41%      1.41% |      106493     26.24%     27.65% |      191622     47.22%     74.87% |       84296     20.77%     95.64% |       15709      3.87%     99.51% |        1790      0.44%     99.95% |         171      0.04%    100.00% |          14      0.00%    100.00% |           3      0.00%    100.00%
+system.ruby.LD.miss_latency_hist::total        405837                      
 system.ruby.ST.latency_hist::bucket_size          512                      
 system.ruby.ST.latency_hist::max_bucket          5119                      
-system.ruby.ST.latency_hist::samples           216063                      
-system.ruby.ST.latency_hist::mean         1794.884353                      
-system.ruby.ST.latency_hist::gmean        1748.377616                      
-system.ruby.ST.latency_hist::stdev         411.177879                      
-system.ruby.ST.latency_hist              |          18      0.01%      0.01% |        2976      1.38%      1.39% |       56720     26.25%     27.64% |      102584     47.48%     75.12% |       44280     20.49%     95.61% |        8413      3.89%     99.50% |         955      0.44%     99.95% |         101      0.05%     99.99% |          15      0.01%    100.00% |           1      0.00%    100.00%
-system.ruby.ST.latency_hist::total             216063                      
+system.ruby.ST.latency_hist::samples           225014                      
+system.ruby.ST.latency_hist::mean         1795.524452                      
+system.ruby.ST.latency_hist::gmean        1748.632095                      
+system.ruby.ST.latency_hist::stdev         412.626104                      
+system.ruby.ST.latency_hist              |          21      0.01%      0.01% |        3203      1.42%      1.43% |       59194     26.31%     27.74% |      106161     47.18%     74.92% |       46441     20.64%     95.56% |        8899      3.95%     99.51% |         990      0.44%     99.95% |          94      0.04%    100.00% |          10      0.00%    100.00% |           1      0.00%    100.00%
+system.ruby.ST.latency_hist::total             225014                      
 system.ruby.ST.miss_latency_hist::bucket_size          512                      
 system.ruby.ST.miss_latency_hist::max_bucket         5119                      
-system.ruby.ST.miss_latency_hist::samples       216063                      
-system.ruby.ST.miss_latency_hist::mean    1794.884353                      
-system.ruby.ST.miss_latency_hist::gmean   1748.377616                      
-system.ruby.ST.miss_latency_hist::stdev    411.177879                      
-system.ruby.ST.miss_latency_hist         |          18      0.01%      0.01% |        2976      1.38%      1.39% |       56720     26.25%     27.64% |      102584     47.48%     75.12% |       44280     20.49%     95.61% |        8413      3.89%     99.50% |         955      0.44%     99.95% |         101      0.05%     99.99% |          15      0.01%    100.00% |           1      0.00%    100.00%
-system.ruby.ST.miss_latency_hist::total        216063                      
+system.ruby.ST.miss_latency_hist::samples       225014                      
+system.ruby.ST.miss_latency_hist::mean    1795.524452                      
+system.ruby.ST.miss_latency_hist::gmean   1748.632095                      
+system.ruby.ST.miss_latency_hist::stdev    412.626104                      
+system.ruby.ST.miss_latency_hist         |          21      0.01%      0.01% |        3203      1.42%      1.43% |       59194     26.31%     27.74% |      106161     47.18%     74.92% |       46441     20.64%     95.56% |        8899      3.95%     99.51% |         990      0.44%     99.95% |          94      0.04%    100.00% |          10      0.00%    100.00% |           1      0.00%    100.00%
+system.ruby.ST.miss_latency_hist::total        225014                      
 system.ruby.L1Cache.miss_mach_latency_hist::bucket_size          512                      
 system.ruby.L1Cache.miss_mach_latency_hist::max_bucket         5119                      
-system.ruby.L1Cache.miss_mach_latency_hist::samples         8208                      
-system.ruby.L1Cache.miss_mach_latency_hist::mean  1692.829678                      
-system.ruby.L1Cache.miss_mach_latency_hist::gmean  1644.794246                      
-system.ruby.L1Cache.miss_mach_latency_hist::stdev   406.296234                      
-system.ruby.L1Cache.miss_mach_latency_hist |           0      0.00%      0.00% |         237      2.89%      2.89% |        2860     34.84%     37.73% |        3603     43.90%     81.63% |        1287     15.68%     97.31% |         196      2.39%     99.70% |          22      0.27%     99.96% |           3      0.04%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.L1Cache.miss_mach_latency_hist::total         8208                      
+system.ruby.L1Cache.miss_mach_latency_hist::samples         8485                      
+system.ruby.L1Cache.miss_mach_latency_hist::mean  1687.011432                      
+system.ruby.L1Cache.miss_mach_latency_hist::gmean  1638.183403                      
+system.ruby.L1Cache.miss_mach_latency_hist::stdev   410.098641                      
+system.ruby.L1Cache.miss_mach_latency_hist |           0      0.00%      0.00% |         266      3.13%      3.13% |        3055     36.00%     39.14% |        3618     42.64%     81.78% |        1298     15.30%     97.08% |         223      2.63%     99.71% |          23      0.27%     99.98% |           2      0.02%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache.miss_mach_latency_hist::total         8485                      
 system.ruby.Directory.miss_mach_latency_hist::bucket_size          512                      
 system.ruby.Directory.miss_mach_latency_hist::max_bucket         5119                      
-system.ruby.Directory.miss_mach_latency_hist::samples       609344                      
-system.ruby.Directory.miss_mach_latency_hist::mean  1797.155638                      
-system.ruby.Directory.miss_mach_latency_hist::gmean  1750.740893                      
-system.ruby.Directory.miss_mach_latency_hist::stdev   410.862833                      
-system.ruby.Directory.miss_mach_latency_hist |          49      0.01%      0.01% |        8284      1.36%      1.37% |      158996     26.09%     27.46% |      289338     47.48%     74.94% |      125763     20.64%     95.58% |       23968      3.93%     99.52% |        2647      0.43%     99.95% |         255      0.04%     99.99% |          42      0.01%    100.00% |           2      0.00%    100.00%
-system.ruby.Directory.miss_mach_latency_hist::total       609344                      
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+system.ruby.Directory.miss_mach_latency_hist::gmean  1750.493671                      
+system.ruby.Directory.miss_mach_latency_hist::stdev   411.977479                      
+system.ruby.Directory.miss_mach_latency_hist |          49      0.01%      0.01% |        8648      1.39%      1.40% |      162632     26.13%     27.53% |      294165     47.27%     74.79% |      129439     20.80%     95.59% |       24385      3.92%     99.51% |        2757      0.44%     99.95% |         263      0.04%    100.00% |          24      0.00%    100.00% |           4      0.00%    100.00%
+system.ruby.Directory.miss_mach_latency_hist::total       622366                      
 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size            1                      
 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::max_bucket            9                      
-system.ruby.Directory.miss_latency_hist.issue_to_initial_request::samples            7                      
-system.ruby.Directory.miss_latency_hist.issue_to_initial_request |           7    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.Directory.miss_latency_hist.issue_to_initial_request::total            7                      
+system.ruby.Directory.miss_latency_hist.issue_to_initial_request::samples            4                      
+system.ruby.Directory.miss_latency_hist.issue_to_initial_request |           4    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.Directory.miss_latency_hist.issue_to_initial_request::total            4                      
 system.ruby.Directory.miss_latency_hist.initial_to_forward::bucket_size            1                      
 system.ruby.Directory.miss_latency_hist.initial_to_forward::max_bucket            9                      
-system.ruby.Directory.miss_latency_hist.initial_to_forward::samples            7                      
-system.ruby.Directory.miss_latency_hist.initial_to_forward |           7    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.Directory.miss_latency_hist.initial_to_forward::total            7                      
+system.ruby.Directory.miss_latency_hist.initial_to_forward::samples            4                      
+system.ruby.Directory.miss_latency_hist.initial_to_forward |           4    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.Directory.miss_latency_hist.initial_to_forward::total            4                      
 system.ruby.Directory.miss_latency_hist.forward_to_first_response::bucket_size            1                      
 system.ruby.Directory.miss_latency_hist.forward_to_first_response::max_bucket            9                      
-system.ruby.Directory.miss_latency_hist.forward_to_first_response::samples            7                      
-system.ruby.Directory.miss_latency_hist.forward_to_first_response |           7    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.Directory.miss_latency_hist.forward_to_first_response::total            7                      
-system.ruby.Directory.miss_latency_hist.first_response_to_completion::bucket_size           32                      
-system.ruby.Directory.miss_latency_hist.first_response_to_completion::max_bucket          319                      
-system.ruby.Directory.miss_latency_hist.first_response_to_completion::samples            7                      
-system.ruby.Directory.miss_latency_hist.first_response_to_completion::mean   113.714286                      
-system.ruby.Directory.miss_latency_hist.first_response_to_completion::gmean   104.188552                      
-system.ruby.Directory.miss_latency_hist.first_response_to_completion::stdev    50.582323                      
-system.ruby.Directory.miss_latency_hist.first_response_to_completion |           0      0.00%      0.00% |           1     14.29%     14.29% |           3     42.86%     57.14% |           0      0.00%     57.14% |           0      0.00%     57.14% |           3     42.86%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.Directory.miss_latency_hist.first_response_to_completion::total            7                      
+system.ruby.Directory.miss_latency_hist.forward_to_first_response::samples            4                      
+system.ruby.Directory.miss_latency_hist.forward_to_first_response |           4    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.Directory.miss_latency_hist.forward_to_first_response::total            4                      
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+system.ruby.Directory.miss_latency_hist.first_response_to_completion::samples            4                      
+system.ruby.Directory.miss_latency_hist.first_response_to_completion::mean    75.250000                      
+system.ruby.Directory.miss_latency_hist.first_response_to_completion::gmean    73.906370                      
+system.ruby.Directory.miss_latency_hist.first_response_to_completion::stdev    17.211914                      
+system.ruby.Directory.miss_latency_hist.first_response_to_completion |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           1     25.00%     25.00% |           2     50.00%     75.00% |           0      0.00%     75.00% |           1     25.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.Directory.miss_latency_hist.first_response_to_completion::total            4                      
 system.ruby.LD.L1Cache.miss_type_mach_latency_hist::bucket_size          512                      
 system.ruby.LD.L1Cache.miss_type_mach_latency_hist::max_bucket         5119                      
-system.ruby.LD.L1Cache.miss_type_mach_latency_hist::samples         5357                      
-system.ruby.LD.L1Cache.miss_type_mach_latency_hist::mean  1694.452679                      
-system.ruby.LD.L1Cache.miss_type_mach_latency_hist::gmean  1647.221011                      
-system.ruby.LD.L1Cache.miss_type_mach_latency_hist::stdev   402.824830                      
-system.ruby.LD.L1Cache.miss_type_mach_latency_hist |           0      0.00%      0.00% |         154      2.87%      2.87% |        1856     34.65%     37.52% |        2366     44.17%     81.69% |         844     15.76%     97.44% |         121      2.26%     99.70% |          14      0.26%     99.96% |           2      0.04%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.LD.L1Cache.miss_type_mach_latency_hist::total         5357                      
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+system.ruby.LD.L1Cache.miss_type_mach_latency_hist::mean  1686.068572                      
+system.ruby.LD.L1Cache.miss_type_mach_latency_hist::gmean  1637.388551                      
+system.ruby.LD.L1Cache.miss_type_mach_latency_hist::stdev   409.754972                      
+system.ruby.LD.L1Cache.miss_type_mach_latency_hist |           0      0.00%      0.00% |         173      3.13%      3.13% |        1989     35.99%     39.12% |        2361     42.72%     81.83% |         838     15.16%     97.00% |         151      2.73%     99.73% |          14      0.25%     99.98% |           1      0.02%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.L1Cache.miss_type_mach_latency_hist::total         5527                      
 system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size          512                      
 system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket         5119                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist::samples       396132                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist::mean  1797.621677                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean  1751.209372                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev   410.802147                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist |          31      0.01%      0.01% |        5391      1.36%      1.37% |      103280     26.07%     27.44% |      187991     47.46%     74.90% |       81926     20.68%     95.58% |       15630      3.95%     99.52% |        1700      0.43%     99.95% |         155      0.04%     99.99% |          27      0.01%    100.00% |           1      0.00%    100.00%
-system.ruby.LD.Directory.miss_type_mach_latency_hist::total       396132                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist::samples       400310                      
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+system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean  1750.694650                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev   411.707345                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist |          28      0.01%      0.01% |        5538      1.38%      1.39% |      104504     26.11%     27.50% |      189261     47.28%     74.77% |       83458     20.85%     95.62% |       15558      3.89%     99.51% |        1776      0.44%     99.95% |         170      0.04%    100.00% |          14      0.00%    100.00% |           3      0.00%    100.00%
+system.ruby.LD.Directory.miss_type_mach_latency_hist::total       400310                      
 system.ruby.ST.L1Cache.miss_type_mach_latency_hist::bucket_size          512                      
 system.ruby.ST.L1Cache.miss_type_mach_latency_hist::max_bucket         5119                      
-system.ruby.ST.L1Cache.miss_type_mach_latency_hist::samples         2851                      
-system.ruby.ST.L1Cache.miss_type_mach_latency_hist::mean  1689.780077                      
-system.ruby.ST.L1Cache.miss_type_mach_latency_hist::gmean  1640.244046                      
-system.ruby.ST.L1Cache.miss_type_mach_latency_hist::stdev   412.793948                      
-system.ruby.ST.L1Cache.miss_type_mach_latency_hist |           0      0.00%      0.00% |          83      2.91%      2.91% |        1004     35.22%     38.13% |        1237     43.39%     81.52% |         443     15.54%     97.05% |          75      2.63%     99.68% |           8      0.28%     99.96% |           1      0.04%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.ST.L1Cache.miss_type_mach_latency_hist::total         2851                      
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+system.ruby.ST.L1Cache.miss_type_mach_latency_hist::gmean  1639.669612                      
+system.ruby.ST.L1Cache.miss_type_mach_latency_hist::stdev   410.803541                      
+system.ruby.ST.L1Cache.miss_type_mach_latency_hist |           0      0.00%      0.00% |          93      3.14%      3.14% |        1066     36.04%     39.18% |        1257     42.49%     81.68% |         460     15.55%     97.23% |          72      2.43%     99.66% |           9      0.30%     99.97% |           1      0.03%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.L1Cache.miss_type_mach_latency_hist::total         2958                      
 system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size          512                      
 system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket         5119                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist::samples       213212                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist::mean  1796.289773                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean  1749.870827                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev   410.975121                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist |          18      0.01%      0.01% |        2893      1.36%      1.37% |       55716     26.13%     27.50% |      101347     47.53%     75.03% |       43837     20.56%     95.59% |        8338      3.91%     99.50% |         947      0.44%     99.95% |         100      0.05%     99.99% |          15      0.01%    100.00% |           1      0.00%    100.00%
-system.ruby.ST.Directory.miss_type_mach_latency_hist::total       213212                      
-system.ruby.L1Cache_Controller.Load      |       50370     12.55%     12.55% |       50258     12.52%     25.06% |       50037     12.46%     37.53% |       49672     12.37%     49.90% |       50004     12.45%     62.35% |       50305     12.53%     74.88% |       50279     12.52%     87.40% |       50578     12.60%    100.00%
-system.ruby.L1Cache_Controller.Load::total       401503                      
-system.ruby.L1Cache_Controller.Store     |       27007     12.50%     12.50% |       26935     12.47%     24.96% |       26787     12.40%     37.36% |       27153     12.57%     49.93% |       27327     12.65%     62.58% |       27084     12.53%     75.11% |       27075     12.53%     87.64% |       26703     12.36%    100.00%
-system.ruby.L1Cache_Controller.Store::total       216071                      
-system.ruby.L1Cache_Controller.Data      |       77375     12.53%     12.53% |       77192     12.50%     25.03% |       76821     12.44%     37.47% |       76821     12.44%     49.91% |       77329     12.52%     62.43% |       77385     12.53%     74.96% |       77352     12.53%     87.49% |       77277     12.51%    100.00%
-system.ruby.L1Cache_Controller.Data::total       617552                      
-system.ruby.L1Cache_Controller.Fwd_GETX  |        1048     12.77%     12.77% |        1042     12.69%     25.46% |        1040     12.67%     38.13% |        1065     12.98%     51.11% |         995     12.12%     63.23% |        1001     12.20%     75.43% |         998     12.16%     87.59% |        1019     12.41%    100.00%
-system.ruby.L1Cache_Controller.Fwd_GETX::total         8208                      
-system.ruby.L1Cache_Controller.Replacement |       77373     12.53%     12.53% |       77189     12.50%     25.03% |       76820     12.44%     37.47% |       76821     12.44%     49.91% |       77327     12.52%     62.43% |       77385     12.53%     74.96% |       77350     12.53%     87.49% |       77277     12.51%    100.00%
-system.ruby.L1Cache_Controller.Replacement::total       617542                      
-system.ruby.L1Cache_Controller.Writeback_Ack |       76323     12.53%     12.53% |       76144     12.50%     25.02% |       75775     12.44%     37.46% |       75751     12.43%     49.89% |       76330     12.53%     62.42% |       76378     12.54%     74.95% |       76350     12.53%     87.49% |       76253     12.51%    100.00%
-system.ruby.L1Cache_Controller.Writeback_Ack::total       609304                      
-system.ruby.L1Cache_Controller.Writeback_Nack |         342     13.04%     13.04% |         322     12.28%     25.31% |         324     12.35%     37.67% |         341     13.00%     50.67% |         327     12.47%     63.13% |         344     13.11%     76.25% |         310     11.82%     88.07% |         313     11.93%    100.00%
-system.ruby.L1Cache_Controller.Writeback_Nack::total         2623                      
-system.ruby.L1Cache_Controller.I.Load    |       50370     12.55%     12.55% |       50258     12.52%     25.06% |       50037     12.46%     37.53% |       49672     12.37%     49.90% |       50004     12.45%     62.35% |       50305     12.53%     74.88% |       50279     12.52%     87.40% |       50578     12.60%    100.00%
-system.ruby.L1Cache_Controller.I.Load::total       401503                      
-system.ruby.L1Cache_Controller.I.Store   |       27007     12.50%     12.50% |       26935     12.47%     24.96% |       26787     12.40%     37.36% |       27153     12.57%     49.93% |       27327     12.65%     62.58% |       27084     12.53%     75.11% |       27075     12.53%     87.64% |       26703     12.36%    100.00%
-system.ruby.L1Cache_Controller.I.Store::total       216071                      
-system.ruby.L1Cache_Controller.I.Replacement |         706     12.64%     12.64% |         720     12.89%     25.53% |         716     12.82%     38.35% |         724     12.96%     51.32% |         668     11.96%     63.28% |         657     11.76%     75.04% |         688     12.32%     87.36% |         706     12.64%    100.00%
-system.ruby.L1Cache_Controller.I.Replacement::total         5585                      
-system.ruby.L1Cache_Controller.II.Writeback_Nack |         342     13.04%     13.04% |         322     12.28%     25.31% |         324     12.35%     37.67% |         341     13.00%     50.67% |         327     12.47%     63.13% |         344     13.11%     76.25% |         310     11.82%     88.07% |         313     11.93%    100.00%
-system.ruby.L1Cache_Controller.II.Writeback_Nack::total         2623                      
-system.ruby.L1Cache_Controller.M.Fwd_GETX |         706     12.64%     12.64% |         720     12.89%     25.53% |         716     12.82%     38.35% |         724     12.96%     51.32% |         668     11.96%     63.28% |         657     11.76%     75.04% |         688     12.32%     87.36% |         706     12.64%    100.00%
-system.ruby.L1Cache_Controller.M.Fwd_GETX::total         5585                      
-system.ruby.L1Cache_Controller.M.Replacement |       76667     12.53%     12.53% |       76469     12.50%     25.02% |       76104     12.44%     37.46% |       76097     12.44%     49.90% |       76659     12.53%     62.42% |       76728     12.54%     74.96% |       76662     12.53%     87.49% |       76571     12.51%    100.00%
-system.ruby.L1Cache_Controller.M.Replacement::total       611957                      
-system.ruby.L1Cache_Controller.MI.Fwd_GETX |         342     13.04%     13.04% |         322     12.28%     25.31% |         324     12.35%     37.67% |         341     13.00%     50.67% |         327     12.47%     63.13% |         344     13.11%     76.25% |         310     11.82%     88.07% |         313     11.93%    100.00%
-system.ruby.L1Cache_Controller.MI.Fwd_GETX::total         2623                      
-system.ruby.L1Cache_Controller.MI.Writeback_Ack |       76323     12.53%     12.53% |       76144     12.50%     25.02% |       75775     12.44%     37.46% |       75751     12.43%     49.89% |       76330     12.53%     62.42% |       76378     12.54%     74.95% |       76350     12.53%     87.49% |       76253     12.51%    100.00%
-system.ruby.L1Cache_Controller.MI.Writeback_Ack::total       609304                      
-system.ruby.L1Cache_Controller.IS.Data   |       50370     12.55%     12.55% |       50258     12.52%     25.06% |       50035     12.46%     37.53% |       49669     12.37%     49.90% |       50002     12.45%     62.35% |       50301     12.53%     74.88% |       50278     12.52%     87.40% |       50576     12.60%    100.00%
-system.ruby.L1Cache_Controller.IS.Data::total       401489                      
-system.ruby.L1Cache_Controller.IM.Data   |       27005     12.50%     12.50% |       26934     12.47%     24.96% |       26786     12.40%     37.36% |       27152     12.57%     49.93% |       27327     12.65%     62.58% |       27084     12.54%     75.11% |       27074     12.53%     87.64% |       26701     12.36%    100.00%
-system.ruby.L1Cache_Controller.IM.Data::total       216063                      
-system.ruby.Directory_Controller.GETX          791175      0.00%      0.00%
-system.ruby.Directory_Controller.PUTX          609324      0.00%      0.00%
-system.ruby.Directory_Controller.PUTX_NotOwner         2623      0.00%      0.00%
-system.ruby.Directory_Controller.Memory_Data       609345      0.00%      0.00%
-system.ruby.Directory_Controller.Memory_Ack       609304      0.00%      0.00%
-system.ruby.Directory_Controller.I.GETX        609354      0.00%      0.00%
-system.ruby.Directory_Controller.M.GETX          8208      0.00%      0.00%
-system.ruby.Directory_Controller.M.PUTX        609324      0.00%      0.00%
-system.ruby.Directory_Controller.M.PUTX_NotOwner         2623      0.00%      0.00%
-system.ruby.Directory_Controller.IM.GETX        65257      0.00%      0.00%
-system.ruby.Directory_Controller.IM.Memory_Data       609345      0.00%      0.00%
-system.ruby.Directory_Controller.MI.GETX       108356      0.00%      0.00%
-system.ruby.Directory_Controller.MI.Memory_Ack       609304      0.00%      0.00%
+system.ruby.ST.Directory.miss_type_mach_latency_hist::samples       222056                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist::mean  1796.946482                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean  1750.131417                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev   412.464819                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist |          21      0.01%      0.01% |        3110      1.40%      1.41% |       58128     26.18%     27.59% |      104904     47.24%     74.83% |       45981     20.71%     95.54% |        8827      3.98%     99.51% |         981      0.44%     99.95% |          93      0.04%    100.00% |          10      0.00%    100.00% |           1      0.00%    100.00%
+system.ruby.ST.Directory.miss_type_mach_latency_hist::total       222056                      
+system.ruby.L1Cache_Controller.Load      |       50822     12.52%     12.52% |       50930     12.55%     25.07% |       50579     12.46%     37.53% |       50992     12.56%     50.10% |       50750     12.50%     62.60% |       50396     12.42%     75.02% |       50785     12.51%     87.53% |       50593     12.47%    100.00%
+system.ruby.L1Cache_Controller.Load::total       405847                      
+system.ruby.L1Cache_Controller.Store     |       28084     12.48%     12.48% |       27932     12.41%     24.89% |       28138     12.50%     37.40% |       28065     12.47%     49.87% |       28051     12.47%     62.34% |       28316     12.58%     74.92% |       27897     12.40%     87.32% |       28539     12.68%    100.00%
+system.ruby.L1Cache_Controller.Store::total       225022                      
+system.ruby.L1Cache_Controller.Data      |       78904     12.51%     12.51% |       78861     12.50%     25.01% |       78715     12.48%     37.49% |       79054     12.53%     50.02% |       78799     12.49%     62.51% |       78709     12.48%     74.98% |       78679     12.47%     87.46% |       79130     12.54%    100.00%
+system.ruby.L1Cache_Controller.Data::total       630851                      
+system.ruby.L1Cache_Controller.Fwd_GETX  |        1018     12.00%     12.00% |        1071     12.62%     24.62% |        1069     12.60%     37.22% |        1051     12.39%     49.61% |        1077     12.69%     62.30% |        1067     12.58%     74.87% |        1110     13.08%     87.96% |        1022     12.04%    100.00%
+system.ruby.L1Cache_Controller.Fwd_GETX::total         8485                      
+system.ruby.L1Cache_Controller.Replacement |       78902     12.51%     12.51% |       78858     12.50%     25.01% |       78713     12.48%     37.49% |       79053     12.53%     50.02% |       78797     12.49%     62.51% |       78708     12.48%     74.98% |       78678     12.47%     87.46% |       79128     12.54%    100.00%
+system.ruby.L1Cache_Controller.Replacement::total       630837                      
+system.ruby.L1Cache_Controller.Writeback_Ack |       77879     12.51%     12.51% |       77785     12.50%     25.01% |       77640     12.48%     37.49% |       77999     12.53%     50.02% |       77717     12.49%     62.51% |       77635     12.48%     74.99% |       77564     12.46%     87.45% |       78105     12.55%    100.00%
+system.ruby.L1Cache_Controller.Writeback_Ack::total       622324                      
+system.ruby.L1Cache_Controller.Writeback_Nack |         325     12.05%     12.05% |         329     12.20%     24.25% |         367     13.61%     37.86% |         333     12.35%     50.20% |         341     12.64%     62.85% |         331     12.27%     75.12% |         348     12.90%     88.02% |         323     11.98%    100.00%
+system.ruby.L1Cache_Controller.Writeback_Nack::total         2697                      
+system.ruby.L1Cache_Controller.I.Load    |       50822     12.52%     12.52% |       50930     12.55%     25.07% |       50579     12.46%     37.53% |       50992     12.56%     50.10% |       50750     12.50%     62.60% |       50396     12.42%     75.02% |       50785     12.51%     87.53% |       50593     12.47%    100.00%
+system.ruby.L1Cache_Controller.I.Load::total       405847                      
+system.ruby.L1Cache_Controller.I.Store   |       28084     12.48%     12.48% |       27932     12.41%     24.89% |       28138     12.50%     37.40% |       28065     12.47%     49.87% |       28051     12.47%     62.34% |       28316     12.58%     74.92% |       27897     12.40%     87.32% |       28539     12.68%    100.00%
+system.ruby.L1Cache_Controller.I.Store::total       225022                      
+system.ruby.L1Cache_Controller.I.Replacement |         693     11.97%     11.97% |         742     12.82%     24.79% |         702     12.13%     36.92% |         718     12.40%     49.33% |         736     12.72%     62.04% |         736     12.72%     74.76% |         762     13.17%     87.92% |         699     12.08%    100.00%
+system.ruby.L1Cache_Controller.I.Replacement::total         5788                      
+system.ruby.L1Cache_Controller.II.Writeback_Nack |         325     12.05%     12.05% |         329     12.20%     24.25% |         367     13.61%     37.86% |         333     12.35%     50.20% |         341     12.64%     62.85% |         331     12.27%     75.12% |         348     12.90%     88.02% |         323     11.98%    100.00%
+system.ruby.L1Cache_Controller.II.Writeback_Nack::total         2697                      
+system.ruby.L1Cache_Controller.M.Fwd_GETX |         693     11.97%     11.97% |         742     12.82%     24.79% |         702     12.13%     36.92% |         718     12.40%     49.33% |         736     12.72%     62.04% |         736     12.72%     74.76% |         762     13.17%     87.92% |         699     12.08%    100.00%
+system.ruby.L1Cache_Controller.M.Fwd_GETX::total         5788                      
+system.ruby.L1Cache_Controller.M.Replacement |       78209     12.51%     12.51% |       78116     12.50%     25.01% |       78011     12.48%     37.49% |       78335     12.53%     50.02% |       78061     12.49%     62.51% |       77972     12.47%     74.99% |       77916     12.47%     87.45% |       78429     12.55%    100.00%
+system.ruby.L1Cache_Controller.M.Replacement::total       625049                      
+system.ruby.L1Cache_Controller.MI.Fwd_GETX |         325     12.05%     12.05% |         329     12.20%     24.25% |         367     13.61%     37.86% |         333     12.35%     50.20% |         341     12.64%     62.85% |         331     12.27%     75.12% |         348     12.90%     88.02% |         323     11.98%    100.00%
+system.ruby.L1Cache_Controller.MI.Fwd_GETX::total         2697                      
+system.ruby.L1Cache_Controller.MI.Writeback_Ack |       77879     12.51%     12.51% |       77785     12.50%     25.01% |       77640     12.48%     37.49% |       77999     12.53%     50.02% |       77717     12.49%     62.51% |       77635     12.48%     74.99% |       77564     12.46%     87.45% |       78105     12.55%    100.00%
+system.ruby.L1Cache_Controller.MI.Writeback_Ack::total       622324                      
+system.ruby.L1Cache_Controller.IS.Data   |       50821     12.52%     12.52% |       50929     12.55%     25.07% |       50577     12.46%     37.53% |       50990     12.56%     50.10% |       50750     12.51%     62.60% |       50395     12.42%     75.02% |       50783     12.51%     87.53% |       50592     12.47%    100.00%
+system.ruby.L1Cache_Controller.IS.Data::total       405837                      
+system.ruby.L1Cache_Controller.IM.Data   |       28083     12.48%     12.48% |       27932     12.41%     24.89% |       28138     12.50%     37.40% |       28064     12.47%     49.87% |       28049     12.47%     62.34% |       28314     12.58%     74.92% |       27896     12.40%     87.32% |       28538     12.68%    100.00%
+system.ruby.L1Cache_Controller.IM.Data::total       225014                      
+system.ruby.Directory_Controller.GETX          808444      0.00%      0.00%
+system.ruby.Directory_Controller.PUTX          622352      0.00%      0.00%
+system.ruby.Directory_Controller.PUTX_NotOwner         2697      0.00%      0.00%
+system.ruby.Directory_Controller.Memory_Data       622367      0.00%      0.00%
+system.ruby.Directory_Controller.Memory_Ack       622324      0.00%      0.00%
+system.ruby.Directory_Controller.I.GETX        622384      0.00%      0.00%
+system.ruby.Directory_Controller.M.GETX          8485      0.00%      0.00%
+system.ruby.Directory_Controller.M.PUTX        622352      0.00%      0.00%
+system.ruby.Directory_Controller.M.PUTX_NotOwner         2697      0.00%      0.00%
+system.ruby.Directory_Controller.IM.GETX        68392      0.00%      0.00%
+system.ruby.Directory_Controller.IM.Memory_Data       622367      0.00%      0.00%
+system.ruby.Directory_Controller.MI.GETX       109183      0.00%      0.00%
+system.ruby.Directory_Controller.MI.Memory_Ack       622324      0.00%      0.00%
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt b/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt
index d30a7aa16..ee0a55e41 100644
--- a/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt
+++ b/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt
@@ -1,663 +1,664 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000653                       # Number of seconds simulated
-sim_ticks                                   652606500                       # Number of ticks simulated
-final_tick                                  652606500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.000667                       # Number of seconds simulated
+sim_ticks                                   666669000                       # Number of ticks simulated
+final_tick                                  666669000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_tick_rate                              148113487                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 336812                       # Number of bytes of host memory used
-host_seconds                                     4.41                       # Real time elapsed on the host
+host_tick_rate                               89799840                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 343700                       # Number of bytes of host memory used
+host_seconds                                     7.42                       # Real time elapsed on the host
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu0                 80014                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1                 82049                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2                 81047                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3                 79011                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu4                 80501                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu5                 83900                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu6                 78451                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu7                 80299                       # Number of bytes read from this memory
-system.physmem.bytes_read::total               645272                       # Number of bytes read from this memory
-system.physmem.bytes_written::writebacks       398848                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0               5221                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1               5261                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu2               5379                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu3               5376                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu4               5284                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu5               5253                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu6               5355                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu7               5238                       # Number of bytes written to this memory
-system.physmem.bytes_written::total            441215                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0                  10966                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1                  11048                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2                  10991                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3                  11034                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu4                  11075                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu5                  11072                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu6                  10915                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu7                  11125                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                 88226                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks            6232                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0                  5221                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1                  5261                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu2                  5379                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu3                  5376                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu4                  5284                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu5                  5253                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu6                  5355                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu7                  5238                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total                48599                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0                122606808                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1                125725073                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2                124189692                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3                121069894                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu4                123353047                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu5                128561392                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu6                120211797                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu7                123043519                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               988761221                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks         611161550                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0                 8000227                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1                 8061519                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu2                 8242333                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu3                 8237736                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu4                 8096763                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu5                 8049261                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu6                 8205557                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu7                 8026276                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total              676081222                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks         611161550                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0               130607035                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1               133786593                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2               132432025                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3               129307630                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu4               131449809                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu5               136610653                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu6               128417354                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu7               131069795                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             1664842443                       # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput                   1664833249                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq               85134                       # Transaction distribution
-system.membus.trans_dist::ReadResp              85128                       # Transaction distribution
-system.membus.trans_dist::WriteReq              42367                       # Transaction distribution
-system.membus.trans_dist::WriteResp             42365                       # Transaction distribution
-system.membus.trans_dist::Writeback              6232                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            57414                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp           46744                       # Transaction distribution
-system.membus.trans_dist::ReadExReq             48586                       # Transaction distribution
-system.membus.trans_dist::ReadExResp             3092                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       417062                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 417062                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port      1086481                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total             1086481                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus                1086481                       # Total data (bytes)
+system.physmem.bytes_read::cpu0                 77587                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1                 78424                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2                 78448                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3                 79552                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu4                 79510                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu5                 77345                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu6                 78315                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu7                 77919                       # Number of bytes read from this memory
+system.physmem.bytes_read::total               627100                       # Number of bytes read from this memory
+system.physmem.bytes_written::writebacks       389952                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0               5508                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1               5505                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu2               5430                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu3               5540                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu4               5369                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu5               5487                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu6               5602                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu7               5488                       # Number of bytes written to this memory
+system.physmem.bytes_written::total            433881                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0                  10807                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1                  10825                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2                  10786                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3                  10945                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu4                  10966                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu5                  10880                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu6                  10905                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu7                  10824                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                 86938                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks            6093                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0                  5508                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu1                  5505                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu2                  5430                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu3                  5540                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu4                  5369                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu5                  5487                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu6                  5602                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu7                  5488                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                50022                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0                116380093                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1                117635588                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2                117671588                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3                119327582                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu4                119264583                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu5                116017094                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu6                117472089                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu7                116878091                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               940646708                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks         584925953                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0                 8261971                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1                 8257471                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu2                 8144971                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu3                 8309971                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu4                 8053472                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu5                 8230471                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu6                 8402971                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu7                 8231971                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total              650819222                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks         584925953                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0               124642064                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1               125893059                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2               125816560                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3               127637553                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu4               127318054                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu5               124247565                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu6               125875059                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu7               125110062                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             1591465930                       # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput                   1591365430                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq               83865                       # Transaction distribution
+system.membus.trans_dist::ReadResp              83861                       # Transaction distribution
+system.membus.trans_dist::WriteReq              43929                       # Transaction distribution
+system.membus.trans_dist::WriteResp             43926                       # Transaction distribution
+system.membus.trans_dist::Writeback              6093                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq            58314                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp           47560                       # Transaction distribution
+system.membus.trans_dist::ReadExReq             50259                       # Transaction distribution
+system.membus.trans_dist::ReadExResp             3073                       # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       420880                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 420880                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port      1060914                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total             1060914                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus                1060914                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy           286485584                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization              43.9                       # Layer utilization (%)
-system.membus.respLayer0.occupancy          311361500                       # Layer occupancy (ticks)
-system.membus.respLayer0.utilization             47.7                       # Layer utilization (%)
+system.membus.reqLayer0.occupancy           288472152                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization              43.3                       # Layer utilization (%)
+system.membus.respLayer0.occupancy          310892000                       # Layer occupancy (ticks)
+system.membus.respLayer0.utilization             46.6                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.l2c.tags.replacements                    13254                       # number of replacements
-system.l2c.tags.tagsinuse                  783.820018                       # Cycle average of tags in use
-system.l2c.tags.total_refs                     149317                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                    14065                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                    10.616210                       # Average number of references to valid blocks.
+system.l2c.tags.replacements                    13077                       # number of replacements
+system.l2c.tags.tagsinuse                  783.417350                       # Cycle average of tags in use
+system.l2c.tags.total_refs                     150095                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                    13853                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                    10.834837                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks     726.472153                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0             7.679894                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1             7.566050                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2             7.311161                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3             6.856177                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu4             7.195523                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu5             6.988954                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu6             6.739476                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu7             7.010629                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.709445                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0            0.007500                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1            0.007389                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2            0.007140                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu3            0.006695                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu4            0.007027                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu5            0.006825                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu6            0.006582                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu7            0.006846                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.765449                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1024          811                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0          611                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1          200                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1024     0.791992                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                  1942968                       # Number of tag accesses
-system.l2c.tags.data_accesses                 1942968                       # Number of data accesses
-system.l2c.ReadReq_hits::cpu0                   10635                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1                   10552                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2                   10744                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu3                   10808                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu4                   10723                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu5                   10748                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu6                   10725                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu7                   10838                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                  85773                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks           74336                       # number of Writeback hits
-system.l2c.Writeback_hits::total                74336                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0                  332                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1                  322                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu2                  337                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu3                  354                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu4                  332                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu5                  353                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu6                  349                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu7                  378                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                2757                       # number of UpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0                  1930                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1                  1860                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu2                  1868                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu3                  1850                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu4                  1871                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu5                  1809                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu6                  1953                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu7                  1858                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total                14999                       # number of ReadExReq hits
-system.l2c.demand_hits::cpu0                    12565                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1                    12412                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2                    12612                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu3                    12658                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu4                    12594                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu5                    12557                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu6                    12678                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu7                    12696                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                  100772                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0                   12565                       # number of overall hits
-system.l2c.overall_hits::cpu1                   12412                       # number of overall hits
-system.l2c.overall_hits::cpu2                   12612                       # number of overall hits
-system.l2c.overall_hits::cpu3                   12658                       # number of overall hits
-system.l2c.overall_hits::cpu4                   12594                       # number of overall hits
-system.l2c.overall_hits::cpu5                   12557                       # number of overall hits
-system.l2c.overall_hits::cpu6                   12678                       # number of overall hits
-system.l2c.overall_hits::cpu7                   12696                       # number of overall hits
-system.l2c.overall_hits::total                 100772                       # number of overall hits
-system.l2c.ReadReq_misses::cpu0                   751                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1                   742                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2                   744                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu3                   696                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu4                   727                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu5                   735                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu6                   708                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu7                   698                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total                 5801                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0               1964                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1               1929                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu2               1920                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu3               1880                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu4               1830                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu5               1887                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu6               1921                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu7               1963                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total             15294                       # number of UpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0                4321                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1                4353                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu2                4358                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu3                4233                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu4                4361                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu5                4404                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu6                4224                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu7                4317                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total              34571                       # number of ReadExReq misses
-system.l2c.demand_misses::cpu0                   5072                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1                   5095                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2                   5102                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu3                   4929                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu4                   5088                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu5                   5139                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu6                   4932                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu7                   5015                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                 40372                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0                  5072                       # number of overall misses
-system.l2c.overall_misses::cpu1                  5095                       # number of overall misses
-system.l2c.overall_misses::cpu2                  5102                       # number of overall misses
-system.l2c.overall_misses::cpu3                  4929                       # number of overall misses
-system.l2c.overall_misses::cpu4                  5088                       # number of overall misses
-system.l2c.overall_misses::cpu5                  5139                       # number of overall misses
-system.l2c.overall_misses::cpu6                  4932                       # number of overall misses
-system.l2c.overall_misses::cpu7                  5015                       # number of overall misses
-system.l2c.overall_misses::total                40372                       # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu0        46656500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1        45888000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu2        46214500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu3        43225999                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu4        45481000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu5        44732500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu6        43604500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu7        43142000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total      358944999                       # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu0     54482000                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1     56107500                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu2     54698000                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu3     55749000                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu4     51718500                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu5     55828000                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu6     55452500                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu7     58605500                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total    442641000                       # number of UpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0     232354499                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1     234531000                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu2     234959000                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu3     228552499                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu4     234872500                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu5     237965000                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu6     227719000                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu7     232651999                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total   1863605497                       # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency::cpu0        279010999                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1        280419000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2        281173500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu3        271778498                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu4        280353500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu5        282697500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu6        271323500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu7        275793999                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total      2222550496                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0       279010999                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1       280419000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2       281173500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu3       271778498                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu4       280353500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu5       282697500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu6       271323500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu7       275793999                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total     2222550496                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu0               11386                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1               11294                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2               11488                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu3               11504                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu4               11450                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu5               11483                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu6               11433                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu7               11536                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total              91574                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks        74336                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total            74336                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0             2296                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1             2251                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu2             2257                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu3             2234                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu4             2162                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu5             2240                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu6             2270                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu7             2341                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total           18051                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0              6251                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1              6213                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu2              6226                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu3              6083                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu4              6232                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu5              6213                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu6              6177                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu7              6175                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total            49570                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0                17637                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1                17507                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2                17714                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu3                17587                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu4                17682                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu5                17696                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu6                17610                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu7                17711                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total              141144                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0               17637                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1               17507                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2               17714                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu3               17587                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu4               17682                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu5               17696                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu6               17610                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu7               17711                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total             141144                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0           0.065958                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1           0.065699                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2           0.064763                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu3           0.060501                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu4           0.063493                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu5           0.064008                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu6           0.061926                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu7           0.060506                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.063348                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0        0.855401                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1        0.856952                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu2        0.850687                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu3        0.841540                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu4        0.846438                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu5        0.842411                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu6        0.846256                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu7        0.838531                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.847266                       # miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0         0.691249                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1         0.700628                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu2         0.699968                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu3         0.695874                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu4         0.699775                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu5         0.708836                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu6         0.683827                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu7         0.699109                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.697418                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0            0.287577                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1            0.291026                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2            0.288021                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu3            0.280264                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu4            0.287750                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu5            0.290405                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu6            0.280068                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu7            0.283157                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.286034                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0           0.287577                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1           0.291026                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2           0.288021                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu3           0.280264                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu4           0.287750                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu5           0.290405                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu6           0.280068                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu7           0.283157                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.286034                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu0 62125.832224                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1 61843.665768                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2 62116.263441                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu3 62106.320402                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu4 62559.834938                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu5 60860.544218                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu6 61588.276836                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu7 61808.022923                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 61876.400448                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu0 27740.325866                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1 29086.314152                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu2 28488.541667                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu3 29653.723404                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu4 28261.475410                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu5 29585.585586                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu6 28866.475794                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu7 29855.068772                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total 28942.134170                       # average UpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0 53773.316131                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1 53878.015162                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu2 53914.410280                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu3 53993.030711                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu4 53857.486815                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu5 54033.832879                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu6 53910.748106                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu7 53892.054436                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 53906.612392                       # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0 55010.055008                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1 55038.076546                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2 55110.446884                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu3 55138.668695                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu4 55100.923742                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu5 55010.215995                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu6 55012.875101                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu7 54993.818345                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 55051.780838                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0 55010.055008                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1 55038.076546                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2 55110.446884                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu3 55138.668695                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu4 55100.923742                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu5 55010.215995                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu6 55012.875101                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu7 54993.818345                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 55051.780838                       # average overall miss latency
-system.l2c.blocked_cycles::no_mshrs             13487                       # number of cycles access was blocked
+system.l2c.tags.occ_blocks::writebacks     730.528683                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0             6.960741                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1             6.211335                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2             6.682597                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu3             6.340197                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu4             6.666463                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu5             5.896963                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu6             7.159072                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu7             6.971301                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.713407                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0            0.006798                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1            0.006066                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2            0.006526                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu3            0.006192                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu4            0.006510                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu5            0.005759                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu6            0.006991                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu7            0.006808                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.765056                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1024          776                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0          556                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1          220                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1024     0.757812                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                  1967301                       # Number of tag accesses
+system.l2c.tags.data_accesses                 1967301                       # Number of data accesses
+system.l2c.ReadReq_hits::cpu0                   10709                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1                   10684                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu2                   10837                       # number of ReadReq hits
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+system.l2c.ReadReq_hits::cpu7                   10772                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                  85828                       # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks           76131                       # number of Writeback hits
+system.l2c.Writeback_hits::total                76131                       # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu0                  391                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1                  342                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu2                  290                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu3                  349                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu4                  346                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu5                  350                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu6                  327                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu7                  361                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                2756                       # number of UpgradeReq hits
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+system.l2c.ReadExReq_hits::total                15515                       # number of ReadExReq hits
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+system.l2c.demand_hits::total                  101343                       # number of demand (read+write) hits
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+system.l2c.overall_hits::total                 101343                       # number of overall hits
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+system.l2c.ReadReq_misses::cpu5                   661                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu6                   687                       # number of ReadReq misses
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+system.l2c.UpgradeReq_misses::cpu0               1900                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1               1921                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu2               1938                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu3               1929                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu4               1958                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu5               1980                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu6               1936                       # number of UpgradeReq misses
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+system.l2c.UpgradeReq_misses::total             15471                       # number of UpgradeReq misses
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+system.l2c.ReadExReq_misses::total              35194                       # number of ReadExReq misses
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+system.l2c.demand_misses::total                 40746                       # number of demand (read+write) misses
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+system.l2c.overall_misses::cpu6                  5090                       # number of overall misses
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+system.l2c.overall_misses::total                40746                       # number of overall misses
+system.l2c.ReadReq_miss_latency::cpu0        44350412                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1        42088920                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu2        42842422                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu3        43387924                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu4        44233435                       # number of ReadReq miss cycles
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+system.l2c.UpgradeReq_miss_latency::cpu0     53982500                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu1     57751996                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu2     56478495                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu3     54930999                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu4     55403495                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu5     57236497                       # number of UpgradeReq miss cycles
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+system.l2c.Writeback_accesses::total            76131                       # number of Writeback accesses(hits+misses)
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+system.l2c.UpgradeReq_accesses::cpu3             2278                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu4             2304                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu5             2330                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu6             2263                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu7             2270                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total           18227                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0              6303                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1              6325                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu2              6299                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu3              6336                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu4              6403                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu5              6471                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu6              6326                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu7              6246                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total            50709                       # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0                17723                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1                17686                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2                17822                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu3                17766                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu4                17795                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu5                17804                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu6                17780                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu7                17713                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total              142089                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0               17723                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1               17686                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2               17822                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu3               17766                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu4               17795                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu5               17804                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu6               17780                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu7               17713                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total             142089                       # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu0           0.062259                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1           0.059590                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu2           0.059533                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu3           0.061592                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu4           0.064168                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu5           0.058325                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu6           0.059979                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu7           0.060609                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.060757                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0        0.829332                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1        0.848873                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu2        0.869838                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu3        0.846795                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu4        0.849826                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu5        0.849785                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu6        0.855502                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu7        0.840969                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.848796                       # miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0         0.691099                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1         0.690909                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu2         0.698206                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu3         0.691288                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu4         0.688740                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu5         0.700974                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu6         0.696016                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu7         0.695005                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.694039                       # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu0            0.285900                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1            0.285367                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2            0.285265                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu3            0.286165                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu4            0.288901                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu5            0.291901                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu6            0.286277                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu7            0.284311                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.286764                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0           0.285900                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1           0.285367                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2           0.285265                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu3           0.286165                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu4           0.288901                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu5           0.291901                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu6           0.286277                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu7           0.284311                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.286764                       # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::cpu0 62377.513361                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1 62169.748892                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu2 62452.510204                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu3 61630.573864                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu4 60510.854993                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu5 61168.568835                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu6 61551.557496                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu7 62294.117986                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 61764.385627                       # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu0 28411.842105                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1 30063.506507                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu2 29142.670279                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu3 28476.412131                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu4 28295.962717                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu5 28907.321717                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu6 29543.387397                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu7 28235.201152                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total 28885.073945                       # average UpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0 53890.598714                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1 53907.423341                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu2 53720.656435                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu3 53860.604566                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu4 53889.443991                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu5 53861.318122                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu6 53943.320463                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu7 53817.424326                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 53861.369807                       # average ReadExReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0 55081.480166                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1 55015.724193                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2 54898.872738                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu3 54936.540519                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu4 54830.943980                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu5 54790.718299                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu6 54970.208251                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu7 54987.261914                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 54938.225053                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0 55081.480166                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1 55015.724193                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2 54898.872738                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu3 54936.540519                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu4 54830.943980                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu5 54790.718299                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu6 54970.208251                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu7 54987.261914                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 54938.225053                       # average overall miss latency
+system.l2c.blocked_cycles::no_mshrs             12282                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
-system.l2c.blocked::no_mshrs                     1906                       # number of cycles access was blocked
+system.l2c.blocked::no_mshrs                     1706                       # number of cycles access was blocked
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs      7.076076                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs      7.199297                       # average number of cycles each access was blocked
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks                6233                       # number of writebacks
-system.l2c.writebacks::total                     6233                       # number of writebacks
-system.l2c.ReadReq_mshr_hits::cpu0                  6                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu1                  8                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu2                  8                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu3                  3                       # number of ReadReq MSHR hits
+system.l2c.writebacks::writebacks                6093                       # number of writebacks
+system.l2c.writebacks::total                     6093                       # number of writebacks
+system.l2c.ReadReq_mshr_hits::cpu0                  1                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu1                  4                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu2                  2                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu3                  7                       # number of ReadReq MSHR hits
 system.l2c.ReadReq_mshr_hits::cpu4                  6                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu5                  4                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu6                  5                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu7                  5                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::total                45                       # number of ReadReq MSHR hits
-system.l2c.UpgradeReq_mshr_hits::cpu0               1                       # number of UpgradeReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu5                 10                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu6                  1                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu7                  7                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::total                38                       # number of ReadReq MSHR hits
+system.l2c.UpgradeReq_mshr_hits::cpu2               1                       # number of UpgradeReq MSHR hits
 system.l2c.UpgradeReq_mshr_hits::cpu3               1                       # number of UpgradeReq MSHR hits
-system.l2c.UpgradeReq_mshr_hits::total              2                       # number of UpgradeReq MSHR hits
-system.l2c.ReadExReq_mshr_hits::cpu0                3                       # number of ReadExReq MSHR hits
-system.l2c.ReadExReq_mshr_hits::cpu1                3                       # number of ReadExReq MSHR hits
+system.l2c.UpgradeReq_mshr_hits::cpu4               1                       # number of UpgradeReq MSHR hits
+system.l2c.UpgradeReq_mshr_hits::total              3                       # number of UpgradeReq MSHR hits
+system.l2c.ReadExReq_mshr_hits::cpu0                2                       # number of ReadExReq MSHR hits
+system.l2c.ReadExReq_mshr_hits::cpu1                6                       # number of ReadExReq MSHR hits
 system.l2c.ReadExReq_mshr_hits::cpu2                3                       # number of ReadExReq MSHR hits
-system.l2c.ReadExReq_mshr_hits::cpu3                3                       # number of ReadExReq MSHR hits
-system.l2c.ReadExReq_mshr_hits::cpu4                5                       # number of ReadExReq MSHR hits
-system.l2c.ReadExReq_mshr_hits::cpu5                6                       # number of ReadExReq MSHR hits
-system.l2c.ReadExReq_mshr_hits::cpu6                4                       # number of ReadExReq MSHR hits
-system.l2c.ReadExReq_mshr_hits::cpu7                3                       # number of ReadExReq MSHR hits
-system.l2c.ReadExReq_mshr_hits::total              30                       # number of ReadExReq MSHR hits
-system.l2c.demand_mshr_hits::cpu0                   9                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1                  11                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu2                  11                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu3                   6                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu4                  11                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu5                  10                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu6                   9                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu7                   8                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total                 75                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits::cpu0                  9                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1                 11                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu2                 11                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu3                  6                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu4                 11                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu5                 10                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu6                  9                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu7                  8                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total                75                       # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses::cpu0              745                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1              734                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu2              736                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu3              693                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu4              721                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu5              731                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu6              703                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu7              693                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total            5756                       # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0          1963                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1          1929                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu2          1920                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu3          1879                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu4          1830                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu5          1887                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu6          1921                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu7          1963                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total        15292                       # number of UpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu0           4318                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1           4350                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu2           4355                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu3           4230                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu4           4356                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu5           4398                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu6           4220                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu7           4314                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total         34541                       # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses::cpu0              5063                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1              5084                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2              5091                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu3              4923                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu4              5077                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu5              5129                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu6              4923                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu7              5007                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total            40297                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu0             5063                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1             5084                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2             5091                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu3             4923                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu4             5077                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu5             5129                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu6             4923                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu7             5007                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total           40297                       # number of overall MSHR misses
-system.l2c.ReadReq_mshr_miss_latency::cpu0     37430000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1     36700000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu2     36861500                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu3     34765499                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu4     36517000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu5     35579500                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu6     34789500                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu7     34507000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total    287149999                       # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu0     80503500                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1     79250000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu2     78828500                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu3     77220000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu4     75116000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu5     77478500                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu6     78872500                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu7     80473500                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total    627742500                       # number of UpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu0    179980999                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1    181689000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu2    182122000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu3    177202499                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu4    181963000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu5    184511000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu6    176480500                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu7    180371999                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total   1444320997                       # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0    217410999                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1    218389000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2    218983500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu3    211967998                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu4    218480000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu5    220090500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu6    211270000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu7    214878999                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total   1731470996                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0    217410999                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1    218389000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2    218983500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu3    211967998                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu4    218480000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu5    220090500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu6    211270000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu7    214878999                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total   1731470996                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0    408599000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1    409928000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu2    408199000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu3    411446500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu4    412339500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu5    409840000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu6    407063000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu7    414602500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total   3282017500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu0    219448000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1    222166000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu2    226500000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu3    227574000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu4    224253000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu5    222853000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu6    225951500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu7    221581000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total   1790326500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0    628047000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1    632094000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu2    634699000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu3    639020500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu4    636592500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu5    632693000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu6    633014500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu7    636183500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total   5072344000                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu0      0.065431                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1      0.064990                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu2      0.064067                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu3      0.060240                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu4      0.062969                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu5      0.063659                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu6      0.061489                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu7      0.060073                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.062856                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0     0.854965                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1     0.856952                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu2     0.850687                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu3     0.841092                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu4     0.846438                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu5     0.842411                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu6     0.846256                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu7     0.838531                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.847155                       # mshr miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0     0.690769                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1     0.700145                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu2     0.699486                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu3     0.695381                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu4     0.698973                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu5     0.707871                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu6     0.683180                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu7     0.698623                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.696813                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0       0.287067                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1       0.290398                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2       0.287400                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu3       0.279923                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu4       0.287128                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu5       0.289840                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu6       0.279557                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu7       0.282706                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.285503                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0      0.287067                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1      0.290398                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2      0.287400                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu3      0.279923                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu4      0.287128                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu5      0.289840                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu6      0.279557                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu7      0.282706                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.285503                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 50241.610738                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1        50000                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 50083.559783                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 50166.665224                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 50647.711512                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 48672.366621                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 49487.197724                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 49793.650794                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 49887.074183                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 41010.443199                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 41083.462934                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 41056.510417                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 41096.327834                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 41046.994536                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 41059.088500                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 41058.042686                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 40995.160469                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 41050.385823                       # average UpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 41681.565308                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 41767.586207                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 41819.058553                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 41891.843735                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 41772.956841                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 41953.387904                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 41820.023697                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 41810.848169                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 41814.683912                       # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0 42941.141418                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1 42956.136900                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2 43013.847967                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3 43056.672354                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu4 43033.287374                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu5 42910.996296                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu6 42914.889295                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu7 42915.717795                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 42967.739435                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0 42941.141418                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1 42956.136900                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2 43013.847967                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3 43056.672354                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu4 43033.287374                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu5 42910.996296                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu6 42914.889295                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu7 42915.717795                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 42967.739435                       # average overall mshr miss latency
+system.l2c.ReadExReq_mshr_hits::cpu3                6                       # number of ReadExReq MSHR hits
+system.l2c.ReadExReq_mshr_hits::cpu4                6                       # number of ReadExReq MSHR hits
+system.l2c.ReadExReq_mshr_hits::cpu5                2                       # number of ReadExReq MSHR hits
+system.l2c.ReadExReq_mshr_hits::cpu6                6                       # number of ReadExReq MSHR hits
+system.l2c.ReadExReq_mshr_hits::cpu7                4                       # number of ReadExReq MSHR hits
+system.l2c.ReadExReq_mshr_hits::total              35                       # number of ReadExReq MSHR hits
+system.l2c.demand_mshr_hits::cpu0                   3                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu1                  10                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu2                   5                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu3                  13                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu4                  12                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu5                  12                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu6                   7                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu7                  11                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::total                 73                       # number of demand (read+write) MSHR hits
+system.l2c.overall_mshr_hits::cpu0                  3                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu1                 10                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu2                  5                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu3                 13                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu4                 12                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu5                 12                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu6                  7                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu7                 11                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::total                73                       # number of overall MSHR hits
+system.l2c.ReadReq_mshr_misses::cpu0              710                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1              673                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu2              684                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu3              697                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu4              725                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu5              651                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu6              686                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu7              688                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::total            5514                       # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu0          1900                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1          1921                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu2          1937                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu3          1928                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu4          1957                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu5          1980                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu6          1936                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu7          1909                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total        15468                       # number of UpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu0           4354                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu1           4364                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu2           4395                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu3           4374                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu4           4404                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu5           4534                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu6           4397                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu7           4337                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total         35159                       # number of ReadExReq MSHR misses
+system.l2c.demand_mshr_misses::cpu0              5064                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1              5037                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu2              5079                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu3              5071                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu4              5129                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu5              5185                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu6              5083                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu7              5025                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total            40673                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu0             5064                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1             5037                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu2             5079                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu3             5071                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu4             5129                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu5             5185                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu6             5083                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu7             5025                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total           40673                       # number of overall MSHR misses
+system.l2c.ReadReq_mshr_miss_latency::cpu0     35751412                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1     33806921                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu2     34429923                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu3     34692924                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu4     35248936                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu5     32226426                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu6     33940420                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu7     34712413                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total    274809375                       # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu0     77994997                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1     78725495                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu2     79510490                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu3     79106497                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu4     80259995                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu5     81257495                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu6     79519997                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu7     78273997                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total    634648963                       # number of UpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu0    181946449                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1    182532940                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu2    182934447                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu3    182700448                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu4    184033448                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu5    189305939                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu6    184033940                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu7    180980939                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total   1468468550                       # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0    217697861                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1    216339861                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2    217364370                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu3    217393372                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu4    219282384                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu5    221532365                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu6    217974360                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu7    215693352                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total   1743277925                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0    217697861                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1    216339861                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2    217364370                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu3    217393372                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu4    219282384                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu5    221532365                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu6    217974360                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu7    215693352                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total   1743277925                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0    401967952                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1    402344948                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu2    400970454                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu3    406380953                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu4    407457452                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu5    405842942                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu6    405383447                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu7    402958951                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total   3233307099                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu0    231807968                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1    231164475                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu2    229115474                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu3    232479973                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu4    225183971                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu5    232284466                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu6    236479465                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu7    230210970                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total   1848726762                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0    633775920                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1    633509423                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu2    630085928                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu3    638860926                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu4    632641423                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu5    638127408                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu6    641862912                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu7    633169921                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total   5082033861                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu0      0.062172                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1      0.059238                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2      0.059360                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu3      0.060980                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu4      0.063641                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu5      0.057443                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu6      0.059892                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu7      0.059998                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.060341                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0     0.829332                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1     0.848873                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu2     0.869390                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu3     0.846356                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu4     0.849392                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu5     0.849785                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu6     0.855502                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu7     0.840969                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.848631                       # mshr miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0     0.690782                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1     0.689960                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu2     0.697730                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu3     0.690341                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu4     0.687803                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu5     0.700665                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu6     0.695068                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu7     0.694364                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.693348                       # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0       0.285730                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1       0.284802                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2       0.284985                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu3       0.285433                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu4       0.288227                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu5       0.291227                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu6       0.285883                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu7       0.283690                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.286250                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0      0.285730                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1      0.284802                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2      0.284985                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu3      0.285433                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu4      0.288227                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu5      0.291227                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu6      0.285883                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu7      0.283690                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.286250                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 50354.101408                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 50233.166419                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 50336.144737                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 49774.639885                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 48619.222069                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 49502.958525                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 49475.830904                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 50454.088663                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 49838.479325                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 41049.998421                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 40981.517439                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 41048.265359                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 41030.340768                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 41011.750128                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 41039.138889                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 41074.378616                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 41002.617601                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 41029.801073                       # average UpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 41788.343822                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 41826.979835                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 41623.309898                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 41769.649749                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 41787.794732                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 41752.522938                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 41854.432568                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 41729.522481                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 41766.505020                       # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0 42989.309044                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1 42950.141155                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2 42796.686356                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3 42869.921514                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu4 42753.438097                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu5 42725.624879                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu6 42883.013968                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu7 42924.050149                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 42860.814914                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0 42989.309044                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1 42950.141155                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2 42796.686356                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3 42869.921514                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu4 42753.438097                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu5 42725.624879                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu6 42883.013968                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu7 42924.050149                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 42860.814914                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2          inf                       # average ReadReq mshr uncacheable latency
@@ -688,169 +689,169 @@ system.l2c.overall_avg_mshr_uncacheable_latency::total          inf
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
 system.funcbus.throughput                           0                       # Throughput (bytes/s)
 system.funcbus.data_through_bus                     0                       # Total data (bytes)
-system.toL2Bus.throughput                 51078499831                       # Throughput (bytes/s)
-system.toL2Bus.trans_dist::ReadReq             368070                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp            368059                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadRespWithInvalidate            1                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             42367                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            42365                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback            74336                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq           28719                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp          28718                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           155928                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          155926                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side       118285                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side       118639                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side       118896                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side       119078                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side       118813                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side       118602                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side       118904                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side       119137                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total                950354                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side      1731443                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side      1726092                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side      1741657                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side      1748194                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side      1742487                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side      1735937                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side      1741406                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side      1745057                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size::total           13912273                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.data_through_bus              13912273                       # Total data (bytes)
-system.toL2Bus.snoop_data_through_bus        19421888                       # Total snoop data (bytes)
-system.toL2Bus.reqLayer0.occupancy          652560490                       # Layer occupancy (ticks)
-system.toL2Bus.reqLayer0.utilization            100.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy         157373515                       # Layer occupancy (ticks)
+system.toL2Bus.throughput                 51067763763                       # Throughput (bytes/s)
+system.toL2Bus.trans_dist::ReadReq             370706                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp            370692                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadRespWithInvalidate            3                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq             43929                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp            43926                       # Transaction distribution
+system.toL2Bus.trans_dist::Writeback            76131                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq           28975                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp          28973                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq           161585                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp          161579                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side       120187                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side       120466                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side       120142                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side       120511                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side       120525                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side       120784                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side       120880                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side       120421                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total                963916                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side      1756245                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side      1754904                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side      1765350                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side      1754211                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side      1769359                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side      1771216                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side      1757581                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side      1758989                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size::total           14087855                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.data_through_bus              14087855                       # Total data (bytes)
+system.toL2Bus.snoop_data_through_bus        19957440                       # Total snoop data (bytes)
+system.toL2Bus.reqLayer0.occupancy          655042579                       # Layer occupancy (ticks)
+system.toL2Bus.reqLayer0.utilization             98.3                       # Layer utilization (%)
+system.toL2Bus.respLayer0.occupancy         160407425                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization            24.1                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy         158243013                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy         161285735                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization            24.2                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy         157858027                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer2.utilization            24.2                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy         157862988                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer3.utilization            24.2                       # Layer utilization (%)
-system.toL2Bus.respLayer4.occupancy         158148657                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer4.utilization            24.2                       # Layer utilization (%)
-system.toL2Bus.respLayer5.occupancy         157838676                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer5.utilization            24.2                       # Layer utilization (%)
-system.toL2Bus.respLayer6.occupancy         158178516                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy         160748299                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.utilization            24.1                       # Layer utilization (%)
+system.toL2Bus.respLayer3.occupancy         160702936                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.utilization            24.1                       # Layer utilization (%)
+system.toL2Bus.respLayer4.occupancy         160745511                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer4.utilization            24.1                       # Layer utilization (%)
+system.toL2Bus.respLayer5.occupancy         160832963                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer5.utilization            24.1                       # Layer utilization (%)
+system.toL2Bus.respLayer6.occupancy         161488791                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer6.utilization            24.2                       # Layer utilization (%)
-system.toL2Bus.respLayer7.occupancy         157763244                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer7.utilization            24.2                       # Layer utilization (%)
-system.cpu0.num_reads                           98977                       # number of read accesses completed
-system.cpu0.num_writes                          53590                       # number of write accesses completed
+system.toL2Bus.respLayer7.occupancy         160912467                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer7.utilization            24.1                       # Layer utilization (%)
+system.cpu0.num_reads                           99051                       # number of read accesses completed
+system.cpu0.num_writes                          54715                       # number of write accesses completed
 system.cpu0.num_copies                              0                       # number of copy accesses completed
-system.cpu0.l1c.tags.replacements               21970                       # number of replacements
-system.cpu0.l1c.tags.tagsinuse             393.709596                       # Cycle average of tags in use
-system.cpu0.l1c.tags.total_refs                 13350                       # Total number of references to valid blocks.
-system.cpu0.l1c.tags.sampled_refs               22370                       # Sample count of references to valid blocks.
-system.cpu0.l1c.tags.avg_refs                0.596781                       # Average number of references to valid blocks.
+system.cpu0.l1c.tags.replacements               22485                       # number of replacements
+system.cpu0.l1c.tags.tagsinuse             393.562401                       # Cycle average of tags in use
+system.cpu0.l1c.tags.total_refs                 13294                       # Total number of references to valid blocks.
+system.cpu0.l1c.tags.sampled_refs               22895                       # Sample count of references to valid blocks.
+system.cpu0.l1c.tags.avg_refs                0.580651                       # Average number of references to valid blocks.
 system.cpu0.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
-system.cpu0.l1c.tags.occ_blocks::cpu0      393.709596                       # Average occupied blocks per requestor
-system.cpu0.l1c.tags.occ_percent::cpu0       0.768964                       # Average percentage of cache occupancy
-system.cpu0.l1c.tags.occ_percent::total      0.768964                       # Average percentage of cache occupancy
-system.cpu0.l1c.tags.occ_task_id_blocks::1024          400                       # Occupied blocks per task id
-system.cpu0.l1c.tags.age_task_id_blocks_1024::0          380                       # Occupied blocks per task id
-system.cpu0.l1c.tags.age_task_id_blocks_1024::1           20                       # Occupied blocks per task id
-system.cpu0.l1c.tags.occ_task_id_percent::1024     0.781250                       # Percentage of cache occupancy per task id
-system.cpu0.l1c.tags.tag_accesses              330568                       # Number of tag accesses
-system.cpu0.l1c.tags.data_accesses             330568                       # Number of data accesses
-system.cpu0.l1c.ReadReq_hits::cpu0               8685                       # number of ReadReq hits
-system.cpu0.l1c.ReadReq_hits::total              8685                       # number of ReadReq hits
-system.cpu0.l1c.WriteReq_hits::cpu0              1118                       # number of WriteReq hits
-system.cpu0.l1c.WriteReq_hits::total             1118                       # number of WriteReq hits
-system.cpu0.l1c.demand_hits::cpu0                9803                       # number of demand (read+write) hits
-system.cpu0.l1c.demand_hits::total               9803                       # number of demand (read+write) hits
-system.cpu0.l1c.overall_hits::cpu0               9803                       # number of overall hits
-system.cpu0.l1c.overall_hits::total              9803                       # number of overall hits
-system.cpu0.l1c.ReadReq_misses::cpu0            35704                       # number of ReadReq misses
-system.cpu0.l1c.ReadReq_misses::total           35704                       # number of ReadReq misses
-system.cpu0.l1c.WriteReq_misses::cpu0           23289                       # number of WriteReq misses
-system.cpu0.l1c.WriteReq_misses::total          23289                       # number of WriteReq misses
-system.cpu0.l1c.demand_misses::cpu0             58993                       # number of demand (read+write) misses
-system.cpu0.l1c.demand_misses::total            58993                       # number of demand (read+write) misses
-system.cpu0.l1c.overall_misses::cpu0            58993                       # number of overall misses
-system.cpu0.l1c.overall_misses::total           58993                       # number of overall misses
-system.cpu0.l1c.ReadReq_miss_latency::cpu0    937059642                       # number of ReadReq miss cycles
-system.cpu0.l1c.ReadReq_miss_latency::total    937059642                       # number of ReadReq miss cycles
-system.cpu0.l1c.WriteReq_miss_latency::cpu0    866806760                       # number of WriteReq miss cycles
-system.cpu0.l1c.WriteReq_miss_latency::total    866806760                       # number of WriteReq miss cycles
-system.cpu0.l1c.demand_miss_latency::cpu0   1803866402                       # number of demand (read+write) miss cycles
-system.cpu0.l1c.demand_miss_latency::total   1803866402                       # number of demand (read+write) miss cycles
-system.cpu0.l1c.overall_miss_latency::cpu0   1803866402                       # number of overall miss cycles
-system.cpu0.l1c.overall_miss_latency::total   1803866402                       # number of overall miss cycles
-system.cpu0.l1c.ReadReq_accesses::cpu0          44389                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l1c.ReadReq_accesses::total         44389                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l1c.WriteReq_accesses::cpu0         24407                       # number of WriteReq accesses(hits+misses)
-system.cpu0.l1c.WriteReq_accesses::total        24407                       # number of WriteReq accesses(hits+misses)
-system.cpu0.l1c.demand_accesses::cpu0           68796                       # number of demand (read+write) accesses
-system.cpu0.l1c.demand_accesses::total          68796                       # number of demand (read+write) accesses
-system.cpu0.l1c.overall_accesses::cpu0          68796                       # number of overall (read+write) accesses
-system.cpu0.l1c.overall_accesses::total         68796                       # number of overall (read+write) accesses
-system.cpu0.l1c.ReadReq_miss_rate::cpu0      0.804343                       # miss rate for ReadReq accesses
-system.cpu0.l1c.ReadReq_miss_rate::total     0.804343                       # miss rate for ReadReq accesses
-system.cpu0.l1c.WriteReq_miss_rate::cpu0     0.954193                       # miss rate for WriteReq accesses
-system.cpu0.l1c.WriteReq_miss_rate::total     0.954193                       # miss rate for WriteReq accesses
-system.cpu0.l1c.demand_miss_rate::cpu0       0.857506                       # miss rate for demand accesses
-system.cpu0.l1c.demand_miss_rate::total      0.857506                       # miss rate for demand accesses
-system.cpu0.l1c.overall_miss_rate::cpu0      0.857506                       # miss rate for overall accesses
-system.cpu0.l1c.overall_miss_rate::total     0.857506                       # miss rate for overall accesses
-system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 26245.228602                       # average ReadReq miss latency
-system.cpu0.l1c.ReadReq_avg_miss_latency::total 26245.228602                       # average ReadReq miss latency
-system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 37219.578342                       # average WriteReq miss latency
-system.cpu0.l1c.WriteReq_avg_miss_latency::total 37219.578342                       # average WriteReq miss latency
-system.cpu0.l1c.demand_avg_miss_latency::cpu0 30577.634669                       # average overall miss latency
-system.cpu0.l1c.demand_avg_miss_latency::total 30577.634669                       # average overall miss latency
-system.cpu0.l1c.overall_avg_miss_latency::cpu0 30577.634669                       # average overall miss latency
-system.cpu0.l1c.overall_avg_miss_latency::total 30577.634669                       # average overall miss latency
-system.cpu0.l1c.blocked_cycles::no_mshrs      1018391                       # number of cycles access was blocked
+system.cpu0.l1c.tags.occ_blocks::cpu0      393.562401                       # Average occupied blocks per requestor
+system.cpu0.l1c.tags.occ_percent::cpu0       0.768677                       # Average percentage of cache occupancy
+system.cpu0.l1c.tags.occ_percent::total      0.768677                       # Average percentage of cache occupancy
+system.cpu0.l1c.tags.occ_task_id_blocks::1024          410                       # Occupied blocks per task id
+system.cpu0.l1c.tags.age_task_id_blocks_1024::0          376                       # Occupied blocks per task id
+system.cpu0.l1c.tags.age_task_id_blocks_1024::1           34                       # Occupied blocks per task id
+system.cpu0.l1c.tags.occ_task_id_percent::1024     0.800781                       # Percentage of cache occupancy per task id
+system.cpu0.l1c.tags.tag_accesses              336265                       # Number of tag accesses
+system.cpu0.l1c.tags.data_accesses             336265                       # Number of data accesses
+system.cpu0.l1c.ReadReq_hits::cpu0               8671                       # number of ReadReq hits
+system.cpu0.l1c.ReadReq_hits::total              8671                       # number of ReadReq hits
+system.cpu0.l1c.WriteReq_hits::cpu0              1068                       # number of WriteReq hits
+system.cpu0.l1c.WriteReq_hits::total             1068                       # number of WriteReq hits
+system.cpu0.l1c.demand_hits::cpu0                9739                       # number of demand (read+write) hits
+system.cpu0.l1c.demand_hits::total               9739                       # number of demand (read+write) hits
+system.cpu0.l1c.overall_hits::cpu0               9739                       # number of overall hits
+system.cpu0.l1c.overall_hits::total              9739                       # number of overall hits
+system.cpu0.l1c.ReadReq_misses::cpu0            36428                       # number of ReadReq misses
+system.cpu0.l1c.ReadReq_misses::total           36428                       # number of ReadReq misses
+system.cpu0.l1c.WriteReq_misses::cpu0           23756                       # number of WriteReq misses
+system.cpu0.l1c.WriteReq_misses::total          23756                       # number of WriteReq misses
+system.cpu0.l1c.demand_misses::cpu0             60184                       # number of demand (read+write) misses
+system.cpu0.l1c.demand_misses::total            60184                       # number of demand (read+write) misses
+system.cpu0.l1c.overall_misses::cpu0            60184                       # number of overall misses
+system.cpu0.l1c.overall_misses::total           60184                       # number of overall misses
+system.cpu0.l1c.ReadReq_miss_latency::cpu0    963275637                       # number of ReadReq miss cycles
+system.cpu0.l1c.ReadReq_miss_latency::total    963275637                       # number of ReadReq miss cycles
+system.cpu0.l1c.WriteReq_miss_latency::cpu0    887897909                       # number of WriteReq miss cycles
+system.cpu0.l1c.WriteReq_miss_latency::total    887897909                       # number of WriteReq miss cycles
+system.cpu0.l1c.demand_miss_latency::cpu0   1851173546                       # number of demand (read+write) miss cycles
+system.cpu0.l1c.demand_miss_latency::total   1851173546                       # number of demand (read+write) miss cycles
+system.cpu0.l1c.overall_miss_latency::cpu0   1851173546                       # number of overall miss cycles
+system.cpu0.l1c.overall_miss_latency::total   1851173546                       # number of overall miss cycles
+system.cpu0.l1c.ReadReq_accesses::cpu0          45099                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l1c.ReadReq_accesses::total         45099                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l1c.WriteReq_accesses::cpu0         24824                       # number of WriteReq accesses(hits+misses)
+system.cpu0.l1c.WriteReq_accesses::total        24824                       # number of WriteReq accesses(hits+misses)
+system.cpu0.l1c.demand_accesses::cpu0           69923                       # number of demand (read+write) accesses
+system.cpu0.l1c.demand_accesses::total          69923                       # number of demand (read+write) accesses
+system.cpu0.l1c.overall_accesses::cpu0          69923                       # number of overall (read+write) accesses
+system.cpu0.l1c.overall_accesses::total         69923                       # number of overall (read+write) accesses
+system.cpu0.l1c.ReadReq_miss_rate::cpu0      0.807734                       # miss rate for ReadReq accesses
+system.cpu0.l1c.ReadReq_miss_rate::total     0.807734                       # miss rate for ReadReq accesses
+system.cpu0.l1c.WriteReq_miss_rate::cpu0     0.956977                       # miss rate for WriteReq accesses
+system.cpu0.l1c.WriteReq_miss_rate::total     0.956977                       # miss rate for WriteReq accesses
+system.cpu0.l1c.demand_miss_rate::cpu0       0.860718                       # miss rate for demand accesses
+system.cpu0.l1c.demand_miss_rate::total      0.860718                       # miss rate for demand accesses
+system.cpu0.l1c.overall_miss_rate::cpu0      0.860718                       # miss rate for overall accesses
+system.cpu0.l1c.overall_miss_rate::total     0.860718                       # miss rate for overall accesses
+system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 26443.275420                       # average ReadReq miss latency
+system.cpu0.l1c.ReadReq_avg_miss_latency::total 26443.275420                       # average ReadReq miss latency
+system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 37375.732825                       # average WriteReq miss latency
+system.cpu0.l1c.WriteReq_avg_miss_latency::total 37375.732825                       # average WriteReq miss latency
+system.cpu0.l1c.demand_avg_miss_latency::cpu0 30758.566164                       # average overall miss latency
+system.cpu0.l1c.demand_avg_miss_latency::total 30758.566164                       # average overall miss latency
+system.cpu0.l1c.overall_avg_miss_latency::cpu0 30758.566164                       # average overall miss latency
+system.cpu0.l1c.overall_avg_miss_latency::total 30758.566164                       # average overall miss latency
+system.cpu0.l1c.blocked_cycles::no_mshrs      1029913                       # number of cycles access was blocked
 system.cpu0.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.l1c.blocked::no_mshrs               62068                       # number of cycles access was blocked
+system.cpu0.l1c.blocked::no_mshrs               62692                       # number of cycles access was blocked
 system.cpu0.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
-system.cpu0.l1c.avg_blocked_cycles::no_mshrs    16.407666                       # average number of cycles each access was blocked
+system.cpu0.l1c.avg_blocked_cycles::no_mshrs    16.428141                       # average number of cycles each access was blocked
 system.cpu0.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.l1c.fast_writes                         0                       # number of fast writes performed
 system.cpu0.l1c.cache_copies                        0                       # number of cache copies performed
-system.cpu0.l1c.writebacks::writebacks           9494                       # number of writebacks
-system.cpu0.l1c.writebacks::total                9494                       # number of writebacks
-system.cpu0.l1c.ReadReq_mshr_misses::cpu0        35704                       # number of ReadReq MSHR misses
-system.cpu0.l1c.ReadReq_mshr_misses::total        35704                       # number of ReadReq MSHR misses
-system.cpu0.l1c.WriteReq_mshr_misses::cpu0        23289                       # number of WriteReq MSHR misses
-system.cpu0.l1c.WriteReq_mshr_misses::total        23289                       # number of WriteReq MSHR misses
-system.cpu0.l1c.demand_mshr_misses::cpu0        58993                       # number of demand (read+write) MSHR misses
-system.cpu0.l1c.demand_mshr_misses::total        58993                       # number of demand (read+write) MSHR misses
-system.cpu0.l1c.overall_mshr_misses::cpu0        58993                       # number of overall MSHR misses
-system.cpu0.l1c.overall_mshr_misses::total        58993                       # number of overall MSHR misses
-system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0    860700776                       # number of ReadReq MSHR miss cycles
-system.cpu0.l1c.ReadReq_mshr_miss_latency::total    860700776                       # number of ReadReq MSHR miss cycles
-system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0    817560778                       # number of WriteReq MSHR miss cycles
-system.cpu0.l1c.WriteReq_mshr_miss_latency::total    817560778                       # number of WriteReq MSHR miss cycles
-system.cpu0.l1c.demand_mshr_miss_latency::cpu0   1678261554                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l1c.demand_mshr_miss_latency::total   1678261554                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l1c.overall_mshr_miss_latency::cpu0   1678261554                       # number of overall MSHR miss cycles
-system.cpu0.l1c.overall_mshr_miss_latency::total   1678261554                       # number of overall MSHR miss cycles
-system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0    703193894                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total    703193894                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0   1636775658                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total   1636775658                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0   2339969552                       # number of overall MSHR uncacheable cycles
-system.cpu0.l1c.overall_mshr_uncacheable_latency::total   2339969552                       # number of overall MSHR uncacheable cycles
-system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0     0.804343                       # mshr miss rate for ReadReq accesses
-system.cpu0.l1c.ReadReq_mshr_miss_rate::total     0.804343                       # mshr miss rate for ReadReq accesses
-system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0     0.954193                       # mshr miss rate for WriteReq accesses
-system.cpu0.l1c.WriteReq_mshr_miss_rate::total     0.954193                       # mshr miss rate for WriteReq accesses
-system.cpu0.l1c.demand_mshr_miss_rate::cpu0     0.857506                       # mshr miss rate for demand accesses
-system.cpu0.l1c.demand_mshr_miss_rate::total     0.857506                       # mshr miss rate for demand accesses
-system.cpu0.l1c.overall_mshr_miss_rate::cpu0     0.857506                       # mshr miss rate for overall accesses
-system.cpu0.l1c.overall_mshr_miss_rate::total     0.857506                       # mshr miss rate for overall accesses
-system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 24106.564419                       # average ReadReq mshr miss latency
-system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 24106.564419                       # average ReadReq mshr miss latency
-system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 35105.018592                       # average WriteReq mshr miss latency
-system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 35105.018592                       # average WriteReq mshr miss latency
-system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 28448.486329                       # average overall mshr miss latency
-system.cpu0.l1c.demand_avg_mshr_miss_latency::total 28448.486329                       # average overall mshr miss latency
-system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 28448.486329                       # average overall mshr miss latency
-system.cpu0.l1c.overall_avg_mshr_miss_latency::total 28448.486329                       # average overall mshr miss latency
+system.cpu0.l1c.writebacks::writebacks           9798                       # number of writebacks
+system.cpu0.l1c.writebacks::total                9798                       # number of writebacks
+system.cpu0.l1c.ReadReq_mshr_misses::cpu0        36428                       # number of ReadReq MSHR misses
+system.cpu0.l1c.ReadReq_mshr_misses::total        36428                       # number of ReadReq MSHR misses
+system.cpu0.l1c.WriteReq_mshr_misses::cpu0        23756                       # number of WriteReq MSHR misses
+system.cpu0.l1c.WriteReq_mshr_misses::total        23756                       # number of WriteReq MSHR misses
+system.cpu0.l1c.demand_mshr_misses::cpu0        60184                       # number of demand (read+write) MSHR misses
+system.cpu0.l1c.demand_mshr_misses::total        60184                       # number of demand (read+write) MSHR misses
+system.cpu0.l1c.overall_mshr_misses::cpu0        60184                       # number of overall MSHR misses
+system.cpu0.l1c.overall_mshr_misses::total        60184                       # number of overall MSHR misses
+system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0    885441811                       # number of ReadReq MSHR miss cycles
+system.cpu0.l1c.ReadReq_mshr_miss_latency::total    885441811                       # number of ReadReq MSHR miss cycles
+system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0    837618111                       # number of WriteReq MSHR miss cycles
+system.cpu0.l1c.WriteReq_mshr_miss_latency::total    837618111                       # number of WriteReq MSHR miss cycles
+system.cpu0.l1c.demand_mshr_miss_latency::cpu0   1723059922                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l1c.demand_mshr_miss_latency::total   1723059922                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l1c.overall_mshr_miss_latency::cpu0   1723059922                       # number of overall MSHR miss cycles
+system.cpu0.l1c.overall_mshr_miss_latency::total   1723059922                       # number of overall MSHR miss cycles
+system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0    694921548                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total    694921548                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0   1720175961                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total   1720175961                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0   2415097509                       # number of overall MSHR uncacheable cycles
+system.cpu0.l1c.overall_mshr_uncacheable_latency::total   2415097509                       # number of overall MSHR uncacheable cycles
+system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0     0.807734                       # mshr miss rate for ReadReq accesses
+system.cpu0.l1c.ReadReq_mshr_miss_rate::total     0.807734                       # mshr miss rate for ReadReq accesses
+system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0     0.956977                       # mshr miss rate for WriteReq accesses
+system.cpu0.l1c.WriteReq_mshr_miss_rate::total     0.956977                       # mshr miss rate for WriteReq accesses
+system.cpu0.l1c.demand_mshr_miss_rate::cpu0     0.860718                       # mshr miss rate for demand accesses
+system.cpu0.l1c.demand_mshr_miss_rate::total     0.860718                       # mshr miss rate for demand accesses
+system.cpu0.l1c.overall_mshr_miss_rate::cpu0     0.860718                       # mshr miss rate for overall accesses
+system.cpu0.l1c.overall_mshr_miss_rate::total     0.860718                       # mshr miss rate for overall accesses
+system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 24306.627073                       # average ReadReq mshr miss latency
+system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 24306.627073                       # average ReadReq mshr miss latency
+system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 35259.223396                       # average WriteReq mshr miss latency
+system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 35259.223396                       # average WriteReq mshr miss latency
+system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 28629.867108                       # average overall mshr miss latency
+system.cpu0.l1c.demand_avg_mshr_miss_latency::total 28629.867108                       # average overall mshr miss latency
+system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 28629.867108                       # average overall mshr miss latency
+system.cpu0.l1c.overall_avg_mshr_miss_latency::total 28629.867108                       # average overall mshr miss latency
 system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0          inf                       # average WriteReq mshr uncacheable latency
@@ -858,120 +859,120 @@ system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total          inf
 system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0          inf                       # average overall mshr uncacheable latency
 system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu0.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
-system.cpu1.num_reads                           99824                       # number of read accesses completed
-system.cpu1.num_writes                          53636                       # number of write accesses completed
+system.cpu1.num_reads                           99180                       # number of read accesses completed
+system.cpu1.num_writes                          55130                       # number of write accesses completed
 system.cpu1.num_copies                              0                       # number of copy accesses completed
-system.cpu1.l1c.tags.replacements               22223                       # number of replacements
-system.cpu1.l1c.tags.tagsinuse             395.298418                       # Cycle average of tags in use
-system.cpu1.l1c.tags.total_refs                 13436                       # Total number of references to valid blocks.
-system.cpu1.l1c.tags.sampled_refs               22630                       # Sample count of references to valid blocks.
-system.cpu1.l1c.tags.avg_refs                0.593725                       # Average number of references to valid blocks.
+system.cpu1.l1c.tags.replacements               22560                       # number of replacements
+system.cpu1.l1c.tags.tagsinuse             393.358014                       # Cycle average of tags in use
+system.cpu1.l1c.tags.total_refs                 13364                       # Total number of references to valid blocks.
+system.cpu1.l1c.tags.sampled_refs               22961                       # Sample count of references to valid blocks.
+system.cpu1.l1c.tags.avg_refs                0.582030                       # Average number of references to valid blocks.
 system.cpu1.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
-system.cpu1.l1c.tags.occ_blocks::cpu1      395.298418                       # Average occupied blocks per requestor
-system.cpu1.l1c.tags.occ_percent::cpu1       0.772067                       # Average percentage of cache occupancy
-system.cpu1.l1c.tags.occ_percent::total      0.772067                       # Average percentage of cache occupancy
-system.cpu1.l1c.tags.occ_task_id_blocks::1024          407                       # Occupied blocks per task id
-system.cpu1.l1c.tags.age_task_id_blocks_1024::0          374                       # Occupied blocks per task id
-system.cpu1.l1c.tags.age_task_id_blocks_1024::1           33                       # Occupied blocks per task id
-system.cpu1.l1c.tags.occ_task_id_percent::1024     0.794922                       # Percentage of cache occupancy per task id
-system.cpu1.l1c.tags.tag_accesses              332439                       # Number of tag accesses
-system.cpu1.l1c.tags.data_accesses             332439                       # Number of data accesses
-system.cpu1.l1c.ReadReq_hits::cpu1               8757                       # number of ReadReq hits
-system.cpu1.l1c.ReadReq_hits::total              8757                       # number of ReadReq hits
-system.cpu1.l1c.WriteReq_hits::cpu1              1135                       # number of WriteReq hits
-system.cpu1.l1c.WriteReq_hits::total             1135                       # number of WriteReq hits
-system.cpu1.l1c.demand_hits::cpu1                9892                       # number of demand (read+write) hits
-system.cpu1.l1c.demand_hits::total               9892                       # number of demand (read+write) hits
-system.cpu1.l1c.overall_hits::cpu1               9892                       # number of overall hits
-system.cpu1.l1c.overall_hits::total              9892                       # number of overall hits
-system.cpu1.l1c.ReadReq_misses::cpu1            36260                       # number of ReadReq misses
-system.cpu1.l1c.ReadReq_misses::total           36260                       # number of ReadReq misses
-system.cpu1.l1c.WriteReq_misses::cpu1           23033                       # number of WriteReq misses
-system.cpu1.l1c.WriteReq_misses::total          23033                       # number of WriteReq misses
-system.cpu1.l1c.demand_misses::cpu1             59293                       # number of demand (read+write) misses
-system.cpu1.l1c.demand_misses::total            59293                       # number of demand (read+write) misses
-system.cpu1.l1c.overall_misses::cpu1            59293                       # number of overall misses
-system.cpu1.l1c.overall_misses::total           59293                       # number of overall misses
-system.cpu1.l1c.ReadReq_miss_latency::cpu1    947629716                       # number of ReadReq miss cycles
-system.cpu1.l1c.ReadReq_miss_latency::total    947629716                       # number of ReadReq miss cycles
-system.cpu1.l1c.WriteReq_miss_latency::cpu1    858813201                       # number of WriteReq miss cycles
-system.cpu1.l1c.WriteReq_miss_latency::total    858813201                       # number of WriteReq miss cycles
-system.cpu1.l1c.demand_miss_latency::cpu1   1806442917                       # number of demand (read+write) miss cycles
-system.cpu1.l1c.demand_miss_latency::total   1806442917                       # number of demand (read+write) miss cycles
-system.cpu1.l1c.overall_miss_latency::cpu1   1806442917                       # number of overall miss cycles
-system.cpu1.l1c.overall_miss_latency::total   1806442917                       # number of overall miss cycles
-system.cpu1.l1c.ReadReq_accesses::cpu1          45017                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l1c.ReadReq_accesses::total         45017                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l1c.WriteReq_accesses::cpu1         24168                       # number of WriteReq accesses(hits+misses)
-system.cpu1.l1c.WriteReq_accesses::total        24168                       # number of WriteReq accesses(hits+misses)
-system.cpu1.l1c.demand_accesses::cpu1           69185                       # number of demand (read+write) accesses
-system.cpu1.l1c.demand_accesses::total          69185                       # number of demand (read+write) accesses
-system.cpu1.l1c.overall_accesses::cpu1          69185                       # number of overall (read+write) accesses
-system.cpu1.l1c.overall_accesses::total         69185                       # number of overall (read+write) accesses
-system.cpu1.l1c.ReadReq_miss_rate::cpu1      0.805473                       # miss rate for ReadReq accesses
-system.cpu1.l1c.ReadReq_miss_rate::total     0.805473                       # miss rate for ReadReq accesses
-system.cpu1.l1c.WriteReq_miss_rate::cpu1     0.953037                       # miss rate for WriteReq accesses
-system.cpu1.l1c.WriteReq_miss_rate::total     0.953037                       # miss rate for WriteReq accesses
-system.cpu1.l1c.demand_miss_rate::cpu1       0.857021                       # miss rate for demand accesses
-system.cpu1.l1c.demand_miss_rate::total      0.857021                       # miss rate for demand accesses
-system.cpu1.l1c.overall_miss_rate::cpu1      0.857021                       # miss rate for overall accesses
-system.cpu1.l1c.overall_miss_rate::total     0.857021                       # miss rate for overall accesses
-system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 26134.299945                       # average ReadReq miss latency
-system.cpu1.l1c.ReadReq_avg_miss_latency::total 26134.299945                       # average ReadReq miss latency
-system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 37286.206790                       # average WriteReq miss latency
-system.cpu1.l1c.WriteReq_avg_miss_latency::total 37286.206790                       # average WriteReq miss latency
-system.cpu1.l1c.demand_avg_miss_latency::cpu1 30466.377431                       # average overall miss latency
-system.cpu1.l1c.demand_avg_miss_latency::total 30466.377431                       # average overall miss latency
-system.cpu1.l1c.overall_avg_miss_latency::cpu1 30466.377431                       # average overall miss latency
-system.cpu1.l1c.overall_avg_miss_latency::total 30466.377431                       # average overall miss latency
-system.cpu1.l1c.blocked_cycles::no_mshrs      1020302                       # number of cycles access was blocked
+system.cpu1.l1c.tags.occ_blocks::cpu1      393.358014                       # Average occupied blocks per requestor
+system.cpu1.l1c.tags.occ_percent::cpu1       0.768277                       # Average percentage of cache occupancy
+system.cpu1.l1c.tags.occ_percent::total      0.768277                       # Average percentage of cache occupancy
+system.cpu1.l1c.tags.occ_task_id_blocks::1024          401                       # Occupied blocks per task id
+system.cpu1.l1c.tags.age_task_id_blocks_1024::0          382                       # Occupied blocks per task id
+system.cpu1.l1c.tags.age_task_id_blocks_1024::1           19                       # Occupied blocks per task id
+system.cpu1.l1c.tags.occ_task_id_percent::1024     0.783203                       # Percentage of cache occupancy per task id
+system.cpu1.l1c.tags.tag_accesses              338096                       # Number of tag accesses
+system.cpu1.l1c.tags.data_accesses             338096                       # Number of data accesses
+system.cpu1.l1c.ReadReq_hits::cpu1               8639                       # number of ReadReq hits
+system.cpu1.l1c.ReadReq_hits::total              8639                       # number of ReadReq hits
+system.cpu1.l1c.WriteReq_hits::cpu1              1152                       # number of WriteReq hits
+system.cpu1.l1c.WriteReq_hits::total             1152                       # number of WriteReq hits
+system.cpu1.l1c.demand_hits::cpu1                9791                       # number of demand (read+write) hits
+system.cpu1.l1c.demand_hits::total               9791                       # number of demand (read+write) hits
+system.cpu1.l1c.overall_hits::cpu1               9791                       # number of overall hits
+system.cpu1.l1c.overall_hits::total              9791                       # number of overall hits
+system.cpu1.l1c.ReadReq_misses::cpu1            36744                       # number of ReadReq misses
+system.cpu1.l1c.ReadReq_misses::total           36744                       # number of ReadReq misses
+system.cpu1.l1c.WriteReq_misses::cpu1           23766                       # number of WriteReq misses
+system.cpu1.l1c.WriteReq_misses::total          23766                       # number of WriteReq misses
+system.cpu1.l1c.demand_misses::cpu1             60510                       # number of demand (read+write) misses
+system.cpu1.l1c.demand_misses::total            60510                       # number of demand (read+write) misses
+system.cpu1.l1c.overall_misses::cpu1            60510                       # number of overall misses
+system.cpu1.l1c.overall_misses::total           60510                       # number of overall misses
+system.cpu1.l1c.ReadReq_miss_latency::cpu1    969995629                       # number of ReadReq miss cycles
+system.cpu1.l1c.ReadReq_miss_latency::total    969995629                       # number of ReadReq miss cycles
+system.cpu1.l1c.WriteReq_miss_latency::cpu1    886374819                       # number of WriteReq miss cycles
+system.cpu1.l1c.WriteReq_miss_latency::total    886374819                       # number of WriteReq miss cycles
+system.cpu1.l1c.demand_miss_latency::cpu1   1856370448                       # number of demand (read+write) miss cycles
+system.cpu1.l1c.demand_miss_latency::total   1856370448                       # number of demand (read+write) miss cycles
+system.cpu1.l1c.overall_miss_latency::cpu1   1856370448                       # number of overall miss cycles
+system.cpu1.l1c.overall_miss_latency::total   1856370448                       # number of overall miss cycles
+system.cpu1.l1c.ReadReq_accesses::cpu1          45383                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l1c.ReadReq_accesses::total         45383                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l1c.WriteReq_accesses::cpu1         24918                       # number of WriteReq accesses(hits+misses)
+system.cpu1.l1c.WriteReq_accesses::total        24918                       # number of WriteReq accesses(hits+misses)
+system.cpu1.l1c.demand_accesses::cpu1           70301                       # number of demand (read+write) accesses
+system.cpu1.l1c.demand_accesses::total          70301                       # number of demand (read+write) accesses
+system.cpu1.l1c.overall_accesses::cpu1          70301                       # number of overall (read+write) accesses
+system.cpu1.l1c.overall_accesses::total         70301                       # number of overall (read+write) accesses
+system.cpu1.l1c.ReadReq_miss_rate::cpu1      0.809642                       # miss rate for ReadReq accesses
+system.cpu1.l1c.ReadReq_miss_rate::total     0.809642                       # miss rate for ReadReq accesses
+system.cpu1.l1c.WriteReq_miss_rate::cpu1     0.953768                       # miss rate for WriteReq accesses
+system.cpu1.l1c.WriteReq_miss_rate::total     0.953768                       # miss rate for WriteReq accesses
+system.cpu1.l1c.demand_miss_rate::cpu1       0.860727                       # miss rate for demand accesses
+system.cpu1.l1c.demand_miss_rate::total      0.860727                       # miss rate for demand accesses
+system.cpu1.l1c.overall_miss_rate::cpu1      0.860727                       # miss rate for overall accesses
+system.cpu1.l1c.overall_miss_rate::total     0.860727                       # miss rate for overall accesses
+system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 26398.748884                       # average ReadReq miss latency
+system.cpu1.l1c.ReadReq_avg_miss_latency::total 26398.748884                       # average ReadReq miss latency
+system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 37295.919339                       # average WriteReq miss latency
+system.cpu1.l1c.WriteReq_avg_miss_latency::total 37295.919339                       # average WriteReq miss latency
+system.cpu1.l1c.demand_avg_miss_latency::cpu1 30678.738192                       # average overall miss latency
+system.cpu1.l1c.demand_avg_miss_latency::total 30678.738192                       # average overall miss latency
+system.cpu1.l1c.overall_avg_miss_latency::cpu1 30678.738192                       # average overall miss latency
+system.cpu1.l1c.overall_avg_miss_latency::total 30678.738192                       # average overall miss latency
+system.cpu1.l1c.blocked_cycles::no_mshrs      1031479                       # number of cycles access was blocked
 system.cpu1.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.l1c.blocked::no_mshrs               62395                       # number of cycles access was blocked
+system.cpu1.l1c.blocked::no_mshrs               63034                       # number of cycles access was blocked
 system.cpu1.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
-system.cpu1.l1c.avg_blocked_cycles::no_mshrs    16.352304                       # average number of cycles each access was blocked
+system.cpu1.l1c.avg_blocked_cycles::no_mshrs    16.363851                       # average number of cycles each access was blocked
 system.cpu1.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.l1c.fast_writes                         0                       # number of fast writes performed
 system.cpu1.l1c.cache_copies                        0                       # number of cache copies performed
-system.cpu1.l1c.writebacks::writebacks           9512                       # number of writebacks
-system.cpu1.l1c.writebacks::total                9512                       # number of writebacks
-system.cpu1.l1c.ReadReq_mshr_misses::cpu1        36260                       # number of ReadReq MSHR misses
-system.cpu1.l1c.ReadReq_mshr_misses::total        36260                       # number of ReadReq MSHR misses
-system.cpu1.l1c.WriteReq_mshr_misses::cpu1        23033                       # number of WriteReq MSHR misses
-system.cpu1.l1c.WriteReq_mshr_misses::total        23033                       # number of WriteReq MSHR misses
-system.cpu1.l1c.demand_mshr_misses::cpu1        59293                       # number of demand (read+write) MSHR misses
-system.cpu1.l1c.demand_mshr_misses::total        59293                       # number of demand (read+write) MSHR misses
-system.cpu1.l1c.overall_mshr_misses::cpu1        59293                       # number of overall MSHR misses
-system.cpu1.l1c.overall_mshr_misses::total        59293                       # number of overall MSHR misses
-system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1    870111848                       # number of ReadReq MSHR miss cycles
-system.cpu1.l1c.ReadReq_mshr_miss_latency::total    870111848                       # number of ReadReq MSHR miss cycles
-system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1    810087173                       # number of WriteReq MSHR miss cycles
-system.cpu1.l1c.WriteReq_mshr_miss_latency::total    810087173                       # number of WriteReq MSHR miss cycles
-system.cpu1.l1c.demand_mshr_miss_latency::cpu1   1680199021                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l1c.demand_mshr_miss_latency::total   1680199021                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l1c.overall_mshr_miss_latency::cpu1   1680199021                       # number of overall MSHR miss cycles
-system.cpu1.l1c.overall_mshr_miss_latency::total   1680199021                       # number of overall MSHR miss cycles
-system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1    702431869                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total    702431869                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1   1631991143                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total   1631991143                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1   2334423012                       # number of overall MSHR uncacheable cycles
-system.cpu1.l1c.overall_mshr_uncacheable_latency::total   2334423012                       # number of overall MSHR uncacheable cycles
-system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1     0.805473                       # mshr miss rate for ReadReq accesses
-system.cpu1.l1c.ReadReq_mshr_miss_rate::total     0.805473                       # mshr miss rate for ReadReq accesses
-system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1     0.953037                       # mshr miss rate for WriteReq accesses
-system.cpu1.l1c.WriteReq_mshr_miss_rate::total     0.953037                       # mshr miss rate for WriteReq accesses
-system.cpu1.l1c.demand_mshr_miss_rate::cpu1     0.857021                       # mshr miss rate for demand accesses
-system.cpu1.l1c.demand_mshr_miss_rate::total     0.857021                       # mshr miss rate for demand accesses
-system.cpu1.l1c.overall_mshr_miss_rate::cpu1     0.857021                       # mshr miss rate for overall accesses
-system.cpu1.l1c.overall_mshr_miss_rate::total     0.857021                       # mshr miss rate for overall accesses
-system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 23996.465747                       # average ReadReq mshr miss latency
-system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 23996.465747                       # average ReadReq mshr miss latency
-system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 35170.719099                       # average WriteReq mshr miss latency
-system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 35170.719099                       # average WriteReq mshr miss latency
-system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 28337.223972                       # average overall mshr miss latency
-system.cpu1.l1c.demand_avg_mshr_miss_latency::total 28337.223972                       # average overall mshr miss latency
-system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 28337.223972                       # average overall mshr miss latency
-system.cpu1.l1c.overall_avg_mshr_miss_latency::total 28337.223972                       # average overall mshr miss latency
+system.cpu1.l1c.writebacks::writebacks           9822                       # number of writebacks
+system.cpu1.l1c.writebacks::total                9822                       # number of writebacks
+system.cpu1.l1c.ReadReq_mshr_misses::cpu1        36744                       # number of ReadReq MSHR misses
+system.cpu1.l1c.ReadReq_mshr_misses::total        36744                       # number of ReadReq MSHR misses
+system.cpu1.l1c.WriteReq_mshr_misses::cpu1        23766                       # number of WriteReq MSHR misses
+system.cpu1.l1c.WriteReq_mshr_misses::total        23766                       # number of WriteReq MSHR misses
+system.cpu1.l1c.demand_mshr_misses::cpu1        60510                       # number of demand (read+write) MSHR misses
+system.cpu1.l1c.demand_mshr_misses::total        60510                       # number of demand (read+write) MSHR misses
+system.cpu1.l1c.overall_mshr_misses::cpu1        60510                       # number of overall MSHR misses
+system.cpu1.l1c.overall_mshr_misses::total        60510                       # number of overall MSHR misses
+system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1    891488909                       # number of ReadReq MSHR miss cycles
+system.cpu1.l1c.ReadReq_mshr_miss_latency::total    891488909                       # number of ReadReq MSHR miss cycles
+system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1    836075987                       # number of WriteReq MSHR miss cycles
+system.cpu1.l1c.WriteReq_mshr_miss_latency::total    836075987                       # number of WriteReq MSHR miss cycles
+system.cpu1.l1c.demand_mshr_miss_latency::cpu1   1727564896                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l1c.demand_mshr_miss_latency::total   1727564896                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l1c.overall_mshr_miss_latency::cpu1   1727564896                       # number of overall MSHR miss cycles
+system.cpu1.l1c.overall_mshr_miss_latency::total   1727564896                       # number of overall MSHR miss cycles
+system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1    694858067                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total    694858067                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1   1710734008                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total   1710734008                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1   2405592075                       # number of overall MSHR uncacheable cycles
+system.cpu1.l1c.overall_mshr_uncacheable_latency::total   2405592075                       # number of overall MSHR uncacheable cycles
+system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1     0.809642                       # mshr miss rate for ReadReq accesses
+system.cpu1.l1c.ReadReq_mshr_miss_rate::total     0.809642                       # mshr miss rate for ReadReq accesses
+system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1     0.953768                       # mshr miss rate for WriteReq accesses
+system.cpu1.l1c.WriteReq_mshr_miss_rate::total     0.953768                       # mshr miss rate for WriteReq accesses
+system.cpu1.l1c.demand_mshr_miss_rate::cpu1     0.860727                       # mshr miss rate for demand accesses
+system.cpu1.l1c.demand_mshr_miss_rate::total     0.860727                       # mshr miss rate for demand accesses
+system.cpu1.l1c.overall_mshr_miss_rate::cpu1     0.860727                       # mshr miss rate for overall accesses
+system.cpu1.l1c.overall_mshr_miss_rate::total     0.860727                       # mshr miss rate for overall accesses
+system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 24262.162775                       # average ReadReq mshr miss latency
+system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 24262.162775                       # average ReadReq mshr miss latency
+system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 35179.499579                       # average WriteReq mshr miss latency
+system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 35179.499579                       # average WriteReq mshr miss latency
+system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 28550.072649                       # average overall mshr miss latency
+system.cpu1.l1c.demand_avg_mshr_miss_latency::total 28550.072649                       # average overall mshr miss latency
+system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 28550.072649                       # average overall mshr miss latency
+system.cpu1.l1c.overall_avg_mshr_miss_latency::total 28550.072649                       # average overall mshr miss latency
 system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1          inf                       # average WriteReq mshr uncacheable latency
@@ -979,120 +980,120 @@ system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total          inf
 system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1          inf                       # average overall mshr uncacheable latency
 system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu1.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
-system.cpu2.num_reads                           99336                       # number of read accesses completed
-system.cpu2.num_writes                          53403                       # number of write accesses completed
+system.cpu2.num_reads                           99086                       # number of read accesses completed
+system.cpu2.num_writes                          55118                       # number of write accesses completed
 system.cpu2.num_copies                              0                       # number of copy accesses completed
-system.cpu2.l1c.tags.replacements               22214                       # number of replacements
-system.cpu2.l1c.tags.tagsinuse             394.859577                       # Cycle average of tags in use
-system.cpu2.l1c.tags.total_refs                 13307                       # Total number of references to valid blocks.
-system.cpu2.l1c.tags.sampled_refs               22614                       # Sample count of references to valid blocks.
-system.cpu2.l1c.tags.avg_refs                0.588441                       # Average number of references to valid blocks.
+system.cpu2.l1c.tags.replacements               22404                       # number of replacements
+system.cpu2.l1c.tags.tagsinuse             393.163299                       # Cycle average of tags in use
+system.cpu2.l1c.tags.total_refs                 13438                       # Total number of references to valid blocks.
+system.cpu2.l1c.tags.sampled_refs               22793                       # Sample count of references to valid blocks.
+system.cpu2.l1c.tags.avg_refs                0.589567                       # Average number of references to valid blocks.
 system.cpu2.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
-system.cpu2.l1c.tags.occ_blocks::cpu2      394.859577                       # Average occupied blocks per requestor
-system.cpu2.l1c.tags.occ_percent::cpu2       0.771210                       # Average percentage of cache occupancy
-system.cpu2.l1c.tags.occ_percent::total      0.771210                       # Average percentage of cache occupancy
-system.cpu2.l1c.tags.occ_task_id_blocks::1024          400                       # Occupied blocks per task id
-system.cpu2.l1c.tags.age_task_id_blocks_1024::0          381                       # Occupied blocks per task id
-system.cpu2.l1c.tags.age_task_id_blocks_1024::1           19                       # Occupied blocks per task id
-system.cpu2.l1c.tags.occ_task_id_percent::1024     0.781250                       # Percentage of cache occupancy per task id
-system.cpu2.l1c.tags.tag_accesses              331261                       # Number of tag accesses
-system.cpu2.l1c.tags.data_accesses             331261                       # Number of data accesses
-system.cpu2.l1c.ReadReq_hits::cpu2               8708                       # number of ReadReq hits
-system.cpu2.l1c.ReadReq_hits::total              8708                       # number of ReadReq hits
-system.cpu2.l1c.WriteReq_hits::cpu2              1070                       # number of WriteReq hits
-system.cpu2.l1c.WriteReq_hits::total             1070                       # number of WriteReq hits
-system.cpu2.l1c.demand_hits::cpu2                9778                       # number of demand (read+write) hits
-system.cpu2.l1c.demand_hits::total               9778                       # number of demand (read+write) hits
-system.cpu2.l1c.overall_hits::cpu2               9778                       # number of overall hits
-system.cpu2.l1c.overall_hits::total              9778                       # number of overall hits
-system.cpu2.l1c.ReadReq_misses::cpu2            36160                       # number of ReadReq misses
-system.cpu2.l1c.ReadReq_misses::total           36160                       # number of ReadReq misses
-system.cpu2.l1c.WriteReq_misses::cpu2           22990                       # number of WriteReq misses
-system.cpu2.l1c.WriteReq_misses::total          22990                       # number of WriteReq misses
-system.cpu2.l1c.demand_misses::cpu2             59150                       # number of demand (read+write) misses
-system.cpu2.l1c.demand_misses::total            59150                       # number of demand (read+write) misses
-system.cpu2.l1c.overall_misses::cpu2            59150                       # number of overall misses
-system.cpu2.l1c.overall_misses::total           59150                       # number of overall misses
-system.cpu2.l1c.ReadReq_miss_latency::cpu2    947354858                       # number of ReadReq miss cycles
-system.cpu2.l1c.ReadReq_miss_latency::total    947354858                       # number of ReadReq miss cycles
-system.cpu2.l1c.WriteReq_miss_latency::cpu2    856510547                       # number of WriteReq miss cycles
-system.cpu2.l1c.WriteReq_miss_latency::total    856510547                       # number of WriteReq miss cycles
-system.cpu2.l1c.demand_miss_latency::cpu2   1803865405                       # number of demand (read+write) miss cycles
-system.cpu2.l1c.demand_miss_latency::total   1803865405                       # number of demand (read+write) miss cycles
-system.cpu2.l1c.overall_miss_latency::cpu2   1803865405                       # number of overall miss cycles
-system.cpu2.l1c.overall_miss_latency::total   1803865405                       # number of overall miss cycles
-system.cpu2.l1c.ReadReq_accesses::cpu2          44868                       # number of ReadReq accesses(hits+misses)
-system.cpu2.l1c.ReadReq_accesses::total         44868                       # number of ReadReq accesses(hits+misses)
-system.cpu2.l1c.WriteReq_accesses::cpu2         24060                       # number of WriteReq accesses(hits+misses)
-system.cpu2.l1c.WriteReq_accesses::total        24060                       # number of WriteReq accesses(hits+misses)
-system.cpu2.l1c.demand_accesses::cpu2           68928                       # number of demand (read+write) accesses
-system.cpu2.l1c.demand_accesses::total          68928                       # number of demand (read+write) accesses
-system.cpu2.l1c.overall_accesses::cpu2          68928                       # number of overall (read+write) accesses
-system.cpu2.l1c.overall_accesses::total         68928                       # number of overall (read+write) accesses
-system.cpu2.l1c.ReadReq_miss_rate::cpu2      0.805920                       # miss rate for ReadReq accesses
-system.cpu2.l1c.ReadReq_miss_rate::total     0.805920                       # miss rate for ReadReq accesses
-system.cpu2.l1c.WriteReq_miss_rate::cpu2     0.955528                       # miss rate for WriteReq accesses
-system.cpu2.l1c.WriteReq_miss_rate::total     0.955528                       # miss rate for WriteReq accesses
-system.cpu2.l1c.demand_miss_rate::cpu2       0.858142                       # miss rate for demand accesses
-system.cpu2.l1c.demand_miss_rate::total      0.858142                       # miss rate for demand accesses
-system.cpu2.l1c.overall_miss_rate::cpu2      0.858142                       # miss rate for overall accesses
-system.cpu2.l1c.overall_miss_rate::total     0.858142                       # miss rate for overall accesses
-system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 26198.972843                       # average ReadReq miss latency
-system.cpu2.l1c.ReadReq_avg_miss_latency::total 26198.972843                       # average ReadReq miss latency
-system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 37255.787168                       # average WriteReq miss latency
-system.cpu2.l1c.WriteReq_avg_miss_latency::total 37255.787168                       # average WriteReq miss latency
-system.cpu2.l1c.demand_avg_miss_latency::cpu2 30496.456551                       # average overall miss latency
-system.cpu2.l1c.demand_avg_miss_latency::total 30496.456551                       # average overall miss latency
-system.cpu2.l1c.overall_avg_miss_latency::cpu2 30496.456551                       # average overall miss latency
-system.cpu2.l1c.overall_avg_miss_latency::total 30496.456551                       # average overall miss latency
-system.cpu2.l1c.blocked_cycles::no_mshrs      1016435                       # number of cycles access was blocked
+system.cpu2.l1c.tags.occ_blocks::cpu2      393.163299                       # Average occupied blocks per requestor
+system.cpu2.l1c.tags.occ_percent::cpu2       0.767897                       # Average percentage of cache occupancy
+system.cpu2.l1c.tags.occ_percent::total      0.767897                       # Average percentage of cache occupancy
+system.cpu2.l1c.tags.occ_task_id_blocks::1024          389                       # Occupied blocks per task id
+system.cpu2.l1c.tags.age_task_id_blocks_1024::0          372                       # Occupied blocks per task id
+system.cpu2.l1c.tags.age_task_id_blocks_1024::1           17                       # Occupied blocks per task id
+system.cpu2.l1c.tags.occ_task_id_percent::1024     0.759766                       # Percentage of cache occupancy per task id
+system.cpu2.l1c.tags.tag_accesses              337674                       # Number of tag accesses
+system.cpu2.l1c.tags.data_accesses             337674                       # Number of data accesses
+system.cpu2.l1c.ReadReq_hits::cpu2               8791                       # number of ReadReq hits
+system.cpu2.l1c.ReadReq_hits::total              8791                       # number of ReadReq hits
+system.cpu2.l1c.WriteReq_hits::cpu2              1160                       # number of WriteReq hits
+system.cpu2.l1c.WriteReq_hits::total             1160                       # number of WriteReq hits
+system.cpu2.l1c.demand_hits::cpu2                9951                       # number of demand (read+write) hits
+system.cpu2.l1c.demand_hits::total               9951                       # number of demand (read+write) hits
+system.cpu2.l1c.overall_hits::cpu2               9951                       # number of overall hits
+system.cpu2.l1c.overall_hits::total              9951                       # number of overall hits
+system.cpu2.l1c.ReadReq_misses::cpu2            36516                       # number of ReadReq misses
+system.cpu2.l1c.ReadReq_misses::total           36516                       # number of ReadReq misses
+system.cpu2.l1c.WriteReq_misses::cpu2           23770                       # number of WriteReq misses
+system.cpu2.l1c.WriteReq_misses::total          23770                       # number of WriteReq misses
+system.cpu2.l1c.demand_misses::cpu2             60286                       # number of demand (read+write) misses
+system.cpu2.l1c.demand_misses::total            60286                       # number of demand (read+write) misses
+system.cpu2.l1c.overall_misses::cpu2            60286                       # number of overall misses
+system.cpu2.l1c.overall_misses::total           60286                       # number of overall misses
+system.cpu2.l1c.ReadReq_miss_latency::cpu2    967487980                       # number of ReadReq miss cycles
+system.cpu2.l1c.ReadReq_miss_latency::total    967487980                       # number of ReadReq miss cycles
+system.cpu2.l1c.WriteReq_miss_latency::cpu2    890162777                       # number of WriteReq miss cycles
+system.cpu2.l1c.WriteReq_miss_latency::total    890162777                       # number of WriteReq miss cycles
+system.cpu2.l1c.demand_miss_latency::cpu2   1857650757                       # number of demand (read+write) miss cycles
+system.cpu2.l1c.demand_miss_latency::total   1857650757                       # number of demand (read+write) miss cycles
+system.cpu2.l1c.overall_miss_latency::cpu2   1857650757                       # number of overall miss cycles
+system.cpu2.l1c.overall_miss_latency::total   1857650757                       # number of overall miss cycles
+system.cpu2.l1c.ReadReq_accesses::cpu2          45307                       # number of ReadReq accesses(hits+misses)
+system.cpu2.l1c.ReadReq_accesses::total         45307                       # number of ReadReq accesses(hits+misses)
+system.cpu2.l1c.WriteReq_accesses::cpu2         24930                       # number of WriteReq accesses(hits+misses)
+system.cpu2.l1c.WriteReq_accesses::total        24930                       # number of WriteReq accesses(hits+misses)
+system.cpu2.l1c.demand_accesses::cpu2           70237                       # number of demand (read+write) accesses
+system.cpu2.l1c.demand_accesses::total          70237                       # number of demand (read+write) accesses
+system.cpu2.l1c.overall_accesses::cpu2          70237                       # number of overall (read+write) accesses
+system.cpu2.l1c.overall_accesses::total         70237                       # number of overall (read+write) accesses
+system.cpu2.l1c.ReadReq_miss_rate::cpu2      0.805968                       # miss rate for ReadReq accesses
+system.cpu2.l1c.ReadReq_miss_rate::total     0.805968                       # miss rate for ReadReq accesses
+system.cpu2.l1c.WriteReq_miss_rate::cpu2     0.953470                       # miss rate for WriteReq accesses
+system.cpu2.l1c.WriteReq_miss_rate::total     0.953470                       # miss rate for WriteReq accesses
+system.cpu2.l1c.demand_miss_rate::cpu2       0.858323                       # miss rate for demand accesses
+system.cpu2.l1c.demand_miss_rate::total      0.858323                       # miss rate for demand accesses
+system.cpu2.l1c.overall_miss_rate::cpu2      0.858323                       # miss rate for overall accesses
+system.cpu2.l1c.overall_miss_rate::total     0.858323                       # miss rate for overall accesses
+system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 26494.905795                       # average ReadReq miss latency
+system.cpu2.l1c.ReadReq_avg_miss_latency::total 26494.905795                       # average ReadReq miss latency
+system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 37449.001977                       # average WriteReq miss latency
+system.cpu2.l1c.WriteReq_avg_miss_latency::total 37449.001977                       # average WriteReq miss latency
+system.cpu2.l1c.demand_avg_miss_latency::cpu2 30813.966045                       # average overall miss latency
+system.cpu2.l1c.demand_avg_miss_latency::total 30813.966045                       # average overall miss latency
+system.cpu2.l1c.overall_avg_miss_latency::cpu2 30813.966045                       # average overall miss latency
+system.cpu2.l1c.overall_avg_miss_latency::total 30813.966045                       # average overall miss latency
+system.cpu2.l1c.blocked_cycles::no_mshrs      1030263                       # number of cycles access was blocked
 system.cpu2.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu2.l1c.blocked::no_mshrs               62092                       # number of cycles access was blocked
+system.cpu2.l1c.blocked::no_mshrs               62774                       # number of cycles access was blocked
 system.cpu2.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
-system.cpu2.l1c.avg_blocked_cycles::no_mshrs    16.369822                       # average number of cycles each access was blocked
+system.cpu2.l1c.avg_blocked_cycles::no_mshrs    16.412257                       # average number of cycles each access was blocked
 system.cpu2.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu2.l1c.fast_writes                         0                       # number of fast writes performed
 system.cpu2.l1c.cache_copies                        0                       # number of cache copies performed
-system.cpu2.l1c.writebacks::writebacks           9582                       # number of writebacks
-system.cpu2.l1c.writebacks::total                9582                       # number of writebacks
-system.cpu2.l1c.ReadReq_mshr_misses::cpu2        36160                       # number of ReadReq MSHR misses
-system.cpu2.l1c.ReadReq_mshr_misses::total        36160                       # number of ReadReq MSHR misses
-system.cpu2.l1c.WriteReq_mshr_misses::cpu2        22990                       # number of WriteReq MSHR misses
-system.cpu2.l1c.WriteReq_mshr_misses::total        22990                       # number of WriteReq MSHR misses
-system.cpu2.l1c.demand_mshr_misses::cpu2        59150                       # number of demand (read+write) MSHR misses
-system.cpu2.l1c.demand_mshr_misses::total        59150                       # number of demand (read+write) MSHR misses
-system.cpu2.l1c.overall_mshr_misses::cpu2        59150                       # number of overall MSHR misses
-system.cpu2.l1c.overall_mshr_misses::total        59150                       # number of overall MSHR misses
-system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2    870067956                       # number of ReadReq MSHR miss cycles
-system.cpu2.l1c.ReadReq_mshr_miss_latency::total    870067956                       # number of ReadReq MSHR miss cycles
-system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2    807866531                       # number of WriteReq MSHR miss cycles
-system.cpu2.l1c.WriteReq_mshr_miss_latency::total    807866531                       # number of WriteReq MSHR miss cycles
-system.cpu2.l1c.demand_mshr_miss_latency::cpu2   1677934487                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.l1c.demand_mshr_miss_latency::total   1677934487                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.l1c.overall_mshr_miss_latency::cpu2   1677934487                       # number of overall MSHR miss cycles
-system.cpu2.l1c.overall_mshr_miss_latency::total   1677934487                       # number of overall MSHR miss cycles
-system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2    699720514                       # number of ReadReq MSHR uncacheable cycles
-system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total    699720514                       # number of ReadReq MSHR uncacheable cycles
-system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2   1649553128                       # number of WriteReq MSHR uncacheable cycles
-system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total   1649553128                       # number of WriteReq MSHR uncacheable cycles
-system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2   2349273642                       # number of overall MSHR uncacheable cycles
-system.cpu2.l1c.overall_mshr_uncacheable_latency::total   2349273642                       # number of overall MSHR uncacheable cycles
-system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2     0.805920                       # mshr miss rate for ReadReq accesses
-system.cpu2.l1c.ReadReq_mshr_miss_rate::total     0.805920                       # mshr miss rate for ReadReq accesses
-system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2     0.955528                       # mshr miss rate for WriteReq accesses
-system.cpu2.l1c.WriteReq_mshr_miss_rate::total     0.955528                       # mshr miss rate for WriteReq accesses
-system.cpu2.l1c.demand_mshr_miss_rate::cpu2     0.858142                       # mshr miss rate for demand accesses
-system.cpu2.l1c.demand_mshr_miss_rate::total     0.858142                       # mshr miss rate for demand accesses
-system.cpu2.l1c.overall_mshr_miss_rate::cpu2     0.858142                       # mshr miss rate for overall accesses
-system.cpu2.l1c.overall_mshr_miss_rate::total     0.858142                       # mshr miss rate for overall accesses
-system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 24061.613827                       # average ReadReq mshr miss latency
-system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 24061.613827                       # average ReadReq mshr miss latency
-system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 35139.910004                       # average WriteReq mshr miss latency
-system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 35139.910004                       # average WriteReq mshr miss latency
-system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 28367.446948                       # average overall mshr miss latency
-system.cpu2.l1c.demand_avg_mshr_miss_latency::total 28367.446948                       # average overall mshr miss latency
-system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 28367.446948                       # average overall mshr miss latency
-system.cpu2.l1c.overall_avg_mshr_miss_latency::total 28367.446948                       # average overall mshr miss latency
+system.cpu2.l1c.writebacks::writebacks           9856                       # number of writebacks
+system.cpu2.l1c.writebacks::total                9856                       # number of writebacks
+system.cpu2.l1c.ReadReq_mshr_misses::cpu2        36516                       # number of ReadReq MSHR misses
+system.cpu2.l1c.ReadReq_mshr_misses::total        36516                       # number of ReadReq MSHR misses
+system.cpu2.l1c.WriteReq_mshr_misses::cpu2        23770                       # number of WriteReq MSHR misses
+system.cpu2.l1c.WriteReq_mshr_misses::total        23770                       # number of WriteReq MSHR misses
+system.cpu2.l1c.demand_mshr_misses::cpu2        60286                       # number of demand (read+write) MSHR misses
+system.cpu2.l1c.demand_mshr_misses::total        60286                       # number of demand (read+write) MSHR misses
+system.cpu2.l1c.overall_mshr_misses::cpu2        60286                       # number of overall MSHR misses
+system.cpu2.l1c.overall_mshr_misses::total        60286                       # number of overall MSHR misses
+system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2    889398318                       # number of ReadReq MSHR miss cycles
+system.cpu2.l1c.ReadReq_mshr_miss_latency::total    889398318                       # number of ReadReq MSHR miss cycles
+system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2    839809073                       # number of WriteReq MSHR miss cycles
+system.cpu2.l1c.WriteReq_mshr_miss_latency::total    839809073                       # number of WriteReq MSHR miss cycles
+system.cpu2.l1c.demand_mshr_miss_latency::cpu2   1729207391                       # number of demand (read+write) MSHR miss cycles
+system.cpu2.l1c.demand_mshr_miss_latency::total   1729207391                       # number of demand (read+write) MSHR miss cycles
+system.cpu2.l1c.overall_mshr_miss_latency::cpu2   1729207391                       # number of overall MSHR miss cycles
+system.cpu2.l1c.overall_mshr_miss_latency::total   1729207391                       # number of overall MSHR miss cycles
+system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2    693154089                       # number of ReadReq MSHR uncacheable cycles
+system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total    693154089                       # number of ReadReq MSHR uncacheable cycles
+system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2   1689336031                       # number of WriteReq MSHR uncacheable cycles
+system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total   1689336031                       # number of WriteReq MSHR uncacheable cycles
+system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2   2382490120                       # number of overall MSHR uncacheable cycles
+system.cpu2.l1c.overall_mshr_uncacheable_latency::total   2382490120                       # number of overall MSHR uncacheable cycles
+system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2     0.805968                       # mshr miss rate for ReadReq accesses
+system.cpu2.l1c.ReadReq_mshr_miss_rate::total     0.805968                       # mshr miss rate for ReadReq accesses
+system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2     0.953470                       # mshr miss rate for WriteReq accesses
+system.cpu2.l1c.WriteReq_mshr_miss_rate::total     0.953470                       # mshr miss rate for WriteReq accesses
+system.cpu2.l1c.demand_mshr_miss_rate::cpu2     0.858323                       # mshr miss rate for demand accesses
+system.cpu2.l1c.demand_mshr_miss_rate::total     0.858323                       # mshr miss rate for demand accesses
+system.cpu2.l1c.overall_mshr_miss_rate::cpu2     0.858323                       # mshr miss rate for overall accesses
+system.cpu2.l1c.overall_mshr_miss_rate::total     0.858323                       # mshr miss rate for overall accesses
+system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 24356.400427                       # average ReadReq mshr miss latency
+system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 24356.400427                       # average ReadReq mshr miss latency
+system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 35330.629912                       # average WriteReq mshr miss latency
+system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 35330.629912                       # average WriteReq mshr miss latency
+system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 28683.398982                       # average overall mshr miss latency
+system.cpu2.l1c.demand_avg_mshr_miss_latency::total 28683.398982                       # average overall mshr miss latency
+system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 28683.398982                       # average overall mshr miss latency
+system.cpu2.l1c.overall_avg_mshr_miss_latency::total 28683.398982                       # average overall mshr miss latency
 system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2          inf                       # average ReadReq mshr uncacheable latency
 system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2          inf                       # average WriteReq mshr uncacheable latency
@@ -1100,120 +1101,120 @@ system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total          inf
 system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2          inf                       # average overall mshr uncacheable latency
 system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu2.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
-system.cpu3.num_reads                          100000                       # number of read accesses completed
-system.cpu3.num_writes                          53536                       # number of write accesses completed
+system.cpu3.num_reads                           99021                       # number of read accesses completed
+system.cpu3.num_writes                          54970                       # number of write accesses completed
 system.cpu3.num_copies                              0                       # number of copy accesses completed
-system.cpu3.l1c.tags.replacements               22464                       # number of replacements
-system.cpu3.l1c.tags.tagsinuse             397.838914                       # Cycle average of tags in use
-system.cpu3.l1c.tags.total_refs                 13424                       # Total number of references to valid blocks.
-system.cpu3.l1c.tags.sampled_refs               22862                       # Sample count of references to valid blocks.
-system.cpu3.l1c.tags.avg_refs                0.587175                       # Average number of references to valid blocks.
+system.cpu3.l1c.tags.replacements               22272                       # number of replacements
+system.cpu3.l1c.tags.tagsinuse             393.391803                       # Cycle average of tags in use
+system.cpu3.l1c.tags.total_refs                 13521                       # Total number of references to valid blocks.
+system.cpu3.l1c.tags.sampled_refs               22662                       # Sample count of references to valid blocks.
+system.cpu3.l1c.tags.avg_refs                0.596638                       # Average number of references to valid blocks.
 system.cpu3.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
-system.cpu3.l1c.tags.occ_blocks::cpu3      397.838914                       # Average occupied blocks per requestor
-system.cpu3.l1c.tags.occ_percent::cpu3       0.777029                       # Average percentage of cache occupancy
-system.cpu3.l1c.tags.occ_percent::total      0.777029                       # Average percentage of cache occupancy
-system.cpu3.l1c.tags.occ_task_id_blocks::1024          398                       # Occupied blocks per task id
-system.cpu3.l1c.tags.age_task_id_blocks_1024::0          380                       # Occupied blocks per task id
-system.cpu3.l1c.tags.age_task_id_blocks_1024::1           18                       # Occupied blocks per task id
-system.cpu3.l1c.tags.occ_task_id_percent::1024     0.777344                       # Percentage of cache occupancy per task id
-system.cpu3.l1c.tags.tag_accesses              331508                       # Number of tag accesses
-system.cpu3.l1c.tags.data_accesses             331508                       # Number of data accesses
-system.cpu3.l1c.ReadReq_hits::cpu3               8781                       # number of ReadReq hits
-system.cpu3.l1c.ReadReq_hits::total              8781                       # number of ReadReq hits
-system.cpu3.l1c.WriteReq_hits::cpu3              1109                       # number of WriteReq hits
-system.cpu3.l1c.WriteReq_hits::total             1109                       # number of WriteReq hits
-system.cpu3.l1c.demand_hits::cpu3                9890                       # number of demand (read+write) hits
-system.cpu3.l1c.demand_hits::total               9890                       # number of demand (read+write) hits
-system.cpu3.l1c.overall_hits::cpu3               9890                       # number of overall hits
-system.cpu3.l1c.overall_hits::total              9890                       # number of overall hits
-system.cpu3.l1c.ReadReq_misses::cpu3            36107                       # number of ReadReq misses
-system.cpu3.l1c.ReadReq_misses::total           36107                       # number of ReadReq misses
-system.cpu3.l1c.WriteReq_misses::cpu3           23001                       # number of WriteReq misses
-system.cpu3.l1c.WriteReq_misses::total          23001                       # number of WriteReq misses
-system.cpu3.l1c.demand_misses::cpu3             59108                       # number of demand (read+write) misses
-system.cpu3.l1c.demand_misses::total            59108                       # number of demand (read+write) misses
-system.cpu3.l1c.overall_misses::cpu3            59108                       # number of overall misses
-system.cpu3.l1c.overall_misses::total           59108                       # number of overall misses
-system.cpu3.l1c.ReadReq_miss_latency::cpu3    940989779                       # number of ReadReq miss cycles
-system.cpu3.l1c.ReadReq_miss_latency::total    940989779                       # number of ReadReq miss cycles
-system.cpu3.l1c.WriteReq_miss_latency::cpu3    850325185                       # number of WriteReq miss cycles
-system.cpu3.l1c.WriteReq_miss_latency::total    850325185                       # number of WriteReq miss cycles
-system.cpu3.l1c.demand_miss_latency::cpu3   1791314964                       # number of demand (read+write) miss cycles
-system.cpu3.l1c.demand_miss_latency::total   1791314964                       # number of demand (read+write) miss cycles
-system.cpu3.l1c.overall_miss_latency::cpu3   1791314964                       # number of overall miss cycles
-system.cpu3.l1c.overall_miss_latency::total   1791314964                       # number of overall miss cycles
-system.cpu3.l1c.ReadReq_accesses::cpu3          44888                       # number of ReadReq accesses(hits+misses)
-system.cpu3.l1c.ReadReq_accesses::total         44888                       # number of ReadReq accesses(hits+misses)
-system.cpu3.l1c.WriteReq_accesses::cpu3         24110                       # number of WriteReq accesses(hits+misses)
-system.cpu3.l1c.WriteReq_accesses::total        24110                       # number of WriteReq accesses(hits+misses)
-system.cpu3.l1c.demand_accesses::cpu3           68998                       # number of demand (read+write) accesses
-system.cpu3.l1c.demand_accesses::total          68998                       # number of demand (read+write) accesses
-system.cpu3.l1c.overall_accesses::cpu3          68998                       # number of overall (read+write) accesses
-system.cpu3.l1c.overall_accesses::total         68998                       # number of overall (read+write) accesses
-system.cpu3.l1c.ReadReq_miss_rate::cpu3      0.804380                       # miss rate for ReadReq accesses
-system.cpu3.l1c.ReadReq_miss_rate::total     0.804380                       # miss rate for ReadReq accesses
-system.cpu3.l1c.WriteReq_miss_rate::cpu3     0.954002                       # miss rate for WriteReq accesses
-system.cpu3.l1c.WriteReq_miss_rate::total     0.954002                       # miss rate for WriteReq accesses
-system.cpu3.l1c.demand_miss_rate::cpu3       0.856663                       # miss rate for demand accesses
-system.cpu3.l1c.demand_miss_rate::total      0.856663                       # miss rate for demand accesses
-system.cpu3.l1c.overall_miss_rate::cpu3      0.856663                       # miss rate for overall accesses
-system.cpu3.l1c.overall_miss_rate::total     0.856663                       # miss rate for overall accesses
-system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 26061.145457                       # average ReadReq miss latency
-system.cpu3.l1c.ReadReq_avg_miss_latency::total 26061.145457                       # average ReadReq miss latency
-system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 36969.052867                       # average WriteReq miss latency
-system.cpu3.l1c.WriteReq_avg_miss_latency::total 36969.052867                       # average WriteReq miss latency
-system.cpu3.l1c.demand_avg_miss_latency::cpu3 30305.795561                       # average overall miss latency
-system.cpu3.l1c.demand_avg_miss_latency::total 30305.795561                       # average overall miss latency
-system.cpu3.l1c.overall_avg_miss_latency::cpu3 30305.795561                       # average overall miss latency
-system.cpu3.l1c.overall_avg_miss_latency::total 30305.795561                       # average overall miss latency
-system.cpu3.l1c.blocked_cycles::no_mshrs      1013074                       # number of cycles access was blocked
+system.cpu3.l1c.tags.occ_blocks::cpu3      393.391803                       # Average occupied blocks per requestor
+system.cpu3.l1c.tags.occ_percent::cpu3       0.768343                       # Average percentage of cache occupancy
+system.cpu3.l1c.tags.occ_percent::total      0.768343                       # Average percentage of cache occupancy
+system.cpu3.l1c.tags.occ_task_id_blocks::1024          390                       # Occupied blocks per task id
+system.cpu3.l1c.tags.age_task_id_blocks_1024::0          367                       # Occupied blocks per task id
+system.cpu3.l1c.tags.age_task_id_blocks_1024::1           23                       # Occupied blocks per task id
+system.cpu3.l1c.tags.occ_task_id_percent::1024     0.761719                       # Percentage of cache occupancy per task id
+system.cpu3.l1c.tags.tag_accesses              337590                       # Number of tag accesses
+system.cpu3.l1c.tags.data_accesses             337590                       # Number of data accesses
+system.cpu3.l1c.ReadReq_hits::cpu3               8806                       # number of ReadReq hits
+system.cpu3.l1c.ReadReq_hits::total              8806                       # number of ReadReq hits
+system.cpu3.l1c.WriteReq_hits::cpu3              1159                       # number of WriteReq hits
+system.cpu3.l1c.WriteReq_hits::total             1159                       # number of WriteReq hits
+system.cpu3.l1c.demand_hits::cpu3                9965                       # number of demand (read+write) hits
+system.cpu3.l1c.demand_hits::total               9965                       # number of demand (read+write) hits
+system.cpu3.l1c.overall_hits::cpu3               9965                       # number of overall hits
+system.cpu3.l1c.overall_hits::total              9965                       # number of overall hits
+system.cpu3.l1c.ReadReq_misses::cpu3            36397                       # number of ReadReq misses
+system.cpu3.l1c.ReadReq_misses::total           36397                       # number of ReadReq misses
+system.cpu3.l1c.WriteReq_misses::cpu3           23878                       # number of WriteReq misses
+system.cpu3.l1c.WriteReq_misses::total          23878                       # number of WriteReq misses
+system.cpu3.l1c.demand_misses::cpu3             60275                       # number of demand (read+write) misses
+system.cpu3.l1c.demand_misses::total            60275                       # number of demand (read+write) misses
+system.cpu3.l1c.overall_misses::cpu3            60275                       # number of overall misses
+system.cpu3.l1c.overall_misses::total           60275                       # number of overall misses
+system.cpu3.l1c.ReadReq_miss_latency::cpu3    959708337                       # number of ReadReq miss cycles
+system.cpu3.l1c.ReadReq_miss_latency::total    959708337                       # number of ReadReq miss cycles
+system.cpu3.l1c.WriteReq_miss_latency::cpu3    888157516                       # number of WriteReq miss cycles
+system.cpu3.l1c.WriteReq_miss_latency::total    888157516                       # number of WriteReq miss cycles
+system.cpu3.l1c.demand_miss_latency::cpu3   1847865853                       # number of demand (read+write) miss cycles
+system.cpu3.l1c.demand_miss_latency::total   1847865853                       # number of demand (read+write) miss cycles
+system.cpu3.l1c.overall_miss_latency::cpu3   1847865853                       # number of overall miss cycles
+system.cpu3.l1c.overall_miss_latency::total   1847865853                       # number of overall miss cycles
+system.cpu3.l1c.ReadReq_accesses::cpu3          45203                       # number of ReadReq accesses(hits+misses)
+system.cpu3.l1c.ReadReq_accesses::total         45203                       # number of ReadReq accesses(hits+misses)
+system.cpu3.l1c.WriteReq_accesses::cpu3         25037                       # number of WriteReq accesses(hits+misses)
+system.cpu3.l1c.WriteReq_accesses::total        25037                       # number of WriteReq accesses(hits+misses)
+system.cpu3.l1c.demand_accesses::cpu3           70240                       # number of demand (read+write) accesses
+system.cpu3.l1c.demand_accesses::total          70240                       # number of demand (read+write) accesses
+system.cpu3.l1c.overall_accesses::cpu3          70240                       # number of overall (read+write) accesses
+system.cpu3.l1c.overall_accesses::total         70240                       # number of overall (read+write) accesses
+system.cpu3.l1c.ReadReq_miss_rate::cpu3      0.805190                       # miss rate for ReadReq accesses
+system.cpu3.l1c.ReadReq_miss_rate::total     0.805190                       # miss rate for ReadReq accesses
+system.cpu3.l1c.WriteReq_miss_rate::cpu3     0.953709                       # miss rate for WriteReq accesses
+system.cpu3.l1c.WriteReq_miss_rate::total     0.953709                       # miss rate for WriteReq accesses
+system.cpu3.l1c.demand_miss_rate::cpu3       0.858129                       # miss rate for demand accesses
+system.cpu3.l1c.demand_miss_rate::total      0.858129                       # miss rate for demand accesses
+system.cpu3.l1c.overall_miss_rate::cpu3      0.858129                       # miss rate for overall accesses
+system.cpu3.l1c.overall_miss_rate::total     0.858129                       # miss rate for overall accesses
+system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 26367.786823                       # average ReadReq miss latency
+system.cpu3.l1c.ReadReq_avg_miss_latency::total 26367.786823                       # average ReadReq miss latency
+system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 37195.641008                       # average WriteReq miss latency
+system.cpu3.l1c.WriteReq_avg_miss_latency::total 37195.641008                       # average WriteReq miss latency
+system.cpu3.l1c.demand_avg_miss_latency::cpu3 30657.251813                       # average overall miss latency
+system.cpu3.l1c.demand_avg_miss_latency::total 30657.251813                       # average overall miss latency
+system.cpu3.l1c.overall_avg_miss_latency::cpu3 30657.251813                       # average overall miss latency
+system.cpu3.l1c.overall_avg_miss_latency::total 30657.251813                       # average overall miss latency
+system.cpu3.l1c.blocked_cycles::no_mshrs      1032981                       # number of cycles access was blocked
 system.cpu3.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu3.l1c.blocked::no_mshrs               62000                       # number of cycles access was blocked
+system.cpu3.l1c.blocked::no_mshrs               63001                       # number of cycles access was blocked
 system.cpu3.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
-system.cpu3.l1c.avg_blocked_cycles::no_mshrs    16.339903                       # average number of cycles each access was blocked
+system.cpu3.l1c.avg_blocked_cycles::no_mshrs    16.396264                       # average number of cycles each access was blocked
 system.cpu3.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu3.l1c.fast_writes                         0                       # number of fast writes performed
 system.cpu3.l1c.cache_copies                        0                       # number of cache copies performed
-system.cpu3.l1c.writebacks::writebacks           9786                       # number of writebacks
-system.cpu3.l1c.writebacks::total                9786                       # number of writebacks
-system.cpu3.l1c.ReadReq_mshr_misses::cpu3        36107                       # number of ReadReq MSHR misses
-system.cpu3.l1c.ReadReq_mshr_misses::total        36107                       # number of ReadReq MSHR misses
-system.cpu3.l1c.WriteReq_mshr_misses::cpu3        23001                       # number of WriteReq MSHR misses
-system.cpu3.l1c.WriteReq_mshr_misses::total        23001                       # number of WriteReq MSHR misses
-system.cpu3.l1c.demand_mshr_misses::cpu3        59108                       # number of demand (read+write) MSHR misses
-system.cpu3.l1c.demand_mshr_misses::total        59108                       # number of demand (read+write) MSHR misses
-system.cpu3.l1c.overall_mshr_misses::cpu3        59108                       # number of overall MSHR misses
-system.cpu3.l1c.overall_mshr_misses::total        59108                       # number of overall MSHR misses
-system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3    863727177                       # number of ReadReq MSHR miss cycles
-system.cpu3.l1c.ReadReq_mshr_miss_latency::total    863727177                       # number of ReadReq MSHR miss cycles
-system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3    801703041                       # number of WriteReq MSHR miss cycles
-system.cpu3.l1c.WriteReq_mshr_miss_latency::total    801703041                       # number of WriteReq MSHR miss cycles
-system.cpu3.l1c.demand_mshr_miss_latency::cpu3   1665430218                       # number of demand (read+write) MSHR miss cycles
-system.cpu3.l1c.demand_mshr_miss_latency::total   1665430218                       # number of demand (read+write) MSHR miss cycles
-system.cpu3.l1c.overall_mshr_miss_latency::cpu3   1665430218                       # number of overall MSHR miss cycles
-system.cpu3.l1c.overall_mshr_miss_latency::total   1665430218                       # number of overall MSHR miss cycles
-system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3    709371346                       # number of ReadReq MSHR uncacheable cycles
-system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total    709371346                       # number of ReadReq MSHR uncacheable cycles
-system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3   1619504156                       # number of WriteReq MSHR uncacheable cycles
-system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total   1619504156                       # number of WriteReq MSHR uncacheable cycles
-system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3   2328875502                       # number of overall MSHR uncacheable cycles
-system.cpu3.l1c.overall_mshr_uncacheable_latency::total   2328875502                       # number of overall MSHR uncacheable cycles
-system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3     0.804380                       # mshr miss rate for ReadReq accesses
-system.cpu3.l1c.ReadReq_mshr_miss_rate::total     0.804380                       # mshr miss rate for ReadReq accesses
-system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3     0.954002                       # mshr miss rate for WriteReq accesses
-system.cpu3.l1c.WriteReq_mshr_miss_rate::total     0.954002                       # mshr miss rate for WriteReq accesses
-system.cpu3.l1c.demand_mshr_miss_rate::cpu3     0.856663                       # mshr miss rate for demand accesses
-system.cpu3.l1c.demand_mshr_miss_rate::total     0.856663                       # mshr miss rate for demand accesses
-system.cpu3.l1c.overall_mshr_miss_rate::cpu3     0.856663                       # mshr miss rate for overall accesses
-system.cpu3.l1c.overall_mshr_miss_rate::total     0.856663                       # mshr miss rate for overall accesses
-system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 23921.322098                       # average ReadReq mshr miss latency
-system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 23921.322098                       # average ReadReq mshr miss latency
-system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 34855.138516                       # average WriteReq mshr miss latency
-system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 34855.138516                       # average WriteReq mshr miss latency
-system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 28176.054307                       # average overall mshr miss latency
-system.cpu3.l1c.demand_avg_mshr_miss_latency::total 28176.054307                       # average overall mshr miss latency
-system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 28176.054307                       # average overall mshr miss latency
-system.cpu3.l1c.overall_avg_mshr_miss_latency::total 28176.054307                       # average overall mshr miss latency
+system.cpu3.l1c.writebacks::writebacks           9730                       # number of writebacks
+system.cpu3.l1c.writebacks::total                9730                       # number of writebacks
+system.cpu3.l1c.ReadReq_mshr_misses::cpu3        36397                       # number of ReadReq MSHR misses
+system.cpu3.l1c.ReadReq_mshr_misses::total        36397                       # number of ReadReq MSHR misses
+system.cpu3.l1c.WriteReq_mshr_misses::cpu3        23878                       # number of WriteReq MSHR misses
+system.cpu3.l1c.WriteReq_mshr_misses::total        23878                       # number of WriteReq MSHR misses
+system.cpu3.l1c.demand_mshr_misses::cpu3        60275                       # number of demand (read+write) MSHR misses
+system.cpu3.l1c.demand_mshr_misses::total        60275                       # number of demand (read+write) MSHR misses
+system.cpu3.l1c.overall_mshr_misses::cpu3        60275                       # number of overall MSHR misses
+system.cpu3.l1c.overall_mshr_misses::total        60275                       # number of overall MSHR misses
+system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3    882022203                       # number of ReadReq MSHR miss cycles
+system.cpu3.l1c.ReadReq_mshr_miss_latency::total    882022203                       # number of ReadReq MSHR miss cycles
+system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3    837608778                       # number of WriteReq MSHR miss cycles
+system.cpu3.l1c.WriteReq_mshr_miss_latency::total    837608778                       # number of WriteReq MSHR miss cycles
+system.cpu3.l1c.demand_mshr_miss_latency::cpu3   1719630981                       # number of demand (read+write) MSHR miss cycles
+system.cpu3.l1c.demand_mshr_miss_latency::total   1719630981                       # number of demand (read+write) MSHR miss cycles
+system.cpu3.l1c.overall_mshr_miss_latency::cpu3   1719630981                       # number of overall MSHR miss cycles
+system.cpu3.l1c.overall_mshr_miss_latency::total   1719630981                       # number of overall MSHR miss cycles
+system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3    701721013                       # number of ReadReq MSHR uncacheable cycles
+system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total    701721013                       # number of ReadReq MSHR uncacheable cycles
+system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3   1702236593                       # number of WriteReq MSHR uncacheable cycles
+system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total   1702236593                       # number of WriteReq MSHR uncacheable cycles
+system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3   2403957606                       # number of overall MSHR uncacheable cycles
+system.cpu3.l1c.overall_mshr_uncacheable_latency::total   2403957606                       # number of overall MSHR uncacheable cycles
+system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3     0.805190                       # mshr miss rate for ReadReq accesses
+system.cpu3.l1c.ReadReq_mshr_miss_rate::total     0.805190                       # mshr miss rate for ReadReq accesses
+system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3     0.953709                       # mshr miss rate for WriteReq accesses
+system.cpu3.l1c.WriteReq_mshr_miss_rate::total     0.953709                       # mshr miss rate for WriteReq accesses
+system.cpu3.l1c.demand_mshr_miss_rate::cpu3     0.858129                       # mshr miss rate for demand accesses
+system.cpu3.l1c.demand_mshr_miss_rate::total     0.858129                       # mshr miss rate for demand accesses
+system.cpu3.l1c.overall_mshr_miss_rate::cpu3     0.858129                       # mshr miss rate for overall accesses
+system.cpu3.l1c.overall_mshr_miss_rate::total     0.858129                       # mshr miss rate for overall accesses
+system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 24233.376460                       # average ReadReq mshr miss latency
+system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 24233.376460                       # average ReadReq mshr miss latency
+system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 35078.682385                       # average WriteReq mshr miss latency
+system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 35078.682385                       # average WriteReq mshr miss latency
+system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 28529.754973                       # average overall mshr miss latency
+system.cpu3.l1c.demand_avg_mshr_miss_latency::total 28529.754973                       # average overall mshr miss latency
+system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 28529.754973                       # average overall mshr miss latency
+system.cpu3.l1c.overall_avg_mshr_miss_latency::total 28529.754973                       # average overall mshr miss latency
 system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3          inf                       # average ReadReq mshr uncacheable latency
 system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3          inf                       # average WriteReq mshr uncacheable latency
@@ -1221,120 +1222,120 @@ system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total          inf
 system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3          inf                       # average overall mshr uncacheable latency
 system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu3.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
-system.cpu4.num_reads                           99830                       # number of read accesses completed
-system.cpu4.num_writes                          54064                       # number of write accesses completed
+system.cpu4.num_reads                           99302                       # number of read accesses completed
+system.cpu4.num_writes                          55134                       # number of write accesses completed
 system.cpu4.num_copies                              0                       # number of copy accesses completed
-system.cpu4.l1c.tags.replacements               22082                       # number of replacements
-system.cpu4.l1c.tags.tagsinuse             393.544066                       # Cycle average of tags in use
-system.cpu4.l1c.tags.total_refs                 13201                       # Total number of references to valid blocks.
-system.cpu4.l1c.tags.sampled_refs               22486                       # Sample count of references to valid blocks.
-system.cpu4.l1c.tags.avg_refs                0.587076                       # Average number of references to valid blocks.
+system.cpu4.l1c.tags.replacements               22459                       # number of replacements
+system.cpu4.l1c.tags.tagsinuse             393.483256                       # Cycle average of tags in use
+system.cpu4.l1c.tags.total_refs                 13509                       # Total number of references to valid blocks.
+system.cpu4.l1c.tags.sampled_refs               22848                       # Sample count of references to valid blocks.
+system.cpu4.l1c.tags.avg_refs                0.591255                       # Average number of references to valid blocks.
 system.cpu4.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
-system.cpu4.l1c.tags.occ_blocks::cpu4      393.544066                       # Average occupied blocks per requestor
-system.cpu4.l1c.tags.occ_percent::cpu4       0.768641                       # Average percentage of cache occupancy
-system.cpu4.l1c.tags.occ_percent::total      0.768641                       # Average percentage of cache occupancy
-system.cpu4.l1c.tags.occ_task_id_blocks::1024          404                       # Occupied blocks per task id
-system.cpu4.l1c.tags.age_task_id_blocks_1024::0          378                       # Occupied blocks per task id
-system.cpu4.l1c.tags.age_task_id_blocks_1024::1           26                       # Occupied blocks per task id
-system.cpu4.l1c.tags.occ_task_id_percent::1024     0.789062                       # Percentage of cache occupancy per task id
-system.cpu4.l1c.tags.tag_accesses              331555                       # Number of tag accesses
-system.cpu4.l1c.tags.data_accesses             331555                       # Number of data accesses
-system.cpu4.l1c.ReadReq_hits::cpu4               8712                       # number of ReadReq hits
-system.cpu4.l1c.ReadReq_hits::total              8712                       # number of ReadReq hits
-system.cpu4.l1c.WriteReq_hits::cpu4              1102                       # number of WriteReq hits
-system.cpu4.l1c.WriteReq_hits::total             1102                       # number of WriteReq hits
-system.cpu4.l1c.demand_hits::cpu4                9814                       # number of demand (read+write) hits
-system.cpu4.l1c.demand_hits::total               9814                       # number of demand (read+write) hits
-system.cpu4.l1c.overall_hits::cpu4               9814                       # number of overall hits
-system.cpu4.l1c.overall_hits::total              9814                       # number of overall hits
-system.cpu4.l1c.ReadReq_misses::cpu4            35977                       # number of ReadReq misses
-system.cpu4.l1c.ReadReq_misses::total           35977                       # number of ReadReq misses
-system.cpu4.l1c.WriteReq_misses::cpu4           23176                       # number of WriteReq misses
-system.cpu4.l1c.WriteReq_misses::total          23176                       # number of WriteReq misses
-system.cpu4.l1c.demand_misses::cpu4             59153                       # number of demand (read+write) misses
-system.cpu4.l1c.demand_misses::total            59153                       # number of demand (read+write) misses
-system.cpu4.l1c.overall_misses::cpu4            59153                       # number of overall misses
-system.cpu4.l1c.overall_misses::total           59153                       # number of overall misses
-system.cpu4.l1c.ReadReq_miss_latency::cpu4    943945635                       # number of ReadReq miss cycles
-system.cpu4.l1c.ReadReq_miss_latency::total    943945635                       # number of ReadReq miss cycles
-system.cpu4.l1c.WriteReq_miss_latency::cpu4    856485364                       # number of WriteReq miss cycles
-system.cpu4.l1c.WriteReq_miss_latency::total    856485364                       # number of WriteReq miss cycles
-system.cpu4.l1c.demand_miss_latency::cpu4   1800430999                       # number of demand (read+write) miss cycles
-system.cpu4.l1c.demand_miss_latency::total   1800430999                       # number of demand (read+write) miss cycles
-system.cpu4.l1c.overall_miss_latency::cpu4   1800430999                       # number of overall miss cycles
-system.cpu4.l1c.overall_miss_latency::total   1800430999                       # number of overall miss cycles
-system.cpu4.l1c.ReadReq_accesses::cpu4          44689                       # number of ReadReq accesses(hits+misses)
-system.cpu4.l1c.ReadReq_accesses::total         44689                       # number of ReadReq accesses(hits+misses)
-system.cpu4.l1c.WriteReq_accesses::cpu4         24278                       # number of WriteReq accesses(hits+misses)
-system.cpu4.l1c.WriteReq_accesses::total        24278                       # number of WriteReq accesses(hits+misses)
-system.cpu4.l1c.demand_accesses::cpu4           68967                       # number of demand (read+write) accesses
-system.cpu4.l1c.demand_accesses::total          68967                       # number of demand (read+write) accesses
-system.cpu4.l1c.overall_accesses::cpu4          68967                       # number of overall (read+write) accesses
-system.cpu4.l1c.overall_accesses::total         68967                       # number of overall (read+write) accesses
-system.cpu4.l1c.ReadReq_miss_rate::cpu4      0.805053                       # miss rate for ReadReq accesses
-system.cpu4.l1c.ReadReq_miss_rate::total     0.805053                       # miss rate for ReadReq accesses
-system.cpu4.l1c.WriteReq_miss_rate::cpu4     0.954609                       # miss rate for WriteReq accesses
-system.cpu4.l1c.WriteReq_miss_rate::total     0.954609                       # miss rate for WriteReq accesses
-system.cpu4.l1c.demand_miss_rate::cpu4       0.857700                       # miss rate for demand accesses
-system.cpu4.l1c.demand_miss_rate::total      0.857700                       # miss rate for demand accesses
-system.cpu4.l1c.overall_miss_rate::cpu4      0.857700                       # miss rate for overall accesses
-system.cpu4.l1c.overall_miss_rate::total     0.857700                       # miss rate for overall accesses
-system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 26237.474915                       # average ReadReq miss latency
-system.cpu4.l1c.ReadReq_avg_miss_latency::total 26237.474915                       # average ReadReq miss latency
-system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 36955.702623                       # average WriteReq miss latency
-system.cpu4.l1c.WriteReq_avg_miss_latency::total 36955.702623                       # average WriteReq miss latency
-system.cpu4.l1c.demand_avg_miss_latency::cpu4 30436.850185                       # average overall miss latency
-system.cpu4.l1c.demand_avg_miss_latency::total 30436.850185                       # average overall miss latency
-system.cpu4.l1c.overall_avg_miss_latency::cpu4 30436.850185                       # average overall miss latency
-system.cpu4.l1c.overall_avg_miss_latency::total 30436.850185                       # average overall miss latency
-system.cpu4.l1c.blocked_cycles::no_mshrs      1017670                       # number of cycles access was blocked
+system.cpu4.l1c.tags.occ_blocks::cpu4      393.483256                       # Average occupied blocks per requestor
+system.cpu4.l1c.tags.occ_percent::cpu4       0.768522                       # Average percentage of cache occupancy
+system.cpu4.l1c.tags.occ_percent::total      0.768522                       # Average percentage of cache occupancy
+system.cpu4.l1c.tags.occ_task_id_blocks::1024          389                       # Occupied blocks per task id
+system.cpu4.l1c.tags.age_task_id_blocks_1024::0          356                       # Occupied blocks per task id
+system.cpu4.l1c.tags.age_task_id_blocks_1024::1           33                       # Occupied blocks per task id
+system.cpu4.l1c.tags.occ_task_id_percent::1024     0.759766                       # Percentage of cache occupancy per task id
+system.cpu4.l1c.tags.tag_accesses              337715                       # Number of tag accesses
+system.cpu4.l1c.tags.data_accesses             337715                       # Number of data accesses
+system.cpu4.l1c.ReadReq_hits::cpu4               8739                       # number of ReadReq hits
+system.cpu4.l1c.ReadReq_hits::total              8739                       # number of ReadReq hits
+system.cpu4.l1c.WriteReq_hits::cpu4              1196                       # number of WriteReq hits
+system.cpu4.l1c.WriteReq_hits::total             1196                       # number of WriteReq hits
+system.cpu4.l1c.demand_hits::cpu4                9935                       # number of demand (read+write) hits
+system.cpu4.l1c.demand_hits::total               9935                       # number of demand (read+write) hits
+system.cpu4.l1c.overall_hits::cpu4               9935                       # number of overall hits
+system.cpu4.l1c.overall_hits::total              9935                       # number of overall hits
+system.cpu4.l1c.ReadReq_misses::cpu4            36407                       # number of ReadReq misses
+system.cpu4.l1c.ReadReq_misses::total           36407                       # number of ReadReq misses
+system.cpu4.l1c.WriteReq_misses::cpu4           23914                       # number of WriteReq misses
+system.cpu4.l1c.WriteReq_misses::total          23914                       # number of WriteReq misses
+system.cpu4.l1c.demand_misses::cpu4             60321                       # number of demand (read+write) misses
+system.cpu4.l1c.demand_misses::total            60321                       # number of demand (read+write) misses
+system.cpu4.l1c.overall_misses::cpu4            60321                       # number of overall misses
+system.cpu4.l1c.overall_misses::total           60321                       # number of overall misses
+system.cpu4.l1c.ReadReq_miss_latency::cpu4    962640133                       # number of ReadReq miss cycles
+system.cpu4.l1c.ReadReq_miss_latency::total    962640133                       # number of ReadReq miss cycles
+system.cpu4.l1c.WriteReq_miss_latency::cpu4    889456301                       # number of WriteReq miss cycles
+system.cpu4.l1c.WriteReq_miss_latency::total    889456301                       # number of WriteReq miss cycles
+system.cpu4.l1c.demand_miss_latency::cpu4   1852096434                       # number of demand (read+write) miss cycles
+system.cpu4.l1c.demand_miss_latency::total   1852096434                       # number of demand (read+write) miss cycles
+system.cpu4.l1c.overall_miss_latency::cpu4   1852096434                       # number of overall miss cycles
+system.cpu4.l1c.overall_miss_latency::total   1852096434                       # number of overall miss cycles
+system.cpu4.l1c.ReadReq_accesses::cpu4          45146                       # number of ReadReq accesses(hits+misses)
+system.cpu4.l1c.ReadReq_accesses::total         45146                       # number of ReadReq accesses(hits+misses)
+system.cpu4.l1c.WriteReq_accesses::cpu4         25110                       # number of WriteReq accesses(hits+misses)
+system.cpu4.l1c.WriteReq_accesses::total        25110                       # number of WriteReq accesses(hits+misses)
+system.cpu4.l1c.demand_accesses::cpu4           70256                       # number of demand (read+write) accesses
+system.cpu4.l1c.demand_accesses::total          70256                       # number of demand (read+write) accesses
+system.cpu4.l1c.overall_accesses::cpu4          70256                       # number of overall (read+write) accesses
+system.cpu4.l1c.overall_accesses::total         70256                       # number of overall (read+write) accesses
+system.cpu4.l1c.ReadReq_miss_rate::cpu4      0.806428                       # miss rate for ReadReq accesses
+system.cpu4.l1c.ReadReq_miss_rate::total     0.806428                       # miss rate for ReadReq accesses
+system.cpu4.l1c.WriteReq_miss_rate::cpu4     0.952370                       # miss rate for WriteReq accesses
+system.cpu4.l1c.WriteReq_miss_rate::total     0.952370                       # miss rate for WriteReq accesses
+system.cpu4.l1c.demand_miss_rate::cpu4       0.858589                       # miss rate for demand accesses
+system.cpu4.l1c.demand_miss_rate::total      0.858589                       # miss rate for demand accesses
+system.cpu4.l1c.overall_miss_rate::cpu4      0.858589                       # miss rate for overall accesses
+system.cpu4.l1c.overall_miss_rate::total     0.858589                       # miss rate for overall accesses
+system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 26441.072678                       # average ReadReq miss latency
+system.cpu4.l1c.ReadReq_avg_miss_latency::total 26441.072678                       # average ReadReq miss latency
+system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 37193.957556                       # average WriteReq miss latency
+system.cpu4.l1c.WriteReq_avg_miss_latency::total 37193.957556                       # average WriteReq miss latency
+system.cpu4.l1c.demand_avg_miss_latency::cpu4 30704.007460                       # average overall miss latency
+system.cpu4.l1c.demand_avg_miss_latency::total 30704.007460                       # average overall miss latency
+system.cpu4.l1c.overall_avg_miss_latency::cpu4 30704.007460                       # average overall miss latency
+system.cpu4.l1c.overall_avg_miss_latency::total 30704.007460                       # average overall miss latency
+system.cpu4.l1c.blocked_cycles::no_mshrs      1036597                       # number of cycles access was blocked
 system.cpu4.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu4.l1c.blocked::no_mshrs               62294                       # number of cycles access was blocked
+system.cpu4.l1c.blocked::no_mshrs               63051                       # number of cycles access was blocked
 system.cpu4.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
-system.cpu4.l1c.avg_blocked_cycles::no_mshrs    16.336565                       # average number of cycles each access was blocked
+system.cpu4.l1c.avg_blocked_cycles::no_mshrs    16.440612                       # average number of cycles each access was blocked
 system.cpu4.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu4.l1c.fast_writes                         0                       # number of fast writes performed
 system.cpu4.l1c.cache_copies                        0                       # number of cache copies performed
-system.cpu4.l1c.writebacks::writebacks           9622                       # number of writebacks
-system.cpu4.l1c.writebacks::total                9622                       # number of writebacks
-system.cpu4.l1c.ReadReq_mshr_misses::cpu4        35977                       # number of ReadReq MSHR misses
-system.cpu4.l1c.ReadReq_mshr_misses::total        35977                       # number of ReadReq MSHR misses
-system.cpu4.l1c.WriteReq_mshr_misses::cpu4        23176                       # number of WriteReq MSHR misses
-system.cpu4.l1c.WriteReq_mshr_misses::total        23176                       # number of WriteReq MSHR misses
-system.cpu4.l1c.demand_mshr_misses::cpu4        59153                       # number of demand (read+write) MSHR misses
-system.cpu4.l1c.demand_mshr_misses::total        59153                       # number of demand (read+write) MSHR misses
-system.cpu4.l1c.overall_mshr_misses::cpu4        59153                       # number of overall MSHR misses
-system.cpu4.l1c.overall_mshr_misses::total        59153                       # number of overall MSHR misses
-system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4    867154515                       # number of ReadReq MSHR miss cycles
-system.cpu4.l1c.ReadReq_mshr_miss_latency::total    867154515                       # number of ReadReq MSHR miss cycles
-system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4    807437346                       # number of WriteReq MSHR miss cycles
-system.cpu4.l1c.WriteReq_mshr_miss_latency::total    807437346                       # number of WriteReq MSHR miss cycles
-system.cpu4.l1c.demand_mshr_miss_latency::cpu4   1674591861                       # number of demand (read+write) MSHR miss cycles
-system.cpu4.l1c.demand_mshr_miss_latency::total   1674591861                       # number of demand (read+write) MSHR miss cycles
-system.cpu4.l1c.overall_mshr_miss_latency::cpu4   1674591861                       # number of overall MSHR miss cycles
-system.cpu4.l1c.overall_mshr_miss_latency::total   1674591861                       # number of overall MSHR miss cycles
-system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4    707224870                       # number of ReadReq MSHR uncacheable cycles
-system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total    707224870                       # number of ReadReq MSHR uncacheable cycles
-system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4   1620907679                       # number of WriteReq MSHR uncacheable cycles
-system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total   1620907679                       # number of WriteReq MSHR uncacheable cycles
-system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4   2328132549                       # number of overall MSHR uncacheable cycles
-system.cpu4.l1c.overall_mshr_uncacheable_latency::total   2328132549                       # number of overall MSHR uncacheable cycles
-system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4     0.805053                       # mshr miss rate for ReadReq accesses
-system.cpu4.l1c.ReadReq_mshr_miss_rate::total     0.805053                       # mshr miss rate for ReadReq accesses
-system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4     0.954609                       # mshr miss rate for WriteReq accesses
-system.cpu4.l1c.WriteReq_mshr_miss_rate::total     0.954609                       # mshr miss rate for WriteReq accesses
-system.cpu4.l1c.demand_mshr_miss_rate::cpu4     0.857700                       # mshr miss rate for demand accesses
-system.cpu4.l1c.demand_mshr_miss_rate::total     0.857700                       # mshr miss rate for demand accesses
-system.cpu4.l1c.overall_mshr_miss_rate::cpu4     0.857700                       # mshr miss rate for overall accesses
-system.cpu4.l1c.overall_mshr_miss_rate::total     0.857700                       # mshr miss rate for overall accesses
-system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 24103.024571                       # average ReadReq mshr miss latency
-system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 24103.024571                       # average ReadReq mshr miss latency
-system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 34839.374612                       # average WriteReq mshr miss latency
-system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 34839.374612                       # average WriteReq mshr miss latency
-system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 28309.500127                       # average overall mshr miss latency
-system.cpu4.l1c.demand_avg_mshr_miss_latency::total 28309.500127                       # average overall mshr miss latency
-system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 28309.500127                       # average overall mshr miss latency
-system.cpu4.l1c.overall_avg_mshr_miss_latency::total 28309.500127                       # average overall mshr miss latency
+system.cpu4.l1c.writebacks::writebacks           9933                       # number of writebacks
+system.cpu4.l1c.writebacks::total                9933                       # number of writebacks
+system.cpu4.l1c.ReadReq_mshr_misses::cpu4        36407                       # number of ReadReq MSHR misses
+system.cpu4.l1c.ReadReq_mshr_misses::total        36407                       # number of ReadReq MSHR misses
+system.cpu4.l1c.WriteReq_mshr_misses::cpu4        23914                       # number of WriteReq MSHR misses
+system.cpu4.l1c.WriteReq_mshr_misses::total        23914                       # number of WriteReq MSHR misses
+system.cpu4.l1c.demand_mshr_misses::cpu4        60321                       # number of demand (read+write) MSHR misses
+system.cpu4.l1c.demand_mshr_misses::total        60321                       # number of demand (read+write) MSHR misses
+system.cpu4.l1c.overall_mshr_misses::cpu4        60321                       # number of overall MSHR misses
+system.cpu4.l1c.overall_mshr_misses::total        60321                       # number of overall MSHR misses
+system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4    884868259                       # number of ReadReq MSHR miss cycles
+system.cpu4.l1c.ReadReq_mshr_miss_latency::total    884868259                       # number of ReadReq MSHR miss cycles
+system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4    838892397                       # number of WriteReq MSHR miss cycles
+system.cpu4.l1c.WriteReq_mshr_miss_latency::total    838892397                       # number of WriteReq MSHR miss cycles
+system.cpu4.l1c.demand_mshr_miss_latency::cpu4   1723760656                       # number of demand (read+write) MSHR miss cycles
+system.cpu4.l1c.demand_mshr_miss_latency::total   1723760656                       # number of demand (read+write) MSHR miss cycles
+system.cpu4.l1c.overall_mshr_miss_latency::cpu4   1723760656                       # number of overall MSHR miss cycles
+system.cpu4.l1c.overall_mshr_miss_latency::total   1723760656                       # number of overall MSHR miss cycles
+system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4    703520432                       # number of ReadReq MSHR uncacheable cycles
+system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total    703520432                       # number of ReadReq MSHR uncacheable cycles
+system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4   1658146550                       # number of WriteReq MSHR uncacheable cycles
+system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total   1658146550                       # number of WriteReq MSHR uncacheable cycles
+system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4   2361666982                       # number of overall MSHR uncacheable cycles
+system.cpu4.l1c.overall_mshr_uncacheable_latency::total   2361666982                       # number of overall MSHR uncacheable cycles
+system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4     0.806428                       # mshr miss rate for ReadReq accesses
+system.cpu4.l1c.ReadReq_mshr_miss_rate::total     0.806428                       # mshr miss rate for ReadReq accesses
+system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4     0.952370                       # mshr miss rate for WriteReq accesses
+system.cpu4.l1c.WriteReq_mshr_miss_rate::total     0.952370                       # mshr miss rate for WriteReq accesses
+system.cpu4.l1c.demand_mshr_miss_rate::cpu4     0.858589                       # mshr miss rate for demand accesses
+system.cpu4.l1c.demand_mshr_miss_rate::total     0.858589                       # mshr miss rate for demand accesses
+system.cpu4.l1c.overall_mshr_miss_rate::cpu4     0.858589                       # mshr miss rate for overall accesses
+system.cpu4.l1c.overall_mshr_miss_rate::total     0.858589                       # mshr miss rate for overall accesses
+system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 24304.893537                       # average ReadReq mshr miss latency
+system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 24304.893537                       # average ReadReq mshr miss latency
+system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 35079.551602                       # average WriteReq mshr miss latency
+system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 35079.551602                       # average WriteReq mshr miss latency
+system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 28576.460205                       # average overall mshr miss latency
+system.cpu4.l1c.demand_avg_mshr_miss_latency::total 28576.460205                       # average overall mshr miss latency
+system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 28576.460205                       # average overall mshr miss latency
+system.cpu4.l1c.overall_avg_mshr_miss_latency::total 28576.460205                       # average overall mshr miss latency
 system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4          inf                       # average ReadReq mshr uncacheable latency
 system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4          inf                       # average WriteReq mshr uncacheable latency
@@ -1342,120 +1343,120 @@ system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total          inf
 system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4          inf                       # average overall mshr uncacheable latency
 system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu4.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
-system.cpu5.num_reads                           99630                       # number of read accesses completed
-system.cpu5.num_writes                          53500                       # number of write accesses completed
+system.cpu5.num_reads                           99936                       # number of read accesses completed
+system.cpu5.num_writes                          55294                       # number of write accesses completed
 system.cpu5.num_copies                              0                       # number of copy accesses completed
-system.cpu5.l1c.tags.replacements               22051                       # number of replacements
-system.cpu5.l1c.tags.tagsinuse             395.592742                       # Cycle average of tags in use
-system.cpu5.l1c.tags.total_refs                 13484                       # Total number of references to valid blocks.
-system.cpu5.l1c.tags.sampled_refs               22450                       # Sample count of references to valid blocks.
-system.cpu5.l1c.tags.avg_refs                0.600624                       # Average number of references to valid blocks.
+system.cpu5.l1c.tags.replacements               22607                       # number of replacements
+system.cpu5.l1c.tags.tagsinuse             394.741985                       # Cycle average of tags in use
+system.cpu5.l1c.tags.total_refs                 13577                       # Total number of references to valid blocks.
+system.cpu5.l1c.tags.sampled_refs               23024                       # Sample count of references to valid blocks.
+system.cpu5.l1c.tags.avg_refs                0.589689                       # Average number of references to valid blocks.
 system.cpu5.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
-system.cpu5.l1c.tags.occ_blocks::cpu5      395.592742                       # Average occupied blocks per requestor
-system.cpu5.l1c.tags.occ_percent::cpu5       0.772642                       # Average percentage of cache occupancy
-system.cpu5.l1c.tags.occ_percent::total      0.772642                       # Average percentage of cache occupancy
-system.cpu5.l1c.tags.occ_task_id_blocks::1024          399                       # Occupied blocks per task id
-system.cpu5.l1c.tags.age_task_id_blocks_1024::0          375                       # Occupied blocks per task id
-system.cpu5.l1c.tags.age_task_id_blocks_1024::1           24                       # Occupied blocks per task id
-system.cpu5.l1c.tags.occ_task_id_percent::1024     0.779297                       # Percentage of cache occupancy per task id
-system.cpu5.l1c.tags.tag_accesses              332072                       # Number of tag accesses
-system.cpu5.l1c.tags.data_accesses             332072                       # Number of data accesses
-system.cpu5.l1c.ReadReq_hits::cpu5               8824                       # number of ReadReq hits
-system.cpu5.l1c.ReadReq_hits::total              8824                       # number of ReadReq hits
-system.cpu5.l1c.WriteReq_hits::cpu5              1160                       # number of WriteReq hits
-system.cpu5.l1c.WriteReq_hits::total             1160                       # number of WriteReq hits
-system.cpu5.l1c.demand_hits::cpu5                9984                       # number of demand (read+write) hits
-system.cpu5.l1c.demand_hits::total               9984                       # number of demand (read+write) hits
-system.cpu5.l1c.overall_hits::cpu5               9984                       # number of overall hits
-system.cpu5.l1c.overall_hits::total              9984                       # number of overall hits
-system.cpu5.l1c.ReadReq_misses::cpu5            36108                       # number of ReadReq misses
-system.cpu5.l1c.ReadReq_misses::total           36108                       # number of ReadReq misses
-system.cpu5.l1c.WriteReq_misses::cpu5           23031                       # number of WriteReq misses
-system.cpu5.l1c.WriteReq_misses::total          23031                       # number of WriteReq misses
-system.cpu5.l1c.demand_misses::cpu5             59139                       # number of demand (read+write) misses
-system.cpu5.l1c.demand_misses::total            59139                       # number of demand (read+write) misses
-system.cpu5.l1c.overall_misses::cpu5            59139                       # number of overall misses
-system.cpu5.l1c.overall_misses::total           59139                       # number of overall misses
-system.cpu5.l1c.ReadReq_miss_latency::cpu5    948980493                       # number of ReadReq miss cycles
-system.cpu5.l1c.ReadReq_miss_latency::total    948980493                       # number of ReadReq miss cycles
-system.cpu5.l1c.WriteReq_miss_latency::cpu5    861190152                       # number of WriteReq miss cycles
-system.cpu5.l1c.WriteReq_miss_latency::total    861190152                       # number of WriteReq miss cycles
-system.cpu5.l1c.demand_miss_latency::cpu5   1810170645                       # number of demand (read+write) miss cycles
-system.cpu5.l1c.demand_miss_latency::total   1810170645                       # number of demand (read+write) miss cycles
-system.cpu5.l1c.overall_miss_latency::cpu5   1810170645                       # number of overall miss cycles
-system.cpu5.l1c.overall_miss_latency::total   1810170645                       # number of overall miss cycles
-system.cpu5.l1c.ReadReq_accesses::cpu5          44932                       # number of ReadReq accesses(hits+misses)
-system.cpu5.l1c.ReadReq_accesses::total         44932                       # number of ReadReq accesses(hits+misses)
-system.cpu5.l1c.WriteReq_accesses::cpu5         24191                       # number of WriteReq accesses(hits+misses)
-system.cpu5.l1c.WriteReq_accesses::total        24191                       # number of WriteReq accesses(hits+misses)
-system.cpu5.l1c.demand_accesses::cpu5           69123                       # number of demand (read+write) accesses
-system.cpu5.l1c.demand_accesses::total          69123                       # number of demand (read+write) accesses
-system.cpu5.l1c.overall_accesses::cpu5          69123                       # number of overall (read+write) accesses
-system.cpu5.l1c.overall_accesses::total         69123                       # number of overall (read+write) accesses
-system.cpu5.l1c.ReadReq_miss_rate::cpu5      0.803614                       # miss rate for ReadReq accesses
-system.cpu5.l1c.ReadReq_miss_rate::total     0.803614                       # miss rate for ReadReq accesses
-system.cpu5.l1c.WriteReq_miss_rate::cpu5     0.952048                       # miss rate for WriteReq accesses
-system.cpu5.l1c.WriteReq_miss_rate::total     0.952048                       # miss rate for WriteReq accesses
-system.cpu5.l1c.demand_miss_rate::cpu5       0.855562                       # miss rate for demand accesses
-system.cpu5.l1c.demand_miss_rate::total      0.855562                       # miss rate for demand accesses
-system.cpu5.l1c.overall_miss_rate::cpu5      0.855562                       # miss rate for overall accesses
-system.cpu5.l1c.overall_miss_rate::total     0.855562                       # miss rate for overall accesses
-system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 26281.724078                       # average ReadReq miss latency
-system.cpu5.l1c.ReadReq_avg_miss_latency::total 26281.724078                       # average ReadReq miss latency
-system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 37392.651296                       # average WriteReq miss latency
-system.cpu5.l1c.WriteReq_avg_miss_latency::total 37392.651296                       # average WriteReq miss latency
-system.cpu5.l1c.demand_avg_miss_latency::cpu5 30608.746259                       # average overall miss latency
-system.cpu5.l1c.demand_avg_miss_latency::total 30608.746259                       # average overall miss latency
-system.cpu5.l1c.overall_avg_miss_latency::cpu5 30608.746259                       # average overall miss latency
-system.cpu5.l1c.overall_avg_miss_latency::total 30608.746259                       # average overall miss latency
-system.cpu5.l1c.blocked_cycles::no_mshrs      1024769                       # number of cycles access was blocked
+system.cpu5.l1c.tags.occ_blocks::cpu5      394.741985                       # Average occupied blocks per requestor
+system.cpu5.l1c.tags.occ_percent::cpu5       0.770980                       # Average percentage of cache occupancy
+system.cpu5.l1c.tags.occ_percent::total      0.770980                       # Average percentage of cache occupancy
+system.cpu5.l1c.tags.occ_task_id_blocks::1024          417                       # Occupied blocks per task id
+system.cpu5.l1c.tags.age_task_id_blocks_1024::0          390                       # Occupied blocks per task id
+system.cpu5.l1c.tags.age_task_id_blocks_1024::1           27                       # Occupied blocks per task id
+system.cpu5.l1c.tags.occ_task_id_percent::1024     0.814453                       # Percentage of cache occupancy per task id
+system.cpu5.l1c.tags.tag_accesses              338075                       # Number of tag accesses
+system.cpu5.l1c.tags.data_accesses             338075                       # Number of data accesses
+system.cpu5.l1c.ReadReq_hits::cpu5               8826                       # number of ReadReq hits
+system.cpu5.l1c.ReadReq_hits::total              8826                       # number of ReadReq hits
+system.cpu5.l1c.WriteReq_hits::cpu5              1123                       # number of WriteReq hits
+system.cpu5.l1c.WriteReq_hits::total             1123                       # number of WriteReq hits
+system.cpu5.l1c.demand_hits::cpu5                9949                       # number of demand (read+write) hits
+system.cpu5.l1c.demand_hits::total               9949                       # number of demand (read+write) hits
+system.cpu5.l1c.overall_hits::cpu5               9949                       # number of overall hits
+system.cpu5.l1c.overall_hits::total              9949                       # number of overall hits
+system.cpu5.l1c.ReadReq_misses::cpu5            36440                       # number of ReadReq misses
+system.cpu5.l1c.ReadReq_misses::total           36440                       # number of ReadReq misses
+system.cpu5.l1c.WriteReq_misses::cpu5           23955                       # number of WriteReq misses
+system.cpu5.l1c.WriteReq_misses::total          23955                       # number of WriteReq misses
+system.cpu5.l1c.demand_misses::cpu5             60395                       # number of demand (read+write) misses
+system.cpu5.l1c.demand_misses::total            60395                       # number of demand (read+write) misses
+system.cpu5.l1c.overall_misses::cpu5            60395                       # number of overall misses
+system.cpu5.l1c.overall_misses::total           60395                       # number of overall misses
+system.cpu5.l1c.ReadReq_miss_latency::cpu5    954691213                       # number of ReadReq miss cycles
+system.cpu5.l1c.ReadReq_miss_latency::total    954691213                       # number of ReadReq miss cycles
+system.cpu5.l1c.WriteReq_miss_latency::cpu5    898328721                       # number of WriteReq miss cycles
+system.cpu5.l1c.WriteReq_miss_latency::total    898328721                       # number of WriteReq miss cycles
+system.cpu5.l1c.demand_miss_latency::cpu5   1853019934                       # number of demand (read+write) miss cycles
+system.cpu5.l1c.demand_miss_latency::total   1853019934                       # number of demand (read+write) miss cycles
+system.cpu5.l1c.overall_miss_latency::cpu5   1853019934                       # number of overall miss cycles
+system.cpu5.l1c.overall_miss_latency::total   1853019934                       # number of overall miss cycles
+system.cpu5.l1c.ReadReq_accesses::cpu5          45266                       # number of ReadReq accesses(hits+misses)
+system.cpu5.l1c.ReadReq_accesses::total         45266                       # number of ReadReq accesses(hits+misses)
+system.cpu5.l1c.WriteReq_accesses::cpu5         25078                       # number of WriteReq accesses(hits+misses)
+system.cpu5.l1c.WriteReq_accesses::total        25078                       # number of WriteReq accesses(hits+misses)
+system.cpu5.l1c.demand_accesses::cpu5           70344                       # number of demand (read+write) accesses
+system.cpu5.l1c.demand_accesses::total          70344                       # number of demand (read+write) accesses
+system.cpu5.l1c.overall_accesses::cpu5          70344                       # number of overall (read+write) accesses
+system.cpu5.l1c.overall_accesses::total         70344                       # number of overall (read+write) accesses
+system.cpu5.l1c.ReadReq_miss_rate::cpu5      0.805019                       # miss rate for ReadReq accesses
+system.cpu5.l1c.ReadReq_miss_rate::total     0.805019                       # miss rate for ReadReq accesses
+system.cpu5.l1c.WriteReq_miss_rate::cpu5     0.955220                       # miss rate for WriteReq accesses
+system.cpu5.l1c.WriteReq_miss_rate::total     0.955220                       # miss rate for WriteReq accesses
+system.cpu5.l1c.demand_miss_rate::cpu5       0.858566                       # miss rate for demand accesses
+system.cpu5.l1c.demand_miss_rate::total      0.858566                       # miss rate for demand accesses
+system.cpu5.l1c.overall_miss_rate::cpu5      0.858566                       # miss rate for overall accesses
+system.cpu5.l1c.overall_miss_rate::total     0.858566                       # miss rate for overall accesses
+system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 26198.990477                       # average ReadReq miss latency
+system.cpu5.l1c.ReadReq_avg_miss_latency::total 26198.990477                       # average ReadReq miss latency
+system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 37500.677145                       # average WriteReq miss latency
+system.cpu5.l1c.WriteReq_avg_miss_latency::total 37500.677145                       # average WriteReq miss latency
+system.cpu5.l1c.demand_avg_miss_latency::cpu5 30681.677854                       # average overall miss latency
+system.cpu5.l1c.demand_avg_miss_latency::total 30681.677854                       # average overall miss latency
+system.cpu5.l1c.overall_avg_miss_latency::cpu5 30681.677854                       # average overall miss latency
+system.cpu5.l1c.overall_avg_miss_latency::total 30681.677854                       # average overall miss latency
+system.cpu5.l1c.blocked_cycles::no_mshrs      1031399                       # number of cycles access was blocked
 system.cpu5.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu5.l1c.blocked::no_mshrs               62427                       # number of cycles access was blocked
+system.cpu5.l1c.blocked::no_mshrs               62997                       # number of cycles access was blocked
 system.cpu5.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
-system.cpu5.l1c.avg_blocked_cycles::no_mshrs    16.415477                       # average number of cycles each access was blocked
+system.cpu5.l1c.avg_blocked_cycles::no_mshrs    16.372192                       # average number of cycles each access was blocked
 system.cpu5.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu5.l1c.fast_writes                         0                       # number of fast writes performed
 system.cpu5.l1c.cache_copies                        0                       # number of cache copies performed
-system.cpu5.l1c.writebacks::writebacks           9521                       # number of writebacks
-system.cpu5.l1c.writebacks::total                9521                       # number of writebacks
-system.cpu5.l1c.ReadReq_mshr_misses::cpu5        36108                       # number of ReadReq MSHR misses
-system.cpu5.l1c.ReadReq_mshr_misses::total        36108                       # number of ReadReq MSHR misses
-system.cpu5.l1c.WriteReq_mshr_misses::cpu5        23031                       # number of WriteReq MSHR misses
-system.cpu5.l1c.WriteReq_mshr_misses::total        23031                       # number of WriteReq MSHR misses
-system.cpu5.l1c.demand_mshr_misses::cpu5        59139                       # number of demand (read+write) MSHR misses
-system.cpu5.l1c.demand_mshr_misses::total        59139                       # number of demand (read+write) MSHR misses
-system.cpu5.l1c.overall_mshr_misses::cpu5        59139                       # number of overall MSHR misses
-system.cpu5.l1c.overall_mshr_misses::total        59139                       # number of overall MSHR misses
-system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5    871850549                       # number of ReadReq MSHR miss cycles
-system.cpu5.l1c.ReadReq_mshr_miss_latency::total    871850549                       # number of ReadReq MSHR miss cycles
-system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5    812508000                       # number of WriteReq MSHR miss cycles
-system.cpu5.l1c.WriteReq_mshr_miss_latency::total    812508000                       # number of WriteReq MSHR miss cycles
-system.cpu5.l1c.demand_mshr_miss_latency::cpu5   1684358549                       # number of demand (read+write) MSHR miss cycles
-system.cpu5.l1c.demand_mshr_miss_latency::total   1684358549                       # number of demand (read+write) MSHR miss cycles
-system.cpu5.l1c.overall_mshr_miss_latency::cpu5   1684358549                       # number of overall MSHR miss cycles
-system.cpu5.l1c.overall_mshr_miss_latency::total   1684358549                       # number of overall MSHR miss cycles
-system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5    704255884                       # number of ReadReq MSHR uncacheable cycles
-system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total    704255884                       # number of ReadReq MSHR uncacheable cycles
-system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5   1614286606                       # number of WriteReq MSHR uncacheable cycles
-system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total   1614286606                       # number of WriteReq MSHR uncacheable cycles
-system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5   2318542490                       # number of overall MSHR uncacheable cycles
-system.cpu5.l1c.overall_mshr_uncacheable_latency::total   2318542490                       # number of overall MSHR uncacheable cycles
-system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5     0.803614                       # mshr miss rate for ReadReq accesses
-system.cpu5.l1c.ReadReq_mshr_miss_rate::total     0.803614                       # mshr miss rate for ReadReq accesses
-system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5     0.952048                       # mshr miss rate for WriteReq accesses
-system.cpu5.l1c.WriteReq_mshr_miss_rate::total     0.952048                       # mshr miss rate for WriteReq accesses
-system.cpu5.l1c.demand_mshr_miss_rate::cpu5     0.855562                       # mshr miss rate for demand accesses
-system.cpu5.l1c.demand_mshr_miss_rate::total     0.855562                       # mshr miss rate for demand accesses
-system.cpu5.l1c.overall_mshr_miss_rate::cpu5     0.855562                       # mshr miss rate for overall accesses
-system.cpu5.l1c.overall_mshr_miss_rate::total     0.855562                       # mshr miss rate for overall accesses
-system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 24145.633904                       # average ReadReq mshr miss latency
-system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 24145.633904                       # average ReadReq mshr miss latency
-system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 35278.884981                       # average WriteReq mshr miss latency
-system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 35278.884981                       # average WriteReq mshr miss latency
-system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 28481.349854                       # average overall mshr miss latency
-system.cpu5.l1c.demand_avg_mshr_miss_latency::total 28481.349854                       # average overall mshr miss latency
-system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 28481.349854                       # average overall mshr miss latency
-system.cpu5.l1c.overall_avg_mshr_miss_latency::total 28481.349854                       # average overall mshr miss latency
+system.cpu5.l1c.writebacks::writebacks           9959                       # number of writebacks
+system.cpu5.l1c.writebacks::total                9959                       # number of writebacks
+system.cpu5.l1c.ReadReq_mshr_misses::cpu5        36440                       # number of ReadReq MSHR misses
+system.cpu5.l1c.ReadReq_mshr_misses::total        36440                       # number of ReadReq MSHR misses
+system.cpu5.l1c.WriteReq_mshr_misses::cpu5        23955                       # number of WriteReq MSHR misses
+system.cpu5.l1c.WriteReq_mshr_misses::total        23955                       # number of WriteReq MSHR misses
+system.cpu5.l1c.demand_mshr_misses::cpu5        60395                       # number of demand (read+write) MSHR misses
+system.cpu5.l1c.demand_mshr_misses::total        60395                       # number of demand (read+write) MSHR misses
+system.cpu5.l1c.overall_mshr_misses::cpu5        60395                       # number of overall MSHR misses
+system.cpu5.l1c.overall_mshr_misses::total        60395                       # number of overall MSHR misses
+system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5    876841351                       # number of ReadReq MSHR miss cycles
+system.cpu5.l1c.ReadReq_mshr_miss_latency::total    876841351                       # number of ReadReq MSHR miss cycles
+system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5    847650833                       # number of WriteReq MSHR miss cycles
+system.cpu5.l1c.WriteReq_mshr_miss_latency::total    847650833                       # number of WriteReq MSHR miss cycles
+system.cpu5.l1c.demand_mshr_miss_latency::cpu5   1724492184                       # number of demand (read+write) MSHR miss cycles
+system.cpu5.l1c.demand_mshr_miss_latency::total   1724492184                       # number of demand (read+write) MSHR miss cycles
+system.cpu5.l1c.overall_mshr_miss_latency::cpu5   1724492184                       # number of overall MSHR miss cycles
+system.cpu5.l1c.overall_mshr_miss_latency::total   1724492184                       # number of overall MSHR miss cycles
+system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5    699333550                       # number of ReadReq MSHR uncacheable cycles
+system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total    699333550                       # number of ReadReq MSHR uncacheable cycles
+system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5   1696976001                       # number of WriteReq MSHR uncacheable cycles
+system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total   1696976001                       # number of WriteReq MSHR uncacheable cycles
+system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5   2396309551                       # number of overall MSHR uncacheable cycles
+system.cpu5.l1c.overall_mshr_uncacheable_latency::total   2396309551                       # number of overall MSHR uncacheable cycles
+system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5     0.805019                       # mshr miss rate for ReadReq accesses
+system.cpu5.l1c.ReadReq_mshr_miss_rate::total     0.805019                       # mshr miss rate for ReadReq accesses
+system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5     0.955220                       # mshr miss rate for WriteReq accesses
+system.cpu5.l1c.WriteReq_mshr_miss_rate::total     0.955220                       # mshr miss rate for WriteReq accesses
+system.cpu5.l1c.demand_mshr_miss_rate::cpu5     0.858566                       # mshr miss rate for demand accesses
+system.cpu5.l1c.demand_mshr_miss_rate::total     0.858566                       # mshr miss rate for demand accesses
+system.cpu5.l1c.overall_mshr_miss_rate::cpu5     0.858566                       # mshr miss rate for overall accesses
+system.cpu5.l1c.overall_mshr_miss_rate::total     0.858566                       # mshr miss rate for overall accesses
+system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 24062.605681                       # average ReadReq mshr miss latency
+system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 24062.605681                       # average ReadReq mshr miss latency
+system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 35385.131831                       # average WriteReq mshr miss latency
+system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 35385.131831                       # average WriteReq mshr miss latency
+system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 28553.558805                       # average overall mshr miss latency
+system.cpu5.l1c.demand_avg_mshr_miss_latency::total 28553.558805                       # average overall mshr miss latency
+system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 28553.558805                       # average overall mshr miss latency
+system.cpu5.l1c.overall_avg_mshr_miss_latency::total 28553.558805                       # average overall mshr miss latency
 system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5          inf                       # average ReadReq mshr uncacheable latency
 system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5          inf                       # average WriteReq mshr uncacheable latency
@@ -1463,120 +1464,120 @@ system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total          inf
 system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5          inf                       # average overall mshr uncacheable latency
 system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu5.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
-system.cpu6.num_reads                           99897                       # number of read accesses completed
-system.cpu6.num_writes                          53584                       # number of write accesses completed
+system.cpu6.num_reads                          100001                       # number of read accesses completed
+system.cpu6.num_writes                          55113                       # number of write accesses completed
 system.cpu6.num_copies                              0                       # number of copy accesses completed
-system.cpu6.l1c.tags.replacements               22385                       # number of replacements
-system.cpu6.l1c.tags.tagsinuse             395.582005                       # Cycle average of tags in use
-system.cpu6.l1c.tags.total_refs                 13337                       # Total number of references to valid blocks.
-system.cpu6.l1c.tags.sampled_refs               22793                       # Sample count of references to valid blocks.
-system.cpu6.l1c.tags.avg_refs                0.585136                       # Average number of references to valid blocks.
+system.cpu6.l1c.tags.replacements               22596                       # number of replacements
+system.cpu6.l1c.tags.tagsinuse             393.612008                       # Cycle average of tags in use
+system.cpu6.l1c.tags.total_refs                 13438                       # Total number of references to valid blocks.
+system.cpu6.l1c.tags.sampled_refs               23004                       # Sample count of references to valid blocks.
+system.cpu6.l1c.tags.avg_refs                0.584159                       # Average number of references to valid blocks.
 system.cpu6.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
-system.cpu6.l1c.tags.occ_blocks::cpu6      395.582005                       # Average occupied blocks per requestor
-system.cpu6.l1c.tags.occ_percent::cpu6       0.772621                       # Average percentage of cache occupancy
-system.cpu6.l1c.tags.occ_percent::total      0.772621                       # Average percentage of cache occupancy
+system.cpu6.l1c.tags.occ_blocks::cpu6      393.612008                       # Average occupied blocks per requestor
+system.cpu6.l1c.tags.occ_percent::cpu6       0.768773                       # Average percentage of cache occupancy
+system.cpu6.l1c.tags.occ_percent::total      0.768773                       # Average percentage of cache occupancy
 system.cpu6.l1c.tags.occ_task_id_blocks::1024          408                       # Occupied blocks per task id
-system.cpu6.l1c.tags.age_task_id_blocks_1024::0          376                       # Occupied blocks per task id
-system.cpu6.l1c.tags.age_task_id_blocks_1024::1           32                       # Occupied blocks per task id
+system.cpu6.l1c.tags.age_task_id_blocks_1024::0          386                       # Occupied blocks per task id
+system.cpu6.l1c.tags.age_task_id_blocks_1024::1           22                       # Occupied blocks per task id
 system.cpu6.l1c.tags.occ_task_id_percent::1024     0.796875                       # Percentage of cache occupancy per task id
-system.cpu6.l1c.tags.tag_accesses              332017                       # Number of tag accesses
-system.cpu6.l1c.tags.data_accesses             332017                       # Number of data accesses
-system.cpu6.l1c.ReadReq_hits::cpu6               8715                       # number of ReadReq hits
-system.cpu6.l1c.ReadReq_hits::total              8715                       # number of ReadReq hits
-system.cpu6.l1c.WriteReq_hits::cpu6              1094                       # number of WriteReq hits
-system.cpu6.l1c.WriteReq_hits::total             1094                       # number of WriteReq hits
-system.cpu6.l1c.demand_hits::cpu6                9809                       # number of demand (read+write) hits
-system.cpu6.l1c.demand_hits::total               9809                       # number of demand (read+write) hits
-system.cpu6.l1c.overall_hits::cpu6               9809                       # number of overall hits
-system.cpu6.l1c.overall_hits::total              9809                       # number of overall hits
-system.cpu6.l1c.ReadReq_misses::cpu6            36235                       # number of ReadReq misses
-system.cpu6.l1c.ReadReq_misses::total           36235                       # number of ReadReq misses
-system.cpu6.l1c.WriteReq_misses::cpu6           23035                       # number of WriteReq misses
-system.cpu6.l1c.WriteReq_misses::total          23035                       # number of WriteReq misses
-system.cpu6.l1c.demand_misses::cpu6             59270                       # number of demand (read+write) misses
-system.cpu6.l1c.demand_misses::total            59270                       # number of demand (read+write) misses
-system.cpu6.l1c.overall_misses::cpu6            59270                       # number of overall misses
-system.cpu6.l1c.overall_misses::total           59270                       # number of overall misses
-system.cpu6.l1c.ReadReq_miss_latency::cpu6    950668375                       # number of ReadReq miss cycles
-system.cpu6.l1c.ReadReq_miss_latency::total    950668375                       # number of ReadReq miss cycles
-system.cpu6.l1c.WriteReq_miss_latency::cpu6    850880053                       # number of WriteReq miss cycles
-system.cpu6.l1c.WriteReq_miss_latency::total    850880053                       # number of WriteReq miss cycles
-system.cpu6.l1c.demand_miss_latency::cpu6   1801548428                       # number of demand (read+write) miss cycles
-system.cpu6.l1c.demand_miss_latency::total   1801548428                       # number of demand (read+write) miss cycles
-system.cpu6.l1c.overall_miss_latency::cpu6   1801548428                       # number of overall miss cycles
-system.cpu6.l1c.overall_miss_latency::total   1801548428                       # number of overall miss cycles
-system.cpu6.l1c.ReadReq_accesses::cpu6          44950                       # number of ReadReq accesses(hits+misses)
-system.cpu6.l1c.ReadReq_accesses::total         44950                       # number of ReadReq accesses(hits+misses)
-system.cpu6.l1c.WriteReq_accesses::cpu6         24129                       # number of WriteReq accesses(hits+misses)
-system.cpu6.l1c.WriteReq_accesses::total        24129                       # number of WriteReq accesses(hits+misses)
-system.cpu6.l1c.demand_accesses::cpu6           69079                       # number of demand (read+write) accesses
-system.cpu6.l1c.demand_accesses::total          69079                       # number of demand (read+write) accesses
-system.cpu6.l1c.overall_accesses::cpu6          69079                       # number of overall (read+write) accesses
-system.cpu6.l1c.overall_accesses::total         69079                       # number of overall (read+write) accesses
-system.cpu6.l1c.ReadReq_miss_rate::cpu6      0.806118                       # miss rate for ReadReq accesses
-system.cpu6.l1c.ReadReq_miss_rate::total     0.806118                       # miss rate for ReadReq accesses
-system.cpu6.l1c.WriteReq_miss_rate::cpu6     0.954660                       # miss rate for WriteReq accesses
-system.cpu6.l1c.WriteReq_miss_rate::total     0.954660                       # miss rate for WriteReq accesses
-system.cpu6.l1c.demand_miss_rate::cpu6       0.858003                       # miss rate for demand accesses
-system.cpu6.l1c.demand_miss_rate::total      0.858003                       # miss rate for demand accesses
-system.cpu6.l1c.overall_miss_rate::cpu6      0.858003                       # miss rate for overall accesses
-system.cpu6.l1c.overall_miss_rate::total     0.858003                       # miss rate for overall accesses
-system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 26236.190838                       # average ReadReq miss latency
-system.cpu6.l1c.ReadReq_avg_miss_latency::total 26236.190838                       # average ReadReq miss latency
-system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 36938.574040                       # average WriteReq miss latency
-system.cpu6.l1c.WriteReq_avg_miss_latency::total 36938.574040                       # average WriteReq miss latency
-system.cpu6.l1c.demand_avg_miss_latency::cpu6 30395.620516                       # average overall miss latency
-system.cpu6.l1c.demand_avg_miss_latency::total 30395.620516                       # average overall miss latency
-system.cpu6.l1c.overall_avg_miss_latency::cpu6 30395.620516                       # average overall miss latency
-system.cpu6.l1c.overall_avg_miss_latency::total 30395.620516                       # average overall miss latency
-system.cpu6.l1c.blocked_cycles::no_mshrs      1011987                       # number of cycles access was blocked
+system.cpu6.l1c.tags.tag_accesses              338625                       # Number of tag accesses
+system.cpu6.l1c.tags.data_accesses             338625                       # Number of data accesses
+system.cpu6.l1c.ReadReq_hits::cpu6               8756                       # number of ReadReq hits
+system.cpu6.l1c.ReadReq_hits::total              8756                       # number of ReadReq hits
+system.cpu6.l1c.WriteReq_hits::cpu6              1144                       # number of WriteReq hits
+system.cpu6.l1c.WriteReq_hits::total             1144                       # number of WriteReq hits
+system.cpu6.l1c.demand_hits::cpu6                9900                       # number of demand (read+write) hits
+system.cpu6.l1c.demand_hits::total               9900                       # number of demand (read+write) hits
+system.cpu6.l1c.overall_hits::cpu6               9900                       # number of overall hits
+system.cpu6.l1c.overall_hits::total              9900                       # number of overall hits
+system.cpu6.l1c.ReadReq_misses::cpu6            36780                       # number of ReadReq misses
+system.cpu6.l1c.ReadReq_misses::total           36780                       # number of ReadReq misses
+system.cpu6.l1c.WriteReq_misses::cpu6           23744                       # number of WriteReq misses
+system.cpu6.l1c.WriteReq_misses::total          23744                       # number of WriteReq misses
+system.cpu6.l1c.demand_misses::cpu6             60524                       # number of demand (read+write) misses
+system.cpu6.l1c.demand_misses::total            60524                       # number of demand (read+write) misses
+system.cpu6.l1c.overall_misses::cpu6            60524                       # number of overall misses
+system.cpu6.l1c.overall_misses::total           60524                       # number of overall misses
+system.cpu6.l1c.ReadReq_miss_latency::cpu6    967768080                       # number of ReadReq miss cycles
+system.cpu6.l1c.ReadReq_miss_latency::total    967768080                       # number of ReadReq miss cycles
+system.cpu6.l1c.WriteReq_miss_latency::cpu6    885331630                       # number of WriteReq miss cycles
+system.cpu6.l1c.WriteReq_miss_latency::total    885331630                       # number of WriteReq miss cycles
+system.cpu6.l1c.demand_miss_latency::cpu6   1853099710                       # number of demand (read+write) miss cycles
+system.cpu6.l1c.demand_miss_latency::total   1853099710                       # number of demand (read+write) miss cycles
+system.cpu6.l1c.overall_miss_latency::cpu6   1853099710                       # number of overall miss cycles
+system.cpu6.l1c.overall_miss_latency::total   1853099710                       # number of overall miss cycles
+system.cpu6.l1c.ReadReq_accesses::cpu6          45536                       # number of ReadReq accesses(hits+misses)
+system.cpu6.l1c.ReadReq_accesses::total         45536                       # number of ReadReq accesses(hits+misses)
+system.cpu6.l1c.WriteReq_accesses::cpu6         24888                       # number of WriteReq accesses(hits+misses)
+system.cpu6.l1c.WriteReq_accesses::total        24888                       # number of WriteReq accesses(hits+misses)
+system.cpu6.l1c.demand_accesses::cpu6           70424                       # number of demand (read+write) accesses
+system.cpu6.l1c.demand_accesses::total          70424                       # number of demand (read+write) accesses
+system.cpu6.l1c.overall_accesses::cpu6          70424                       # number of overall (read+write) accesses
+system.cpu6.l1c.overall_accesses::total         70424                       # number of overall (read+write) accesses
+system.cpu6.l1c.ReadReq_miss_rate::cpu6      0.807713                       # miss rate for ReadReq accesses
+system.cpu6.l1c.ReadReq_miss_rate::total     0.807713                       # miss rate for ReadReq accesses
+system.cpu6.l1c.WriteReq_miss_rate::cpu6     0.954034                       # miss rate for WriteReq accesses
+system.cpu6.l1c.WriteReq_miss_rate::total     0.954034                       # miss rate for WriteReq accesses
+system.cpu6.l1c.demand_miss_rate::cpu6       0.859423                       # miss rate for demand accesses
+system.cpu6.l1c.demand_miss_rate::total      0.859423                       # miss rate for demand accesses
+system.cpu6.l1c.overall_miss_rate::cpu6      0.859423                       # miss rate for overall accesses
+system.cpu6.l1c.overall_miss_rate::total     0.859423                       # miss rate for overall accesses
+system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 26312.345840                       # average ReadReq miss latency
+system.cpu6.l1c.ReadReq_avg_miss_latency::total 26312.345840                       # average ReadReq miss latency
+system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 37286.541021                       # average WriteReq miss latency
+system.cpu6.l1c.WriteReq_avg_miss_latency::total 37286.541021                       # average WriteReq miss latency
+system.cpu6.l1c.demand_avg_miss_latency::cpu6 30617.601447                       # average overall miss latency
+system.cpu6.l1c.demand_avg_miss_latency::total 30617.601447                       # average overall miss latency
+system.cpu6.l1c.overall_avg_miss_latency::cpu6 30617.601447                       # average overall miss latency
+system.cpu6.l1c.overall_avg_miss_latency::total 30617.601447                       # average overall miss latency
+system.cpu6.l1c.blocked_cycles::no_mshrs      1031115                       # number of cycles access was blocked
 system.cpu6.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu6.l1c.blocked::no_mshrs               61933                       # number of cycles access was blocked
+system.cpu6.l1c.blocked::no_mshrs               63035                       # number of cycles access was blocked
 system.cpu6.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
-system.cpu6.l1c.avg_blocked_cycles::no_mshrs    16.340029                       # average number of cycles each access was blocked
+system.cpu6.l1c.avg_blocked_cycles::no_mshrs    16.357817                       # average number of cycles each access was blocked
 system.cpu6.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu6.l1c.fast_writes                         0                       # number of fast writes performed
 system.cpu6.l1c.cache_copies                        0                       # number of cache copies performed
-system.cpu6.l1c.writebacks::writebacks           9690                       # number of writebacks
-system.cpu6.l1c.writebacks::total                9690                       # number of writebacks
-system.cpu6.l1c.ReadReq_mshr_misses::cpu6        36235                       # number of ReadReq MSHR misses
-system.cpu6.l1c.ReadReq_mshr_misses::total        36235                       # number of ReadReq MSHR misses
-system.cpu6.l1c.WriteReq_mshr_misses::cpu6        23035                       # number of WriteReq MSHR misses
-system.cpu6.l1c.WriteReq_mshr_misses::total        23035                       # number of WriteReq MSHR misses
-system.cpu6.l1c.demand_mshr_misses::cpu6        59270                       # number of demand (read+write) MSHR misses
-system.cpu6.l1c.demand_mshr_misses::total        59270                       # number of demand (read+write) MSHR misses
-system.cpu6.l1c.overall_mshr_misses::cpu6        59270                       # number of overall MSHR misses
-system.cpu6.l1c.overall_mshr_misses::total        59270                       # number of overall MSHR misses
-system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6    873220563                       # number of ReadReq MSHR miss cycles
-system.cpu6.l1c.ReadReq_mshr_miss_latency::total    873220563                       # number of ReadReq MSHR miss cycles
-system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6    802141037                       # number of WriteReq MSHR miss cycles
-system.cpu6.l1c.WriteReq_mshr_miss_latency::total    802141037                       # number of WriteReq MSHR miss cycles
-system.cpu6.l1c.demand_mshr_miss_latency::cpu6   1675361600                       # number of demand (read+write) MSHR miss cycles
-system.cpu6.l1c.demand_mshr_miss_latency::total   1675361600                       # number of demand (read+write) MSHR miss cycles
-system.cpu6.l1c.overall_mshr_miss_latency::cpu6   1675361600                       # number of overall MSHR miss cycles
-system.cpu6.l1c.overall_mshr_miss_latency::total   1675361600                       # number of overall MSHR miss cycles
-system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6    697661939                       # number of ReadReq MSHR uncacheable cycles
-system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total    697661939                       # number of ReadReq MSHR uncacheable cycles
-system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6   1639994129                       # number of WriteReq MSHR uncacheable cycles
-system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total   1639994129                       # number of WriteReq MSHR uncacheable cycles
-system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6   2337656068                       # number of overall MSHR uncacheable cycles
-system.cpu6.l1c.overall_mshr_uncacheable_latency::total   2337656068                       # number of overall MSHR uncacheable cycles
-system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6     0.806118                       # mshr miss rate for ReadReq accesses
-system.cpu6.l1c.ReadReq_mshr_miss_rate::total     0.806118                       # mshr miss rate for ReadReq accesses
-system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6     0.954660                       # mshr miss rate for WriteReq accesses
-system.cpu6.l1c.WriteReq_mshr_miss_rate::total     0.954660                       # mshr miss rate for WriteReq accesses
-system.cpu6.l1c.demand_mshr_miss_rate::cpu6     0.858003                       # mshr miss rate for demand accesses
-system.cpu6.l1c.demand_mshr_miss_rate::total     0.858003                       # mshr miss rate for demand accesses
-system.cpu6.l1c.overall_mshr_miss_rate::cpu6     0.858003                       # mshr miss rate for overall accesses
-system.cpu6.l1c.overall_mshr_miss_rate::total     0.858003                       # mshr miss rate for overall accesses
-system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 24098.815041                       # average ReadReq mshr miss latency
-system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 24098.815041                       # average ReadReq mshr miss latency
-system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 34822.706186                       # average WriteReq mshr miss latency
-system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 34822.706186                       # average WriteReq mshr miss latency
-system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 28266.603678                       # average overall mshr miss latency
-system.cpu6.l1c.demand_avg_mshr_miss_latency::total 28266.603678                       # average overall mshr miss latency
-system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 28266.603678                       # average overall mshr miss latency
-system.cpu6.l1c.overall_avg_mshr_miss_latency::total 28266.603678                       # average overall mshr miss latency
+system.cpu6.l1c.writebacks::writebacks           9778                       # number of writebacks
+system.cpu6.l1c.writebacks::total                9778                       # number of writebacks
+system.cpu6.l1c.ReadReq_mshr_misses::cpu6        36780                       # number of ReadReq MSHR misses
+system.cpu6.l1c.ReadReq_mshr_misses::total        36780                       # number of ReadReq MSHR misses
+system.cpu6.l1c.WriteReq_mshr_misses::cpu6        23744                       # number of WriteReq MSHR misses
+system.cpu6.l1c.WriteReq_mshr_misses::total        23744                       # number of WriteReq MSHR misses
+system.cpu6.l1c.demand_mshr_misses::cpu6        60524                       # number of demand (read+write) MSHR misses
+system.cpu6.l1c.demand_mshr_misses::total        60524                       # number of demand (read+write) MSHR misses
+system.cpu6.l1c.overall_mshr_misses::cpu6        60524                       # number of overall MSHR misses
+system.cpu6.l1c.overall_mshr_misses::total        60524                       # number of overall MSHR misses
+system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6    889223312                       # number of ReadReq MSHR miss cycles
+system.cpu6.l1c.ReadReq_mshr_miss_latency::total    889223312                       # number of ReadReq MSHR miss cycles
+system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6    835020954                       # number of WriteReq MSHR miss cycles
+system.cpu6.l1c.WriteReq_mshr_miss_latency::total    835020954                       # number of WriteReq MSHR miss cycles
+system.cpu6.l1c.demand_mshr_miss_latency::cpu6   1724244266                       # number of demand (read+write) MSHR miss cycles
+system.cpu6.l1c.demand_mshr_miss_latency::total   1724244266                       # number of demand (read+write) MSHR miss cycles
+system.cpu6.l1c.overall_mshr_miss_latency::cpu6   1724244266                       # number of overall MSHR miss cycles
+system.cpu6.l1c.overall_mshr_miss_latency::total   1724244266                       # number of overall MSHR miss cycles
+system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6    698387416                       # number of ReadReq MSHR uncacheable cycles
+system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total    698387416                       # number of ReadReq MSHR uncacheable cycles
+system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6   1741021536                       # number of WriteReq MSHR uncacheable cycles
+system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total   1741021536                       # number of WriteReq MSHR uncacheable cycles
+system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6   2439408952                       # number of overall MSHR uncacheable cycles
+system.cpu6.l1c.overall_mshr_uncacheable_latency::total   2439408952                       # number of overall MSHR uncacheable cycles
+system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6     0.807713                       # mshr miss rate for ReadReq accesses
+system.cpu6.l1c.ReadReq_mshr_miss_rate::total     0.807713                       # mshr miss rate for ReadReq accesses
+system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6     0.954034                       # mshr miss rate for WriteReq accesses
+system.cpu6.l1c.WriteReq_mshr_miss_rate::total     0.954034                       # mshr miss rate for WriteReq accesses
+system.cpu6.l1c.demand_mshr_miss_rate::cpu6     0.859423                       # mshr miss rate for demand accesses
+system.cpu6.l1c.demand_mshr_miss_rate::total     0.859423                       # mshr miss rate for demand accesses
+system.cpu6.l1c.overall_mshr_miss_rate::cpu6     0.859423                       # mshr miss rate for overall accesses
+system.cpu6.l1c.overall_mshr_miss_rate::total     0.859423                       # mshr miss rate for overall accesses
+system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 24176.816531                       # average ReadReq mshr miss latency
+system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 24176.816531                       # average ReadReq mshr miss latency
+system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 35167.661472                       # average WriteReq mshr miss latency
+system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 35167.661472                       # average WriteReq mshr miss latency
+system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 28488.603959                       # average overall mshr miss latency
+system.cpu6.l1c.demand_avg_mshr_miss_latency::total 28488.603959                       # average overall mshr miss latency
+system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 28488.603959                       # average overall mshr miss latency
+system.cpu6.l1c.overall_avg_mshr_miss_latency::total 28488.603959                       # average overall mshr miss latency
 system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6          inf                       # average ReadReq mshr uncacheable latency
 system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6          inf                       # average WriteReq mshr uncacheable latency
@@ -1584,120 +1585,120 @@ system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total          inf
 system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6          inf                       # average overall mshr uncacheable latency
 system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu6.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
-system.cpu7.num_reads                           99207                       # number of read accesses completed
-system.cpu7.num_writes                          53401                       # number of write accesses completed
+system.cpu7.num_reads                           99455                       # number of read accesses completed
+system.cpu7.num_writes                          55321                       # number of write accesses completed
 system.cpu7.num_copies                              0                       # number of copy accesses completed
-system.cpu7.l1c.tags.replacements               22143                       # number of replacements
-system.cpu7.l1c.tags.tagsinuse             394.587693                       # Cycle average of tags in use
-system.cpu7.l1c.tags.total_refs                 13403                       # Total number of references to valid blocks.
-system.cpu7.l1c.tags.sampled_refs               22544                       # Sample count of references to valid blocks.
-system.cpu7.l1c.tags.avg_refs                0.594526                       # Average number of references to valid blocks.
+system.cpu7.l1c.tags.replacements               22276                       # number of replacements
+system.cpu7.l1c.tags.tagsinuse             392.282274                       # Cycle average of tags in use
+system.cpu7.l1c.tags.total_refs                 13267                       # Total number of references to valid blocks.
+system.cpu7.l1c.tags.sampled_refs               22648                       # Sample count of references to valid blocks.
+system.cpu7.l1c.tags.avg_refs                0.585791                       # Average number of references to valid blocks.
 system.cpu7.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
-system.cpu7.l1c.tags.occ_blocks::cpu7      394.587693                       # Average occupied blocks per requestor
-system.cpu7.l1c.tags.occ_percent::cpu7       0.770679                       # Average percentage of cache occupancy
-system.cpu7.l1c.tags.occ_percent::total      0.770679                       # Average percentage of cache occupancy
-system.cpu7.l1c.tags.occ_task_id_blocks::1024          401                       # Occupied blocks per task id
-system.cpu7.l1c.tags.age_task_id_blocks_1024::0          370                       # Occupied blocks per task id
-system.cpu7.l1c.tags.age_task_id_blocks_1024::1           31                       # Occupied blocks per task id
-system.cpu7.l1c.tags.occ_task_id_percent::1024     0.783203                       # Percentage of cache occupancy per task id
-system.cpu7.l1c.tags.tag_accesses              331300                       # Number of tag accesses
-system.cpu7.l1c.tags.data_accesses             331300                       # Number of data accesses
-system.cpu7.l1c.ReadReq_hits::cpu7               8635                       # number of ReadReq hits
-system.cpu7.l1c.ReadReq_hits::total              8635                       # number of ReadReq hits
-system.cpu7.l1c.WriteReq_hits::cpu7              1078                       # number of WriteReq hits
-system.cpu7.l1c.WriteReq_hits::total             1078                       # number of WriteReq hits
-system.cpu7.l1c.demand_hits::cpu7                9713                       # number of demand (read+write) hits
-system.cpu7.l1c.demand_hits::total               9713                       # number of demand (read+write) hits
-system.cpu7.l1c.overall_hits::cpu7               9713                       # number of overall hits
-system.cpu7.l1c.overall_hits::total              9713                       # number of overall hits
-system.cpu7.l1c.ReadReq_misses::cpu7            36141                       # number of ReadReq misses
-system.cpu7.l1c.ReadReq_misses::total           36141                       # number of ReadReq misses
-system.cpu7.l1c.WriteReq_misses::cpu7           23098                       # number of WriteReq misses
-system.cpu7.l1c.WriteReq_misses::total          23098                       # number of WriteReq misses
-system.cpu7.l1c.demand_misses::cpu7             59239                       # number of demand (read+write) misses
-system.cpu7.l1c.demand_misses::total            59239                       # number of demand (read+write) misses
-system.cpu7.l1c.overall_misses::cpu7            59239                       # number of overall misses
-system.cpu7.l1c.overall_misses::total           59239                       # number of overall misses
-system.cpu7.l1c.ReadReq_miss_latency::cpu7    942615817                       # number of ReadReq miss cycles
-system.cpu7.l1c.ReadReq_miss_latency::total    942615817                       # number of ReadReq miss cycles
-system.cpu7.l1c.WriteReq_miss_latency::cpu7    859348059                       # number of WriteReq miss cycles
-system.cpu7.l1c.WriteReq_miss_latency::total    859348059                       # number of WriteReq miss cycles
-system.cpu7.l1c.demand_miss_latency::cpu7   1801963876                       # number of demand (read+write) miss cycles
-system.cpu7.l1c.demand_miss_latency::total   1801963876                       # number of demand (read+write) miss cycles
-system.cpu7.l1c.overall_miss_latency::cpu7   1801963876                       # number of overall miss cycles
-system.cpu7.l1c.overall_miss_latency::total   1801963876                       # number of overall miss cycles
-system.cpu7.l1c.ReadReq_accesses::cpu7          44776                       # number of ReadReq accesses(hits+misses)
-system.cpu7.l1c.ReadReq_accesses::total         44776                       # number of ReadReq accesses(hits+misses)
-system.cpu7.l1c.WriteReq_accesses::cpu7         24176                       # number of WriteReq accesses(hits+misses)
-system.cpu7.l1c.WriteReq_accesses::total        24176                       # number of WriteReq accesses(hits+misses)
-system.cpu7.l1c.demand_accesses::cpu7           68952                       # number of demand (read+write) accesses
-system.cpu7.l1c.demand_accesses::total          68952                       # number of demand (read+write) accesses
-system.cpu7.l1c.overall_accesses::cpu7          68952                       # number of overall (read+write) accesses
-system.cpu7.l1c.overall_accesses::total         68952                       # number of overall (read+write) accesses
-system.cpu7.l1c.ReadReq_miss_rate::cpu7      0.807151                       # miss rate for ReadReq accesses
-system.cpu7.l1c.ReadReq_miss_rate::total     0.807151                       # miss rate for ReadReq accesses
-system.cpu7.l1c.WriteReq_miss_rate::cpu7     0.955410                       # miss rate for WriteReq accesses
-system.cpu7.l1c.WriteReq_miss_rate::total     0.955410                       # miss rate for WriteReq accesses
-system.cpu7.l1c.demand_miss_rate::cpu7       0.859134                       # miss rate for demand accesses
-system.cpu7.l1c.demand_miss_rate::total      0.859134                       # miss rate for demand accesses
-system.cpu7.l1c.overall_miss_rate::cpu7      0.859134                       # miss rate for overall accesses
-system.cpu7.l1c.overall_miss_rate::total     0.859134                       # miss rate for overall accesses
-system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 26081.619684                       # average ReadReq miss latency
-system.cpu7.l1c.ReadReq_avg_miss_latency::total 26081.619684                       # average ReadReq miss latency
-system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 37204.435839                       # average WriteReq miss latency
-system.cpu7.l1c.WriteReq_avg_miss_latency::total 37204.435839                       # average WriteReq miss latency
-system.cpu7.l1c.demand_avg_miss_latency::cpu7 30418.539746                       # average overall miss latency
-system.cpu7.l1c.demand_avg_miss_latency::total 30418.539746                       # average overall miss latency
-system.cpu7.l1c.overall_avg_miss_latency::cpu7 30418.539746                       # average overall miss latency
-system.cpu7.l1c.overall_avg_miss_latency::total 30418.539746                       # average overall miss latency
-system.cpu7.l1c.blocked_cycles::no_mshrs      1024987                       # number of cycles access was blocked
+system.cpu7.l1c.tags.occ_blocks::cpu7      392.282274                       # Average occupied blocks per requestor
+system.cpu7.l1c.tags.occ_percent::cpu7       0.766176                       # Average percentage of cache occupancy
+system.cpu7.l1c.tags.occ_percent::total      0.766176                       # Average percentage of cache occupancy
+system.cpu7.l1c.tags.occ_task_id_blocks::1024          372                       # Occupied blocks per task id
+system.cpu7.l1c.tags.age_task_id_blocks_1024::0          356                       # Occupied blocks per task id
+system.cpu7.l1c.tags.age_task_id_blocks_1024::1           16                       # Occupied blocks per task id
+system.cpu7.l1c.tags.occ_task_id_percent::1024     0.726562                       # Percentage of cache occupancy per task id
+system.cpu7.l1c.tags.tag_accesses              337172                       # Number of tag accesses
+system.cpu7.l1c.tags.data_accesses             337172                       # Number of data accesses
+system.cpu7.l1c.ReadReq_hits::cpu7               8517                       # number of ReadReq hits
+system.cpu7.l1c.ReadReq_hits::total              8517                       # number of ReadReq hits
+system.cpu7.l1c.WriteReq_hits::cpu7              1168                       # number of WriteReq hits
+system.cpu7.l1c.WriteReq_hits::total             1168                       # number of WriteReq hits
+system.cpu7.l1c.demand_hits::cpu7                9685                       # number of demand (read+write) hits
+system.cpu7.l1c.demand_hits::total               9685                       # number of demand (read+write) hits
+system.cpu7.l1c.overall_hits::cpu7               9685                       # number of overall hits
+system.cpu7.l1c.overall_hits::total              9685                       # number of overall hits
+system.cpu7.l1c.ReadReq_misses::cpu7            36632                       # number of ReadReq misses
+system.cpu7.l1c.ReadReq_misses::total           36632                       # number of ReadReq misses
+system.cpu7.l1c.WriteReq_misses::cpu7           23782                       # number of WriteReq misses
+system.cpu7.l1c.WriteReq_misses::total          23782                       # number of WriteReq misses
+system.cpu7.l1c.demand_misses::cpu7             60414                       # number of demand (read+write) misses
+system.cpu7.l1c.demand_misses::total            60414                       # number of demand (read+write) misses
+system.cpu7.l1c.overall_misses::cpu7            60414                       # number of overall misses
+system.cpu7.l1c.overall_misses::total           60414                       # number of overall misses
+system.cpu7.l1c.ReadReq_miss_latency::cpu7    969238606                       # number of ReadReq miss cycles
+system.cpu7.l1c.ReadReq_miss_latency::total    969238606                       # number of ReadReq miss cycles
+system.cpu7.l1c.WriteReq_miss_latency::cpu7    880763834                       # number of WriteReq miss cycles
+system.cpu7.l1c.WriteReq_miss_latency::total    880763834                       # number of WriteReq miss cycles
+system.cpu7.l1c.demand_miss_latency::cpu7   1850002440                       # number of demand (read+write) miss cycles
+system.cpu7.l1c.demand_miss_latency::total   1850002440                       # number of demand (read+write) miss cycles
+system.cpu7.l1c.overall_miss_latency::cpu7   1850002440                       # number of overall miss cycles
+system.cpu7.l1c.overall_miss_latency::total   1850002440                       # number of overall miss cycles
+system.cpu7.l1c.ReadReq_accesses::cpu7          45149                       # number of ReadReq accesses(hits+misses)
+system.cpu7.l1c.ReadReq_accesses::total         45149                       # number of ReadReq accesses(hits+misses)
+system.cpu7.l1c.WriteReq_accesses::cpu7         24950                       # number of WriteReq accesses(hits+misses)
+system.cpu7.l1c.WriteReq_accesses::total        24950                       # number of WriteReq accesses(hits+misses)
+system.cpu7.l1c.demand_accesses::cpu7           70099                       # number of demand (read+write) accesses
+system.cpu7.l1c.demand_accesses::total          70099                       # number of demand (read+write) accesses
+system.cpu7.l1c.overall_accesses::cpu7          70099                       # number of overall (read+write) accesses
+system.cpu7.l1c.overall_accesses::total         70099                       # number of overall (read+write) accesses
+system.cpu7.l1c.ReadReq_miss_rate::cpu7      0.811358                       # miss rate for ReadReq accesses
+system.cpu7.l1c.ReadReq_miss_rate::total     0.811358                       # miss rate for ReadReq accesses
+system.cpu7.l1c.WriteReq_miss_rate::cpu7     0.953186                       # miss rate for WriteReq accesses
+system.cpu7.l1c.WriteReq_miss_rate::total     0.953186                       # miss rate for WriteReq accesses
+system.cpu7.l1c.demand_miss_rate::cpu7       0.861838                       # miss rate for demand accesses
+system.cpu7.l1c.demand_miss_rate::total      0.861838                       # miss rate for demand accesses
+system.cpu7.l1c.overall_miss_rate::cpu7      0.861838                       # miss rate for overall accesses
+system.cpu7.l1c.overall_miss_rate::total     0.861838                       # miss rate for overall accesses
+system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 26458.795752                       # average ReadReq miss latency
+system.cpu7.l1c.ReadReq_avg_miss_latency::total 26458.795752                       # average ReadReq miss latency
+system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 37034.893365                       # average WriteReq miss latency
+system.cpu7.l1c.WriteReq_avg_miss_latency::total 37034.893365                       # average WriteReq miss latency
+system.cpu7.l1c.demand_avg_miss_latency::cpu7 30622.081637                       # average overall miss latency
+system.cpu7.l1c.demand_avg_miss_latency::total 30622.081637                       # average overall miss latency
+system.cpu7.l1c.overall_avg_miss_latency::cpu7 30622.081637                       # average overall miss latency
+system.cpu7.l1c.overall_avg_miss_latency::total 30622.081637                       # average overall miss latency
+system.cpu7.l1c.blocked_cycles::no_mshrs      1029627                       # number of cycles access was blocked
 system.cpu7.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu7.l1c.blocked::no_mshrs               62690                       # number of cycles access was blocked
+system.cpu7.l1c.blocked::no_mshrs               62765                       # number of cycles access was blocked
 system.cpu7.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
-system.cpu7.l1c.avg_blocked_cycles::no_mshrs    16.350088                       # average number of cycles each access was blocked
+system.cpu7.l1c.avg_blocked_cycles::no_mshrs    16.404477                       # average number of cycles each access was blocked
 system.cpu7.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu7.l1c.fast_writes                         0                       # number of fast writes performed
 system.cpu7.l1c.cache_copies                        0                       # number of cache copies performed
-system.cpu7.l1c.writebacks::writebacks           9629                       # number of writebacks
-system.cpu7.l1c.writebacks::total                9629                       # number of writebacks
-system.cpu7.l1c.ReadReq_mshr_misses::cpu7        36141                       # number of ReadReq MSHR misses
-system.cpu7.l1c.ReadReq_mshr_misses::total        36141                       # number of ReadReq MSHR misses
-system.cpu7.l1c.WriteReq_mshr_misses::cpu7        23098                       # number of WriteReq MSHR misses
-system.cpu7.l1c.WriteReq_mshr_misses::total        23098                       # number of WriteReq MSHR misses
-system.cpu7.l1c.demand_mshr_misses::cpu7        59239                       # number of demand (read+write) MSHR misses
-system.cpu7.l1c.demand_mshr_misses::total        59239                       # number of demand (read+write) MSHR misses
-system.cpu7.l1c.overall_mshr_misses::cpu7        59239                       # number of overall MSHR misses
-system.cpu7.l1c.overall_mshr_misses::total        59239                       # number of overall MSHR misses
-system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7    865505701                       # number of ReadReq MSHR miss cycles
-system.cpu7.l1c.ReadReq_mshr_miss_latency::total    865505701                       # number of ReadReq MSHR miss cycles
-system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7    810567819                       # number of WriteReq MSHR miss cycles
-system.cpu7.l1c.WriteReq_mshr_miss_latency::total    810567819                       # number of WriteReq MSHR miss cycles
-system.cpu7.l1c.demand_mshr_miss_latency::cpu7   1676073520                       # number of demand (read+write) MSHR miss cycles
-system.cpu7.l1c.demand_mshr_miss_latency::total   1676073520                       # number of demand (read+write) MSHR miss cycles
-system.cpu7.l1c.overall_mshr_miss_latency::cpu7   1676073520                       # number of overall MSHR miss cycles
-system.cpu7.l1c.overall_mshr_miss_latency::total   1676073520                       # number of overall MSHR miss cycles
-system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7    711693302                       # number of ReadReq MSHR uncacheable cycles
-system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total    711693302                       # number of ReadReq MSHR uncacheable cycles
-system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7   1603062205                       # number of WriteReq MSHR uncacheable cycles
-system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total   1603062205                       # number of WriteReq MSHR uncacheable cycles
-system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7   2314755507                       # number of overall MSHR uncacheable cycles
-system.cpu7.l1c.overall_mshr_uncacheable_latency::total   2314755507                       # number of overall MSHR uncacheable cycles
-system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7     0.807151                       # mshr miss rate for ReadReq accesses
-system.cpu7.l1c.ReadReq_mshr_miss_rate::total     0.807151                       # mshr miss rate for ReadReq accesses
-system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7     0.955410                       # mshr miss rate for WriteReq accesses
-system.cpu7.l1c.WriteReq_mshr_miss_rate::total     0.955410                       # mshr miss rate for WriteReq accesses
-system.cpu7.l1c.demand_mshr_miss_rate::cpu7     0.859134                       # mshr miss rate for demand accesses
-system.cpu7.l1c.demand_mshr_miss_rate::total     0.859134                       # mshr miss rate for demand accesses
-system.cpu7.l1c.overall_mshr_miss_rate::cpu7     0.859134                       # mshr miss rate for overall accesses
-system.cpu7.l1c.overall_mshr_miss_rate::total     0.859134                       # mshr miss rate for overall accesses
-system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 23948.028582                       # average ReadReq mshr miss latency
-system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 23948.028582                       # average ReadReq mshr miss latency
-system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 35092.554290                       # average WriteReq mshr miss latency
-system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 35092.554290                       # average WriteReq mshr miss latency
-system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 28293.413461                       # average overall mshr miss latency
-system.cpu7.l1c.demand_avg_mshr_miss_latency::total 28293.413461                       # average overall mshr miss latency
-system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 28293.413461                       # average overall mshr miss latency
-system.cpu7.l1c.overall_avg_mshr_miss_latency::total 28293.413461                       # average overall mshr miss latency
+system.cpu7.l1c.writebacks::writebacks           9888                       # number of writebacks
+system.cpu7.l1c.writebacks::total                9888                       # number of writebacks
+system.cpu7.l1c.ReadReq_mshr_misses::cpu7        36632                       # number of ReadReq MSHR misses
+system.cpu7.l1c.ReadReq_mshr_misses::total        36632                       # number of ReadReq MSHR misses
+system.cpu7.l1c.WriteReq_mshr_misses::cpu7        23782                       # number of WriteReq MSHR misses
+system.cpu7.l1c.WriteReq_mshr_misses::total        23782                       # number of WriteReq MSHR misses
+system.cpu7.l1c.demand_mshr_misses::cpu7        60414                       # number of demand (read+write) MSHR misses
+system.cpu7.l1c.demand_mshr_misses::total        60414                       # number of demand (read+write) MSHR misses
+system.cpu7.l1c.overall_mshr_misses::cpu7        60414                       # number of overall MSHR misses
+system.cpu7.l1c.overall_mshr_misses::total        60414                       # number of overall MSHR misses
+system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7    891054702                       # number of ReadReq MSHR miss cycles
+system.cpu7.l1c.ReadReq_mshr_miss_latency::total    891054702                       # number of ReadReq MSHR miss cycles
+system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7    830452960                       # number of WriteReq MSHR miss cycles
+system.cpu7.l1c.WriteReq_mshr_miss_latency::total    830452960                       # number of WriteReq MSHR miss cycles
+system.cpu7.l1c.demand_mshr_miss_latency::cpu7   1721507662                       # number of demand (read+write) MSHR miss cycles
+system.cpu7.l1c.demand_mshr_miss_latency::total   1721507662                       # number of demand (read+write) MSHR miss cycles
+system.cpu7.l1c.overall_mshr_miss_latency::cpu7   1721507662                       # number of overall MSHR miss cycles
+system.cpu7.l1c.overall_mshr_miss_latency::total   1721507662                       # number of overall MSHR miss cycles
+system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7    698299057                       # number of ReadReq MSHR uncacheable cycles
+system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total    698299057                       # number of ReadReq MSHR uncacheable cycles
+system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7   1725454906                       # number of WriteReq MSHR uncacheable cycles
+system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total   1725454906                       # number of WriteReq MSHR uncacheable cycles
+system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7   2423753963                       # number of overall MSHR uncacheable cycles
+system.cpu7.l1c.overall_mshr_uncacheable_latency::total   2423753963                       # number of overall MSHR uncacheable cycles
+system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7     0.811358                       # mshr miss rate for ReadReq accesses
+system.cpu7.l1c.ReadReq_mshr_miss_rate::total     0.811358                       # mshr miss rate for ReadReq accesses
+system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7     0.953186                       # mshr miss rate for WriteReq accesses
+system.cpu7.l1c.WriteReq_mshr_miss_rate::total     0.953186                       # mshr miss rate for WriteReq accesses
+system.cpu7.l1c.demand_mshr_miss_rate::cpu7     0.861838                       # mshr miss rate for demand accesses
+system.cpu7.l1c.demand_mshr_miss_rate::total     0.861838                       # mshr miss rate for demand accesses
+system.cpu7.l1c.overall_mshr_miss_rate::cpu7     0.861838                       # mshr miss rate for overall accesses
+system.cpu7.l1c.overall_mshr_miss_rate::total     0.861838                       # mshr miss rate for overall accesses
+system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 24324.489572                       # average ReadReq mshr miss latency
+system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 24324.489572                       # average ReadReq mshr miss latency
+system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 34919.391136                       # average WriteReq mshr miss latency
+system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 34919.391136                       # average WriteReq mshr miss latency
+system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 28495.177641                       # average overall mshr miss latency
+system.cpu7.l1c.demand_avg_mshr_miss_latency::total 28495.177641                       # average overall mshr miss latency
+system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 28495.177641                       # average overall mshr miss latency
+system.cpu7.l1c.overall_avg_mshr_miss_latency::total 28495.177641                       # average overall mshr miss latency
 system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7          inf                       # average ReadReq mshr uncacheable latency
 system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7          inf                       # average WriteReq mshr uncacheable latency
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/stats.txt
index 4cbff215b..c1d5ff6e5 100644
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/stats.txt
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/stats.txt
@@ -1,60 +1,60 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000312                       # Number of seconds simulated
-sim_ticks                                      312261                       # Number of ticks simulated
-final_tick                                     312261                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.000328                       # Number of seconds simulated
+sim_ticks                                      327571                       # Number of ticks simulated
+final_tick                                     327571                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_tick_rate                                1203947                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 170440                       # Number of bytes of host memory used
+host_tick_rate                                1251967                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 128368                       # Number of bytes of host memory used
 host_seconds                                     0.26                       # Real time elapsed on the host
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                             1                       # Clock period in ticks
 system.ruby.clk_domain.clock                        1                       # Clock period in ticks
 system.ruby.delayHist::bucket_size                512                       # delay histogram for all message
 system.ruby.delayHist::max_bucket                5119                       # delay histogram for all message
-system.ruby.delayHist::samples                   6975                       # delay histogram for all message
-system.ruby.delayHist::mean                 57.310251                       # delay histogram for all message
-system.ruby.delayHist::stdev               258.377513                       # delay histogram for all message
-system.ruby.delayHist                    |        6687     95.87%     95.87% |         165      2.37%     98.24% |          67      0.96%     99.20% |          29      0.42%     99.61% |          15      0.22%     99.83% |           8      0.11%     99.94% |           4      0.06%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for all message
-system.ruby.delayHist::total                     6975                       # delay histogram for all message
+system.ruby.delayHist::samples                   7183                       # delay histogram for all message
+system.ruby.delayHist::mean                 55.693443                       # delay histogram for all message
+system.ruby.delayHist::stdev               252.452700                       # delay histogram for all message
+system.ruby.delayHist                    |        6908     96.17%     96.17% |         159      2.21%     98.39% |          57      0.79%     99.18% |          31      0.43%     99.61% |          18      0.25%     99.86% |           9      0.13%     99.99% |           0      0.00%     99.99% |           0      0.00%     99.99% |           1      0.01%    100.00% |           0      0.00%    100.00% # delay histogram for all message
+system.ruby.delayHist::total                     7183                       # delay histogram for all message
 system.ruby.outstanding_req_hist::bucket_size            2                      
 system.ruby.outstanding_req_hist::max_bucket           19                      
-system.ruby.outstanding_req_hist::samples          983                      
-system.ruby.outstanding_req_hist::mean      15.827060                      
-system.ruby.outstanding_req_hist::gmean     15.727011                      
-system.ruby.outstanding_req_hist::stdev      1.133008                      
-system.ruby.outstanding_req_hist         |           1      0.10%      0.10% |           2      0.20%      0.31% |           2      0.20%      0.51% |           2      0.20%      0.71% |           2      0.20%      0.92% |           2      0.20%      1.12% |           2      0.20%      1.32% |          52      5.29%      6.61% |         918     93.39%    100.00% |           0      0.00%    100.00%
-system.ruby.outstanding_req_hist::total           983                      
+system.ruby.outstanding_req_hist::samples         1017                      
+system.ruby.outstanding_req_hist::mean      15.830875                      
+system.ruby.outstanding_req_hist::gmean     15.734065                      
+system.ruby.outstanding_req_hist::stdev      1.114909                      
+system.ruby.outstanding_req_hist         |           1      0.10%      0.10% |           2      0.20%      0.29% |           2      0.20%      0.49% |           2      0.20%      0.69% |           2      0.20%      0.88% |           2      0.20%      1.08% |           2      0.20%      1.28% |          54      5.31%      6.59% |         950     93.41%    100.00% |           0      0.00%    100.00%
+system.ruby.outstanding_req_hist::total          1017                      
 system.ruby.latency_hist::bucket_size            1024                      
 system.ruby.latency_hist::max_bucket            10239                      
-system.ruby.latency_hist::samples                 968                      
-system.ruby.latency_hist::mean            5101.012397                      
-system.ruby.latency_hist::gmean           2832.118198                      
-system.ruby.latency_hist::stdev           2084.563420                      
-system.ruby.latency_hist                 |         125     12.91%     12.91% |          22      2.27%     15.19% |           2      0.21%     15.39% |           4      0.41%     15.81% |          57      5.89%     21.69% |         468     48.35%     70.04% |         263     27.17%     97.21% |          27      2.79%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.latency_hist::total                   968                      
+system.ruby.latency_hist::samples                1002                      
+system.ruby.latency_hist::mean            5171.353293                      
+system.ruby.latency_hist::gmean           2828.922262                      
+system.ruby.latency_hist::stdev           2096.025855                      
+system.ruby.latency_hist                 |         135     13.47%     13.47% |          12      1.20%     14.67% |           4      0.40%     15.07% |           4      0.40%     15.47% |          30      2.99%     18.46% |         460     45.91%     64.37% |         320     31.94%     96.31% |          37      3.69%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.latency_hist::total                  1002                      
 system.ruby.hit_latency_hist::bucket_size           16                      
 system.ruby.hit_latency_hist::max_bucket          159                      
-system.ruby.hit_latency_hist::samples              74                      
-system.ruby.hit_latency_hist::mean          11.527027                      
-system.ruby.hit_latency_hist::gmean          3.324632                      
-system.ruby.hit_latency_hist::stdev         29.929242                      
-system.ruby.hit_latency_hist             |          68     91.89%     91.89% |           0      0.00%     91.89% |           0      0.00%     91.89% |           0      0.00%     91.89% |           0      0.00%     91.89% |           0      0.00%     91.89% |           2      2.70%     94.59% |           4      5.41%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.hit_latency_hist::total                74                      
+system.ruby.hit_latency_hist::samples              77                      
+system.ruby.hit_latency_hist::mean           9.597403                      
+system.ruby.hit_latency_hist::gmean          2.761367                      
+system.ruby.hit_latency_hist::stdev         27.303489                      
+system.ruby.hit_latency_hist             |          72     93.51%     93.51% |           0      0.00%     93.51% |           0      0.00%     93.51% |           0      0.00%     93.51% |           0      0.00%     93.51% |           0      0.00%     93.51% |           2      2.60%     96.10% |           3      3.90%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.hit_latency_hist::total                77                      
 system.ruby.miss_latency_hist::bucket_size         1024                      
 system.ruby.miss_latency_hist::max_bucket        10239                      
-system.ruby.miss_latency_hist::samples            894                      
-system.ruby.miss_latency_hist::mean       5522.289709                      
-system.ruby.miss_latency_hist::gmean      4950.736161                      
-system.ruby.miss_latency_hist::stdev      1543.133800                      
-system.ruby.miss_latency_hist            |          51      5.70%      5.70% |          22      2.46%      8.17% |           2      0.22%      8.39% |           4      0.45%      8.84% |          57      6.38%     15.21% |         468     52.35%     67.56% |         263     29.42%     96.98% |          27      3.02%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.miss_latency_hist::total              894                      
-system.ruby.l1_cntrl0.L1Dcache.demand_hits           74                       # Number of cache demand hits
-system.ruby.l1_cntrl0.L1Dcache.demand_misses          839                       # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Dcache.demand_accesses          913                       # Number of cache demand accesses
+system.ruby.miss_latency_hist::samples            925                      
+system.ruby.miss_latency_hist::mean       5601.034595                      
+system.ruby.miss_latency_hist::gmean      5037.610012                      
+system.ruby.miss_latency_hist::stdev      1534.352398                      
+system.ruby.miss_latency_hist            |          58      6.27%      6.27% |          12      1.30%      7.57% |           4      0.43%      8.00% |           4      0.43%      8.43% |          30      3.24%     11.68% |         460     49.73%     61.41% |         320     34.59%     96.00% |          37      4.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.miss_latency_hist::total              925                      
+system.ruby.l1_cntrl0.L1Dcache.demand_hits           77                       # Number of cache demand hits
+system.ruby.l1_cntrl0.L1Dcache.demand_misses          881                       # Number of cache demand misses
+system.ruby.l1_cntrl0.L1Dcache.demand_accesses          958                       # Number of cache demand accesses
 system.ruby.l1_cntrl0.L1Icache.demand_hits            0                       # Number of cache demand hits
-system.ruby.l1_cntrl0.L1Icache.demand_misses           57                       # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Icache.demand_accesses           57                       # Number of cache demand accesses
+system.ruby.l1_cntrl0.L1Icache.demand_misses           46                       # Number of cache demand misses
+system.ruby.l1_cntrl0.L1Icache.demand_accesses           46                       # Number of cache demand accesses
 system.ruby.l1_cntrl0.prefetcher.miss_observed            0                       # number of misses observed
 system.ruby.l1_cntrl0.prefetcher.allocated_streams            0                       # number of streams allocated for prefetching
 system.ruby.l1_cntrl0.prefetcher.prefetches_requested            0                       # number of prefetch requests made
@@ -64,355 +64,355 @@ system.ruby.l1_cntrl0.prefetcher.hits               0                       # nu
 system.ruby.l1_cntrl0.prefetcher.partial_hits            0                       # number of misses observed for a block being prefetched
 system.ruby.l1_cntrl0.prefetcher.pages_crossed            0                       # number of prefetches across pages
 system.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks            0                       # number of misses for blocks that were prefetched, yet missed
-system.ruby.l1_cntrl0.sequencer.store_waiting_on_load            5                       # Number of times a store aliased with a pending load
-system.ruby.l1_cntrl0.sequencer.store_waiting_on_store           80                       # Number of times a store aliased with a pending store
-system.ruby.l1_cntrl0.sequencer.load_waiting_on_store            6                       # Number of times a load aliased with a pending store
-system.ruby.l1_cntrl0.sequencer.load_waiting_on_load            1                       # Number of times a load aliased with a pending load
-system.ruby.network.routers0.percent_links_utilized     1.779361                      
-system.ruby.network.routers0.msg_count.Control::0          896                      
-system.ruby.network.routers0.msg_count.Request_Control::2          559                      
-system.ruby.network.routers0.msg_count.Response_Data::1          894                      
-system.ruby.network.routers0.msg_count.Response_Control::1          812                      
-system.ruby.network.routers0.msg_count.Response_Control::2          837                      
-system.ruby.network.routers0.msg_count.Writeback_Data::0          726                      
-system.ruby.network.routers0.msg_count.Writeback_Data::1          501                      
-system.ruby.network.routers0.msg_count.Writeback_Control::0           32                      
-system.ruby.network.routers0.msg_bytes.Control::0         7168                      
-system.ruby.network.routers0.msg_bytes.Request_Control::2         4472                      
-system.ruby.network.routers0.msg_bytes.Response_Data::1        64368                      
-system.ruby.network.routers0.msg_bytes.Response_Control::1         6496                      
-system.ruby.network.routers0.msg_bytes.Response_Control::2         6696                      
-system.ruby.network.routers0.msg_bytes.Writeback_Data::0        52272                      
-system.ruby.network.routers0.msg_bytes.Writeback_Data::1        36072                      
-system.ruby.network.routers0.msg_bytes.Writeback_Control::0          256                      
-system.ruby.l2_cntrl0.L2cache.demand_hits           32                       # Number of cache demand hits
-system.ruby.l2_cntrl0.L2cache.demand_misses          864                       # Number of cache demand misses
-system.ruby.l2_cntrl0.L2cache.demand_accesses          896                       # Number of cache demand accesses
-system.ruby.network.routers1.percent_links_utilized     3.102133                      
-system.ruby.network.routers1.msg_count.Control::0         1759                      
-system.ruby.network.routers1.msg_count.Request_Control::2          559                      
-system.ruby.network.routers1.msg_count.Response_Data::1         2529                      
-system.ruby.network.routers1.msg_count.Response_Control::1         1756                      
-system.ruby.network.routers1.msg_count.Response_Control::2          837                      
-system.ruby.network.routers1.msg_count.Writeback_Data::0          726                      
-system.ruby.network.routers1.msg_count.Writeback_Data::1          501                      
-system.ruby.network.routers1.msg_count.Writeback_Control::0           32                      
-system.ruby.network.routers1.msg_bytes.Control::0        14072                      
-system.ruby.network.routers1.msg_bytes.Request_Control::2         4472                      
-system.ruby.network.routers1.msg_bytes.Response_Data::1       182088                      
-system.ruby.network.routers1.msg_bytes.Response_Control::1        14048                      
-system.ruby.network.routers1.msg_bytes.Response_Control::2         6696                      
-system.ruby.network.routers1.msg_bytes.Writeback_Data::0        52272                      
-system.ruby.network.routers1.msg_bytes.Writeback_Data::1        36072                      
-system.ruby.network.routers1.msg_bytes.Writeback_Control::0          256                      
+system.ruby.l1_cntrl0.sequencer.store_waiting_on_load            6                       # Number of times a store aliased with a pending load
+system.ruby.l1_cntrl0.sequencer.store_waiting_on_store          110                       # Number of times a store aliased with a pending store
+system.ruby.l1_cntrl0.sequencer.load_waiting_on_store           10                       # Number of times a load aliased with a pending store
+system.ruby.network.routers0.percent_links_utilized     1.749086                      
+system.ruby.network.routers0.msg_count.Control::0          925                      
+system.ruby.network.routers0.msg_count.Request_Control::2          563                      
+system.ruby.network.routers0.msg_count.Response_Data::1          925                      
+system.ruby.network.routers0.msg_count.Response_Control::1          827                      
+system.ruby.network.routers0.msg_count.Response_Control::2          877                      
+system.ruby.network.routers0.msg_count.Writeback_Data::0          742                      
+system.ruby.network.routers0.msg_count.Writeback_Data::1          520                      
+system.ruby.network.routers0.msg_count.Writeback_Control::0           43                      
+system.ruby.network.routers0.msg_bytes.Control::0         7400                      
+system.ruby.network.routers0.msg_bytes.Request_Control::2         4504                      
+system.ruby.network.routers0.msg_bytes.Response_Data::1        66600                      
+system.ruby.network.routers0.msg_bytes.Response_Control::1         6616                      
+system.ruby.network.routers0.msg_bytes.Response_Control::2         7016                      
+system.ruby.network.routers0.msg_bytes.Writeback_Data::0        53424                      
+system.ruby.network.routers0.msg_bytes.Writeback_Data::1        37440                      
+system.ruby.network.routers0.msg_bytes.Writeback_Control::0          344                      
+system.ruby.l2_cntrl0.L2cache.demand_hits           41                       # Number of cache demand hits
+system.ruby.l2_cntrl0.L2cache.demand_misses          884                       # Number of cache demand misses
+system.ruby.l2_cntrl0.L2cache.demand_accesses          925                       # Number of cache demand accesses
+system.ruby.network.routers1.percent_links_utilized     3.043386                      
+system.ruby.network.routers1.msg_count.Control::0         1809                      
+system.ruby.network.routers1.msg_count.Request_Control::2          563                      
+system.ruby.network.routers1.msg_count.Response_Data::1         2604                      
+system.ruby.network.routers1.msg_count.Response_Control::1         1791                      
+system.ruby.network.routers1.msg_count.Response_Control::2          877                      
+system.ruby.network.routers1.msg_count.Writeback_Data::0          742                      
+system.ruby.network.routers1.msg_count.Writeback_Data::1          520                      
+system.ruby.network.routers1.msg_count.Writeback_Control::0           43                      
+system.ruby.network.routers1.msg_bytes.Control::0        14472                      
+system.ruby.network.routers1.msg_bytes.Request_Control::2         4504                      
+system.ruby.network.routers1.msg_bytes.Response_Data::1       187488                      
+system.ruby.network.routers1.msg_bytes.Response_Control::1        14328                      
+system.ruby.network.routers1.msg_bytes.Response_Control::2         7016                      
+system.ruby.network.routers1.msg_bytes.Writeback_Data::0        53424                      
+system.ruby.network.routers1.msg_bytes.Writeback_Data::1        37440                      
+system.ruby.network.routers1.msg_bytes.Writeback_Control::0          344                      
 system.ruby.memctrl_clk_domain.clock                3                       # Clock period in ticks
-system.ruby.dir_cntrl0.memBuffer.memReq          1633                       # Total number of memory requests
-system.ruby.dir_cntrl0.memBuffer.memRead          863                       # Number of memory reads
-system.ruby.dir_cntrl0.memBuffer.memWrite          770                       # Number of memory writes
-system.ruby.dir_cntrl0.memBuffer.memRefresh         2168                       # Number of memory refreshes
-system.ruby.dir_cntrl0.memBuffer.memWaitCycles          631                       # Delay stalled at the head of the bank queue
-system.ruby.dir_cntrl0.memBuffer.memInputQ           46                       # Delay in the input queue
-system.ruby.dir_cntrl0.memBuffer.memBankQ            4                       # Delay behind the head of the bank queue
-system.ruby.dir_cntrl0.memBuffer.totalStalls          681                       # Total number of stall cycles
-system.ruby.dir_cntrl0.memBuffer.stallsPerReq     0.417024                       # Expected number of stall cycles per request
-system.ruby.dir_cntrl0.memBuffer.memBankBusy          209                       # memory stalls due to busy bank
-system.ruby.dir_cntrl0.memBuffer.memBusBusy          210                       # memory stalls due to busy bus
-system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy          102                       # memory stalls due to read write turnaround
-system.ruby.dir_cntrl0.memBuffer.memDataBusBusy           76                       # memory stalls due to read read turnaround
-system.ruby.dir_cntrl0.memBuffer.memArbWait           34                       # memory stalls due to arbitration
-system.ruby.dir_cntrl0.memBuffer.memBankCount |          41      2.51%      2.51% |          47      2.88%      5.39% |          57      3.49%      8.88% |          77      4.72%     13.59% |          68      4.16%     17.76% |          61      3.74%     21.49% |          66      4.04%     25.54% |          57      3.49%     29.03% |          48      2.94%     31.97% |          40      2.45%     34.42% |          51      3.12%     37.54% |          55      3.37%     40.91% |          46      2.82%     43.72% |          63      3.86%     47.58% |          42      2.57%     50.15% |          41      2.51%     52.66% |          40      2.45%     55.11% |          63      3.86%     58.97% |          38      2.33%     61.30% |          41      2.51%     63.81% |          44      2.69%     66.50% |          54      3.31%     69.81% |          50      3.06%     72.87% |          49      3.00%     75.87% |          56      3.43%     79.30% |          41      2.51%     81.81% |          55      3.37%     85.18% |          35      2.14%     87.32% |          45      2.76%     90.08% |          56      3.43%     93.51% |          51      3.12%     96.63% |          55      3.37%    100.00% # Number of accesses per bank
-system.ruby.dir_cntrl0.memBuffer.memBankCount::total         1633                       # Number of accesses per bank
-system.ruby.network.routers2.percent_links_utilized     1.321331                      
-system.ruby.network.routers2.msg_count.Control::0          863                      
-system.ruby.network.routers2.msg_count.Response_Data::1         1633                      
-system.ruby.network.routers2.msg_count.Response_Control::1          944                      
-system.ruby.network.routers2.msg_bytes.Control::0         6904                      
-system.ruby.network.routers2.msg_bytes.Response_Data::1       117576                      
-system.ruby.network.routers2.msg_bytes.Response_Control::1         7552                      
-system.ruby.network.routers3.percent_links_utilized     2.067608                      
-system.ruby.network.routers3.msg_count.Control::0         1759                      
-system.ruby.network.routers3.msg_count.Request_Control::2          559                      
-system.ruby.network.routers3.msg_count.Response_Data::1         2528                      
-system.ruby.network.routers3.msg_count.Response_Control::1         1756                      
-system.ruby.network.routers3.msg_count.Response_Control::2          837                      
-system.ruby.network.routers3.msg_count.Writeback_Data::0          726                      
-system.ruby.network.routers3.msg_count.Writeback_Data::1          501                      
-system.ruby.network.routers3.msg_count.Writeback_Control::0           32                      
-system.ruby.network.routers3.msg_bytes.Control::0        14072                      
-system.ruby.network.routers3.msg_bytes.Request_Control::2         4472                      
-system.ruby.network.routers3.msg_bytes.Response_Data::1       182016                      
-system.ruby.network.routers3.msg_bytes.Response_Control::1        14048                      
-system.ruby.network.routers3.msg_bytes.Response_Control::2         6696                      
-system.ruby.network.routers3.msg_bytes.Writeback_Data::0        52272                      
-system.ruby.network.routers3.msg_bytes.Writeback_Data::1        36072                      
-system.ruby.network.routers3.msg_bytes.Writeback_Control::0          256                      
-system.ruby.network.msg_count.Control            5277                      
-system.ruby.network.msg_count.Request_Control         1677                      
-system.ruby.network.msg_count.Response_Data         7584                      
-system.ruby.network.msg_count.Response_Control         7779                      
-system.ruby.network.msg_count.Writeback_Data         3681                      
-system.ruby.network.msg_count.Writeback_Control           96                      
-system.ruby.network.msg_byte.Control            42216                      
-system.ruby.network.msg_byte.Request_Control        13416                      
-system.ruby.network.msg_byte.Response_Data       546048                      
-system.ruby.network.msg_byte.Response_Control        62232                      
-system.ruby.network.msg_byte.Writeback_Data       265032                      
-system.ruby.network.msg_byte.Writeback_Control          768                      
-system.ruby.network.routers0.throttle0.link_utilization     1.498906                      
-system.ruby.network.routers0.throttle0.msg_count.Request_Control::2          559                      
-system.ruby.network.routers0.throttle0.msg_count.Response_Data::1          894                      
-system.ruby.network.routers0.throttle0.msg_count.Response_Control::1          756                      
-system.ruby.network.routers0.throttle0.msg_bytes.Request_Control::2         4472                      
-system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::1        64368                      
-system.ruby.network.routers0.throttle0.msg_bytes.Response_Control::1         6048                      
-system.ruby.network.routers0.throttle1.link_utilization     2.059815                      
-system.ruby.network.routers0.throttle1.msg_count.Control::0          896                      
-system.ruby.network.routers0.throttle1.msg_count.Response_Control::1           56                      
-system.ruby.network.routers0.throttle1.msg_count.Response_Control::2          837                      
-system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::0          726                      
-system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::1          501                      
-system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::0           32                      
-system.ruby.network.routers0.throttle1.msg_bytes.Control::0         7168                      
-system.ruby.network.routers0.throttle1.msg_bytes.Response_Control::1          448                      
-system.ruby.network.routers0.throttle1.msg_bytes.Response_Control::2         6696                      
-system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::0        52272                      
-system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::1        36072                      
-system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::0          256                      
-system.ruby.network.routers1.throttle0.link_utilization     3.440711                      
-system.ruby.network.routers1.throttle0.msg_count.Control::0          896                      
-system.ruby.network.routers1.throttle0.msg_count.Response_Data::1          863                      
-system.ruby.network.routers1.throttle0.msg_count.Response_Control::1          913                      
-system.ruby.network.routers1.throttle0.msg_count.Response_Control::2          837                      
-system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::0          726                      
-system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::1          501                      
-system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::0           32                      
-system.ruby.network.routers1.throttle0.msg_bytes.Control::0         7168                      
-system.ruby.network.routers1.throttle0.msg_bytes.Response_Data::1        62136                      
-system.ruby.network.routers1.throttle0.msg_bytes.Response_Control::1         7304                      
-system.ruby.network.routers1.throttle0.msg_bytes.Response_Control::2         6696                      
-system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::0        52272                      
-system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::1        36072                      
-system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::0          256                      
-system.ruby.network.routers1.throttle1.link_utilization     2.763554                      
-system.ruby.network.routers1.throttle1.msg_count.Control::0          863                      
-system.ruby.network.routers1.throttle1.msg_count.Request_Control::2          559                      
-system.ruby.network.routers1.throttle1.msg_count.Response_Data::1         1666                      
-system.ruby.network.routers1.throttle1.msg_count.Response_Control::1          843                      
-system.ruby.network.routers1.throttle1.msg_bytes.Control::0         6904                      
-system.ruby.network.routers1.throttle1.msg_bytes.Request_Control::2         4472                      
-system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::1       119952                      
-system.ruby.network.routers1.throttle1.msg_bytes.Response_Control::1         6744                      
-system.ruby.network.routers2.throttle0.link_utilization     1.261765                      
-system.ruby.network.routers2.throttle0.msg_count.Control::0          863                      
-system.ruby.network.routers2.throttle0.msg_count.Response_Data::1          770                      
-system.ruby.network.routers2.throttle0.msg_count.Response_Control::1           87                      
-system.ruby.network.routers2.throttle0.msg_bytes.Control::0         6904                      
-system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::1        55440                      
-system.ruby.network.routers2.throttle0.msg_bytes.Response_Control::1          696                      
-system.ruby.network.routers2.throttle1.link_utilization     1.380896                      
-system.ruby.network.routers2.throttle1.msg_count.Response_Data::1          863                      
-system.ruby.network.routers2.throttle1.msg_count.Response_Control::1          857                      
-system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::1        62136                      
-system.ruby.network.routers2.throttle1.msg_bytes.Response_Control::1         6856                      
-system.ruby.network.routers3.throttle0.link_utilization     1.498906                      
-system.ruby.network.routers3.throttle0.msg_count.Request_Control::2          559                      
-system.ruby.network.routers3.throttle0.msg_count.Response_Data::1          894                      
-system.ruby.network.routers3.throttle0.msg_count.Response_Control::1          756                      
-system.ruby.network.routers3.throttle0.msg_bytes.Request_Control::2         4472                      
-system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::1        64368                      
-system.ruby.network.routers3.throttle0.msg_bytes.Response_Control::1         6048                      
-system.ruby.network.routers3.throttle1.link_utilization     3.440711                      
-system.ruby.network.routers3.throttle1.msg_count.Control::0          896                      
-system.ruby.network.routers3.throttle1.msg_count.Response_Data::1          863                      
-system.ruby.network.routers3.throttle1.msg_count.Response_Control::1          913                      
-system.ruby.network.routers3.throttle1.msg_count.Response_Control::2          837                      
-system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::0          726                      
-system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::1          501                      
-system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::0           32                      
-system.ruby.network.routers3.throttle1.msg_bytes.Control::0         7168                      
-system.ruby.network.routers3.throttle1.msg_bytes.Response_Data::1        62136                      
-system.ruby.network.routers3.throttle1.msg_bytes.Response_Control::1         7304                      
-system.ruby.network.routers3.throttle1.msg_bytes.Response_Control::2         6696                      
-system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::0        52272                      
-system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::1        36072                      
-system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::0          256                      
-system.ruby.network.routers3.throttle2.link_utilization     1.263206                      
-system.ruby.network.routers3.throttle2.msg_count.Control::0          863                      
-system.ruby.network.routers3.throttle2.msg_count.Response_Data::1          771                      
-system.ruby.network.routers3.throttle2.msg_count.Response_Control::1           87                      
-system.ruby.network.routers3.throttle2.msg_bytes.Control::0         6904                      
-system.ruby.network.routers3.throttle2.msg_bytes.Response_Data::1        55512                      
-system.ruby.network.routers3.throttle2.msg_bytes.Response_Control::1          696                      
+system.ruby.dir_cntrl0.memBuffer.memReq          1679                       # Total number of memory requests
+system.ruby.dir_cntrl0.memBuffer.memRead          884                       # Number of memory reads
+system.ruby.dir_cntrl0.memBuffer.memWrite          795                       # Number of memory writes
+system.ruby.dir_cntrl0.memBuffer.memRefresh         2274                       # Number of memory refreshes
+system.ruby.dir_cntrl0.memBuffer.memWaitCycles          511                       # Delay stalled at the head of the bank queue
+system.ruby.dir_cntrl0.memBuffer.memInputQ           43                       # Delay in the input queue
+system.ruby.dir_cntrl0.memBuffer.totalStalls          554                       # Total number of stall cycles
+system.ruby.dir_cntrl0.memBuffer.stallsPerReq     0.329958                       # Expected number of stall cycles per request
+system.ruby.dir_cntrl0.memBuffer.memBankBusy          149                       # memory stalls due to busy bank
+system.ruby.dir_cntrl0.memBuffer.memBusBusy          180                       # memory stalls due to busy bus
+system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy           93                       # memory stalls due to read write turnaround
+system.ruby.dir_cntrl0.memBuffer.memDataBusBusy           60                       # memory stalls due to read read turnaround
+system.ruby.dir_cntrl0.memBuffer.memArbWait           29                       # memory stalls due to arbitration
+system.ruby.dir_cntrl0.memBuffer.memBankCount |          59      3.51%      3.51% |          51      3.04%      6.55% |          42      2.50%      9.05% |         102      6.08%     15.13% |          61      3.63%     18.76% |          47      2.80%     21.56% |          70      4.17%     25.73% |          56      3.34%     29.06% |          51      3.04%     32.10% |          62      3.69%     35.80% |          53      3.16%     38.95% |          35      2.08%     41.04% |          65      3.87%     44.91% |          50      2.98%     47.89% |          40      2.38%     50.27% |          53      3.16%     53.42% |          36      2.14%     55.57% |          55      3.28%     58.84% |          66      3.93%     62.78% |          41      2.44%     65.22% |          49      2.92%     68.14% |          43      2.56%     70.70% |          65      3.87%     74.57% |          53      3.16%     77.72% |          50      2.98%     80.70% |          53      3.16%     83.86% |          51      3.04%     86.90% |          48      2.86%     89.76% |          44      2.62%     92.38% |          41      2.44%     94.82% |          41      2.44%     97.26% |          46      2.74%    100.00% # Number of accesses per bank
+system.ruby.dir_cntrl0.memBuffer.memBankCount::total         1679                       # Number of accesses per bank
+system.ruby.network.routers2.percent_links_utilized     1.294300                      
+system.ruby.network.routers2.msg_count.Control::0          884                      
+system.ruby.network.routers2.msg_count.Response_Data::1         1679                      
+system.ruby.network.routers2.msg_count.Response_Control::1          964                      
+system.ruby.network.routers2.msg_bytes.Control::0         7072                      
+system.ruby.network.routers2.msg_bytes.Response_Data::1       120888                      
+system.ruby.network.routers2.msg_bytes.Response_Control::1         7712                      
+system.ruby.network.routers3.percent_links_utilized     2.028924                      
+system.ruby.network.routers3.msg_count.Control::0         1809                      
+system.ruby.network.routers3.msg_count.Request_Control::2          563                      
+system.ruby.network.routers3.msg_count.Response_Data::1         2604                      
+system.ruby.network.routers3.msg_count.Response_Control::1         1791                      
+system.ruby.network.routers3.msg_count.Response_Control::2          877                      
+system.ruby.network.routers3.msg_count.Writeback_Data::0          742                      
+system.ruby.network.routers3.msg_count.Writeback_Data::1          520                      
+system.ruby.network.routers3.msg_count.Writeback_Control::0           43                      
+system.ruby.network.routers3.msg_bytes.Control::0        14472                      
+system.ruby.network.routers3.msg_bytes.Request_Control::2         4504                      
+system.ruby.network.routers3.msg_bytes.Response_Data::1       187488                      
+system.ruby.network.routers3.msg_bytes.Response_Control::1        14328                      
+system.ruby.network.routers3.msg_bytes.Response_Control::2         7016                      
+system.ruby.network.routers3.msg_bytes.Writeback_Data::0        53424                      
+system.ruby.network.routers3.msg_bytes.Writeback_Data::1        37440                      
+system.ruby.network.routers3.msg_bytes.Writeback_Control::0          344                      
+system.ruby.network.msg_count.Control            5427                      
+system.ruby.network.msg_count.Request_Control         1689                      
+system.ruby.network.msg_count.Response_Data         7812                      
+system.ruby.network.msg_count.Response_Control         8004                      
+system.ruby.network.msg_count.Writeback_Data         3786                      
+system.ruby.network.msg_count.Writeback_Control          129                      
+system.ruby.network.msg_byte.Control            43416                      
+system.ruby.network.msg_byte.Request_Control        13512                      
+system.ruby.network.msg_byte.Response_Data       562464                      
+system.ruby.network.msg_byte.Response_Control        64032                      
+system.ruby.network.msg_byte.Writeback_Data       272592                      
+system.ruby.network.msg_byte.Writeback_Control         1032                      
+system.ruby.network.routers0.throttle0.link_utilization     1.476321                      
+system.ruby.network.routers0.throttle0.msg_count.Request_Control::2          563                      
+system.ruby.network.routers0.throttle0.msg_count.Response_Data::1          925                      
+system.ruby.network.routers0.throttle0.msg_count.Response_Control::1          784                      
+system.ruby.network.routers0.throttle0.msg_bytes.Request_Control::2         4504                      
+system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::1        66600                      
+system.ruby.network.routers0.throttle0.msg_bytes.Response_Control::1         6272                      
+system.ruby.network.routers0.throttle1.link_utilization     2.021852                      
+system.ruby.network.routers0.throttle1.msg_count.Control::0          925                      
+system.ruby.network.routers0.throttle1.msg_count.Response_Control::1           43                      
+system.ruby.network.routers0.throttle1.msg_count.Response_Control::2          877                      
+system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::0          742                      
+system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::1          520                      
+system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::0           43                      
+system.ruby.network.routers0.throttle1.msg_bytes.Control::0         7400                      
+system.ruby.network.routers0.throttle1.msg_bytes.Response_Control::1          344                      
+system.ruby.network.routers0.throttle1.msg_bytes.Response_Control::2         7016                      
+system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::0        53424                      
+system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::1        37440                      
+system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::0          344                      
+system.ruby.network.routers1.throttle0.link_utilization     3.370414                      
+system.ruby.network.routers1.throttle0.msg_count.Control::0          925                      
+system.ruby.network.routers1.throttle0.msg_count.Response_Data::1          884                      
+system.ruby.network.routers1.throttle0.msg_count.Response_Control::1          922                      
+system.ruby.network.routers1.throttle0.msg_count.Response_Control::2          877                      
+system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::0          742                      
+system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::1          520                      
+system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::0           43                      
+system.ruby.network.routers1.throttle0.msg_bytes.Control::0         7400                      
+system.ruby.network.routers1.throttle0.msg_bytes.Response_Data::1        63648                      
+system.ruby.network.routers1.throttle0.msg_bytes.Response_Control::1         7376                      
+system.ruby.network.routers1.throttle0.msg_bytes.Response_Control::2         7016                      
+system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::0        53424                      
+system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::1        37440                      
+system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::0          344                      
+system.ruby.network.routers1.throttle1.link_utilization     2.716358                      
+system.ruby.network.routers1.throttle1.msg_count.Control::0          884                      
+system.ruby.network.routers1.throttle1.msg_count.Request_Control::2          563                      
+system.ruby.network.routers1.throttle1.msg_count.Response_Data::1         1720                      
+system.ruby.network.routers1.throttle1.msg_count.Response_Control::1          869                      
+system.ruby.network.routers1.throttle1.msg_bytes.Control::0         7072                      
+system.ruby.network.routers1.throttle1.msg_bytes.Request_Control::2         4504                      
+system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::1       123840                      
+system.ruby.network.routers1.throttle1.msg_bytes.Response_Control::1         6952                      
+system.ruby.network.routers2.throttle0.link_utilization     1.240037                      
+system.ruby.network.routers2.throttle0.msg_count.Control::0          884                      
+system.ruby.network.routers2.throttle0.msg_count.Response_Data::1          795                      
+system.ruby.network.routers2.throttle0.msg_count.Response_Control::1           85                      
+system.ruby.network.routers2.throttle0.msg_bytes.Control::0         7072                      
+system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::1        57240                      
+system.ruby.network.routers2.throttle0.msg_bytes.Response_Control::1          680                      
+system.ruby.network.routers2.throttle1.link_utilization     1.348563                      
+system.ruby.network.routers2.throttle1.msg_count.Response_Data::1          884                      
+system.ruby.network.routers2.throttle1.msg_count.Response_Control::1          879                      
+system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::1        63648                      
+system.ruby.network.routers2.throttle1.msg_bytes.Response_Control::1         7032                      
+system.ruby.network.routers3.throttle0.link_utilization     1.476321                      
+system.ruby.network.routers3.throttle0.msg_count.Request_Control::2          563                      
+system.ruby.network.routers3.throttle0.msg_count.Response_Data::1          925                      
+system.ruby.network.routers3.throttle0.msg_count.Response_Control::1          784                      
+system.ruby.network.routers3.throttle0.msg_bytes.Request_Control::2         4504                      
+system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::1        66600                      
+system.ruby.network.routers3.throttle0.msg_bytes.Response_Control::1         6272                      
+system.ruby.network.routers3.throttle1.link_utilization     3.370414                      
+system.ruby.network.routers3.throttle1.msg_count.Control::0          925                      
+system.ruby.network.routers3.throttle1.msg_count.Response_Data::1          884                      
+system.ruby.network.routers3.throttle1.msg_count.Response_Control::1          922                      
+system.ruby.network.routers3.throttle1.msg_count.Response_Control::2          877                      
+system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::0          742                      
+system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::1          520                      
+system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::0           43                      
+system.ruby.network.routers3.throttle1.msg_bytes.Control::0         7400                      
+system.ruby.network.routers3.throttle1.msg_bytes.Response_Data::1        63648                      
+system.ruby.network.routers3.throttle1.msg_bytes.Response_Control::1         7376                      
+system.ruby.network.routers3.throttle1.msg_bytes.Response_Control::2         7016                      
+system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::0        53424                      
+system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::1        37440                      
+system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::0          344                      
+system.ruby.network.routers3.throttle2.link_utilization     1.240037                      
+system.ruby.network.routers3.throttle2.msg_count.Control::0          884                      
+system.ruby.network.routers3.throttle2.msg_count.Response_Data::1          795                      
+system.ruby.network.routers3.throttle2.msg_count.Response_Control::1           85                      
+system.ruby.network.routers3.throttle2.msg_bytes.Control::0         7072                      
+system.ruby.network.routers3.throttle2.msg_bytes.Response_Data::1        57240                      
+system.ruby.network.routers3.throttle2.msg_bytes.Response_Control::1          680                      
 system.ruby.delayVCHist.vnet_0::bucket_size          512                       # delay histogram for vnet_0
 system.ruby.delayVCHist.vnet_0::max_bucket         5119                       # delay histogram for vnet_0
-system.ruby.delayVCHist.vnet_0::samples          2489                       # delay histogram for vnet_0
-system.ruby.delayVCHist.vnet_0::mean       159.486139                       # delay histogram for vnet_0
-system.ruby.delayVCHist.vnet_0::stdev      413.379625                       # delay histogram for vnet_0
-system.ruby.delayVCHist.vnet_0           |        2201     88.43%     88.43% |         165      6.63%     95.06% |          67      2.69%     97.75% |          29      1.17%     98.92% |          15      0.60%     99.52% |           8      0.32%     99.84% |           4      0.16%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for vnet_0
-system.ruby.delayVCHist.vnet_0::total            2489                       # delay histogram for vnet_0
+system.ruby.delayVCHist.vnet_0::samples          2586                       # delay histogram for vnet_0
+system.ruby.delayVCHist.vnet_0::mean       153.589327                       # delay histogram for vnet_0
+system.ruby.delayVCHist.vnet_0::stdev      402.594576                       # delay histogram for vnet_0
+system.ruby.delayVCHist.vnet_0           |        2311     89.37%     89.37% |         159      6.15%     95.51% |          57      2.20%     97.72% |          31      1.20%     98.92% |          18      0.70%     99.61% |           9      0.35%     99.96% |           0      0.00%     99.96% |           0      0.00%     99.96% |           1      0.04%    100.00% |           0      0.00%    100.00% # delay histogram for vnet_0
+system.ruby.delayVCHist.vnet_0::total            2586                       # delay histogram for vnet_0
 system.ruby.delayVCHist.vnet_1::bucket_size            4                       # delay histogram for vnet_1
 system.ruby.delayVCHist.vnet_1::max_bucket           39                       # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::samples          3927                       # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::mean         0.706901                       # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::stdev        2.143932                       # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1           |        3546     90.30%     90.30% |         268      6.82%     97.12% |          81      2.06%     99.19% |          28      0.71%     99.90% |           1      0.03%     99.92% |           3      0.08%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::total            3927                       # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1::samples          4034                       # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1::mean         0.709470                       # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1::stdev        2.104009                       # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1           |        3622     89.79%     89.79% |         315      7.81%     97.60% |          68      1.69%     99.28% |          23      0.57%     99.85% |           5      0.12%     99.98% |           0      0.00%     99.98% |           1      0.02%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1::total            4034                       # delay histogram for vnet_1
 system.ruby.delayVCHist.vnet_2::bucket_size            1                       # delay histogram for vnet_2
 system.ruby.delayVCHist.vnet_2::max_bucket            9                       # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::samples           559                       # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::mean         0.003578                       # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::stdev        0.084591                       # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2           |         558     99.82%     99.82% |           0      0.00%     99.82% |           1      0.18%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::total             559                       # delay histogram for vnet_2
+system.ruby.delayVCHist.vnet_2::samples           563                       # delay histogram for vnet_2
+system.ruby.delayVCHist.vnet_2::mean         0.003552                       # delay histogram for vnet_2
+system.ruby.delayVCHist.vnet_2::stdev        0.084290                       # delay histogram for vnet_2
+system.ruby.delayVCHist.vnet_2           |         562     99.82%     99.82% |           0      0.00%     99.82% |           1      0.18%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for vnet_2
+system.ruby.delayVCHist.vnet_2::total             563                       # delay histogram for vnet_2
 system.ruby.LD.latency_hist::bucket_size         1024                      
 system.ruby.LD.latency_hist::max_bucket         10239                      
-system.ruby.LD.latency_hist::samples               43                      
-system.ruby.LD.latency_hist::mean         5169.837209                      
-system.ruby.LD.latency_hist::gmean        2077.331542                      
-system.ruby.LD.latency_hist::stdev        2197.240205                      
-system.ruby.LD.latency_hist              |           6     13.95%     13.95% |           0      0.00%     13.95% |           0      0.00%     13.95% |           0      0.00%     13.95% |           2      4.65%     18.60% |          22     51.16%     69.77% |          10     23.26%     93.02% |           3      6.98%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.LD.latency_hist::total                 43                      
-system.ruby.LD.hit_latency_hist::bucket_size            1                      
-system.ruby.LD.hit_latency_hist::max_bucket            9                      
-system.ruby.LD.hit_latency_hist::samples            6                      
-system.ruby.LD.hit_latency_hist::mean        3.166667                      
-system.ruby.LD.hit_latency_hist::gmean       3.086164                      
-system.ruby.LD.hit_latency_hist::stdev       0.752773                      
-system.ruby.LD.hit_latency_hist          |           0      0.00%      0.00% |           0      0.00%      0.00% |           1     16.67%     16.67% |           3     50.00%     66.67% |           2     33.33%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.LD.hit_latency_hist::total              6                      
+system.ruby.LD.latency_hist::samples               54                      
+system.ruby.LD.latency_hist::mean         5695.537037                      
+system.ruby.LD.latency_hist::gmean        3661.591532                      
+system.ruby.LD.latency_hist::stdev        1733.262348                      
+system.ruby.LD.latency_hist              |           4      7.41%      7.41% |           0      0.00%      7.41% |           0      0.00%      7.41% |           0      0.00%      7.41% |           3      5.56%     12.96% |          19     35.19%     48.15% |          24     44.44%     92.59% |           4      7.41%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.latency_hist::total                 54                      
+system.ruby.LD.hit_latency_hist::bucket_size           16                      
+system.ruby.LD.hit_latency_hist::max_bucket          159                      
+system.ruby.LD.hit_latency_hist::samples            4                      
+system.ruby.LD.hit_latency_hist::mean       29.500000                      
+system.ruby.LD.hit_latency_hist::gmean       6.027587                      
+system.ruby.LD.hit_latency_hist::stdev      53.681157                      
+system.ruby.LD.hit_latency_hist          |           3     75.00%     75.00% |           0      0.00%     75.00% |           0      0.00%     75.00% |           0      0.00%     75.00% |           0      0.00%     75.00% |           0      0.00%     75.00% |           1     25.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.hit_latency_hist::total              4                      
 system.ruby.LD.miss_latency_hist::bucket_size         1024                      
 system.ruby.LD.miss_latency_hist::max_bucket        10239                      
-system.ruby.LD.miss_latency_hist::samples           37                      
-system.ruby.LD.miss_latency_hist::mean    6007.675676                      
-system.ruby.LD.miss_latency_hist::gmean   5971.927068                      
-system.ruby.LD.miss_latency_hist::stdev    679.672881                      
-system.ruby.LD.miss_latency_hist         |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           2      5.41%      5.41% |          22     59.46%     64.86% |          10     27.03%     91.89% |           3      8.11%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.LD.miss_latency_hist::total            37                      
+system.ruby.LD.miss_latency_hist::samples           50                      
+system.ruby.LD.miss_latency_hist::mean    6148.820000                      
+system.ruby.LD.miss_latency_hist::gmean   6114.374114                      
+system.ruby.LD.miss_latency_hist::stdev    647.202668                      
+system.ruby.LD.miss_latency_hist         |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           3      6.00%      6.00% |          19     38.00%     44.00% |          24     48.00%     92.00% |           4      8.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.miss_latency_hist::total            50                      
 system.ruby.ST.latency_hist::bucket_size         1024                      
 system.ruby.ST.latency_hist::max_bucket         10239                      
-system.ruby.ST.latency_hist::samples              868                      
-system.ruby.ST.latency_hist::mean         5376.413594                      
-system.ruby.ST.latency_hist::gmean        3136.848535                      
-system.ruby.ST.latency_hist::stdev        1827.946779                      
-system.ruby.ST.latency_hist              |          82      9.45%      9.45% |           2      0.23%      9.68% |           2      0.23%      9.91% |           4      0.46%     10.37% |          55      6.34%     16.71% |         446     51.38%     68.09% |         253     29.15%     97.24% |          24      2.76%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.ST.latency_hist::total                868                      
+system.ruby.ST.latency_hist::samples              902                      
+system.ruby.ST.latency_hist::mean         5364.286031                      
+system.ruby.ST.latency_hist::gmean        2990.478756                      
+system.ruby.ST.latency_hist::stdev        1912.037218                      
+system.ruby.ST.latency_hist              |          94     10.42%     10.42% |           4      0.44%     10.86% |           3      0.33%     11.20% |           4      0.44%     11.64% |          27      2.99%     14.63% |         441     48.89%     63.53% |         296     32.82%     96.34% |          33      3.66%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.latency_hist::total                902                      
 system.ruby.ST.hit_latency_hist::bucket_size           16                      
 system.ruby.ST.hit_latency_hist::max_bucket          159                      
-system.ruby.ST.hit_latency_hist::samples           68                      
-system.ruby.ST.hit_latency_hist::mean       12.264706                      
-system.ruby.ST.hit_latency_hist::gmean       3.346538                      
-system.ruby.ST.hit_latency_hist::stdev      31.130739                      
-system.ruby.ST.hit_latency_hist          |          62     91.18%     91.18% |           0      0.00%     91.18% |           0      0.00%     91.18% |           0      0.00%     91.18% |           0      0.00%     91.18% |           0      0.00%     91.18% |           2      2.94%     94.12% |           4      5.88%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.ST.hit_latency_hist::total             68                      
+system.ruby.ST.hit_latency_hist::samples           73                      
+system.ruby.ST.hit_latency_hist::mean        8.506849                      
+system.ruby.ST.hit_latency_hist::gmean       2.645743                      
+system.ruby.ST.hit_latency_hist::stdev      25.369559                      
+system.ruby.ST.hit_latency_hist          |          69     94.52%     94.52% |           0      0.00%     94.52% |           0      0.00%     94.52% |           0      0.00%     94.52% |           0      0.00%     94.52% |           0      0.00%     94.52% |           1      1.37%     95.89% |           3      4.11%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.hit_latency_hist::total             73                      
 system.ruby.ST.miss_latency_hist::bucket_size         1024                      
 system.ruby.ST.miss_latency_hist::max_bucket        10239                      
-system.ruby.ST.miss_latency_hist::samples          800                      
-system.ruby.ST.miss_latency_hist::mean    5832.366250                      
-system.ruby.ST.miss_latency_hist::gmean   5611.834584                      
-system.ruby.ST.miss_latency_hist::stdev    984.210196                      
-system.ruby.ST.miss_latency_hist         |          14      1.75%      1.75% |           2      0.25%      2.00% |           2      0.25%      2.25% |           4      0.50%      2.75% |          55      6.88%      9.62% |         446     55.75%     65.38% |         253     31.62%     97.00% |          24      3.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.ST.miss_latency_hist::total           800                      
+system.ruby.ST.miss_latency_hist::samples          829                      
+system.ruby.ST.miss_latency_hist::mean    5835.904704                      
+system.ruby.ST.miss_latency_hist::gmean   5553.905612                      
+system.ruby.ST.miss_latency_hist::stdev   1107.483624                      
+system.ruby.ST.miss_latency_hist         |          21      2.53%      2.53% |           4      0.48%      3.02% |           3      0.36%      3.38% |           4      0.48%      3.86% |          27      3.26%      7.12% |         441     53.20%     60.31% |         296     35.71%     96.02% |          33      3.98%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.miss_latency_hist::total           829                      
 system.ruby.IFETCH.latency_hist::bucket_size          256                      
 system.ruby.IFETCH.latency_hist::max_bucket         2559                      
-system.ruby.IFETCH.latency_hist::samples           57                      
-system.ruby.IFETCH.latency_hist::mean      855.263158                      
-system.ruby.IFETCH.latency_hist::gmean     754.746405                      
-system.ruby.IFETCH.latency_hist::stdev     394.368008                      
-system.ruby.IFETCH.latency_hist          |           3      5.26%      5.26% |           8     14.04%     19.30% |          15     26.32%     45.61% |          11     19.30%     64.91% |          12     21.05%     85.96% |           6     10.53%     96.49% |           1      1.75%     98.25% |           1      1.75%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.IFETCH.latency_hist::total             57                      
+system.ruby.IFETCH.latency_hist::samples           46                      
+system.ruby.IFETCH.latency_hist::mean      772.847826                      
+system.ruby.IFETCH.latency_hist::gmean     703.281758                      
+system.ruby.IFETCH.latency_hist::stdev     370.399662                      
+system.ruby.IFETCH.latency_hist          |           0      0.00%      0.00% |          10     21.74%     21.74% |          20     43.48%     65.22% |           7     15.22%     80.43% |           3      6.52%     86.96% |           4      8.70%     95.65% |           1      2.17%     97.83% |           0      0.00%     97.83% |           1      2.17%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.latency_hist::total             46                      
 system.ruby.IFETCH.miss_latency_hist::bucket_size          256                      
 system.ruby.IFETCH.miss_latency_hist::max_bucket         2559                      
-system.ruby.IFETCH.miss_latency_hist::samples           57                      
-system.ruby.IFETCH.miss_latency_hist::mean   855.263158                      
-system.ruby.IFETCH.miss_latency_hist::gmean   754.746405                      
-system.ruby.IFETCH.miss_latency_hist::stdev   394.368008                      
-system.ruby.IFETCH.miss_latency_hist     |           3      5.26%      5.26% |           8     14.04%     19.30% |          15     26.32%     45.61% |          11     19.30%     64.91% |          12     21.05%     85.96% |           6     10.53%     96.49% |           1      1.75%     98.25% |           1      1.75%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.IFETCH.miss_latency_hist::total           57                      
-system.ruby.L1Cache_Controller.Load                43      0.00%      0.00%
-system.ruby.L1Cache_Controller.Ifetch              63      0.00%      0.00%
-system.ruby.L1Cache_Controller.Store              870      0.00%      0.00%
-system.ruby.L1Cache_Controller.Inv                559      0.00%      0.00%
-system.ruby.L1Cache_Controller.L1_Replacement         9999      0.00%      0.00%
-system.ruby.L1Cache_Controller.Data_Exclusive           37      0.00%      0.00%
-system.ruby.L1Cache_Controller.Data_all_Acks          857      0.00%      0.00%
-system.ruby.L1Cache_Controller.WB_Ack             756      0.00%      0.00%
-system.ruby.L1Cache_Controller.NP.Load             37      0.00%      0.00%
-system.ruby.L1Cache_Controller.NP.Ifetch           57      0.00%      0.00%
-system.ruby.L1Cache_Controller.NP.Store           802      0.00%      0.00%
-system.ruby.L1Cache_Controller.NP.Inv               1      0.00%      0.00%
-system.ruby.L1Cache_Controller.I.L1_Replacement          127      0.00%      0.00%
-system.ruby.L1Cache_Controller.S.Inv               35      0.00%      0.00%
-system.ruby.L1Cache_Controller.S.L1_Replacement            6      0.00%      0.00%
+system.ruby.IFETCH.miss_latency_hist::samples           46                      
+system.ruby.IFETCH.miss_latency_hist::mean   772.847826                      
+system.ruby.IFETCH.miss_latency_hist::gmean   703.281758                      
+system.ruby.IFETCH.miss_latency_hist::stdev   370.399662                      
+system.ruby.IFETCH.miss_latency_hist     |           0      0.00%      0.00% |          10     21.74%     21.74% |          20     43.48%     65.22% |           7     15.22%     80.43% |           3      6.52%     86.96% |           4      8.70%     95.65% |           1      2.17%     97.83% |           0      0.00%     97.83% |           1      2.17%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.miss_latency_hist::total           46                      
+system.ruby.L1Cache_Controller.Load                54      0.00%      0.00%
+system.ruby.L1Cache_Controller.Ifetch              54      0.00%      0.00%
+system.ruby.L1Cache_Controller.Store              904      0.00%      0.00%
+system.ruby.L1Cache_Controller.Inv                563      0.00%      0.00%
+system.ruby.L1Cache_Controller.L1_Replacement        10554      0.00%      0.00%
+system.ruby.L1Cache_Controller.Data_Exclusive           50      0.00%      0.00%
+system.ruby.L1Cache_Controller.Data_all_Acks          875      0.00%      0.00%
+system.ruby.L1Cache_Controller.WB_Ack             784      0.00%      0.00%
+system.ruby.L1Cache_Controller.NP.Load             50      0.00%      0.00%
+system.ruby.L1Cache_Controller.NP.Ifetch           46      0.00%      0.00%
+system.ruby.L1Cache_Controller.NP.Store           831      0.00%      0.00%
+system.ruby.L1Cache_Controller.NP.Inv               2      0.00%      0.00%
+system.ruby.L1Cache_Controller.I.L1_Replacement          125      0.00%      0.00%
+system.ruby.L1Cache_Controller.S.Inv               28      0.00%      0.00%
+system.ruby.L1Cache_Controller.S.L1_Replacement           10      0.00%      0.00%
+system.ruby.L1Cache_Controller.E.Store              1      0.00%      0.00%
 system.ruby.L1Cache_Controller.E.Inv                5      0.00%      0.00%
-system.ruby.L1Cache_Controller.E.L1_Replacement           32      0.00%      0.00%
-system.ruby.L1Cache_Controller.M.Load               6      0.00%      0.00%
-system.ruby.L1Cache_Controller.M.Store             68      0.00%      0.00%
-system.ruby.L1Cache_Controller.M.Inv               73      0.00%      0.00%
-system.ruby.L1Cache_Controller.M.L1_Replacement          726      0.00%      0.00%
-system.ruby.L1Cache_Controller.IS.Inv              16      0.00%      0.00%
-system.ruby.L1Cache_Controller.IS.L1_Replacement          433      0.00%      0.00%
-system.ruby.L1Cache_Controller.IS.Data_Exclusive           37      0.00%      0.00%
-system.ruby.L1Cache_Controller.IS.Data_all_Acks           41      0.00%      0.00%
-system.ruby.L1Cache_Controller.IM.L1_Replacement         8675      0.00%      0.00%
-system.ruby.L1Cache_Controller.IM.Data_all_Acks          800      0.00%      0.00%
-system.ruby.L1Cache_Controller.IS_I.Data_all_Acks           16      0.00%      0.00%
-system.ruby.L1Cache_Controller.M_I.Ifetch            6      0.00%      0.00%
-system.ruby.L1Cache_Controller.M_I.Inv            429      0.00%      0.00%
-system.ruby.L1Cache_Controller.M_I.WB_Ack          329      0.00%      0.00%
-system.ruby.L1Cache_Controller.SINK_WB_ACK.WB_Ack          427      0.00%      0.00%
-system.ruby.L2Cache_Controller.L1_GET_INSTR           57      0.00%      0.00%
-system.ruby.L2Cache_Controller.L1_GETS             37      0.00%      0.00%
-system.ruby.L2Cache_Controller.L1_GETX            802      0.00%      0.00%
-system.ruby.L2Cache_Controller.L1_PUTX            335      0.00%      0.00%
-system.ruby.L2Cache_Controller.L1_PUTX_old          787      0.00%      0.00%
-system.ruby.L2Cache_Controller.L2_Replacement          283      0.00%      0.00%
-system.ruby.L2Cache_Controller.L2_Replacement_clean         1213      0.00%      0.00%
-system.ruby.L2Cache_Controller.Mem_Data           863      0.00%      0.00%
-system.ruby.L2Cache_Controller.Mem_Ack            857      0.00%      0.00%
-system.ruby.L2Cache_Controller.WB_Data            488      0.00%      0.00%
-system.ruby.L2Cache_Controller.WB_Data_clean           13      0.00%      0.00%
-system.ruby.L2Cache_Controller.Ack_all             56      0.00%      0.00%
-system.ruby.L2Cache_Controller.Exclusive_Unblock          837      0.00%      0.00%
-system.ruby.L2Cache_Controller.NP.L1_GET_INSTR           52      0.00%      0.00%
-system.ruby.L2Cache_Controller.NP.L1_GETS           36      0.00%      0.00%
-system.ruby.L2Cache_Controller.NP.L1_GETX          776      0.00%      0.00%
-system.ruby.L2Cache_Controller.NP.L1_PUTX_old          321      0.00%      0.00%
-system.ruby.L2Cache_Controller.SS.L1_GETX            5      0.00%      0.00%
-system.ruby.L2Cache_Controller.SS.L2_Replacement_clean           52      0.00%      0.00%
-system.ruby.L2Cache_Controller.M.L1_GET_INSTR            5      0.00%      0.00%
+system.ruby.L1Cache_Controller.E.L1_Replacement           44      0.00%      0.00%
+system.ruby.L1Cache_Controller.M.Load               4      0.00%      0.00%
+system.ruby.L1Cache_Controller.M.Store             72      0.00%      0.00%
+system.ruby.L1Cache_Controller.M.Inv               86      0.00%      0.00%
+system.ruby.L1Cache_Controller.M.L1_Replacement          743      0.00%      0.00%
+system.ruby.L1Cache_Controller.IS.Inv               8      0.00%      0.00%
+system.ruby.L1Cache_Controller.IS.L1_Replacement          519      0.00%      0.00%
+system.ruby.L1Cache_Controller.IS.Data_Exclusive           50      0.00%      0.00%
+system.ruby.L1Cache_Controller.IS.Data_all_Acks           38      0.00%      0.00%
+system.ruby.L1Cache_Controller.IM.L1_Replacement         9113      0.00%      0.00%
+system.ruby.L1Cache_Controller.IM.Data_all_Acks          829      0.00%      0.00%
+system.ruby.L1Cache_Controller.IS_I.Data_all_Acks            8      0.00%      0.00%
+system.ruby.L1Cache_Controller.M_I.Ifetch            8      0.00%      0.00%
+system.ruby.L1Cache_Controller.M_I.Inv            434      0.00%      0.00%
+system.ruby.L1Cache_Controller.M_I.WB_Ack          351      0.00%      0.00%
+system.ruby.L1Cache_Controller.SINK_WB_ACK.WB_Ack          433      0.00%      0.00%
+system.ruby.L2Cache_Controller.L1_GET_INSTR           47      0.00%      0.00%
+system.ruby.L2Cache_Controller.L1_GETS             50      0.00%      0.00%
+system.ruby.L2Cache_Controller.L1_GETX            829      0.00%      0.00%
+system.ruby.L2Cache_Controller.L1_PUTX            358      0.00%      0.00%
+system.ruby.L2Cache_Controller.L1_PUTX_old          826      0.00%      0.00%
+system.ruby.L2Cache_Controller.L2_Replacement          302      0.00%      0.00%
+system.ruby.L2Cache_Controller.L2_Replacement_clean         1188      0.00%      0.00%
+system.ruby.L2Cache_Controller.Mem_Data           884      0.00%      0.00%
+system.ruby.L2Cache_Controller.Mem_Ack            878      0.00%      0.00%
+system.ruby.L2Cache_Controller.WB_Data            493      0.00%      0.00%
+system.ruby.L2Cache_Controller.WB_Data_clean           27      0.00%      0.00%
+system.ruby.L2Cache_Controller.Ack_all             43      0.00%      0.00%
+system.ruby.L2Cache_Controller.Exclusive_Unblock          877      0.00%      0.00%
+system.ruby.L2Cache_Controller.NP.L1_GET_INSTR           38      0.00%      0.00%
+system.ruby.L2Cache_Controller.NP.L1_GETS           49      0.00%      0.00%
+system.ruby.L2Cache_Controller.NP.L1_GETX          797      0.00%      0.00%
+system.ruby.L2Cache_Controller.NP.L1_PUTX_old          309      0.00%      0.00%
+system.ruby.L2Cache_Controller.SS.L1_GETX            8      0.00%      0.00%
+system.ruby.L2Cache_Controller.SS.L2_Replacement_clean           38      0.00%      0.00%
+system.ruby.L2Cache_Controller.M.L1_GET_INSTR            8      0.00%      0.00%
 system.ruby.L2Cache_Controller.M.L1_GETS            1      0.00%      0.00%
-system.ruby.L2Cache_Controller.M.L1_GETX           21      0.00%      0.00%
-system.ruby.L2Cache_Controller.M.L2_Replacement          283      0.00%      0.00%
-system.ruby.L2Cache_Controller.M.L2_Replacement_clean           18      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT.L1_PUTX          329      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT.L2_Replacement_clean          507      0.00%      0.00%
-system.ruby.L2Cache_Controller.M_I.L1_PUTX_old          106      0.00%      0.00%
-system.ruby.L2Cache_Controller.M_I.Mem_Ack          857      0.00%      0.00%
-system.ruby.L2Cache_Controller.MCT_I.L1_PUTX_old          206      0.00%      0.00%
-system.ruby.L2Cache_Controller.MCT_I.WB_Data          488      0.00%      0.00%
-system.ruby.L2Cache_Controller.MCT_I.WB_Data_clean           13      0.00%      0.00%
+system.ruby.L2Cache_Controller.M.L1_GETX           24      0.00%      0.00%
+system.ruby.L2Cache_Controller.M.L2_Replacement          302      0.00%      0.00%
+system.ruby.L2Cache_Controller.M.L2_Replacement_clean           15      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT.L1_PUTX          351      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT.L2_Replacement_clean          525      0.00%      0.00%
+system.ruby.L2Cache_Controller.M_I.L1_GET_INSTR            1      0.00%      0.00%
+system.ruby.L2Cache_Controller.M_I.L1_PUTX_old          124      0.00%      0.00%
+system.ruby.L2Cache_Controller.M_I.Mem_Ack          878      0.00%      0.00%
+system.ruby.L2Cache_Controller.MCT_I.L1_PUTX_old          215      0.00%      0.00%
+system.ruby.L2Cache_Controller.MCT_I.WB_Data          493      0.00%      0.00%
+system.ruby.L2Cache_Controller.MCT_I.WB_Data_clean           27      0.00%      0.00%
 system.ruby.L2Cache_Controller.MCT_I.Ack_all            5      0.00%      0.00%
-system.ruby.L2Cache_Controller.I_I.Ack_all           51      0.00%      0.00%
-system.ruby.L2Cache_Controller.ISS.L2_Replacement_clean           12      0.00%      0.00%
-system.ruby.L2Cache_Controller.ISS.Mem_Data           36      0.00%      0.00%
-system.ruby.L2Cache_Controller.IS.L2_Replacement_clean           51      0.00%      0.00%
-system.ruby.L2Cache_Controller.IS.Mem_Data           52      0.00%      0.00%
-system.ruby.L2Cache_Controller.IM.L2_Replacement_clean          231      0.00%      0.00%
-system.ruby.L2Cache_Controller.IM.Mem_Data          775      0.00%      0.00%
-system.ruby.L2Cache_Controller.SS_MB.Exclusive_Unblock            5      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT_MB.L1_PUTX            6      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT_MB.L1_PUTX_old          154      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT_MB.L2_Replacement_clean          342      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT_MB.Exclusive_Unblock          832      0.00%      0.00%
-system.ruby.Directory_Controller.Fetch            863      0.00%      0.00%
-system.ruby.Directory_Controller.Data             770      0.00%      0.00%
-system.ruby.Directory_Controller.Memory_Data          863      0.00%      0.00%
-system.ruby.Directory_Controller.Memory_Ack          770      0.00%      0.00%
-system.ruby.Directory_Controller.CleanReplacement           87      0.00%      0.00%
-system.ruby.Directory_Controller.I.Fetch          863      0.00%      0.00%
-system.ruby.Directory_Controller.M.Data           770      0.00%      0.00%
-system.ruby.Directory_Controller.M.CleanReplacement           87      0.00%      0.00%
-system.ruby.Directory_Controller.IM.Memory_Data          863      0.00%      0.00%
-system.ruby.Directory_Controller.MI.Memory_Ack          770      0.00%      0.00%
+system.ruby.L2Cache_Controller.I_I.Ack_all           38      0.00%      0.00%
+system.ruby.L2Cache_Controller.ISS.L2_Replacement_clean           16      0.00%      0.00%
+system.ruby.L2Cache_Controller.ISS.Mem_Data           49      0.00%      0.00%
+system.ruby.L2Cache_Controller.IS.L2_Replacement_clean           19      0.00%      0.00%
+system.ruby.L2Cache_Controller.IS.Mem_Data           38      0.00%      0.00%
+system.ruby.L2Cache_Controller.IM.L2_Replacement_clean          224      0.00%      0.00%
+system.ruby.L2Cache_Controller.IM.Mem_Data          797      0.00%      0.00%
+system.ruby.L2Cache_Controller.SS_MB.Exclusive_Unblock            8      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT_MB.L1_PUTX            7      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT_MB.L1_PUTX_old          178      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT_MB.L2_Replacement_clean          351      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT_MB.Exclusive_Unblock          869      0.00%      0.00%
+system.ruby.Directory_Controller.Fetch            884      0.00%      0.00%
+system.ruby.Directory_Controller.Data             795      0.00%      0.00%
+system.ruby.Directory_Controller.Memory_Data          884      0.00%      0.00%
+system.ruby.Directory_Controller.Memory_Ack          795      0.00%      0.00%
+system.ruby.Directory_Controller.CleanReplacement           85      0.00%      0.00%
+system.ruby.Directory_Controller.I.Fetch          884      0.00%      0.00%
+system.ruby.Directory_Controller.M.Data           795      0.00%      0.00%
+system.ruby.Directory_Controller.M.CleanReplacement           85      0.00%      0.00%
+system.ruby.Directory_Controller.IM.Memory_Data          884      0.00%      0.00%
+system.ruby.Directory_Controller.MI.Memory_Ack          795      0.00%      0.00%
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt
index aefa03a40..26ba1fbd4 100644
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt
@@ -1,391 +1,404 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000327                       # Number of seconds simulated
-sim_ticks                                      327361                       # Number of ticks simulated
-final_tick                                     327361                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.000338                       # Number of seconds simulated
+sim_ticks                                      338071                       # Number of ticks simulated
+final_tick                                     338071                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_tick_rate                                 771883                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 124808                       # Number of bytes of host memory used
-host_seconds                                     0.42                       # Real time elapsed on the host
+host_tick_rate                                 719839                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 158348                       # Number of bytes of host memory used
+host_seconds                                     0.47                       # Real time elapsed on the host
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                             1                       # Clock period in ticks
 system.ruby.clk_domain.clock                        1                       # Clock period in ticks
 system.ruby.outstanding_req_hist::bucket_size            2                      
 system.ruby.outstanding_req_hist::max_bucket           19                      
-system.ruby.outstanding_req_hist::samples         1000                      
-system.ruby.outstanding_req_hist::mean      15.813000                      
-system.ruby.outstanding_req_hist::gmean     15.714362                      
-system.ruby.outstanding_req_hist::stdev      1.128408                      
-system.ruby.outstanding_req_hist         |           1      0.10%      0.10% |           2      0.20%      0.30% |           2      0.20%      0.50% |           2      0.20%      0.70% |           2      0.20%      0.90% |           2      0.20%      1.10% |           2      0.20%      1.30% |          69      6.90%      8.20% |         918     91.80%    100.00% |           0      0.00%    100.00%
-system.ruby.outstanding_req_hist::total          1000                      
+system.ruby.outstanding_req_hist::samples          987                      
+system.ruby.outstanding_req_hist::mean      15.827761                      
+system.ruby.outstanding_req_hist::gmean     15.728108                      
+system.ruby.outstanding_req_hist::stdev      1.130761                      
+system.ruby.outstanding_req_hist         |           1      0.10%      0.10% |           2      0.20%      0.30% |           2      0.20%      0.51% |           2      0.20%      0.71% |           2      0.20%      0.91% |           2      0.20%      1.11% |           2      0.20%      1.32% |          52      5.27%      6.59% |         922     93.41%    100.00% |           0      0.00%    100.00%
+system.ruby.outstanding_req_hist::total           987                      
 system.ruby.latency_hist::bucket_size            4096                      
 system.ruby.latency_hist::max_bucket            40959                      
-system.ruby.latency_hist::samples                 985                      
-system.ruby.latency_hist::mean            5192.155330                      
-system.ruby.latency_hist::gmean           1411.192372                      
-system.ruby.latency_hist::stdev           6963.102626                      
-system.ruby.latency_hist                 |         695     70.56%     70.56% |          43      4.37%     74.92% |          33      3.35%     78.27% |          91      9.24%     87.51% |          85      8.63%     96.14% |          28      2.84%     98.98% |           9      0.91%     99.90% |           1      0.10%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.latency_hist::total                   985                      
+system.ruby.latency_hist::samples                 972                      
+system.ruby.latency_hist::mean            5437.663580                      
+system.ruby.latency_hist::gmean           1650.672742                      
+system.ruby.latency_hist::stdev           7600.061844                      
+system.ruby.latency_hist                 |         700     72.02%     72.02% |          56      5.76%     77.78% |          10      1.03%     78.81% |          35      3.60%     82.41% |          92      9.47%     91.87% |          63      6.48%     98.35% |          14      1.44%     99.79% |           2      0.21%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.latency_hist::total                   972                      
 system.ruby.hit_latency_hist::bucket_size           16                      
 system.ruby.hit_latency_hist::max_bucket          159                      
-system.ruby.hit_latency_hist::samples              78                      
-system.ruby.hit_latency_hist::mean           9.089744                      
-system.ruby.hit_latency_hist::gmean          2.589753                      
-system.ruby.hit_latency_hist::stdev         26.203591                      
-system.ruby.hit_latency_hist             |          73     93.59%     93.59% |           0      0.00%     93.59% |           0      0.00%     93.59% |           0      0.00%     93.59% |           0      0.00%     93.59% |           0      0.00%     93.59% |           4      5.13%     98.72% |           1      1.28%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.hit_latency_hist::total                78                      
+system.ruby.hit_latency_hist::samples              57                      
+system.ruby.hit_latency_hist::mean          21.684211                      
+system.ruby.hit_latency_hist::gmean          4.921220                      
+system.ruby.hit_latency_hist::stdev         41.339257                      
+system.ruby.hit_latency_hist             |          47     82.46%     82.46% |           0      0.00%     82.46% |           0      0.00%     82.46% |           0      0.00%     82.46% |           0      0.00%     82.46% |           0      0.00%     82.46% |           6     10.53%     92.98% |           4      7.02%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.hit_latency_hist::total                57                      
 system.ruby.miss_latency_hist::bucket_size         4096                      
 system.ruby.miss_latency_hist::max_bucket        40959                      
-system.ruby.miss_latency_hist::samples            907                      
-system.ruby.miss_latency_hist::mean       5637.887541                      
-system.ruby.miss_latency_hist::gmean      2426.075868                      
-system.ruby.miss_latency_hist::stdev      7081.470328                      
-system.ruby.miss_latency_hist            |         617     68.03%     68.03% |          43      4.74%     72.77% |          33      3.64%     76.41% |          91     10.03%     86.44% |          85      9.37%     95.81% |          28      3.09%     98.90% |           9      0.99%     99.89% |           1      0.11%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.miss_latency_hist::total              907                      
-system.ruby.l1_cntrl0.L1Dcache.demand_hits           78                       # Number of cache demand hits
-system.ruby.l1_cntrl0.L1Dcache.demand_misses          852                       # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Dcache.demand_accesses          930                       # Number of cache demand accesses
-system.ruby.l1_cntrl0.L1Icache.demand_hits            0                       # Number of cache demand hits
-system.ruby.l1_cntrl0.L1Icache.demand_misses           56                       # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Icache.demand_accesses           56                       # Number of cache demand accesses
-system.ruby.l1_cntrl0.sequencer.store_waiting_on_load            8                       # Number of times a store aliased with a pending load
-system.ruby.l1_cntrl0.sequencer.store_waiting_on_store          111                       # Number of times a store aliased with a pending store
-system.ruby.l1_cntrl0.sequencer.load_waiting_on_store           15                       # Number of times a load aliased with a pending store
-system.ruby.l1_cntrl0.sequencer.load_waiting_on_load            2                       # Number of times a load aliased with a pending load
-system.ruby.network.routers0.percent_links_utilized     1.520569                      
-system.ruby.network.routers0.msg_count.Request_Control::0          908                      
-system.ruby.network.routers0.msg_count.Response_Data::2          854                      
-system.ruby.network.routers0.msg_count.ResponseL2hit_Data::2           53                      
-system.ruby.network.routers0.msg_count.Writeback_Data::2          903                      
-system.ruby.network.routers0.msg_count.Writeback_Control::0         1806                      
-system.ruby.network.routers0.msg_count.Unblock_Control::2          907                      
-system.ruby.network.routers0.msg_bytes.Request_Control::0         7264                      
-system.ruby.network.routers0.msg_bytes.Response_Data::2        61488                      
-system.ruby.network.routers0.msg_bytes.ResponseL2hit_Data::2         3816                      
-system.ruby.network.routers0.msg_bytes.Writeback_Data::2        65016                      
-system.ruby.network.routers0.msg_bytes.Writeback_Control::0        14448                      
-system.ruby.network.routers0.msg_bytes.Unblock_Control::2         7256                      
-system.ruby.l2_cntrl0.L2cache.demand_hits           53                       # Number of cache demand hits
-system.ruby.l2_cntrl0.L2cache.demand_misses          855                       # Number of cache demand misses
-system.ruby.l2_cntrl0.L2cache.demand_accesses          908                       # Number of cache demand accesses
-system.ruby.network.routers1.percent_links_utilized     2.898940                      
-system.ruby.network.routers1.msg_count.Request_Control::0          908                      
-system.ruby.network.routers1.msg_count.Request_Control::1          855                      
-system.ruby.network.routers1.msg_count.Response_Data::2         1708                      
-system.ruby.network.routers1.msg_count.ResponseL2hit_Data::2           53                      
-system.ruby.network.routers1.msg_count.Writeback_Data::2         1668                      
-system.ruby.network.routers1.msg_count.Writeback_Control::0         1806                      
-system.ruby.network.routers1.msg_count.Writeback_Control::1         1692                      
-system.ruby.network.routers1.msg_count.Writeback_Control::2           80                      
-system.ruby.network.routers1.msg_count.Unblock_Control::2         1758                      
-system.ruby.network.routers1.msg_bytes.Request_Control::0         7264                      
-system.ruby.network.routers1.msg_bytes.Request_Control::1         6840                      
-system.ruby.network.routers1.msg_bytes.Response_Data::2       122976                      
-system.ruby.network.routers1.msg_bytes.ResponseL2hit_Data::2         3816                      
-system.ruby.network.routers1.msg_bytes.Writeback_Data::2       120096                      
-system.ruby.network.routers1.msg_bytes.Writeback_Control::0        14448                      
-system.ruby.network.routers1.msg_bytes.Writeback_Control::1        13536                      
-system.ruby.network.routers1.msg_bytes.Writeback_Control::2          640                      
-system.ruby.network.routers1.msg_bytes.Unblock_Control::2        14064                      
+system.ruby.miss_latency_hist::samples            915                      
+system.ruby.miss_latency_hist::mean       5775.052459                      
+system.ruby.miss_latency_hist::gmean      2371.333869                      
+system.ruby.miss_latency_hist::stdev      7708.420615                      
+system.ruby.miss_latency_hist            |         643     70.27%     70.27% |          56      6.12%     76.39% |          10      1.09%     77.49% |          35      3.83%     81.31% |          92     10.05%     91.37% |          63      6.89%     98.25% |          14      1.53%     99.78% |           2      0.22%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.miss_latency_hist::total              915                      
+system.ruby.l1_cntrl0.L1Dcache.demand_hits           54                       # Number of cache demand hits
+system.ruby.l1_cntrl0.L1Dcache.demand_misses          862                       # Number of cache demand misses
+system.ruby.l1_cntrl0.L1Dcache.demand_accesses          916                       # Number of cache demand accesses
+system.ruby.l1_cntrl0.L1Icache.demand_hits            3                       # Number of cache demand hits
+system.ruby.l1_cntrl0.L1Icache.demand_misses           55                       # Number of cache demand misses
+system.ruby.l1_cntrl0.L1Icache.demand_accesses           58                       # Number of cache demand accesses
+system.ruby.l1_cntrl0.sequencer.store_waiting_on_load            1                       # Number of times a store aliased with a pending load
+system.ruby.l1_cntrl0.sequencer.store_waiting_on_store           87                       # Number of times a store aliased with a pending store
+system.ruby.l1_cntrl0.sequencer.load_waiting_on_store            3                       # Number of times a load aliased with a pending store
+system.ruby.network.routers0.percent_links_utilized     1.484895                      
+system.ruby.network.routers0.msg_count.Request_Control::0          917                      
+system.ruby.network.routers0.msg_count.Response_Data::2          860                      
+system.ruby.network.routers0.msg_count.ResponseL2hit_Data::2           55                      
+system.ruby.network.routers0.msg_count.Writeback_Data::2          910                      
+system.ruby.network.routers0.msg_count.Writeback_Control::0         1823                      
+system.ruby.network.routers0.msg_count.Unblock_Control::2          915                      
+system.ruby.network.routers0.msg_bytes.Request_Control::0         7336                      
+system.ruby.network.routers0.msg_bytes.Response_Data::2        61920                      
+system.ruby.network.routers0.msg_bytes.ResponseL2hit_Data::2         3960                      
+system.ruby.network.routers0.msg_bytes.Writeback_Data::2        65520                      
+system.ruby.network.routers0.msg_bytes.Writeback_Control::0        14584                      
+system.ruby.network.routers0.msg_bytes.Unblock_Control::2         7320                      
+system.ruby.l2_cntrl0.L2cache.demand_hits           55                       # Number of cache demand hits
+system.ruby.l2_cntrl0.L2cache.demand_misses          862                       # Number of cache demand misses
+system.ruby.l2_cntrl0.L2cache.demand_accesses          917                       # Number of cache demand accesses
+system.ruby.network.routers1.percent_links_utilized     2.834981                      
+system.ruby.network.routers1.msg_count.Request_Control::0          917                      
+system.ruby.network.routers1.msg_count.Request_Control::1          862                      
+system.ruby.network.routers1.msg_count.Response_Data::2         1721                      
+system.ruby.network.routers1.msg_count.ResponseL2hit_Data::2           55                      
+system.ruby.network.routers1.msg_count.Writeback_Data::2         1689                      
+system.ruby.network.routers1.msg_count.Writeback_Control::0         1823                      
+system.ruby.network.routers1.msg_count.Writeback_Control::1         1704                      
+system.ruby.network.routers1.msg_count.Writeback_Control::2           73                      
+system.ruby.network.routers1.msg_count.Unblock_Control::2         1773                      
+system.ruby.network.routers1.msg_bytes.Request_Control::0         7336                      
+system.ruby.network.routers1.msg_bytes.Request_Control::1         6896                      
+system.ruby.network.routers1.msg_bytes.Response_Data::2       123912                      
+system.ruby.network.routers1.msg_bytes.ResponseL2hit_Data::2         3960                      
+system.ruby.network.routers1.msg_bytes.Writeback_Data::2       121608                      
+system.ruby.network.routers1.msg_bytes.Writeback_Control::0        14584                      
+system.ruby.network.routers1.msg_bytes.Writeback_Control::1        13632                      
+system.ruby.network.routers1.msg_bytes.Writeback_Control::2          584                      
+system.ruby.network.routers1.msg_bytes.Unblock_Control::2        14184                      
 system.ruby.memctrl_clk_domain.clock                3                       # Clock period in ticks
-system.ruby.dir_cntrl0.memBuffer.memReq          1619                       # Total number of memory requests
-system.ruby.dir_cntrl0.memBuffer.memRead          854                       # Number of memory reads
-system.ruby.dir_cntrl0.memBuffer.memWrite          765                       # Number of memory writes
-system.ruby.dir_cntrl0.memBuffer.memRefresh         2273                       # Number of memory refreshes
-system.ruby.dir_cntrl0.memBuffer.memWaitCycles          420                       # Delay stalled at the head of the bank queue
+system.ruby.dir_cntrl0.memBuffer.memReq          1640                       # Total number of memory requests
+system.ruby.dir_cntrl0.memBuffer.memRead          861                       # Number of memory reads
+system.ruby.dir_cntrl0.memBuffer.memWrite          779                       # Number of memory writes
+system.ruby.dir_cntrl0.memBuffer.memRefresh         2346                       # Number of memory refreshes
+system.ruby.dir_cntrl0.memBuffer.memWaitCycles          430                       # Delay stalled at the head of the bank queue
 system.ruby.dir_cntrl0.memBuffer.memInputQ           26                       # Delay in the input queue
-system.ruby.dir_cntrl0.memBuffer.totalStalls          446                       # Total number of stall cycles
-system.ruby.dir_cntrl0.memBuffer.stallsPerReq     0.275479                       # Expected number of stall cycles per request
-system.ruby.dir_cntrl0.memBuffer.memBankBusy          163                       # memory stalls due to busy bank
-system.ruby.dir_cntrl0.memBuffer.memBusBusy          144                       # memory stalls due to busy bus
+system.ruby.dir_cntrl0.memBuffer.totalStalls          456                       # Total number of stall cycles
+system.ruby.dir_cntrl0.memBuffer.stallsPerReq     0.278049                       # Expected number of stall cycles per request
+system.ruby.dir_cntrl0.memBuffer.memBankBusy          167                       # memory stalls due to busy bank
+system.ruby.dir_cntrl0.memBuffer.memBusBusy          152                       # memory stalls due to busy bus
 system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy           21                       # memory stalls due to read write turnaround
-system.ruby.dir_cntrl0.memBuffer.memDataBusBusy           60                       # memory stalls due to read read turnaround
+system.ruby.dir_cntrl0.memBuffer.memDataBusBusy           58                       # memory stalls due to read read turnaround
 system.ruby.dir_cntrl0.memBuffer.memArbWait           32                       # memory stalls due to arbitration
-system.ruby.dir_cntrl0.memBuffer.memBankCount |          49      3.03%      3.03% |          44      2.72%      5.74% |          48      2.96%      8.71% |          84      5.19%     13.90% |          49      3.03%     16.92% |          52      3.21%     20.14% |          64      3.95%     24.09% |          51      3.15%     27.24% |          40      2.47%     29.71% |          45      2.78%     32.49% |          48      2.96%     35.45% |          41      2.53%     37.99% |          74      4.57%     42.56% |          47      2.90%     45.46% |          51      3.15%     48.61% |          38      2.35%     50.96% |          56      3.46%     54.42% |          62      3.83%     58.25% |          37      2.29%     60.53% |          58      3.58%     64.11% |          46      2.84%     66.95% |          50      3.09%     70.04% |          55      3.40%     73.44% |          36      2.22%     75.66% |          49      3.03%     78.69% |          71      4.39%     83.08% |          52      3.21%     86.29% |          40      2.47%     88.76% |          42      2.59%     91.35% |          33      2.04%     93.39% |          48      2.96%     96.36% |          59      3.64%    100.00% # Number of accesses per bank
-system.ruby.dir_cntrl0.memBuffer.memBankCount::total         1619                       # Number of accesses per bank
-system.ruby.network.routers2.percent_links_utilized     1.378219                      
-system.ruby.network.routers2.msg_count.Request_Control::1          854                      
-system.ruby.network.routers2.msg_count.Response_Data::2          854                      
-system.ruby.network.routers2.msg_count.Writeback_Data::2          765                      
-system.ruby.network.routers2.msg_count.Writeback_Control::1         1690                      
-system.ruby.network.routers2.msg_count.Writeback_Control::2           80                      
-system.ruby.network.routers2.msg_count.Unblock_Control::2          852                      
-system.ruby.network.routers2.msg_bytes.Request_Control::1         6832                      
-system.ruby.network.routers2.msg_bytes.Response_Data::2        61488                      
-system.ruby.network.routers2.msg_bytes.Writeback_Data::2        55080                      
-system.ruby.network.routers2.msg_bytes.Writeback_Control::1        13520                      
-system.ruby.network.routers2.msg_bytes.Writeback_Control::2          640                      
-system.ruby.network.routers2.msg_bytes.Unblock_Control::2         6816                      
-system.ruby.network.routers3.percent_links_utilized     1.932474                      
-system.ruby.network.routers3.msg_count.Request_Control::0          908                      
-system.ruby.network.routers3.msg_count.Request_Control::1          854                      
-system.ruby.network.routers3.msg_count.Response_Data::2         1708                      
-system.ruby.network.routers3.msg_count.ResponseL2hit_Data::2           53                      
-system.ruby.network.routers3.msg_count.Writeback_Data::2         1668                      
-system.ruby.network.routers3.msg_count.Writeback_Control::0         1806                      
-system.ruby.network.routers3.msg_count.Writeback_Control::1         1690                      
-system.ruby.network.routers3.msg_count.Writeback_Control::2           80                      
-system.ruby.network.routers3.msg_count.Unblock_Control::2         1758                      
-system.ruby.network.routers3.msg_bytes.Request_Control::0         7264                      
-system.ruby.network.routers3.msg_bytes.Request_Control::1         6832                      
-system.ruby.network.routers3.msg_bytes.Response_Data::2       122976                      
-system.ruby.network.routers3.msg_bytes.ResponseL2hit_Data::2         3816                      
-system.ruby.network.routers3.msg_bytes.Writeback_Data::2       120096                      
-system.ruby.network.routers3.msg_bytes.Writeback_Control::0        14448                      
-system.ruby.network.routers3.msg_bytes.Writeback_Control::1        13520                      
-system.ruby.network.routers3.msg_bytes.Writeback_Control::2          640                      
-system.ruby.network.routers3.msg_bytes.Unblock_Control::2        14064                      
-system.ruby.network.msg_count.Request_Control         5287                      
-system.ruby.network.msg_count.Response_Data         5124                      
-system.ruby.network.msg_count.ResponseL2hit_Data          159                      
-system.ruby.network.msg_count.Writeback_Data         5004                      
-system.ruby.network.msg_count.Writeback_Control        10730                      
-system.ruby.network.msg_count.Unblock_Control         5275                      
-system.ruby.network.msg_byte.Request_Control        42296                      
-system.ruby.network.msg_byte.Response_Data       368928                      
-system.ruby.network.msg_byte.ResponseL2hit_Data        11448                      
-system.ruby.network.msg_byte.Writeback_Data       360288                      
-system.ruby.network.msg_byte.Writeback_Control        85840                      
-system.ruby.network.msg_byte.Unblock_Control        42200                      
-system.ruby.network.routers0.throttle0.link_utilization     1.384710                      
-system.ruby.network.routers0.throttle0.msg_count.Response_Data::2          854                      
-system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::2           53                      
-system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::0          903                      
-system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::2        61488                      
-system.ruby.network.routers0.throttle0.msg_bytes.ResponseL2hit_Data::2         3816                      
-system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::0         7224                      
-system.ruby.network.routers0.throttle1.link_utilization     1.656428                      
-system.ruby.network.routers0.throttle1.msg_count.Request_Control::0          908                      
-system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::2          903                      
-system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::0          903                      
-system.ruby.network.routers0.throttle1.msg_count.Unblock_Control::2          907                      
-system.ruby.network.routers0.throttle1.msg_bytes.Request_Control::0         7264                      
-system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::2        65016                      
-system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::0         7224                      
-system.ruby.network.routers0.throttle1.msg_bytes.Unblock_Control::2         7256                      
-system.ruby.network.routers1.throttle0.link_utilization     2.959271                      
-system.ruby.network.routers1.throttle0.msg_count.Request_Control::0          908                      
-system.ruby.network.routers1.throttle0.msg_count.Response_Data::2          854                      
-system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::2          903                      
-system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::0          903                      
-system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::1          845                      
-system.ruby.network.routers1.throttle0.msg_count.Unblock_Control::2          906                      
-system.ruby.network.routers1.throttle0.msg_bytes.Request_Control::0         7264                      
-system.ruby.network.routers1.throttle0.msg_bytes.Response_Data::2        61488                      
-system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::2        65016                      
-system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::0         7224                      
-system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::1         6760                      
-system.ruby.network.routers1.throttle0.msg_bytes.Unblock_Control::2         7248                      
-system.ruby.network.routers1.throttle1.link_utilization     2.838609                      
-system.ruby.network.routers1.throttle1.msg_count.Request_Control::1          855                      
-system.ruby.network.routers1.throttle1.msg_count.Response_Data::2          854                      
-system.ruby.network.routers1.throttle1.msg_count.ResponseL2hit_Data::2           53                      
-system.ruby.network.routers1.throttle1.msg_count.Writeback_Data::2          765                      
-system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::0          903                      
-system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::1          847                      
-system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::2           80                      
-system.ruby.network.routers1.throttle1.msg_count.Unblock_Control::2          852                      
-system.ruby.network.routers1.throttle1.msg_bytes.Request_Control::1         6840                      
-system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::2        61488                      
-system.ruby.network.routers1.throttle1.msg_bytes.ResponseL2hit_Data::2         3816                      
-system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::2        55080                      
-system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::0         7224                      
-system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::1         6776                      
-system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::2          640                      
-system.ruby.network.routers1.throttle1.msg_bytes.Unblock_Control::2         6816                      
-system.ruby.network.routers2.throttle0.link_utilization     1.453441                      
-system.ruby.network.routers2.throttle0.msg_count.Request_Control::1          854                      
-system.ruby.network.routers2.throttle0.msg_count.Writeback_Data::2          765                      
-system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::1          845                      
-system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::2           80                      
-system.ruby.network.routers2.throttle0.msg_count.Unblock_Control::2          852                      
-system.ruby.network.routers2.throttle0.msg_bytes.Request_Control::1         6832                      
-system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Data::2        55080                      
-system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::1         6760                      
-system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::2          640                      
-system.ruby.network.routers2.throttle0.msg_bytes.Unblock_Control::2         6816                      
-system.ruby.network.routers2.throttle1.link_utilization     1.302996                      
-system.ruby.network.routers2.throttle1.msg_count.Response_Data::2          854                      
-system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::1          845                      
-system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::2        61488                      
-system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::1         6760                      
-system.ruby.network.routers3.throttle0.link_utilization     1.384710                      
-system.ruby.network.routers3.throttle0.msg_count.Response_Data::2          854                      
-system.ruby.network.routers3.throttle0.msg_count.ResponseL2hit_Data::2           53                      
-system.ruby.network.routers3.throttle0.msg_count.Writeback_Control::0          903                      
-system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::2        61488                      
-system.ruby.network.routers3.throttle0.msg_bytes.ResponseL2hit_Data::2         3816                      
-system.ruby.network.routers3.throttle0.msg_bytes.Writeback_Control::0         7224                      
-system.ruby.network.routers3.throttle1.link_utilization     2.959271                      
-system.ruby.network.routers3.throttle1.msg_count.Request_Control::0          908                      
-system.ruby.network.routers3.throttle1.msg_count.Response_Data::2          854                      
-system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::2          903                      
-system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::0          903                      
-system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::1          845                      
-system.ruby.network.routers3.throttle1.msg_count.Unblock_Control::2          906                      
-system.ruby.network.routers3.throttle1.msg_bytes.Request_Control::0         7264                      
-system.ruby.network.routers3.throttle1.msg_bytes.Response_Data::2        61488                      
-system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::2        65016                      
-system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::0         7224                      
-system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::1         6760                      
-system.ruby.network.routers3.throttle1.msg_bytes.Unblock_Control::2         7248                      
-system.ruby.network.routers3.throttle2.link_utilization     1.453441                      
-system.ruby.network.routers3.throttle2.msg_count.Request_Control::1          854                      
-system.ruby.network.routers3.throttle2.msg_count.Writeback_Data::2          765                      
-system.ruby.network.routers3.throttle2.msg_count.Writeback_Control::1          845                      
-system.ruby.network.routers3.throttle2.msg_count.Writeback_Control::2           80                      
-system.ruby.network.routers3.throttle2.msg_count.Unblock_Control::2          852                      
-system.ruby.network.routers3.throttle2.msg_bytes.Request_Control::1         6832                      
-system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Data::2        55080                      
-system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Control::1         6760                      
-system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Control::2          640                      
-system.ruby.network.routers3.throttle2.msg_bytes.Unblock_Control::2         6816                      
+system.ruby.dir_cntrl0.memBuffer.memBankCount |          58      3.54%      3.54% |          44      2.68%      6.22% |          40      2.44%      8.66% |          88      5.37%     14.02% |          64      3.90%     17.93% |          67      4.09%     22.01% |          55      3.35%     25.37% |          38      2.32%     27.68% |          52      3.17%     30.85% |          39      2.38%     33.23% |          42      2.56%     35.79% |          42      2.56%     38.35% |          49      2.99%     41.34% |          50      3.05%     44.39% |          48      2.93%     47.32% |          55      3.35%     50.67% |          48      2.93%     53.60% |          48      2.93%     56.52% |          50      3.05%     59.57% |          46      2.80%     62.38% |          49      2.99%     65.37% |          70      4.27%     69.63% |          43      2.62%     72.26% |          63      3.84%     76.10% |          59      3.60%     79.70% |          46      2.80%     82.50% |          53      3.23%     85.73% |          56      3.41%     89.15% |          35      2.13%     91.28% |          46      2.80%     94.09% |          42      2.56%     96.65% |          55      3.35%    100.00% # Number of accesses per bank
+system.ruby.dir_cntrl0.memBuffer.memBankCount::total         1640                       # Number of accesses per bank
+system.ruby.network.routers2.percent_links_utilized     1.350086                      
+system.ruby.network.routers2.msg_count.Request_Control::1          861                      
+system.ruby.network.routers2.msg_count.Response_Data::2          861                      
+system.ruby.network.routers2.msg_count.Writeback_Data::2          779                      
+system.ruby.network.routers2.msg_count.Writeback_Control::1         1704                      
+system.ruby.network.routers2.msg_count.Writeback_Control::2           73                      
+system.ruby.network.routers2.msg_count.Unblock_Control::2          859                      
+system.ruby.network.routers2.msg_bytes.Request_Control::1         6888                      
+system.ruby.network.routers2.msg_bytes.Response_Data::2        61992                      
+system.ruby.network.routers2.msg_bytes.Writeback_Data::2        56088                      
+system.ruby.network.routers2.msg_bytes.Writeback_Control::1        13632                      
+system.ruby.network.routers2.msg_bytes.Writeback_Control::2          584                      
+system.ruby.network.routers2.msg_bytes.Unblock_Control::2         6872                      
+system.ruby.network.routers3.percent_links_utilized     1.890037                      
+system.ruby.network.routers3.msg_count.Request_Control::0          917                      
+system.ruby.network.routers3.msg_count.Request_Control::1          862                      
+system.ruby.network.routers3.msg_count.Response_Data::2         1721                      
+system.ruby.network.routers3.msg_count.ResponseL2hit_Data::2           55                      
+system.ruby.network.routers3.msg_count.Writeback_Data::2         1689                      
+system.ruby.network.routers3.msg_count.Writeback_Control::0         1823                      
+system.ruby.network.routers3.msg_count.Writeback_Control::1         1704                      
+system.ruby.network.routers3.msg_count.Writeback_Control::2           73                      
+system.ruby.network.routers3.msg_count.Unblock_Control::2         1774                      
+system.ruby.network.routers3.msg_bytes.Request_Control::0         7336                      
+system.ruby.network.routers3.msg_bytes.Request_Control::1         6896                      
+system.ruby.network.routers3.msg_bytes.Response_Data::2       123912                      
+system.ruby.network.routers3.msg_bytes.ResponseL2hit_Data::2         3960                      
+system.ruby.network.routers3.msg_bytes.Writeback_Data::2       121608                      
+system.ruby.network.routers3.msg_bytes.Writeback_Control::0        14584                      
+system.ruby.network.routers3.msg_bytes.Writeback_Control::1        13632                      
+system.ruby.network.routers3.msg_bytes.Writeback_Control::2          584                      
+system.ruby.network.routers3.msg_bytes.Unblock_Control::2        14192                      
+system.ruby.network.msg_count.Request_Control         5336                      
+system.ruby.network.msg_count.Response_Data         5163                      
+system.ruby.network.msg_count.ResponseL2hit_Data          165                      
+system.ruby.network.msg_count.Writeback_Data         5067                      
+system.ruby.network.msg_count.Writeback_Control        10800                      
+system.ruby.network.msg_count.Unblock_Control         5321                      
+system.ruby.network.msg_byte.Request_Control        42688                      
+system.ruby.network.msg_byte.Response_Data       371736                      
+system.ruby.network.msg_byte.ResponseL2hit_Data        11880                      
+system.ruby.network.msg_byte.Writeback_Data       364824                      
+system.ruby.network.msg_byte.Writeback_Control        86400                      
+system.ruby.network.msg_byte.Unblock_Control        42568                      
+system.ruby.network.routers0.throttle0.link_utilization     1.352674                      
+system.ruby.network.routers0.throttle0.msg_count.Response_Data::2          860                      
+system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::2           55                      
+system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::0          911                      
+system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::2        61920                      
+system.ruby.network.routers0.throttle0.msg_bytes.ResponseL2hit_Data::2         3960                      
+system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::0         7288                      
+system.ruby.network.routers0.throttle1.link_utilization     1.617116                      
+system.ruby.network.routers0.throttle1.msg_count.Request_Control::0          917                      
+system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::2          910                      
+system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::0          912                      
+system.ruby.network.routers0.throttle1.msg_count.Unblock_Control::2          915                      
+system.ruby.network.routers0.throttle1.msg_bytes.Request_Control::0         7336                      
+system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::2        65520                      
+system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::0         7296                      
+system.ruby.network.routers0.throttle1.msg_bytes.Unblock_Control::2         7320                      
+system.ruby.network.routers1.throttle0.link_utilization     2.889038                      
+system.ruby.network.routers1.throttle0.msg_count.Request_Control::0          917                      
+system.ruby.network.routers1.throttle0.msg_count.Response_Data::2          861                      
+system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::2          910                      
+system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::0          912                      
+system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::1          852                      
+system.ruby.network.routers1.throttle0.msg_count.Unblock_Control::2          914                      
+system.ruby.network.routers1.throttle0.msg_bytes.Request_Control::0         7336                      
+system.ruby.network.routers1.throttle0.msg_bytes.Response_Data::2        61992                      
+system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::2        65520                      
+system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::0         7296                      
+system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::1         6816                      
+system.ruby.network.routers1.throttle0.msg_bytes.Unblock_Control::2         7312                      
+system.ruby.network.routers1.throttle1.link_utilization     2.780925                      
+system.ruby.network.routers1.throttle1.msg_count.Request_Control::1          862                      
+system.ruby.network.routers1.throttle1.msg_count.Response_Data::2          860                      
+system.ruby.network.routers1.throttle1.msg_count.ResponseL2hit_Data::2           55                      
+system.ruby.network.routers1.throttle1.msg_count.Writeback_Data::2          779                      
+system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::0          911                      
+system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::1          852                      
+system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::2           73                      
+system.ruby.network.routers1.throttle1.msg_count.Unblock_Control::2          859                      
+system.ruby.network.routers1.throttle1.msg_bytes.Request_Control::1         6896                      
+system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::2        61920                      
+system.ruby.network.routers1.throttle1.msg_bytes.ResponseL2hit_Data::2         3960                      
+system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::2        56088                      
+system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::0         7288                      
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 system.ruby.LD.latency_hist::bucket_size         4096                      
 system.ruby.LD.latency_hist::max_bucket         40959                      
-system.ruby.LD.latency_hist::samples               44                      
-system.ruby.LD.latency_hist::mean         5510.704545                      
-system.ruby.LD.latency_hist::gmean         869.978187                      
-system.ruby.LD.latency_hist::stdev        7880.576607                      
-system.ruby.LD.latency_hist              |          32     72.73%     72.73% |           0      0.00%     72.73% |           1      2.27%     75.00% |           4      9.09%     84.09% |           5     11.36%     95.45% |           1      2.27%     97.73% |           1      2.27%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.LD.latency_hist::total                 44                      
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+system.ruby.LD.latency_hist::mean         6256.744186                      
+system.ruby.LD.latency_hist::gmean        1688.376032                      
+system.ruby.LD.latency_hist::stdev        8068.365932                      
+system.ruby.LD.latency_hist              |          29     67.44%     67.44% |           1      2.33%     69.77% |           1      2.33%     72.09% |           3      6.98%     79.07% |           4      9.30%     88.37% |           5     11.63%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.latency_hist::total                 43                      
 system.ruby.LD.hit_latency_hist::bucket_size            1                      
 system.ruby.LD.hit_latency_hist::max_bucket            9                      
-system.ruby.LD.hit_latency_hist::samples            6                      
-system.ruby.LD.hit_latency_hist::mean        2.166667                      
-system.ruby.LD.hit_latency_hist::gmean       1.906369                      
-system.ruby.LD.hit_latency_hist::stdev       1.169045                      
-system.ruby.LD.hit_latency_hist          |           0      0.00%      0.00% |           2     33.33%     33.33% |           2     33.33%     66.67% |           1     16.67%     83.33% |           1     16.67%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.LD.hit_latency_hist::total              6                      
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+system.ruby.LD.hit_latency_hist::mean        3.666667                      
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+system.ruby.LD.hit_latency_hist::stdev       0.577350                      
+system.ruby.LD.hit_latency_hist          |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           1     33.33%     33.33% |           2     66.67%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.hit_latency_hist::total              3                      
 system.ruby.LD.miss_latency_hist::bucket_size         4096                      
 system.ruby.LD.miss_latency_hist::max_bucket        40959                      
-system.ruby.LD.miss_latency_hist::samples           38                      
-system.ruby.LD.miss_latency_hist::mean    6380.473684                      
-system.ruby.LD.miss_latency_hist::gmean   2287.694735                      
-system.ruby.LD.miss_latency_hist::stdev   8153.326443                      
-system.ruby.LD.miss_latency_hist         |          26     68.42%     68.42% |           0      0.00%     68.42% |           1      2.63%     71.05% |           4     10.53%     81.58% |           5     13.16%     94.74% |           1      2.63%     97.37% |           1      2.63%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.LD.miss_latency_hist::total            38                      
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+system.ruby.LD.miss_latency_hist::gmean   2676.075339                      
+system.ruby.LD.miss_latency_hist::stdev   8177.576523                      
+system.ruby.LD.miss_latency_hist         |          26     65.00%     65.00% |           1      2.50%     67.50% |           1      2.50%     70.00% |           3      7.50%     77.50% |           4     10.00%     87.50% |           5     12.50%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.miss_latency_hist::total            40                      
 system.ruby.ST.latency_hist::bucket_size         4096                      
 system.ruby.ST.latency_hist::max_bucket         40959                      
-system.ruby.ST.latency_hist::samples              885                      
-system.ruby.ST.latency_hist::mean         5462.276836                      
-system.ruby.ST.latency_hist::gmean        1523.559741                      
-system.ruby.ST.latency_hist::stdev        7040.777523                      
-system.ruby.ST.latency_hist              |         607     68.59%     68.59% |          43      4.86%     73.45% |          32      3.62%     77.06% |          87      9.83%     86.89% |          80      9.04%     95.93% |          27      3.05%     98.98% |           8      0.90%     99.89% |           1      0.11%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.ST.latency_hist::total                885                      
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+system.ruby.ST.latency_hist              |         614     70.41%     70.41% |          55      6.31%     76.72% |           9      1.03%     77.75% |          32      3.67%     81.42% |          88     10.09%     91.51% |          58      6.65%     98.17% |          14      1.61%     99.77% |           2      0.23%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
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 system.ruby.ST.hit_latency_hist::bucket_size           16                      
 system.ruby.ST.hit_latency_hist::max_bucket          159                      
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-system.ruby.ST.hit_latency_hist::mean        9.666667                      
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-system.ruby.ST.hit_latency_hist::stdev      27.206047                      
-system.ruby.ST.hit_latency_hist          |          67     93.06%     93.06% |           0      0.00%     93.06% |           0      0.00%     93.06% |           0      0.00%     93.06% |           0      0.00%     93.06% |           0      0.00%     93.06% |           4      5.56%     98.61% |           1      1.39%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.ST.hit_latency_hist::total             72                      
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+system.ruby.ST.hit_latency_hist::stdev      41.550942                      
+system.ruby.ST.hit_latency_hist          |          42     82.35%     82.35% |           0      0.00%     82.35% |           0      0.00%     82.35% |           0      0.00%     82.35% |           0      0.00%     82.35% |           0      0.00%     82.35% |           5      9.80%     92.16% |           4      7.84%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.hit_latency_hist::total             51                      
 system.ruby.ST.miss_latency_hist::bucket_size         4096                      
 system.ruby.ST.miss_latency_hist::max_bucket        40959                      
-system.ruby.ST.miss_latency_hist::samples          813                      
-system.ruby.ST.miss_latency_hist::mean    5945.164822                      
-system.ruby.ST.miss_latency_hist::gmean   2673.966009                      
-system.ruby.ST.miss_latency_hist::stdev   7148.312268                      
-system.ruby.ST.miss_latency_hist         |         535     65.81%     65.81% |          43      5.29%     71.09% |          32      3.94%     75.03% |          87     10.70%     85.73% |          80      9.84%     95.57% |          27      3.32%     98.89% |           8      0.98%     99.88% |           1      0.12%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.ST.miss_latency_hist::total           813                      
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-system.ruby.IFETCH.latency_hist::max_bucket         2559                      
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-system.ruby.IFETCH.latency_hist::mean      672.982143                      
-system.ruby.IFETCH.latency_hist::gmean     614.909107                      
-system.ruby.IFETCH.latency_hist::stdev     260.614623                      
-system.ruby.IFETCH.latency_hist          |           4      7.14%      7.14% |           9     16.07%     23.21% |          24     42.86%     66.07% |          17     30.36%     96.43% |           1      1.79%     98.21% |           1      1.79%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.IFETCH.latency_hist::total             56                      
-system.ruby.IFETCH.miss_latency_hist::bucket_size          256                      
-system.ruby.IFETCH.miss_latency_hist::max_bucket         2559                      
-system.ruby.IFETCH.miss_latency_hist::samples           56                      
-system.ruby.IFETCH.miss_latency_hist::mean   672.982143                      
-system.ruby.IFETCH.miss_latency_hist::gmean   614.909107                      
-system.ruby.IFETCH.miss_latency_hist::stdev   260.614623                      
-system.ruby.IFETCH.miss_latency_hist     |           4      7.14%      7.14% |           9     16.07%     23.21% |          24     42.86%     66.07% |          17     30.36%     96.43% |           1      1.79%     98.21% |           1      1.79%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.IFETCH.miss_latency_hist::total           56                      
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+system.ruby.ST.miss_latency_hist::stdev   7820.542647                      
+system.ruby.ST.miss_latency_hist         |         563     68.57%     68.57% |          55      6.70%     75.27% |           9      1.10%     76.37% |          32      3.90%     80.27% |          88     10.72%     90.99% |          58      7.06%     98.05% |          14      1.71%     99.76% |           2      0.24%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
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+system.ruby.IFETCH.latency_hist::bucket_size          128                      
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+system.ruby.IFETCH.latency_hist::stdev     271.884544                      
+system.ruby.IFETCH.latency_hist          |           3      5.26%      5.26% |           3      5.26%     10.53% |           9     15.79%     26.32% |           6     10.53%     36.84% |          11     19.30%     56.14% |          10     17.54%     73.68% |           8     14.04%     87.72% |           3      5.26%     92.98% |           4      7.02%    100.00% |           0      0.00%    100.00%
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+system.ruby.IFETCH.hit_latency_hist::stdev    61.784572                      
+system.ruby.IFETCH.hit_latency_hist      |           2     66.67%     66.67% |           0      0.00%     66.67% |           0      0.00%     66.67% |           0      0.00%     66.67% |           0      0.00%     66.67% |           0      0.00%     66.67% |           1     33.33%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.hit_latency_hist::total            3                      
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+system.ruby.IFETCH.miss_latency_hist::total           54                      
 system.ruby.L1Cache_Controller.Load                44      0.00%      0.00%
-system.ruby.L1Cache_Controller.Ifetch             192      0.00%      0.00%
-system.ruby.L1Cache_Controller.Store             1001      0.00%      0.00%
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-system.ruby.L1Cache_Controller.Exclusive_Data          907      0.00%      0.00%
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-system.ruby.L1Cache_Controller.All_acks           813      0.00%      0.00%
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 system.ruby.L1Cache_Controller.M.L1_Replacement           92      0.00%      0.00%
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 system.ruby.L1Cache_Controller.M_W.Use_Timeout           93      0.00%      0.00%
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-system.ruby.L1Cache_Controller.IM.Exclusive_Data          813      0.00%      0.00%
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-system.ruby.L1Cache_Controller.MI.Ifetch          136      0.00%      0.00%
-system.ruby.L1Cache_Controller.MI.Store           115      0.00%      0.00%
-system.ruby.L1Cache_Controller.MI.Writeback_Ack_Data          903      0.00%      0.00%
-system.ruby.L2Cache_Controller.L1_GETS            127      0.00%      0.00%
-system.ruby.L2Cache_Controller.L1_GETX            895      0.00%      0.00%
-system.ruby.L2Cache_Controller.L1_PUTX           2308      0.00%      0.00%
-system.ruby.L2Cache_Controller.All_Acks           766      0.00%      0.00%
-system.ruby.L2Cache_Controller.Data               766      0.00%      0.00%
-system.ruby.L2Cache_Controller.Data_Exclusive           88      0.00%      0.00%
-system.ruby.L2Cache_Controller.L1_WBCLEANDATA           86      0.00%      0.00%
-system.ruby.L2Cache_Controller.L1_WBDIRTYDATA          817      0.00%      0.00%
-system.ruby.L2Cache_Controller.Writeback_Ack          845      0.00%      0.00%
-system.ruby.L2Cache_Controller.Exclusive_Unblock          906      0.00%      0.00%
-system.ruby.L2Cache_Controller.L2_Replacement          847      0.00%      0.00%
-system.ruby.L2Cache_Controller.NP.L1_GETS           88      0.00%      0.00%
-system.ruby.L2Cache_Controller.NP.L1_GETX          767      0.00%      0.00%
-system.ruby.L2Cache_Controller.ILX.L1_PUTX          903      0.00%      0.00%
-system.ruby.L2Cache_Controller.M.L1_GETS            6      0.00%      0.00%
-system.ruby.L2Cache_Controller.M.L1_GETX           47      0.00%      0.00%
-system.ruby.L2Cache_Controller.M.L2_Replacement          847      0.00%      0.00%
-system.ruby.L2Cache_Controller.ILXW.L1_GETS           33      0.00%      0.00%
-system.ruby.L2Cache_Controller.ILXW.L1_WBCLEANDATA           86      0.00%      0.00%
-system.ruby.L2Cache_Controller.ILXW.L1_WBDIRTYDATA          817      0.00%      0.00%
-system.ruby.L2Cache_Controller.IGS.L1_PUTX           65      0.00%      0.00%
-system.ruby.L2Cache_Controller.IGS.Data_Exclusive           88      0.00%      0.00%
-system.ruby.L2Cache_Controller.IGS.Exclusive_Unblock           87      0.00%      0.00%
-system.ruby.L2Cache_Controller.IGM.Data           766      0.00%      0.00%
-system.ruby.L2Cache_Controller.IGMO.L1_PUTX         1324      0.00%      0.00%
-system.ruby.L2Cache_Controller.IGMO.All_Acks          766      0.00%      0.00%
-system.ruby.L2Cache_Controller.IGMO.Exclusive_Unblock          766      0.00%      0.00%
-system.ruby.L2Cache_Controller.MM.L1_PUTX            5      0.00%      0.00%
-system.ruby.L2Cache_Controller.MM.Exclusive_Unblock           47      0.00%      0.00%
-system.ruby.L2Cache_Controller.OO.L1_PUTX           11      0.00%      0.00%
-system.ruby.L2Cache_Controller.OO.Exclusive_Unblock            6      0.00%      0.00%
-system.ruby.L2Cache_Controller.MI.L1_GETX           81      0.00%      0.00%
-system.ruby.L2Cache_Controller.MI.Writeback_Ack          845      0.00%      0.00%
-system.ruby.Directory_Controller.GETX             837      0.00%      0.00%
-system.ruby.Directory_Controller.GETS              88      0.00%      0.00%
-system.ruby.Directory_Controller.PUTX             845      0.00%      0.00%
-system.ruby.Directory_Controller.Exclusive_Unblock          852      0.00%      0.00%
-system.ruby.Directory_Controller.Clean_Writeback           80      0.00%      0.00%
-system.ruby.Directory_Controller.Dirty_Writeback          765      0.00%      0.00%
-system.ruby.Directory_Controller.Memory_Data          854      0.00%      0.00%
-system.ruby.Directory_Controller.Memory_Ack          765      0.00%      0.00%
-system.ruby.Directory_Controller.I.GETX           766      0.00%      0.00%
-system.ruby.Directory_Controller.I.GETS            88      0.00%      0.00%
-system.ruby.Directory_Controller.I.Memory_Ack          760      0.00%      0.00%
-system.ruby.Directory_Controller.M.PUTX           845      0.00%      0.00%
-system.ruby.Directory_Controller.IS.Exclusive_Unblock           87      0.00%      0.00%
-system.ruby.Directory_Controller.IS.Memory_Data           88      0.00%      0.00%
-system.ruby.Directory_Controller.IS.Memory_Ack            1      0.00%      0.00%
-system.ruby.Directory_Controller.MM.Exclusive_Unblock          765      0.00%      0.00%
-system.ruby.Directory_Controller.MM.Memory_Data          766      0.00%      0.00%
-system.ruby.Directory_Controller.MM.Memory_Ack            4      0.00%      0.00%
-system.ruby.Directory_Controller.MI.GETX           71      0.00%      0.00%
-system.ruby.Directory_Controller.MI.Clean_Writeback           80      0.00%      0.00%
-system.ruby.Directory_Controller.MI.Dirty_Writeback          765      0.00%      0.00%
+system.ruby.L1Cache_Controller.MI.Load              1      0.00%      0.00%
+system.ruby.L1Cache_Controller.MI.Ifetch          249      0.00%      0.00%
+system.ruby.L1Cache_Controller.MI.Store           141      0.00%      0.00%
+system.ruby.L1Cache_Controller.MI.Writeback_Ack_Data          911      0.00%      0.00%
+system.ruby.L2Cache_Controller.L1_GETS            142      0.00%      0.00%
+system.ruby.L2Cache_Controller.L1_GETX            948      0.00%      0.00%
+system.ruby.L2Cache_Controller.L1_PUTX           2296      0.00%      0.00%
+system.ruby.L2Cache_Controller.All_Acks           782      0.00%      0.00%
+system.ruby.L2Cache_Controller.Data               782      0.00%      0.00%
+system.ruby.L2Cache_Controller.Data_Exclusive           79      0.00%      0.00%
+system.ruby.L2Cache_Controller.L1_WBCLEANDATA           77      0.00%      0.00%
+system.ruby.L2Cache_Controller.L1_WBDIRTYDATA          833      0.00%      0.00%
+system.ruby.L2Cache_Controller.Writeback_Ack          852      0.00%      0.00%
+system.ruby.L2Cache_Controller.Exclusive_Unblock          914      0.00%      0.00%
+system.ruby.L2Cache_Controller.L2_Replacement          923      0.00%      0.00%
+system.ruby.L2Cache_Controller.NP.L1_GETS           80      0.00%      0.00%
+system.ruby.L2Cache_Controller.NP.L1_GETX          782      0.00%      0.00%
+system.ruby.L2Cache_Controller.ILX.L1_PUTX          912      0.00%      0.00%
+system.ruby.L2Cache_Controller.M.L1_GETS           15      0.00%      0.00%
+system.ruby.L2Cache_Controller.M.L1_GETX           40      0.00%      0.00%
+system.ruby.L2Cache_Controller.M.L2_Replacement          852      0.00%      0.00%
+system.ruby.L2Cache_Controller.ILXW.L1_GETS           30      0.00%      0.00%
+system.ruby.L2Cache_Controller.ILXW.L1_GETX           85      0.00%      0.00%
+system.ruby.L2Cache_Controller.ILXW.L1_WBCLEANDATA           77      0.00%      0.00%
+system.ruby.L2Cache_Controller.ILXW.L1_WBDIRTYDATA          833      0.00%      0.00%
+system.ruby.L2Cache_Controller.IGS.L1_PUTX           25      0.00%      0.00%
+system.ruby.L2Cache_Controller.IGS.Data_Exclusive           79      0.00%      0.00%
+system.ruby.L2Cache_Controller.IGS.Exclusive_Unblock           78      0.00%      0.00%
+system.ruby.L2Cache_Controller.IGM.Data           782      0.00%      0.00%
+system.ruby.L2Cache_Controller.IGMO.L1_PUTX         1344      0.00%      0.00%
+system.ruby.L2Cache_Controller.IGMO.All_Acks          782      0.00%      0.00%
+system.ruby.L2Cache_Controller.IGMO.Exclusive_Unblock          781      0.00%      0.00%
+system.ruby.L2Cache_Controller.MM.L1_PUTX           15      0.00%      0.00%
+system.ruby.L2Cache_Controller.MM.Exclusive_Unblock           40      0.00%      0.00%
+system.ruby.L2Cache_Controller.OO.Exclusive_Unblock           15      0.00%      0.00%
+system.ruby.L2Cache_Controller.OO.L2_Replacement           71      0.00%      0.00%
+system.ruby.L2Cache_Controller.MI.L1_GETS           17      0.00%      0.00%
+system.ruby.L2Cache_Controller.MI.L1_GETX           41      0.00%      0.00%
+system.ruby.L2Cache_Controller.MI.Writeback_Ack          852      0.00%      0.00%
+system.ruby.Directory_Controller.GETX             792      0.00%      0.00%
+system.ruby.Directory_Controller.GETS              79      0.00%      0.00%
+system.ruby.Directory_Controller.PUTX             852      0.00%      0.00%
+system.ruby.Directory_Controller.Exclusive_Unblock          859      0.00%      0.00%
+system.ruby.Directory_Controller.Clean_Writeback           73      0.00%      0.00%
+system.ruby.Directory_Controller.Dirty_Writeback          779      0.00%      0.00%
+system.ruby.Directory_Controller.Memory_Data          861      0.00%      0.00%
+system.ruby.Directory_Controller.Memory_Ack          779      0.00%      0.00%
+system.ruby.Directory_Controller.I.GETX           782      0.00%      0.00%
+system.ruby.Directory_Controller.I.GETS            79      0.00%      0.00%
+system.ruby.Directory_Controller.I.Memory_Ack          775      0.00%      0.00%
+system.ruby.Directory_Controller.M.PUTX           852      0.00%      0.00%
+system.ruby.Directory_Controller.IS.Exclusive_Unblock           78      0.00%      0.00%
+system.ruby.Directory_Controller.IS.Memory_Data           79      0.00%      0.00%
+system.ruby.Directory_Controller.IS.Memory_Ack            2      0.00%      0.00%
+system.ruby.Directory_Controller.MM.Exclusive_Unblock          781      0.00%      0.00%
+system.ruby.Directory_Controller.MM.Memory_Data          782      0.00%      0.00%
+system.ruby.Directory_Controller.MM.Memory_Ack            2      0.00%      0.00%
+system.ruby.Directory_Controller.MI.GETX           10      0.00%      0.00%
+system.ruby.Directory_Controller.MI.Clean_Writeback           73      0.00%      0.00%
+system.ruby.Directory_Controller.MI.Dirty_Writeback          779      0.00%      0.00%
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt
index 389c45695..b6763f2e1 100644
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt
@@ -1,492 +1,495 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000225                       # Number of seconds simulated
-sim_ticks                                      225141                       # Number of ticks simulated
-final_tick                                     225141                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.000230                       # Number of seconds simulated
+sim_ticks                                      229551                       # Number of ticks simulated
+final_tick                                     229551                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_tick_rate                                1830870                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 123716                       # Number of bytes of host memory used
+host_tick_rate                                1899298                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 157300                       # Number of bytes of host memory used
 host_seconds                                     0.12                       # Real time elapsed on the host
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                             1                       # Clock period in ticks
 system.ruby.clk_domain.clock                        1                       # Clock period in ticks
 system.ruby.outstanding_req_hist::bucket_size            2                      
 system.ruby.outstanding_req_hist::max_bucket           19                      
-system.ruby.outstanding_req_hist::samples         1007                      
-system.ruby.outstanding_req_hist::mean      15.821251                      
-system.ruby.outstanding_req_hist::gmean     15.723382                      
-system.ruby.outstanding_req_hist::stdev      1.122615                      
-system.ruby.outstanding_req_hist         |           1      0.10%      0.10% |           2      0.20%      0.30% |           2      0.20%      0.50% |           2      0.20%      0.70% |           2      0.20%      0.89% |           2      0.20%      1.09% |           2      0.20%      1.29% |          62      6.16%      7.45% |         932     92.55%    100.00% |           0      0.00%    100.00%
-system.ruby.outstanding_req_hist::total          1007                      
+system.ruby.outstanding_req_hist::samples          985                      
+system.ruby.outstanding_req_hist::mean      15.815228                      
+system.ruby.outstanding_req_hist::gmean     15.715128                      
+system.ruby.outstanding_req_hist::stdev      1.136234                      
+system.ruby.outstanding_req_hist         |           1      0.10%      0.10% |           2      0.20%      0.30% |           2      0.20%      0.51% |           2      0.20%      0.71% |           2      0.20%      0.91% |           2      0.20%      1.12% |           2      0.20%      1.32% |          63      6.40%      7.72% |         909     92.28%    100.00% |           0      0.00%    100.00%
+system.ruby.outstanding_req_hist::total           985                      
 system.ruby.latency_hist::bucket_size            1024                      
 system.ruby.latency_hist::max_bucket            10239                      
-system.ruby.latency_hist::samples                 992                      
-system.ruby.latency_hist::mean            3579.074597                      
-system.ruby.latency_hist::gmean           1947.833541                      
-system.ruby.latency_hist::stdev           1577.291313                      
-system.ruby.latency_hist                 |         164     16.53%     16.53% |           5      0.50%     17.04% |           9      0.91%     17.94% |         298     30.04%     47.98% |         470     47.38%     95.36% |          46      4.64%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.latency_hist::total                   992                      
+system.ruby.latency_hist::samples                 969                      
+system.ruby.latency_hist::mean            3745.879257                      
+system.ruby.latency_hist::gmean           2201.717205                      
+system.ruby.latency_hist::stdev           1540.597184                      
+system.ruby.latency_hist                 |         143     14.76%     14.76% |           5      0.52%     15.27% |           8      0.83%     16.10% |         232     23.94%     40.04% |         512     52.84%     92.88% |          69      7.12%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.latency_hist::total                   969                      
 system.ruby.hit_latency_hist::bucket_size         1024                      
 system.ruby.hit_latency_hist::max_bucket        10239                      
-system.ruby.hit_latency_hist::samples             126                      
-system.ruby.hit_latency_hist::mean         988.373016                      
-system.ruby.hit_latency_hist::gmean         33.259483                      
-system.ruby.hit_latency_hist::stdev       1726.172973                      
-system.ruby.hit_latency_hist             |          99     78.57%     78.57% |           0      0.00%     78.57% |           0      0.00%     78.57% |          12      9.52%     88.10% |          13     10.32%     98.41% |           2      1.59%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.hit_latency_hist::total               126                      
+system.ruby.hit_latency_hist::samples             109                      
+system.ruby.hit_latency_hist::mean               1139                      
+system.ruby.hit_latency_hist::gmean         39.996322                      
+system.ruby.hit_latency_hist::stdev       1803.950983                      
+system.ruby.hit_latency_hist             |          82     75.23%     75.23% |           0      0.00%     75.23% |           0      0.00%     75.23% |          12     11.01%     86.24% |          14     12.84%     99.08% |           1      0.92%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.hit_latency_hist::total               109                      
 system.ruby.miss_latency_hist::bucket_size         1024                      
 system.ruby.miss_latency_hist::max_bucket        10239                      
-system.ruby.miss_latency_hist::samples            866                      
-system.ruby.miss_latency_hist::mean       3956.012702                      
-system.ruby.miss_latency_hist::gmean      3521.573885                      
-system.ruby.miss_latency_hist::stdev      1140.061981                      
-system.ruby.miss_latency_hist            |          65      7.51%      7.51% |           5      0.58%      8.08% |           9      1.04%      9.12% |         286     33.03%     42.15% |         457     52.77%     94.92% |          44      5.08%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.miss_latency_hist::total              866                      
-system.ruby.Directory.incomplete_times            866                      
-system.ruby.l1_cntrl0.L1Dcache.demand_hits           82                       # Number of cache demand hits
-system.ruby.l1_cntrl0.L1Dcache.demand_misses          864                       # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Dcache.demand_accesses          946                       # Number of cache demand accesses
-system.ruby.l1_cntrl0.L1Icache.demand_hits            0                       # Number of cache demand hits
-system.ruby.l1_cntrl0.L1Icache.demand_misses           47                       # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Icache.demand_accesses           47                       # Number of cache demand accesses
+system.ruby.miss_latency_hist::samples            860                      
+system.ruby.miss_latency_hist::mean       4076.286047                      
+system.ruby.miss_latency_hist::gmean      3659.235822                      
+system.ruby.miss_latency_hist::stdev      1137.467741                      
+system.ruby.miss_latency_hist            |          61      7.09%      7.09% |           5      0.58%      7.67% |           8      0.93%      8.60% |         220     25.58%     34.19% |         498     57.91%     92.09% |          68      7.91%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.miss_latency_hist::total              860                      
+system.ruby.Directory.incomplete_times            860                      
+system.ruby.l1_cntrl0.L1Dcache.demand_hits           65                       # Number of cache demand hits
+system.ruby.l1_cntrl0.L1Dcache.demand_misses          858                       # Number of cache demand misses
+system.ruby.l1_cntrl0.L1Dcache.demand_accesses          923                       # Number of cache demand accesses
+system.ruby.l1_cntrl0.L1Icache.demand_hits            1                       # Number of cache demand hits
+system.ruby.l1_cntrl0.L1Icache.demand_misses           48                       # Number of cache demand misses
+system.ruby.l1_cntrl0.L1Icache.demand_accesses           49                       # Number of cache demand accesses
 system.ruby.l1_cntrl0.sequencer.store_waiting_on_load           10                       # Number of times a store aliased with a pending load
-system.ruby.l1_cntrl0.sequencer.store_waiting_on_store           87                       # Number of times a store aliased with a pending store
-system.ruby.l1_cntrl0.sequencer.load_waiting_on_store            6                       # Number of times a load aliased with a pending store
-system.ruby.l1_cntrl0.sequencer.load_waiting_on_load            1                       # Number of times a load aliased with a pending load
-system.ruby.network.routers0.percent_links_utilized     2.173860                      
-system.ruby.network.routers0.msg_count.Request_Control::1          911                      
-system.ruby.network.routers0.msg_count.Response_Data::4          925                      
-system.ruby.network.routers0.msg_count.ResponseL2hit_Data::4           40                      
-system.ruby.network.routers0.msg_count.Response_Control::4            1                      
-system.ruby.network.routers0.msg_count.Writeback_Data::4         1026                      
-system.ruby.network.routers0.msg_count.Persistent_Control::3          746                      
-system.ruby.network.routers0.msg_bytes.Request_Control::1         7288                      
-system.ruby.network.routers0.msg_bytes.Response_Data::4        66600                      
-system.ruby.network.routers0.msg_bytes.ResponseL2hit_Data::4         2880                      
-system.ruby.network.routers0.msg_bytes.Response_Control::4            8                      
-system.ruby.network.routers0.msg_bytes.Writeback_Data::4        73872                      
-system.ruby.network.routers0.msg_bytes.Persistent_Control::3         5968                      
-system.ruby.l2_cntrl0.L2cache.demand_hits           39                       # Number of cache demand hits
-system.ruby.l2_cntrl0.L2cache.demand_misses          872                       # Number of cache demand misses
-system.ruby.l2_cntrl0.L2cache.demand_accesses          911                       # Number of cache demand accesses
-system.ruby.network.routers1.percent_links_utilized     1.983424                      
-system.ruby.network.routers1.msg_count.Request_Control::1          911                      
-system.ruby.network.routers1.msg_count.Request_Control::2          872                      
-system.ruby.network.routers1.msg_count.Response_Data::4           28                      
-system.ruby.network.routers1.msg_count.ResponseL2hit_Data::4           40                      
-system.ruby.network.routers1.msg_count.Response_Control::4            1                      
-system.ruby.network.routers1.msg_count.Writeback_Data::4         1669                      
-system.ruby.network.routers1.msg_count.Writeback_Control::4           72                      
-system.ruby.network.routers1.msg_count.Persistent_Control::3          373                      
-system.ruby.network.routers1.msg_bytes.Request_Control::1         7288                      
-system.ruby.network.routers1.msg_bytes.Request_Control::2         6976                      
-system.ruby.network.routers1.msg_bytes.Response_Data::4         2016                      
-system.ruby.network.routers1.msg_bytes.ResponseL2hit_Data::4         2880                      
-system.ruby.network.routers1.msg_bytes.Response_Control::4            8                      
-system.ruby.network.routers1.msg_bytes.Writeback_Data::4       120168                      
-system.ruby.network.routers1.msg_bytes.Writeback_Control::4          576                      
-system.ruby.network.routers1.msg_bytes.Persistent_Control::3         2984                      
+system.ruby.l1_cntrl0.sequencer.store_waiting_on_store           96                       # Number of times a store aliased with a pending store
+system.ruby.l1_cntrl0.sequencer.load_waiting_on_store            2                       # Number of times a load aliased with a pending store
+system.ruby.l1_cntrl0.sequencer.load_waiting_on_load            3                       # Number of times a load aliased with a pending load
+system.ruby.network.routers0.percent_links_utilized     2.057604                      
+system.ruby.network.routers0.msg_count.Request_Control::1          906                      
+system.ruby.network.routers0.msg_count.Response_Data::4          885                      
+system.ruby.network.routers0.msg_count.ResponseL2hit_Data::4           39                      
+system.ruby.network.routers0.msg_count.Writeback_Data::4         1007                      
+system.ruby.network.routers0.msg_count.Persistent_Control::3          608                      
+system.ruby.network.routers0.msg_bytes.Request_Control::1         7248                      
+system.ruby.network.routers0.msg_bytes.Response_Data::4        63720                      
+system.ruby.network.routers0.msg_bytes.ResponseL2hit_Data::4         2808                      
+system.ruby.network.routers0.msg_bytes.Writeback_Data::4        72504                      
+system.ruby.network.routers0.msg_bytes.Persistent_Control::3         4864                      
+system.ruby.l2_cntrl0.L2cache.demand_hits           38                       # Number of cache demand hits
+system.ruby.l2_cntrl0.L2cache.demand_misses          866                       # Number of cache demand misses
+system.ruby.l2_cntrl0.L2cache.demand_accesses          904                       # Number of cache demand accesses
+system.ruby.network.routers1.percent_links_utilized     1.916676                      
+system.ruby.network.routers1.msg_count.Request_Control::1          904                      
+system.ruby.network.routers1.msg_count.Request_Control::2          866                      
+system.ruby.network.routers1.msg_count.Response_Data::4           15                      
+system.ruby.network.routers1.msg_count.ResponseL2hit_Data::4           39                      
+system.ruby.network.routers1.msg_count.Writeback_Data::4         1663                      
+system.ruby.network.routers1.msg_count.Writeback_Control::4           80                      
+system.ruby.network.routers1.msg_count.Persistent_Control::3          301                      
+system.ruby.network.routers1.msg_bytes.Request_Control::1         7232                      
+system.ruby.network.routers1.msg_bytes.Request_Control::2         6928                      
+system.ruby.network.routers1.msg_bytes.Response_Data::4         1080                      
+system.ruby.network.routers1.msg_bytes.ResponseL2hit_Data::4         2808                      
+system.ruby.network.routers1.msg_bytes.Writeback_Data::4       119736                      
+system.ruby.network.routers1.msg_bytes.Writeback_Control::4          640                      
+system.ruby.network.routers1.msg_bytes.Persistent_Control::3         2408                      
 system.ruby.memctrl_clk_domain.clock                3                       # Clock period in ticks
-system.ruby.dir_cntrl0.memBuffer.memReq          1655                       # Total number of memory requests
-system.ruby.dir_cntrl0.memBuffer.memRead          868                       # Number of memory reads
-system.ruby.dir_cntrl0.memBuffer.memWrite          787                       # Number of memory writes
-system.ruby.dir_cntrl0.memBuffer.memRefresh         1564                       # Number of memory refreshes
-system.ruby.dir_cntrl0.memBuffer.memWaitCycles          469                       # Delay stalled at the head of the bank queue
-system.ruby.dir_cntrl0.memBuffer.memInputQ           34                       # Delay in the input queue
-system.ruby.dir_cntrl0.memBuffer.totalStalls          503                       # Total number of stall cycles
-system.ruby.dir_cntrl0.memBuffer.stallsPerReq     0.303927                       # Expected number of stall cycles per request
-system.ruby.dir_cntrl0.memBuffer.memBankBusy          134                       # memory stalls due to busy bank
-system.ruby.dir_cntrl0.memBuffer.memBusBusy          192                       # memory stalls due to busy bus
-system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy           48                       # memory stalls due to read write turnaround
+system.ruby.dir_cntrl0.memBuffer.memReq          1634                       # Total number of memory requests
+system.ruby.dir_cntrl0.memBuffer.memRead          861                       # Number of memory reads
+system.ruby.dir_cntrl0.memBuffer.memWrite          773                       # Number of memory writes
+system.ruby.dir_cntrl0.memBuffer.memRefresh         1593                       # Number of memory refreshes
+system.ruby.dir_cntrl0.memBuffer.memWaitCycles          544                       # Delay stalled at the head of the bank queue
+system.ruby.dir_cntrl0.memBuffer.memInputQ           45                       # Delay in the input queue
+system.ruby.dir_cntrl0.memBuffer.memBankQ            1                       # Delay behind the head of the bank queue
+system.ruby.dir_cntrl0.memBuffer.totalStalls          590                       # Total number of stall cycles
+system.ruby.dir_cntrl0.memBuffer.stallsPerReq     0.361077                       # Expected number of stall cycles per request
+system.ruby.dir_cntrl0.memBuffer.memBankBusy          168                       # memory stalls due to busy bank
+system.ruby.dir_cntrl0.memBuffer.memBusBusy          199                       # memory stalls due to busy bus
+system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy           85                       # memory stalls due to read write turnaround
 system.ruby.dir_cntrl0.memBuffer.memDataBusBusy           56                       # memory stalls due to read read turnaround
-system.ruby.dir_cntrl0.memBuffer.memArbWait           39                       # memory stalls due to arbitration
-system.ruby.dir_cntrl0.memBuffer.memBankCount |          51      3.08%      3.08% |          47      2.84%      5.92% |          34      2.05%      7.98% |          94      5.68%     13.66% |          74      4.47%     18.13% |          59      3.56%     21.69% |          55      3.32%     25.02% |          45      2.72%     27.73% |          53      3.20%     30.94% |          55      3.32%     34.26% |          62      3.75%     38.01% |          49      2.96%     40.97% |          52      3.14%     44.11% |          51      3.08%     47.19% |          44      2.66%     49.85% |          57      3.44%     53.29% |          49      2.96%     56.25% |          51      3.08%     59.34% |          46      2.78%     62.11% |          44      2.66%     64.77% |          46      2.78%     67.55% |          41      2.48%     70.03% |          54      3.26%     73.29% |          56      3.38%     76.68% |          46      2.78%     79.46% |          55      3.32%     82.78% |          50      3.02%     85.80% |          43      2.60%     88.40% |          43      2.60%     91.00% |          47      2.84%     93.84% |          62      3.75%     97.58% |          40      2.42%    100.00% # Number of accesses per bank
-system.ruby.dir_cntrl0.memBuffer.memBankCount::total         1655                       # Number of accesses per bank
-system.ruby.network.routers2.percent_links_utilized     1.823191                      
-system.ruby.network.routers2.msg_count.Request_Control::2          872                      
-system.ruby.network.routers2.msg_count.Response_Data::4          897                      
-system.ruby.network.routers2.msg_count.Writeback_Data::4          781                      
-system.ruby.network.routers2.msg_count.Writeback_Control::4           72                      
-system.ruby.network.routers2.msg_count.Persistent_Control::3          373                      
-system.ruby.network.routers2.msg_bytes.Request_Control::2         6976                      
-system.ruby.network.routers2.msg_bytes.Response_Data::4        64584                      
-system.ruby.network.routers2.msg_bytes.Writeback_Data::4        56232                      
-system.ruby.network.routers2.msg_bytes.Writeback_Control::4          576                      
-system.ruby.network.routers2.msg_bytes.Persistent_Control::3         2984                      
-system.ruby.network.routers3.percent_links_utilized     1.993491                      
-system.ruby.network.routers3.msg_count.Request_Control::1          911                      
-system.ruby.network.routers3.msg_count.Request_Control::2          872                      
-system.ruby.network.routers3.msg_count.Response_Data::4          925                      
-system.ruby.network.routers3.msg_count.ResponseL2hit_Data::4           40                      
-system.ruby.network.routers3.msg_count.Response_Control::4            1                      
-system.ruby.network.routers3.msg_count.Writeback_Data::4         1738                      
-system.ruby.network.routers3.msg_count.Writeback_Control::4           72                      
-system.ruby.network.routers3.msg_count.Persistent_Control::3          746                      
-system.ruby.network.routers3.msg_bytes.Request_Control::1         7288                      
-system.ruby.network.routers3.msg_bytes.Request_Control::2         6976                      
-system.ruby.network.routers3.msg_bytes.Response_Data::4        66600                      
-system.ruby.network.routers3.msg_bytes.ResponseL2hit_Data::4         2880                      
-system.ruby.network.routers3.msg_bytes.Response_Control::4            8                      
-system.ruby.network.routers3.msg_bytes.Writeback_Data::4       125136                      
-system.ruby.network.routers3.msg_bytes.Writeback_Control::4          576                      
-system.ruby.network.routers3.msg_bytes.Persistent_Control::3         5968                      
-system.ruby.network.msg_count.Request_Control         5349                      
-system.ruby.network.msg_count.Response_Data         2775                      
-system.ruby.network.msg_count.ResponseL2hit_Data          120                      
-system.ruby.network.msg_count.Response_Control            3                      
-system.ruby.network.msg_count.Writeback_Data         5214                      
-system.ruby.network.msg_count.Writeback_Control          216                      
-system.ruby.network.msg_count.Persistent_Control         2238                      
-system.ruby.network.msg_byte.Request_Control        42792                      
-system.ruby.network.msg_byte.Response_Data       199800                      
-system.ruby.network.msg_byte.ResponseL2hit_Data         8640                      
-system.ruby.network.msg_byte.Response_Control           24                      
-system.ruby.network.msg_byte.Writeback_Data       375408                      
-system.ruby.network.msg_byte.Writeback_Control         1728                      
-system.ruby.network.msg_byte.Persistent_Control        17904                      
-system.ruby.network.routers0.throttle0.link_utilization     2.077809                      
-system.ruby.network.routers0.throttle0.msg_count.Response_Data::4          898                      
-system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::4           40                      
-system.ruby.network.routers0.throttle0.msg_count.Response_Control::4            1                      
-system.ruby.network.routers0.throttle0.msg_count.Writeback_Data::4           60                      
-system.ruby.network.routers0.throttle0.msg_count.Persistent_Control::3          373                      
-system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4        64656                      
-system.ruby.network.routers0.throttle0.msg_bytes.ResponseL2hit_Data::4         2880                      
-system.ruby.network.routers0.throttle0.msg_bytes.Response_Control::4            8                      
-system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Data::4         4320                      
-system.ruby.network.routers0.throttle0.msg_bytes.Persistent_Control::3         2984                      
-system.ruby.network.routers0.throttle1.link_utilization     2.269911                      
-system.ruby.network.routers0.throttle1.msg_count.Request_Control::1          911                      
-system.ruby.network.routers0.throttle1.msg_count.Response_Data::4           27                      
-system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::4          966                      
-system.ruby.network.routers0.throttle1.msg_count.Persistent_Control::3          373                      
-system.ruby.network.routers0.throttle1.msg_bytes.Request_Control::1         7288                      
-system.ruby.network.routers0.throttle1.msg_bytes.Response_Data::4         1944                      
-system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::4        69552                      
-system.ruby.network.routers0.throttle1.msg_bytes.Persistent_Control::3         2984                      
-system.ruby.network.routers1.throttle0.link_utilization     2.096020                      
-system.ruby.network.routers1.throttle0.msg_count.Request_Control::1          911                      
-system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::4          906                      
-system.ruby.network.routers1.throttle0.msg_count.Persistent_Control::3          373                      
-system.ruby.network.routers1.throttle0.msg_bytes.Request_Control::1         7288                      
-system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::4        65232                      
-system.ruby.network.routers1.throttle0.msg_bytes.Persistent_Control::3         2984                      
-system.ruby.network.routers1.throttle1.link_utilization     1.870828                      
-system.ruby.network.routers1.throttle1.msg_count.Request_Control::2          872                      
-system.ruby.network.routers1.throttle1.msg_count.Response_Data::4           28                      
-system.ruby.network.routers1.throttle1.msg_count.ResponseL2hit_Data::4           40                      
-system.ruby.network.routers1.throttle1.msg_count.Response_Control::4            1                      
-system.ruby.network.routers1.throttle1.msg_count.Writeback_Data::4          763                      
-system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::4           72                      
-system.ruby.network.routers1.throttle1.msg_bytes.Request_Control::2         6976                      
-system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4         2016                      
-system.ruby.network.routers1.throttle1.msg_bytes.ResponseL2hit_Data::4         2880                      
-system.ruby.network.routers1.throttle1.msg_bytes.Response_Control::4            8                      
-system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::4        54936                      
-system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::4          576                      
-system.ruby.network.routers2.throttle0.link_utilization     1.889483                      
-system.ruby.network.routers2.throttle0.msg_count.Request_Control::2          872                      
-system.ruby.network.routers2.throttle0.msg_count.Response_Data::4           27                      
-system.ruby.network.routers2.throttle0.msg_count.Writeback_Data::4          772                      
-system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::4           72                      
-system.ruby.network.routers2.throttle0.msg_count.Persistent_Control::3          373                      
-system.ruby.network.routers2.throttle0.msg_bytes.Request_Control::2         6976                      
-system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4         1944                      
-system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Data::4        55584                      
-system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::4          576                      
-system.ruby.network.routers2.throttle0.msg_bytes.Persistent_Control::3         2984                      
-system.ruby.network.routers2.throttle1.link_utilization     1.756899                      
-system.ruby.network.routers2.throttle1.msg_count.Response_Data::4          870                      
-system.ruby.network.routers2.throttle1.msg_count.Writeback_Data::4            9                      
-system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::4        62640                      
-system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Data::4          648                      
-system.ruby.network.routers3.throttle0.link_utilization     1.994972                      
-system.ruby.network.routers3.throttle0.msg_count.Response_Data::4          898                      
-system.ruby.network.routers3.throttle0.msg_count.ResponseL2hit_Data::4           40                      
-system.ruby.network.routers3.throttle0.msg_count.Response_Control::4            1                      
-system.ruby.network.routers3.throttle0.msg_count.Writeback_Data::4           60                      
-system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::4        64656                      
-system.ruby.network.routers3.throttle0.msg_bytes.ResponseL2hit_Data::4         2880                      
-system.ruby.network.routers3.throttle0.msg_bytes.Response_Control::4            8                      
-system.ruby.network.routers3.throttle0.msg_bytes.Writeback_Data::4         4320                      
-system.ruby.network.routers3.throttle1.link_utilization     2.096020                      
-system.ruby.network.routers3.throttle1.msg_count.Request_Control::1          911                      
-system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::4          906                      
-system.ruby.network.routers3.throttle1.msg_count.Persistent_Control::3          373                      
-system.ruby.network.routers3.throttle1.msg_bytes.Request_Control::1         7288                      
-system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::4        65232                      
-system.ruby.network.routers3.throttle1.msg_bytes.Persistent_Control::3         2984                      
-system.ruby.network.routers3.throttle2.link_utilization     1.889483                      
-system.ruby.network.routers3.throttle2.msg_count.Request_Control::2          872                      
-system.ruby.network.routers3.throttle2.msg_count.Response_Data::4           27                      
-system.ruby.network.routers3.throttle2.msg_count.Writeback_Data::4          772                      
-system.ruby.network.routers3.throttle2.msg_count.Writeback_Control::4           72                      
-system.ruby.network.routers3.throttle2.msg_count.Persistent_Control::3          373                      
-system.ruby.network.routers3.throttle2.msg_bytes.Request_Control::2         6976                      
-system.ruby.network.routers3.throttle2.msg_bytes.Response_Data::4         1944                      
-system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Data::4        55584                      
-system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Control::4          576                      
-system.ruby.network.routers3.throttle2.msg_bytes.Persistent_Control::3         2984                      
+system.ruby.dir_cntrl0.memBuffer.memArbWait           36                       # memory stalls due to arbitration
+system.ruby.dir_cntrl0.memBuffer.memBankCount |          45      2.75%      2.75% |          38      2.33%      5.08% |          48      2.94%      8.02% |         106      6.49%     14.50% |          75      4.59%     19.09% |          81      4.96%     24.05% |          55      3.37%     27.42% |          64      3.92%     31.33% |          51      3.12%     34.46% |          56      3.43%     37.88% |          37      2.26%     40.15% |          37      2.26%     42.41% |          56      3.43%     45.84% |          37      2.26%     48.10% |          48      2.94%     51.04% |          54      3.30%     54.35% |          44      2.69%     57.04% |          44      2.69%     59.73% |          44      2.69%     62.42% |          38      2.33%     64.75% |          55      3.37%     68.12% |          45      2.75%     70.87% |          57      3.49%     74.36% |          42      2.57%     76.93% |          41      2.51%     79.44% |          50      3.06%     82.50% |          35      2.14%     84.64% |          53      3.24%     87.88% |          47      2.88%     90.76% |          50      3.06%     93.82% |          49      3.00%     96.82% |          52      3.18%    100.00% # Number of accesses per bank
+system.ruby.dir_cntrl0.memBuffer.memBankCount::total         1634                       # Number of accesses per bank
+system.ruby.network.routers2.percent_links_utilized     1.744384                      
+system.ruby.network.routers2.msg_count.Request_Control::2          865                      
+system.ruby.network.routers2.msg_count.Response_Data::4          870                      
+system.ruby.network.routers2.msg_count.Writeback_Data::4          771                      
+system.ruby.network.routers2.msg_count.Writeback_Control::4           80                      
+system.ruby.network.routers2.msg_count.Persistent_Control::3          303                      
+system.ruby.network.routers2.msg_bytes.Request_Control::2         6920                      
+system.ruby.network.routers2.msg_bytes.Response_Data::4        62640                      
+system.ruby.network.routers2.msg_bytes.Writeback_Data::4        55512                      
+system.ruby.network.routers2.msg_bytes.Writeback_Control::4          640                      
+system.ruby.network.routers2.msg_bytes.Persistent_Control::3         2424                      
+system.ruby.network.routers3.percent_links_utilized     1.906766                      
+system.ruby.network.routers3.msg_count.Request_Control::1          905                      
+system.ruby.network.routers3.msg_count.Request_Control::2          865                      
+system.ruby.network.routers3.msg_count.Response_Data::4          885                      
+system.ruby.network.routers3.msg_count.ResponseL2hit_Data::4           39                      
+system.ruby.network.routers3.msg_count.Writeback_Data::4         1721                      
+system.ruby.network.routers3.msg_count.Writeback_Control::4           80                      
+system.ruby.network.routers3.msg_count.Persistent_Control::3          607                      
+system.ruby.network.routers3.msg_bytes.Request_Control::1         7240                      
+system.ruby.network.routers3.msg_bytes.Request_Control::2         6920                      
+system.ruby.network.routers3.msg_bytes.Response_Data::4        63720                      
+system.ruby.network.routers3.msg_bytes.ResponseL2hit_Data::4         2808                      
+system.ruby.network.routers3.msg_bytes.Writeback_Data::4       123912                      
+system.ruby.network.routers3.msg_bytes.Writeback_Control::4          640                      
+system.ruby.network.routers3.msg_bytes.Persistent_Control::3         4856                      
+system.ruby.network.msg_count.Request_Control         5311                      
+system.ruby.network.msg_count.Response_Data         2655                      
+system.ruby.network.msg_count.ResponseL2hit_Data          117                      
+system.ruby.network.msg_count.Writeback_Data         5162                      
+system.ruby.network.msg_count.Writeback_Control          240                      
+system.ruby.network.msg_count.Persistent_Control         1819                      
+system.ruby.network.msg_byte.Request_Control        42488                      
+system.ruby.network.msg_byte.Response_Data       191160                      
+system.ruby.network.msg_byte.ResponseL2hit_Data         8424                      
+system.ruby.network.msg_byte.Writeback_Data       371664                      
+system.ruby.network.msg_byte.Writeback_Control         1920                      
+system.ruby.network.msg_byte.Persistent_Control        14552                      
+system.ruby.network.routers0.throttle0.link_utilization     1.963834                      
+system.ruby.network.routers0.throttle0.msg_count.Response_Data::4          875                      
+system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::4           39                      
+system.ruby.network.routers0.throttle0.msg_count.Writeback_Data::4           54                      
+system.ruby.network.routers0.throttle0.msg_count.Persistent_Control::3          304                      
+system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4        63000                      
+system.ruby.network.routers0.throttle0.msg_bytes.ResponseL2hit_Data::4         2808                      
+system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Data::4         3888                      
+system.ruby.network.routers0.throttle0.msg_bytes.Persistent_Control::3         2432                      
+system.ruby.network.routers0.throttle1.link_utilization     2.151374                      
+system.ruby.network.routers0.throttle1.msg_count.Request_Control::1          906                      
+system.ruby.network.routers0.throttle1.msg_count.Response_Data::4           10                      
+system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::4          953                      
+system.ruby.network.routers0.throttle1.msg_count.Persistent_Control::3          304                      
+system.ruby.network.routers0.throttle1.msg_bytes.Request_Control::1         7248                      
+system.ruby.network.routers0.throttle1.msg_bytes.Response_Data::4          720                      
+system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::4        68616                      
+system.ruby.network.routers0.throttle1.msg_bytes.Persistent_Control::3         2432                      
+system.ruby.network.routers1.throttle0.link_utilization     2.023733                      
+system.ruby.network.routers1.throttle0.msg_count.Request_Control::1          904                      
+system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::4          899                      
+system.ruby.network.routers1.throttle0.msg_count.Persistent_Control::3          301                      
+system.ruby.network.routers1.throttle0.msg_bytes.Request_Control::1         7232                      
+system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::4        64728                      
+system.ruby.network.routers1.throttle0.msg_bytes.Persistent_Control::3         2408                      
+system.ruby.network.routers1.throttle1.link_utilization     1.809620                      
+system.ruby.network.routers1.throttle1.msg_count.Request_Control::2          866                      
+system.ruby.network.routers1.throttle1.msg_count.Response_Data::4           15                      
+system.ruby.network.routers1.throttle1.msg_count.ResponseL2hit_Data::4           39                      
+system.ruby.network.routers1.throttle1.msg_count.Writeback_Data::4          764                      
+system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::4           80                      
+system.ruby.network.routers1.throttle1.msg_bytes.Request_Control::2         6928                      
+system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4         1080                      
+system.ruby.network.routers1.throttle1.msg_bytes.ResponseL2hit_Data::4         2808                      
+system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::4        55008                      
+system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::4          640                      
+system.ruby.network.routers2.throttle0.link_utilization     1.795026                      
+system.ruby.network.routers2.throttle0.msg_count.Request_Control::2          865                      
+system.ruby.network.routers2.throttle0.msg_count.Response_Data::4           10                      
+system.ruby.network.routers2.throttle0.msg_count.Writeback_Data::4          767                      
+system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::4           80                      
+system.ruby.network.routers2.throttle0.msg_count.Persistent_Control::3          303                      
+system.ruby.network.routers2.throttle0.msg_bytes.Request_Control::2         6920                      
+system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4          720                      
+system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Data::4        55224                      
+system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::4          640                      
+system.ruby.network.routers2.throttle0.msg_bytes.Persistent_Control::3         2424                      
+system.ruby.network.routers2.throttle1.link_utilization     1.693741                      
+system.ruby.network.routers2.throttle1.msg_count.Response_Data::4          860                      
+system.ruby.network.routers2.throttle1.msg_count.Writeback_Data::4            4                      
+system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::4        61920                      
+system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Data::4          288                      
+system.ruby.network.routers3.throttle0.link_utilization     1.897618                      
+system.ruby.network.routers3.throttle0.msg_count.Response_Data::4          875                      
+system.ruby.network.routers3.throttle0.msg_count.ResponseL2hit_Data::4           39                      
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+system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::4        63000                      
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+system.ruby.network.routers3.throttle0.msg_bytes.Writeback_Data::4         3888                      
+system.ruby.network.routers3.throttle1.link_utilization     2.025476                      
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+system.ruby.network.routers3.throttle1.msg_bytes.Request_Control::1         7240                      
+system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::4        64728                      
+system.ruby.network.routers3.throttle1.msg_bytes.Persistent_Control::3         2424                      
+system.ruby.network.routers3.throttle2.link_utilization     1.797204                      
+system.ruby.network.routers3.throttle2.msg_count.Request_Control::2          865                      
+system.ruby.network.routers3.throttle2.msg_count.Response_Data::4           10                      
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+system.ruby.network.routers3.throttle2.msg_bytes.Persistent_Control::3         2432                      
 system.ruby.LD.latency_hist::bucket_size         1024                      
 system.ruby.LD.latency_hist::max_bucket         10239                      
-system.ruby.LD.latency_hist::samples               53                      
-system.ruby.LD.latency_hist::mean         3847.981132                      
-system.ruby.LD.latency_hist::gmean        2117.840098                      
-system.ruby.LD.latency_hist::stdev        1453.914034                      
-system.ruby.LD.latency_hist              |           6     11.32%     11.32% |           0      0.00%     11.32% |           1      1.89%     13.21% |          15     28.30%     41.51% |          26     49.06%     90.57% |           5      9.43%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.LD.latency_hist::total                 53                      
+system.ruby.LD.latency_hist::samples               52                      
+system.ruby.LD.latency_hist::mean         4084.307692                      
+system.ruby.LD.latency_hist::gmean        2925.833819                      
+system.ruby.LD.latency_hist::stdev        1345.909453                      
+system.ruby.LD.latency_hist              |           5      9.62%      9.62% |           0      0.00%      9.62% |           0      0.00%      9.62% |           7     13.46%     23.08% |          34     65.38%     88.46% |           6     11.54%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.latency_hist::total                 52                      
 system.ruby.LD.hit_latency_hist::bucket_size          512                      
 system.ruby.LD.hit_latency_hist::max_bucket         5119                      
-system.ruby.LD.hit_latency_hist::samples            7                      
-system.ruby.LD.hit_latency_hist::mean     1354.142857                      
-system.ruby.LD.hit_latency_hist::gmean      28.155273                      
-system.ruby.LD.hit_latency_hist::stdev    2279.826048                      
-system.ruby.LD.hit_latency_hist          |           5     71.43%     71.43% |           0      0.00%     71.43% |           0      0.00%     71.43% |           0      0.00%     71.43% |           0      0.00%     71.43% |           0      0.00%     71.43% |           0      0.00%     71.43% |           0      0.00%     71.43% |           1     14.29%     85.71% |           1     14.29%    100.00%
-system.ruby.LD.hit_latency_hist::total              7                      
+system.ruby.LD.hit_latency_hist::samples            5                      
+system.ruby.LD.hit_latency_hist::mean      997.400000                      
+system.ruby.LD.hit_latency_hist::gmean      89.277594                      
+system.ruby.LD.hit_latency_hist::stdev    1774.639344                      
+system.ruby.LD.hit_latency_hist          |           4     80.00%     80.00% |           0      0.00%     80.00% |           0      0.00%     80.00% |           0      0.00%     80.00% |           0      0.00%     80.00% |           0      0.00%     80.00% |           0      0.00%     80.00% |           0      0.00%     80.00% |           1     20.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.hit_latency_hist::total              5                      
 system.ruby.LD.miss_latency_hist::bucket_size         1024                      
 system.ruby.LD.miss_latency_hist::max_bucket        10239                      
-system.ruby.LD.miss_latency_hist::samples           46                      
-system.ruby.LD.miss_latency_hist::mean    4227.478261                      
-system.ruby.LD.miss_latency_hist::gmean   4087.164963                      
-system.ruby.LD.miss_latency_hist::stdev    796.882195                      
-system.ruby.LD.miss_latency_hist         |           1      2.17%      2.17% |           0      0.00%      2.17% |           1      2.17%      4.35% |          15     32.61%     36.96% |          24     52.17%     89.13% |           5     10.87%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.LD.miss_latency_hist::total            46                      
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+system.ruby.LD.miss_latency_hist::mean    4412.702128                      
+system.ruby.LD.miss_latency_hist::gmean   4241.054205                      
+system.ruby.LD.miss_latency_hist::stdev    767.181372                      
+system.ruby.LD.miss_latency_hist         |           1      2.13%      2.13% |           0      0.00%      2.13% |           0      0.00%      2.13% |           7     14.89%     17.02% |          33     70.21%     87.23% |           6     12.77%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.miss_latency_hist::total            47                      
 system.ruby.ST.latency_hist::bucket_size         1024                      
 system.ruby.ST.latency_hist::max_bucket         10239                      
-system.ruby.ST.latency_hist::samples              892                      
-system.ruby.ST.latency_hist::mean         3728.136771                      
-system.ruby.ST.latency_hist::gmean        2108.403124                      
-system.ruby.ST.latency_hist::stdev        1448.246319                      
-system.ruby.ST.latency_hist              |         111     12.44%     12.44% |           5      0.56%     13.00% |           8      0.90%     13.90% |         283     31.73%     45.63% |         444     49.78%     95.40% |          41      4.60%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.ST.latency_hist::total                892                      
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+system.ruby.ST.latency_hist::gmean        2393.585593                      
+system.ruby.ST.latency_hist::stdev        1376.670697                      
+system.ruby.ST.latency_hist              |          90     10.36%     10.36% |           5      0.58%     10.93% |           8      0.92%     11.85% |         225     25.89%     37.74% |         478     55.01%     92.75% |          63      7.25%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.latency_hist::total                869                      
 system.ruby.ST.hit_latency_hist::bucket_size         1024                      
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-system.ruby.ST.hit_latency_hist::samples          114                      
-system.ruby.ST.hit_latency_hist::mean      981.052632                      
-system.ruby.ST.hit_latency_hist::gmean      29.537745                      
-system.ruby.ST.hit_latency_hist::stdev    1733.689885                      
-system.ruby.ST.hit_latency_hist          |          89     78.07%     78.07% |           0      0.00%     78.07% |           0      0.00%     78.07% |          12     10.53%     88.60% |          11      9.65%     98.25% |           2      1.75%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.ST.hit_latency_hist::total            114                      
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+system.ruby.ST.hit_latency_hist::stdev    1865.494830                      
+system.ruby.ST.hit_latency_hist          |          71     73.20%     73.20% |           0      0.00%     73.20% |           0      0.00%     73.20% |          12     12.37%     85.57% |          13     13.40%     98.97% |           1      1.03%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.hit_latency_hist::total             97                      
 system.ruby.ST.miss_latency_hist::bucket_size         1024                      
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-system.ruby.ST.miss_latency_hist::samples          778                      
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-system.ruby.ST.miss_latency_hist::gmean   3940.554861                      
-system.ruby.ST.miss_latency_hist::stdev    835.813724                      
-system.ruby.ST.miss_latency_hist         |          22      2.83%      2.83% |           5      0.64%      3.47% |           8      1.03%      4.50% |         271     34.83%     39.33% |         433     55.66%     94.99% |          39      5.01%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.ST.miss_latency_hist::total           778                      
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+system.ruby.ST.miss_latency_hist::stdev    812.787360                      
+system.ruby.ST.miss_latency_hist         |          19      2.46%      2.46% |           5      0.65%      3.11% |           8      1.04%      4.15% |         213     27.59%     31.74% |         465     60.23%     91.97% |          62      8.03%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.miss_latency_hist::total           772                      
 system.ruby.IFETCH.latency_hist::bucket_size          128                      
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-system.ruby.IFETCH.latency_hist::samples           47                      
-system.ruby.IFETCH.latency_hist::mean      446.829787                      
-system.ruby.IFETCH.latency_hist::gmean     394.156540                      
-system.ruby.IFETCH.latency_hist::stdev     206.945941                      
-system.ruby.IFETCH.latency_hist          |           2      4.26%      4.26% |          10     21.28%     25.53% |           6     12.77%     38.30% |           9     19.15%     57.45% |          10     21.28%     78.72% |           6     12.77%     91.49% |           4      8.51%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.IFETCH.latency_hist::total             47                      
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+system.ruby.IFETCH.latency_hist::gmean     356.475043                      
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+system.ruby.IFETCH.latency_hist          |           3      6.25%      6.25% |           4      8.33%     14.58% |          13     27.08%     41.67% |          11     22.92%     64.58% |          11     22.92%     87.50% |           5     10.42%     97.92% |           1      2.08%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.latency_hist::total             48                      
 system.ruby.IFETCH.hit_latency_hist::bucket_size          128                      
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-system.ruby.IFETCH.hit_latency_hist::gmean   628.468542                      
-system.ruby.IFETCH.hit_latency_hist::stdev   152.681695                      
-system.ruby.IFETCH.hit_latency_hist      |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           1     20.00%     20.00% |           1     20.00%     40.00% |           2     40.00%     80.00% |           1     20.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.IFETCH.hit_latency_hist::total            5                      
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+system.ruby.IFETCH.hit_latency_hist      |           1     14.29%     14.29% |           1     14.29%     28.57% |           2     28.57%     57.14% |           0      0.00%     57.14% |           1     14.29%     71.43% |           1     14.29%     85.71% |           1     14.29%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.hit_latency_hist::total            7                      
 system.ruby.IFETCH.miss_latency_hist::bucket_size          128                      
 system.ruby.IFETCH.miss_latency_hist::max_bucket         1279                      
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-system.ruby.IFETCH.miss_latency_hist::gmean   372.861830                      
-system.ruby.IFETCH.miss_latency_hist::stdev   201.277530                      
-system.ruby.IFETCH.miss_latency_hist     |           2      4.76%      4.76% |          10     23.81%     28.57% |           6     14.29%     42.86% |           8     19.05%     61.90% |           9     21.43%     83.33% |           4      9.52%     92.86% |           3      7.14%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.IFETCH.miss_latency_hist::total           42                      
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+system.ruby.IFETCH.miss_latency_hist::stdev   162.430015                      
+system.ruby.IFETCH.miss_latency_hist     |           2      4.88%      4.88% |           3      7.32%     12.20% |          11     26.83%     39.02% |          11     26.83%     65.85% |          10     24.39%     90.24% |           4      9.76%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.miss_latency_hist::total           41                      
 system.ruby.L1Cache.hit_mach_latency_hist::bucket_size           16                      
 system.ruby.L1Cache.hit_mach_latency_hist::max_bucket          159                      
-system.ruby.L1Cache.hit_mach_latency_hist::samples           82                      
-system.ruby.L1Cache.hit_mach_latency_hist::mean    18.256098                      
-system.ruby.L1Cache.hit_mach_latency_hist::gmean     3.930313                      
-system.ruby.L1Cache.hit_mach_latency_hist::stdev    38.332467                      
-system.ruby.L1Cache.hit_mach_latency_hist |          70     85.37%     85.37% |           0      0.00%     85.37% |           0      0.00%     85.37% |           0      0.00%     85.37% |           0      0.00%     85.37% |           0      0.00%     85.37% |           7      8.54%     93.90% |           5      6.10%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.L1Cache.hit_mach_latency_hist::total           82                      
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+system.ruby.L1Cache.hit_mach_latency_hist::stdev    33.303296                      
+system.ruby.L1Cache.hit_mach_latency_hist |          59     89.39%     89.39% |           0      0.00%     89.39% |           0      0.00%     89.39% |           0      0.00%     89.39% |           0      0.00%     89.39% |           0      0.00%     89.39% |           3      4.55%     93.94% |           4      6.06%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache.hit_mach_latency_hist::total           66                      
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 system.ruby.L2Cache.hit_mach_latency_hist::max_bucket        10239                      
-system.ruby.L2Cache.hit_mach_latency_hist::samples           44                      
-system.ruby.L2Cache.hit_mach_latency_hist::mean  2796.318182                      
-system.ruby.L2Cache.hit_mach_latency_hist::gmean  1779.985903                      
-system.ruby.L2Cache.hit_mach_latency_hist::stdev  1876.082197                      
-system.ruby.L2Cache.hit_mach_latency_hist |          17     38.64%     38.64% |           0      0.00%     38.64% |           0      0.00%     38.64% |          12     27.27%     65.91% |          13     29.55%     95.45% |           2      4.55%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.L2Cache.hit_mach_latency_hist::total           44                      
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+system.ruby.L2Cache.hit_mach_latency_hist::mean  2866.116279                      
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+system.ruby.L2Cache.hit_mach_latency_hist::stdev  1822.821364                      
+system.ruby.L2Cache.hit_mach_latency_hist |          16     37.21%     37.21% |           0      0.00%     37.21% |           0      0.00%     37.21% |          12     27.91%     65.12% |          14     32.56%     97.67% |           1      2.33%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.L2Cache.hit_mach_latency_hist::total           43                      
 system.ruby.Directory.miss_mach_latency_hist::bucket_size         1024                      
 system.ruby.Directory.miss_mach_latency_hist::max_bucket        10239                      
-system.ruby.Directory.miss_mach_latency_hist::samples          866                      
-system.ruby.Directory.miss_mach_latency_hist::mean  3956.012702                      
-system.ruby.Directory.miss_mach_latency_hist::gmean  3521.573885                      
-system.ruby.Directory.miss_mach_latency_hist::stdev  1140.061981                      
-system.ruby.Directory.miss_mach_latency_hist |          65      7.51%      7.51% |           5      0.58%      8.08% |           9      1.04%      9.12% |         286     33.03%     42.15% |         457     52.77%     94.92% |          44      5.08%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.Directory.miss_mach_latency_hist::total          866                      
-system.ruby.LD.L1Cache.hit_type_mach_latency_hist::bucket_size           16                      
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-system.ruby.LD.L1Cache.hit_type_mach_latency_hist::samples            5                      
-system.ruby.LD.L1Cache.hit_type_mach_latency_hist::mean    22.800000                      
-system.ruby.LD.L1Cache.hit_type_mach_latency_hist::gmean     3.643401                      
-system.ruby.LD.L1Cache.hit_type_mach_latency_hist::stdev    47.076533                      
-system.ruby.LD.L1Cache.hit_type_mach_latency_hist |           4     80.00%     80.00% |           0      0.00%     80.00% |           0      0.00%     80.00% |           0      0.00%     80.00% |           0      0.00%     80.00% |           0      0.00%     80.00% |           1     20.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.LD.L1Cache.hit_type_mach_latency_hist::total            5                      
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+system.ruby.Directory.miss_mach_latency_hist::gmean  3659.235822                      
+system.ruby.Directory.miss_mach_latency_hist::stdev  1137.467741                      
+system.ruby.Directory.miss_mach_latency_hist |          61      7.09%      7.09% |           5      0.58%      7.67% |           8      0.93%      8.60% |         220     25.58%     34.19% |         498     57.91%     92.09% |          68      7.91%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.Directory.miss_mach_latency_hist::total          860                      
+system.ruby.LD.L1Cache.hit_type_mach_latency_hist::bucket_size            1                      
+system.ruby.LD.L1Cache.hit_type_mach_latency_hist::max_bucket            9                      
+system.ruby.LD.L1Cache.hit_type_mach_latency_hist::samples            2                      
+system.ruby.LD.L1Cache.hit_type_mach_latency_hist::mean            3                      
+system.ruby.LD.L1Cache.hit_type_mach_latency_hist::gmean     2.828427                      
+system.ruby.LD.L1Cache.hit_type_mach_latency_hist::stdev     1.414214                      
+system.ruby.LD.L1Cache.hit_type_mach_latency_hist |           0      0.00%      0.00% |           0      0.00%      0.00% |           1     50.00%     50.00% |           0      0.00%     50.00% |           1     50.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.L1Cache.hit_type_mach_latency_hist::total            2                      
 system.ruby.LD.L2Cache.hit_type_mach_latency_hist::bucket_size          512                      
 system.ruby.LD.L2Cache.hit_type_mach_latency_hist::max_bucket         5119                      
-system.ruby.LD.L2Cache.hit_type_mach_latency_hist::samples            2                      
-system.ruby.LD.L2Cache.hit_type_mach_latency_hist::mean  4682.500000                      
-system.ruby.LD.L2Cache.hit_type_mach_latency_hist::gmean  4674.030809                      
-system.ruby.LD.L2Cache.hit_type_mach_latency_hist::stdev   398.101118                      
-system.ruby.LD.L2Cache.hit_type_mach_latency_hist |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           1     50.00%     50.00% |           1     50.00%    100.00%
-system.ruby.LD.L2Cache.hit_type_mach_latency_hist::total            2                      
+system.ruby.LD.L2Cache.hit_type_mach_latency_hist::samples            3                      
+system.ruby.LD.L2Cache.hit_type_mach_latency_hist::mean  1660.333333                      
+system.ruby.LD.L2Cache.hit_type_mach_latency_hist::gmean   891.676803                      
+system.ruby.LD.L2Cache.hit_type_mach_latency_hist::stdev  2156.533406                      
+system.ruby.LD.L2Cache.hit_type_mach_latency_hist |           2     66.67%     66.67% |           0      0.00%     66.67% |           0      0.00%     66.67% |           0      0.00%     66.67% |           0      0.00%     66.67% |           0      0.00%     66.67% |           0      0.00%     66.67% |           0      0.00%     66.67% |           1     33.33%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.L2Cache.hit_type_mach_latency_hist::total            3                      
 system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size         1024                      
 system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket        10239                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist::samples           46                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist::mean  4227.478261                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean  4087.164963                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev   796.882195                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist |           1      2.17%      2.17% |           0      0.00%      2.17% |           1      2.17%      4.35% |          15     32.61%     36.96% |          24     52.17%     89.13% |           5     10.87%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.LD.Directory.miss_type_mach_latency_hist::total           46                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist::samples           47                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist::mean  4412.702128                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean  4241.054205                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev   767.181372                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist |           1      2.13%      2.13% |           0      0.00%      2.13% |           0      0.00%      2.13% |           7     14.89%     17.02% |          33     70.21%     87.23% |           6     12.77%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.Directory.miss_type_mach_latency_hist::total           47                      
 system.ruby.ST.L1Cache.hit_type_mach_latency_hist::bucket_size           16                      
 system.ruby.ST.L1Cache.hit_type_mach_latency_hist::max_bucket          159                      
-system.ruby.ST.L1Cache.hit_type_mach_latency_hist::samples           77                      
-system.ruby.ST.L1Cache.hit_type_mach_latency_hist::mean    17.961039                      
-system.ruby.ST.L1Cache.hit_type_mach_latency_hist::gmean     3.949706                      
-system.ruby.ST.L1Cache.hit_type_mach_latency_hist::stdev    38.052056                      
-system.ruby.ST.L1Cache.hit_type_mach_latency_hist |          66     85.71%     85.71% |           0      0.00%     85.71% |           0      0.00%     85.71% |           0      0.00%     85.71% |           0      0.00%     85.71% |           0      0.00%     85.71% |           6      7.79%     93.51% |           5      6.49%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.ST.L1Cache.hit_type_mach_latency_hist::total           77                      
+system.ruby.ST.L1Cache.hit_type_mach_latency_hist::samples           63                      
+system.ruby.ST.L1Cache.hit_type_mach_latency_hist::mean    14.269841                      
+system.ruby.ST.L1Cache.hit_type_mach_latency_hist::gmean     3.210866                      
+system.ruby.ST.L1Cache.hit_type_mach_latency_hist::stdev    34.012904                      
+system.ruby.ST.L1Cache.hit_type_mach_latency_hist |          56     88.89%     88.89% |           0      0.00%     88.89% |           0      0.00%     88.89% |           0      0.00%     88.89% |           0      0.00%     88.89% |           0      0.00%     88.89% |           3      4.76%     93.65% |           4      6.35%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.L1Cache.hit_type_mach_latency_hist::total           63                      
 system.ruby.ST.L2Cache.hit_type_mach_latency_hist::bucket_size         1024                      
 system.ruby.ST.L2Cache.hit_type_mach_latency_hist::max_bucket        10239                      
-system.ruby.ST.L2Cache.hit_type_mach_latency_hist::samples           37                      
-system.ruby.ST.L2Cache.hit_type_mach_latency_hist::mean  2985.324324                      
-system.ruby.ST.L2Cache.hit_type_mach_latency_hist::gmean  1944.697722                      
-system.ruby.ST.L2Cache.hit_type_mach_latency_hist::stdev  1821.766406                      
-system.ruby.ST.L2Cache.hit_type_mach_latency_hist |          12     32.43%     32.43% |           0      0.00%     32.43% |           0      0.00%     32.43% |          12     32.43%     64.86% |          11     29.73%     94.59% |           2      5.41%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.ST.L2Cache.hit_type_mach_latency_hist::total           37                      
+system.ruby.ST.L2Cache.hit_type_mach_latency_hist::samples           34                      
+system.ruby.ST.L2Cache.hit_type_mach_latency_hist::mean  3395.676471                      
+system.ruby.ST.L2Cache.hit_type_mach_latency_hist::gmean  2727.100257                      
+system.ruby.ST.L2Cache.hit_type_mach_latency_hist::stdev  1571.778046                      
+system.ruby.ST.L2Cache.hit_type_mach_latency_hist |           8     23.53%     23.53% |           0      0.00%     23.53% |           0      0.00%     23.53% |          12     35.29%     58.82% |          13     38.24%     97.06% |           1      2.94%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.L2Cache.hit_type_mach_latency_hist::total           34                      
 system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size         1024                      
 system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket        10239                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist::samples          778                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist::mean  4130.665810                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean  3940.554861                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev   835.813724                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist |          22      2.83%      2.83% |           5      0.64%      3.47% |           8      1.03%      4.50% |         271     34.83%     39.33% |         433     55.66%     94.99% |          39      5.01%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.ST.Directory.miss_type_mach_latency_hist::total          778                      
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+system.ruby.ST.Directory.miss_type_mach_latency_hist::mean  4249.514249                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean  4082.834729                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev   812.787360                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist |          19      2.46%      2.46% |           5      0.65%      3.11% |           8      1.04%      4.15% |         213     27.59%     31.74% |         465     60.23%     91.97% |          62      8.03%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.Directory.miss_type_mach_latency_hist::total          772                      
+system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::bucket_size            1                      
+system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::max_bucket            9                      
+system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::samples            1                      
+system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::mean            3                      
+system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::gmean     3.000000                      
+system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::stdev          nan                      
+system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           1    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::total            1                      
 system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::bucket_size          128                      
 system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::max_bucket         1279                      
-system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::samples            5                      
-system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::mean   643.200000                      
-system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::gmean   628.468542                      
-system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::stdev   152.681695                      
-system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           1     20.00%     20.00% |           1     20.00%     40.00% |           2     40.00%     80.00% |           1     20.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::total            5                      
+system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::samples            6                      
+system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::mean   468.166667                      
+system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::gmean   407.116701                      
+system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::stdev   255.999544                      
+system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist |           0      0.00%      0.00% |           1     16.67%     16.67% |           2     33.33%     50.00% |           0      0.00%     50.00% |           1     16.67%     66.67% |           1     16.67%     83.33% |           1     16.67%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::total            6                      
 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size          128                      
 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket         1279                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples           42                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean   423.452381                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean   372.861830                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev   201.277530                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist |           2      4.76%      4.76% |          10     23.81%     28.57% |           6     14.29%     42.86% |           8     19.05%     61.90% |           9     21.43%     83.33% |           4      9.52%     92.86% |           3      7.14%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total           42                      
-system.ruby.L1Cache_Controller.Load                53      0.00%      0.00%
-system.ruby.L1Cache_Controller.Ifetch              47      0.00%      0.00%
-system.ruby.L1Cache_Controller.Store              893      0.00%      0.00%
-system.ruby.L1Cache_Controller.L1_Replacement        19950      0.00%      0.00%
-system.ruby.L1Cache_Controller.Data_Shared            3      0.00%      0.00%
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples           41                      
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean   428.878049                      
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean   392.820579                      
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev   162.430015                      
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist |           2      4.88%      4.88% |           3      7.32%     12.20% |          11     26.83%     39.02% |          11     26.83%     65.85% |          10     24.39%     90.24% |           4      9.76%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total           41                      
+system.ruby.L1Cache_Controller.Load                52      0.00%      0.00%
+system.ruby.L1Cache_Controller.Ifetch              49      0.00%      0.00%
+system.ruby.L1Cache_Controller.Store              871      0.00%      0.00%
+system.ruby.L1Cache_Controller.L1_Replacement        19827      0.00%      0.00%
+system.ruby.L1Cache_Controller.Data_Shared            7      0.00%      0.00%
 system.ruby.L1Cache_Controller.Data_Owner            1      0.00%      0.00%
-system.ruby.L1Cache_Controller.Data_All_Tokens          993      0.00%      0.00%
-system.ruby.L1Cache_Controller.Ack_All_Tokens            1      0.00%      0.00%
-system.ruby.L1Cache_Controller.Own_Lock_or_Unlock          373      0.00%      0.00%
-system.ruby.L1Cache_Controller.Request_Timeout          509      0.00%      0.00%
-system.ruby.L1Cache_Controller.Use_TimeoutNoStarvers          906      0.00%      0.00%
-system.ruby.L1Cache_Controller.NP.Load             48      0.00%      0.00%
-system.ruby.L1Cache_Controller.NP.Ifetch           47      0.00%      0.00%
-system.ruby.L1Cache_Controller.NP.Store           816      0.00%      0.00%
-system.ruby.L1Cache_Controller.NP.Data_All_Tokens           87      0.00%      0.00%
-system.ruby.L1Cache_Controller.NP.Own_Lock_or_Unlock          180      0.00%      0.00%
-system.ruby.L1Cache_Controller.S.L1_Replacement            3      0.00%      0.00%
+system.ruby.L1Cache_Controller.Data_All_Tokens          960      0.00%      0.00%
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-system.ruby.L1Cache_Controller.M.Own_Lock_or_Unlock           18      0.00%      0.00%
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-system.ruby.L1Cache_Controller.M_W.L1_Replacement          468      0.00%      0.00%
-system.ruby.L1Cache_Controller.M_W.Own_Lock_or_Unlock            1      0.00%      0.00%
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-system.ruby.L1Cache_Controller.MM_W.Store           11      0.00%      0.00%
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-system.ruby.L1Cache_Controller.MM_W.Use_TimeoutNoStarvers          815      0.00%      0.00%
-system.ruby.L1Cache_Controller.IM.L1_Replacement        10210      0.00%      0.00%
-system.ruby.L1Cache_Controller.IM.Data_Owner            1      0.00%      0.00%
-system.ruby.L1Cache_Controller.IM.Data_All_Tokens          814      0.00%      0.00%
-system.ruby.L1Cache_Controller.IM.Own_Lock_or_Unlock          114      0.00%      0.00%
-system.ruby.L1Cache_Controller.IM.Request_Timeout          443      0.00%      0.00%
-system.ruby.L1Cache_Controller.OM.Ack_All_Tokens            1      0.00%      0.00%
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-system.ruby.L1Cache_Controller.OM.Request_Timeout            6      0.00%      0.00%
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+system.ruby.L1Cache_Controller.MM_W.Own_Lock_or_Unlock           12      0.00%      0.00%
+system.ruby.L1Cache_Controller.MM_W.Use_TimeoutNoStarvers          806      0.00%      0.00%
+system.ruby.L1Cache_Controller.IM.L1_Replacement        10077      0.00%      0.00%
+system.ruby.L1Cache_Controller.IM.Data_All_Tokens          805      0.00%      0.00%
+system.ruby.L1Cache_Controller.IM.Own_Lock_or_Unlock          105      0.00%      0.00%
+system.ruby.L1Cache_Controller.IM.Request_Timeout          510      0.00%      0.00%
+system.ruby.L1Cache_Controller.SM.Data_All_Tokens            1      0.00%      0.00%
+system.ruby.L1Cache_Controller.IS.L1_Replacement          594      0.00%      0.00%
+system.ruby.L1Cache_Controller.IS.Data_Shared            7      0.00%      0.00%
+system.ruby.L1Cache_Controller.IS.Data_All_Tokens           90      0.00%      0.00%
+system.ruby.L1Cache_Controller.IS.Own_Lock_or_Unlock           12      0.00%      0.00%
+system.ruby.L1Cache_Controller.IS.Request_Timeout           38      0.00%      0.00%
+system.ruby.L2Cache_Controller.L1_GETS             97      0.00%      0.00%
+system.ruby.L2Cache_Controller.L1_GETX            807      0.00%      0.00%
+system.ruby.L2Cache_Controller.L2_Replacement          807      0.00%      0.00%
 system.ruby.L2Cache_Controller.Writeback_Shared_Data            1      0.00%      0.00%
-system.ruby.L2Cache_Controller.Writeback_All_Tokens          905      0.00%      0.00%
-system.ruby.L2Cache_Controller.Persistent_GETX          163      0.00%      0.00%
-system.ruby.L2Cache_Controller.Persistent_GETS           24      0.00%      0.00%
-system.ruby.L2Cache_Controller.Own_Lock_or_Unlock          186      0.00%      0.00%
-system.ruby.L2Cache_Controller.NP.L1_GETS           91      0.00%      0.00%
-system.ruby.L2Cache_Controller.NP.L1_GETX          779      0.00%      0.00%
-system.ruby.L2Cache_Controller.NP.Writeback_All_Tokens          821      0.00%      0.00%
-system.ruby.L2Cache_Controller.NP.Own_Lock_or_Unlock          158      0.00%      0.00%
+system.ruby.L2Cache_Controller.Writeback_All_Tokens          898      0.00%      0.00%
+system.ruby.L2Cache_Controller.Persistent_GETX          135      0.00%      0.00%
+system.ruby.L2Cache_Controller.Persistent_GETS           16      0.00%      0.00%
+system.ruby.L2Cache_Controller.Own_Lock_or_Unlock          150      0.00%      0.00%
+system.ruby.L2Cache_Controller.NP.L1_GETS           89      0.00%      0.00%
+system.ruby.L2Cache_Controller.NP.L1_GETX          774      0.00%      0.00%
+system.ruby.L2Cache_Controller.NP.Writeback_Shared_Data            1      0.00%      0.00%
+system.ruby.L2Cache_Controller.NP.Writeback_All_Tokens          810      0.00%      0.00%
+system.ruby.L2Cache_Controller.NP.Own_Lock_or_Unlock          134      0.00%      0.00%
 system.ruby.L2Cache_Controller.I.L1_GETS            1      0.00%      0.00%
-system.ruby.L2Cache_Controller.I.L2_Replacement           32      0.00%      0.00%
-system.ruby.L2Cache_Controller.I.Writeback_Shared_Data            1      0.00%      0.00%
-system.ruby.L2Cache_Controller.I.Writeback_All_Tokens           31      0.00%      0.00%
-system.ruby.L2Cache_Controller.S.Persistent_GETX            1      0.00%      0.00%
+system.ruby.L2Cache_Controller.I.L1_GETX            1      0.00%      0.00%
+system.ruby.L2Cache_Controller.I.L2_Replacement           12      0.00%      0.00%
+system.ruby.L2Cache_Controller.I.Writeback_All_Tokens           33      0.00%      0.00%
+system.ruby.L2Cache_Controller.I.Persistent_GETX            1      0.00%      0.00%
+system.ruby.L2Cache_Controller.S.L2_Replacement            1      0.00%      0.00%
+system.ruby.L2Cache_Controller.S.Writeback_All_Tokens            1      0.00%      0.00%
 system.ruby.L2Cache_Controller.O.L1_GETX            1      0.00%      0.00%
-system.ruby.L2Cache_Controller.O.Writeback_All_Tokens            2      0.00%      0.00%
-system.ruby.L2Cache_Controller.M.L1_GETS            3      0.00%      0.00%
-system.ruby.L2Cache_Controller.M.L1_GETX           36      0.00%      0.00%
-system.ruby.L2Cache_Controller.M.L2_Replacement          784      0.00%      0.00%
-system.ruby.L2Cache_Controller.M.Persistent_GETX           23      0.00%      0.00%
-system.ruby.L2Cache_Controller.M.Persistent_GETS            5      0.00%      0.00%
-system.ruby.L2Cache_Controller.I_L.L2_Replacement            1      0.00%      0.00%
-system.ruby.L2Cache_Controller.I_L.Writeback_All_Tokens           51      0.00%      0.00%
-system.ruby.L2Cache_Controller.I_L.Persistent_GETX          139      0.00%      0.00%
-system.ruby.L2Cache_Controller.I_L.Persistent_GETS           19      0.00%      0.00%
-system.ruby.L2Cache_Controller.I_L.Own_Lock_or_Unlock           28      0.00%      0.00%
-system.ruby.Directory_Controller.GETX             789      0.00%      0.00%
+system.ruby.L2Cache_Controller.O.L2_Replacement            1      0.00%      0.00%
+system.ruby.L2Cache_Controller.O.Writeback_All_Tokens            4      0.00%      0.00%
+system.ruby.L2Cache_Controller.O.Persistent_GETS            1      0.00%      0.00%
+system.ruby.L2Cache_Controller.M.L1_GETS            7      0.00%      0.00%
+system.ruby.L2Cache_Controller.M.L1_GETX           31      0.00%      0.00%
+system.ruby.L2Cache_Controller.M.L2_Replacement          793      0.00%      0.00%
+system.ruby.L2Cache_Controller.M.Persistent_GETX           12      0.00%      0.00%
+system.ruby.L2Cache_Controller.M.Persistent_GETS            2      0.00%      0.00%
+system.ruby.L2Cache_Controller.I_L.Writeback_All_Tokens           50      0.00%      0.00%
+system.ruby.L2Cache_Controller.I_L.Persistent_GETX          122      0.00%      0.00%
+system.ruby.L2Cache_Controller.I_L.Persistent_GETS           13      0.00%      0.00%
+system.ruby.L2Cache_Controller.I_L.Own_Lock_or_Unlock           15      0.00%      0.00%
+system.ruby.L2Cache_Controller.S_L.Own_Lock_or_Unlock            1      0.00%      0.00%
+system.ruby.Directory_Controller.GETX             784      0.00%      0.00%
 system.ruby.Directory_Controller.GETS              94      0.00%      0.00%
-system.ruby.Directory_Controller.Lockdown          187      0.00%      0.00%
-system.ruby.Directory_Controller.Unlockdown          186      0.00%      0.00%
-system.ruby.Directory_Controller.Data_All_Tokens          799      0.00%      0.00%
-system.ruby.Directory_Controller.Ack_Owner_All_Tokens           72      0.00%      0.00%
-system.ruby.Directory_Controller.Memory_Data          868      0.00%      0.00%
-system.ruby.Directory_Controller.Memory_Ack          787      0.00%      0.00%
-system.ruby.Directory_Controller.O.GETX           768      0.00%      0.00%
-system.ruby.Directory_Controller.O.GETS            86      0.00%      0.00%
-system.ruby.Directory_Controller.O.Lockdown           14      0.00%      0.00%
-system.ruby.Directory_Controller.NO.GETX            2      0.00%      0.00%
-system.ruby.Directory_Controller.NO.GETS            4      0.00%      0.00%
-system.ruby.Directory_Controller.NO.Lockdown          166      0.00%      0.00%
-system.ruby.Directory_Controller.NO.Data_All_Tokens          787      0.00%      0.00%
-system.ruby.Directory_Controller.NO.Ack_Owner_All_Tokens           72      0.00%      0.00%
-system.ruby.Directory_Controller.L.GETX            10      0.00%      0.00%
-system.ruby.Directory_Controller.L.GETS             2      0.00%      0.00%
-system.ruby.Directory_Controller.L.Unlockdown          185      0.00%      0.00%
-system.ruby.Directory_Controller.L.Data_All_Tokens           12      0.00%      0.00%
+system.ruby.Directory_Controller.Lockdown          152      0.00%      0.00%
+system.ruby.Directory_Controller.Unlockdown          151      0.00%      0.00%
+system.ruby.Directory_Controller.Data_Owner            1      0.00%      0.00%
+system.ruby.Directory_Controller.Data_All_Tokens          776      0.00%      0.00%
+system.ruby.Directory_Controller.Ack_Owner_All_Tokens           79      0.00%      0.00%
+system.ruby.Directory_Controller.Ack_All_Tokens            1      0.00%      0.00%
+system.ruby.Directory_Controller.Memory_Data          861      0.00%      0.00%
+system.ruby.Directory_Controller.Memory_Ack          773      0.00%      0.00%
+system.ruby.Directory_Controller.O.GETX           765      0.00%      0.00%
+system.ruby.Directory_Controller.O.GETS            88      0.00%      0.00%
+system.ruby.Directory_Controller.O.Lockdown            8      0.00%      0.00%
+system.ruby.Directory_Controller.O.Ack_All_Tokens            1      0.00%      0.00%
+system.ruby.Directory_Controller.NO.GETX            5      0.00%      0.00%
+system.ruby.Directory_Controller.NO.GETS            2      0.00%      0.00%
+system.ruby.Directory_Controller.NO.Lockdown          133      0.00%      0.00%
+system.ruby.Directory_Controller.NO.Data_Owner            1      0.00%      0.00%
+system.ruby.Directory_Controller.NO.Data_All_Tokens          772      0.00%      0.00%
+system.ruby.Directory_Controller.NO.Ack_Owner_All_Tokens           79      0.00%      0.00%
+system.ruby.Directory_Controller.L.GETX             5      0.00%      0.00%
+system.ruby.Directory_Controller.L.Unlockdown          150      0.00%      0.00%
+system.ruby.Directory_Controller.L.Data_All_Tokens            4      0.00%      0.00%
+system.ruby.Directory_Controller.O_W.GETS            4      0.00%      0.00%
 system.ruby.Directory_Controller.O_W.Memory_Data            1      0.00%      0.00%
-system.ruby.Directory_Controller.O_W.Memory_Ack          787      0.00%      0.00%
+system.ruby.Directory_Controller.O_W.Memory_Ack          773      0.00%      0.00%
 system.ruby.Directory_Controller.L_O_W.GETX            9      0.00%      0.00%
-system.ruby.Directory_Controller.L_O_W.GETS            2      0.00%      0.00%
 system.ruby.Directory_Controller.L_O_W.Unlockdown            1      0.00%      0.00%
-system.ruby.Directory_Controller.L_O_W.Memory_Data           13      0.00%      0.00%
-system.ruby.Directory_Controller.L_NO_W.Memory_Data            7      0.00%      0.00%
-system.ruby.Directory_Controller.NO_W.Lockdown            7      0.00%      0.00%
-system.ruby.Directory_Controller.NO_W.Memory_Data          847      0.00%      0.00%
+system.ruby.Directory_Controller.L_O_W.Memory_Data            7      0.00%      0.00%
+system.ruby.Directory_Controller.L_NO_W.Memory_Data           11      0.00%      0.00%
+system.ruby.Directory_Controller.NO_W.Lockdown           11      0.00%      0.00%
+system.ruby.Directory_Controller.NO_W.Memory_Data          842      0.00%      0.00%
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt
index 618345d21..d9bed26dd 100644
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt
@@ -1,448 +1,443 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000172                       # Number of seconds simulated
-sim_ticks                                      172201                       # Number of ticks simulated
-final_tick                                     172201                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.000180                       # Number of seconds simulated
+sim_ticks                                      180141                       # Number of ticks simulated
+final_tick                                     180141                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_tick_rate                                1805084                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 124680                       # Number of bytes of host memory used
+host_tick_rate                                1826543                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 157212                       # Number of bytes of host memory used
 host_seconds                                     0.10                       # Real time elapsed on the host
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                             1                       # Clock period in ticks
 system.ruby.clk_domain.clock                        1                       # Clock period in ticks
 system.ruby.outstanding_req_hist::bucket_size            2                      
 system.ruby.outstanding_req_hist::max_bucket           19                      
-system.ruby.outstanding_req_hist::samples          986                      
-system.ruby.outstanding_req_hist::mean      15.788032                      
-system.ruby.outstanding_req_hist::gmean     15.687524                      
-system.ruby.outstanding_req_hist::stdev      1.144707                      
-system.ruby.outstanding_req_hist         |           1      0.10%      0.10% |           2      0.20%      0.30% |           2      0.20%      0.51% |           2      0.20%      0.71% |           2      0.20%      0.91% |           2      0.20%      1.12% |           2      0.20%      1.32% |          88      8.92%     10.24% |         885     89.76%    100.00% |           0      0.00%    100.00%
-system.ruby.outstanding_req_hist::total           986                      
+system.ruby.outstanding_req_hist::samples         1006                      
+system.ruby.outstanding_req_hist::mean      15.782306                      
+system.ruby.outstanding_req_hist::gmean     15.683612                      
+system.ruby.outstanding_req_hist::stdev      1.136165                      
+system.ruby.outstanding_req_hist         |           1      0.10%      0.10% |           2      0.20%      0.30% |           2      0.20%      0.50% |           2      0.20%      0.70% |           2      0.20%      0.89% |           2      0.20%      1.09% |           2      0.20%      1.29% |          98      9.74%     11.03% |         895     88.97%    100.00% |           0      0.00%    100.00%
+system.ruby.outstanding_req_hist::total          1006                      
 system.ruby.latency_hist::bucket_size             512                      
 system.ruby.latency_hist::max_bucket             5119                      
-system.ruby.latency_hist::samples                 971                      
-system.ruby.latency_hist::mean            2802.392379                      
-system.ruby.latency_hist::gmean           1451.351840                      
-system.ruby.latency_hist::stdev           1327.570901                      
-system.ruby.latency_hist                 |         157     16.17%     16.17% |          29      2.99%     19.16% |           1      0.10%     19.26% |           3      0.31%     19.57% |          15      1.54%     21.11% |         152     15.65%     36.77% |         362     37.28%     74.05% |         199     20.49%     94.54% |          42      4.33%     98.87% |          11      1.13%    100.00%
-system.ruby.latency_hist::total                   971                      
+system.ruby.latency_hist::samples                 991                      
+system.ruby.latency_hist::mean            2874.908174                      
+system.ruby.latency_hist::gmean           1571.008914                      
+system.ruby.latency_hist::stdev           1325.547924                      
+system.ruby.latency_hist                 |         153     15.44%     15.44% |          26      2.62%     18.06% |           4      0.40%     18.47% |           0      0.00%     18.47% |          24      2.42%     20.89% |         118     11.91%     32.80% |         341     34.41%     67.20% |         267     26.94%     94.15% |          51      5.15%     99.29% |           7      0.71%    100.00%
+system.ruby.latency_hist::total                   991                      
 system.ruby.hit_latency_hist::bucket_size          512                      
 system.ruby.hit_latency_hist::max_bucket         5119                      
-system.ruby.hit_latency_hist::samples             125                      
-system.ruby.hit_latency_hist::mean         762.232000                      
-system.ruby.hit_latency_hist::gmean         22.623560                      
-system.ruby.hit_latency_hist::stdev       1395.728456                      
-system.ruby.hit_latency_hist             |          97     77.60%     77.60% |           1      0.80%     78.40% |           0      0.00%     78.40% |           0      0.00%     78.40% |           1      0.80%     79.20% |           7      5.60%     84.80% |          10      8.00%     92.80% |           7      5.60%     98.40% |           2      1.60%    100.00% |           0      0.00%    100.00%
-system.ruby.hit_latency_hist::total               125                      
+system.ruby.hit_latency_hist::samples             118                      
+system.ruby.hit_latency_hist::mean         809.601695                      
+system.ruby.hit_latency_hist::gmean         26.745437                      
+system.ruby.hit_latency_hist::stdev       1402.420911                      
+system.ruby.hit_latency_hist             |          88     74.58%     74.58% |           2      1.69%     76.27% |           0      0.00%     76.27% |           0      0.00%     76.27% |           2      1.69%     77.97% |           8      6.78%     84.75% |          11      9.32%     94.07% |           6      5.08%     99.15% |           1      0.85%    100.00% |           0      0.00%    100.00%
+system.ruby.hit_latency_hist::total               118                      
 system.ruby.miss_latency_hist::bucket_size          512                      
 system.ruby.miss_latency_hist::max_bucket         5119                      
-system.ruby.miss_latency_hist::samples            846                      
-system.ruby.miss_latency_hist::mean       3103.834515                      
-system.ruby.miss_latency_hist::gmean      2684.081643                      
-system.ruby.miss_latency_hist::stdev      1015.184360                      
-system.ruby.miss_latency_hist            |          60      7.09%      7.09% |          28      3.31%     10.40% |           1      0.12%     10.52% |           3      0.35%     10.87% |          14      1.65%     12.53% |         145     17.14%     29.67% |         352     41.61%     71.28% |         192     22.70%     93.97% |          40      4.73%     98.70% |          11      1.30%    100.00%
-system.ruby.miss_latency_hist::total              846                      
-system.ruby.Directory.incomplete_times            846                      
+system.ruby.miss_latency_hist::samples            873                      
+system.ruby.miss_latency_hist::mean       3154.067583                      
+system.ruby.miss_latency_hist::gmean      2724.443878                      
+system.ruby.miss_latency_hist::stdev      1037.171502                      
+system.ruby.miss_latency_hist            |          65      7.45%      7.45% |          24      2.75%     10.19% |           4      0.46%     10.65% |           0      0.00%     10.65% |          22      2.52%     13.17% |         110     12.60%     25.77% |         330     37.80%     63.57% |         261     29.90%     93.47% |          50      5.73%     99.20% |           7      0.80%    100.00%
+system.ruby.miss_latency_hist::total              873                      
+system.ruby.Directory.incomplete_times            873                      
 system.ruby.memctrl_clk_domain.clock                3                       # Clock period in ticks
-system.ruby.l1_cntrl0.L1Dcache.demand_hits           70                       # Number of cache demand hits
-system.ruby.l1_cntrl0.L1Dcache.demand_misses          848                       # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Dcache.demand_accesses          918                       # Number of cache demand accesses
+system.ruby.l1_cntrl0.L1Dcache.demand_hits           65                       # Number of cache demand hits
+system.ruby.l1_cntrl0.L1Dcache.demand_misses          875                       # Number of cache demand misses
+system.ruby.l1_cntrl0.L1Dcache.demand_accesses          940                       # Number of cache demand accesses
 system.ruby.l1_cntrl0.L1Icache.demand_hits            1                       # Number of cache demand hits
-system.ruby.l1_cntrl0.L1Icache.demand_misses           49                       # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Icache.demand_accesses           50                       # Number of cache demand accesses
-system.ruby.l1_cntrl0.L2cache.demand_hits           49                       # Number of cache demand hits
-system.ruby.l1_cntrl0.L2cache.demand_misses          848                       # Number of cache demand misses
-system.ruby.l1_cntrl0.L2cache.demand_accesses          897                       # Number of cache demand accesses
-system.ruby.l1_cntrl0.sequencer.store_waiting_on_load            7                       # Number of times a store aliased with a pending load
-system.ruby.l1_cntrl0.sequencer.store_waiting_on_store           86                       # Number of times a store aliased with a pending store
-system.ruby.l1_cntrl0.sequencer.load_waiting_on_store           11                       # Number of times a load aliased with a pending store
-system.ruby.l1_cntrl0.sequencer.load_waiting_on_load            2                       # Number of times a load aliased with a pending load
-system.ruby.network.routers0.percent_links_utilized     2.616564                      
-system.ruby.network.routers0.msg_count.Request_Control::2          852                      
-system.ruby.network.routers0.msg_count.Response_Data::4          850                      
-system.ruby.network.routers0.msg_count.Writeback_Data::5          768                      
-system.ruby.network.routers0.msg_count.Writeback_Control::2          845                      
-system.ruby.network.routers0.msg_count.Writeback_Control::3          844                      
-system.ruby.network.routers0.msg_count.Writeback_Control::5           75                      
-system.ruby.network.routers0.msg_count.Unblock_Control::5          845                      
-system.ruby.network.routers0.msg_bytes.Request_Control::2         6816                      
-system.ruby.network.routers0.msg_bytes.Response_Data::4        61200                      
-system.ruby.network.routers0.msg_bytes.Writeback_Data::5        55296                      
-system.ruby.network.routers0.msg_bytes.Writeback_Control::2         6760                      
-system.ruby.network.routers0.msg_bytes.Writeback_Control::3         6752                      
-system.ruby.network.routers0.msg_bytes.Writeback_Control::5          600                      
-system.ruby.network.routers0.msg_bytes.Unblock_Control::5         6760                      
-system.ruby.dir_cntrl0.memBuffer.memReq          1617                       # Total number of memory requests
-system.ruby.dir_cntrl0.memBuffer.memRead          850                       # Number of memory reads
-system.ruby.dir_cntrl0.memBuffer.memWrite          767                       # Number of memory writes
-system.ruby.dir_cntrl0.memBuffer.memRefresh         1196                       # Number of memory refreshes
-system.ruby.dir_cntrl0.memBuffer.memWaitCycles          550                       # Delay stalled at the head of the bank queue
-system.ruby.dir_cntrl0.memBuffer.memInputQ           48                       # Delay in the input queue
-system.ruby.dir_cntrl0.memBuffer.memBankQ            1                       # Delay behind the head of the bank queue
-system.ruby.dir_cntrl0.memBuffer.totalStalls          599                       # Total number of stall cycles
-system.ruby.dir_cntrl0.memBuffer.stallsPerReq     0.370439                       # Expected number of stall cycles per request
-system.ruby.dir_cntrl0.memBuffer.memBankBusy          172                       # memory stalls due to busy bank
-system.ruby.dir_cntrl0.memBuffer.memBusBusy          204                       # memory stalls due to busy bus
-system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy           52                       # memory stalls due to read write turnaround
-system.ruby.dir_cntrl0.memBuffer.memDataBusBusy           82                       # memory stalls due to read read turnaround
-system.ruby.dir_cntrl0.memBuffer.memArbWait           40                       # memory stalls due to arbitration
-system.ruby.dir_cntrl0.memBuffer.memBankCount |          60      3.71%      3.71% |          50      3.09%      6.80% |          58      3.59%     10.39% |          80      4.95%     15.34% |          69      4.27%     19.60% |          77      4.76%     24.37% |          71      4.39%     28.76% |          48      2.97%     31.73% |          48      2.97%     34.69% |          38      2.35%     37.04% |          42      2.60%     39.64% |          44      2.72%     42.36% |          39      2.41%     44.77% |          57      3.53%     48.30% |          47      2.91%     51.21% |          44      2.72%     53.93% |          42      2.60%     56.52% |          45      2.78%     59.31% |          53      3.28%     62.59% |          54      3.34%     65.92% |          55      3.40%     69.33% |          41      2.54%     71.86% |          48      2.97%     74.83% |          56      3.46%     78.29% |          29      1.79%     80.09% |          45      2.78%     82.87% |          43      2.66%     85.53% |          51      3.15%     88.68% |          47      2.91%     91.59% |          51      3.15%     94.74% |          42      2.60%     97.34% |          43      2.66%    100.00% # Number of accesses per bank
-system.ruby.dir_cntrl0.memBuffer.memBankCount::total         1617                       # Number of accesses per bank
+system.ruby.l1_cntrl0.L1Icache.demand_misses           50                       # Number of cache demand misses
+system.ruby.l1_cntrl0.L1Icache.demand_accesses           51                       # Number of cache demand accesses
+system.ruby.l1_cntrl0.L2cache.demand_hits           50                       # Number of cache demand hits
+system.ruby.l1_cntrl0.L2cache.demand_misses          875                       # Number of cache demand misses
+system.ruby.l1_cntrl0.L2cache.demand_accesses          925                       # Number of cache demand accesses
+system.ruby.l1_cntrl0.sequencer.store_waiting_on_load            3                       # Number of times a store aliased with a pending load
+system.ruby.l1_cntrl0.sequencer.store_waiting_on_store           83                       # Number of times a store aliased with a pending store
+system.ruby.l1_cntrl0.sequencer.load_waiting_on_store            5                       # Number of times a load aliased with a pending store
+system.ruby.network.routers0.percent_links_utilized     2.571180                      
+system.ruby.network.routers0.msg_count.Request_Control::2          876                      
+system.ruby.network.routers0.msg_count.Response_Data::4          874                      
+system.ruby.network.routers0.msg_count.Writeback_Data::5          789                      
+system.ruby.network.routers0.msg_count.Writeback_Control::2          869                      
+system.ruby.network.routers0.msg_count.Writeback_Control::3          866                      
+system.ruby.network.routers0.msg_count.Writeback_Control::5           76                      
+system.ruby.network.routers0.msg_count.Unblock_Control::5          873                      
+system.ruby.network.routers0.msg_bytes.Request_Control::2         7008                      
+system.ruby.network.routers0.msg_bytes.Response_Data::4        62928                      
+system.ruby.network.routers0.msg_bytes.Writeback_Data::5        56808                      
+system.ruby.network.routers0.msg_bytes.Writeback_Control::2         6952                      
+system.ruby.network.routers0.msg_bytes.Writeback_Control::3         6928                      
+system.ruby.network.routers0.msg_bytes.Writeback_Control::5          608                      
+system.ruby.network.routers0.msg_bytes.Unblock_Control::5         6984                      
+system.ruby.dir_cntrl0.memBuffer.memReq          1663                       # Total number of memory requests
+system.ruby.dir_cntrl0.memBuffer.memRead          874                       # Number of memory reads
+system.ruby.dir_cntrl0.memBuffer.memWrite          789                       # Number of memory writes
+system.ruby.dir_cntrl0.memBuffer.memRefresh         1251                       # Number of memory refreshes
+system.ruby.dir_cntrl0.memBuffer.memWaitCycles          540                       # Delay stalled at the head of the bank queue
+system.ruby.dir_cntrl0.memBuffer.memInputQ           46                       # Delay in the input queue
+system.ruby.dir_cntrl0.memBuffer.memBankQ            5                       # Delay behind the head of the bank queue
+system.ruby.dir_cntrl0.memBuffer.totalStalls          591                       # Total number of stall cycles
+system.ruby.dir_cntrl0.memBuffer.stallsPerReq     0.355382                       # Expected number of stall cycles per request
+system.ruby.dir_cntrl0.memBuffer.memBankBusy          182                       # memory stalls due to busy bank
+system.ruby.dir_cntrl0.memBuffer.memBusBusy          208                       # memory stalls due to busy bus
+system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy           34                       # memory stalls due to read write turnaround
+system.ruby.dir_cntrl0.memBuffer.memDataBusBusy           83                       # memory stalls due to read read turnaround
+system.ruby.dir_cntrl0.memBuffer.memArbWait           33                       # memory stalls due to arbitration
+system.ruby.dir_cntrl0.memBuffer.memBankCount |          66      3.97%      3.97% |          48      2.89%      6.86% |          54      3.25%     10.10% |          88      5.29%     15.39% |          64      3.85%     19.24% |          67      4.03%     23.27% |          67      4.03%     27.30% |          52      3.13%     30.43% |          60      3.61%     34.03% |          53      3.19%     37.22% |          57      3.43%     40.65% |          32      1.92%     42.57% |          42      2.53%     45.10% |          48      2.89%     47.99% |          35      2.10%     50.09% |          37      2.22%     52.32% |          52      3.13%     55.44% |          55      3.31%     58.75% |          45      2.71%     61.46% |          46      2.77%     64.22% |          43      2.59%     66.81% |          60      3.61%     70.41% |          49      2.95%     73.36% |          52      3.13%     76.49% |          54      3.25%     79.74% |          44      2.65%     82.38% |          47      2.83%     85.21% |          51      3.07%     88.27% |          37      2.22%     90.50% |          52      3.13%     93.63% |          50      3.01%     96.63% |          56      3.37%    100.00% # Number of accesses per bank
+system.ruby.dir_cntrl0.memBuffer.memBankCount::total         1663                       # Number of accesses per bank
 system.ruby.dir_cntrl0.probeFilter.demand_hits            0                       # Number of cache demand hits
 system.ruby.dir_cntrl0.probeFilter.demand_misses            0                       # Number of cache demand misses
 system.ruby.dir_cntrl0.probeFilter.demand_accesses            0                       # Number of cache demand accesses
-system.ruby.network.routers1.percent_links_utilized     2.614822                      
-system.ruby.network.routers1.msg_count.Request_Control::2          851                      
-system.ruby.network.routers1.msg_count.Response_Data::4          850                      
-system.ruby.network.routers1.msg_count.Writeback_Data::5          767                      
-system.ruby.network.routers1.msg_count.Writeback_Control::2          843                      
-system.ruby.network.routers1.msg_count.Writeback_Control::3          844                      
-system.ruby.network.routers1.msg_count.Writeback_Control::5           75                      
-system.ruby.network.routers1.msg_count.Unblock_Control::5          845                      
-system.ruby.network.routers1.msg_bytes.Request_Control::2         6808                      
-system.ruby.network.routers1.msg_bytes.Response_Data::4        61200                      
-system.ruby.network.routers1.msg_bytes.Writeback_Data::5        55224                      
-system.ruby.network.routers1.msg_bytes.Writeback_Control::2         6744                      
-system.ruby.network.routers1.msg_bytes.Writeback_Control::3         6752                      
-system.ruby.network.routers1.msg_bytes.Writeback_Control::5          600                      
-system.ruby.network.routers1.msg_bytes.Unblock_Control::5         6760                      
-system.ruby.network.routers2.percent_links_utilized     2.616129                      
-system.ruby.network.routers2.msg_count.Request_Control::2          851                      
-system.ruby.network.routers2.msg_count.Response_Data::4          850                      
-system.ruby.network.routers2.msg_count.Writeback_Data::5          768                      
-system.ruby.network.routers2.msg_count.Writeback_Control::2          843                      
-system.ruby.network.routers2.msg_count.Writeback_Control::3          844                      
-system.ruby.network.routers2.msg_count.Writeback_Control::5           75                      
-system.ruby.network.routers2.msg_count.Unblock_Control::5          845                      
-system.ruby.network.routers2.msg_bytes.Request_Control::2         6808                      
-system.ruby.network.routers2.msg_bytes.Response_Data::4        61200                      
-system.ruby.network.routers2.msg_bytes.Writeback_Data::5        55296                      
-system.ruby.network.routers2.msg_bytes.Writeback_Control::2         6744                      
-system.ruby.network.routers2.msg_bytes.Writeback_Control::3         6752                      
-system.ruby.network.routers2.msg_bytes.Writeback_Control::5          600                      
-system.ruby.network.routers2.msg_bytes.Unblock_Control::5         6760                      
-system.ruby.network.msg_count.Request_Control         2554                      
-system.ruby.network.msg_count.Response_Data         2550                      
-system.ruby.network.msg_count.Writeback_Data         2303                      
-system.ruby.network.msg_count.Writeback_Control         5288                      
-system.ruby.network.msg_count.Unblock_Control         2535                      
-system.ruby.network.msg_byte.Request_Control        20432                      
-system.ruby.network.msg_byte.Response_Data       183600                      
-system.ruby.network.msg_byte.Writeback_Data       165816                      
-system.ruby.network.msg_byte.Writeback_Control        42304                      
-system.ruby.network.msg_byte.Unblock_Control        20280                      
-system.ruby.network.routers0.throttle0.link_utilization     2.466304                      
-system.ruby.network.routers0.throttle0.msg_count.Response_Data::4          850                      
-system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3          844                      
-system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4        61200                      
-system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3         6752                      
-system.ruby.network.routers0.throttle1.link_utilization     2.766825                      
-system.ruby.network.routers0.throttle1.msg_count.Request_Control::2          852                      
-system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::5          768                      
-system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::2          845                      
-system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::5           75                      
-system.ruby.network.routers0.throttle1.msg_count.Unblock_Control::5          845                      
-system.ruby.network.routers0.throttle1.msg_bytes.Request_Control::2         6816                      
-system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::5        55296                      
-system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::2         6760                      
-system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::5          600                      
-system.ruby.network.routers0.throttle1.msg_bytes.Unblock_Control::5         6760                      
-system.ruby.network.routers1.throttle0.link_utilization     2.763341                      
-system.ruby.network.routers1.throttle0.msg_count.Request_Control::2          851                      
-system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::5          767                      
-system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::2          843                      
-system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::5           75                      
-system.ruby.network.routers1.throttle0.msg_count.Unblock_Control::5          845                      
-system.ruby.network.routers1.throttle0.msg_bytes.Request_Control::2         6808                      
-system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::5        55224                      
-system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::2         6744                      
-system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::5          600                      
-system.ruby.network.routers1.throttle0.msg_bytes.Unblock_Control::5         6760                      
-system.ruby.network.routers1.throttle1.link_utilization     2.466304                      
-system.ruby.network.routers1.throttle1.msg_count.Response_Data::4          850                      
-system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3          844                      
-system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4        61200                      
-system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3         6752                      
-system.ruby.network.routers2.throttle0.link_utilization     2.466304                      
-system.ruby.network.routers2.throttle0.msg_count.Response_Data::4          850                      
-system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3          844                      
-system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4        61200                      
-system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3         6752                      
-system.ruby.network.routers2.throttle1.link_utilization     2.765954                      
-system.ruby.network.routers2.throttle1.msg_count.Request_Control::2          851                      
-system.ruby.network.routers2.throttle1.msg_count.Writeback_Data::5          768                      
-system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::2          843                      
-system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::5           75                      
-system.ruby.network.routers2.throttle1.msg_count.Unblock_Control::5          845                      
-system.ruby.network.routers2.throttle1.msg_bytes.Request_Control::2         6808                      
-system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Data::5        55296                      
-system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::2         6744                      
-system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::5          600                      
-system.ruby.network.routers2.throttle1.msg_bytes.Unblock_Control::5         6760                      
+system.ruby.network.routers1.percent_links_utilized     2.570764                      
+system.ruby.network.routers1.msg_count.Request_Control::2          875                      
+system.ruby.network.routers1.msg_count.Response_Data::4          874                      
+system.ruby.network.routers1.msg_count.Writeback_Data::5          789                      
+system.ruby.network.routers1.msg_count.Writeback_Control::2          868                      
+system.ruby.network.routers1.msg_count.Writeback_Control::3          868                      
+system.ruby.network.routers1.msg_count.Writeback_Control::5           76                      
+system.ruby.network.routers1.msg_count.Unblock_Control::5          870                      
+system.ruby.network.routers1.msg_bytes.Request_Control::2         7000                      
+system.ruby.network.routers1.msg_bytes.Response_Data::4        62928                      
+system.ruby.network.routers1.msg_bytes.Writeback_Data::5        56808                      
+system.ruby.network.routers1.msg_bytes.Writeback_Control::2         6944                      
+system.ruby.network.routers1.msg_bytes.Writeback_Control::3         6944                      
+system.ruby.network.routers1.msg_bytes.Writeback_Control::5          608                      
+system.ruby.network.routers1.msg_bytes.Unblock_Control::5         6960                      
+system.ruby.network.routers2.percent_links_utilized     2.571042                      
+system.ruby.network.routers2.msg_count.Request_Control::2          876                      
+system.ruby.network.routers2.msg_count.Response_Data::4          874                      
+system.ruby.network.routers2.msg_count.Writeback_Data::5          789                      
+system.ruby.network.routers2.msg_count.Writeback_Control::2          869                      
+system.ruby.network.routers2.msg_count.Writeback_Control::3          866                      
+system.ruby.network.routers2.msg_count.Writeback_Control::5           76                      
+system.ruby.network.routers2.msg_count.Unblock_Control::5          872                      
+system.ruby.network.routers2.msg_bytes.Request_Control::2         7008                      
+system.ruby.network.routers2.msg_bytes.Response_Data::4        62928                      
+system.ruby.network.routers2.msg_bytes.Writeback_Data::5        56808                      
+system.ruby.network.routers2.msg_bytes.Writeback_Control::2         6952                      
+system.ruby.network.routers2.msg_bytes.Writeback_Control::3         6928                      
+system.ruby.network.routers2.msg_bytes.Writeback_Control::5          608                      
+system.ruby.network.routers2.msg_bytes.Unblock_Control::5         6976                      
+system.ruby.network.msg_count.Request_Control         2627                      
+system.ruby.network.msg_count.Response_Data         2622                      
+system.ruby.network.msg_count.Writeback_Data         2367                      
+system.ruby.network.msg_count.Writeback_Control         5434                      
+system.ruby.network.msg_count.Unblock_Control         2615                      
+system.ruby.network.msg_byte.Request_Control        21016                      
+system.ruby.network.msg_byte.Response_Data       188784                      
+system.ruby.network.msg_byte.Writeback_Data       170424                      
+system.ruby.network.msg_byte.Writeback_Control        43472                      
+system.ruby.network.msg_byte.Unblock_Control        20920                      
+system.ruby.network.routers0.throttle0.link_utilization     2.423657                      
+system.ruby.network.routers0.throttle0.msg_count.Response_Data::4          874                      
+system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3          866                      
+system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4        62928                      
+system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3         6928                      
+system.ruby.network.routers0.throttle1.link_utilization     2.718704                      
+system.ruby.network.routers0.throttle1.msg_count.Request_Control::2          876                      
+system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::5          789                      
+system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::2          869                      
+system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::5           76                      
+system.ruby.network.routers0.throttle1.msg_count.Unblock_Control::5          873                      
+system.ruby.network.routers0.throttle1.msg_bytes.Request_Control::2         7008                      
+system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::5        56808                      
+system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::2         6952                      
+system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::5          608                      
+system.ruby.network.routers0.throttle1.msg_bytes.Unblock_Control::5         6984                      
+system.ruby.network.routers1.throttle0.link_utilization     2.717316                      
+system.ruby.network.routers1.throttle0.msg_count.Request_Control::2          875                      
+system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::5          789                      
+system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::2          868                      
+system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::5           76                      
+system.ruby.network.routers1.throttle0.msg_count.Unblock_Control::5          870                      
+system.ruby.network.routers1.throttle0.msg_bytes.Request_Control::2         7000                      
+system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::5        56808                      
+system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::2         6944                      
+system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::5          608                      
+system.ruby.network.routers1.throttle0.msg_bytes.Unblock_Control::5         6960                      
+system.ruby.network.routers1.throttle1.link_utilization     2.424212                      
+system.ruby.network.routers1.throttle1.msg_count.Response_Data::4          874                      
+system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3          868                      
+system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4        62928                      
+system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3         6944                      
+system.ruby.network.routers2.throttle0.link_utilization     2.423657                      
+system.ruby.network.routers2.throttle0.msg_count.Response_Data::4          874                      
+system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3          866                      
+system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4        62928                      
+system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3         6928                      
+system.ruby.network.routers2.throttle1.link_utilization     2.718426                      
+system.ruby.network.routers2.throttle1.msg_count.Request_Control::2          876                      
+system.ruby.network.routers2.throttle1.msg_count.Writeback_Data::5          789                      
+system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::2          869                      
+system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::5           76                      
+system.ruby.network.routers2.throttle1.msg_count.Unblock_Control::5          872                      
+system.ruby.network.routers2.throttle1.msg_bytes.Request_Control::2         7008                      
+system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Data::5        56808                      
+system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::2         6952                      
+system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::5          608                      
+system.ruby.network.routers2.throttle1.msg_bytes.Unblock_Control::5         6976                      
 system.ruby.LD.latency_hist::bucket_size          512                      
 system.ruby.LD.latency_hist::max_bucket          5119                      
-system.ruby.LD.latency_hist::samples               50                      
-system.ruby.LD.latency_hist::mean         2780.460000                      
-system.ruby.LD.latency_hist::gmean        1341.395991                      
-system.ruby.LD.latency_hist::stdev        1378.721224                      
-system.ruby.LD.latency_hist              |           9     18.00%     18.00% |           1      2.00%     20.00% |           0      0.00%     20.00% |           0      0.00%     20.00% |           1      2.00%     22.00% |           8     16.00%     38.00% |          15     30.00%     68.00% |          14     28.00%     96.00% |           2      4.00%    100.00% |           0      0.00%    100.00%
-system.ruby.LD.latency_hist::total                 50                      
+system.ruby.LD.latency_hist::samples               49                      
+system.ruby.LD.latency_hist::mean         3191.306122                      
+system.ruby.LD.latency_hist::gmean        2107.747152                      
+system.ruby.LD.latency_hist::stdev        1000.724721                      
+system.ruby.LD.latency_hist              |           4      8.16%      8.16% |           0      0.00%      8.16% |           0      0.00%      8.16% |           0      0.00%      8.16% |           0      0.00%      8.16% |           5     10.20%     18.37% |          25     51.02%     69.39% |          15     30.61%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.latency_hist::total                 49                      
 system.ruby.LD.hit_latency_hist::bucket_size           16                      
 system.ruby.LD.hit_latency_hist::max_bucket          159                      
-system.ruby.LD.hit_latency_hist::samples            5                      
-system.ruby.LD.hit_latency_hist::mean              24                      
-system.ruby.LD.hit_latency_hist::gmean       3.987421                      
-system.ruby.LD.hit_latency_hist::stdev      49.203658                      
-system.ruby.LD.hit_latency_hist          |           4     80.00%     80.00% |           0      0.00%     80.00% |           0      0.00%     80.00% |           0      0.00%     80.00% |           0      0.00%     80.00% |           0      0.00%     80.00% |           0      0.00%     80.00% |           1     20.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.LD.hit_latency_hist::total              5                      
+system.ruby.LD.hit_latency_hist::samples            4                      
+system.ruby.LD.hit_latency_hist::mean       31.750000                      
+system.ruby.LD.hit_latency_hist::gmean       8.056049                      
+system.ruby.LD.hit_latency_hist::stdev      56.835288                      
+system.ruby.LD.hit_latency_hist          |           3     75.00%     75.00% |           0      0.00%     75.00% |           0      0.00%     75.00% |           0      0.00%     75.00% |           0      0.00%     75.00% |           0      0.00%     75.00% |           0      0.00%     75.00% |           1     25.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.hit_latency_hist::total              4                      
 system.ruby.LD.miss_latency_hist::bucket_size          512                      
 system.ruby.LD.miss_latency_hist::max_bucket         5119                      
 system.ruby.LD.miss_latency_hist::samples           45                      
-system.ruby.LD.miss_latency_hist::mean    3086.733333                      
-system.ruby.LD.miss_latency_hist::gmean   2560.470465                      
-system.ruby.LD.miss_latency_hist::stdev   1075.782430                      
-system.ruby.LD.miss_latency_hist         |           4      8.89%      8.89% |           1      2.22%     11.11% |           0      0.00%     11.11% |           0      0.00%     11.11% |           1      2.22%     13.33% |           8     17.78%     31.11% |          15     33.33%     64.44% |          14     31.11%     95.56% |           2      4.44%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.miss_latency_hist::mean    3472.155556                      
+system.ruby.LD.miss_latency_hist::gmean   3457.202829                      
+system.ruby.LD.miss_latency_hist::stdev    322.606216                      
+system.ruby.LD.miss_latency_hist         |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           5     11.11%     11.11% |          25     55.56%     66.67% |          15     33.33%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.LD.miss_latency_hist::total            45                      
 system.ruby.ST.latency_hist::bucket_size          512                      
 system.ruby.ST.latency_hist::max_bucket          5119                      
-system.ruby.ST.latency_hist::samples              866                      
-system.ruby.ST.latency_hist::mean         2940.797921                      
-system.ruby.ST.latency_hist::gmean        1643.954154                      
-system.ruby.ST.latency_hist::stdev        1219.878101                      
-system.ruby.ST.latency_hist              |         110     12.70%     12.70% |          16      1.85%     14.55% |           1      0.12%     14.67% |           3      0.35%     15.01% |          14      1.62%     16.63% |         144     16.63%     33.26% |         345     39.84%     73.09% |         183     21.13%     94.23% |          39      4.50%     98.73% |          11      1.27%    100.00%
-system.ruby.ST.latency_hist::total                866                      
+system.ruby.ST.latency_hist::samples              889                      
+system.ruby.ST.latency_hist::mean         3004.976378                      
+system.ruby.ST.latency_hist::gmean        1749.500693                      
+system.ruby.ST.latency_hist::stdev        1224.459726                      
+system.ruby.ST.latency_hist              |         109     12.26%     12.26% |          14      1.57%     13.84% |           4      0.45%     14.29% |           0      0.00%     14.29% |          24      2.70%     16.99% |         113     12.71%     29.70% |         316     35.55%     65.24% |         251     28.23%     93.48% |          51      5.74%     99.21% |           7      0.79%    100.00%
+system.ruby.ST.latency_hist::total                889                      
 system.ruby.ST.hit_latency_hist::bucket_size          512                      
 system.ruby.ST.hit_latency_hist::max_bucket         5119                      
-system.ruby.ST.hit_latency_hist::samples          105                      
-system.ruby.ST.hit_latency_hist::mean      726.142857                      
-system.ruby.ST.hit_latency_hist::gmean      21.587264                      
-system.ruby.ST.hit_latency_hist::stdev    1344.515765                      
-system.ruby.ST.hit_latency_hist          |          82     78.10%     78.10% |           1      0.95%     79.05% |           0      0.00%     79.05% |           0      0.00%     79.05% |           1      0.95%     80.00% |           7      6.67%     86.67% |           8      7.62%     94.29% |           5      4.76%     99.05% |           1      0.95%    100.00% |           0      0.00%    100.00%
-system.ruby.ST.hit_latency_hist::total            105                      
+system.ruby.ST.hit_latency_hist::samples          102                      
+system.ruby.ST.hit_latency_hist::mean      887.392157                      
+system.ruby.ST.hit_latency_hist::gmean      28.209510                      
+system.ruby.ST.hit_latency_hist::stdev    1444.836166                      
+system.ruby.ST.hit_latency_hist          |          74     72.55%     72.55% |           1      0.98%     73.53% |           0      0.00%     73.53% |           0      0.00%     73.53% |           2      1.96%     75.49% |           8      7.84%     83.33% |          11     10.78%     94.12% |           5      4.90%     99.02% |           1      0.98%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.hit_latency_hist::total            102                      
 system.ruby.ST.miss_latency_hist::bucket_size          512                      
 system.ruby.ST.miss_latency_hist::max_bucket         5119                      
-system.ruby.ST.miss_latency_hist::samples          761                      
-system.ruby.ST.miss_latency_hist::mean    3246.367937                      
-system.ruby.ST.miss_latency_hist::gmean   2988.950366                      
-system.ruby.ST.miss_latency_hist::stdev    821.708353                      
-system.ruby.ST.miss_latency_hist         |          28      3.68%      3.68% |          15      1.97%      5.65% |           1      0.13%      5.78% |           3      0.39%      6.18% |          13      1.71%      7.88% |         137     18.00%     25.89% |         337     44.28%     70.17% |         178     23.39%     93.56% |          38      4.99%     98.55% |          11      1.45%    100.00%
-system.ruby.ST.miss_latency_hist::total           761                      
+system.ruby.ST.miss_latency_hist::samples          787                      
+system.ruby.ST.miss_latency_hist::mean    3279.428208                      
+system.ruby.ST.miss_latency_hist::gmean   2987.001628                      
+system.ruby.ST.miss_latency_hist::stdev    876.519166                      
+system.ruby.ST.miss_latency_hist         |          35      4.45%      4.45% |          13      1.65%      6.10% |           4      0.51%      6.61% |           0      0.00%      6.61% |          22      2.80%      9.40% |         105     13.34%     22.74% |         305     38.75%     61.50% |         246     31.26%     92.76% |          50      6.35%     99.11% |           7      0.89%    100.00%
+system.ruby.ST.miss_latency_hist::total           787                      
 system.ruby.IFETCH.latency_hist::bucket_size          128                      
 system.ruby.IFETCH.latency_hist::max_bucket         1279                      
-system.ruby.IFETCH.latency_hist::samples           50                      
-system.ruby.IFETCH.latency_hist::mean      332.280000                      
-system.ruby.IFETCH.latency_hist::gmean     165.036201                      
-system.ruby.IFETCH.latency_hist::stdev     230.031678                      
-system.ruby.IFETCH.latency_hist          |          12     24.00%     24.00% |           6     12.00%     36.00% |          11     22.00%     58.00% |           9     18.00%     76.00% |           7     14.00%     90.00% |           4      8.00%     98.00% |           1      2.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.IFETCH.latency_hist::total             50                      
+system.ruby.IFETCH.latency_hist::samples           51                      
+system.ruby.IFETCH.latency_hist::mean      325.960784                      
+system.ruby.IFETCH.latency_hist::gmean     181.443736                      
+system.ruby.IFETCH.latency_hist::stdev     223.289316                      
+system.ruby.IFETCH.latency_hist          |          11     21.57%     21.57% |           8     15.69%     37.25% |          11     21.57%     58.82% |          10     19.61%     78.43% |           7     13.73%     92.16% |           3      5.88%     98.04% |           0      0.00%     98.04% |           1      1.96%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.latency_hist::total             51                      
 system.ruby.IFETCH.hit_latency_hist::bucket_size           16                      
 system.ruby.IFETCH.hit_latency_hist::max_bucket          159                      
 system.ruby.IFETCH.hit_latency_hist::samples           10                      
-system.ruby.IFETCH.hit_latency_hist::mean    15.900000                      
-system.ruby.IFETCH.hit_latency_hist::gmean     6.857887                      
-system.ruby.IFETCH.hit_latency_hist::stdev    32.084784                      
-system.ruby.IFETCH.hit_latency_hist      |           9     90.00%     90.00% |           0      0.00%     90.00% |           0      0.00%     90.00% |           0      0.00%     90.00% |           0      0.00%     90.00% |           0      0.00%     90.00% |           1     10.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.hit_latency_hist::mean           28                      
+system.ruby.IFETCH.hit_latency_hist::gmean    11.094785                      
+system.ruby.IFETCH.hit_latency_hist::stdev    45.397014                      
+system.ruby.IFETCH.hit_latency_hist      |           8     80.00%     80.00% |           0      0.00%     80.00% |           0      0.00%     80.00% |           0      0.00%     80.00% |           0      0.00%     80.00% |           0      0.00%     80.00% |           1     10.00%     90.00% |           1     10.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.IFETCH.hit_latency_hist::total           10                      
 system.ruby.IFETCH.miss_latency_hist::bucket_size          128                      
 system.ruby.IFETCH.miss_latency_hist::max_bucket         1279                      
-system.ruby.IFETCH.miss_latency_hist::samples           40                      
-system.ruby.IFETCH.miss_latency_hist::mean   411.375000                      
-system.ruby.IFETCH.miss_latency_hist::gmean   365.532878                      
-system.ruby.IFETCH.miss_latency_hist::stdev   184.831550                      
-system.ruby.IFETCH.miss_latency_hist     |           2      5.00%      5.00% |           6     15.00%     20.00% |          11     27.50%     47.50% |           9     22.50%     70.00% |           7     17.50%     87.50% |           4     10.00%     97.50% |           1      2.50%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.IFETCH.miss_latency_hist::total           40                      
+system.ruby.IFETCH.miss_latency_hist::samples           41                      
+system.ruby.IFETCH.miss_latency_hist::mean   398.634146                      
+system.ruby.IFETCH.miss_latency_hist::gmean   358.713406                      
+system.ruby.IFETCH.miss_latency_hist::stdev   185.068468                      
+system.ruby.IFETCH.miss_latency_hist     |           1      2.44%      2.44% |           8     19.51%     21.95% |          11     26.83%     48.78% |          10     24.39%     73.17% |           7     17.07%     90.24% |           3      7.32%     97.56% |           0      0.00%     97.56% |           1      2.44%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.miss_latency_hist::total           41                      
 system.ruby.FLUSH.latency_hist::bucket_size          512                      
 system.ruby.FLUSH.latency_hist::max_bucket         5119                      
-system.ruby.FLUSH.latency_hist::samples             5                      
-system.ruby.FLUSH.latency_hist::mean             3751                      
-system.ruby.FLUSH.latency_hist::gmean     3739.394420                      
-system.ruby.FLUSH.latency_hist::stdev      332.267212                      
-system.ruby.FLUSH.latency_hist           |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           2     40.00%     40.00% |           2     40.00%     80.00% |           1     20.00%    100.00% |           0      0.00%    100.00%
-system.ruby.FLUSH.latency_hist::total               5                      
+system.ruby.FLUSH.latency_hist::samples             2                      
+system.ruby.FLUSH.latency_hist::mean             2306                      
+system.ruby.FLUSH.latency_hist::gmean     1583.874995                      
+system.ruby.FLUSH.latency_hist::stdev     2370.221931                      
+system.ruby.FLUSH.latency_hist           |           0      0.00%      0.00% |           1     50.00%     50.00% |           0      0.00%     50.00% |           0      0.00%     50.00% |           0      0.00%     50.00% |           0      0.00%     50.00% |           0      0.00%     50.00% |           1     50.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.FLUSH.latency_hist::total               2                      
 system.ruby.FLUSH.hit_latency_hist::bucket_size          512                      
 system.ruby.FLUSH.hit_latency_hist::max_bucket         5119                      
-system.ruby.FLUSH.hit_latency_hist::samples            5                      
-system.ruby.FLUSH.hit_latency_hist::mean         3751                      
-system.ruby.FLUSH.hit_latency_hist::gmean  3739.394420                      
-system.ruby.FLUSH.hit_latency_hist::stdev   332.267212                      
-system.ruby.FLUSH.hit_latency_hist       |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           2     40.00%     40.00% |           2     40.00%     80.00% |           1     20.00%    100.00% |           0      0.00%    100.00%
-system.ruby.FLUSH.hit_latency_hist::total            5                      
+system.ruby.FLUSH.hit_latency_hist::samples            2                      
+system.ruby.FLUSH.hit_latency_hist::mean         2306                      
+system.ruby.FLUSH.hit_latency_hist::gmean  1583.874995                      
+system.ruby.FLUSH.hit_latency_hist::stdev  2370.221931                      
+system.ruby.FLUSH.hit_latency_hist       |           0      0.00%      0.00% |           1     50.00%     50.00% |           0      0.00%     50.00% |           0      0.00%     50.00% |           0      0.00%     50.00% |           0      0.00%     50.00% |           0      0.00%     50.00% |           1     50.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.FLUSH.hit_latency_hist::total            2                      
 system.ruby.L1Cache.hit_mach_latency_hist::bucket_size          512                      
 system.ruby.L1Cache.hit_mach_latency_hist::max_bucket         5119                      
-system.ruby.L1Cache.hit_mach_latency_hist::samples           76                      
-system.ruby.L1Cache.hit_mach_latency_hist::mean   256.355263                      
-system.ruby.L1Cache.hit_mach_latency_hist::gmean     4.735297                      
-system.ruby.L1Cache.hit_mach_latency_hist::stdev   937.091695                      
-system.ruby.L1Cache.hit_mach_latency_hist |          71     93.42%     93.42% |           0      0.00%     93.42% |           0      0.00%     93.42% |           0      0.00%     93.42% |           0      0.00%     93.42% |           0      0.00%     93.42% |           2      2.63%     96.05% |           2      2.63%     98.68% |           1      1.32%    100.00% |           0      0.00%    100.00%
-system.ruby.L1Cache.hit_mach_latency_hist::total           76                      
+system.ruby.L1Cache.hit_mach_latency_hist::samples           68                      
+system.ruby.L1Cache.hit_mach_latency_hist::mean    81.279412                      
+system.ruby.L1Cache.hit_mach_latency_hist::gmean     4.024527                      
+system.ruby.L1Cache.hit_mach_latency_hist::stdev   486.967063                      
+system.ruby.L1Cache.hit_mach_latency_hist |          66     97.06%     97.06% |           1      1.47%     98.53% |           0      0.00%     98.53% |           0      0.00%     98.53% |           0      0.00%     98.53% |           0      0.00%     98.53% |           0      0.00%     98.53% |           1      1.47%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache.hit_mach_latency_hist::total           68                      
 system.ruby.L2Cache.hit_mach_latency_hist::bucket_size          512                      
 system.ruby.L2Cache.hit_mach_latency_hist::max_bucket         5119                      
-system.ruby.L2Cache.hit_mach_latency_hist::samples           49                      
-system.ruby.L2Cache.hit_mach_latency_hist::mean  1546.857143                      
-system.ruby.L2Cache.hit_mach_latency_hist::gmean   255.879347                      
-system.ruby.L2Cache.hit_mach_latency_hist::stdev  1620.719799                      
-system.ruby.L2Cache.hit_mach_latency_hist |          26     53.06%     53.06% |           1      2.04%     55.10% |           0      0.00%     55.10% |           0      0.00%     55.10% |           1      2.04%     57.14% |           7     14.29%     71.43% |           8     16.33%     87.76% |           5     10.20%     97.96% |           1      2.04%    100.00% |           0      0.00%    100.00%
-system.ruby.L2Cache.hit_mach_latency_hist::total           49                      
+system.ruby.L2Cache.hit_mach_latency_hist::samples           50                      
+system.ruby.L2Cache.hit_mach_latency_hist::mean  1800.120000                      
+system.ruby.L2Cache.hit_mach_latency_hist::gmean   351.477196                      
+system.ruby.L2Cache.hit_mach_latency_hist::stdev  1623.164265                      
+system.ruby.L2Cache.hit_mach_latency_hist |          22     44.00%     44.00% |           1      2.00%     46.00% |           0      0.00%     46.00% |           0      0.00%     46.00% |           2      4.00%     50.00% |           8     16.00%     66.00% |          11     22.00%     88.00% |           5     10.00%     98.00% |           1      2.00%    100.00% |           0      0.00%    100.00%
+system.ruby.L2Cache.hit_mach_latency_hist::total           50                      
 system.ruby.Directory.miss_mach_latency_hist::bucket_size          512                      
 system.ruby.Directory.miss_mach_latency_hist::max_bucket         5119                      
-system.ruby.Directory.miss_mach_latency_hist::samples          846                      
-system.ruby.Directory.miss_mach_latency_hist::mean  3103.834515                      
-system.ruby.Directory.miss_mach_latency_hist::gmean  2684.081643                      
-system.ruby.Directory.miss_mach_latency_hist::stdev  1015.184360                      
-system.ruby.Directory.miss_mach_latency_hist |          60      7.09%      7.09% |          28      3.31%     10.40% |           1      0.12%     10.52% |           3      0.35%     10.87% |          14      1.65%     12.53% |         145     17.14%     29.67% |         352     41.61%     71.28% |         192     22.70%     93.97% |          40      4.73%     98.70% |          11      1.30%    100.00%
-system.ruby.Directory.miss_mach_latency_hist::total          846                      
+system.ruby.Directory.miss_mach_latency_hist::samples          873                      
+system.ruby.Directory.miss_mach_latency_hist::mean  3154.067583                      
+system.ruby.Directory.miss_mach_latency_hist::gmean  2724.443878                      
+system.ruby.Directory.miss_mach_latency_hist::stdev  1037.171502                      
+system.ruby.Directory.miss_mach_latency_hist |          65      7.45%      7.45% |          24      2.75%     10.19% |           4      0.46%     10.65% |           0      0.00%     10.65% |          22      2.52%     13.17% |         110     12.60%     25.77% |         330     37.80%     63.57% |         261     29.90%     93.47% |          50      5.73%     99.20% |           7      0.80%    100.00%
+system.ruby.Directory.miss_mach_latency_hist::total          873                      
 system.ruby.LD.L1Cache.hit_type_mach_latency_hist::bucket_size           16                      
 system.ruby.LD.L1Cache.hit_type_mach_latency_hist::max_bucket          159                      
-system.ruby.LD.L1Cache.hit_type_mach_latency_hist::samples            5                      
-system.ruby.LD.L1Cache.hit_type_mach_latency_hist::mean           24                      
-system.ruby.LD.L1Cache.hit_type_mach_latency_hist::gmean     3.987421                      
-system.ruby.LD.L1Cache.hit_type_mach_latency_hist::stdev    49.203658                      
-system.ruby.LD.L1Cache.hit_type_mach_latency_hist |           4     80.00%     80.00% |           0      0.00%     80.00% |           0      0.00%     80.00% |           0      0.00%     80.00% |           0      0.00%     80.00% |           0      0.00%     80.00% |           0      0.00%     80.00% |           1     20.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.LD.L1Cache.hit_type_mach_latency_hist::total            5                      
+system.ruby.LD.L1Cache.hit_type_mach_latency_hist::samples            4                      
+system.ruby.LD.L1Cache.hit_type_mach_latency_hist::mean    31.750000                      
+system.ruby.LD.L1Cache.hit_type_mach_latency_hist::gmean     8.056049                      
+system.ruby.LD.L1Cache.hit_type_mach_latency_hist::stdev    56.835288                      
+system.ruby.LD.L1Cache.hit_type_mach_latency_hist |           3     75.00%     75.00% |           0      0.00%     75.00% |           0      0.00%     75.00% |           0      0.00%     75.00% |           0      0.00%     75.00% |           0      0.00%     75.00% |           0      0.00%     75.00% |           1     25.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.L1Cache.hit_type_mach_latency_hist::total            4                      
 system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size          512                      
 system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket         5119                      
 system.ruby.LD.Directory.miss_type_mach_latency_hist::samples           45                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist::mean  3086.733333                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean  2560.470465                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev  1075.782430                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist |           4      8.89%      8.89% |           1      2.22%     11.11% |           0      0.00%     11.11% |           0      0.00%     11.11% |           1      2.22%     13.33% |           8     17.78%     31.11% |          15     33.33%     64.44% |          14     31.11%     95.56% |           2      4.44%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.Directory.miss_type_mach_latency_hist::mean  3472.155556                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean  3457.202829                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev   322.606216                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           5     11.11%     11.11% |          25     55.56%     66.67% |          15     33.33%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.LD.Directory.miss_type_mach_latency_hist::total           45                      
 system.ruby.ST.L1Cache.hit_type_mach_latency_hist::bucket_size           16                      
 system.ruby.ST.L1Cache.hit_type_mach_latency_hist::max_bucket          159                      
-system.ruby.ST.L1Cache.hit_type_mach_latency_hist::samples           65                      
-system.ruby.ST.L1Cache.hit_type_mach_latency_hist::mean     9.338462                      
-system.ruby.ST.L1Cache.hit_type_mach_latency_hist::gmean     2.941703                      
-system.ruby.ST.L1Cache.hit_type_mach_latency_hist::stdev    26.601384                      
-system.ruby.ST.L1Cache.hit_type_mach_latency_hist |          61     93.85%     93.85% |           0      0.00%     93.85% |           0      0.00%     93.85% |           0      0.00%     93.85% |           0      0.00%     93.85% |           0      0.00%     93.85% |           2      3.08%     96.92% |           2      3.08%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.ST.L1Cache.hit_type_mach_latency_hist::total           65                      
+system.ruby.ST.L1Cache.hit_type_mach_latency_hist::samples           61                      
+system.ruby.ST.L1Cache.hit_type_mach_latency_hist::mean    11.114754                      
+system.ruby.ST.L1Cache.hit_type_mach_latency_hist::gmean     2.994444                      
+system.ruby.ST.L1Cache.hit_type_mach_latency_hist::stdev    29.103893                      
+system.ruby.ST.L1Cache.hit_type_mach_latency_hist |          56     91.80%     91.80% |           0      0.00%     91.80% |           0      0.00%     91.80% |           0      0.00%     91.80% |           0      0.00%     91.80% |           0      0.00%     91.80% |           4      6.56%     98.36% |           1      1.64%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.L1Cache.hit_type_mach_latency_hist::total           61                      
 system.ruby.ST.L2Cache.hit_type_mach_latency_hist::bucket_size          512                      
 system.ruby.ST.L2Cache.hit_type_mach_latency_hist::max_bucket         5119                      
-system.ruby.ST.L2Cache.hit_type_mach_latency_hist::samples           40                      
-system.ruby.ST.L2Cache.hit_type_mach_latency_hist::mean  1890.950000                      
-system.ruby.ST.L2Cache.hit_type_mach_latency_hist::gmean   550.548503                      
-system.ruby.ST.L2Cache.hit_type_mach_latency_hist::stdev  1603.595990                      
-system.ruby.ST.L2Cache.hit_type_mach_latency_hist |          17     42.50%     42.50% |           1      2.50%     45.00% |           0      0.00%     45.00% |           0      0.00%     45.00% |           1      2.50%     47.50% |           7     17.50%     65.00% |           8     20.00%     85.00% |           5     12.50%     97.50% |           1      2.50%    100.00% |           0      0.00%    100.00%
-system.ruby.ST.L2Cache.hit_type_mach_latency_hist::total           40                      
+system.ruby.ST.L2Cache.hit_type_mach_latency_hist::samples           41                      
+system.ruby.ST.L2Cache.hit_type_mach_latency_hist::mean  2191.121951                      
+system.ruby.ST.L2Cache.hit_type_mach_latency_hist::gmean   793.662103                      
+system.ruby.ST.L2Cache.hit_type_mach_latency_hist::stdev  1535.123207                      
+system.ruby.ST.L2Cache.hit_type_mach_latency_hist |          13     31.71%     31.71% |           1      2.44%     34.15% |           0      0.00%     34.15% |           0      0.00%     34.15% |           2      4.88%     39.02% |           8     19.51%     58.54% |          11     26.83%     85.37% |           5     12.20%     97.56% |           1      2.44%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.L2Cache.hit_type_mach_latency_hist::total           41                      
 system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size          512                      
 system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket         5119                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist::samples          761                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist::mean  3246.367937                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean  2988.950366                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev   821.708353                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist |          28      3.68%      3.68% |          15      1.97%      5.65% |           1      0.13%      5.78% |           3      0.39%      6.18% |          13      1.71%      7.88% |         137     18.00%     25.89% |         337     44.28%     70.17% |         178     23.39%     93.56% |          38      4.99%     98.55% |          11      1.45%    100.00%
-system.ruby.ST.Directory.miss_type_mach_latency_hist::total          761                      
-system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::bucket_size            1                      
-system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::max_bucket            9                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist::samples          787                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist::mean  3279.428208                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean  2987.001628                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev   876.519166                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist |          35      4.45%      4.45% |          13      1.65%      6.10% |           4      0.51%      6.61% |           0      0.00%      6.61% |          22      2.80%      9.40% |         105     13.34%     22.74% |         305     38.75%     61.50% |         246     31.26%     92.76% |          50      6.35%     99.11% |           7      0.89%    100.00%
+system.ruby.ST.Directory.miss_type_mach_latency_hist::total          787                      
+system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::bucket_size           16                      
+system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::max_bucket          159                      
 system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::samples            1                      
-system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::mean            1                      
-system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::gmean            1                      
+system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::mean          110                      
+system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::gmean   110.000000                      
 system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::stdev          nan                      
-system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist |           0      0.00%      0.00% |           1    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           1    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::total            1                      
 system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::bucket_size           16                      
 system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::max_bucket          159                      
 system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::samples            9                      
-system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::mean    17.555556                      
-system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::gmean     8.493767                      
-system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::stdev    33.574958                      
-system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist |           8     88.89%     88.89% |           0      0.00%     88.89% |           0      0.00%     88.89% |           0      0.00%     88.89% |           0      0.00%     88.89% |           0      0.00%     88.89% |           1     11.11%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::mean    18.888889                      
+system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::gmean     8.598482                      
+system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::stdev    37.210363                      
+system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist |           8     88.89%     88.89% |           0      0.00%     88.89% |           0      0.00%     88.89% |           0      0.00%     88.89% |           0      0.00%     88.89% |           0      0.00%     88.89% |           0      0.00%     88.89% |           1     11.11%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::total            9                      
 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size          128                      
 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket         1279                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples           40                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean   411.375000                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean   365.532878                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev   184.831550                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist |           2      5.00%      5.00% |           6     15.00%     20.00% |          11     27.50%     47.50% |           9     22.50%     70.00% |           7     17.50%     87.50% |           4     10.00%     97.50% |           1      2.50%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total           40                      
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples           41                      
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean   398.634146                      
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean   358.713406                      
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev   185.068468                      
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist |           1      2.44%      2.44% |           8     19.51%     21.95% |          11     26.83%     48.78% |          10     24.39%     73.17% |           7     17.07%     90.24% |           3      7.32%     97.56% |           0      0.00%     97.56% |           1      2.44%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total           41                      
 system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist::bucket_size          512                      
 system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist::max_bucket         5119                      
-system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist::samples            5                      
-system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist::mean         3751                      
-system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist::gmean  3739.394420                      
-system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist::stdev   332.267212                      
-system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           2     40.00%     40.00% |           2     40.00%     80.00% |           1     20.00%    100.00% |           0      0.00%    100.00%
-system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist::total            5                      
-system.ruby.L1Cache_Controller.Load                52      0.00%      0.00%
-system.ruby.L1Cache_Controller.Ifetch              53      0.00%      0.00%
-system.ruby.L1Cache_Controller.Store              888      0.00%      0.00%
-system.ruby.L1Cache_Controller.L2_Replacement          840      0.00%      0.00%
-system.ruby.L1Cache_Controller.L1_to_L2         16587      0.00%      0.00%
+system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist::samples            2                      
+system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist::mean         2306                      
+system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist::gmean  1583.874995                      
+system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist::stdev  2370.221931                      
+system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist |           0      0.00%      0.00% |           1     50.00%     50.00% |           0      0.00%     50.00% |           0      0.00%     50.00% |           0      0.00%     50.00% |           0      0.00%     50.00% |           0      0.00%     50.00% |           1     50.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist::total            2                      
+system.ruby.L1Cache_Controller.Load                49      0.00%      0.00%
+system.ruby.L1Cache_Controller.Ifetch              55      0.00%      0.00%
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 system.ruby.L1Cache_Controller.Trigger_L2_to_L1I            9      0.00%      0.00%
 system.ruby.L1Cache_Controller.Complete_L2_to_L1           50      0.00%      0.00%
-system.ruby.L1Cache_Controller.Exclusive_Data          850      0.00%      0.00%
-system.ruby.L1Cache_Controller.Writeback_Ack          843      0.00%      0.00%
-system.ruby.L1Cache_Controller.All_acks_no_sharers          850      0.00%      0.00%
-system.ruby.L1Cache_Controller.Flush_line            5      0.00%      0.00%
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 system.ruby.L1Cache_Controller.Block_Ack            1      0.00%      0.00%
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-system.ruby.L1Cache_Controller.I.Ifetch            40      0.00%      0.00%
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 system.ruby.L1Cache_Controller.MM.Trigger_L2_to_L1I            9      0.00%      0.00%
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 system.ruby.L1Cache_Controller.MMR.Ifetch            9      0.00%      0.00%
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 system.ruby.L1Cache_Controller.MM_F.Block_Ack            1      0.00%      0.00%
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-system.ruby.L1Cache_Controller.MM_WF.All_acks_no_sharers            4      0.00%      0.00%
-system.ruby.Directory_Controller.GETX             761      0.00%      0.00%
+system.ruby.L1Cache_Controller.IM_F.Exclusive_Data            1      0.00%      0.00%
+system.ruby.L1Cache_Controller.MM_WF.All_acks_no_sharers            1      0.00%      0.00%
+system.ruby.Directory_Controller.GETX             787      0.00%      0.00%
 system.ruby.Directory_Controller.GETS              87      0.00%      0.00%
-system.ruby.Directory_Controller.PUT              913      0.00%      0.00%
-system.ruby.Directory_Controller.UnblockM          845      0.00%      0.00%
-system.ruby.Directory_Controller.Writeback_Exclusive_Clean           75      0.00%      0.00%
-system.ruby.Directory_Controller.Writeback_Exclusive_Dirty          767      0.00%      0.00%
-system.ruby.Directory_Controller.Memory_Data          850      0.00%      0.00%
-system.ruby.Directory_Controller.Memory_Ack          767      0.00%      0.00%
-system.ruby.Directory_Controller.GETF               5      0.00%      0.00%
-system.ruby.Directory_Controller.PUTF               5      0.00%      0.00%
-system.ruby.Directory_Controller.NO.PUT           838      0.00%      0.00%
+system.ruby.Directory_Controller.PUT              932      0.00%      0.00%
+system.ruby.Directory_Controller.UnblockM          870      0.00%      0.00%
+system.ruby.Directory_Controller.Writeback_Exclusive_Clean           76      0.00%      0.00%
+system.ruby.Directory_Controller.Writeback_Exclusive_Dirty          789      0.00%      0.00%
+system.ruby.Directory_Controller.Memory_Data          874      0.00%      0.00%
+system.ruby.Directory_Controller.Memory_Ack          789      0.00%      0.00%
+system.ruby.Directory_Controller.GETF               2      0.00%      0.00%
+system.ruby.Directory_Controller.PUTF               2      0.00%      0.00%
+system.ruby.Directory_Controller.NO.PUT           866      0.00%      0.00%
 system.ruby.Directory_Controller.NO.GETF            1      0.00%      0.00%
-system.ruby.Directory_Controller.E.GETX           761      0.00%      0.00%
-system.ruby.Directory_Controller.E.GETS            85      0.00%      0.00%
-system.ruby.Directory_Controller.E.GETF             4      0.00%      0.00%
-system.ruby.Directory_Controller.NO_B.PUT           75      0.00%      0.00%
-system.ruby.Directory_Controller.NO_B.UnblockM          845      0.00%      0.00%
-system.ruby.Directory_Controller.NO_B_W.Memory_Data          846      0.00%      0.00%
+system.ruby.Directory_Controller.E.GETX           787      0.00%      0.00%
+system.ruby.Directory_Controller.E.GETS            86      0.00%      0.00%
+system.ruby.Directory_Controller.E.GETF             1      0.00%      0.00%
+system.ruby.Directory_Controller.NO_B.PUT           66      0.00%      0.00%
+system.ruby.Directory_Controller.NO_B.UnblockM          870      0.00%      0.00%
+system.ruby.Directory_Controller.NO_B_W.Memory_Data          873      0.00%      0.00%
 system.ruby.Directory_Controller.WB.GETS            1      0.00%      0.00%
-system.ruby.Directory_Controller.WB.Writeback_Exclusive_Clean           75      0.00%      0.00%
-system.ruby.Directory_Controller.WB.Writeback_Exclusive_Dirty          767      0.00%      0.00%
-system.ruby.Directory_Controller.WB_E_W.GETS            1      0.00%      0.00%
-system.ruby.Directory_Controller.WB_E_W.Memory_Ack          767      0.00%      0.00%
-system.ruby.Directory_Controller.NO_F.PUTF            5      0.00%      0.00%
-system.ruby.Directory_Controller.NO_F_W.Memory_Data            4      0.00%      0.00%
+system.ruby.Directory_Controller.WB.Writeback_Exclusive_Clean           76      0.00%      0.00%
+system.ruby.Directory_Controller.WB.Writeback_Exclusive_Dirty          789      0.00%      0.00%
+system.ruby.Directory_Controller.WB_E_W.Memory_Ack          789      0.00%      0.00%
+system.ruby.Directory_Controller.NO_F.PUTF            2      0.00%      0.00%
+system.ruby.Directory_Controller.NO_F_W.Memory_Data            1      0.00%      0.00%
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt
index 83714cb16..f36d287b9 100644
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt
@@ -1,276 +1,285 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000222                       # Number of seconds simulated
-sim_ticks                                      221941                       # Number of ticks simulated
-final_tick                                     221941                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.000228                       # Number of seconds simulated
+sim_ticks                                      228001                       # Number of ticks simulated
+final_tick                                     228001                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_tick_rate                                2110232                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 170916                       # Number of bytes of host memory used
-host_seconds                                     0.11                       # Real time elapsed on the host
+host_tick_rate                                3675993                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 127868                       # Number of bytes of host memory used
+host_seconds                                     0.06                       # Real time elapsed on the host
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                             1                       # Clock period in ticks
 system.ruby.clk_domain.clock                        1                       # Clock period in ticks
-system.ruby.delayHist::bucket_size                  4                       # delay histogram for all message
-system.ruby.delayHist::max_bucket                  39                       # delay histogram for all message
-system.ruby.delayHist::samples                   1828                       # delay histogram for all message
-system.ruby.delayHist::mean                  0.560175                       # delay histogram for all message
-system.ruby.delayHist::stdev                 2.065483                       # delay histogram for all message
-system.ruby.delayHist                    |        1690     92.45%     92.45% |          89      4.87%     97.32% |          33      1.81%     99.12% |          11      0.60%     99.73% |           4      0.22%     99.95% |           0      0.00%     99.95% |           1      0.05%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for all message
-system.ruby.delayHist::total                     1828                       # delay histogram for all message
+system.ruby.delayHist::bucket_size                  2                       # delay histogram for all message
+system.ruby.delayHist::max_bucket                  19                       # delay histogram for all message
+system.ruby.delayHist::samples                   1875                       # delay histogram for all message
+system.ruby.delayHist::mean                  0.413867                       # delay histogram for all message
+system.ruby.delayHist::stdev                 1.755437                       # delay histogram for all message
+system.ruby.delayHist                    |        1737     92.64%     92.64% |          40      2.13%     94.77% |          28      1.49%     96.27% |          28      1.49%     97.76% |          24      1.28%     99.04% |           9      0.48%     99.52% |           3      0.16%     99.68% |           1      0.05%     99.73% |           3      0.16%     99.89% |           2      0.11%    100.00% # delay histogram for all message
+system.ruby.delayHist::total                     1875                       # delay histogram for all message
 system.ruby.outstanding_req_hist::bucket_size            2                      
 system.ruby.outstanding_req_hist::max_bucket           19                      
-system.ruby.outstanding_req_hist::samples          969                      
-system.ruby.outstanding_req_hist::mean      15.737874                      
-system.ruby.outstanding_req_hist::gmean     15.630840                      
-system.ruby.outstanding_req_hist::stdev      1.200645                      
-system.ruby.outstanding_req_hist         |           1      0.10%      0.10% |           2      0.21%      0.31% |           2      0.21%      0.52% |           3      0.31%      0.83% |           2      0.21%      1.03% |           2      0.21%      1.24% |           2      0.21%      1.44% |         119     12.28%     13.73% |         836     86.27%    100.00% |           0      0.00%    100.00%
-system.ruby.outstanding_req_hist::total           969                      
+system.ruby.outstanding_req_hist::samples          993                      
+system.ruby.outstanding_req_hist::mean      15.769386                      
+system.ruby.outstanding_req_hist::gmean     15.669183                      
+system.ruby.outstanding_req_hist::stdev      1.147486                      
+system.ruby.outstanding_req_hist         |           1      0.10%      0.10% |           2      0.20%      0.30% |           2      0.20%      0.50% |           2      0.20%      0.70% |           2      0.20%      0.91% |           2      0.20%      1.11% |           2      0.20%      1.31% |         106     10.67%     11.98% |         874     88.02%    100.00% |           0      0.00%    100.00%
+system.ruby.outstanding_req_hist::total           993                      
 system.ruby.latency_hist::bucket_size            1024                      
 system.ruby.latency_hist::max_bucket            10239                      
-system.ruby.latency_hist::samples                 954                      
-system.ruby.latency_hist::mean            3683.388889                      
-system.ruby.latency_hist::gmean           3615.866127                      
-system.ruby.latency_hist::stdev            578.018149                      
-system.ruby.latency_hist                 |           6      0.63%      0.63% |           5      0.52%      1.15% |          97     10.17%     11.32% |         613     64.26%     75.58% |         232     24.32%     99.90% |           1      0.10%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.latency_hist::total                   954                      
+system.ruby.latency_hist::samples                 978                      
+system.ruby.latency_hist::mean            3693.343558                      
+system.ruby.latency_hist::gmean           3643.123362                      
+system.ruby.latency_hist::stdev            533.362444                      
+system.ruby.latency_hist                 |           4      0.41%      0.41% |           4      0.41%      0.82% |          73      7.46%      8.28% |         689     70.45%     78.73% |         206     21.06%     99.80% |           2      0.20%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.latency_hist::total                   978                      
 system.ruby.hit_latency_hist::bucket_size          512                      
 system.ruby.hit_latency_hist::max_bucket         5119                      
-system.ruby.hit_latency_hist::samples              38                      
-system.ruby.hit_latency_hist::mean        3245.526316                      
-system.ruby.hit_latency_hist::gmean       3205.871342                      
-system.ruby.hit_latency_hist::stdev        508.824864                      
-system.ruby.hit_latency_hist             |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           1      2.63%      2.63% |           2      5.26%      7.89% |          13     34.21%     42.11% |          14     36.84%     78.95% |           5     13.16%     92.11% |           3      7.89%    100.00% |           0      0.00%    100.00%
-system.ruby.hit_latency_hist::total                38                      
+system.ruby.hit_latency_hist::samples              39                      
+system.ruby.hit_latency_hist::mean        3214.641026                      
+system.ruby.hit_latency_hist::gmean       3186.126692                      
+system.ruby.hit_latency_hist::stdev        431.722041                      
+system.ruby.hit_latency_hist             |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           3      7.69%      7.69% |          10     25.64%     33.33% |          17     43.59%     76.92% |           8     20.51%     97.44% |           1      2.56%    100.00% |           0      0.00%    100.00%
+system.ruby.hit_latency_hist::total                39                      
 system.ruby.miss_latency_hist::bucket_size         1024                      
 system.ruby.miss_latency_hist::max_bucket        10239                      
-system.ruby.miss_latency_hist::samples            916                      
-system.ruby.miss_latency_hist::mean       3701.553493                      
-system.ruby.miss_latency_hist::gmean      3633.963773                      
-system.ruby.miss_latency_hist::stdev       573.775637                      
-system.ruby.miss_latency_hist            |           6      0.66%      0.66% |           4      0.44%      1.09% |          82      8.95%     10.04% |         594     64.85%     74.89% |         229     25.00%     99.89% |           1      0.11%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.miss_latency_hist::total              916                      
-system.ruby.Directory.incomplete_times            916                      
+system.ruby.miss_latency_hist::samples            939                      
+system.ruby.miss_latency_hist::mean       3713.225772                      
+system.ruby.miss_latency_hist::gmean      3663.461061                      
+system.ruby.miss_latency_hist::stdev       528.042705                      
+system.ruby.miss_latency_hist            |           4      0.43%      0.43% |           4      0.43%      0.85% |          60      6.39%      7.24% |         664     70.71%     77.96% |         205     21.83%     99.79% |           2      0.21%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.miss_latency_hist::total              939                      
+system.ruby.Directory.incomplete_times            939                      
 system.ruby.memctrl_clk_domain.clock                3                       # Clock period in ticks
-system.ruby.l1_cntrl0.cacheMemory.demand_hits           38                       # Number of cache demand hits
-system.ruby.l1_cntrl0.cacheMemory.demand_misses          917                       # Number of cache demand misses
-system.ruby.l1_cntrl0.cacheMemory.demand_accesses          955                       # Number of cache demand accesses
+system.ruby.l1_cntrl0.cacheMemory.demand_hits           39                       # Number of cache demand hits
+system.ruby.l1_cntrl0.cacheMemory.demand_misses          941                       # Number of cache demand misses
+system.ruby.l1_cntrl0.cacheMemory.demand_accesses          980                       # Number of cache demand accesses
 system.ruby.l1_cntrl0.sequencer.store_waiting_on_load           10                       # Number of times a store aliased with a pending load
-system.ruby.l1_cntrl0.sequencer.store_waiting_on_store          116                       # Number of times a store aliased with a pending store
-system.ruby.l1_cntrl0.sequencer.load_waiting_on_store            9                       # Number of times a load aliased with a pending store
+system.ruby.l1_cntrl0.sequencer.store_waiting_on_store          112                       # Number of times a store aliased with a pending store
+system.ruby.l1_cntrl0.sequencer.load_waiting_on_store            6                       # Number of times a load aliased with a pending store
 system.ruby.l1_cntrl0.sequencer.load_waiting_on_load            2                       # Number of times a load aliased with a pending load
-system.ruby.network.routers0.percent_links_utilized     2.061246                      
-system.ruby.network.routers0.msg_count.Control::2          916                      
-system.ruby.network.routers0.msg_count.Data::2          914                      
-system.ruby.network.routers0.msg_count.Response_Data::4          916                      
-system.ruby.network.routers0.msg_count.Writeback_Control::3          913                      
-system.ruby.network.routers0.msg_bytes.Control::2         7328                      
-system.ruby.network.routers0.msg_bytes.Data::2        65808                      
-system.ruby.network.routers0.msg_bytes.Response_Data::4        65952                      
-system.ruby.network.routers0.msg_bytes.Writeback_Control::3         7304                      
-system.ruby.dir_cntrl0.memBuffer.memReq          1830                       # Total number of memory requests
-system.ruby.dir_cntrl0.memBuffer.memRead          916                       # Number of memory reads
-system.ruby.dir_cntrl0.memBuffer.memWrite          914                       # Number of memory writes
-system.ruby.dir_cntrl0.memBuffer.memRefresh         1542                       # Number of memory refreshes
-system.ruby.dir_cntrl0.memBuffer.memWaitCycles         1745                       # Delay stalled at the head of the bank queue
-system.ruby.dir_cntrl0.memBuffer.memInputQ          182                       # Delay in the input queue
-system.ruby.dir_cntrl0.memBuffer.memBankQ            3                       # Delay behind the head of the bank queue
-system.ruby.dir_cntrl0.memBuffer.totalStalls         1930                       # Total number of stall cycles
-system.ruby.dir_cntrl0.memBuffer.stallsPerReq     1.054645                       # Expected number of stall cycles per request
-system.ruby.dir_cntrl0.memBuffer.memBankBusy          343                       # memory stalls due to busy bank
-system.ruby.dir_cntrl0.memBuffer.memBusBusy          617                       # memory stalls due to busy bus
-system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy          556                       # memory stalls due to read write turnaround
-system.ruby.dir_cntrl0.memBuffer.memDataBusBusy           62                       # memory stalls due to read read turnaround
-system.ruby.dir_cntrl0.memBuffer.memArbWait          167                       # memory stalls due to arbitration
-system.ruby.dir_cntrl0.memBuffer.memBankCount |          64      3.50%      3.50% |          60      3.28%      6.78% |          44      2.40%      9.18% |          96      5.25%     14.43% |         107      5.85%     20.27% |          64      3.50%     23.77% |          62      3.39%     27.16% |          38      2.08%     29.23% |          55      3.01%     32.24% |          54      2.95%     35.19% |          54      2.95%     38.14% |          36      1.97%     40.11% |          48      2.62%     42.73% |          34      1.86%     44.59% |          66      3.61%     48.20% |          48      2.62%     50.82% |          56      3.06%     53.88% |          54      2.95%     56.83% |          60      3.28%     60.11% |          70      3.83%     63.93% |          56      3.06%     66.99% |          62      3.39%     70.38% |          44      2.40%     72.79% |          62      3.39%     76.17% |          48      2.62%     78.80% |          58      3.17%     81.97% |          64      3.50%     85.46% |          72      3.93%     89.40% |          46      2.51%     91.91% |          46      2.51%     94.43% |          36      1.97%     96.39% |          66      3.61%    100.00% # Number of accesses per bank
-system.ruby.dir_cntrl0.memBuffer.memBankCount::total         1830                       # Number of accesses per bank
-system.ruby.network.routers1.percent_links_utilized     2.061246                      
-system.ruby.network.routers1.msg_count.Control::2          916                      
-system.ruby.network.routers1.msg_count.Data::2          914                      
-system.ruby.network.routers1.msg_count.Response_Data::4          916                      
-system.ruby.network.routers1.msg_count.Writeback_Control::3          913                      
-system.ruby.network.routers1.msg_bytes.Control::2         7328                      
-system.ruby.network.routers1.msg_bytes.Data::2        65808                      
-system.ruby.network.routers1.msg_bytes.Response_Data::4        65952                      
-system.ruby.network.routers1.msg_bytes.Writeback_Control::3         7304                      
-system.ruby.network.routers2.percent_links_utilized     2.061246                      
-system.ruby.network.routers2.msg_count.Control::2          916                      
-system.ruby.network.routers2.msg_count.Data::2          914                      
-system.ruby.network.routers2.msg_count.Response_Data::4          916                      
-system.ruby.network.routers2.msg_count.Writeback_Control::3          913                      
-system.ruby.network.routers2.msg_bytes.Control::2         7328                      
-system.ruby.network.routers2.msg_bytes.Data::2        65808                      
-system.ruby.network.routers2.msg_bytes.Response_Data::4        65952                      
-system.ruby.network.routers2.msg_bytes.Writeback_Control::3         7304                      
-system.ruby.network.msg_count.Control            2748                      
-system.ruby.network.msg_count.Data               2742                      
-system.ruby.network.msg_count.Response_Data         2748                      
-system.ruby.network.msg_count.Writeback_Control         2739                      
-system.ruby.network.msg_byte.Control            21984                      
-system.ruby.network.msg_byte.Data              197424                      
-system.ruby.network.msg_byte.Response_Data       197856                      
-system.ruby.network.msg_byte.Writeback_Control        21912                      
-system.ruby.network.routers0.throttle0.link_utilization     2.062936                      
-system.ruby.network.routers0.throttle0.msg_count.Response_Data::4          916                      
-system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3          913                      
-system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4        65952                      
-system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3         7304                      
-system.ruby.network.routers0.throttle1.link_utilization     2.059556                      
-system.ruby.network.routers0.throttle1.msg_count.Control::2          916                      
-system.ruby.network.routers0.throttle1.msg_count.Data::2          914                      
-system.ruby.network.routers0.throttle1.msg_bytes.Control::2         7328                      
-system.ruby.network.routers0.throttle1.msg_bytes.Data::2        65808                      
-system.ruby.network.routers1.throttle0.link_utilization     2.059556                      
-system.ruby.network.routers1.throttle0.msg_count.Control::2          916                      
-system.ruby.network.routers1.throttle0.msg_count.Data::2          914                      
-system.ruby.network.routers1.throttle0.msg_bytes.Control::2         7328                      
-system.ruby.network.routers1.throttle0.msg_bytes.Data::2        65808                      
-system.ruby.network.routers1.throttle1.link_utilization     2.062936                      
-system.ruby.network.routers1.throttle1.msg_count.Response_Data::4          916                      
-system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3          913                      
-system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4        65952                      
-system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3         7304                      
-system.ruby.network.routers2.throttle0.link_utilization     2.062936                      
-system.ruby.network.routers2.throttle0.msg_count.Response_Data::4          916                      
-system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3          913                      
-system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4        65952                      
-system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3         7304                      
-system.ruby.network.routers2.throttle1.link_utilization     2.059556                      
-system.ruby.network.routers2.throttle1.msg_count.Control::2          916                      
-system.ruby.network.routers2.throttle1.msg_count.Data::2          914                      
-system.ruby.network.routers2.throttle1.msg_bytes.Control::2         7328                      
-system.ruby.network.routers2.throttle1.msg_bytes.Data::2        65808                      
+system.ruby.network.routers0.percent_links_utilized     2.055583                      
+system.ruby.network.routers0.msg_count.Control::2          939                      
+system.ruby.network.routers0.msg_count.Data::2          936                      
+system.ruby.network.routers0.msg_count.Response_Data::4          939                      
+system.ruby.network.routers0.msg_count.Writeback_Control::3          936                      
+system.ruby.network.routers0.msg_bytes.Control::2         7512                      
+system.ruby.network.routers0.msg_bytes.Data::2        67392                      
+system.ruby.network.routers0.msg_bytes.Response_Data::4        67608                      
+system.ruby.network.routers0.msg_bytes.Writeback_Control::3         7488                      
+system.ruby.dir_cntrl0.memBuffer.memReq          1875                       # Total number of memory requests
+system.ruby.dir_cntrl0.memBuffer.memRead          939                       # Number of memory reads
+system.ruby.dir_cntrl0.memBuffer.memWrite          936                       # Number of memory writes
+system.ruby.dir_cntrl0.memBuffer.memRefresh         1584                       # Number of memory refreshes
+system.ruby.dir_cntrl0.memBuffer.memWaitCycles         1797                       # Delay stalled at the head of the bank queue
+system.ruby.dir_cntrl0.memBuffer.memInputQ          156                       # Delay in the input queue
+system.ruby.dir_cntrl0.memBuffer.memBankQ           18                       # Delay behind the head of the bank queue
+system.ruby.dir_cntrl0.memBuffer.totalStalls         1971                       # Total number of stall cycles
+system.ruby.dir_cntrl0.memBuffer.stallsPerReq     1.051200                       # Expected number of stall cycles per request
+system.ruby.dir_cntrl0.memBuffer.memBankBusy          297                       # memory stalls due to busy bank
+system.ruby.dir_cntrl0.memBuffer.memBusBusy          648                       # memory stalls due to busy bus
+system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy          605                       # memory stalls due to read write turnaround
+system.ruby.dir_cntrl0.memBuffer.memDataBusBusy           60                       # memory stalls due to read read turnaround
+system.ruby.dir_cntrl0.memBuffer.memArbWait          187                       # memory stalls due to arbitration
+system.ruby.dir_cntrl0.memBuffer.memBankCount |          59      3.15%      3.15% |          68      3.63%      6.77% |          62      3.31%     10.08% |          78      4.16%     14.24% |         119      6.35%     20.59% |          54      2.88%     23.47% |          61      3.25%     26.72% |          54      2.88%     29.60% |          40      2.13%     31.73% |          64      3.41%     35.15% |          46      2.45%     37.60% |          60      3.20%     40.80% |          54      2.88%     43.68% |          68      3.63%     47.31% |          52      2.77%     50.08% |          44      2.35%     52.43% |          50      2.67%     55.09% |          42      2.24%     57.33% |          44      2.35%     59.68% |          64      3.41%     63.09% |          64      3.41%     66.51% |          44      2.35%     68.85% |          64      3.41%     72.27% |          52      2.77%     75.04% |          62      3.31%     78.35% |          58      3.09%     81.44% |          60      3.20%     84.64% |          56      2.99%     87.63% |          52      2.77%     90.40% |          64      3.41%     93.81% |          52      2.77%     96.59% |          64      3.41%    100.00% # Number of accesses per bank
+system.ruby.dir_cntrl0.memBuffer.memBankCount::total         1875                       # Number of accesses per bank
+system.ruby.network.routers1.percent_links_utilized     2.055912                      
+system.ruby.network.routers1.msg_count.Control::2          939                      
+system.ruby.network.routers1.msg_count.Data::2          936                      
+system.ruby.network.routers1.msg_count.Response_Data::4          939                      
+system.ruby.network.routers1.msg_count.Writeback_Control::3          936                      
+system.ruby.network.routers1.msg_bytes.Control::2         7512                      
+system.ruby.network.routers1.msg_bytes.Data::2        67392                      
+system.ruby.network.routers1.msg_bytes.Response_Data::4        67608                      
+system.ruby.network.routers1.msg_bytes.Writeback_Control::3         7488                      
+system.ruby.network.routers2.percent_links_utilized     2.055912                      
+system.ruby.network.routers2.msg_count.Control::2          939                      
+system.ruby.network.routers2.msg_count.Data::2          936                      
+system.ruby.network.routers2.msg_count.Response_Data::4          939                      
+system.ruby.network.routers2.msg_count.Writeback_Control::3          936                      
+system.ruby.network.routers2.msg_bytes.Control::2         7512                      
+system.ruby.network.routers2.msg_bytes.Data::2        67392                      
+system.ruby.network.routers2.msg_bytes.Response_Data::4        67608                      
+system.ruby.network.routers2.msg_bytes.Writeback_Control::3         7488                      
+system.ruby.network.msg_count.Control            2817                      
+system.ruby.network.msg_count.Data               2808                      
+system.ruby.network.msg_count.Response_Data         2817                      
+system.ruby.network.msg_count.Writeback_Control         2808                      
+system.ruby.network.msg_byte.Control            22536                      
+system.ruby.network.msg_byte.Data              202176                      
+system.ruby.network.msg_byte.Response_Data       202824                      
+system.ruby.network.msg_byte.Writeback_Control        22464                      
+system.ruby.network.routers0.throttle0.link_utilization     2.057886                      
+system.ruby.network.routers0.throttle0.msg_count.Response_Data::4          939                      
+system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3          936                      
+system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4        67608                      
+system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3         7488                      
+system.ruby.network.routers0.throttle1.link_utilization     2.053280                      
+system.ruby.network.routers0.throttle1.msg_count.Control::2          939                      
+system.ruby.network.routers0.throttle1.msg_count.Data::2          936                      
+system.ruby.network.routers0.throttle1.msg_bytes.Control::2         7512                      
+system.ruby.network.routers0.throttle1.msg_bytes.Data::2        67392                      
+system.ruby.network.routers1.throttle0.link_utilization     2.053280                      
+system.ruby.network.routers1.throttle0.msg_count.Control::2          939                      
+system.ruby.network.routers1.throttle0.msg_count.Data::2          936                      
+system.ruby.network.routers1.throttle0.msg_bytes.Control::2         7512                      
+system.ruby.network.routers1.throttle0.msg_bytes.Data::2        67392                      
+system.ruby.network.routers1.throttle1.link_utilization     2.058544                      
+system.ruby.network.routers1.throttle1.msg_count.Response_Data::4          939                      
+system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3          936                      
+system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4        67608                      
+system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3         7488                      
+system.ruby.network.routers2.throttle0.link_utilization     2.058544                      
+system.ruby.network.routers2.throttle0.msg_count.Response_Data::4          939                      
+system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3          936                      
+system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4        67608                      
+system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3         7488                      
+system.ruby.network.routers2.throttle1.link_utilization     2.053280                      
+system.ruby.network.routers2.throttle1.msg_count.Control::2          939                      
+system.ruby.network.routers2.throttle1.msg_count.Data::2          936                      
+system.ruby.network.routers2.throttle1.msg_bytes.Control::2         7512                      
+system.ruby.network.routers2.throttle1.msg_bytes.Data::2        67392                      
 system.ruby.delayVCHist.vnet_1::bucket_size            2                       # delay histogram for vnet_1
 system.ruby.delayVCHist.vnet_1::max_bucket           19                       # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::samples           916                       # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::mean         0.530568                       # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::stdev        1.830567                       # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1           |         824     89.96%     89.96% |          19      2.07%     92.03% |          30      3.28%     95.31% |          28      3.06%     98.36% |           3      0.33%     98.69% |           6      0.66%     99.34% |           4      0.44%     99.78% |           2      0.22%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::total             916                       # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_2::bucket_size            4                       # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::max_bucket           39                       # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::samples           912                       # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::mean         0.589912                       # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::stdev        2.277805                       # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2           |         847     92.87%     92.87% |          31      3.40%     96.27% |          24      2.63%     98.90% |           5      0.55%     99.45% |           4      0.44%     99.89% |           0      0.00%     99.89% |           1      0.11%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::total             912                       # delay histogram for vnet_2
+system.ruby.delayVCHist.vnet_1::samples           939                       # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1::mean         0.470714                       # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1::stdev        1.775198                       # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1           |         854     90.95%     90.95% |          28      2.98%     93.93% |          18      1.92%     95.85% |          17      1.81%     97.66% |          12      1.28%     98.94% |           5      0.53%     99.47% |           3      0.32%     99.79% |           1      0.11%     99.89% |           1      0.11%    100.00% |           0      0.00%    100.00% # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1::total             939                       # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_2::bucket_size            2                       # delay histogram for vnet_2
+system.ruby.delayVCHist.vnet_2::max_bucket           19                       # delay histogram for vnet_2
+system.ruby.delayVCHist.vnet_2::samples           936                       # delay histogram for vnet_2
+system.ruby.delayVCHist.vnet_2::mean         0.356838                       # delay histogram for vnet_2
+system.ruby.delayVCHist.vnet_2::stdev        1.734462                       # delay histogram for vnet_2
+system.ruby.delayVCHist.vnet_2           |         883     94.34%     94.34% |          12      1.28%     95.62% |          10      1.07%     96.69% |          11      1.18%     97.86% |          12      1.28%     99.15% |           4      0.43%     99.57% |           0      0.00%     99.57% |           0      0.00%     99.57% |           2      0.21%     99.79% |           2      0.21%    100.00% # delay histogram for vnet_2
+system.ruby.delayVCHist.vnet_2::total             936                       # delay histogram for vnet_2
 system.ruby.LD.latency_hist::bucket_size          512                      
 system.ruby.LD.latency_hist::max_bucket          5119                      
-system.ruby.LD.latency_hist::samples               42                      
-system.ruby.LD.latency_hist::mean         3722.095238                      
-system.ruby.LD.latency_hist::gmean        3693.389751                      
-system.ruby.LD.latency_hist::stdev         463.961143                      
-system.ruby.LD.latency_hist              |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           5     11.90%     11.90% |          11     26.19%     38.10% |          18     42.86%     80.95% |           8     19.05%    100.00% |           0      0.00%    100.00%
-system.ruby.LD.latency_hist::total                 42                      
+system.ruby.LD.latency_hist::samples               50                      
+system.ruby.LD.latency_hist::mean         3717.400000                      
+system.ruby.LD.latency_hist::gmean        3691.585103                      
+system.ruby.LD.latency_hist::stdev         435.779386                      
+system.ruby.LD.latency_hist              |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           2      4.00%      4.00% |          18     36.00%     40.00% |          20     40.00%     80.00% |          10     20.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.latency_hist::total                 50                      
+system.ruby.LD.hit_latency_hist::bucket_size          512                      
+system.ruby.LD.hit_latency_hist::max_bucket         5119                      
+system.ruby.LD.hit_latency_hist::samples            2                      
+system.ruby.LD.hit_latency_hist::mean            2856                      
+system.ruby.LD.hit_latency_hist::gmean    2844.049050                      
+system.ruby.LD.hit_latency_hist::stdev     369.109740                      
+system.ruby.LD.hit_latency_hist          |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           1     50.00%     50.00% |           1     50.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.hit_latency_hist::total              2                      
 system.ruby.LD.miss_latency_hist::bucket_size          512                      
 system.ruby.LD.miss_latency_hist::max_bucket         5119                      
-system.ruby.LD.miss_latency_hist::samples           42                      
-system.ruby.LD.miss_latency_hist::mean    3722.095238                      
-system.ruby.LD.miss_latency_hist::gmean   3693.389751                      
-system.ruby.LD.miss_latency_hist::stdev    463.961143                      
-system.ruby.LD.miss_latency_hist         |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           5     11.90%     11.90% |          11     26.19%     38.10% |          18     42.86%     80.95% |           8     19.05%    100.00% |           0      0.00%    100.00%
-system.ruby.LD.miss_latency_hist::total            42                      
+system.ruby.LD.miss_latency_hist::samples           48                      
+system.ruby.LD.miss_latency_hist::mean    3753.291667                      
+system.ruby.LD.miss_latency_hist::gmean   3731.923305                      
+system.ruby.LD.miss_latency_hist::stdev    402.734903                      
+system.ruby.LD.miss_latency_hist         |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           1      2.08%      2.08% |          17     35.42%     37.50% |          20     41.67%     79.17% |          10     20.83%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.miss_latency_hist::total            48                      
 system.ruby.ST.latency_hist::bucket_size         1024                      
 system.ruby.ST.latency_hist::max_bucket         10239                      
-system.ruby.ST.latency_hist::samples              854                      
-system.ruby.ST.latency_hist::mean         3677.291569                      
-system.ruby.ST.latency_hist::gmean        3606.100027                      
-system.ruby.ST.latency_hist::stdev         585.222193                      
-system.ruby.ST.latency_hist              |           6      0.70%      0.70% |           5      0.59%      1.29% |          85      9.95%     11.24% |         549     64.29%     75.53% |         208     24.36%     99.88% |           1      0.12%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.ST.latency_hist::total                854                      
+system.ruby.ST.latency_hist::samples              878                      
+system.ruby.ST.latency_hist::mean         3684.186788                      
+system.ruby.ST.latency_hist::gmean        3631.018183                      
+system.ruby.ST.latency_hist::stdev         544.872418                      
+system.ruby.ST.latency_hist              |           4      0.46%      0.46% |           4      0.46%      0.91% |          70      7.97%      8.88% |         611     69.59%     78.47% |         188     21.41%     99.89% |           1      0.11%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.latency_hist::total                878                      
 system.ruby.ST.hit_latency_hist::bucket_size          512                      
 system.ruby.ST.hit_latency_hist::max_bucket         5119                      
 system.ruby.ST.hit_latency_hist::samples           36                      
-system.ruby.ST.hit_latency_hist::mean            3241                      
-system.ruby.ST.hit_latency_hist::gmean    3199.557019                      
-system.ruby.ST.hit_latency_hist::stdev     520.842724                      
-system.ruby.ST.hit_latency_hist          |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           1      2.78%      2.78% |           2      5.56%      8.33% |          13     36.11%     44.44% |          12     33.33%     77.78% |           5     13.89%     91.67% |           3      8.33%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.hit_latency_hist::mean     3222.750000                      
+system.ruby.ST.hit_latency_hist::gmean    3194.454829                      
+system.ruby.ST.hit_latency_hist::stdev     431.138120                      
+system.ruby.ST.hit_latency_hist          |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           3      8.33%      8.33% |           9     25.00%     33.33% |          16     44.44%     77.78% |           7     19.44%     97.22% |           1      2.78%    100.00% |           0      0.00%    100.00%
 system.ruby.ST.hit_latency_hist::total             36                      
 system.ruby.ST.miss_latency_hist::bucket_size         1024                      
 system.ruby.ST.miss_latency_hist::max_bucket        10239                      
-system.ruby.ST.miss_latency_hist::samples          818                      
-system.ruby.ST.miss_latency_hist::mean    3696.492665                      
-system.ruby.ST.miss_latency_hist::gmean   3625.133340                      
-system.ruby.ST.miss_latency_hist::stdev    580.687585                      
-system.ruby.ST.miss_latency_hist         |           6      0.73%      0.73% |           4      0.49%      1.22% |          70      8.56%      9.78% |         532     65.04%     74.82% |         205     25.06%     99.88% |           1      0.12%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.ST.miss_latency_hist::total           818                      
-system.ruby.IFETCH.latency_hist::bucket_size          512                      
-system.ruby.IFETCH.latency_hist::max_bucket         5119                      
-system.ruby.IFETCH.latency_hist::samples           58                      
-system.ruby.IFETCH.latency_hist::mean     3745.137931                      
-system.ruby.IFETCH.latency_hist::gmean    3705.404222                      
-system.ruby.IFETCH.latency_hist::stdev     548.056325                      
-system.ruby.IFETCH.latency_hist          |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           7     12.07%     12.07% |          17     29.31%     41.38% |          18     31.03%     72.41% |          14     24.14%     96.55% |           2      3.45%    100.00%
-system.ruby.IFETCH.latency_hist::total             58                      
+system.ruby.ST.miss_latency_hist::samples          842                      
+system.ruby.ST.miss_latency_hist::mean    3703.915677                      
+system.ruby.ST.miss_latency_hist::gmean   3650.959161                      
+system.ruby.ST.miss_latency_hist::stdev    540.698215                      
+system.ruby.ST.miss_latency_hist         |           4      0.48%      0.48% |           4      0.48%      0.95% |          58      6.89%      7.84% |         588     69.83%     77.67% |         187     22.21%     99.88% |           1      0.12%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.miss_latency_hist::total           842                      
+system.ruby.IFETCH.latency_hist::bucket_size         1024                      
+system.ruby.IFETCH.latency_hist::max_bucket        10239                      
+system.ruby.IFETCH.latency_hist::samples           50                      
+system.ruby.IFETCH.latency_hist::mean     3830.080000                      
+system.ruby.IFETCH.latency_hist::gmean    3811.685277                      
+system.ruby.IFETCH.latency_hist::stdev     383.882042                      
+system.ruby.IFETCH.latency_hist          |           0      0.00%      0.00% |           0      0.00%      0.00% |           1      2.00%      2.00% |          40     80.00%     82.00% |           8     16.00%     98.00% |           1      2.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.latency_hist::total             50                      
 system.ruby.IFETCH.hit_latency_hist::bucket_size          512                      
 system.ruby.IFETCH.hit_latency_hist::max_bucket         5119                      
-system.ruby.IFETCH.hit_latency_hist::samples            2                      
-system.ruby.IFETCH.hit_latency_hist::mean         3327                      
-system.ruby.IFETCH.hit_latency_hist::gmean  3321.684061                      
-system.ruby.IFETCH.hit_latency_hist::stdev   265.872150                      
-system.ruby.IFETCH.hit_latency_hist      |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           2    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.IFETCH.hit_latency_hist::total            2                      
-system.ruby.IFETCH.miss_latency_hist::bucket_size          512                      
-system.ruby.IFETCH.miss_latency_hist::max_bucket         5119                      
-system.ruby.IFETCH.miss_latency_hist::samples           56                      
-system.ruby.IFETCH.miss_latency_hist::mean  3760.071429                      
-system.ruby.IFETCH.miss_latency_hist::gmean  3719.899517                      
-system.ruby.IFETCH.miss_latency_hist::stdev   550.833942                      
-system.ruby.IFETCH.miss_latency_hist     |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           7     12.50%     12.50% |          15     26.79%     39.29% |          18     32.14%     71.43% |          14     25.00%     96.43% |           2      3.57%    100.00%
-system.ruby.IFETCH.miss_latency_hist::total           56                      
+system.ruby.IFETCH.hit_latency_hist::samples            1                      
+system.ruby.IFETCH.hit_latency_hist::mean         3640                      
+system.ruby.IFETCH.hit_latency_hist::gmean  3640.000000                      
+system.ruby.IFETCH.hit_latency_hist::stdev          nan                      
+system.ruby.IFETCH.hit_latency_hist      |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           1    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.hit_latency_hist::total            1                      
+system.ruby.IFETCH.miss_latency_hist::bucket_size         1024                      
+system.ruby.IFETCH.miss_latency_hist::max_bucket        10239                      
+system.ruby.IFETCH.miss_latency_hist::samples           49                      
+system.ruby.IFETCH.miss_latency_hist::mean  3833.959184                      
+system.ruby.IFETCH.miss_latency_hist::gmean  3815.272105                      
+system.ruby.IFETCH.miss_latency_hist::stdev   386.868785                      
+system.ruby.IFETCH.miss_latency_hist     |           0      0.00%      0.00% |           0      0.00%      0.00% |           1      2.04%      2.04% |          39     79.59%     81.63% |           8     16.33%     97.96% |           1      2.04%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.miss_latency_hist::total           49                      
 system.ruby.Directory.miss_mach_latency_hist::bucket_size         1024                      
 system.ruby.Directory.miss_mach_latency_hist::max_bucket        10239                      
-system.ruby.Directory.miss_mach_latency_hist::samples          916                      
-system.ruby.Directory.miss_mach_latency_hist::mean  3701.553493                      
-system.ruby.Directory.miss_mach_latency_hist::gmean  3633.963773                      
-system.ruby.Directory.miss_mach_latency_hist::stdev   573.775637                      
-system.ruby.Directory.miss_mach_latency_hist |           6      0.66%      0.66% |           4      0.44%      1.09% |          82      8.95%     10.04% |         594     64.85%     74.89% |         229     25.00%     99.89% |           1      0.11%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.Directory.miss_mach_latency_hist::total          916                      
+system.ruby.Directory.miss_mach_latency_hist::samples          939                      
+system.ruby.Directory.miss_mach_latency_hist::mean  3713.225772                      
+system.ruby.Directory.miss_mach_latency_hist::gmean  3663.461061                      
+system.ruby.Directory.miss_mach_latency_hist::stdev   528.042705                      
+system.ruby.Directory.miss_mach_latency_hist |           4      0.43%      0.43% |           4      0.43%      0.85% |          60      6.39%      7.24% |         664     70.71%     77.96% |         205     21.83%     99.79% |           2      0.21%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.Directory.miss_mach_latency_hist::total          939                      
 system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size          512                      
 system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket         5119                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist::samples           42                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist::mean  3722.095238                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean  3693.389751                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev   463.961143                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           5     11.90%     11.90% |          11     26.19%     38.10% |          18     42.86%     80.95% |           8     19.05%    100.00% |           0      0.00%    100.00%
-system.ruby.LD.Directory.miss_type_mach_latency_hist::total           42                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist::samples           48                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist::mean  3753.291667                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean  3731.923305                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev   402.734903                      
+system.ruby.LD.Directory.miss_type_mach_latency_hist |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           1      2.08%      2.08% |          17     35.42%     37.50% |          20     41.67%     79.17% |          10     20.83%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.Directory.miss_type_mach_latency_hist::total           48                      
 system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size         1024                      
 system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket        10239                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist::samples          818                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist::mean  3696.492665                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean  3625.133340                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev   580.687585                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist |           6      0.73%      0.73% |           4      0.49%      1.22% |          70      8.56%      9.78% |         532     65.04%     74.82% |         205     25.06%     99.88% |           1      0.12%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.ST.Directory.miss_type_mach_latency_hist::total          818                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size          512                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket         5119                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples           56                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean  3760.071429                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean  3719.899517                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev   550.833942                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           7     12.50%     12.50% |          15     26.79%     39.29% |          18     32.14%     71.43% |          14     25.00%     96.43% |           2      3.57%    100.00%
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total           56                      
-system.ruby.L1Cache_Controller.Load                42      0.00%      0.00%
-system.ruby.L1Cache_Controller.Ifetch              58      0.00%      0.00%
-system.ruby.L1Cache_Controller.Store              855      0.00%      0.00%
-system.ruby.L1Cache_Controller.Data               916      0.00%      0.00%
-system.ruby.L1Cache_Controller.Replacement          914      0.00%      0.00%
-system.ruby.L1Cache_Controller.Writeback_Ack          912      0.00%      0.00%
-system.ruby.L1Cache_Controller.I.Load              42      0.00%      0.00%
-system.ruby.L1Cache_Controller.I.Ifetch            56      0.00%      0.00%
-system.ruby.L1Cache_Controller.I.Store            819      0.00%      0.00%
-system.ruby.L1Cache_Controller.M.Ifetch             2      0.00%      0.00%
+system.ruby.ST.Directory.miss_type_mach_latency_hist::samples          842                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist::mean  3703.915677                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean  3650.959161                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev   540.698215                      
+system.ruby.ST.Directory.miss_type_mach_latency_hist |           4      0.48%      0.48% |           4      0.48%      0.95% |          58      6.89%      7.84% |         588     69.83%     77.67% |         187     22.21%     99.88% |           1      0.12%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.Directory.miss_type_mach_latency_hist::total          842                      
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size         1024                      
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket        10239                      
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples           49                      
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean  3833.959184                      
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean  3815.272105                      
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev   386.868785                      
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist |           0      0.00%      0.00% |           0      0.00%      0.00% |           1      2.04%      2.04% |          39     79.59%     81.63% |           8     16.33%     97.96% |           1      2.04%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total           49                      
+system.ruby.L1Cache_Controller.Load                50      0.00%      0.00%
+system.ruby.L1Cache_Controller.Ifetch              50      0.00%      0.00%
+system.ruby.L1Cache_Controller.Store              880      0.00%      0.00%
+system.ruby.L1Cache_Controller.Data               939      0.00%      0.00%
+system.ruby.L1Cache_Controller.Replacement          938      0.00%      0.00%
+system.ruby.L1Cache_Controller.Writeback_Ack          936      0.00%      0.00%
+system.ruby.L1Cache_Controller.I.Load              48      0.00%      0.00%
+system.ruby.L1Cache_Controller.I.Ifetch            49      0.00%      0.00%
+system.ruby.L1Cache_Controller.I.Store            844      0.00%      0.00%
+system.ruby.L1Cache_Controller.M.Load               2      0.00%      0.00%
+system.ruby.L1Cache_Controller.M.Ifetch             1      0.00%      0.00%
 system.ruby.L1Cache_Controller.M.Store             36      0.00%      0.00%
-system.ruby.L1Cache_Controller.M.Replacement          914      0.00%      0.00%
-system.ruby.L1Cache_Controller.MI.Writeback_Ack          912      0.00%      0.00%
-system.ruby.L1Cache_Controller.IS.Data             98      0.00%      0.00%
-system.ruby.L1Cache_Controller.IM.Data            818      0.00%      0.00%
-system.ruby.Directory_Controller.GETX             916      0.00%      0.00%
-system.ruby.Directory_Controller.PUTX             914      0.00%      0.00%
-system.ruby.Directory_Controller.Memory_Data          916      0.00%      0.00%
-system.ruby.Directory_Controller.Memory_Ack          914      0.00%      0.00%
-system.ruby.Directory_Controller.I.GETX           916      0.00%      0.00%
-system.ruby.Directory_Controller.M.PUTX           914      0.00%      0.00%
-system.ruby.Directory_Controller.IM.Memory_Data          916      0.00%      0.00%
-system.ruby.Directory_Controller.MI.Memory_Ack          914      0.00%      0.00%
+system.ruby.L1Cache_Controller.M.Replacement          938      0.00%      0.00%
+system.ruby.L1Cache_Controller.MI.Writeback_Ack          936      0.00%      0.00%
+system.ruby.L1Cache_Controller.IS.Data             97      0.00%      0.00%
+system.ruby.L1Cache_Controller.IM.Data            842      0.00%      0.00%
+system.ruby.Directory_Controller.GETX             939      0.00%      0.00%
+system.ruby.Directory_Controller.PUTX             936      0.00%      0.00%
+system.ruby.Directory_Controller.Memory_Data          939      0.00%      0.00%
+system.ruby.Directory_Controller.Memory_Ack          936      0.00%      0.00%
+system.ruby.Directory_Controller.I.GETX           939      0.00%      0.00%
+system.ruby.Directory_Controller.M.PUTX           936      0.00%      0.00%
+system.ruby.Directory_Controller.IM.Memory_Data          939      0.00%      0.00%
+system.ruby.Directory_Controller.MI.Memory_Ack          936      0.00%      0.00%
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/stats.txt b/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/stats.txt
index bc520582f..779d261ee 100644
--- a/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/stats.txt
+++ b/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/stats.txt
@@ -4,99 +4,99 @@ sim_seconds                                  0.100000                       # Nu
 sim_ticks                                100000000000                       # Number of ticks simulated
 final_tick                               100000000000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_tick_rate                            14337554787                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 228672                       # Number of bytes of host memory used
-host_seconds                                     6.97                       # Real time elapsed on the host
+host_tick_rate                            10849136429                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 200176                       # Number of bytes of host memory used
+host_seconds                                     9.22                       # Real time elapsed on the host
 system.clk_domain.voltage_domain.voltage            1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu              106798016                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            106798016                       # Number of bytes read from this memory
-system.physmem.bytes_written::cpu           106535680                       # Number of bytes written to this memory
-system.physmem.bytes_written::total         106535680                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu                 1668719                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1668719                       # Number of read requests responded to by this memory
-system.physmem.num_writes::cpu                1664620                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1664620                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu                1067980160                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              1067980160                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu               1065356800                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total             1065356800                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu               2133336960                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             2133336960                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                       1668720                       # Number of read requests accepted
-system.physmem.writeReqs                      1664620                       # Number of write requests accepted
-system.physmem.readBursts                     1668720                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                    1664620                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                106797184                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                       896                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                 106533952                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                 106798080                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys              106535680                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                       14                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                       8                       # Number of DRAM write bursts merged with an existing one
+system.physmem.bytes_read::cpu              106649408                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            106649408                       # Number of bytes read from this memory
+system.physmem.bytes_written::cpu           106680256                       # Number of bytes written to this memory
+system.physmem.bytes_written::total         106680256                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu                 1666397                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               1666397                       # Number of read requests responded to by this memory
+system.physmem.num_writes::cpu                1666879                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total              1666879                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu                1066494080                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              1066494080                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu               1066802560                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total             1066802560                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu               2133296640                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             2133296640                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                       1666397                       # Number of read requests accepted
+system.physmem.writeReqs                      1666879                       # Number of write requests accepted
+system.physmem.readBursts                     1666397                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                    1666879                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                106647616                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      1792                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                 106676608                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                 106649408                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys              106680256                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                       28                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                      33                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0              104195                       # Per bank write bursts
-system.physmem.perBankRdBursts::1              104188                       # Per bank write bursts
-system.physmem.perBankRdBursts::2              104541                       # Per bank write bursts
-system.physmem.perBankRdBursts::3              104589                       # Per bank write bursts
-system.physmem.perBankRdBursts::4              103994                       # Per bank write bursts
-system.physmem.perBankRdBursts::5              104203                       # Per bank write bursts
-system.physmem.perBankRdBursts::6              104803                       # Per bank write bursts
-system.physmem.perBankRdBursts::7              104557                       # Per bank write bursts
-system.physmem.perBankRdBursts::8              104630                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              104040                       # Per bank write bursts
-system.physmem.perBankRdBursts::10             104372                       # Per bank write bursts
-system.physmem.perBankRdBursts::11             104177                       # Per bank write bursts
-system.physmem.perBankRdBursts::12             103805                       # Per bank write bursts
-system.physmem.perBankRdBursts::13             104138                       # Per bank write bursts
-system.physmem.perBankRdBursts::14             103922                       # Per bank write bursts
-system.physmem.perBankRdBursts::15             104552                       # Per bank write bursts
-system.physmem.perBankWrBursts::0              103587                       # Per bank write bursts
-system.physmem.perBankWrBursts::1              104082                       # Per bank write bursts
-system.physmem.perBankWrBursts::2              103950                       # Per bank write bursts
-system.physmem.perBankWrBursts::3              104334                       # Per bank write bursts
-system.physmem.perBankWrBursts::4              104264                       # Per bank write bursts
-system.physmem.perBankWrBursts::5              104509                       # Per bank write bursts
-system.physmem.perBankWrBursts::6              103927                       # Per bank write bursts
-system.physmem.perBankWrBursts::7              104060                       # Per bank write bursts
-system.physmem.perBankWrBursts::8              104076                       # Per bank write bursts
-system.physmem.perBankWrBursts::9              104072                       # Per bank write bursts
-system.physmem.perBankWrBursts::10             104151                       # Per bank write bursts
-system.physmem.perBankWrBursts::11             104328                       # Per bank write bursts
-system.physmem.perBankWrBursts::12             103712                       # Per bank write bursts
-system.physmem.perBankWrBursts::13             103871                       # Per bank write bursts
-system.physmem.perBankWrBursts::14             103773                       # Per bank write bursts
-system.physmem.perBankWrBursts::15             103897                       # Per bank write bursts
+system.physmem.perBankRdBursts::0              104030                       # Per bank write bursts
+system.physmem.perBankRdBursts::1              103995                       # Per bank write bursts
+system.physmem.perBankRdBursts::2              104918                       # Per bank write bursts
+system.physmem.perBankRdBursts::3              104597                       # Per bank write bursts
+system.physmem.perBankRdBursts::4              103868                       # Per bank write bursts
+system.physmem.perBankRdBursts::5              103934                       # Per bank write bursts
+system.physmem.perBankRdBursts::6              103649                       # Per bank write bursts
+system.physmem.perBankRdBursts::7              104312                       # Per bank write bursts
+system.physmem.perBankRdBursts::8              103869                       # Per bank write bursts
+system.physmem.perBankRdBursts::9              104353                       # Per bank write bursts
+system.physmem.perBankRdBursts::10             103834                       # Per bank write bursts
+system.physmem.perBankRdBursts::11             104272                       # Per bank write bursts
+system.physmem.perBankRdBursts::12             104075                       # Per bank write bursts
+system.physmem.perBankRdBursts::13             104034                       # Per bank write bursts
+system.physmem.perBankRdBursts::14             104583                       # Per bank write bursts
+system.physmem.perBankRdBursts::15             104046                       # Per bank write bursts
+system.physmem.perBankWrBursts::0              104355                       # Per bank write bursts
+system.physmem.perBankWrBursts::1              104090                       # Per bank write bursts
+system.physmem.perBankWrBursts::2              104175                       # Per bank write bursts
+system.physmem.perBankWrBursts::3              103885                       # Per bank write bursts
+system.physmem.perBankWrBursts::4              104730                       # Per bank write bursts
+system.physmem.perBankWrBursts::5              104507                       # Per bank write bursts
+system.physmem.perBankWrBursts::6              104082                       # Per bank write bursts
+system.physmem.perBankWrBursts::7              104224                       # Per bank write bursts
+system.physmem.perBankWrBursts::8              104318                       # Per bank write bursts
+system.physmem.perBankWrBursts::9              104219                       # Per bank write bursts
+system.physmem.perBankWrBursts::10             104228                       # Per bank write bursts
+system.physmem.perBankWrBursts::11             103701                       # Per bank write bursts
+system.physmem.perBankWrBursts::12             104103                       # Per bank write bursts
+system.physmem.perBankWrBursts::13             103984                       # Per bank write bursts
+system.physmem.perBankWrBursts::14             104297                       # Per bank write bursts
+system.physmem.perBankWrBursts::15             103924                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                     99999960227                       # Total gap between requests
+system.physmem.totGap                     99999956143                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                 1668720                       # Read request sizes (log2)
+system.physmem.readPktSize::6                 1666397                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                1664620                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    766507                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    779035                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     72986                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                     24510                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                     10942                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                      7167                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                      4128                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                      2045                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                       890                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                       388                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                       97                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                        9                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                        2                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                1666879                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    765065                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    778270                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     73012                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                     24424                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                     10950                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                      7150                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                      4169                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                      2026                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                       823                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                       361                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                       94                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                       20                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                        5                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
@@ -131,33 +131,33 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                    21583                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                    26179                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    48990                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                   101142                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                   110031                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                   109380                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                   103714                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                   100305                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                   100049                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                   122199                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                   111635                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                   105240                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                   100495                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                    98624                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    98614                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                    98524                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                    98476                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                    98391                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                     3802                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                     2853                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                     2040                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                     1283                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      674                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      285                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                       72                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                       16                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                    21652                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                    26132                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                    49040                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                   101252                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                   110536                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                   109573                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                   103779                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                   100515                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                   100211                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                   122657                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                   111795                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                   105251                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                   100593                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                    98735                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                    98656                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                    98627                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                    98577                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                    98503                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                     3706                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                     2792                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                     1955                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                     1254                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      676                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      274                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                       74                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                       14                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                        2                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
@@ -180,12 +180,12 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples      3296563                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean       64.713043                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean      64.189923                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev      23.988602                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127        3288788     99.76%     99.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255         5620      0.17%     99.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::samples      3296334                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean       64.715403                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean      64.191581                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev      23.992085                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127        3288433     99.76%     99.76% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255         5746      0.17%     99.93% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::256-383           32      0.00%     99.94% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::384-511           32      0.00%     99.94% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::512-639           32      0.00%     99.94% # Bytes accessed per row activation
@@ -193,76 +193,76 @@ system.physmem.bytesPerActivate::640-767           32      0.00%     99.94% # By
 system.physmem.bytesPerActivate::768-895           32      0.00%     99.94% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::896-1023           32      0.00%     99.94% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::1024-1151         1963      0.06%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total        3296563                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         97746                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        17.071819                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::gmean       15.727304                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      106.831001                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047          97745    100.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::total        3296334                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         97889                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        17.022975                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::gmean       15.667690                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      106.738588                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047          97888    100.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::32768-34815            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           97746                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         97746                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        17.029781                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.939241                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        1.836351                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16              73134     74.82%     74.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17                545      0.56%     75.38% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18                655      0.67%     76.05% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19               1612      1.65%     77.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20              16208     16.58%     94.28% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21               5168      5.29%     99.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22                147      0.15%     99.72% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23                 85      0.09%     99.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24                 66      0.07%     99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::25                 49      0.05%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26                 29      0.03%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::27                 26      0.03%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28                 16      0.02%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::29                  4      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::30                  2      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           97746                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    58049969454                       # Total ticks spent queuing
-system.physmem.totMemAccLat               89338206954                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   8343530000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       34787.42                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total           97889                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         97889                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.027674                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.937663                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        1.829790                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16              73237     74.82%     74.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17                524      0.54%     75.35% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18                736      0.75%     76.10% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19               1545      1.58%     77.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20              16291     16.64%     94.32% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21               5161      5.27%     99.60% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22                155      0.16%     99.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23                 78      0.08%     99.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24                 59      0.06%     99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25                 41      0.04%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26                 31      0.03%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::27                 13      0.01%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28                  9      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::29                  6      0.01%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::30                  3      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           97889                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    57937365003                       # Total ticks spent queuing
+system.physmem.totMemAccLat               89181783753                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   8331845000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       34768.63                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  53537.42                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                        1067.97                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                        1065.34                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                     1067.98                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                     1065.36                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  53518.63                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                        1066.48                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                        1066.77                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                     1066.49                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                     1066.80                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                          16.67                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       8.34                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      8.32                       # Data bus utilization in percentage for writes
+system.physmem.busUtilRead                       8.33                       # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite                      8.33                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.68                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                        25.19                       # Average write queue length when enqueuing
-system.physmem.readRowHits                      32203                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                      4525                       # Number of row buffer hits during writes
+system.physmem.readRowHits                      32168                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                      4679                       # Number of row buffer hits during writes
 system.physmem.readRowHitRate                    1.93                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                   0.27                       # Row buffer hit rate for writes
-system.physmem.avgGap                        29999.93                       # Average gap between requests
-system.physmem.pageHitRate                       1.10                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE          5508849                       # Time in different power states
+system.physmem.writeRowHitRate                   0.28                       # Row buffer hit rate for writes
+system.physmem.avgGap                        30000.50                       # Average gap between requests
+system.physmem.pageHitRate                       1.11                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE          5459951                       # Time in different power states
 system.physmem.memoryStateTime::REF        3339180000                       # Time in different power states
 system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT       96654451752                       # Time in different power states
+system.physmem.memoryStateTime::ACT       96654442549                       # Time in different power states
 system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.membus.throughput                   2133336960                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq             1668720                       # Transaction distribution
-system.membus.trans_dist::ReadResp            1668719                       # Transaction distribution
-system.membus.trans_dist::WriteReq            1664620                       # Transaction distribution
-system.membus.trans_dist::WriteResp           1664620                       # Transaction distribution
-system.membus.pkt_count_system.monitor-master::system.physmem.port      6666679                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                6666679                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.monitor-master::system.physmem.port    213333696                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total           213333696                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus              213333696                       # Total data (bytes)
-system.membus.reqLayer0.occupancy         11669983278                       # Layer occupancy (ticks)
+system.membus.throughput                   2133296640                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq             1666397                       # Transaction distribution
+system.membus.trans_dist::ReadResp            1666397                       # Transaction distribution
+system.membus.trans_dist::WriteReq            1666879                       # Transaction distribution
+system.membus.trans_dist::WriteResp           1666879                       # Transaction distribution
+system.membus.pkt_count_system.monitor-master::system.physmem.port      6666552                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                6666552                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.monitor-master::system.physmem.port    213329664                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total           213329664                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus              213329664                       # Total data (bytes)
+system.membus.reqLayer0.occupancy         11679751447                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization              11.7                       # Layer utilization (%)
-system.membus.respLayer0.occupancy        11409038076                       # Layer occupancy (ticks)
+system.membus.respLayer0.occupancy        11400175366                       # Layer occupancy (ticks)
 system.membus.respLayer0.utilization             11.4                       # Layer utilization (%)
-system.monitor.readBurstLengthHist::samples      1668720                       # Histogram of burst lengths of transmitted packets
+system.monitor.readBurstLengthHist::samples      1666397                       # Histogram of burst lengths of transmitted packets
 system.monitor.readBurstLengthHist::mean           64                       # Histogram of burst lengths of transmitted packets
 system.monitor.readBurstLengthHist::gmean    64.000000                       # Histogram of burst lengths of transmitted packets
 system.monitor.readBurstLengthHist::stdev            0                       # Histogram of burst lengths of transmitted packets
@@ -282,12 +282,12 @@ system.monitor.readBurstLengthHist::48-51            0      0.00%      0.00% # H
 system.monitor.readBurstLengthHist::52-55            0      0.00%      0.00% # Histogram of burst lengths of transmitted packets
 system.monitor.readBurstLengthHist::56-59            0      0.00%      0.00% # Histogram of burst lengths of transmitted packets
 system.monitor.readBurstLengthHist::60-63            0      0.00%      0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::64-67      1668720    100.00%    100.00% # Histogram of burst lengths of transmitted packets
+system.monitor.readBurstLengthHist::64-67      1666397    100.00%    100.00% # Histogram of burst lengths of transmitted packets
 system.monitor.readBurstLengthHist::68-71            0      0.00%    100.00% # Histogram of burst lengths of transmitted packets
 system.monitor.readBurstLengthHist::72-75            0      0.00%    100.00% # Histogram of burst lengths of transmitted packets
 system.monitor.readBurstLengthHist::76-79            0      0.00%    100.00% # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::total      1668720                       # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::samples      1664620                       # Histogram of burst lengths of transmitted packets
+system.monitor.readBurstLengthHist::total      1666397                       # Histogram of burst lengths of transmitted packets
+system.monitor.writeBurstLengthHist::samples      1666879                       # Histogram of burst lengths of transmitted packets
 system.monitor.writeBurstLengthHist::mean           64                       # Histogram of burst lengths of transmitted packets
 system.monitor.writeBurstLengthHist::gmean    64.000000                       # Histogram of burst lengths of transmitted packets
 system.monitor.writeBurstLengthHist::stdev            0                       # Histogram of burst lengths of transmitted packets
@@ -307,15 +307,15 @@ system.monitor.writeBurstLengthHist::48-51            0      0.00%      0.00% #
 system.monitor.writeBurstLengthHist::52-55            0      0.00%      0.00% # Histogram of burst lengths of transmitted packets
 system.monitor.writeBurstLengthHist::56-59            0      0.00%      0.00% # Histogram of burst lengths of transmitted packets
 system.monitor.writeBurstLengthHist::60-63            0      0.00%      0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::64-67      1664620    100.00%    100.00% # Histogram of burst lengths of transmitted packets
+system.monitor.writeBurstLengthHist::64-67      1666879    100.00%    100.00% # Histogram of burst lengths of transmitted packets
 system.monitor.writeBurstLengthHist::68-71            0      0.00%    100.00% # Histogram of burst lengths of transmitted packets
 system.monitor.writeBurstLengthHist::72-75            0      0.00%    100.00% # Histogram of burst lengths of transmitted packets
 system.monitor.writeBurstLengthHist::76-79            0      0.00%    100.00% # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::total      1664620                       # Histogram of burst lengths of transmitted packets
+system.monitor.writeBurstLengthHist::total      1666879                       # Histogram of burst lengths of transmitted packets
 system.monitor.readBandwidthHist::samples          100                       # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::mean     1067980160                       # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::gmean  1064651766.271052                       # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::stdev  107759819.009425                       # Histogram of read bandwidth per sample period (bytes/s)
+system.monitor.readBandwidthHist::mean     1066494080                       # Histogram of read bandwidth per sample period (bytes/s)
+system.monitor.readBandwidthHist::gmean  1063154518.573643                       # Histogram of read bandwidth per sample period (bytes/s)
+system.monitor.readBandwidthHist::stdev  107916008.948195                       # Histogram of read bandwidth per sample period (bytes/s)
 system.monitor.readBandwidthHist::0-1.34218e+08            0      0.00%      0.00% # Histogram of read bandwidth per sample period (bytes/s)
 system.monitor.readBandwidthHist::1.34218e+08-2.68435e+08            0      0.00%      0.00% # Histogram of read bandwidth per sample period (bytes/s)
 system.monitor.readBandwidthHist::2.68435e+08-4.02653e+08            0      0.00%      0.00% # Histogram of read bandwidth per sample period (bytes/s)
@@ -337,12 +337,12 @@ system.monitor.readBandwidthHist::2.2817e+09-2.41592e+09            0      0.00%
 system.monitor.readBandwidthHist::2.41592e+09-2.55014e+09            0      0.00%    100.00% # Histogram of read bandwidth per sample period (bytes/s)
 system.monitor.readBandwidthHist::2.55014e+09-2.68435e+09            0      0.00%    100.00% # Histogram of read bandwidth per sample period (bytes/s)
 system.monitor.readBandwidthHist::total           100                       # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.averageReadBandwidth        1067980160      0.00%      0.00% # Average read bandwidth (bytes/s)
-system.monitor.totalReadBytes               106798016                       # Number of bytes read
+system.monitor.averageReadBandwidth        1066494080      0.00%      0.00% # Average read bandwidth (bytes/s)
+system.monitor.totalReadBytes               106649408                       # Number of bytes read
 system.monitor.writeBandwidthHist::samples          100                       # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::mean    1065356800                       # Histogram of write bandwidth (bytes/s)
+system.monitor.writeBandwidthHist::mean    1066802560                       # Histogram of write bandwidth (bytes/s)
 system.monitor.writeBandwidthHist::gmean            0                       # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::stdev 107770982.104450                       # Histogram of write bandwidth (bytes/s)
+system.monitor.writeBandwidthHist::stdev 107924720.268046                       # Histogram of write bandwidth (bytes/s)
 system.monitor.writeBandwidthHist::0-6.71089e+07            1      1.00%      1.00% # Histogram of write bandwidth (bytes/s)
 system.monitor.writeBandwidthHist::6.71089e+07-1.34218e+08            0      0.00%      1.00% # Histogram of write bandwidth (bytes/s)
 system.monitor.writeBandwidthHist::1.34218e+08-2.01327e+08            0      0.00%      1.00% # Histogram of write bandwidth (bytes/s)
@@ -364,37 +364,37 @@ system.monitor.writeBandwidthHist::1.14085e+09-1.20796e+09            0      0.0
 system.monitor.writeBandwidthHist::1.20796e+09-1.27507e+09            0      0.00%    100.00% # Histogram of write bandwidth (bytes/s)
 system.monitor.writeBandwidthHist::1.27507e+09-1.34218e+09            0      0.00%    100.00% # Histogram of write bandwidth (bytes/s)
 system.monitor.writeBandwidthHist::total          100                       # Histogram of write bandwidth (bytes/s)
-system.monitor.averageWriteBandwidth       1065356800      0.00%      0.00% # Average write bandwidth (bytes/s)
-system.monitor.totalWrittenBytes            106535680                       # Number of bytes written
-system.monitor.readLatencyHist::samples       1668719                       # Read request-response latency
-system.monitor.readLatencyHist::mean     73576.537902                       # Read request-response latency
-system.monitor.readLatencyHist::gmean    68507.812375                       # Read request-response latency
-system.monitor.readLatencyHist::stdev    39270.153648                       # Read request-response latency
-system.monitor.readLatencyHist::0-32767            14      0.00%      0.00% # Read request-response latency
-system.monitor.readLatencyHist::32768-65535       454232     27.22%     27.22% # Read request-response latency
-system.monitor.readLatencyHist::65536-98303      1043171     62.51%     89.73% # Read request-response latency
-system.monitor.readLatencyHist::98304-131071        73085      4.38%     94.11% # Read request-response latency
-system.monitor.readLatencyHist::131072-163839        46931      2.81%     96.93% # Read request-response latency
-system.monitor.readLatencyHist::163840-196607        12458      0.75%     97.67% # Read request-response latency
-system.monitor.readLatencyHist::196608-229375         7854      0.47%     98.14% # Read request-response latency
-system.monitor.readLatencyHist::229376-262143         7990      0.48%     98.62% # Read request-response latency
-system.monitor.readLatencyHist::262144-294911         8124      0.49%     99.11% # Read request-response latency
-system.monitor.readLatencyHist::294912-327679         7849      0.47%     99.58% # Read request-response latency
-system.monitor.readLatencyHist::327680-360447         4246      0.25%     99.83% # Read request-response latency
-system.monitor.readLatencyHist::360448-393215         1108      0.07%     99.90% # Read request-response latency
-system.monitor.readLatencyHist::393216-425983          866      0.05%     99.95% # Read request-response latency
-system.monitor.readLatencyHist::425984-458751          601      0.04%     99.99% # Read request-response latency
-system.monitor.readLatencyHist::458752-491519          183      0.01%    100.00% # Read request-response latency
-system.monitor.readLatencyHist::491520-524287            7      0.00%    100.00% # Read request-response latency
+system.monitor.averageWriteBandwidth       1066802560      0.00%      0.00% # Average write bandwidth (bytes/s)
+system.monitor.totalWrittenBytes            106680256                       # Number of bytes written
+system.monitor.readLatencyHist::samples       1666397                       # Read request-response latency
+system.monitor.readLatencyHist::mean     73557.268741                       # Read request-response latency
+system.monitor.readLatencyHist::gmean    68501.179139                       # Read request-response latency
+system.monitor.readLatencyHist::stdev    39156.791762                       # Read request-response latency
+system.monitor.readLatencyHist::0-32767            28      0.00%      0.00% # Read request-response latency
+system.monitor.readLatencyHist::32768-65535       454399     27.27%     27.27% # Read request-response latency
+system.monitor.readLatencyHist::65536-98303      1040506     62.44%     89.71% # Read request-response latency
+system.monitor.readLatencyHist::98304-131071        73250      4.40%     94.11% # Read request-response latency
+system.monitor.readLatencyHist::131072-163839        47036      2.82%     96.93% # Read request-response latency
+system.monitor.readLatencyHist::163840-196607        12641      0.76%     97.69% # Read request-response latency
+system.monitor.readLatencyHist::196608-229375         7802      0.47%     98.16% # Read request-response latency
+system.monitor.readLatencyHist::229376-262143         7940      0.48%     98.63% # Read request-response latency
+system.monitor.readLatencyHist::262144-294911         8093      0.49%     99.12% # Read request-response latency
+system.monitor.readLatencyHist::294912-327679         7856      0.47%     99.59% # Read request-response latency
+system.monitor.readLatencyHist::327680-360447         4214      0.25%     99.84% # Read request-response latency
+system.monitor.readLatencyHist::360448-393215         1043      0.06%     99.90% # Read request-response latency
+system.monitor.readLatencyHist::393216-425983          827      0.05%     99.95% # Read request-response latency
+system.monitor.readLatencyHist::425984-458751          590      0.04%     99.99% # Read request-response latency
+system.monitor.readLatencyHist::458752-491519          166      0.01%    100.00% # Read request-response latency
+system.monitor.readLatencyHist::491520-524287            6      0.00%    100.00% # Read request-response latency
 system.monitor.readLatencyHist::524288-557055            0      0.00%    100.00% # Read request-response latency
 system.monitor.readLatencyHist::557056-589823            0      0.00%    100.00% # Read request-response latency
 system.monitor.readLatencyHist::589824-622591            0      0.00%    100.00% # Read request-response latency
 system.monitor.readLatencyHist::622592-655359            0      0.00%    100.00% # Read request-response latency
-system.monitor.readLatencyHist::total         1668719                       # Read request-response latency
-system.monitor.writeLatencyHist::samples      1664620                       # Write request-response latency
-system.monitor.writeLatencyHist::mean    10570.968616                       # Write request-response latency
-system.monitor.writeLatencyHist::gmean   10511.906115                       # Write request-response latency
-system.monitor.writeLatencyHist::stdev    1198.829619                       # Write request-response latency
+system.monitor.readLatencyHist::total         1666397                       # Read request-response latency
+system.monitor.writeLatencyHist::samples      1666879                       # Write request-response latency
+system.monitor.writeLatencyHist::mean    10569.121768                       # Write request-response latency
+system.monitor.writeLatencyHist::gmean   10510.211461                       # Write request-response latency
+system.monitor.writeLatencyHist::stdev    1197.318213                       # Write request-response latency
 system.monitor.writeLatencyHist::0-1023             0      0.00%      0.00% # Write request-response latency
 system.monitor.writeLatencyHist::1024-2047            0      0.00%      0.00% # Write request-response latency
 system.monitor.writeLatencyHist::2048-3071            0      0.00%      0.00% # Write request-response latency
@@ -404,91 +404,91 @@ system.monitor.writeLatencyHist::5120-6143            0      0.00%      0.00% #
 system.monitor.writeLatencyHist::6144-7167            0      0.00%      0.00% # Write request-response latency
 system.monitor.writeLatencyHist::7168-8191            0      0.00%      0.00% # Write request-response latency
 system.monitor.writeLatencyHist::8192-9215            0      0.00%      0.00% # Write request-response latency
-system.monitor.writeLatencyHist::9216-10239      1266039     76.06%     76.06% # Write request-response latency
-system.monitor.writeLatencyHist::10240-11263        92649      5.57%     81.62% # Write request-response latency
-system.monitor.writeLatencyHist::11264-12287       113174      6.80%     88.42% # Write request-response latency
-system.monitor.writeLatencyHist::12288-13311        92637      5.57%     93.99% # Write request-response latency
-system.monitor.writeLatencyHist::13312-14335        63204      3.80%     97.78% # Write request-response latency
-system.monitor.writeLatencyHist::14336-15359        32757      1.97%     99.75% # Write request-response latency
-system.monitor.writeLatencyHist::15360-16383         4158      0.25%    100.00% # Write request-response latency
-system.monitor.writeLatencyHist::16384-17407            2      0.00%    100.00% # Write request-response latency
+system.monitor.writeLatencyHist::9216-10239      1268910     76.12%     76.12% # Write request-response latency
+system.monitor.writeLatencyHist::10240-11263        92420      5.54%     81.67% # Write request-response latency
+system.monitor.writeLatencyHist::11264-12287       113112      6.79%     88.46% # Write request-response latency
+system.monitor.writeLatencyHist::12288-13311        92715      5.56%     94.02% # Write request-response latency
+system.monitor.writeLatencyHist::13312-14335        62904      3.77%     97.79% # Write request-response latency
+system.monitor.writeLatencyHist::14336-15359        32645      1.96%     99.75% # Write request-response latency
+system.monitor.writeLatencyHist::15360-16383         4173      0.25%    100.00% # Write request-response latency
+system.monitor.writeLatencyHist::16384-17407            0      0.00%    100.00% # Write request-response latency
 system.monitor.writeLatencyHist::17408-18431            0      0.00%    100.00% # Write request-response latency
 system.monitor.writeLatencyHist::18432-19455            0      0.00%    100.00% # Write request-response latency
 system.monitor.writeLatencyHist::19456-20479            0      0.00%    100.00% # Write request-response latency
-system.monitor.writeLatencyHist::total        1664620                       # Write request-response latency
-system.monitor.ittReadRead::samples           1668719                       # Read-to-read inter transaction time
-system.monitor.ittReadRead::mean         59926.183034                       # Read-to-read inter transaction time
-system.monitor.ittReadRead::stdev        42757.593151                       # Read-to-read inter transaction time
+system.monitor.writeLatencyHist::total        1666879                       # Write request-response latency
+system.monitor.ittReadRead::samples           1666396                       # Read-to-read inter transaction time
+system.monitor.ittReadRead::mean         60009.683149                       # Read-to-read inter transaction time
+system.monitor.ittReadRead::stdev        42949.620471                       # Read-to-read inter transaction time
 system.monitor.ittReadRead::underflows              0      0.00%      0.00% # Read-to-read inter transaction time
 system.monitor.ittReadRead::1-5000                  0      0.00%      0.00% # Read-to-read inter transaction time
 system.monitor.ittReadRead::5001-10000              0      0.00%      0.00% # Read-to-read inter transaction time
 system.monitor.ittReadRead::10001-15000             0      0.00%      0.00% # Read-to-read inter transaction time
 system.monitor.ittReadRead::15001-20000             0      0.00%      0.00% # Read-to-read inter transaction time
 system.monitor.ittReadRead::20001-25000             0      0.00%      0.00% # Read-to-read inter transaction time
-system.monitor.ittReadRead::25001-30000        438300     26.27%     26.27% # Read-to-read inter transaction time
-system.monitor.ittReadRead::30001-35000        404751     24.26%     50.52% # Read-to-read inter transaction time
-system.monitor.ittReadRead::35001-40000             3      0.00%     50.52% # Read-to-read inter transaction time
-system.monitor.ittReadRead::40001-45000             3      0.00%     50.52% # Read-to-read inter transaction time
-system.monitor.ittReadRead::45001-50000             0      0.00%     50.52% # Read-to-read inter transaction time
-system.monitor.ittReadRead::50001-55000             3      0.00%     50.52% # Read-to-read inter transaction time
-system.monitor.ittReadRead::55001-60000        204975     12.28%     62.80% # Read-to-read inter transaction time
-system.monitor.ittReadRead::60001-65000        204546     12.26%     75.06% # Read-to-read inter transaction time
-system.monitor.ittReadRead::65001-70000             3      0.00%     75.06% # Read-to-read inter transaction time
-system.monitor.ittReadRead::70001-75000             3      0.00%     75.06% # Read-to-read inter transaction time
-system.monitor.ittReadRead::75001-80000             2      0.00%     75.06% # Read-to-read inter transaction time
-system.monitor.ittReadRead::80001-85000           527      0.03%     75.09% # Read-to-read inter transaction time
-system.monitor.ittReadRead::85001-90000        102490      6.14%     81.24% # Read-to-read inter transaction time
-system.monitor.ittReadRead::90001-95000        102495      6.14%     87.38% # Read-to-read inter transaction time
-system.monitor.ittReadRead::95001-100000          551      0.03%     87.41% # Read-to-read inter transaction time
-system.monitor.ittReadRead::overflows          210067     12.59%    100.00% # Read-to-read inter transaction time
+system.monitor.ittReadRead::25001-30000        438119     26.29%     26.29% # Read-to-read inter transaction time
+system.monitor.ittReadRead::30001-35000        404012     24.24%     50.54% # Read-to-read inter transaction time
+system.monitor.ittReadRead::35001-40000             1      0.00%     50.54% # Read-to-read inter transaction time
+system.monitor.ittReadRead::40001-45000             3      0.00%     50.54% # Read-to-read inter transaction time
+system.monitor.ittReadRead::45001-50000             3      0.00%     50.54% # Read-to-read inter transaction time
+system.monitor.ittReadRead::50001-55000             4      0.00%     50.54% # Read-to-read inter transaction time
+system.monitor.ittReadRead::55001-60000        203859     12.23%     62.77% # Read-to-read inter transaction time
+system.monitor.ittReadRead::60001-65000        203873     12.23%     75.00% # Read-to-read inter transaction time
+system.monitor.ittReadRead::65001-70000             6      0.00%     75.00% # Read-to-read inter transaction time
+system.monitor.ittReadRead::70001-75000             2      0.00%     75.01% # Read-to-read inter transaction time
+system.monitor.ittReadRead::75001-80000             4      0.00%     75.01% # Read-to-read inter transaction time
+system.monitor.ittReadRead::80001-85000           571      0.03%     75.04% # Read-to-read inter transaction time
+system.monitor.ittReadRead::85001-90000        102408      6.15%     81.19% # Read-to-read inter transaction time
+system.monitor.ittReadRead::90001-95000        102628      6.16%     87.34% # Read-to-read inter transaction time
+system.monitor.ittReadRead::95001-100000          570      0.03%     87.38% # Read-to-read inter transaction time
+system.monitor.ittReadRead::overflows          210333     12.62%    100.00% # Read-to-read inter transaction time
 system.monitor.ittReadRead::min_value           28000                       # Read-to-read inter transaction time
-system.monitor.ittReadRead::max_value         1041420                       # Read-to-read inter transaction time
-system.monitor.ittReadRead::total             1668719                       # Read-to-read inter transaction time
-system.monitor.ittWriteWrite::samples         1664619                       # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::mean       59472.389997                       # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::stdev      41840.398153                       # Write-to-write inter transaction time
+system.monitor.ittReadRead::max_value         1130700                       # Read-to-read inter transaction time
+system.monitor.ittReadRead::total             1666396                       # Read-to-read inter transaction time
+system.monitor.ittWriteWrite::samples         1666878                       # Write-to-write inter transaction time
+system.monitor.ittWriteWrite::mean       59391.842015                       # Write-to-write inter transaction time
+system.monitor.ittWriteWrite::stdev      41837.032784                       # Write-to-write inter transaction time
 system.monitor.ittWriteWrite::underflows            0      0.00%      0.00% # Write-to-write inter transaction time
 system.monitor.ittWriteWrite::1-5000                0      0.00%      0.00% # Write-to-write inter transaction time
 system.monitor.ittWriteWrite::5001-10000            0      0.00%      0.00% # Write-to-write inter transaction time
 system.monitor.ittWriteWrite::10001-15000            0      0.00%      0.00% # Write-to-write inter transaction time
 system.monitor.ittWriteWrite::15001-20000            0      0.00%      0.00% # Write-to-write inter transaction time
 system.monitor.ittWriteWrite::20001-25000            0      0.00%      0.00% # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::25001-30000       419825     25.22%     25.22% # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::30001-35000       419112     25.18%     50.40% # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::35001-40000            4      0.00%     50.40% # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::40001-45000            6      0.00%     50.40% # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::45001-50000            6      0.00%     50.40% # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::50001-55000            6      0.00%     50.40% # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::55001-60000       208578     12.53%     62.93% # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::60001-65000       207985     12.49%     75.42% # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::65001-70000            3      0.00%     75.42% # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::70001-75000            3      0.00%     75.42% # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::75001-80000            3      0.00%     75.42% # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::80001-85000          552      0.03%     75.46% # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::85001-90000       102802      6.18%     81.63% # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::90001-95000       102817      6.18%     87.81% # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::95001-100000          552      0.03%     87.84% # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::overflows        202365     12.16%    100.00% # Write-to-write inter transaction time
+system.monitor.ittWriteWrite::25001-30000       422194     25.33%     25.33% # Write-to-write inter transaction time
+system.monitor.ittWriteWrite::30001-35000       420422     25.22%     50.55% # Write-to-write inter transaction time
+system.monitor.ittWriteWrite::35001-40000            7      0.00%     50.55% # Write-to-write inter transaction time
+system.monitor.ittWriteWrite::40001-45000            3      0.00%     50.55% # Write-to-write inter transaction time
+system.monitor.ittWriteWrite::45001-50000            3      0.00%     50.55% # Write-to-write inter transaction time
+system.monitor.ittWriteWrite::50001-55000            1      0.00%     50.55% # Write-to-write inter transaction time
+system.monitor.ittWriteWrite::55001-60000       208021     12.48%     63.03% # Write-to-write inter transaction time
+system.monitor.ittWriteWrite::60001-65000       207862     12.47%     75.50% # Write-to-write inter transaction time
+system.monitor.ittWriteWrite::65001-70000            4      0.00%     75.50% # Write-to-write inter transaction time
+system.monitor.ittWriteWrite::70001-75000            2      0.00%     75.50% # Write-to-write inter transaction time
+system.monitor.ittWriteWrite::75001-80000            2      0.00%     75.50% # Write-to-write inter transaction time
+system.monitor.ittWriteWrite::80001-85000          506      0.03%     75.53% # Write-to-write inter transaction time
+system.monitor.ittWriteWrite::85001-90000       102058      6.12%     81.65% # Write-to-write inter transaction time
+system.monitor.ittWriteWrite::90001-95000       103058      6.18%     87.84% # Write-to-write inter transaction time
+system.monitor.ittWriteWrite::95001-100000          512      0.03%     87.87% # Write-to-write inter transaction time
+system.monitor.ittWriteWrite::overflows        202223     12.13%    100.00% # Write-to-write inter transaction time
 system.monitor.ittWriteWrite::min_value         28000                       # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::max_value        598079                       # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::total           1664619                       # Write-to-write inter transaction time
-system.monitor.ittReqReq::samples             3333339                       # Request-to-request inter transaction time
-system.monitor.ittReqReq::mean           29999.937068                       # Request-to-request inter transaction time
-system.monitor.ittReqReq::stdev           1278.967916                       # Request-to-request inter transaction time
+system.monitor.ittWriteWrite::max_value        600949                       # Write-to-write inter transaction time
+system.monitor.ittWriteWrite::total           1666878                       # Write-to-write inter transaction time
+system.monitor.ittReqReq::samples             3333275                       # Request-to-request inter transaction time
+system.monitor.ittReqReq::mean           30000.511852                       # Request-to-request inter transaction time
+system.monitor.ittReqReq::stdev           1280.006862                       # Request-to-request inter transaction time
 system.monitor.ittReqReq::underflows                0      0.00%      0.00% # Request-to-request inter transaction time
 system.monitor.ittReqReq::1-5000                    0      0.00%      0.00% # Request-to-request inter transaction time
 system.monitor.ittReqReq::5001-10000                0      0.00%      0.00% # Request-to-request inter transaction time
 system.monitor.ittReqReq::10001-15000               0      0.00%      0.00% # Request-to-request inter transaction time
 system.monitor.ittReqReq::15001-20000               0      0.00%      0.00% # Request-to-request inter transaction time
 system.monitor.ittReqReq::20001-25000               0      0.00%      0.00% # Request-to-request inter transaction time
-system.monitor.ittReqReq::25001-30000         1684541     50.54%     50.54% # Request-to-request inter transaction time
-system.monitor.ittReqReq::30001-35000         1648718     49.46%    100.00% # Request-to-request inter transaction time
+system.monitor.ittReqReq::25001-30000         1684866     50.55%     50.55% # Request-to-request inter transaction time
+system.monitor.ittReqReq::30001-35000         1648324     49.45%    100.00% # Request-to-request inter transaction time
 system.monitor.ittReqReq::35001-40000              18      0.00%    100.00% # Request-to-request inter transaction time
-system.monitor.ittReqReq::40001-45000              15      0.00%    100.00% # Request-to-request inter transaction time
-system.monitor.ittReqReq::45001-50000              11      0.00%    100.00% # Request-to-request inter transaction time
-system.monitor.ittReqReq::50001-55000              20      0.00%    100.00% # Request-to-request inter transaction time
-system.monitor.ittReqReq::55001-60000              13      0.00%    100.00% # Request-to-request inter transaction time
-system.monitor.ittReqReq::60001-65000               2      0.00%    100.00% # Request-to-request inter transaction time
+system.monitor.ittReqReq::40001-45000              13      0.00%    100.00% # Request-to-request inter transaction time
+system.monitor.ittReqReq::45001-50000              13      0.00%    100.00% # Request-to-request inter transaction time
+system.monitor.ittReqReq::50001-55000              16      0.00%    100.00% # Request-to-request inter transaction time
+system.monitor.ittReqReq::55001-60000              16      0.00%    100.00% # Request-to-request inter transaction time
+system.monitor.ittReqReq::60001-65000               8      0.00%    100.00% # Request-to-request inter transaction time
 system.monitor.ittReqReq::65001-70000               0      0.00%    100.00% # Request-to-request inter transaction time
 system.monitor.ittReqReq::70001-75000               0      0.00%    100.00% # Request-to-request inter transaction time
 system.monitor.ittReqReq::75001-80000               0      0.00%    100.00% # Request-to-request inter transaction time
@@ -498,21 +498,21 @@ system.monitor.ittReqReq::90001-95000               0      0.00%    100.00% # Re
 system.monitor.ittReqReq::95001-100000              0      0.00%    100.00% # Request-to-request inter transaction time
 system.monitor.ittReqReq::overflows                 1      0.00%    100.00% # Request-to-request inter transaction time
 system.monitor.ittReqReq::min_value             28000                       # Request-to-request inter transaction time
-system.monitor.ittReqReq::max_value           1041420                       # Request-to-request inter transaction time
-system.monitor.ittReqReq::total               3333339                       # Request-to-request inter transaction time
+system.monitor.ittReqReq::max_value           1041309                       # Request-to-request inter transaction time
+system.monitor.ittReqReq::total               3333275                       # Request-to-request inter transaction time
 system.monitor.outstandingReadsHist::samples          100                       # Outstanding read transactions
-system.monitor.outstandingReadsHist::mean     1.030000                       # Outstanding read transactions
+system.monitor.outstandingReadsHist::mean     1.160000                       # Outstanding read transactions
 system.monitor.outstandingReadsHist::gmean            0                       # Outstanding read transactions
-system.monitor.outstandingReadsHist::stdev     0.881402                       # Outstanding read transactions
+system.monitor.outstandingReadsHist::stdev     1.212061                       # Outstanding read transactions
 system.monitor.outstandingReadsHist::0             28     28.00%     28.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::1             47     47.00%     75.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::2             21     21.00%     96.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::3              3      3.00%     99.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::4              0      0.00%     99.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::5              1      1.00%    100.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::6              0      0.00%    100.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::7              0      0.00%    100.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::8              0      0.00%    100.00% # Outstanding read transactions
+system.monitor.outstandingReadsHist::1             45     45.00%     73.00% # Outstanding read transactions
+system.monitor.outstandingReadsHist::2             19     19.00%     92.00% # Outstanding read transactions
+system.monitor.outstandingReadsHist::3              5      5.00%     97.00% # Outstanding read transactions
+system.monitor.outstandingReadsHist::4              0      0.00%     97.00% # Outstanding read transactions
+system.monitor.outstandingReadsHist::5              2      2.00%     99.00% # Outstanding read transactions
+system.monitor.outstandingReadsHist::6              0      0.00%     99.00% # Outstanding read transactions
+system.monitor.outstandingReadsHist::7              0      0.00%     99.00% # Outstanding read transactions
+system.monitor.outstandingReadsHist::8              1      1.00%    100.00% # Outstanding read transactions
 system.monitor.outstandingReadsHist::9              0      0.00%    100.00% # Outstanding read transactions
 system.monitor.outstandingReadsHist::10             0      0.00%    100.00% # Outstanding read transactions
 system.monitor.outstandingReadsHist::11             0      0.00%    100.00% # Outstanding read transactions
@@ -526,11 +526,11 @@ system.monitor.outstandingReadsHist::18             0      0.00%    100.00% # Ou
 system.monitor.outstandingReadsHist::19             0      0.00%    100.00% # Outstanding read transactions
 system.monitor.outstandingReadsHist::total          100                       # Outstanding read transactions
 system.monitor.outstandingWritesHist::samples          100                       # Outstanding write transactions
-system.monitor.outstandingWritesHist::mean     0.150000                       # Outstanding write transactions
+system.monitor.outstandingWritesHist::mean     0.190000                       # Outstanding write transactions
 system.monitor.outstandingWritesHist::gmean            0                       # Outstanding write transactions
-system.monitor.outstandingWritesHist::stdev     0.358870                       # Outstanding write transactions
-system.monitor.outstandingWritesHist::0            85     85.00%     85.00% # Outstanding write transactions
-system.monitor.outstandingWritesHist::1            15     15.00%    100.00% # Outstanding write transactions
+system.monitor.outstandingWritesHist::stdev     0.394277                       # Outstanding write transactions
+system.monitor.outstandingWritesHist::0            81     81.00%     81.00% # Outstanding write transactions
+system.monitor.outstandingWritesHist::1            19     19.00%    100.00% # Outstanding write transactions
 system.monitor.outstandingWritesHist::2             0      0.00%    100.00% # Outstanding write transactions
 system.monitor.outstandingWritesHist::3             0      0.00%    100.00% # Outstanding write transactions
 system.monitor.outstandingWritesHist::4             0      0.00%    100.00% # Outstanding write transactions
@@ -551,9 +551,9 @@ system.monitor.outstandingWritesHist::18            0      0.00%    100.00% # Ou
 system.monitor.outstandingWritesHist::19            0      0.00%    100.00% # Outstanding write transactions
 system.monitor.outstandingWritesHist::total          100                       # Outstanding write transactions
 system.monitor.readTransHist::samples             100                       # Histogram of read transactions per sample period
-system.monitor.readTransHist::mean       16687.200000                       # Histogram of read transactions per sample period
-system.monitor.readTransHist::gmean      16635.188141                       # Histogram of read transactions per sample period
-system.monitor.readTransHist::stdev       1683.853859                       # Histogram of read transactions per sample period
+system.monitor.readTransHist::mean       16663.970000                       # Histogram of read transactions per sample period
+system.monitor.readTransHist::gmean      16611.784927                       # Histogram of read transactions per sample period
+system.monitor.readTransHist::stdev       1686.281945                       # Histogram of read transactions per sample period
 system.monitor.readTransHist::0-2047                0      0.00%      0.00% # Histogram of read transactions per sample period
 system.monitor.readTransHist::2048-4095             0      0.00%      0.00% # Histogram of read transactions per sample period
 system.monitor.readTransHist::4096-6143             0      0.00%      0.00% # Histogram of read transactions per sample period
@@ -561,8 +561,8 @@ system.monitor.readTransHist::6144-8191             0      0.00%      0.00% # Hi
 system.monitor.readTransHist::8192-10239            0      0.00%      0.00% # Histogram of read transactions per sample period
 system.monitor.readTransHist::10240-12287            0      0.00%      0.00% # Histogram of read transactions per sample period
 system.monitor.readTransHist::12288-14335            0      0.00%      0.00% # Histogram of read transactions per sample period
-system.monitor.readTransHist::14336-16383            5      5.00%      5.00% # Histogram of read transactions per sample period
-system.monitor.readTransHist::16384-18431           94     94.00%     99.00% # Histogram of read transactions per sample period
+system.monitor.readTransHist::14336-16383           12     12.00%     12.00% # Histogram of read transactions per sample period
+system.monitor.readTransHist::16384-18431           87     87.00%     99.00% # Histogram of read transactions per sample period
 system.monitor.readTransHist::18432-20479            0      0.00%     99.00% # Histogram of read transactions per sample period
 system.monitor.readTransHist::20480-22527            0      0.00%     99.00% # Histogram of read transactions per sample period
 system.monitor.readTransHist::22528-24575            0      0.00%     99.00% # Histogram of read transactions per sample period
@@ -576,9 +576,9 @@ system.monitor.readTransHist::36864-38911            0      0.00%    100.00% # H
 system.monitor.readTransHist::38912-40959            0      0.00%    100.00% # Histogram of read transactions per sample period
 system.monitor.readTransHist::total               100                       # Histogram of read transactions per sample period
 system.monitor.writeTransHist::samples            100                       # Histogram of read transactions per sample period
-system.monitor.writeTransHist::mean      16646.200000                       # Histogram of read transactions per sample period
+system.monitor.writeTransHist::mean      16668.790000                       # Histogram of read transactions per sample period
 system.monitor.writeTransHist::gmean                0                       # Histogram of read transactions per sample period
-system.monitor.writeTransHist::stdev      1683.921595                       # Histogram of read transactions per sample period
+system.monitor.writeTransHist::stdev      1686.323754                       # Histogram of read transactions per sample period
 system.monitor.writeTransHist::0-1023               1      1.00%      1.00% # Histogram of read transactions per sample period
 system.monitor.writeTransHist::1024-2047            0      0.00%      1.00% # Histogram of read transactions per sample period
 system.monitor.writeTransHist::2048-3071            0      0.00%      1.00% # Histogram of read transactions per sample period
@@ -600,7 +600,7 @@ system.monitor.writeTransHist::17408-18431            0      0.00%    100.00% #
 system.monitor.writeTransHist::18432-19455            0      0.00%    100.00% # Histogram of read transactions per sample period
 system.monitor.writeTransHist::19456-20479            0      0.00%    100.00% # Histogram of read transactions per sample period
 system.monitor.writeTransHist::total              100                       # Histogram of read transactions per sample period
-system.cpu.numPackets                         3333340                       # Number of packets generated
+system.cpu.numPackets                         3333276                       # Number of packets generated
 system.cpu.numRetries                               0                       # Number of retries
 system.cpu.retryTicks                               0                       # Time spent waiting due to back-pressure (ticks)